2 * Copyright (c) 2006, 2007 QLogic Corporation. All rights reserved.
3 * Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved.
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 * This file contains all of the code that is specific to the InfiniPath
39 #include <linux/vmalloc.h>
40 #include <linux/pci.h>
41 #include <linux/delay.h>
42 #include <linux/htirq.h>
44 #include "ipath_kernel.h"
45 #include "ipath_registers.h"
47 static void ipath_setup_ht_setextled(struct ipath_devdata *, u64, u64);
51 * This lists the InfiniPath registers, in the actual chip layout.
52 * This structure should never be directly accessed.
54 * The names are in InterCap form because they're taken straight from
55 * the chip specification. Since they're only used in this file, they
56 * don't pollute the rest of the source.
59 struct _infinipath_do_not_use_kernel_regs {
60 unsigned long long Revision;
61 unsigned long long Control;
62 unsigned long long PageAlign;
63 unsigned long long PortCnt;
64 unsigned long long DebugPortSelect;
65 unsigned long long DebugPort;
66 unsigned long long SendRegBase;
67 unsigned long long UserRegBase;
68 unsigned long long CounterRegBase;
69 unsigned long long Scratch;
70 unsigned long long ReservedMisc1;
71 unsigned long long InterruptConfig;
72 unsigned long long IntBlocked;
73 unsigned long long IntMask;
74 unsigned long long IntStatus;
75 unsigned long long IntClear;
76 unsigned long long ErrorMask;
77 unsigned long long ErrorStatus;
78 unsigned long long ErrorClear;
79 unsigned long long HwErrMask;
80 unsigned long long HwErrStatus;
81 unsigned long long HwErrClear;
82 unsigned long long HwDiagCtrl;
83 unsigned long long MDIO;
84 unsigned long long IBCStatus;
85 unsigned long long IBCCtrl;
86 unsigned long long ExtStatus;
87 unsigned long long ExtCtrl;
88 unsigned long long GPIOOut;
89 unsigned long long GPIOMask;
90 unsigned long long GPIOStatus;
91 unsigned long long GPIOClear;
92 unsigned long long RcvCtrl;
93 unsigned long long RcvBTHQP;
94 unsigned long long RcvHdrSize;
95 unsigned long long RcvHdrCnt;
96 unsigned long long RcvHdrEntSize;
97 unsigned long long RcvTIDBase;
98 unsigned long long RcvTIDCnt;
99 unsigned long long RcvEgrBase;
100 unsigned long long RcvEgrCnt;
101 unsigned long long RcvBufBase;
102 unsigned long long RcvBufSize;
103 unsigned long long RxIntMemBase;
104 unsigned long long RxIntMemSize;
105 unsigned long long RcvPartitionKey;
106 unsigned long long ReservedRcv[10];
107 unsigned long long SendCtrl;
108 unsigned long long SendPIOBufBase;
109 unsigned long long SendPIOSize;
110 unsigned long long SendPIOBufCnt;
111 unsigned long long SendPIOAvailAddr;
112 unsigned long long TxIntMemBase;
113 unsigned long long TxIntMemSize;
114 unsigned long long ReservedSend[9];
115 unsigned long long SendBufferError;
116 unsigned long long SendBufferErrorCONT1;
117 unsigned long long SendBufferErrorCONT2;
118 unsigned long long SendBufferErrorCONT3;
119 unsigned long long ReservedSBE[4];
120 unsigned long long RcvHdrAddr0;
121 unsigned long long RcvHdrAddr1;
122 unsigned long long RcvHdrAddr2;
123 unsigned long long RcvHdrAddr3;
124 unsigned long long RcvHdrAddr4;
125 unsigned long long RcvHdrAddr5;
126 unsigned long long RcvHdrAddr6;
127 unsigned long long RcvHdrAddr7;
128 unsigned long long RcvHdrAddr8;
129 unsigned long long ReservedRHA[7];
130 unsigned long long RcvHdrTailAddr0;
131 unsigned long long RcvHdrTailAddr1;
132 unsigned long long RcvHdrTailAddr2;
133 unsigned long long RcvHdrTailAddr3;
134 unsigned long long RcvHdrTailAddr4;
135 unsigned long long RcvHdrTailAddr5;
136 unsigned long long RcvHdrTailAddr6;
137 unsigned long long RcvHdrTailAddr7;
138 unsigned long long RcvHdrTailAddr8;
139 unsigned long long ReservedRHTA[7];
140 unsigned long long Sync; /* Software only */
141 unsigned long long Dump; /* Software only */
142 unsigned long long SimVer; /* Software only */
143 unsigned long long ReservedSW[5];
144 unsigned long long SerdesConfig0;
145 unsigned long long SerdesConfig1;
146 unsigned long long SerdesStatus;
147 unsigned long long XGXSConfig;
148 unsigned long long ReservedSW2[4];
151 struct _infinipath_do_not_use_counters {
153 __u64 LBFlowStallCnt;
155 __u64 TxUnsupVLErrCnt;
160 __u64 TxMaxMinLenErrCnt;
162 __u64 TxFlowStallCnt;
163 __u64 TxDroppedPktCnt;
164 __u64 RxDroppedPktCnt;
169 __u64 RxMaxMinLenErrCnt;
172 __u64 RxFlowCtrlErrCnt;
173 __u64 RxBadFormatCnt;
174 __u64 RxLinkProblemCnt;
178 __u64 RxTIDFullErrCnt;
179 __u64 RxTIDValidErrCnt;
180 __u64 RxPKeyMismatchCnt;
181 __u64 RxP0HdrEgrOvflCnt;
182 __u64 RxP1HdrEgrOvflCnt;
183 __u64 RxP2HdrEgrOvflCnt;
184 __u64 RxP3HdrEgrOvflCnt;
185 __u64 RxP4HdrEgrOvflCnt;
186 __u64 RxP5HdrEgrOvflCnt;
187 __u64 RxP6HdrEgrOvflCnt;
188 __u64 RxP7HdrEgrOvflCnt;
189 __u64 RxP8HdrEgrOvflCnt;
192 __u64 IBStatusChangeCnt;
193 __u64 IBLinkErrRecoveryCnt;
194 __u64 IBLinkDownedCnt;
195 __u64 IBSymbolErrCnt;
198 #define IPATH_KREG_OFFSET(field) (offsetof( \
199 struct _infinipath_do_not_use_kernel_regs, field) / sizeof(u64))
200 #define IPATH_CREG_OFFSET(field) (offsetof( \
201 struct _infinipath_do_not_use_counters, field) / sizeof(u64))
203 static const struct ipath_kregs ipath_ht_kregs = {
204 .kr_control = IPATH_KREG_OFFSET(Control),
205 .kr_counterregbase = IPATH_KREG_OFFSET(CounterRegBase),
206 .kr_debugport = IPATH_KREG_OFFSET(DebugPort),
207 .kr_debugportselect = IPATH_KREG_OFFSET(DebugPortSelect),
208 .kr_errorclear = IPATH_KREG_OFFSET(ErrorClear),
209 .kr_errormask = IPATH_KREG_OFFSET(ErrorMask),
210 .kr_errorstatus = IPATH_KREG_OFFSET(ErrorStatus),
211 .kr_extctrl = IPATH_KREG_OFFSET(ExtCtrl),
212 .kr_extstatus = IPATH_KREG_OFFSET(ExtStatus),
213 .kr_gpio_clear = IPATH_KREG_OFFSET(GPIOClear),
214 .kr_gpio_mask = IPATH_KREG_OFFSET(GPIOMask),
215 .kr_gpio_out = IPATH_KREG_OFFSET(GPIOOut),
216 .kr_gpio_status = IPATH_KREG_OFFSET(GPIOStatus),
217 .kr_hwdiagctrl = IPATH_KREG_OFFSET(HwDiagCtrl),
218 .kr_hwerrclear = IPATH_KREG_OFFSET(HwErrClear),
219 .kr_hwerrmask = IPATH_KREG_OFFSET(HwErrMask),
220 .kr_hwerrstatus = IPATH_KREG_OFFSET(HwErrStatus),
221 .kr_ibcctrl = IPATH_KREG_OFFSET(IBCCtrl),
222 .kr_ibcstatus = IPATH_KREG_OFFSET(IBCStatus),
223 .kr_intblocked = IPATH_KREG_OFFSET(IntBlocked),
224 .kr_intclear = IPATH_KREG_OFFSET(IntClear),
225 .kr_interruptconfig = IPATH_KREG_OFFSET(InterruptConfig),
226 .kr_intmask = IPATH_KREG_OFFSET(IntMask),
227 .kr_intstatus = IPATH_KREG_OFFSET(IntStatus),
228 .kr_mdio = IPATH_KREG_OFFSET(MDIO),
229 .kr_pagealign = IPATH_KREG_OFFSET(PageAlign),
230 .kr_partitionkey = IPATH_KREG_OFFSET(RcvPartitionKey),
231 .kr_portcnt = IPATH_KREG_OFFSET(PortCnt),
232 .kr_rcvbthqp = IPATH_KREG_OFFSET(RcvBTHQP),
233 .kr_rcvbufbase = IPATH_KREG_OFFSET(RcvBufBase),
234 .kr_rcvbufsize = IPATH_KREG_OFFSET(RcvBufSize),
235 .kr_rcvctrl = IPATH_KREG_OFFSET(RcvCtrl),
236 .kr_rcvegrbase = IPATH_KREG_OFFSET(RcvEgrBase),
237 .kr_rcvegrcnt = IPATH_KREG_OFFSET(RcvEgrCnt),
238 .kr_rcvhdrcnt = IPATH_KREG_OFFSET(RcvHdrCnt),
239 .kr_rcvhdrentsize = IPATH_KREG_OFFSET(RcvHdrEntSize),
240 .kr_rcvhdrsize = IPATH_KREG_OFFSET(RcvHdrSize),
241 .kr_rcvintmembase = IPATH_KREG_OFFSET(RxIntMemBase),
242 .kr_rcvintmemsize = IPATH_KREG_OFFSET(RxIntMemSize),
243 .kr_rcvtidbase = IPATH_KREG_OFFSET(RcvTIDBase),
244 .kr_rcvtidcnt = IPATH_KREG_OFFSET(RcvTIDCnt),
245 .kr_revision = IPATH_KREG_OFFSET(Revision),
246 .kr_scratch = IPATH_KREG_OFFSET(Scratch),
247 .kr_sendbuffererror = IPATH_KREG_OFFSET(SendBufferError),
248 .kr_sendctrl = IPATH_KREG_OFFSET(SendCtrl),
249 .kr_sendpioavailaddr = IPATH_KREG_OFFSET(SendPIOAvailAddr),
250 .kr_sendpiobufbase = IPATH_KREG_OFFSET(SendPIOBufBase),
251 .kr_sendpiobufcnt = IPATH_KREG_OFFSET(SendPIOBufCnt),
252 .kr_sendpiosize = IPATH_KREG_OFFSET(SendPIOSize),
253 .kr_sendregbase = IPATH_KREG_OFFSET(SendRegBase),
254 .kr_txintmembase = IPATH_KREG_OFFSET(TxIntMemBase),
255 .kr_txintmemsize = IPATH_KREG_OFFSET(TxIntMemSize),
256 .kr_userregbase = IPATH_KREG_OFFSET(UserRegBase),
257 .kr_serdesconfig0 = IPATH_KREG_OFFSET(SerdesConfig0),
258 .kr_serdesconfig1 = IPATH_KREG_OFFSET(SerdesConfig1),
259 .kr_serdesstatus = IPATH_KREG_OFFSET(SerdesStatus),
260 .kr_xgxsconfig = IPATH_KREG_OFFSET(XGXSConfig),
262 * These should not be used directly via ipath_write_kreg64(),
263 * use them with ipath_write_kreg64_port(),
265 .kr_rcvhdraddr = IPATH_KREG_OFFSET(RcvHdrAddr0),
266 .kr_rcvhdrtailaddr = IPATH_KREG_OFFSET(RcvHdrTailAddr0)
269 static const struct ipath_cregs ipath_ht_cregs = {
270 .cr_badformatcnt = IPATH_CREG_OFFSET(RxBadFormatCnt),
271 .cr_erricrccnt = IPATH_CREG_OFFSET(RxICRCErrCnt),
272 .cr_errlinkcnt = IPATH_CREG_OFFSET(RxLinkProblemCnt),
273 .cr_errlpcrccnt = IPATH_CREG_OFFSET(RxLPCRCErrCnt),
274 .cr_errpkey = IPATH_CREG_OFFSET(RxPKeyMismatchCnt),
275 .cr_errrcvflowctrlcnt = IPATH_CREG_OFFSET(RxFlowCtrlErrCnt),
276 .cr_err_rlencnt = IPATH_CREG_OFFSET(RxLenErrCnt),
277 .cr_errslencnt = IPATH_CREG_OFFSET(TxLenErrCnt),
278 .cr_errtidfull = IPATH_CREG_OFFSET(RxTIDFullErrCnt),
279 .cr_errtidvalid = IPATH_CREG_OFFSET(RxTIDValidErrCnt),
280 .cr_errvcrccnt = IPATH_CREG_OFFSET(RxVCRCErrCnt),
281 .cr_ibstatuschange = IPATH_CREG_OFFSET(IBStatusChangeCnt),
282 /* calc from Reg_CounterRegBase + offset */
283 .cr_intcnt = IPATH_CREG_OFFSET(LBIntCnt),
284 .cr_invalidrlencnt = IPATH_CREG_OFFSET(RxMaxMinLenErrCnt),
285 .cr_invalidslencnt = IPATH_CREG_OFFSET(TxMaxMinLenErrCnt),
286 .cr_lbflowstallcnt = IPATH_CREG_OFFSET(LBFlowStallCnt),
287 .cr_pktrcvcnt = IPATH_CREG_OFFSET(RxDataPktCnt),
288 .cr_pktrcvflowctrlcnt = IPATH_CREG_OFFSET(RxFlowPktCnt),
289 .cr_pktsendcnt = IPATH_CREG_OFFSET(TxDataPktCnt),
290 .cr_pktsendflowcnt = IPATH_CREG_OFFSET(TxFlowPktCnt),
291 .cr_portovflcnt = IPATH_CREG_OFFSET(RxP0HdrEgrOvflCnt),
292 .cr_rcvebpcnt = IPATH_CREG_OFFSET(RxEBPCnt),
293 .cr_rcvovflcnt = IPATH_CREG_OFFSET(RxBufOvflCnt),
294 .cr_senddropped = IPATH_CREG_OFFSET(TxDroppedPktCnt),
295 .cr_sendstallcnt = IPATH_CREG_OFFSET(TxFlowStallCnt),
296 .cr_sendunderruncnt = IPATH_CREG_OFFSET(TxUnderrunCnt),
297 .cr_wordrcvcnt = IPATH_CREG_OFFSET(RxDwordCnt),
298 .cr_wordsendcnt = IPATH_CREG_OFFSET(TxDwordCnt),
299 .cr_unsupvlcnt = IPATH_CREG_OFFSET(TxUnsupVLErrCnt),
300 .cr_rxdroppktcnt = IPATH_CREG_OFFSET(RxDroppedPktCnt),
301 .cr_iblinkerrrecovcnt = IPATH_CREG_OFFSET(IBLinkErrRecoveryCnt),
302 .cr_iblinkdowncnt = IPATH_CREG_OFFSET(IBLinkDownedCnt),
303 .cr_ibsymbolerrcnt = IPATH_CREG_OFFSET(IBSymbolErrCnt)
306 /* kr_intstatus, kr_intclear, kr_intmask bits */
307 #define INFINIPATH_I_RCVURG_MASK ((1U<<9)-1)
308 #define INFINIPATH_I_RCVAVAIL_MASK ((1U<<9)-1)
310 /* kr_hwerrclear, kr_hwerrmask, kr_hwerrstatus, bits */
311 #define INFINIPATH_HWE_HTCMEMPARITYERR_SHIFT 0
312 #define INFINIPATH_HWE_HTCMEMPARITYERR_MASK 0x3FFFFFULL
313 #define INFINIPATH_HWE_HTCLNKABYTE0CRCERR 0x0000000000800000ULL
314 #define INFINIPATH_HWE_HTCLNKABYTE1CRCERR 0x0000000001000000ULL
315 #define INFINIPATH_HWE_HTCLNKBBYTE0CRCERR 0x0000000002000000ULL
316 #define INFINIPATH_HWE_HTCLNKBBYTE1CRCERR 0x0000000004000000ULL
317 #define INFINIPATH_HWE_HTCMISCERR4 0x0000000008000000ULL
318 #define INFINIPATH_HWE_HTCMISCERR5 0x0000000010000000ULL
319 #define INFINIPATH_HWE_HTCMISCERR6 0x0000000020000000ULL
320 #define INFINIPATH_HWE_HTCMISCERR7 0x0000000040000000ULL
321 #define INFINIPATH_HWE_HTCBUSTREQPARITYERR 0x0000000080000000ULL
322 #define INFINIPATH_HWE_HTCBUSTRESPPARITYERR 0x0000000100000000ULL
323 #define INFINIPATH_HWE_HTCBUSIREQPARITYERR 0x0000000200000000ULL
324 #define INFINIPATH_HWE_COREPLL_FBSLIP 0x0080000000000000ULL
325 #define INFINIPATH_HWE_COREPLL_RFSLIP 0x0100000000000000ULL
326 #define INFINIPATH_HWE_HTBPLL_FBSLIP 0x0200000000000000ULL
327 #define INFINIPATH_HWE_HTBPLL_RFSLIP 0x0400000000000000ULL
328 #define INFINIPATH_HWE_HTAPLL_FBSLIP 0x0800000000000000ULL
329 #define INFINIPATH_HWE_HTAPLL_RFSLIP 0x1000000000000000ULL
330 #define INFINIPATH_HWE_SERDESPLLFAILED 0x2000000000000000ULL
332 /* kr_extstatus bits */
333 #define INFINIPATH_EXTS_FREQSEL 0x2
334 #define INFINIPATH_EXTS_SERDESSEL 0x4
335 #define INFINIPATH_EXTS_MEMBIST_ENDTEST 0x0000000000004000
336 #define INFINIPATH_EXTS_MEMBIST_CORRECT 0x0000000000008000
339 /* TID entries (memory), HT-only */
340 #define INFINIPATH_RT_ADDR_MASK 0xFFFFFFFFFFULL /* 40 bits valid */
341 #define INFINIPATH_RT_VALID 0x8000000000000000ULL
342 #define INFINIPATH_RT_ADDR_SHIFT 0
343 #define INFINIPATH_RT_BUFSIZE_MASK 0x3FFFULL
344 #define INFINIPATH_RT_BUFSIZE_SHIFT 48
346 #define INFINIPATH_R_INTRAVAIL_SHIFT 16
347 #define INFINIPATH_R_TAILUPD_SHIFT 31
349 /* kr_xgxsconfig bits */
350 #define INFINIPATH_XGXS_RESET 0x7ULL
353 * masks and bits that are different in different chips, or present only
356 static const ipath_err_t infinipath_hwe_htcmemparityerr_mask =
357 INFINIPATH_HWE_HTCMEMPARITYERR_MASK;
358 static const ipath_err_t infinipath_hwe_htcmemparityerr_shift =
359 INFINIPATH_HWE_HTCMEMPARITYERR_SHIFT;
361 static const ipath_err_t infinipath_hwe_htclnkabyte0crcerr =
362 INFINIPATH_HWE_HTCLNKABYTE0CRCERR;
363 static const ipath_err_t infinipath_hwe_htclnkabyte1crcerr =
364 INFINIPATH_HWE_HTCLNKABYTE1CRCERR;
365 static const ipath_err_t infinipath_hwe_htclnkbbyte0crcerr =
366 INFINIPATH_HWE_HTCLNKBBYTE0CRCERR;
367 static const ipath_err_t infinipath_hwe_htclnkbbyte1crcerr =
368 INFINIPATH_HWE_HTCLNKBBYTE1CRCERR;
370 #define _IPATH_GPIO_SDA_NUM 1
371 #define _IPATH_GPIO_SCL_NUM 0
373 #define IPATH_GPIO_SDA \
374 (1ULL << (_IPATH_GPIO_SDA_NUM+INFINIPATH_EXTC_GPIOOE_SHIFT))
375 #define IPATH_GPIO_SCL \
376 (1ULL << (_IPATH_GPIO_SCL_NUM+INFINIPATH_EXTC_GPIOOE_SHIFT))
378 /* keep the code below somewhat more readonable; not used elsewhere */
379 #define _IPATH_HTLINK0_CRCBITS (infinipath_hwe_htclnkabyte0crcerr | \
380 infinipath_hwe_htclnkabyte1crcerr)
381 #define _IPATH_HTLINK1_CRCBITS (infinipath_hwe_htclnkbbyte0crcerr | \
382 infinipath_hwe_htclnkbbyte1crcerr)
383 #define _IPATH_HTLANE0_CRCBITS (infinipath_hwe_htclnkabyte0crcerr | \
384 infinipath_hwe_htclnkbbyte0crcerr)
385 #define _IPATH_HTLANE1_CRCBITS (infinipath_hwe_htclnkabyte1crcerr | \
386 infinipath_hwe_htclnkbbyte1crcerr)
388 static void hwerr_crcbits(struct ipath_devdata *dd, ipath_err_t hwerrs,
389 char *msg, size_t msgl)
392 ipath_err_t crcbits = hwerrs &
393 (_IPATH_HTLINK0_CRCBITS | _IPATH_HTLINK1_CRCBITS);
394 /* don't check if 8bit HT */
395 if (dd->ipath_flags & IPATH_8BIT_IN_HT0)
396 crcbits &= ~infinipath_hwe_htclnkabyte1crcerr;
397 /* don't check if 8bit HT */
398 if (dd->ipath_flags & IPATH_8BIT_IN_HT1)
399 crcbits &= ~infinipath_hwe_htclnkbbyte1crcerr;
401 * we'll want to ignore link errors on link that is
402 * not in use, if any. For now, complain about both
406 snprintf(bitsmsg, sizeof bitsmsg,
407 "[HT%s lane %s CRC (%llx); powercycle to completely clear]",
408 !(crcbits & _IPATH_HTLINK1_CRCBITS) ?
409 "0 (A)" : (!(crcbits & _IPATH_HTLINK0_CRCBITS)
410 ? "1 (B)" : "0+1 (A+B)"),
411 !(crcbits & _IPATH_HTLANE1_CRCBITS) ? "0"
412 : (!(crcbits & _IPATH_HTLANE0_CRCBITS) ? "1" :
413 "0+1"), (unsigned long long) crcbits);
414 strlcat(msg, bitsmsg, msgl);
417 * print extra info for debugging. slave/primary
418 * config word 4, 8 (link control 0, 1)
421 if (pci_read_config_word(dd->pcidev,
422 dd->ipath_ht_slave_off + 0x4,
424 dev_info(&dd->pcidev->dev, "Couldn't read "
425 "linkctrl0 of slave/primary "
427 else if (!(ctrl0 & 1 << 6))
428 /* not if EOC bit set */
429 ipath_dbg("HT linkctrl0 0x%x%s%s\n", ctrl0,
430 ((ctrl0 >> 8) & 7) ? " CRC" : "",
431 ((ctrl0 >> 4) & 1) ? "linkfail" :
433 if (pci_read_config_word(dd->pcidev,
434 dd->ipath_ht_slave_off + 0x8,
436 dev_info(&dd->pcidev->dev, "Couldn't read "
437 "linkctrl1 of slave/primary "
439 else if (!(ctrl1 & 1 << 6))
440 /* not if EOC bit set */
441 ipath_dbg("HT linkctrl1 0x%x%s%s\n", ctrl1,
442 ((ctrl1 >> 8) & 7) ? " CRC" : "",
443 ((ctrl1 >> 4) & 1) ? "linkfail" :
446 /* disable until driver reloaded */
447 dd->ipath_hwerrmask &= ~crcbits;
448 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask,
449 dd->ipath_hwerrmask);
450 ipath_dbg("HT crc errs: %s\n", msg);
452 ipath_dbg("ignoring HT crc errors 0x%llx, "
453 "not in use\n", (unsigned long long)
454 (hwerrs & (_IPATH_HTLINK0_CRCBITS |
455 _IPATH_HTLINK1_CRCBITS)));
458 /* 6110 specific hardware errors... */
459 static const struct ipath_hwerror_msgs ipath_6110_hwerror_msgs[] = {
460 INFINIPATH_HWE_MSG(HTCBUSIREQPARITYERR, "HTC Ireq Parity"),
461 INFINIPATH_HWE_MSG(HTCBUSTREQPARITYERR, "HTC Treq Parity"),
462 INFINIPATH_HWE_MSG(HTCBUSTRESPPARITYERR, "HTC Tresp Parity"),
463 INFINIPATH_HWE_MSG(HTCMISCERR5, "HT core Misc5"),
464 INFINIPATH_HWE_MSG(HTCMISCERR6, "HT core Misc6"),
465 INFINIPATH_HWE_MSG(HTCMISCERR7, "HT core Misc7"),
466 INFINIPATH_HWE_MSG(RXDSYNCMEMPARITYERR, "Rx Dsync"),
467 INFINIPATH_HWE_MSG(SERDESPLLFAILED, "SerDes PLL"),
470 #define TXE_PIO_PARITY ((INFINIPATH_HWE_TXEMEMPARITYERR_PIOBUF | \
471 INFINIPATH_HWE_TXEMEMPARITYERR_PIOPBC) \
472 << INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT)
473 #define RXE_EAGER_PARITY (INFINIPATH_HWE_RXEMEMPARITYERR_EAGERTID \
474 << INFINIPATH_HWE_RXEMEMPARITYERR_SHIFT)
476 static int ipath_ht_txe_recover(struct ipath_devdata *);
479 * ipath_ht_handle_hwerrors - display hardware errors.
480 * @dd: the infinipath device
481 * @msg: the output buffer
482 * @msgl: the size of the output buffer
484 * Use same msg buffer as regular errors to avoid excessive stack
485 * use. Most hardware errors are catastrophic, but for right now,
486 * we'll print them and continue. We reuse the same message buffer as
487 * ipath_handle_errors() to avoid excessive stack usage.
489 static void ipath_ht_handle_hwerrors(struct ipath_devdata *dd, char *msg,
498 hwerrs = ipath_read_kreg64(dd, dd->ipath_kregs->kr_hwerrstatus);
501 ipath_cdbg(VERBOSE, "Called but no hardware errors set\n");
503 * better than printing cofusing messages
504 * This seems to be related to clearing the crc error, or
505 * the pll error during init.
508 } else if (hwerrs == -1LL) {
509 ipath_dev_err(dd, "Read of hardware error status failed "
510 "(all bits set); ignoring\n");
513 ipath_stats.sps_hwerrs++;
515 /* Always clear the error status register, except MEMBISTFAIL,
516 * regardless of whether we continue or stop using the chip.
517 * We want that set so we know it failed, even across driver reload.
518 * We'll still ignore it in the hwerrmask. We do this partly for
519 * diagnostics, but also for support */
520 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrclear,
521 hwerrs&~INFINIPATH_HWE_MEMBISTFAILED);
523 hwerrs &= dd->ipath_hwerrmask;
525 /* We log some errors to EEPROM, check if we have any of those. */
526 for (log_idx = 0; log_idx < IPATH_EEP_LOG_CNT; ++log_idx)
527 if (hwerrs & dd->ipath_eep_st_masks[log_idx].hwerrs_to_log)
528 ipath_inc_eeprom_err(dd, log_idx, 1);
531 * make sure we get this much out, unless told to be quiet,
532 * it's a parity error we may recover from,
533 * or it's occurred within the last 5 seconds
535 if ((hwerrs & ~(dd->ipath_lasthwerror | TXE_PIO_PARITY |
536 RXE_EAGER_PARITY)) ||
537 (ipath_debug & __IPATH_VERBDBG))
538 dev_info(&dd->pcidev->dev, "Hardware error: hwerr=0x%llx "
539 "(cleared)\n", (unsigned long long) hwerrs);
540 dd->ipath_lasthwerror |= hwerrs;
542 if (hwerrs & ~dd->ipath_hwe_bitsextant)
543 ipath_dev_err(dd, "hwerror interrupt with unknown errors "
544 "%llx set\n", (unsigned long long)
545 (hwerrs & ~dd->ipath_hwe_bitsextant));
547 ctrl = ipath_read_kreg32(dd, dd->ipath_kregs->kr_control);
548 if ((ctrl & INFINIPATH_C_FREEZEMODE) && !ipath_diag_inuse) {
550 * parity errors in send memory are recoverable,
551 * just cancel the send (if indicated in * sendbuffererror),
552 * count the occurrence, unfreeze (if no other handled
553 * hardware error bits are set), and continue. They can
554 * occur if a processor speculative read is done to the PIO
555 * buffer while we are sending a packet, for example.
557 if ((hwerrs & TXE_PIO_PARITY) && ipath_ht_txe_recover(dd))
558 hwerrs &= ~TXE_PIO_PARITY;
559 if (hwerrs & RXE_EAGER_PARITY)
560 ipath_dev_err(dd, "RXE parity, Eager TID error is not "
563 ipath_dbg("Clearing freezemode on ignored or "
564 "recovered hardware error\n");
565 ipath_clear_freeze(dd);
572 * may someday want to decode into which bits are which
573 * functional area for parity errors, etc.
575 if (hwerrs & (infinipath_hwe_htcmemparityerr_mask
576 << INFINIPATH_HWE_HTCMEMPARITYERR_SHIFT)) {
577 bits = (u32) ((hwerrs >>
578 INFINIPATH_HWE_HTCMEMPARITYERR_SHIFT) &
579 INFINIPATH_HWE_HTCMEMPARITYERR_MASK);
580 snprintf(bitsmsg, sizeof bitsmsg, "[HTC Parity Errs %x] ",
582 strlcat(msg, bitsmsg, msgl);
585 ipath_format_hwerrors(hwerrs,
586 ipath_6110_hwerror_msgs,
587 sizeof(ipath_6110_hwerror_msgs) /
588 sizeof(ipath_6110_hwerror_msgs[0]),
591 if (hwerrs & (_IPATH_HTLINK0_CRCBITS | _IPATH_HTLINK1_CRCBITS))
592 hwerr_crcbits(dd, hwerrs, msg, msgl);
594 if (hwerrs & INFINIPATH_HWE_MEMBISTFAILED) {
595 strlcat(msg, "[Memory BIST test failed, InfiniPath hardware unusable]",
597 /* ignore from now on, so disable until driver reloaded */
598 dd->ipath_hwerrmask &= ~INFINIPATH_HWE_MEMBISTFAILED;
599 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask,
600 dd->ipath_hwerrmask);
602 #define _IPATH_PLL_FAIL (INFINIPATH_HWE_COREPLL_FBSLIP | \
603 INFINIPATH_HWE_COREPLL_RFSLIP | \
604 INFINIPATH_HWE_HTBPLL_FBSLIP | \
605 INFINIPATH_HWE_HTBPLL_RFSLIP | \
606 INFINIPATH_HWE_HTAPLL_FBSLIP | \
607 INFINIPATH_HWE_HTAPLL_RFSLIP)
609 if (hwerrs & _IPATH_PLL_FAIL) {
610 snprintf(bitsmsg, sizeof bitsmsg,
611 "[PLL failed (%llx), InfiniPath hardware unusable]",
612 (unsigned long long) (hwerrs & _IPATH_PLL_FAIL));
613 strlcat(msg, bitsmsg, msgl);
614 /* ignore from now on, so disable until driver reloaded */
615 dd->ipath_hwerrmask &= ~(hwerrs & _IPATH_PLL_FAIL);
616 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask,
617 dd->ipath_hwerrmask);
620 if (hwerrs & INFINIPATH_HWE_SERDESPLLFAILED) {
622 * If it occurs, it is left masked since the eternal
623 * interface is unused
625 dd->ipath_hwerrmask &= ~INFINIPATH_HWE_SERDESPLLFAILED;
626 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask,
627 dd->ipath_hwerrmask);
632 * if any set that we aren't ignoring; only
633 * make the complaint once, in case it's stuck
634 * or recurring, and we get here multiple
636 * force link down, so switch knows, and
637 * LEDs are turned off
639 if (dd->ipath_flags & IPATH_INITTED) {
640 ipath_set_linkstate(dd, IPATH_IB_LINKDOWN);
641 ipath_setup_ht_setextled(dd,
642 INFINIPATH_IBCS_L_STATE_DOWN,
643 INFINIPATH_IBCS_LT_STATE_DISABLED);
644 ipath_dev_err(dd, "Fatal Hardware Error (freeze "
645 "mode), no longer usable, SN %.16s\n",
649 *dd->ipath_statusp &= ~IPATH_STATUS_IB_READY;
650 /* mark as having had error */
651 *dd->ipath_statusp |= IPATH_STATUS_HWERROR;
653 * mark as not usable, at a minimum until driver
654 * is reloaded, probably until reboot, since no
655 * other reset is possible.
657 dd->ipath_flags &= ~IPATH_INITTED;
660 *msg = 0; /* recovered from all of them */
662 ipath_dev_err(dd, "%s hardware error\n", msg);
663 if (isfatal && !ipath_diag_inuse && dd->ipath_freezemsg)
665 * for status file; if no trailing brace is copied,
666 * we'll know it was truncated.
668 snprintf(dd->ipath_freezemsg,
669 dd->ipath_freezelen, "{%s}", msg);
675 * ipath_ht_boardname - fill in the board name
676 * @dd: the infinipath device
677 * @name: the output buffer
678 * @namelen: the size of the output buffer
680 * fill in the board name, based on the board revision register
682 static int ipath_ht_boardname(struct ipath_devdata *dd, char *name,
686 u8 boardrev = dd->ipath_boardrev;
692 * original production board; two production levels, with
693 * different serial number ranges. See ipath_ht_early_init() for
694 * case where we enable IPATH_GPIO_INTR for later serial # range.
695 * Original 112* serial number is no longer supported.
697 n = "InfiniPath_QHT7040";
700 /* small form factor production board */
701 n = "InfiniPath_QHT7140";
703 default: /* don't know, just print the number */
704 ipath_dev_err(dd, "Don't yet know about board "
705 "with ID %u\n", boardrev);
706 snprintf(name, namelen, "Unknown_InfiniPath_QHT7xxx_%u",
712 snprintf(name, namelen, "%s", n);
715 ipath_dev_err(dd, "Unsupported InfiniPath board %s!\n", name);
718 if (dd->ipath_majrev != 3 || (dd->ipath_minrev < 2 ||
719 dd->ipath_minrev > 4)) {
721 * This version of the driver only supports Rev 3.2 - 3.4
724 "Unsupported InfiniPath hardware revision %u.%u!\n",
725 dd->ipath_majrev, dd->ipath_minrev);
730 * pkt/word counters are 32 bit, and therefore wrap fast enough
731 * that we snapshot them from a timer, and maintain 64 bit shadow
734 dd->ipath_flags |= IPATH_32BITCOUNTERS;
735 dd->ipath_flags |= IPATH_GPIO_INTR;
736 if (dd->ipath_htspeed != 800)
738 "Incorrectly configured for HT @ %uMHz\n",
746 static void ipath_check_htlink(struct ipath_devdata *dd)
748 u8 linkerr, link_off, i;
750 for (i = 0; i < 2; i++) {
751 link_off = dd->ipath_ht_slave_off + i * 4 + 0xd;
752 if (pci_read_config_byte(dd->pcidev, link_off, &linkerr))
753 dev_info(&dd->pcidev->dev, "Couldn't read "
754 "linkerror%d of HT slave/primary block\n",
756 else if (linkerr & 0xf0) {
757 ipath_cdbg(VERBOSE, "HT linkerr%d bits 0x%x set, "
758 "clearing\n", linkerr >> 4, i);
760 * writing the linkerr bits that are set should
763 if (pci_write_config_byte(dd->pcidev, link_off,
765 ipath_dbg("Failed write to clear HT "
767 if (pci_read_config_byte(dd->pcidev, link_off,
769 dev_info(&dd->pcidev->dev,
770 "Couldn't reread linkerror%d of "
771 "HT slave/primary block\n", i);
772 else if (linkerr & 0xf0)
773 dev_info(&dd->pcidev->dev,
774 "HT linkerror%d bits 0x%x "
775 "couldn't be cleared\n",
781 static int ipath_setup_ht_reset(struct ipath_devdata *dd)
783 ipath_dbg("No reset possible for this InfiniPath hardware\n");
787 #define HT_INTR_DISC_CONFIG 0x80 /* HT interrupt and discovery cap */
788 #define HT_INTR_REG_INDEX 2 /* intconfig requires indirect accesses */
791 * Bits 13-15 of command==0 is slave/primary block. Clear any HT CRC
792 * errors. We only bother to do this at load time, because it's OK if
793 * it happened before we were loaded (first time after boot/reset),
794 * but any time after that, it's fatal anyway. Also need to not check
795 * for for upper byte errors if we are in 8 bit mode, so figure out
796 * our width. For now, at least, also complain if it's 8 bit.
798 static void slave_or_pri_blk(struct ipath_devdata *dd, struct pci_dev *pdev,
799 int pos, u8 cap_type)
801 u8 linkwidth = 0, linkerr, link_a_b_off, link_off;
805 dd->ipath_ht_slave_off = pos;
806 /* command word, master_host bit */
807 /* master host || slave */
808 if ((cap_type >> 2) & 1)
812 ipath_cdbg(VERBOSE, "HT%u (Link %c) connected to processor\n",
813 link_a_b_off ? 1 : 0,
814 link_a_b_off ? 'B' : 'A');
819 * check both link control registers; clear both HT CRC sets if
822 for (i = 0; i < 2; i++) {
823 link_off = pos + i * 4 + 0x4;
824 if (pci_read_config_word(pdev, link_off, &linkctrl))
825 ipath_dev_err(dd, "Couldn't read HT link control%d "
827 else if (linkctrl & (0xf << 8)) {
828 ipath_cdbg(VERBOSE, "Clear linkctrl%d CRC Error "
829 "bits %x\n", i, linkctrl & (0xf << 8));
831 * now write them back to clear the error.
833 pci_write_config_byte(pdev, link_off,
834 linkctrl & (0xf << 8));
839 * As with HT CRC bits, same for protocol errors that might occur
842 for (i = 0; i < 2; i++) {
843 link_off = pos + i * 4 + 0xd;
844 if (pci_read_config_byte(pdev, link_off, &linkerr))
845 dev_info(&pdev->dev, "Couldn't read linkerror%d "
846 "of HT slave/primary block\n", i);
847 else if (linkerr & 0xf0) {
848 ipath_cdbg(VERBOSE, "HT linkerr%d bits 0x%x set, "
849 "clearing\n", linkerr >> 4, i);
851 * writing the linkerr bits that are set will clear
854 if (pci_write_config_byte
855 (pdev, link_off, linkerr))
856 ipath_dbg("Failed write to clear HT "
858 if (pci_read_config_byte(pdev, link_off, &linkerr))
859 dev_info(&pdev->dev, "Couldn't reread "
860 "linkerror%d of HT slave/primary "
862 else if (linkerr & 0xf0)
863 dev_info(&pdev->dev, "HT linkerror%d bits "
864 "0x%x couldn't be cleared\n",
870 * this is just for our link to the host, not devices connected
874 if (pci_read_config_byte(pdev, link_a_b_off + 7, &linkwidth))
875 ipath_dev_err(dd, "Couldn't read HT link width "
876 "config register\n");
879 switch (linkwidth & 7) {
893 default: /* if wrong, assume 8 bit */
898 dd->ipath_htwidth = width;
900 if (linkwidth != 0x11) {
901 ipath_dev_err(dd, "Not configured for 16 bit HT "
902 "(%x)\n", linkwidth);
903 if (!(linkwidth & 0xf)) {
904 ipath_dbg("Will ignore HT lane1 errors\n");
905 dd->ipath_flags |= IPATH_8BIT_IN_HT0;
911 * this is just for our link to the host, not devices connected
914 if (pci_read_config_byte(pdev, link_a_b_off + 0xd, &linkwidth))
915 ipath_dev_err(dd, "Couldn't read HT link frequency "
916 "config register\n");
919 switch (linkwidth & 0xf) {
940 * assume reserved and vendor-specific are 200...
946 dd->ipath_htspeed = speed;
950 static int ipath_ht_intconfig(struct ipath_devdata *dd)
954 if (dd->ipath_intconfig) {
955 ipath_write_kreg(dd, dd->ipath_kregs->kr_interruptconfig,
956 dd->ipath_intconfig); /* interrupt address */
959 ipath_dev_err(dd, "No interrupts enabled, couldn't setup "
960 "interrupt address\n");
967 static void ipath_ht_irq_update(struct pci_dev *dev, int irq,
968 struct ht_irq_msg *msg)
970 struct ipath_devdata *dd = pci_get_drvdata(dev);
971 u64 prev_intconfig = dd->ipath_intconfig;
973 dd->ipath_intconfig = msg->address_lo;
974 dd->ipath_intconfig |= ((u64) msg->address_hi) << 32;
977 * If the previous value of dd->ipath_intconfig is zero, we're
978 * getting configured for the first time, and must not program the
979 * intconfig register here (it will be programmed later, when the
980 * hardware is ready). Otherwise, we should.
983 ipath_ht_intconfig(dd);
987 * ipath_setup_ht_config - setup the interruptconfig register
988 * @dd: the infinipath device
989 * @pdev: the PCI device
991 * setup the interruptconfig register from the HT config info.
992 * Also clear CRC errors in HT linkcontrol, if necessary.
993 * This is done only for the real hardware. It is done before
994 * chip address space is initted, so can't touch infinipath registers
996 static int ipath_setup_ht_config(struct ipath_devdata *dd,
997 struct pci_dev *pdev)
1001 ret = __ht_create_irq(pdev, 0, ipath_ht_irq_update);
1003 ipath_dev_err(dd, "Couldn't create interrupt handler: "
1007 dd->ipath_irq = ret;
1011 * Handle clearing CRC errors in linkctrl register if necessary. We
1012 * do this early, before we ever enable errors or hardware errors,
1013 * mostly to avoid causing the chip to enter freeze mode.
1015 pos = pci_find_capability(pdev, PCI_CAP_ID_HT);
1017 ipath_dev_err(dd, "Couldn't find HyperTransport "
1018 "capability; no interrupts\n");
1025 /* the HT capability type byte is 3 bytes after the
1028 if (pci_read_config_byte(pdev, pos + 3, &cap_type)) {
1029 dev_info(&pdev->dev, "Couldn't read config "
1030 "command @ %d\n", pos);
1033 if (!(cap_type & 0xE0))
1034 slave_or_pri_blk(dd, pdev, pos, cap_type);
1035 } while ((pos = pci_find_next_capability(pdev, pos,
1043 * ipath_setup_ht_cleanup - clean up any per-chip chip-specific stuff
1044 * @dd: the infinipath device
1046 * Called during driver unload.
1047 * This is currently a nop for the HT chip, not for all chips
1049 static void ipath_setup_ht_cleanup(struct ipath_devdata *dd)
1054 * ipath_setup_ht_setextled - set the state of the two external LEDs
1055 * @dd: the infinipath device
1057 * @ltst: the LT state
1059 * Set the state of the two external LEDs, to indicate physical and
1060 * logical state of IB link. For this chip (at least with recommended
1061 * board pinouts), LED1 is Green (physical state), and LED2 is Yellow
1064 * Note: We try to match the Mellanox HCA LED behavior as best
1065 * we can. Green indicates physical link state is OK (something is
1066 * plugged in, and we can train).
1067 * Amber indicates the link is logically up (ACTIVE).
1068 * Mellanox further blinks the amber LED to indicate data packet
1069 * activity, but we have no hardware support for that, so it would
1070 * require waking up every 10-20 msecs and checking the counters
1071 * on the chip, and then turning the LED off if appropriate. That's
1072 * visible overhead, so not something we will do.
1075 static void ipath_setup_ht_setextled(struct ipath_devdata *dd,
1079 unsigned long flags = 0;
1081 /* the diags use the LED to indicate diag info, so we leave
1082 * the external LED alone when the diags are running */
1083 if (ipath_diag_inuse)
1086 /* Allow override of LED display for, e.g. Locating system in rack */
1087 if (dd->ipath_led_override) {
1088 ltst = (dd->ipath_led_override & IPATH_LED_PHYS)
1089 ? INFINIPATH_IBCS_LT_STATE_LINKUP
1090 : INFINIPATH_IBCS_LT_STATE_DISABLED;
1091 lst = (dd->ipath_led_override & IPATH_LED_LOG)
1092 ? INFINIPATH_IBCS_L_STATE_ACTIVE
1093 : INFINIPATH_IBCS_L_STATE_DOWN;
1096 spin_lock_irqsave(&dd->ipath_gpio_lock, flags);
1098 * start by setting both LED control bits to off, then turn
1099 * on the appropriate bit(s).
1101 if (dd->ipath_boardrev == 8) { /* LS/X-1 uses different pins */
1103 * major difference is that INFINIPATH_EXTC_LEDGBLERR_OFF
1104 * is inverted, because it is normally used to indicate
1105 * a hardware fault at reset, if there were errors
1107 extctl = (dd->ipath_extctrl & ~INFINIPATH_EXTC_LEDGBLOK_ON)
1108 | INFINIPATH_EXTC_LEDGBLERR_OFF;
1109 if (ltst == INFINIPATH_IBCS_LT_STATE_LINKUP)
1110 extctl &= ~INFINIPATH_EXTC_LEDGBLERR_OFF;
1111 if (lst == INFINIPATH_IBCS_L_STATE_ACTIVE)
1112 extctl |= INFINIPATH_EXTC_LEDGBLOK_ON;
1115 extctl = dd->ipath_extctrl &
1116 ~(INFINIPATH_EXTC_LED1PRIPORT_ON |
1117 INFINIPATH_EXTC_LED2PRIPORT_ON);
1118 if (ltst == INFINIPATH_IBCS_LT_STATE_LINKUP)
1119 extctl |= INFINIPATH_EXTC_LED1PRIPORT_ON;
1120 if (lst == INFINIPATH_IBCS_L_STATE_ACTIVE)
1121 extctl |= INFINIPATH_EXTC_LED2PRIPORT_ON;
1123 dd->ipath_extctrl = extctl;
1124 ipath_write_kreg(dd, dd->ipath_kregs->kr_extctrl, extctl);
1125 spin_unlock_irqrestore(&dd->ipath_gpio_lock, flags);
1128 static void ipath_init_ht_variables(struct ipath_devdata *dd)
1130 dd->ipath_gpio_sda_num = _IPATH_GPIO_SDA_NUM;
1131 dd->ipath_gpio_scl_num = _IPATH_GPIO_SCL_NUM;
1132 dd->ipath_gpio_sda = IPATH_GPIO_SDA;
1133 dd->ipath_gpio_scl = IPATH_GPIO_SCL;
1135 /* Fill in shifts for RcvCtrl. */
1136 dd->ipath_r_portenable_shift = INFINIPATH_R_PORTENABLE_SHIFT;
1137 dd->ipath_r_intravail_shift = INFINIPATH_R_INTRAVAIL_SHIFT;
1138 dd->ipath_r_tailupd_shift = INFINIPATH_R_TAILUPD_SHIFT;
1139 dd->ipath_r_portcfg_shift = 0; /* Not on IBA6110 */
1141 dd->ipath_i_bitsextant =
1142 (INFINIPATH_I_RCVURG_MASK << INFINIPATH_I_RCVURG_SHIFT) |
1143 (INFINIPATH_I_RCVAVAIL_MASK <<
1144 INFINIPATH_I_RCVAVAIL_SHIFT) |
1145 INFINIPATH_I_ERROR | INFINIPATH_I_SPIOSENT |
1146 INFINIPATH_I_SPIOBUFAVAIL | INFINIPATH_I_GPIO;
1148 dd->ipath_e_bitsextant =
1149 INFINIPATH_E_RFORMATERR | INFINIPATH_E_RVCRC |
1150 INFINIPATH_E_RICRC | INFINIPATH_E_RMINPKTLEN |
1151 INFINIPATH_E_RMAXPKTLEN | INFINIPATH_E_RLONGPKTLEN |
1152 INFINIPATH_E_RSHORTPKTLEN | INFINIPATH_E_RUNEXPCHAR |
1153 INFINIPATH_E_RUNSUPVL | INFINIPATH_E_REBP |
1154 INFINIPATH_E_RIBFLOW | INFINIPATH_E_RBADVERSION |
1155 INFINIPATH_E_RRCVEGRFULL | INFINIPATH_E_RRCVHDRFULL |
1156 INFINIPATH_E_RBADTID | INFINIPATH_E_RHDRLEN |
1157 INFINIPATH_E_RHDR | INFINIPATH_E_RIBLOSTLINK |
1158 INFINIPATH_E_SMINPKTLEN | INFINIPATH_E_SMAXPKTLEN |
1159 INFINIPATH_E_SUNDERRUN | INFINIPATH_E_SPKTLEN |
1160 INFINIPATH_E_SDROPPEDSMPPKT | INFINIPATH_E_SDROPPEDDATAPKT |
1161 INFINIPATH_E_SPIOARMLAUNCH | INFINIPATH_E_SUNEXPERRPKTNUM |
1162 INFINIPATH_E_SUNSUPVL | INFINIPATH_E_IBSTATUSCHANGED |
1163 INFINIPATH_E_INVALIDADDR | INFINIPATH_E_RESET |
1164 INFINIPATH_E_HARDWARE;
1166 dd->ipath_hwe_bitsextant =
1167 (INFINIPATH_HWE_HTCMEMPARITYERR_MASK <<
1168 INFINIPATH_HWE_HTCMEMPARITYERR_SHIFT) |
1169 (INFINIPATH_HWE_TXEMEMPARITYERR_MASK <<
1170 INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT) |
1171 (INFINIPATH_HWE_RXEMEMPARITYERR_MASK <<
1172 INFINIPATH_HWE_RXEMEMPARITYERR_SHIFT) |
1173 INFINIPATH_HWE_HTCLNKABYTE0CRCERR |
1174 INFINIPATH_HWE_HTCLNKABYTE1CRCERR |
1175 INFINIPATH_HWE_HTCLNKBBYTE0CRCERR |
1176 INFINIPATH_HWE_HTCLNKBBYTE1CRCERR |
1177 INFINIPATH_HWE_HTCMISCERR4 |
1178 INFINIPATH_HWE_HTCMISCERR5 | INFINIPATH_HWE_HTCMISCERR6 |
1179 INFINIPATH_HWE_HTCMISCERR7 |
1180 INFINIPATH_HWE_HTCBUSTREQPARITYERR |
1181 INFINIPATH_HWE_HTCBUSTRESPPARITYERR |
1182 INFINIPATH_HWE_HTCBUSIREQPARITYERR |
1183 INFINIPATH_HWE_RXDSYNCMEMPARITYERR |
1184 INFINIPATH_HWE_MEMBISTFAILED |
1185 INFINIPATH_HWE_COREPLL_FBSLIP |
1186 INFINIPATH_HWE_COREPLL_RFSLIP |
1187 INFINIPATH_HWE_HTBPLL_FBSLIP |
1188 INFINIPATH_HWE_HTBPLL_RFSLIP |
1189 INFINIPATH_HWE_HTAPLL_FBSLIP |
1190 INFINIPATH_HWE_HTAPLL_RFSLIP |
1191 INFINIPATH_HWE_SERDESPLLFAILED |
1192 INFINIPATH_HWE_IBCBUSTOSPCPARITYERR |
1193 INFINIPATH_HWE_IBCBUSFRSPCPARITYERR;
1195 dd->ipath_i_rcvavail_mask = INFINIPATH_I_RCVAVAIL_MASK;
1196 dd->ipath_i_rcvurg_mask = INFINIPATH_I_RCVURG_MASK;
1199 * EEPROM error log 0 is TXE Parity errors. 1 is RXE Parity.
1200 * 2 is Some Misc, 3 is reserved for future.
1202 dd->ipath_eep_st_masks[0].hwerrs_to_log =
1203 INFINIPATH_HWE_TXEMEMPARITYERR_MASK <<
1204 INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT;
1206 dd->ipath_eep_st_masks[1].hwerrs_to_log =
1207 INFINIPATH_HWE_RXEMEMPARITYERR_MASK <<
1208 INFINIPATH_HWE_RXEMEMPARITYERR_SHIFT;
1210 dd->ipath_eep_st_masks[2].errs_to_log =
1211 INFINIPATH_E_INVALIDADDR | INFINIPATH_E_RESET;
1216 * ipath_ht_init_hwerrors - enable hardware errors
1217 * @dd: the infinipath device
1219 * now that we have finished initializing everything that might reasonably
1220 * cause a hardware error, and cleared those errors bits as they occur,
1221 * we can enable hardware errors in the mask (potentially enabling
1222 * freeze mode), and enable hardware errors as errors (along with
1223 * everything else) in errormask
1225 static void ipath_ht_init_hwerrors(struct ipath_devdata *dd)
1230 extsval = ipath_read_kreg64(dd, dd->ipath_kregs->kr_extstatus);
1232 if (!(extsval & INFINIPATH_EXTS_MEMBIST_ENDTEST))
1233 ipath_dev_err(dd, "MemBIST did not complete!\n");
1234 if (extsval & INFINIPATH_EXTS_MEMBIST_CORRECT)
1235 ipath_dbg("MemBIST corrected\n");
1237 ipath_check_htlink(dd);
1239 /* barring bugs, all hwerrors become interrupts, which can */
1241 /* don't look at crc lane1 if 8 bit */
1242 if (dd->ipath_flags & IPATH_8BIT_IN_HT0)
1243 val &= ~infinipath_hwe_htclnkabyte1crcerr;
1244 /* don't look at crc lane1 if 8 bit */
1245 if (dd->ipath_flags & IPATH_8BIT_IN_HT1)
1246 val &= ~infinipath_hwe_htclnkbbyte1crcerr;
1249 * disable RXDSYNCMEMPARITY because external serdes is unused,
1250 * and therefore the logic will never be used or initialized,
1251 * and uninitialized state will normally result in this error
1252 * being asserted. Similarly for the external serdess pll
1255 val &= ~(INFINIPATH_HWE_SERDESPLLFAILED |
1256 INFINIPATH_HWE_RXDSYNCMEMPARITYERR);
1259 * Disable MISCERR4 because of an inversion in the HT core
1260 * logic checking for errors that cause this bit to be set.
1261 * The errata can also cause the protocol error bit to be set
1262 * in the HT config space linkerror register(s).
1264 val &= ~INFINIPATH_HWE_HTCMISCERR4;
1267 * PLL ignored because MDIO interface has a logic problem
1268 * for reads, on Comstock and Ponderosa. BRINGUP
1270 if (dd->ipath_boardrev == 4 || dd->ipath_boardrev == 9)
1271 val &= ~INFINIPATH_HWE_SERDESPLLFAILED;
1272 dd->ipath_hwerrmask = val;
1276 * ipath_ht_bringup_serdes - bring up the serdes
1277 * @dd: the infinipath device
1279 static int ipath_ht_bringup_serdes(struct ipath_devdata *dd)
1282 int ret = 0, change = 0;
1284 ipath_dbg("Trying to bringup serdes\n");
1286 if (ipath_read_kreg64(dd, dd->ipath_kregs->kr_hwerrstatus) &
1287 INFINIPATH_HWE_SERDESPLLFAILED)
1289 ipath_dbg("At start, serdes PLL failed bit set in "
1290 "hwerrstatus, clearing and continuing\n");
1291 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrclear,
1292 INFINIPATH_HWE_SERDESPLLFAILED);
1295 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesconfig0);
1296 config1 = ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesconfig1);
1298 ipath_cdbg(VERBOSE, "Initial serdes status is config0=%llx "
1299 "config1=%llx, sstatus=%llx xgxs %llx\n",
1300 (unsigned long long) val, (unsigned long long) config1,
1301 (unsigned long long)
1302 ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesstatus),
1303 (unsigned long long)
1304 ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig));
1306 /* force reset on */
1307 val |= INFINIPATH_SERDC0_RESET_PLL
1308 /* | INFINIPATH_SERDC0_RESET_MASK */
1310 ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig0, val);
1311 udelay(15); /* need pll reset set at least for a bit */
1313 if (val & INFINIPATH_SERDC0_RESET_PLL) {
1314 u64 val2 = val &= ~INFINIPATH_SERDC0_RESET_PLL;
1315 /* set lane resets, and tx idle, during pll reset */
1316 val2 |= INFINIPATH_SERDC0_RESET_MASK |
1317 INFINIPATH_SERDC0_TXIDLE;
1318 ipath_cdbg(VERBOSE, "Clearing serdes PLL reset (writing "
1319 "%llx)\n", (unsigned long long) val2);
1320 ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig0,
1323 * be sure chip saw it
1325 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
1327 * need pll reset clear at least 11 usec before lane
1328 * resets cleared; give it a few more
1331 val = val2; /* for check below */
1334 if (val & (INFINIPATH_SERDC0_RESET_PLL |
1335 INFINIPATH_SERDC0_RESET_MASK |
1336 INFINIPATH_SERDC0_TXIDLE)) {
1337 val &= ~(INFINIPATH_SERDC0_RESET_PLL |
1338 INFINIPATH_SERDC0_RESET_MASK |
1339 INFINIPATH_SERDC0_TXIDLE);
1341 ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig0,
1345 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig);
1346 if (((val >> INFINIPATH_XGXS_MDIOADDR_SHIFT) &
1347 INFINIPATH_XGXS_MDIOADDR_MASK) != 3) {
1348 val &= ~(INFINIPATH_XGXS_MDIOADDR_MASK <<
1349 INFINIPATH_XGXS_MDIOADDR_SHIFT);
1353 val |= 3ULL << INFINIPATH_XGXS_MDIOADDR_SHIFT;
1356 if (val & INFINIPATH_XGXS_RESET) {
1357 /* normally true after boot */
1358 val &= ~INFINIPATH_XGXS_RESET;
1361 if (((val >> INFINIPATH_XGXS_RX_POL_SHIFT) &
1362 INFINIPATH_XGXS_RX_POL_MASK) != dd->ipath_rx_pol_inv ) {
1363 /* need to compensate for Tx inversion in partner */
1364 val &= ~(INFINIPATH_XGXS_RX_POL_MASK <<
1365 INFINIPATH_XGXS_RX_POL_SHIFT);
1366 val |= dd->ipath_rx_pol_inv <<
1367 INFINIPATH_XGXS_RX_POL_SHIFT;
1371 ipath_write_kreg(dd, dd->ipath_kregs->kr_xgxsconfig, val);
1373 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesconfig0);
1375 /* clear current and de-emphasis bits */
1376 config1 &= ~0x0ffffffff00ULL;
1377 /* set current to 20ma */
1378 config1 |= 0x00000000000ULL;
1379 /* set de-emphasis to -5.68dB */
1380 config1 |= 0x0cccc000000ULL;
1381 ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig1, config1);
1383 ipath_cdbg(VERBOSE, "After setup: serdes status is config0=%llx "
1384 "config1=%llx, sstatus=%llx xgxs %llx\n",
1385 (unsigned long long) val, (unsigned long long) config1,
1386 (unsigned long long)
1387 ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesstatus),
1388 (unsigned long long)
1389 ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig));
1391 if (!ipath_waitfor_mdio_cmdready(dd)) {
1392 ipath_write_kreg(dd, dd->ipath_kregs->kr_mdio,
1393 ipath_mdio_req(IPATH_MDIO_CMD_READ, 31,
1394 IPATH_MDIO_CTRL_XGXS_REG_8,
1396 if (ipath_waitfor_complete(dd, dd->ipath_kregs->kr_mdio,
1397 IPATH_MDIO_DATAVALID, &val))
1398 ipath_dbg("Never got MDIO data for XGXS status "
1401 ipath_cdbg(VERBOSE, "MDIO Read reg8, "
1402 "'bank' 31 %x\n", (u32) val);
1404 ipath_dbg("Never got MDIO cmdready for XGXS status read\n");
1406 return ret; /* for now, say we always succeeded */
1410 * ipath_ht_quiet_serdes - set serdes to txidle
1411 * @dd: the infinipath device
1412 * driver is being unloaded
1414 static void ipath_ht_quiet_serdes(struct ipath_devdata *dd)
1416 u64 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesconfig0);
1418 val |= INFINIPATH_SERDC0_TXIDLE;
1419 ipath_dbg("Setting TxIdleEn on serdes (config0 = %llx)\n",
1420 (unsigned long long) val);
1421 ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig0, val);
1425 * ipath_pe_put_tid - write a TID in chip
1426 * @dd: the infinipath device
1427 * @tidptr: pointer to the expected TID (in chip) to udpate
1428 * @tidtype: RCVHQ_RCV_TYPE_EAGER (1) for eager, RCVHQ_RCV_TYPE_EXPECTED (0) for expected
1429 * @pa: physical address of in memory buffer; ipath_tidinvalid if freeing
1431 * This exists as a separate routine to allow for special locking etc.
1432 * It's used for both the full cleanup on exit, as well as the normal
1433 * setup and teardown.
1435 static void ipath_ht_put_tid(struct ipath_devdata *dd,
1436 u64 __iomem *tidptr, u32 type,
1439 if (!dd->ipath_kregbase)
1442 if (pa != dd->ipath_tidinvalid) {
1443 if (unlikely((pa & ~INFINIPATH_RT_ADDR_MASK))) {
1444 dev_info(&dd->pcidev->dev,
1445 "physaddr %lx has more than "
1446 "40 bits, using only 40!!!\n", pa);
1447 pa &= INFINIPATH_RT_ADDR_MASK;
1449 if (type == RCVHQ_RCV_TYPE_EAGER)
1450 pa |= dd->ipath_tidtemplate;
1452 /* in words (fixed, full page). */
1453 u64 lenvalid = PAGE_SIZE >> 2;
1454 lenvalid <<= INFINIPATH_RT_BUFSIZE_SHIFT;
1455 pa |= lenvalid | INFINIPATH_RT_VALID;
1463 * ipath_ht_clear_tid - clear all TID entries for a port, expected and eager
1464 * @dd: the infinipath device
1467 * Used from ipath_close(), and at chip initialization.
1469 static void ipath_ht_clear_tids(struct ipath_devdata *dd, unsigned port)
1471 u64 __iomem *tidbase;
1474 if (!dd->ipath_kregbase)
1477 ipath_cdbg(VERBOSE, "Invalidate TIDs for port %u\n", port);
1480 * need to invalidate all of the expected TID entries for this
1481 * port, so we don't have valid entries that might somehow get
1482 * used (early in next use of this port, or through some bug)
1484 tidbase = (u64 __iomem *) ((char __iomem *)(dd->ipath_kregbase) +
1485 dd->ipath_rcvtidbase +
1486 port * dd->ipath_rcvtidcnt *
1488 for (i = 0; i < dd->ipath_rcvtidcnt; i++)
1489 ipath_ht_put_tid(dd, &tidbase[i], RCVHQ_RCV_TYPE_EXPECTED,
1490 dd->ipath_tidinvalid);
1492 tidbase = (u64 __iomem *) ((char __iomem *)(dd->ipath_kregbase) +
1493 dd->ipath_rcvegrbase +
1494 port * dd->ipath_rcvegrcnt *
1497 for (i = 0; i < dd->ipath_rcvegrcnt; i++)
1498 ipath_ht_put_tid(dd, &tidbase[i], RCVHQ_RCV_TYPE_EAGER,
1499 dd->ipath_tidinvalid);
1503 * ipath_ht_tidtemplate - setup constants for TID updates
1504 * @dd: the infinipath device
1506 * We setup stuff that we use a lot, to avoid calculating each time
1508 static void ipath_ht_tidtemplate(struct ipath_devdata *dd)
1510 dd->ipath_tidtemplate = dd->ipath_ibmaxlen >> 2;
1511 dd->ipath_tidtemplate <<= INFINIPATH_RT_BUFSIZE_SHIFT;
1512 dd->ipath_tidtemplate |= INFINIPATH_RT_VALID;
1515 * work around chip errata bug 7358, by marking invalid tids
1516 * as having max length
1518 dd->ipath_tidinvalid = (-1LL & INFINIPATH_RT_BUFSIZE_MASK) <<
1519 INFINIPATH_RT_BUFSIZE_SHIFT;
1522 static int ipath_ht_early_init(struct ipath_devdata *dd)
1524 u32 __iomem *piobuf;
1529 * one cache line; long IB headers will spill over into received
1532 dd->ipath_rcvhdrentsize = 16;
1533 dd->ipath_rcvhdrsize = IPATH_DFLT_RCVHDRSIZE;
1536 * For HT, we allocate a somewhat overly large eager buffer,
1537 * such that we can guarantee that we can receive the largest
1538 * packet that we can send out. To truly support a 4KB MTU,
1539 * we need to bump this to a large value. To date, other than
1540 * testing, we have never encountered an HCA that can really
1541 * send 4KB MTU packets, so we do not handle that (we'll get
1542 * errors interrupts if we ever see one).
1544 dd->ipath_rcvegrbufsize = dd->ipath_piosize2k;
1547 * the min() check here is currently a nop, but it may not
1548 * always be, depending on just how we do ipath_rcvegrbufsize
1550 dd->ipath_ibmaxlen = min(dd->ipath_piosize2k,
1551 dd->ipath_rcvegrbufsize);
1552 dd->ipath_init_ibmaxlen = dd->ipath_ibmaxlen;
1553 ipath_ht_tidtemplate(dd);
1556 * zero all the TID entries at startup. We do this for sanity,
1557 * in case of a previous driver crash of some kind, and also
1558 * because the chip powers up with these memories in an unknown
1559 * state. Use portcnt, not cfgports, since this is for the
1560 * full chip, not for current (possibly different) configuration
1562 * Chip Errata bug 6447
1564 for (val32 = 0; val32 < dd->ipath_portcnt; val32++)
1565 ipath_ht_clear_tids(dd, val32);
1568 * write the pbc of each buffer, to be sure it's initialized, then
1569 * cancel all the buffers, and also abort any packets that might
1570 * have been in flight for some reason (the latter is for driver
1571 * unload/reload, but isn't a bad idea at first init). PIO send
1572 * isn't enabled at this point, so there is no danger of sending
1573 * these out on the wire.
1574 * Chip Errata bug 6610
1576 piobuf = (u32 __iomem *) (((char __iomem *)(dd->ipath_kregbase)) +
1577 dd->ipath_piobufbase);
1578 pioincr = dd->ipath_palign / sizeof(*piobuf);
1579 for (i = 0; i < dd->ipath_piobcnt2k; i++) {
1581 * reasonable word count, just to init pbc
1587 ipath_get_eeprom_info(dd);
1588 if (dd->ipath_boardrev == 5 && dd->ipath_serial[0] == '1' &&
1589 dd->ipath_serial[1] == '2' && dd->ipath_serial[2] == '8') {
1591 * Later production QHT7040 has same changes as QHT7140, so
1592 * can use GPIO interrupts. They have serial #'s starting
1593 * with 128, rather than 112.
1595 if (dd->ipath_serial[0] == '1' &&
1596 dd->ipath_serial[1] == '2' &&
1597 dd->ipath_serial[2] == '8')
1598 dd->ipath_flags |= IPATH_GPIO_INTR;
1600 ipath_dev_err(dd, "Unsupported InfiniPath board "
1601 "(serial number %.16s)!\n",
1607 if (dd->ipath_minrev >= 4) {
1608 /* Rev4+ reports extra errors via internal GPIO pins */
1609 dd->ipath_flags |= IPATH_GPIO_ERRINTRS;
1610 dd->ipath_gpio_mask |= IPATH_GPIO_ERRINTR_MASK;
1611 ipath_write_kreg(dd, dd->ipath_kregs->kr_gpio_mask,
1612 dd->ipath_gpio_mask);
1619 static int ipath_ht_txe_recover(struct ipath_devdata *dd)
1621 int cnt = ++ipath_stats.sps_txeparity;
1622 if (cnt >= IPATH_MAX_PARITY_ATTEMPTS) {
1623 if (cnt == IPATH_MAX_PARITY_ATTEMPTS)
1625 "Too many attempts to recover from "
1626 "TXE parity, giving up\n");
1629 dev_info(&dd->pcidev->dev,
1630 "Recovering from TXE PIO parity error\n");
1636 * ipath_init_ht_get_base_info - set chip-specific flags for user code
1637 * @dd: the infinipath device
1638 * @kbase: ipath_base_info pointer
1640 * We set the PCIE flag because the lower bandwidth on PCIe vs
1641 * HyperTransport can affect some user packet algorithms.
1643 static int ipath_ht_get_base_info(struct ipath_portdata *pd, void *kbase)
1645 struct ipath_base_info *kinfo = kbase;
1647 kinfo->spi_runtime_flags |= IPATH_RUNTIME_HT |
1648 IPATH_RUNTIME_PIO_REGSWAPPED;
1650 if (pd->port_dd->ipath_minrev < 4)
1651 kinfo->spi_runtime_flags |= IPATH_RUNTIME_RCVHDR_COPY;
1656 static void ipath_ht_free_irq(struct ipath_devdata *dd)
1658 free_irq(dd->ipath_irq, dd);
1659 ht_destroy_irq(dd->ipath_irq);
1661 dd->ipath_intconfig = 0;
1664 static void ipath_ht_read_counters(struct ipath_devdata *dd,
1665 struct infinipath_counters *cntrs)
1668 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(LBIntCnt));
1669 cntrs->LBFlowStallCnt =
1670 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(LBFlowStallCnt));
1671 cntrs->TxSDmaDescCnt = 0;
1672 cntrs->TxUnsupVLErrCnt =
1673 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(TxUnsupVLErrCnt));
1674 cntrs->TxDataPktCnt =
1675 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(TxDataPktCnt));
1676 cntrs->TxFlowPktCnt =
1677 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(TxFlowPktCnt));
1679 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(TxDwordCnt));
1680 cntrs->TxLenErrCnt =
1681 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(TxLenErrCnt));
1682 cntrs->TxMaxMinLenErrCnt =
1683 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(TxMaxMinLenErrCnt));
1684 cntrs->TxUnderrunCnt =
1685 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(TxUnderrunCnt));
1686 cntrs->TxFlowStallCnt =
1687 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(TxFlowStallCnt));
1688 cntrs->TxDroppedPktCnt =
1689 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(TxDroppedPktCnt));
1690 cntrs->RxDroppedPktCnt =
1691 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxDroppedPktCnt));
1692 cntrs->RxDataPktCnt =
1693 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxDataPktCnt));
1694 cntrs->RxFlowPktCnt =
1695 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxFlowPktCnt));
1697 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxDwordCnt));
1698 cntrs->RxLenErrCnt =
1699 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxLenErrCnt));
1700 cntrs->RxMaxMinLenErrCnt =
1701 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxMaxMinLenErrCnt));
1702 cntrs->RxICRCErrCnt =
1703 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxICRCErrCnt));
1704 cntrs->RxVCRCErrCnt =
1705 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxVCRCErrCnt));
1706 cntrs->RxFlowCtrlErrCnt =
1707 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxFlowCtrlErrCnt));
1708 cntrs->RxBadFormatCnt =
1709 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxBadFormatCnt));
1710 cntrs->RxLinkProblemCnt =
1711 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxLinkProblemCnt));
1713 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxEBPCnt));
1714 cntrs->RxLPCRCErrCnt =
1715 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxLPCRCErrCnt));
1716 cntrs->RxBufOvflCnt =
1717 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxBufOvflCnt));
1718 cntrs->RxTIDFullErrCnt =
1719 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxTIDFullErrCnt));
1720 cntrs->RxTIDValidErrCnt =
1721 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxTIDValidErrCnt));
1722 cntrs->RxPKeyMismatchCnt =
1723 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxPKeyMismatchCnt));
1724 cntrs->RxP0HdrEgrOvflCnt =
1725 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxP0HdrEgrOvflCnt));
1726 cntrs->RxP1HdrEgrOvflCnt =
1727 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxP1HdrEgrOvflCnt));
1728 cntrs->RxP2HdrEgrOvflCnt =
1729 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxP2HdrEgrOvflCnt));
1730 cntrs->RxP3HdrEgrOvflCnt =
1731 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxP3HdrEgrOvflCnt));
1732 cntrs->RxP4HdrEgrOvflCnt =
1733 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxP4HdrEgrOvflCnt));
1734 cntrs->RxP5HdrEgrOvflCnt =
1735 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxP5HdrEgrOvflCnt));
1736 cntrs->RxP6HdrEgrOvflCnt =
1737 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxP6HdrEgrOvflCnt));
1738 cntrs->RxP7HdrEgrOvflCnt =
1739 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxP7HdrEgrOvflCnt));
1740 cntrs->RxP8HdrEgrOvflCnt =
1741 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxP8HdrEgrOvflCnt));
1742 cntrs->RxP9HdrEgrOvflCnt = 0;
1743 cntrs->RxP10HdrEgrOvflCnt = 0;
1744 cntrs->RxP11HdrEgrOvflCnt = 0;
1745 cntrs->RxP12HdrEgrOvflCnt = 0;
1746 cntrs->RxP13HdrEgrOvflCnt = 0;
1747 cntrs->RxP14HdrEgrOvflCnt = 0;
1748 cntrs->RxP15HdrEgrOvflCnt = 0;
1749 cntrs->RxP16HdrEgrOvflCnt = 0;
1750 cntrs->IBStatusChangeCnt =
1751 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(IBStatusChangeCnt));
1752 cntrs->IBLinkErrRecoveryCnt =
1753 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(IBLinkErrRecoveryCnt));
1754 cntrs->IBLinkDownedCnt =
1755 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(IBLinkDownedCnt));
1756 cntrs->IBSymbolErrCnt =
1757 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(IBSymbolErrCnt));
1758 cntrs->RxVL15DroppedPktCnt = 0;
1759 cntrs->RxOtherLocalPhyErrCnt = 0;
1760 cntrs->PcieRetryBufDiagQwordCnt = 0;
1761 cntrs->ExcessBufferOvflCnt = dd->ipath_overrun_thresh_errs;
1762 cntrs->LocalLinkIntegrityErrCnt =
1763 (dd->ipath_flags & IPATH_GPIO_ERRINTRS) ?
1764 dd->ipath_lli_errs : dd->ipath_lli_errors;
1765 cntrs->RxVlErrCnt = 0;
1766 cntrs->RxDlidFltrCnt = 0;
1770 * ipath_init_iba6110_funcs - set up the chip-specific function pointers
1771 * @dd: the infinipath device
1773 * This is global, and is called directly at init to set up the
1774 * chip-specific function pointers for later use.
1776 void ipath_init_iba6110_funcs(struct ipath_devdata *dd)
1778 dd->ipath_f_intrsetup = ipath_ht_intconfig;
1779 dd->ipath_f_bus = ipath_setup_ht_config;
1780 dd->ipath_f_reset = ipath_setup_ht_reset;
1781 dd->ipath_f_get_boardname = ipath_ht_boardname;
1782 dd->ipath_f_init_hwerrors = ipath_ht_init_hwerrors;
1783 dd->ipath_f_early_init = ipath_ht_early_init;
1784 dd->ipath_f_handle_hwerrors = ipath_ht_handle_hwerrors;
1785 dd->ipath_f_quiet_serdes = ipath_ht_quiet_serdes;
1786 dd->ipath_f_bringup_serdes = ipath_ht_bringup_serdes;
1787 dd->ipath_f_clear_tids = ipath_ht_clear_tids;
1788 dd->ipath_f_put_tid = ipath_ht_put_tid;
1789 dd->ipath_f_cleanup = ipath_setup_ht_cleanup;
1790 dd->ipath_f_setextled = ipath_setup_ht_setextled;
1791 dd->ipath_f_get_base_info = ipath_ht_get_base_info;
1792 dd->ipath_f_free_irq = ipath_ht_free_irq;
1793 dd->ipath_f_read_counters = ipath_ht_read_counters;
1796 * initialize chip-specific variables
1798 dd->ipath_f_tidtemplate = ipath_ht_tidtemplate;
1801 * setup the register offsets, since they are different for each
1804 dd->ipath_kregs = &ipath_ht_kregs;
1805 dd->ipath_cregs = &ipath_ht_cregs;
1808 * do very early init that is needed before ipath_f_bus is
1811 ipath_init_ht_variables(dd);