drivers/infiniband/hw/ipath/ipath_iba6120.c

   1 /*
   2  * Copyright (c) 2006, 2007 QLogic Corporation. All rights reserved.
   3  * Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved.
   4  *
   5  * This software is available to you under a choice of one of two
   6  * licenses.  You may choose to be licensed under the terms of the GNU
   7  * General Public License (GPL) Version 2, available from the file
   8  * COPYING in the main directory of this source tree, or the
   9  * OpenIB.org BSD license below:
  10  *
  11  *     Redistribution and use in source and binary forms, with or
  12  *     without modification, are permitted provided that the following
  13  *     conditions are met:
  14  *
  15  *      - Redistributions of source code must retain the above
  16  *        copyright notice, this list of conditions and the following
  17  *        disclaimer.
  18  *
  19  *      - Redistributions in binary form must reproduce the above
  20  *        copyright notice, this list of conditions and the following
  21  *        disclaimer in the documentation and/or other materials
  22  *        provided with the distribution.
  23  *
  24  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  25  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  26  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  27  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  28  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  29  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  30  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  31  * SOFTWARE.
  32  */
  33 /*
  34  * This file contains all of the code that is specific to the
  35  * InfiniPath PCIe chip.
  36  */
  37
  38 #include <linux/interrupt.h>
  39 #include <linux/pci.h>
  40 #include <linux/delay.h>
  41
  42
  43 #include "ipath_kernel.h"
  44 #include "ipath_registers.h"
  45
  46 static void ipath_setup_pe_setextled(struct ipath_devdata *, u64, u64);
  47
  48 /*
  49  * This file contains all the chip-specific register information and
  50  * access functions for the QLogic InfiniPath PCI-Express chip.
  51  *
  52  * This lists the InfiniPath registers, in the actual chip layout.
  53  * This structure should never be directly accessed.
  54  */
  55 struct _infinipath_do_not_use_kernel_regs {
  56         unsigned long long Revision;
  57         unsigned long long Control;
  58         unsigned long long PageAlign;
  59         unsigned long long PortCnt;
  60         unsigned long long DebugPortSelect;
  61         unsigned long long Reserved0;
  62         unsigned long long SendRegBase;
  63         unsigned long long UserRegBase;
  64         unsigned long long CounterRegBase;
  65         unsigned long long Scratch;
  66         unsigned long long Reserved1;
  67         unsigned long long Reserved2;
  68         unsigned long long IntBlocked;
  69         unsigned long long IntMask;
  70         unsigned long long IntStatus;
  71         unsigned long long IntClear;
  72         unsigned long long ErrorMask;
  73         unsigned long long ErrorStatus;
  74         unsigned long long ErrorClear;
  75         unsigned long long HwErrMask;
  76         unsigned long long HwErrStatus;
  77         unsigned long long HwErrClear;
  78         unsigned long long HwDiagCtrl;
  79         unsigned long long MDIO;
  80         unsigned long long IBCStatus;
  81         unsigned long long IBCCtrl;
  82         unsigned long long ExtStatus;
  83         unsigned long long ExtCtrl;
  84         unsigned long long GPIOOut;
  85         unsigned long long GPIOMask;
  86         unsigned long long GPIOStatus;
  87         unsigned long long GPIOClear;
  88         unsigned long long RcvCtrl;
  89         unsigned long long RcvBTHQP;
  90         unsigned long long RcvHdrSize;
  91         unsigned long long RcvHdrCnt;
  92         unsigned long long RcvHdrEntSize;
  93         unsigned long long RcvTIDBase;
  94         unsigned long long RcvTIDCnt;
  95         unsigned long long RcvEgrBase;
  96         unsigned long long RcvEgrCnt;
  97         unsigned long long RcvBufBase;
  98         unsigned long long RcvBufSize;
  99         unsigned long long RxIntMemBase;
 100         unsigned long long RxIntMemSize;
 101         unsigned long long RcvPartitionKey;
 102         unsigned long long Reserved3;
 103         unsigned long long RcvPktLEDCnt;
 104         unsigned long long Reserved4[8];
 105         unsigned long long SendCtrl;
 106         unsigned long long SendPIOBufBase;
 107         unsigned long long SendPIOSize;
 108         unsigned long long SendPIOBufCnt;
 109         unsigned long long SendPIOAvailAddr;
 110         unsigned long long TxIntMemBase;
 111         unsigned long long TxIntMemSize;
 112         unsigned long long Reserved5;
 113         unsigned long long PCIeRBufTestReg0;
 114         unsigned long long PCIeRBufTestReg1;
 115         unsigned long long Reserved51[6];
 116         unsigned long long SendBufferError;
 117         unsigned long long SendBufferErrorCONT1;
 118         unsigned long long Reserved6SBE[6];
 119         unsigned long long RcvHdrAddr0;
 120         unsigned long long RcvHdrAddr1;
 121         unsigned long long RcvHdrAddr2;
 122         unsigned long long RcvHdrAddr3;
 123         unsigned long long RcvHdrAddr4;
 124         unsigned long long Reserved7RHA[11];
 125         unsigned long long RcvHdrTailAddr0;
 126         unsigned long long RcvHdrTailAddr1;
 127         unsigned long long RcvHdrTailAddr2;
 128         unsigned long long RcvHdrTailAddr3;
 129         unsigned long long RcvHdrTailAddr4;
 130         unsigned long long Reserved8RHTA[11];
 131         unsigned long long Reserved9SW[8];
 132         unsigned long long SerdesConfig0;
 133         unsigned long long SerdesConfig1;
 134         unsigned long long SerdesStatus;
 135         unsigned long long XGXSConfig;
 136         unsigned long long IBPLLCfg;
 137         unsigned long long Reserved10SW2[3];
 138         unsigned long long PCIEQ0SerdesConfig0;
 139         unsigned long long PCIEQ0SerdesConfig1;
 140         unsigned long long PCIEQ0SerdesStatus;
 141         unsigned long long Reserved11;
 142         unsigned long long PCIEQ1SerdesConfig0;
 143         unsigned long long PCIEQ1SerdesConfig1;
 144         unsigned long long PCIEQ1SerdesStatus;
 145         unsigned long long Reserved12;
 146 };
 147
 148 struct _infinipath_do_not_use_counters {
 149         __u64 LBIntCnt;
 150         __u64 LBFlowStallCnt;
 151         __u64 Reserved1;
 152         __u64 TxUnsupVLErrCnt;
 153         __u64 TxDataPktCnt;
 154         __u64 TxFlowPktCnt;
 155         __u64 TxDwordCnt;
 156         __u64 TxLenErrCnt;
 157         __u64 TxMaxMinLenErrCnt;
 158         __u64 TxUnderrunCnt;
 159         __u64 TxFlowStallCnt;
 160         __u64 TxDroppedPktCnt;
 161         __u64 RxDroppedPktCnt;
 162         __u64 RxDataPktCnt;
 163         __u64 RxFlowPktCnt;
 164         __u64 RxDwordCnt;
 165         __u64 RxLenErrCnt;
 166         __u64 RxMaxMinLenErrCnt;
 167         __u64 RxICRCErrCnt;
 168         __u64 RxVCRCErrCnt;
 169         __u64 RxFlowCtrlErrCnt;
 170         __u64 RxBadFormatCnt;
 171         __u64 RxLinkProblemCnt;
 172         __u64 RxEBPCnt;
 173         __u64 RxLPCRCErrCnt;
 174         __u64 RxBufOvflCnt;
 175         __u64 RxTIDFullErrCnt;
 176         __u64 RxTIDValidErrCnt;
 177         __u64 RxPKeyMismatchCnt;
 178         __u64 RxP0HdrEgrOvflCnt;
 179         __u64 RxP1HdrEgrOvflCnt;
 180         __u64 RxP2HdrEgrOvflCnt;
 181         __u64 RxP3HdrEgrOvflCnt;
 182         __u64 RxP4HdrEgrOvflCnt;
 183         __u64 RxP5HdrEgrOvflCnt;
 184         __u64 RxP6HdrEgrOvflCnt;
 185         __u64 RxP7HdrEgrOvflCnt;
 186         __u64 RxP8HdrEgrOvflCnt;
 187         __u64 Reserved6;
 188         __u64 Reserved7;
 189         __u64 IBStatusChangeCnt;
 190         __u64 IBLinkErrRecoveryCnt;
 191         __u64 IBLinkDownedCnt;
 192         __u64 IBSymbolErrCnt;
 193 };
 194
 195 #define IPATH_KREG_OFFSET(field) (offsetof( \
 196         struct _infinipath_do_not_use_kernel_regs, field) / sizeof(u64))
 197 #define IPATH_CREG_OFFSET(field) (offsetof( \
 198         struct _infinipath_do_not_use_counters, field) / sizeof(u64))
 199
 200 static const struct ipath_kregs ipath_pe_kregs = {
 201         .kr_control = IPATH_KREG_OFFSET(Control),
 202         .kr_counterregbase = IPATH_KREG_OFFSET(CounterRegBase),
 203         .kr_debugportselect = IPATH_KREG_OFFSET(DebugPortSelect),
 204         .kr_errorclear = IPATH_KREG_OFFSET(ErrorClear),
 205         .kr_errormask = IPATH_KREG_OFFSET(ErrorMask),
 206         .kr_errorstatus = IPATH_KREG_OFFSET(ErrorStatus),
 207         .kr_extctrl = IPATH_KREG_OFFSET(ExtCtrl),
 208         .kr_extstatus = IPATH_KREG_OFFSET(ExtStatus),
 209         .kr_gpio_clear = IPATH_KREG_OFFSET(GPIOClear),
 210         .kr_gpio_mask = IPATH_KREG_OFFSET(GPIOMask),
 211         .kr_gpio_out = IPATH_KREG_OFFSET(GPIOOut),
 212         .kr_gpio_status = IPATH_KREG_OFFSET(GPIOStatus),
 213         .kr_hwdiagctrl = IPATH_KREG_OFFSET(HwDiagCtrl),
 214         .kr_hwerrclear = IPATH_KREG_OFFSET(HwErrClear),
 215         .kr_hwerrmask = IPATH_KREG_OFFSET(HwErrMask),
 216         .kr_hwerrstatus = IPATH_KREG_OFFSET(HwErrStatus),
 217         .kr_ibcctrl = IPATH_KREG_OFFSET(IBCCtrl),
 218         .kr_ibcstatus = IPATH_KREG_OFFSET(IBCStatus),
 219         .kr_intblocked = IPATH_KREG_OFFSET(IntBlocked),
 220         .kr_intclear = IPATH_KREG_OFFSET(IntClear),
 221         .kr_intmask = IPATH_KREG_OFFSET(IntMask),
 222         .kr_intstatus = IPATH_KREG_OFFSET(IntStatus),
 223         .kr_mdio = IPATH_KREG_OFFSET(MDIO),
 224         .kr_pagealign = IPATH_KREG_OFFSET(PageAlign),
 225         .kr_partitionkey = IPATH_KREG_OFFSET(RcvPartitionKey),
 226         .kr_portcnt = IPATH_KREG_OFFSET(PortCnt),
 227         .kr_rcvbthqp = IPATH_KREG_OFFSET(RcvBTHQP),
 228         .kr_rcvbufbase = IPATH_KREG_OFFSET(RcvBufBase),
 229         .kr_rcvbufsize = IPATH_KREG_OFFSET(RcvBufSize),
 230         .kr_rcvctrl = IPATH_KREG_OFFSET(RcvCtrl),
 231         .kr_rcvegrbase = IPATH_KREG_OFFSET(RcvEgrBase),
 232         .kr_rcvegrcnt = IPATH_KREG_OFFSET(RcvEgrCnt),
 233         .kr_rcvhdrcnt = IPATH_KREG_OFFSET(RcvHdrCnt),
 234         .kr_rcvhdrentsize = IPATH_KREG_OFFSET(RcvHdrEntSize),
 235         .kr_rcvhdrsize = IPATH_KREG_OFFSET(RcvHdrSize),
 236         .kr_rcvintmembase = IPATH_KREG_OFFSET(RxIntMemBase),
 237         .kr_rcvintmemsize = IPATH_KREG_OFFSET(RxIntMemSize),
 238         .kr_rcvtidbase = IPATH_KREG_OFFSET(RcvTIDBase),
 239         .kr_rcvtidcnt = IPATH_KREG_OFFSET(RcvTIDCnt),
 240         .kr_revision = IPATH_KREG_OFFSET(Revision),
 241         .kr_scratch = IPATH_KREG_OFFSET(Scratch),
 242         .kr_sendbuffererror = IPATH_KREG_OFFSET(SendBufferError),
 243         .kr_sendctrl = IPATH_KREG_OFFSET(SendCtrl),
 244         .kr_sendpioavailaddr = IPATH_KREG_OFFSET(SendPIOAvailAddr),
 245         .kr_sendpiobufbase = IPATH_KREG_OFFSET(SendPIOBufBase),
 246         .kr_sendpiobufcnt = IPATH_KREG_OFFSET(SendPIOBufCnt),
 247         .kr_sendpiosize = IPATH_KREG_OFFSET(SendPIOSize),
 248         .kr_sendregbase = IPATH_KREG_OFFSET(SendRegBase),
 249         .kr_txintmembase = IPATH_KREG_OFFSET(TxIntMemBase),
 250         .kr_txintmemsize = IPATH_KREG_OFFSET(TxIntMemSize),
 251         .kr_userregbase = IPATH_KREG_OFFSET(UserRegBase),
 252         .kr_serdesconfig0 = IPATH_KREG_OFFSET(SerdesConfig0),
 253         .kr_serdesconfig1 = IPATH_KREG_OFFSET(SerdesConfig1),
 254         .kr_serdesstatus = IPATH_KREG_OFFSET(SerdesStatus),
 255         .kr_xgxsconfig = IPATH_KREG_OFFSET(XGXSConfig),
 256         .kr_ibpllcfg = IPATH_KREG_OFFSET(IBPLLCfg),
 257
 258         /*
 259          * These should not be used directly via ipath_write_kreg64(),
 260          * use them with ipath_write_kreg64_port(),
 261          */
 262         .kr_rcvhdraddr = IPATH_KREG_OFFSET(RcvHdrAddr0),
 263         .kr_rcvhdrtailaddr = IPATH_KREG_OFFSET(RcvHdrTailAddr0),
 264
 265         /* The rcvpktled register controls one of the debug port signals, so
 266          * a packet activity LED can be connected to it. */
 267         .kr_rcvpktledcnt = IPATH_KREG_OFFSET(RcvPktLEDCnt),
 268         .kr_pcierbuftestreg0 = IPATH_KREG_OFFSET(PCIeRBufTestReg0),
 269         .kr_pcierbuftestreg1 = IPATH_KREG_OFFSET(PCIeRBufTestReg1),
 270         .kr_pcieq0serdesconfig0 = IPATH_KREG_OFFSET(PCIEQ0SerdesConfig0),
 271         .kr_pcieq0serdesconfig1 = IPATH_KREG_OFFSET(PCIEQ0SerdesConfig1),
 272         .kr_pcieq0serdesstatus = IPATH_KREG_OFFSET(PCIEQ0SerdesStatus),
 273         .kr_pcieq1serdesconfig0 = IPATH_KREG_OFFSET(PCIEQ1SerdesConfig0),
 274         .kr_pcieq1serdesconfig1 = IPATH_KREG_OFFSET(PCIEQ1SerdesConfig1),
 275         .kr_pcieq1serdesstatus = IPATH_KREG_OFFSET(PCIEQ1SerdesStatus)
 276 };
 277
 278 static const struct ipath_cregs ipath_pe_cregs = {
 279         .cr_badformatcnt = IPATH_CREG_OFFSET(RxBadFormatCnt),
 280         .cr_erricrccnt = IPATH_CREG_OFFSET(RxICRCErrCnt),
 281         .cr_errlinkcnt = IPATH_CREG_OFFSET(RxLinkProblemCnt),
 282         .cr_errlpcrccnt = IPATH_CREG_OFFSET(RxLPCRCErrCnt),
 283         .cr_errpkey = IPATH_CREG_OFFSET(RxPKeyMismatchCnt),
 284         .cr_errrcvflowctrlcnt = IPATH_CREG_OFFSET(RxFlowCtrlErrCnt),
 285         .cr_err_rlencnt = IPATH_CREG_OFFSET(RxLenErrCnt),
 286         .cr_errslencnt = IPATH_CREG_OFFSET(TxLenErrCnt),
 287         .cr_errtidfull = IPATH_CREG_OFFSET(RxTIDFullErrCnt),
 288         .cr_errtidvalid = IPATH_CREG_OFFSET(RxTIDValidErrCnt),
 289         .cr_errvcrccnt = IPATH_CREG_OFFSET(RxVCRCErrCnt),
 290         .cr_ibstatuschange = IPATH_CREG_OFFSET(IBStatusChangeCnt),
 291         .cr_intcnt = IPATH_CREG_OFFSET(LBIntCnt),
 292         .cr_invalidrlencnt = IPATH_CREG_OFFSET(RxMaxMinLenErrCnt),
 293         .cr_invalidslencnt = IPATH_CREG_OFFSET(TxMaxMinLenErrCnt),
 294         .cr_lbflowstallcnt = IPATH_CREG_OFFSET(LBFlowStallCnt),
 295         .cr_pktrcvcnt = IPATH_CREG_OFFSET(RxDataPktCnt),
 296         .cr_pktrcvflowctrlcnt = IPATH_CREG_OFFSET(RxFlowPktCnt),
 297         .cr_pktsendcnt = IPATH_CREG_OFFSET(TxDataPktCnt),
 298         .cr_pktsendflowcnt = IPATH_CREG_OFFSET(TxFlowPktCnt),
 299         .cr_portovflcnt = IPATH_CREG_OFFSET(RxP0HdrEgrOvflCnt),
 300         .cr_rcvebpcnt = IPATH_CREG_OFFSET(RxEBPCnt),
 301         .cr_rcvovflcnt = IPATH_CREG_OFFSET(RxBufOvflCnt),
 302         .cr_senddropped = IPATH_CREG_OFFSET(TxDroppedPktCnt),
 303         .cr_sendstallcnt = IPATH_CREG_OFFSET(TxFlowStallCnt),
 304         .cr_sendunderruncnt = IPATH_CREG_OFFSET(TxUnderrunCnt),
 305         .cr_wordrcvcnt = IPATH_CREG_OFFSET(RxDwordCnt),
 306         .cr_wordsendcnt = IPATH_CREG_OFFSET(TxDwordCnt),
 307         .cr_unsupvlcnt = IPATH_CREG_OFFSET(TxUnsupVLErrCnt),
 308         .cr_rxdroppktcnt = IPATH_CREG_OFFSET(RxDroppedPktCnt),
 309         .cr_iblinkerrrecovcnt = IPATH_CREG_OFFSET(IBLinkErrRecoveryCnt),
 310         .cr_iblinkdowncnt = IPATH_CREG_OFFSET(IBLinkDownedCnt),
 311         .cr_ibsymbolerrcnt = IPATH_CREG_OFFSET(IBSymbolErrCnt)
 312 };
 313
 314 /* kr_intstatus, kr_intclear, kr_intmask bits */
 315 #define INFINIPATH_I_RCVURG_MASK ((1U<<5)-1)
 316 #define INFINIPATH_I_RCVAVAIL_MASK ((1U<<5)-1)
 317
 318 /* kr_hwerrclear, kr_hwerrmask, kr_hwerrstatus, bits */
 319 #define INFINIPATH_HWE_PCIEMEMPARITYERR_MASK  0x000000000000003fULL
 320 #define INFINIPATH_HWE_PCIEMEMPARITYERR_SHIFT 0
 321 #define INFINIPATH_HWE_PCIEPOISONEDTLP      0x0000000010000000ULL
 322 #define INFINIPATH_HWE_PCIECPLTIMEOUT       0x0000000020000000ULL
 323 #define INFINIPATH_HWE_PCIEBUSPARITYXTLH    0x0000000040000000ULL
 324 #define INFINIPATH_HWE_PCIEBUSPARITYXADM    0x0000000080000000ULL
 325 #define INFINIPATH_HWE_PCIEBUSPARITYRADM    0x0000000100000000ULL
 326 #define INFINIPATH_HWE_COREPLL_FBSLIP       0x0080000000000000ULL
 327 #define INFINIPATH_HWE_COREPLL_RFSLIP       0x0100000000000000ULL
 328 #define INFINIPATH_HWE_PCIE1PLLFAILED       0x0400000000000000ULL
 329 #define INFINIPATH_HWE_PCIE0PLLFAILED       0x0800000000000000ULL
 330 #define INFINIPATH_HWE_SERDESPLLFAILED      0x1000000000000000ULL
 331
 332 /* kr_extstatus bits */
 333 #define INFINIPATH_EXTS_FREQSEL 0x2
 334 #define INFINIPATH_EXTS_SERDESSEL 0x4
 335 #define INFINIPATH_EXTS_MEMBIST_ENDTEST     0x0000000000004000
 336 #define INFINIPATH_EXTS_MEMBIST_FOUND       0x0000000000008000
 337
 338 #define _IPATH_GPIO_SDA_NUM 1
 339 #define _IPATH_GPIO_SCL_NUM 0
 340
 341 #define IPATH_GPIO_SDA (1ULL << \
 342         (_IPATH_GPIO_SDA_NUM+INFINIPATH_EXTC_GPIOOE_SHIFT))
 343 #define IPATH_GPIO_SCL (1ULL << \
 344         (_IPATH_GPIO_SCL_NUM+INFINIPATH_EXTC_GPIOOE_SHIFT))
 345
 346 #define INFINIPATH_R_INTRAVAIL_SHIFT 16
 347 #define INFINIPATH_R_TAILUPD_SHIFT 31
 348
 349 /* 6120 specific hardware errors... */
 350 static const struct ipath_hwerror_msgs ipath_6120_hwerror_msgs[] = {
 351         INFINIPATH_HWE_MSG(PCIEPOISONEDTLP, "PCIe Poisoned TLP"),
 352         INFINIPATH_HWE_MSG(PCIECPLTIMEOUT, "PCIe completion timeout"),
 353         /*
 354          * In practice, it's unlikely wthat we'll see PCIe PLL, or bus
 355          * parity or memory parity error failures, because most likely we
 356          * won't be able to talk to the core of the chip.  Nonetheless, we
 357          * might see them, if they are in parts of the PCIe core that aren't
 358          * essential.
 359          */
 360         INFINIPATH_HWE_MSG(PCIE1PLLFAILED, "PCIePLL1"),
 361         INFINIPATH_HWE_MSG(PCIE0PLLFAILED, "PCIePLL0"),
 362         INFINIPATH_HWE_MSG(PCIEBUSPARITYXTLH, "PCIe XTLH core parity"),
 363         INFINIPATH_HWE_MSG(PCIEBUSPARITYXADM, "PCIe ADM TX core parity"),
 364         INFINIPATH_HWE_MSG(PCIEBUSPARITYRADM, "PCIe ADM RX core parity"),
 365         INFINIPATH_HWE_MSG(RXDSYNCMEMPARITYERR, "Rx Dsync"),
 366         INFINIPATH_HWE_MSG(SERDESPLLFAILED, "SerDes PLL"),
 367 };
 368
 369 #define TXE_PIO_PARITY ((INFINIPATH_HWE_TXEMEMPARITYERR_PIOBUF | \
 370                         INFINIPATH_HWE_TXEMEMPARITYERR_PIOPBC) \
 371                         << INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT)
 372
 373 static int ipath_pe_txe_recover(struct ipath_devdata *);
 374 static void ipath_pe_put_tid_2(struct ipath_devdata *, u64 __iomem *,
 375                                u32, unsigned long);
 376
 377 /**
 378  * ipath_pe_handle_hwerrors - display hardware errors.
 379  * @dd: the infinipath device
 380  * @msg: the output buffer
 381  * @msgl: the size of the output buffer
 382  *
 383  * Use same msg buffer as regular errors to avoid excessive stack
 384  * use.  Most hardware errors are catastrophic, but for right now,
 385  * we'll print them and continue.  We reuse the same message buffer as
 386  * ipath_handle_errors() to avoid excessive stack usage.
 387  */
 388 static void ipath_pe_handle_hwerrors(struct ipath_devdata *dd, char *msg,
 389                                      size_t msgl)
 390 {
 391         ipath_err_t hwerrs;
 392         u32 bits, ctrl;
 393         int isfatal = 0;
 394         char bitsmsg[64];
 395         int log_idx;
 396
 397         hwerrs = ipath_read_kreg64(dd, dd->ipath_kregs->kr_hwerrstatus);
 398         if (!hwerrs) {
 399                 /*
 400                  * better than printing cofusing messages
 401                  * This seems to be related to clearing the crc error, or
 402                  * the pll error during init.
 403                  */
 404                 ipath_cdbg(VERBOSE, "Called but no hardware errors set\n");
 405                 return;
 406         } else if (hwerrs == ~0ULL) {
 407                 ipath_dev_err(dd, "Read of hardware error status failed "
 408                               "(all bits set); ignoring\n");
 409                 return;
 410         }
 411         ipath_stats.sps_hwerrs++;
 412
 413         /* Always clear the error status register, except MEMBISTFAIL,
 414          * regardless of whether we continue or stop using the chip.
 415          * We want that set so we know it failed, even across driver reload.
 416          * We'll still ignore it in the hwerrmask.  We do this partly for
 417          * diagnostics, but also for support */
 418         ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrclear,
 419                          hwerrs&~INFINIPATH_HWE_MEMBISTFAILED);
 420
 421         hwerrs &= dd->ipath_hwerrmask;
 422
 423         /* We log some errors to EEPROM, check if we have any of those. */
 424         for (log_idx = 0; log_idx < IPATH_EEP_LOG_CNT; ++log_idx)
 425                 if (hwerrs & dd->ipath_eep_st_masks[log_idx].hwerrs_to_log)
 426                         ipath_inc_eeprom_err(dd, log_idx, 1);
 427
 428         /*
 429          * make sure we get this much out, unless told to be quiet,
 430          * or it's occurred within the last 5 seconds
 431          */
 432         if ((hwerrs & ~(dd->ipath_lasthwerror |
 433                         ((INFINIPATH_HWE_TXEMEMPARITYERR_PIOBUF |
 434                           INFINIPATH_HWE_TXEMEMPARITYERR_PIOPBC)
 435                          << INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT))) ||
 436             (ipath_debug & __IPATH_VERBDBG))
 437                 dev_info(&dd->pcidev->dev, "Hardware error: hwerr=0x%llx "
 438                          "(cleared)\n", (unsigned long long) hwerrs);
 439         dd->ipath_lasthwerror |= hwerrs;
 440
 441         if (hwerrs & ~dd->ipath_hwe_bitsextant)
 442                 ipath_dev_err(dd, "hwerror interrupt with unknown errors "
 443                               "%llx set\n", (unsigned long long)
 444                               (hwerrs & ~dd->ipath_hwe_bitsextant));
 445
 446         ctrl = ipath_read_kreg32(dd, dd->ipath_kregs->kr_control);
 447         if (ctrl & INFINIPATH_C_FREEZEMODE) {
 448                 /*
 449                  * parity errors in send memory are recoverable,
 450                  * just cancel the send (if indicated in * sendbuffererror),
 451                  * count the occurrence, unfreeze (if no other handled
 452                  * hardware error bits are set), and continue. They can
 453                  * occur if a processor speculative read is done to the PIO
 454                  * buffer while we are sending a packet, for example.
 455                  */
 456                 if ((hwerrs & TXE_PIO_PARITY) && ipath_pe_txe_recover(dd))
 457                         hwerrs &= ~TXE_PIO_PARITY;
 458                 if (hwerrs) {
 459                         /*
 460                          * if any set that we aren't ignoring only make the
 461                          * complaint once, in case it's stuck or recurring,
 462                          * and we get here multiple times
 463                          * Force link down, so switch knows, and
 464                          * LEDs are turned off
 465                          */
 466                         if (dd->ipath_flags & IPATH_INITTED) {
 467                                 ipath_set_linkstate(dd, IPATH_IB_LINKDOWN);
 468                                 ipath_setup_pe_setextled(dd,
 469                                         INFINIPATH_IBCS_L_STATE_DOWN,
 470                                         INFINIPATH_IBCS_LT_STATE_DISABLED);
 471                                 ipath_dev_err(dd, "Fatal Hardware Error (freeze "
 472                                               "mode), no longer usable, SN %.16s\n",
 473                                                   dd->ipath_serial);
 474                                 isfatal = 1;
 475                         }
 476                         /*
 477                          * Mark as having had an error for driver, and also
 478                          * for /sys and status word mapped to user programs.
 479                          * This marks unit as not usable, until reset
 480                          */
 481                         *dd->ipath_statusp &= ~IPATH_STATUS_IB_READY;
 482                         *dd->ipath_statusp |= IPATH_STATUS_HWERROR;
 483                         dd->ipath_flags &= ~IPATH_INITTED;
 484                 } else {
 485                         static u32 freeze_cnt;
 486
 487                         freeze_cnt++;
 488                         ipath_dbg("Clearing freezemode on ignored or recovered "
 489                                   "hardware error (%u)\n", freeze_cnt);
 490                         ipath_clear_freeze(dd);
 491                 }
 492         }
 493
 494         *msg = '\0';
 495
 496         if (hwerrs & INFINIPATH_HWE_MEMBISTFAILED) {
 497                 strlcat(msg, "[Memory BIST test failed, InfiniPath hardware unusable]",
 498                         msgl);
 499                 /* ignore from now on, so disable until driver reloaded */
 500                 *dd->ipath_statusp |= IPATH_STATUS_HWERROR;
 501                 dd->ipath_hwerrmask &= ~INFINIPATH_HWE_MEMBISTFAILED;
 502                 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask,
 503                                  dd->ipath_hwerrmask);
 504         }
 505
 506         ipath_format_hwerrors(hwerrs,
 507                               ipath_6120_hwerror_msgs,
 508                               sizeof(ipath_6120_hwerror_msgs)/
 509                               sizeof(ipath_6120_hwerror_msgs[0]),
 510                               msg, msgl);
 511
 512         if (hwerrs & (INFINIPATH_HWE_PCIEMEMPARITYERR_MASK
 513                       << INFINIPATH_HWE_PCIEMEMPARITYERR_SHIFT)) {
 514                 bits = (u32) ((hwerrs >>
 515                                INFINIPATH_HWE_PCIEMEMPARITYERR_SHIFT) &
 516                               INFINIPATH_HWE_PCIEMEMPARITYERR_MASK);
 517                 snprintf(bitsmsg, sizeof bitsmsg,
 518                          "[PCIe Mem Parity Errs %x] ", bits);
 519                 strlcat(msg, bitsmsg, msgl);
 520         }
 521
 522 #define _IPATH_PLL_FAIL (INFINIPATH_HWE_COREPLL_FBSLIP |        \
 523                          INFINIPATH_HWE_COREPLL_RFSLIP )
 524
 525         if (hwerrs & _IPATH_PLL_FAIL) {
 526                 snprintf(bitsmsg, sizeof bitsmsg,
 527                          "[PLL failed (%llx), InfiniPath hardware unusable]",
 528                          (unsigned long long) hwerrs & _IPATH_PLL_FAIL);
 529                 strlcat(msg, bitsmsg, msgl);
 530                 /* ignore from now on, so disable until driver reloaded */
 531                 dd->ipath_hwerrmask &= ~(hwerrs & _IPATH_PLL_FAIL);
 532                 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask,
 533                                  dd->ipath_hwerrmask);
 534         }
 535
 536         if (hwerrs & INFINIPATH_HWE_SERDESPLLFAILED) {
 537                 /*
 538                  * If it occurs, it is left masked since the external
 539                  * interface is unused
 540                  */
 541                 dd->ipath_hwerrmask &= ~INFINIPATH_HWE_SERDESPLLFAILED;
 542                 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask,
 543                                  dd->ipath_hwerrmask);
 544         }
 545
 546         if (*msg)
 547                 ipath_dev_err(dd, "%s hardware error\n", msg);
 548         if (isfatal && !ipath_diag_inuse && dd->ipath_freezemsg) {
 549                 /*
 550                  * for /sys status file ; if no trailing } is copied, we'll
 551                  * know it was truncated.
 552                  */
 553                 snprintf(dd->ipath_freezemsg, dd->ipath_freezelen,
 554                          "{%s}", msg);
 555         }
 556 }
 557
 558 /**
 559  * ipath_pe_boardname - fill in the board name
 560  * @dd: the infinipath device
 561  * @name: the output buffer
 562  * @namelen: the size of the output buffer
 563  *
 564  * info is based on the board revision register
 565  */
 566 static int ipath_pe_boardname(struct ipath_devdata *dd, char *name,
 567                               size_t namelen)
 568 {
 569         char *n = NULL;
 570         u8 boardrev = dd->ipath_boardrev;
 571         int ret;
 572
 573         switch (boardrev) {
 574         case 0:
 575                 n = "InfiniPath_Emulation";
 576                 break;
 577         case 1:
 578                 n = "InfiniPath_QLE7140-Bringup";
 579                 break;
 580         case 2:
 581                 n = "InfiniPath_QLE7140";
 582                 break;
 583         case 3:
 584                 n = "InfiniPath_QMI7140";
 585                 break;
 586         case 4:
 587                 n = "InfiniPath_QEM7140";
 588                 break;
 589         case 5:
 590                 n = "InfiniPath_QMH7140";
 591                 break;
 592         case 6:
 593                 n = "InfiniPath_QLE7142";
 594                 break;
 595         default:
 596                 ipath_dev_err(dd,
 597                               "Don't yet know about board with ID %u\n",
 598                               boardrev);
 599                 snprintf(name, namelen, "Unknown_InfiniPath_PCIe_%u",
 600                          boardrev);
 601                 break;
 602         }
 603         if (n)
 604                 snprintf(name, namelen, "%s", n);
 605
 606         if (dd->ipath_majrev != 4 || !dd->ipath_minrev || dd->ipath_minrev>2) {
 607                 ipath_dev_err(dd, "Unsupported InfiniPath hardware revision %u.%u!\n",
 608                               dd->ipath_majrev, dd->ipath_minrev);
 609                 ret = 1;
 610         } else {
 611                 ret = 0;
 612                 if (dd->ipath_minrev >= 2)
 613                         dd->ipath_f_put_tid = ipath_pe_put_tid_2;
 614         }
 615
 616
 617         /*
 618          * set here, not in ipath_init_*_funcs because we have to do
 619          * it after we can read chip registers.
 620          */
 621         dd->ipath_ureg_align =
 622                 ipath_read_kreg32(dd, dd->ipath_kregs->kr_pagealign);
 623
 624         return ret;
 625 }
 626
 627 /**
 628  * ipath_pe_init_hwerrors - enable hardware errors
 629  * @dd: the infinipath device
 630  *
 631  * now that we have finished initializing everything that might reasonably
 632  * cause a hardware error, and cleared those errors bits as they occur,
 633  * we can enable hardware errors in the mask (potentially enabling
 634  * freeze mode), and enable hardware errors as errors (along with
 635  * everything else) in errormask
 636  */
 637 static void ipath_pe_init_hwerrors(struct ipath_devdata *dd)
 638 {
 639         ipath_err_t val;
 640         u64 extsval;
 641
 642         extsval = ipath_read_kreg64(dd, dd->ipath_kregs->kr_extstatus);
 643
 644         if (!(extsval & INFINIPATH_EXTS_MEMBIST_ENDTEST))
 645                 ipath_dev_err(dd, "MemBIST did not complete!\n");
 646         if (extsval & INFINIPATH_EXTS_MEMBIST_FOUND)
 647                 ipath_dbg("MemBIST corrected\n");
 648
 649         val = ~0ULL;    /* barring bugs, all hwerrors become interrupts, */
 650
 651         if (!dd->ipath_boardrev)        // no PLL for Emulator
 652                 val &= ~INFINIPATH_HWE_SERDESPLLFAILED;
 653
 654         if (dd->ipath_minrev < 2) {
 655                 /* workaround bug 9460 in internal interface bus parity
 656                  * checking. Fixed (HW bug 9490) in Rev2.
 657                  */
 658                 val &= ~INFINIPATH_HWE_PCIEBUSPARITYRADM;
 659         }
 660         dd->ipath_hwerrmask = val;
 661 }
 662
 663 /**
 664  * ipath_pe_bringup_serdes - bring up the serdes
 665  * @dd: the infinipath device
 666  */
 667 static int ipath_pe_bringup_serdes(struct ipath_devdata *dd)
 668 {
 669         u64 val, config1, prev_val;
 670         int ret = 0;
 671
 672         ipath_dbg("Trying to bringup serdes\n");
 673
 674         if (ipath_read_kreg64(dd, dd->ipath_kregs->kr_hwerrstatus) &
 675             INFINIPATH_HWE_SERDESPLLFAILED) {
 676                 ipath_dbg("At start, serdes PLL failed bit set "
 677                           "in hwerrstatus, clearing and continuing\n");
 678                 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrclear,
 679                                  INFINIPATH_HWE_SERDESPLLFAILED);
 680         }
 681
 682         val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesconfig0);
 683         config1 = ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesconfig1);
 684
 685         ipath_cdbg(VERBOSE, "SerDes status config0=%llx config1=%llx, "
 686                    "xgxsconfig %llx\n", (unsigned long long) val,
 687                    (unsigned long long) config1, (unsigned long long)
 688                    ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig));
 689
 690         /*
 691          * Force reset on, also set rxdetect enable.  Must do before reading
 692          * serdesstatus at least for simulation, or some of the bits in
 693          * serdes status will come back as undefined and cause simulation
 694          * failures
 695          */
 696         val |= INFINIPATH_SERDC0_RESET_PLL | INFINIPATH_SERDC0_RXDETECT_EN
 697                 | INFINIPATH_SERDC0_L1PWR_DN;
 698         ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig0, val);
 699         /* be sure chip saw it */
 700         ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
 701         udelay(5);              /* need pll reset set at least for a bit */
 702         /*
 703          * after PLL is reset, set the per-lane Resets and TxIdle and
 704          * clear the PLL reset and rxdetect (to get falling edge).
 705          * Leave L1PWR bits set (permanently)
 706          */
 707         val &= ~(INFINIPATH_SERDC0_RXDETECT_EN | INFINIPATH_SERDC0_RESET_PLL
 708                  | INFINIPATH_SERDC0_L1PWR_DN);
 709         val |= INFINIPATH_SERDC0_RESET_MASK | INFINIPATH_SERDC0_TXIDLE;
 710         ipath_cdbg(VERBOSE, "Clearing pll reset and setting lane resets "
 711                    "and txidle (%llx)\n", (unsigned long long) val);
 712         ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig0, val);
 713         /* be sure chip saw it */
 714         ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
 715         /* need PLL reset clear for at least 11 usec before lane
 716          * resets cleared; give it a few more to be sure */
 717         udelay(15);
 718         val &= ~(INFINIPATH_SERDC0_RESET_MASK | INFINIPATH_SERDC0_TXIDLE);
 719
 720         ipath_cdbg(VERBOSE, "Clearing lane resets and txidle "
 721                    "(writing %llx)\n", (unsigned long long) val);
 722         ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig0, val);
 723         /* be sure chip saw it */
 724         val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
 725
 726         val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig);
 727         prev_val = val;
 728         if (((val >> INFINIPATH_XGXS_MDIOADDR_SHIFT) &
 729              INFINIPATH_XGXS_MDIOADDR_MASK) != 3) {
 730                 val &=
 731                         ~(INFINIPATH_XGXS_MDIOADDR_MASK <<
 732                           INFINIPATH_XGXS_MDIOADDR_SHIFT);
 733                 /* MDIO address 3 */
 734                 val |= 3ULL << INFINIPATH_XGXS_MDIOADDR_SHIFT;
 735         }
 736         if (val & INFINIPATH_XGXS_RESET) {
 737                 val &= ~INFINIPATH_XGXS_RESET;
 738         }
 739         if (((val >> INFINIPATH_XGXS_RX_POL_SHIFT) &
 740              INFINIPATH_XGXS_RX_POL_MASK) != dd->ipath_rx_pol_inv ) {
 741                 /* need to compensate for Tx inversion in partner */
 742                 val &= ~(INFINIPATH_XGXS_RX_POL_MASK <<
 743                          INFINIPATH_XGXS_RX_POL_SHIFT);
 744                 val |= dd->ipath_rx_pol_inv <<
 745                         INFINIPATH_XGXS_RX_POL_SHIFT;
 746         }
 747         if (val != prev_val)
 748                 ipath_write_kreg(dd, dd->ipath_kregs->kr_xgxsconfig, val);
 749
 750         val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesconfig0);
 751
 752         /* clear current and de-emphasis bits */
 753         config1 &= ~0x0ffffffff00ULL;
 754         /* set current to 20ma */
 755         config1 |= 0x00000000000ULL;
 756         /* set de-emphasis to -5.68dB */
 757         config1 |= 0x0cccc000000ULL;
 758         ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig1, config1);
 759
 760         ipath_cdbg(VERBOSE, "done: SerDes status config0=%llx "
 761                    "config1=%llx, sstatus=%llx xgxs=%llx\n",
 762                    (unsigned long long) val, (unsigned long long) config1,
 763                    (unsigned long long)
 764                    ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesstatus),
 765                    (unsigned long long)
 766                    ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig));
 767
 768         if (!ipath_waitfor_mdio_cmdready(dd)) {
 769                 ipath_write_kreg(
 770                         dd, dd->ipath_kregs->kr_mdio,
 771                         ipath_mdio_req(IPATH_MDIO_CMD_READ, 31,
 772                                        IPATH_MDIO_CTRL_XGXS_REG_8, 0));
 773                 if (ipath_waitfor_complete(dd, dd->ipath_kregs->kr_mdio,
 774                                            IPATH_MDIO_DATAVALID, &val))
 775                         ipath_dbg("Never got MDIO data for XGXS "
 776                                   "status read\n");
 777                 else
 778                         ipath_cdbg(VERBOSE, "MDIO Read reg8, "
 779                                    "'bank' 31 %x\n", (u32) val);
 780         } else
 781                 ipath_dbg("Never got MDIO cmdready for XGXS status read\n");
 782
 783         return ret;
 784 }
 785
 786 /**
 787  * ipath_pe_quiet_serdes - set serdes to txidle
 788  * @dd: the infinipath device
 789  * Called when driver is being unloaded
 790  */
 791 static void ipath_pe_quiet_serdes(struct ipath_devdata *dd)
 792 {
 793         u64 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesconfig0);
 794
 795         val |= INFINIPATH_SERDC0_TXIDLE;
 796         ipath_dbg("Setting TxIdleEn on serdes (config0 = %llx)\n",
 797                   (unsigned long long) val);
 798         ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig0, val);
 799 }
 800
 801 static int ipath_pe_intconfig(struct ipath_devdata *dd)
 802 {
 803         u32 chiprev;
 804
 805         /*
 806          * If the chip supports added error indication via GPIO pins,
 807          * enable interrupts on those bits so the interrupt routine
 808          * can count the events. Also set flag so interrupt routine
 809          * can know they are expected.
 810          */
 811         chiprev = dd->ipath_revision >> INFINIPATH_R_CHIPREVMINOR_SHIFT;
 812         if ((chiprev & INFINIPATH_R_CHIPREVMINOR_MASK) > 1) {
 813                 /* Rev2+ reports extra errors via internal GPIO pins */
 814                 dd->ipath_flags |= IPATH_GPIO_ERRINTRS;
 815                 dd->ipath_gpio_mask |= IPATH_GPIO_ERRINTR_MASK;
 816                 ipath_write_kreg(dd, dd->ipath_kregs->kr_gpio_mask,
 817                                  dd->ipath_gpio_mask);
 818         }
 819         return 0;
 820 }
 821
 822 /**
 823  * ipath_setup_pe_setextled - set the state of the two external LEDs
 824  * @dd: the infinipath device
 825  * @lst: the L state
 826  * @ltst: the LT state
 827
 828  * These LEDs indicate the physical and logical state of IB link.
 829  * For this chip (at least with recommended board pinouts), LED1
 830  * is Yellow (logical state) and LED2 is Green (physical state),
 831  *
 832  * Note:  We try to match the Mellanox HCA LED behavior as best
 833  * we can.  Green indicates physical link state is OK (something is
 834  * plugged in, and we can train).
 835  * Amber indicates the link is logically up (ACTIVE).
 836  * Mellanox further blinks the amber LED to indicate data packet
 837  * activity, but we have no hardware support for that, so it would
 838  * require waking up every 10-20 msecs and checking the counters
 839  * on the chip, and then turning the LED off if appropriate.  That's
 840  * visible overhead, so not something we will do.
 841  *
 842  */
 843 static void ipath_setup_pe_setextled(struct ipath_devdata *dd, u64 lst,
 844                                      u64 ltst)
 845 {
 846         u64 extctl;
 847         unsigned long flags = 0;
 848
 849         /* the diags use the LED to indicate diag info, so we leave
 850          * the external LED alone when the diags are running */
 851         if (ipath_diag_inuse)
 852                 return;
 853
 854         /* Allow override of LED display for, e.g. Locating system in rack */
 855         if (dd->ipath_led_override) {
 856                 ltst = (dd->ipath_led_override & IPATH_LED_PHYS)
 857                         ? INFINIPATH_IBCS_LT_STATE_LINKUP
 858                         : INFINIPATH_IBCS_LT_STATE_DISABLED;
 859                 lst = (dd->ipath_led_override & IPATH_LED_LOG)
 860                         ? INFINIPATH_IBCS_L_STATE_ACTIVE
 861                         : INFINIPATH_IBCS_L_STATE_DOWN;
 862         }
 863
 864         spin_lock_irqsave(&dd->ipath_gpio_lock, flags);
 865         extctl = dd->ipath_extctrl & ~(INFINIPATH_EXTC_LED1PRIPORT_ON |
 866                                        INFINIPATH_EXTC_LED2PRIPORT_ON);
 867
 868         if (ltst & INFINIPATH_IBCS_LT_STATE_LINKUP)
 869                 extctl |= INFINIPATH_EXTC_LED2PRIPORT_ON;
 870         if (lst == INFINIPATH_IBCS_L_STATE_ACTIVE)
 871                 extctl |= INFINIPATH_EXTC_LED1PRIPORT_ON;
 872         dd->ipath_extctrl = extctl;
 873         ipath_write_kreg(dd, dd->ipath_kregs->kr_extctrl, extctl);
 874         spin_unlock_irqrestore(&dd->ipath_gpio_lock, flags);
 875 }
 876
 877 /**
 878  * ipath_setup_pe_cleanup - clean up any per-chip chip-specific stuff
 879  * @dd: the infinipath device
 880  *
 881  * This is called during driver unload.
 882  * We do the pci_disable_msi here, not in generic code, because it
 883  * isn't used for the HT chips. If we do end up needing pci_enable_msi
 884  * at some point in the future for HT, we'll move the call back
 885  * into the main init_one code.
 886  */
 887 static void ipath_setup_pe_cleanup(struct ipath_devdata *dd)
 888 {
 889         dd->ipath_msi_lo = 0;   /* just in case unload fails */
 890         pci_disable_msi(dd->pcidev);
 891 }
 892
 893 /**
 894  * ipath_setup_pe_config - setup PCIe config related stuff
 895  * @dd: the infinipath device
 896  * @pdev: the PCI device
 897  *
 898  * The pci_enable_msi() call will fail on systems with MSI quirks
 899  * such as those with AMD8131, even if the device of interest is not
 900  * attached to that device, (in the 2.6.13 - 2.6.15 kernels, at least, fixed
 901  * late in 2.6.16).
 902  * All that can be done is to edit the kernel source to remove the quirk
 903  * check until that is fixed.
 904  * We do not need to call enable_msi() for our HyperTransport chip,
 905  * even though it uses MSI, and we want to avoid the quirk warning, so
 906  * So we call enable_msi only for PCIe.  If we do end up needing
 907  * pci_enable_msi at some point in the future for HT, we'll move the
 908  * call back into the main init_one code.
 909  * We save the msi lo and hi values, so we can restore them after
 910  * chip reset (the kernel PCI infrastructure doesn't yet handle that
 911  * correctly).
 912  */
 913 static int ipath_setup_pe_config(struct ipath_devdata *dd,
 914                                  struct pci_dev *pdev)
 915 {
 916         int pos, ret;
 917
 918         dd->ipath_msi_lo = 0;   /* used as a flag during reset processing */
 919         ret = pci_enable_msi(dd->pcidev);
 920         if (ret)
 921                 ipath_dev_err(dd, "pci_enable_msi failed: %d, "
 922                               "interrupts may not work\n", ret);
 923         /* continue even if it fails, we may still be OK... */
 924         dd->ipath_irq = pdev->irq;
 925
 926         if ((pos = pci_find_capability(dd->pcidev, PCI_CAP_ID_MSI))) {
 927                 u16 control;
 928                 pci_read_config_dword(dd->pcidev, pos + PCI_MSI_ADDRESS_LO,
 929                                       &dd->ipath_msi_lo);
 930                 pci_read_config_dword(dd->pcidev, pos + PCI_MSI_ADDRESS_HI,
 931                                       &dd->ipath_msi_hi);
 932                 pci_read_config_word(dd->pcidev, pos + PCI_MSI_FLAGS,
 933                                      &control);
 934                 /* now save the data (vector) info */
 935                 pci_read_config_word(dd->pcidev,
 936                                      pos + ((control & PCI_MSI_FLAGS_64BIT)
 937                                             ? 12 : 8),
 938                                      &dd->ipath_msi_data);
 939                 ipath_cdbg(VERBOSE, "Read msi data 0x%x from config offset "
 940                            "0x%x, control=0x%x\n", dd->ipath_msi_data,
 941                            pos + ((control & PCI_MSI_FLAGS_64BIT) ? 12 : 8),
 942                            control);
 943                 /* we save the cachelinesize also, although it doesn't
 944                  * really matter */
 945                 pci_read_config_byte(dd->pcidev, PCI_CACHE_LINE_SIZE,
 946                                      &dd->ipath_pci_cacheline);
 947         } else
 948                 ipath_dev_err(dd, "Can't find MSI capability, "
 949                               "can't save MSI settings for reset\n");
 950         if ((pos = pci_find_capability(dd->pcidev, PCI_CAP_ID_EXP))) {
 951                 u16 linkstat;
 952                 pci_read_config_word(dd->pcidev, pos + PCI_EXP_LNKSTA,
 953                                      &linkstat);
 954                 linkstat >>= 4;
 955                 linkstat &= 0x1f;
 956                 if (linkstat != 8)
 957                         ipath_dev_err(dd, "PCIe width %u, "
 958                                       "performance reduced\n", linkstat);
 959         }
 960         else
 961                 ipath_dev_err(dd, "Can't find PCI Express "
 962                               "capability!\n");
 963         return 0;
 964 }
 965
 966 static void ipath_init_pe_variables(struct ipath_devdata *dd)
 967 {
 968         /*
 969          * bits for selecting i2c direction and values,
 970          * used for I2C serial flash
 971          */
 972         dd->ipath_gpio_sda_num = _IPATH_GPIO_SDA_NUM;
 973         dd->ipath_gpio_scl_num = _IPATH_GPIO_SCL_NUM;
 974         dd->ipath_gpio_sda = IPATH_GPIO_SDA;
 975         dd->ipath_gpio_scl = IPATH_GPIO_SCL;
 976
 977         /* Fill in shifts for RcvCtrl. */
 978         dd->ipath_r_portenable_shift = INFINIPATH_R_PORTENABLE_SHIFT;
 979         dd->ipath_r_intravail_shift = INFINIPATH_R_INTRAVAIL_SHIFT;
 980         dd->ipath_r_tailupd_shift = INFINIPATH_R_TAILUPD_SHIFT;
 981         dd->ipath_r_portcfg_shift = 0; /* Not on IBA6120 */
 982
 983         /* variables for sanity checking interrupt and errors */
 984         dd->ipath_hwe_bitsextant =
 985                 (INFINIPATH_HWE_RXEMEMPARITYERR_MASK <<
 986                  INFINIPATH_HWE_RXEMEMPARITYERR_SHIFT) |
 987                 (INFINIPATH_HWE_TXEMEMPARITYERR_MASK <<
 988                  INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT) |
 989                 (INFINIPATH_HWE_PCIEMEMPARITYERR_MASK <<
 990                  INFINIPATH_HWE_PCIEMEMPARITYERR_SHIFT) |
 991                 INFINIPATH_HWE_PCIE1PLLFAILED |
 992                 INFINIPATH_HWE_PCIE0PLLFAILED |
 993                 INFINIPATH_HWE_PCIEPOISONEDTLP |
 994                 INFINIPATH_HWE_PCIECPLTIMEOUT |
 995                 INFINIPATH_HWE_PCIEBUSPARITYXTLH |
 996                 INFINIPATH_HWE_PCIEBUSPARITYXADM |
 997                 INFINIPATH_HWE_PCIEBUSPARITYRADM |
 998                 INFINIPATH_HWE_MEMBISTFAILED |
 999                 INFINIPATH_HWE_COREPLL_FBSLIP |
1000                 INFINIPATH_HWE_COREPLL_RFSLIP |
1001                 INFINIPATH_HWE_SERDESPLLFAILED |
1002                 INFINIPATH_HWE_IBCBUSTOSPCPARITYERR |
1003                 INFINIPATH_HWE_IBCBUSFRSPCPARITYERR;
1004         dd->ipath_i_bitsextant =
1005                 (INFINIPATH_I_RCVURG_MASK << INFINIPATH_I_RCVURG_SHIFT) |
1006                 (INFINIPATH_I_RCVAVAIL_MASK <<
1007                  INFINIPATH_I_RCVAVAIL_SHIFT) |
1008                 INFINIPATH_I_ERROR | INFINIPATH_I_SPIOSENT |
1009                 INFINIPATH_I_SPIOBUFAVAIL | INFINIPATH_I_GPIO;
1010         dd->ipath_e_bitsextant =
1011                 INFINIPATH_E_RFORMATERR | INFINIPATH_E_RVCRC |
1012                 INFINIPATH_E_RICRC | INFINIPATH_E_RMINPKTLEN |
1013                 INFINIPATH_E_RMAXPKTLEN | INFINIPATH_E_RLONGPKTLEN |
1014                 INFINIPATH_E_RSHORTPKTLEN | INFINIPATH_E_RUNEXPCHAR |
1015                 INFINIPATH_E_RUNSUPVL | INFINIPATH_E_REBP |
1016                 INFINIPATH_E_RIBFLOW | INFINIPATH_E_RBADVERSION |
1017                 INFINIPATH_E_RRCVEGRFULL | INFINIPATH_E_RRCVHDRFULL |
1018                 INFINIPATH_E_RBADTID | INFINIPATH_E_RHDRLEN |
1019                 INFINIPATH_E_RHDR | INFINIPATH_E_RIBLOSTLINK |
1020                 INFINIPATH_E_SMINPKTLEN | INFINIPATH_E_SMAXPKTLEN |
1021                 INFINIPATH_E_SUNDERRUN | INFINIPATH_E_SPKTLEN |
1022                 INFINIPATH_E_SDROPPEDSMPPKT | INFINIPATH_E_SDROPPEDDATAPKT |
1023                 INFINIPATH_E_SPIOARMLAUNCH | INFINIPATH_E_SUNEXPERRPKTNUM |
1024                 INFINIPATH_E_SUNSUPVL | INFINIPATH_E_IBSTATUSCHANGED |
1025                 INFINIPATH_E_INVALIDADDR | INFINIPATH_E_RESET |
1026                 INFINIPATH_E_HARDWARE;
1027
1028         dd->ipath_i_rcvavail_mask = INFINIPATH_I_RCVAVAIL_MASK;
1029         dd->ipath_i_rcvurg_mask = INFINIPATH_I_RCVURG_MASK;
1030
1031         /*
1032          * EEPROM error log 0 is TXE Parity errors. 1 is RXE Parity.
1033          * 2 is Some Misc, 3 is reserved for future.
1034          */
1035         dd->ipath_eep_st_masks[0].hwerrs_to_log =
1036                 INFINIPATH_HWE_TXEMEMPARITYERR_MASK <<
1037                 INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT;
1038
1039         /* Ignore errors in PIO/PBC on systems with unordered write-combining */
1040         if (ipath_unordered_wc())
1041                 dd->ipath_eep_st_masks[0].hwerrs_to_log &= ~TXE_PIO_PARITY;
1042
1043         dd->ipath_eep_st_masks[1].hwerrs_to_log =
1044                 INFINIPATH_HWE_RXEMEMPARITYERR_MASK <<
1045                 INFINIPATH_HWE_RXEMEMPARITYERR_SHIFT;
1046
1047         dd->ipath_eep_st_masks[2].errs_to_log =
1048                 INFINIPATH_E_INVALIDADDR | INFINIPATH_E_RESET;
1049
1050
1051 }
1052
1053 /* setup the MSI stuff again after a reset.  I'd like to just call
1054  * pci_enable_msi() and request_irq() again, but when I do that,
1055  * the MSI enable bit doesn't get set in the command word, and
1056  * we switch to to a different interrupt vector, which is confusing,
1057  * so I instead just do it all inline.  Perhaps somehow can tie this
1058  * into the PCIe hotplug support at some point
1059  * Note, because I'm doing it all here, I don't call pci_disable_msi()
1060  * or free_irq() at the start of ipath_setup_pe_reset().
1061  */
1062 static int ipath_reinit_msi(struct ipath_devdata *dd)
1063 {
1064         int pos;
1065         u16 control;
1066         int ret;
1067
1068         if (!dd->ipath_msi_lo) {
1069                 dev_info(&dd->pcidev->dev, "Can't restore MSI config, "
1070                          "initial setup failed?\n");
1071                 ret = 0;
1072                 goto bail;
1073         }
1074
1075         if (!(pos = pci_find_capability(dd->pcidev, PCI_CAP_ID_MSI))) {
1076                 ipath_dev_err(dd, "Can't find MSI capability, "
1077                               "can't restore MSI settings\n");
1078                 ret = 0;
1079                 goto bail;
1080         }
1081         ipath_cdbg(VERBOSE, "Writing msi_lo 0x%x to config offset 0x%x\n",
1082                    dd->ipath_msi_lo, pos + PCI_MSI_ADDRESS_LO);
1083         pci_write_config_dword(dd->pcidev, pos + PCI_MSI_ADDRESS_LO,
1084                                dd->ipath_msi_lo);
1085         ipath_cdbg(VERBOSE, "Writing msi_lo 0x%x to config offset 0x%x\n",
1086                    dd->ipath_msi_hi, pos + PCI_MSI_ADDRESS_HI);
1087         pci_write_config_dword(dd->pcidev, pos + PCI_MSI_ADDRESS_HI,
1088                                dd->ipath_msi_hi);
1089         pci_read_config_word(dd->pcidev, pos + PCI_MSI_FLAGS, &control);
1090         if (!(control & PCI_MSI_FLAGS_ENABLE)) {
1091                 ipath_cdbg(VERBOSE, "MSI control at off %x was %x, "
1092                            "setting MSI enable (%x)\n", pos + PCI_MSI_FLAGS,
1093                            control, control | PCI_MSI_FLAGS_ENABLE);
1094                 control |= PCI_MSI_FLAGS_ENABLE;
1095                 pci_write_config_word(dd->pcidev, pos + PCI_MSI_FLAGS,
1096                                       control);
1097         }
1098         /* now rewrite the data (vector) info */
1099         pci_write_config_word(dd->pcidev, pos +
1100                               ((control & PCI_MSI_FLAGS_64BIT) ? 12 : 8),
1101                               dd->ipath_msi_data);
1102         /* we restore the cachelinesize also, although it doesn't really
1103          * matter */
1104         pci_write_config_byte(dd->pcidev, PCI_CACHE_LINE_SIZE,
1105                               dd->ipath_pci_cacheline);
1106         /* and now set the pci master bit again */
1107         pci_set_master(dd->pcidev);
1108         ret = 1;
1109
1110 bail:
1111         return ret;
1112 }
1113
1114 /* This routine sleeps, so it can only be called from user context, not
1115  * from interrupt context.  If we need interrupt context, we can split
1116  * it into two routines.
1117 */
1118 static int ipath_setup_pe_reset(struct ipath_devdata *dd)
1119 {
1120         u64 val;
1121         int i;
1122         int ret;
1123
1124         /* Use ERROR so it shows up in logs, etc. */
1125         ipath_dev_err(dd, "Resetting InfiniPath unit %u\n", dd->ipath_unit);
1126         /* keep chip from being accessed in a few places */
1127         dd->ipath_flags &= ~(IPATH_INITTED|IPATH_PRESENT);
1128         val = dd->ipath_control | INFINIPATH_C_RESET;
1129         ipath_write_kreg(dd, dd->ipath_kregs->kr_control, val);
1130         mb();
1131
1132         for (i = 1; i <= 5; i++) {
1133                 int r;
1134                 /* allow MBIST, etc. to complete; longer on each retry.
1135                  * We sometimes get machine checks from bus timeout if no
1136                  * response, so for now, make it *really* long.
1137                  */
1138                 msleep(1000 + (1 + i) * 2000);
1139                 if ((r =
1140                      pci_write_config_dword(dd->pcidev, PCI_BASE_ADDRESS_0,
1141                                             dd->ipath_pcibar0)))
1142                         ipath_dev_err(dd, "rewrite of BAR0 failed: %d\n",
1143                                       r);
1144                 if ((r =
1145                      pci_write_config_dword(dd->pcidev, PCI_BASE_ADDRESS_1,
1146                                             dd->ipath_pcibar1)))
1147                         ipath_dev_err(dd, "rewrite of BAR1 failed: %d\n",
1148                                       r);
1149                 /* now re-enable memory access */
1150                 if ((r = pci_enable_device(dd->pcidev)))
1151                         ipath_dev_err(dd, "pci_enable_device failed after "
1152                                       "reset: %d\n", r);
1153                 /* whether it worked or not, mark as present, again */
1154                 dd->ipath_flags |= IPATH_PRESENT;
1155                 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_revision);
1156                 if (val == dd->ipath_revision) {
1157                         ipath_cdbg(VERBOSE, "Got matching revision "
1158                                    "register %llx on try %d\n",
1159                                    (unsigned long long) val, i);
1160                         ret = ipath_reinit_msi(dd);
1161                         goto bail;
1162                 }
1163                 /* Probably getting -1 back */
1164                 ipath_dbg("Didn't get expected revision register, "
1165                           "got %llx, try %d\n", (unsigned long long) val,
1166                           i + 1);
1167         }
1168         ret = 0; /* failed */
1169
1170 bail:
1171         return ret;
1172 }
1173
1174 /**
1175  * ipath_pe_put_tid - write a TID in chip
1176  * @dd: the infinipath device
1177  * @tidptr: pointer to the expected TID (in chip) to udpate
1178  * @tidtype: RCVHQ_RCV_TYPE_EAGER (1) for eager, RCVHQ_RCV_TYPE_EXPECTED (0) for expected
1179  * @pa: physical address of in memory buffer; ipath_tidinvalid if freeing
1180  *
1181  * This exists as a separate routine to allow for special locking etc.
1182  * It's used for both the full cleanup on exit, as well as the normal
1183  * setup and teardown.
1184  */
1185 static void ipath_pe_put_tid(struct ipath_devdata *dd, u64 __iomem *tidptr,
1186                              u32 type, unsigned long pa)
1187 {
1188         u32 __iomem *tidp32 = (u32 __iomem *)tidptr;
1189         unsigned long flags = 0; /* keep gcc quiet */
1190
1191         if (pa != dd->ipath_tidinvalid) {
1192                 if (pa & ((1U << 11) - 1)) {
1193                         dev_info(&dd->pcidev->dev, "BUG: physaddr %lx "
1194                                  "not 4KB aligned!\n", pa);
1195                         return;
1196                 }
1197                 pa >>= 11;
1198                 /* paranoia check */
1199                 if (pa & (7<<29))
1200                         ipath_dev_err(dd,
1201                                       "BUG: Physical page address 0x%lx "
1202                                       "has bits set in 31-29\n", pa);
1203
1204                 if (type == RCVHQ_RCV_TYPE_EAGER)
1205                         pa |= dd->ipath_tidtemplate;
1206                 else /* for now, always full 4KB page */
1207                         pa |= 2 << 29;
1208         }
1209
1210         /*
1211          * Workaround chip bug 9437 by writing the scratch register
1212          * before and after the TID, and with an io write barrier.
1213          * We use a spinlock around the writes, so they can't intermix
1214          * with other TID (eager or expected) writes (the chip bug
1215          * is triggered by back to back TID writes). Unfortunately, this
1216          * call can be done from interrupt level for the port 0 eager TIDs,
1217          * so we have to use irqsave locks.
1218          */
1219         spin_lock_irqsave(&dd->ipath_tid_lock, flags);
1220         ipath_write_kreg(dd, dd->ipath_kregs->kr_scratch, 0xfeeddeaf);
1221         if (dd->ipath_kregbase)
1222                 writel(pa, tidp32);
1223         ipath_write_kreg(dd, dd->ipath_kregs->kr_scratch, 0xdeadbeef);
1224         mmiowb();
1225         spin_unlock_irqrestore(&dd->ipath_tid_lock, flags);
1226 }
1227 /**
1228  * ipath_pe_put_tid_2 - write a TID in chip, Revision 2 or higher
1229  * @dd: the infinipath device
1230  * @tidptr: pointer to the expected TID (in chip) to udpate
1231  * @tidtype: RCVHQ_RCV_TYPE_EAGER (1) for eager, RCVHQ_RCV_TYPE_EXPECTED (0) for expected
1232  * @pa: physical address of in memory buffer; ipath_tidinvalid if freeing
1233  *
1234  * This exists as a separate routine to allow for selection of the
1235  * appropriate "flavor". The static calls in cleanup just use the
1236  * revision-agnostic form, as they are not performance critical.
1237  */
1238 static void ipath_pe_put_tid_2(struct ipath_devdata *dd, u64 __iomem *tidptr,
1239                              u32 type, unsigned long pa)
1240 {
1241         u32 __iomem *tidp32 = (u32 __iomem *)tidptr;
1242
1243         if (pa != dd->ipath_tidinvalid) {
1244                 if (pa & ((1U << 11) - 1)) {
1245                         dev_info(&dd->pcidev->dev, "BUG: physaddr %lx "
1246                                  "not 2KB aligned!\n", pa);
1247                         return;
1248                 }
1249                 pa >>= 11;
1250                 /* paranoia check */
1251                 if (pa & (7<<29))
1252                         ipath_dev_err(dd,
1253                                       "BUG: Physical page address 0x%lx "
1254                                       "has bits set in 31-29\n", pa);
1255
1256                 if (type == RCVHQ_RCV_TYPE_EAGER)
1257                         pa |= dd->ipath_tidtemplate;
1258                 else /* for now, always full 4KB page */
1259                         pa |= 2 << 29;
1260         }
1261         if (dd->ipath_kregbase)
1262                 writel(pa, tidp32);
1263         mmiowb();
1264 }
1265
1266
1267 /**
1268  * ipath_pe_clear_tid - clear all TID entries for a port, expected and eager
1269  * @dd: the infinipath device
1270  * @port: the port
1271  *
1272  * clear all TID entries for a port, expected and eager.
1273  * Used from ipath_close().  On this chip, TIDs are only 32 bits,
1274  * not 64, but they are still on 64 bit boundaries, so tidbase
1275  * is declared as u64 * for the pointer math, even though we write 32 bits
1276  */
1277 static void ipath_pe_clear_tids(struct ipath_devdata *dd, unsigned port)
1278 {
1279         u64 __iomem *tidbase;
1280         unsigned long tidinv;
1281         int i;
1282
1283         if (!dd->ipath_kregbase)
1284                 return;
1285
1286         ipath_cdbg(VERBOSE, "Invalidate TIDs for port %u\n", port);
1287
1288         tidinv = dd->ipath_tidinvalid;
1289         tidbase = (u64 __iomem *)
1290                 ((char __iomem *)(dd->ipath_kregbase) +
1291                  dd->ipath_rcvtidbase +
1292                  port * dd->ipath_rcvtidcnt * sizeof(*tidbase));
1293
1294         for (i = 0; i < dd->ipath_rcvtidcnt; i++)
1295                 dd->ipath_f_put_tid(dd, &tidbase[i], RCVHQ_RCV_TYPE_EXPECTED,
1296                                  tidinv);
1297
1298         tidbase = (u64 __iomem *)
1299                 ((char __iomem *)(dd->ipath_kregbase) +
1300                  dd->ipath_rcvegrbase +
1301                  port * dd->ipath_rcvegrcnt * sizeof(*tidbase));
1302
1303         for (i = 0; i < dd->ipath_rcvegrcnt; i++)
1304                 dd->ipath_f_put_tid(dd, &tidbase[i], RCVHQ_RCV_TYPE_EAGER,
1305                                  tidinv);
1306 }
1307
1308 /**
1309  * ipath_pe_tidtemplate - setup constants for TID updates
1310  * @dd: the infinipath device
1311  *
1312  * We setup stuff that we use a lot, to avoid calculating each time
1313  */
1314 static void ipath_pe_tidtemplate(struct ipath_devdata *dd)
1315 {
1316         u32 egrsize = dd->ipath_rcvegrbufsize;
1317
1318         /* For now, we always allocate 4KB buffers (at init) so we can
1319          * receive max size packets.  We may want a module parameter to
1320          * specify 2KB or 4KB and/or make be per port instead of per device
1321          * for those who want to reduce memory footprint.  Note that the
1322          * ipath_rcvhdrentsize size must be large enough to hold the largest
1323          * IB header (currently 96 bytes) that we expect to handle (plus of
1324          * course the 2 dwords of RHF).
1325          */
1326         if (egrsize == 2048)
1327                 dd->ipath_tidtemplate = 1U << 29;
1328         else if (egrsize == 4096)
1329                 dd->ipath_tidtemplate = 2U << 29;
1330         else {
1331                 egrsize = 4096;
1332                 dev_info(&dd->pcidev->dev, "BUG: unsupported egrbufsize "
1333                          "%u, using %u\n", dd->ipath_rcvegrbufsize,
1334                          egrsize);
1335                 dd->ipath_tidtemplate = 2U << 29;
1336         }
1337         dd->ipath_tidinvalid = 0;
1338 }
1339
1340 static int ipath_pe_early_init(struct ipath_devdata *dd)
1341 {
1342         dd->ipath_flags |= IPATH_4BYTE_TID;
1343         if (ipath_unordered_wc())
1344                 dd->ipath_flags |= IPATH_PIO_FLUSH_WC;
1345
1346         /*
1347          * For openfabrics, we need to be able to handle an IB header of
1348          * 24 dwords.  HT chip has arbitrary sized receive buffers, so we
1349          * made them the same size as the PIO buffers.  This chip does not
1350          * handle arbitrary size buffers, so we need the header large enough
1351          * to handle largest IB header, but still have room for a 2KB MTU
1352          * standard IB packet.
1353          */
1354         dd->ipath_rcvhdrentsize = 24;
1355         dd->ipath_rcvhdrsize = IPATH_DFLT_RCVHDRSIZE;
1356
1357         /*
1358          * To truly support a 4KB MTU (for usermode), we need to
1359          * bump this to a larger value.  For now, we use them for
1360          * the kernel only.
1361          */
1362         dd->ipath_rcvegrbufsize = 2048;
1363         /*
1364          * the min() check here is currently a nop, but it may not always
1365          * be, depending on just how we do ipath_rcvegrbufsize
1366          */
1367         dd->ipath_ibmaxlen = min(dd->ipath_piosize2k,
1368                                  dd->ipath_rcvegrbufsize +
1369                                  (dd->ipath_rcvhdrentsize << 2));
1370         dd->ipath_init_ibmaxlen = dd->ipath_ibmaxlen;
1371
1372         /*
1373          * We can request a receive interrupt for 1 or
1374          * more packets from current offset.  For now, we set this
1375          * up for a single packet.
1376          */
1377         dd->ipath_rhdrhead_intr_off = 1ULL<<32;
1378
1379         ipath_get_eeprom_info(dd);
1380
1381         return 0;
1382 }
1383
1384 int __attribute__((weak)) ipath_unordered_wc(void)
1385 {
1386         return 0;
1387 }
1388
1389 /**
1390  * ipath_init_pe_get_base_info - set chip-specific flags for user code
1391  * @pd: the infinipath port
1392  * @kbase: ipath_base_info pointer
1393  *
1394  * We set the PCIE flag because the lower bandwidth on PCIe vs
1395  * HyperTransport can affect some user packet algorithms.
1396  */
1397 static int ipath_pe_get_base_info(struct ipath_portdata *pd, void *kbase)
1398 {
1399         struct ipath_base_info *kinfo = kbase;
1400         struct ipath_devdata *dd;
1401
1402         if (ipath_unordered_wc()) {
1403                 kinfo->spi_runtime_flags |= IPATH_RUNTIME_FORCE_WC_ORDER;
1404                 ipath_cdbg(PROC, "Intel processor, forcing WC order\n");
1405         }
1406         else
1407                 ipath_cdbg(PROC, "Not Intel processor, WC ordered\n");
1408
1409         if (pd == NULL)
1410                 goto done;
1411
1412         dd = pd->port_dd;
1413
1414 done:
1415         kinfo->spi_runtime_flags |= IPATH_RUNTIME_PCIE |
1416                 IPATH_RUNTIME_FORCE_PIOAVAIL | IPATH_RUNTIME_PIO_REGSWAPPED;
1417         return 0;
1418 }
1419
1420 static void ipath_pe_free_irq(struct ipath_devdata *dd)
1421 {
1422         free_irq(dd->ipath_irq, dd);
1423         dd->ipath_irq = 0;
1424 }
1425
1426 static void ipath_pe_config_ports(struct ipath_devdata *dd, ushort cfgports)
1427 {
1428         dd->ipath_portcnt =
1429                 ipath_read_kreg32(dd, dd->ipath_kregs->kr_portcnt);
1430         dd->ipath_p0_rcvegrcnt =
1431                 ipath_read_kreg32(dd, dd->ipath_kregs->kr_rcvegrcnt);
1432 }
1433
1434 static void ipath_pe_read_counters(struct ipath_devdata *dd,
1435                                    struct infinipath_counters *cntrs)
1436 {
1437         cntrs->LBIntCnt =
1438                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(LBIntCnt));
1439         cntrs->LBFlowStallCnt =
1440                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(LBFlowStallCnt));
1441         cntrs->TxSDmaDescCnt = 0;
1442         cntrs->TxUnsupVLErrCnt =
1443                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(TxUnsupVLErrCnt));
1444         cntrs->TxDataPktCnt =
1445                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(TxDataPktCnt));
1446         cntrs->TxFlowPktCnt =
1447                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(TxFlowPktCnt));
1448         cntrs->TxDwordCnt =
1449                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(TxDwordCnt));
1450         cntrs->TxLenErrCnt =
1451                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(TxLenErrCnt));
1452         cntrs->TxMaxMinLenErrCnt =
1453                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(TxMaxMinLenErrCnt));
1454         cntrs->TxUnderrunCnt =
1455                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(TxUnderrunCnt));
1456         cntrs->TxFlowStallCnt =
1457                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(TxFlowStallCnt));
1458         cntrs->TxDroppedPktCnt =
1459                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(TxDroppedPktCnt));
1460         cntrs->RxDroppedPktCnt =
1461                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxDroppedPktCnt));
1462         cntrs->RxDataPktCnt =
1463                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxDataPktCnt));
1464         cntrs->RxFlowPktCnt =
1465                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxFlowPktCnt));
1466         cntrs->RxDwordCnt =
1467                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxDwordCnt));
1468         cntrs->RxLenErrCnt =
1469                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxLenErrCnt));
1470         cntrs->RxMaxMinLenErrCnt =
1471                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxMaxMinLenErrCnt));
1472         cntrs->RxICRCErrCnt =
1473                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxICRCErrCnt));
1474         cntrs->RxVCRCErrCnt =
1475                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxVCRCErrCnt));
1476         cntrs->RxFlowCtrlErrCnt =
1477                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxFlowCtrlErrCnt));
1478         cntrs->RxBadFormatCnt =
1479                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxBadFormatCnt));
1480         cntrs->RxLinkProblemCnt =
1481                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxLinkProblemCnt));
1482         cntrs->RxEBPCnt =
1483                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxEBPCnt));
1484         cntrs->RxLPCRCErrCnt =
1485                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxLPCRCErrCnt));
1486         cntrs->RxBufOvflCnt =
1487                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxBufOvflCnt));
1488         cntrs->RxTIDFullErrCnt =
1489                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxTIDFullErrCnt));
1490         cntrs->RxTIDValidErrCnt =
1491                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxTIDValidErrCnt));
1492         cntrs->RxPKeyMismatchCnt =
1493                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxPKeyMismatchCnt));
1494         cntrs->RxP0HdrEgrOvflCnt =
1495                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxP0HdrEgrOvflCnt));
1496         cntrs->RxP1HdrEgrOvflCnt =
1497                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxP1HdrEgrOvflCnt));
1498         cntrs->RxP2HdrEgrOvflCnt =
1499                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxP2HdrEgrOvflCnt));
1500         cntrs->RxP3HdrEgrOvflCnt =
1501                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxP3HdrEgrOvflCnt));
1502         cntrs->RxP4HdrEgrOvflCnt =
1503                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxP4HdrEgrOvflCnt));
1504         cntrs->RxP5HdrEgrOvflCnt = 0;
1505         cntrs->RxP6HdrEgrOvflCnt = 0;
1506         cntrs->RxP7HdrEgrOvflCnt = 0;
1507         cntrs->RxP8HdrEgrOvflCnt = 0;
1508         cntrs->RxP9HdrEgrOvflCnt = 0;
1509         cntrs->RxP10HdrEgrOvflCnt = 0;
1510         cntrs->RxP11HdrEgrOvflCnt = 0;
1511         cntrs->RxP12HdrEgrOvflCnt = 0;
1512         cntrs->RxP13HdrEgrOvflCnt = 0;
1513         cntrs->RxP14HdrEgrOvflCnt = 0;
1514         cntrs->RxP15HdrEgrOvflCnt = 0;
1515         cntrs->RxP16HdrEgrOvflCnt = 0;
1516         cntrs->IBStatusChangeCnt =
1517                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(IBStatusChangeCnt));
1518         cntrs->IBLinkErrRecoveryCnt =
1519                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(IBLinkErrRecoveryCnt));
1520         cntrs->IBLinkDownedCnt =
1521                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(IBLinkDownedCnt));
1522         cntrs->IBSymbolErrCnt =
1523                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(IBSymbolErrCnt));
1524         cntrs->RxVL15DroppedPktCnt = 0;
1525         cntrs->RxOtherLocalPhyErrCnt = 0;
1526         cntrs->PcieRetryBufDiagQwordCnt = 0;
1527         cntrs->ExcessBufferOvflCnt = dd->ipath_overrun_thresh_errs;
1528         cntrs->LocalLinkIntegrityErrCnt = dd->ipath_lli_errs;
1529         cntrs->RxVlErrCnt = 0;
1530         cntrs->RxDlidFltrCnt = 0;
1531 }
1532
1533 /*
1534  * On platforms using this chip, and not having ordered WC stores, we
1535  * can get TXE parity errors due to speculative reads to the PIO buffers,
1536  * and this, due to a chip bug can result in (many) false parity error
1537  * reports.  So it's a debug print on those, and an info print on systems
1538  * where the speculative reads don't occur.
1539  * Because we can get lots of false errors, we have no upper limit
1540  * on recovery attempts on those platforms.
1541  */
1542 static int ipath_pe_txe_recover(struct ipath_devdata *dd)
1543 {
1544         if (ipath_unordered_wc())
1545                 ipath_dbg("Recovering from TXE PIO parity error\n");
1546         else {
1547                 int cnt = ++ipath_stats.sps_txeparity;
1548                 if (cnt >= IPATH_MAX_PARITY_ATTEMPTS)  {
1549                         if (cnt == IPATH_MAX_PARITY_ATTEMPTS)
1550                                 ipath_dev_err(dd,
1551                                         "Too many attempts to recover from "
1552                                         "TXE parity, giving up\n");
1553                         return 0;
1554                 }
1555                 dev_info(&dd->pcidev->dev,
1556                         "Recovering from TXE PIO parity error\n");
1557         }
1558         return 1;
1559 }
1560
1561 /**
1562  * ipath_init_iba6120_funcs - set up the chip-specific function pointers
1563  * @dd: the infinipath device
1564  *
1565  * This is global, and is called directly at init to set up the
1566  * chip-specific function pointers for later use.
1567  */
1568 void ipath_init_iba6120_funcs(struct ipath_devdata *dd)
1569 {
1570         dd->ipath_f_intrsetup = ipath_pe_intconfig;
1571         dd->ipath_f_bus = ipath_setup_pe_config;
1572         dd->ipath_f_reset = ipath_setup_pe_reset;
1573         dd->ipath_f_get_boardname = ipath_pe_boardname;
1574         dd->ipath_f_init_hwerrors = ipath_pe_init_hwerrors;
1575         dd->ipath_f_early_init = ipath_pe_early_init;
1576         dd->ipath_f_handle_hwerrors = ipath_pe_handle_hwerrors;
1577         dd->ipath_f_quiet_serdes = ipath_pe_quiet_serdes;
1578         dd->ipath_f_bringup_serdes = ipath_pe_bringup_serdes;
1579         dd->ipath_f_clear_tids = ipath_pe_clear_tids;
1580         /*
1581          * this may get changed after we read the chip revision,
1582          * but we start with the safe version for all revs
1583          */
1584         dd->ipath_f_put_tid = ipath_pe_put_tid;
1585         dd->ipath_f_cleanup = ipath_setup_pe_cleanup;
1586         dd->ipath_f_setextled = ipath_setup_pe_setextled;
1587         dd->ipath_f_get_base_info = ipath_pe_get_base_info;
1588         dd->ipath_f_free_irq = ipath_pe_free_irq;
1589
1590         /* initialize chip-specific variables */
1591         dd->ipath_f_tidtemplate = ipath_pe_tidtemplate;
1592         dd->ipath_f_config_ports = ipath_pe_config_ports;
1593         dd->ipath_f_read_counters = ipath_pe_read_counters;
1594
1595         /*
1596          * setup the register offsets, since they are different for each
1597          * chip
1598          */
1599         dd->ipath_kregs = &ipath_pe_kregs;
1600         dd->ipath_cregs = &ipath_pe_cregs;
1601
1602         ipath_init_pe_variables(dd);
1603 }
1604