2 * Copyright (c) 2006, 2007 QLogic Corporation. All rights reserved.
3 * Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved.
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
34 #include <linux/pci.h>
35 #include <linux/delay.h>
37 #include "ipath_kernel.h"
38 #include "ipath_verbs.h"
39 #include "ipath_common.h"
42 * clear (write) a pio buffer, to clear a parity error. This routine
43 * should only be called when in freeze mode, and the buffer should be
44 * canceled afterwards.
46 static void ipath_clrpiobuf(struct ipath_devdata *dd, u32 pnum)
49 u32 dwcnt; /* dword count to write */
50 if (pnum < dd->ipath_piobcnt2k) {
51 pbuf = (u32 __iomem *) (dd->ipath_pio2kbase + pnum *
53 dwcnt = dd->ipath_piosize2k >> 2;
56 pbuf = (u32 __iomem *) (dd->ipath_pio4kbase +
57 (pnum - dd->ipath_piobcnt2k) * dd->ipath_4kalign);
58 dwcnt = dd->ipath_piosize4k >> 2;
60 dev_info(&dd->pcidev->dev,
61 "Rewrite PIO buffer %u, to recover from parity error\n",
64 /* no flush required, since already in freeze */
65 writel(dwcnt + 1, pbuf);
71 * Called when we might have an error that is specific to a particular
72 * PIO buffer, and may need to cancel that buffer, so it can be re-used.
73 * If rewrite is true, and bits are set in the sendbufferror registers,
74 * we'll write to the buffer, for error recovery on parity errors.
76 static void ipath_disarm_senderrbufs(struct ipath_devdata *dd, int rewrite)
79 unsigned long sbuf[4];
81 * it's possible that sendbuffererror could have bits set; might
82 * have already done this as a result of hardware error handling
84 piobcnt = dd->ipath_piobcnt2k + dd->ipath_piobcnt4k;
85 /* read these before writing errorclear */
86 sbuf[0] = ipath_read_kreg64(
87 dd, dd->ipath_kregs->kr_sendbuffererror);
88 sbuf[1] = ipath_read_kreg64(
89 dd, dd->ipath_kregs->kr_sendbuffererror + 1);
91 sbuf[2] = ipath_read_kreg64(
92 dd, dd->ipath_kregs->kr_sendbuffererror + 2);
93 sbuf[3] = ipath_read_kreg64(
94 dd, dd->ipath_kregs->kr_sendbuffererror + 3);
97 if (sbuf[0] || sbuf[1] || (piobcnt > 128 && (sbuf[2] || sbuf[3]))) {
99 if (ipath_debug & (__IPATH_PKTDBG|__IPATH_DBG) &&
100 dd->ipath_lastcancel > jiffies) {
101 __IPATH_DBG_WHICH(__IPATH_PKTDBG|__IPATH_DBG,
102 "SendbufErrs %lx %lx", sbuf[0],
104 if (ipath_debug & __IPATH_PKTDBG && piobcnt > 128)
105 printk(" %lx %lx ", sbuf[2], sbuf[3]);
109 for (i = 0; i < piobcnt; i++)
110 if (test_bit(i, sbuf)) {
112 ipath_clrpiobuf(dd, i);
113 ipath_disarm_piobufs(dd, i, 1);
115 /* ignore armlaunch errs for a bit */
116 dd->ipath_lastcancel = jiffies+3;
121 /* These are all rcv-related errors which we want to count for stats */
122 #define E_SUM_PKTERRS \
123 (INFINIPATH_E_RHDRLEN | INFINIPATH_E_RBADTID | \
124 INFINIPATH_E_RBADVERSION | INFINIPATH_E_RHDR | \
125 INFINIPATH_E_RLONGPKTLEN | INFINIPATH_E_RSHORTPKTLEN | \
126 INFINIPATH_E_RMAXPKTLEN | INFINIPATH_E_RMINPKTLEN | \
127 INFINIPATH_E_RFORMATERR | INFINIPATH_E_RUNSUPVL | \
128 INFINIPATH_E_RUNEXPCHAR | INFINIPATH_E_REBP)
130 /* These are all send-related errors which we want to count for stats */
132 (INFINIPATH_E_SPIOARMLAUNCH | INFINIPATH_E_SUNEXPERRPKTNUM | \
133 INFINIPATH_E_SDROPPEDDATAPKT | INFINIPATH_E_SDROPPEDSMPPKT | \
134 INFINIPATH_E_SMAXPKTLEN | INFINIPATH_E_SUNSUPVL | \
135 INFINIPATH_E_SMINPKTLEN | INFINIPATH_E_SPKTLEN | \
136 INFINIPATH_E_INVALIDADDR)
139 * this is similar to E_SUM_ERRS, but can't ignore armlaunch, don't ignore
140 * errors not related to freeze and cancelling buffers. Can't ignore
141 * armlaunch because could get more while still cleaning up, and need
142 * to cancel those as they happen.
144 #define E_SPKT_ERRS_IGNORE \
145 (INFINIPATH_E_SDROPPEDDATAPKT | INFINIPATH_E_SDROPPEDSMPPKT | \
146 INFINIPATH_E_SMAXPKTLEN | INFINIPATH_E_SMINPKTLEN | \
147 INFINIPATH_E_SPKTLEN)
150 * these are errors that can occur when the link changes state while
151 * a packet is being sent or received. This doesn't cover things
152 * like EBP or VCRC that can be the result of a sending having the
153 * link change state, so we receive a "known bad" packet.
155 #define E_SUM_LINK_PKTERRS \
156 (INFINIPATH_E_SDROPPEDDATAPKT | INFINIPATH_E_SDROPPEDSMPPKT | \
157 INFINIPATH_E_SMINPKTLEN | INFINIPATH_E_SPKTLEN | \
158 INFINIPATH_E_RSHORTPKTLEN | INFINIPATH_E_RMINPKTLEN | \
159 INFINIPATH_E_RUNEXPCHAR)
161 static u64 handle_e_sum_errs(struct ipath_devdata *dd, ipath_err_t errs)
163 u64 ignore_this_time = 0;
165 ipath_disarm_senderrbufs(dd, 0);
166 if ((errs & E_SUM_LINK_PKTERRS) &&
167 !(dd->ipath_flags & IPATH_LINKACTIVE)) {
169 * This can happen when SMA is trying to bring the link
170 * up, but the IB link changes state at the "wrong" time.
171 * The IB logic then complains that the packet isn't
172 * valid. We don't want to confuse people, so we just
173 * don't print them, except at debug
175 ipath_dbg("Ignoring packet errors %llx, because link not "
176 "ACTIVE\n", (unsigned long long) errs);
177 ignore_this_time = errs & E_SUM_LINK_PKTERRS;
180 return ignore_this_time;
183 /* generic hw error messages... */
184 #define INFINIPATH_HWE_TXEMEMPARITYERR_MSG(a) \
186 .mask = ( INFINIPATH_HWE_TXEMEMPARITYERR_##a << \
187 INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT ), \
188 .msg = "TXE " #a " Memory Parity" \
190 #define INFINIPATH_HWE_RXEMEMPARITYERR_MSG(a) \
192 .mask = ( INFINIPATH_HWE_RXEMEMPARITYERR_##a << \
193 INFINIPATH_HWE_RXEMEMPARITYERR_SHIFT ), \
194 .msg = "RXE " #a " Memory Parity" \
197 static const struct ipath_hwerror_msgs ipath_generic_hwerror_msgs[] = {
198 INFINIPATH_HWE_MSG(IBCBUSFRSPCPARITYERR, "IPATH2IB Parity"),
199 INFINIPATH_HWE_MSG(IBCBUSTOSPCPARITYERR, "IB2IPATH Parity"),
201 INFINIPATH_HWE_TXEMEMPARITYERR_MSG(PIOBUF),
202 INFINIPATH_HWE_TXEMEMPARITYERR_MSG(PIOPBC),
203 INFINIPATH_HWE_TXEMEMPARITYERR_MSG(PIOLAUNCHFIFO),
205 INFINIPATH_HWE_RXEMEMPARITYERR_MSG(RCVBUF),
206 INFINIPATH_HWE_RXEMEMPARITYERR_MSG(LOOKUPQ),
207 INFINIPATH_HWE_RXEMEMPARITYERR_MSG(EAGERTID),
208 INFINIPATH_HWE_RXEMEMPARITYERR_MSG(EXPTID),
209 INFINIPATH_HWE_RXEMEMPARITYERR_MSG(FLAGBUF),
210 INFINIPATH_HWE_RXEMEMPARITYERR_MSG(DATAINFO),
211 INFINIPATH_HWE_RXEMEMPARITYERR_MSG(HDRINFO),
215 * ipath_format_hwmsg - format a single hwerror message
216 * @msg message buffer
217 * @msgl length of message buffer
218 * @hwmsg message to add to message buffer
220 static void ipath_format_hwmsg(char *msg, size_t msgl, const char *hwmsg)
222 strlcat(msg, "[", msgl);
223 strlcat(msg, hwmsg, msgl);
224 strlcat(msg, "]", msgl);
228 * ipath_format_hwerrors - format hardware error messages for display
229 * @hwerrs hardware errors bit vector
230 * @hwerrmsgs hardware error descriptions
231 * @nhwerrmsgs number of hwerrmsgs
232 * @msg message buffer
233 * @msgl message buffer length
235 void ipath_format_hwerrors(u64 hwerrs,
236 const struct ipath_hwerror_msgs *hwerrmsgs,
238 char *msg, size_t msgl)
242 sizeof(ipath_generic_hwerror_msgs) /
243 sizeof(ipath_generic_hwerror_msgs[0]);
245 for (i=0; i<glen; i++) {
246 if (hwerrs & ipath_generic_hwerror_msgs[i].mask) {
247 ipath_format_hwmsg(msg, msgl,
248 ipath_generic_hwerror_msgs[i].msg);
252 for (i=0; i<nhwerrmsgs; i++) {
253 if (hwerrs & hwerrmsgs[i].mask) {
254 ipath_format_hwmsg(msg, msgl, hwerrmsgs[i].msg);
259 /* return the strings for the most common link states */
260 static char *ib_linkstate(struct ipath_devdata *dd, u64 ibcs)
265 state = ipath_ib_state(dd, ibcs);
266 if (state == dd->ib_init)
268 else if (state == dd->ib_arm)
270 else if (state == dd->ib_active)
277 void signal_ib_event(struct ipath_devdata *dd, enum ib_event_type ev)
279 struct ib_event event;
281 event.device = &dd->verbs_dev->ibdev;
282 event.element.port_num = 1;
284 ib_dispatch_event(&event);
287 static void handle_e_ibstatuschanged(struct ipath_devdata *dd,
290 u32 ltstate, lstate, ibstate, lastlstate;
291 u32 init = dd->ib_init;
292 u32 arm = dd->ib_arm;
293 u32 active = dd->ib_active;
294 const u64 ibcs = ipath_read_kreg64(dd, dd->ipath_kregs->kr_ibcstatus);
296 lstate = ipath_ib_linkstate(dd, ibcs); /* linkstate */
297 ibstate = ipath_ib_state(dd, ibcs);
298 /* linkstate at last interrupt */
299 lastlstate = ipath_ib_linkstate(dd, dd->ipath_lastibcstat);
300 ltstate = ipath_ib_linktrstate(dd, ibcs); /* linktrainingtate */
303 * if linkstate transitions into INIT from any of the various down
304 * states, or if it transitions from any of the up (INIT or better)
305 * states into any of the down states (except link recovery), then
306 * call the chip-specific code to take appropriate actions.
308 if (lstate >= INFINIPATH_IBCS_L_STATE_INIT &&
309 lastlstate == INFINIPATH_IBCS_L_STATE_DOWN) {
310 /* transitioned to UP */
311 if (dd->ipath_f_ib_updown(dd, 1, ibcs)) {
312 ipath_cdbg(LINKVERB, "LinkUp handled, skipped\n");
313 goto skip_ibchange; /* chip-code handled */
315 } else if ((lastlstate >= INFINIPATH_IBCS_L_STATE_INIT ||
316 (dd->ipath_flags & IPATH_IB_FORCE_NOTIFY)) &&
317 ltstate <= INFINIPATH_IBCS_LT_STATE_CFGDEBOUNCE &&
318 ltstate != INFINIPATH_IBCS_LT_STATE_LINKUP) {
320 handled = dd->ipath_f_ib_updown(dd, 0, ibcs);
321 dd->ipath_flags &= ~IPATH_IB_FORCE_NOTIFY;
323 ipath_cdbg(LINKVERB, "LinkDown handled, skipped\n");
324 goto skip_ibchange; /* chip-code handled */
329 * Significant enough to always print and get into logs, if it was
330 * unexpected. If it was a requested state change, we'll have
331 * already cleared the flags, so we won't print this warning
333 if ((ibstate != arm && ibstate != active) &&
334 (dd->ipath_flags & (IPATH_LINKARMED | IPATH_LINKACTIVE))) {
335 dev_info(&dd->pcidev->dev, "Link state changed from %s "
336 "to %s\n", (dd->ipath_flags & IPATH_LINKARMED) ?
337 "ARM" : "ACTIVE", ib_linkstate(dd, ibcs));
340 if (ltstate == INFINIPATH_IBCS_LT_STATE_POLLACTIVE ||
341 ltstate == INFINIPATH_IBCS_LT_STATE_POLLQUIET) {
343 lastlts = ipath_ib_linktrstate(dd, dd->ipath_lastibcstat);
345 * Ignore cycling back and forth from Polling.Active to
346 * Polling.Quiet while waiting for the other end of the link
347 * to come up, except to try and decide if we are connected
348 * to a live IB device or not. We will cycle back and
349 * forth between them if no cable is plugged in, the other
350 * device is powered off or disabled, etc.
352 if (lastlts == INFINIPATH_IBCS_LT_STATE_POLLACTIVE ||
353 lastlts == INFINIPATH_IBCS_LT_STATE_POLLQUIET) {
354 if (++dd->ipath_ibpollcnt == 40) {
355 dd->ipath_flags |= IPATH_NOCABLE;
356 *dd->ipath_statusp |=
357 IPATH_STATUS_IB_NOCABLE;
358 ipath_cdbg(LINKVERB, "Set NOCABLE\n");
360 ipath_cdbg(LINKVERB, "POLL change to %s (%x)\n",
361 ipath_ibcstatus_str[ltstate], ibstate);
366 dd->ipath_ibpollcnt = 0; /* not poll*, now */
367 ipath_stats.sps_iblink++;
369 if (ibstate != init && dd->ipath_lastlinkrecov && ipath_linkrecovery) {
371 linkrecov = ipath_snap_cntr(dd,
372 dd->ipath_cregs->cr_iblinkerrrecovcnt);
373 if (linkrecov != dd->ipath_lastlinkrecov) {
374 ipath_dbg("IB linkrecov up %Lx (%s %s) recov %Lu\n",
375 ibcs, ib_linkstate(dd, ibcs),
376 ipath_ibcstatus_str[ltstate],
378 /* and no more until active again */
379 dd->ipath_lastlinkrecov = 0;
380 ipath_set_linkstate(dd, IPATH_IB_LINKDOWN);
385 if (ibstate == init || ibstate == arm || ibstate == active) {
386 *dd->ipath_statusp &= ~IPATH_STATUS_IB_NOCABLE;
387 if (ibstate == init || ibstate == arm) {
388 *dd->ipath_statusp &= ~IPATH_STATUS_IB_READY;
389 if (dd->ipath_flags & IPATH_LINKACTIVE)
390 signal_ib_event(dd, IB_EVENT_PORT_ERR);
392 if (ibstate == arm) {
393 dd->ipath_flags |= IPATH_LINKARMED;
394 dd->ipath_flags &= ~(IPATH_LINKUNK |
395 IPATH_LINKINIT | IPATH_LINKDOWN |
396 IPATH_LINKACTIVE | IPATH_NOCABLE);
398 } else if (ibstate == init) {
400 * set INIT and DOWN. Down is checked by
401 * most of the other code, but INIT is
402 * useful to know in a few places.
404 dd->ipath_flags |= IPATH_LINKINIT |
406 dd->ipath_flags &= ~(IPATH_LINKUNK |
407 IPATH_LINKARMED | IPATH_LINKACTIVE |
410 } else { /* active */
411 dd->ipath_lastlinkrecov = ipath_snap_cntr(dd,
412 dd->ipath_cregs->cr_iblinkerrrecovcnt);
413 *dd->ipath_statusp |=
414 IPATH_STATUS_IB_READY | IPATH_STATUS_IB_CONF;
415 dd->ipath_flags |= IPATH_LINKACTIVE;
416 dd->ipath_flags &= ~(IPATH_LINKUNK | IPATH_LINKINIT
417 | IPATH_LINKDOWN | IPATH_LINKARMED |
419 signal_ib_event(dd, IB_EVENT_PORT_ACTIVE);
420 /* LED active not handled in chip _f_updown */
421 dd->ipath_f_setextled(dd, lstate, ltstate);
426 * print after we've already done the work, so as not to
427 * delay the state changes and notifications, for debugging
429 if (lstate == lastlstate)
430 ipath_cdbg(LINKVERB, "Unchanged from last: %s "
431 "(%x)\n", ib_linkstate(dd, ibcs), ibstate);
433 ipath_cdbg(VERBOSE, "Unit %u: link up to %s %s (%x)\n",
434 dd->ipath_unit, ib_linkstate(dd, ibcs),
435 ipath_ibcstatus_str[ltstate], ibstate);
437 if (dd->ipath_flags & IPATH_LINKACTIVE)
438 signal_ib_event(dd, IB_EVENT_PORT_ERR);
439 dd->ipath_flags |= IPATH_LINKDOWN;
440 dd->ipath_flags &= ~(IPATH_LINKUNK | IPATH_LINKINIT
443 *dd->ipath_statusp &= ~IPATH_STATUS_IB_READY;
444 dd->ipath_lli_counter = 0;
446 if (lastlstate != INFINIPATH_IBCS_L_STATE_DOWN)
447 ipath_cdbg(VERBOSE, "Unit %u link state down "
448 "(state 0x%x), from %s\n",
449 dd->ipath_unit, lstate,
450 ib_linkstate(dd, dd->ipath_lastibcstat));
452 ipath_cdbg(LINKVERB, "Unit %u link state changed "
453 "to %s (0x%x) from down (%x)\n",
455 ipath_ibcstatus_str[ltstate],
456 ibstate, lastlstate);
460 dd->ipath_lastibcstat = ibcs;
463 static void handle_supp_msgs(struct ipath_devdata *dd,
464 unsigned supp_msgs, char *msg, int msgsz)
467 * Print the message unless it's ibc status change only, which
468 * happens so often we never want to count it.
470 if (dd->ipath_lasterror & ~INFINIPATH_E_IBSTATUSCHANGED) {
472 iserr = ipath_decode_err(msg, msgsz,
473 dd->ipath_lasterror &
474 ~INFINIPATH_E_IBSTATUSCHANGED);
475 if (dd->ipath_lasterror &
476 ~(INFINIPATH_E_RRCVEGRFULL |
477 INFINIPATH_E_RRCVHDRFULL | INFINIPATH_E_PKTERRS))
478 ipath_dev_err(dd, "Suppressed %u messages for "
479 "fast-repeating errors (%s) (%llx)\n",
482 dd->ipath_lasterror);
485 * rcvegrfull and rcvhdrqfull are "normal", for some
486 * types of processes (mostly benchmarks) that send
487 * huge numbers of messages, while not processing
488 * them. So only complain about these at debug
492 ipath_dbg("Suppressed %u messages for %s\n",
496 "Suppressed %u messages for %s\n",
502 static unsigned handle_frequent_errors(struct ipath_devdata *dd,
503 ipath_err_t errs, char *msg,
504 int msgsz, int *noprint)
507 static unsigned long nextmsg_time;
508 static unsigned nmsgs, supp_msgs;
511 * Throttle back "fast" messages to no more than 10 per 5 seconds.
512 * This isn't perfect, but it's a reasonable heuristic. If we get
513 * more than 10, give a 6x longer delay.
517 if (time_before(nc, nextmsg_time)) {
520 nextmsg_time = nc + HZ * 3;
522 else if (supp_msgs) {
523 handle_supp_msgs(dd, supp_msgs, msg, msgsz);
528 else if (!nmsgs++ || time_after(nc, nextmsg_time))
529 nextmsg_time = nc + HZ / 2;
534 static int handle_errors(struct ipath_devdata *dd, ipath_err_t errs)
537 u64 ignore_this_time = 0;
539 int chkerrpkts = 0, noprint = 0;
543 supp_msgs = handle_frequent_errors(dd, errs, msg, sizeof msg, &noprint);
545 /* don't report errors that are masked */
546 errs &= ~dd->ipath_maskederrs;
548 /* do these first, they are most important */
549 if (errs & INFINIPATH_E_HARDWARE) {
550 /* reuse same msg buf */
551 dd->ipath_f_handle_hwerrors(dd, msg, sizeof msg);
554 for (log_idx = 0; log_idx < IPATH_EEP_LOG_CNT; ++log_idx) {
555 mask = dd->ipath_eep_st_masks[log_idx].errs_to_log;
557 ipath_inc_eeprom_err(dd, log_idx, 1);
561 if (!noprint && (errs & ~dd->ipath_e_bitsextant))
562 ipath_dev_err(dd, "error interrupt with unknown errors "
563 "%llx set\n", (unsigned long long)
564 (errs & ~dd->ipath_e_bitsextant));
566 if (errs & E_SUM_ERRS)
567 ignore_this_time = handle_e_sum_errs(dd, errs);
568 else if ((errs & E_SUM_LINK_PKTERRS) &&
569 !(dd->ipath_flags & IPATH_LINKACTIVE)) {
571 * This can happen when SMA is trying to bring the link
572 * up, but the IB link changes state at the "wrong" time.
573 * The IB logic then complains that the packet isn't
574 * valid. We don't want to confuse people, so we just
575 * don't print them, except at debug
577 ipath_dbg("Ignoring packet errors %llx, because link not "
578 "ACTIVE\n", (unsigned long long) errs);
579 ignore_this_time = errs & E_SUM_LINK_PKTERRS;
582 if (supp_msgs == 250000) {
585 * It's not entirely reasonable assuming that the errors set
586 * in the last clear period are all responsible for the
587 * problem, but the alternative is to assume it's the only
588 * ones on this particular interrupt, which also isn't great
590 dd->ipath_maskederrs |= dd->ipath_lasterror | errs;
591 dd->ipath_errormask &= ~dd->ipath_maskederrs;
592 ipath_write_kreg(dd, dd->ipath_kregs->kr_errormask,
593 dd->ipath_errormask);
594 s_iserr = ipath_decode_err(msg, sizeof msg,
595 dd->ipath_maskederrs);
597 if (dd->ipath_maskederrs &
598 ~(INFINIPATH_E_RRCVEGRFULL |
599 INFINIPATH_E_RRCVHDRFULL | INFINIPATH_E_PKTERRS))
600 ipath_dev_err(dd, "Temporarily disabling "
601 "error(s) %llx reporting; too frequent (%s)\n",
602 (unsigned long long)dd->ipath_maskederrs,
606 * rcvegrfull and rcvhdrqfull are "normal",
607 * for some types of processes (mostly benchmarks)
608 * that send huge numbers of messages, while not
609 * processing them. So only complain about
610 * these at debug level.
613 ipath_dbg("Temporarily disabling reporting "
614 "too frequent queue full errors (%s)\n",
618 "Temporarily disabling reporting too"
619 " frequent packet errors (%s)\n",
624 * Re-enable the masked errors after around 3 minutes. in
625 * ipath_get_faststats(). If we have a series of fast
626 * repeating but different errors, the interval will keep
627 * stretching out, but that's OK, as that's pretty
630 dd->ipath_unmasktime = jiffies + HZ * 180;
633 ipath_write_kreg(dd, dd->ipath_kregs->kr_errorclear, errs);
634 if (ignore_this_time)
635 errs &= ~ignore_this_time;
636 if (errs & ~dd->ipath_lasterror) {
637 errs &= ~dd->ipath_lasterror;
638 /* never suppress duplicate hwerrors or ibstatuschange */
639 dd->ipath_lasterror |= errs &
640 ~(INFINIPATH_E_HARDWARE |
641 INFINIPATH_E_IBSTATUSCHANGED);
644 /* likely due to cancel, so suppress */
645 if ((errs & (INFINIPATH_E_SPKTLEN | INFINIPATH_E_SPIOARMLAUNCH)) &&
646 dd->ipath_lastcancel > jiffies) {
647 ipath_dbg("Suppressed armlaunch/spktlen after error send cancel\n");
648 errs &= ~(INFINIPATH_E_SPIOARMLAUNCH | INFINIPATH_E_SPKTLEN);
656 * the ones we mask off are handled specially below or above
658 ipath_decode_err(msg, sizeof msg,
659 errs & ~(INFINIPATH_E_IBSTATUSCHANGED |
660 INFINIPATH_E_RRCVEGRFULL |
661 INFINIPATH_E_RRCVHDRFULL |
662 INFINIPATH_E_HARDWARE));
664 /* so we don't need if (!noprint) at strlcat's below */
667 if (errs & E_SUM_PKTERRS) {
668 ipath_stats.sps_pkterrs++;
671 if (errs & E_SUM_ERRS)
672 ipath_stats.sps_errs++;
674 if (errs & (INFINIPATH_E_RICRC | INFINIPATH_E_RVCRC)) {
675 ipath_stats.sps_crcerrs++;
678 iserr = errs & ~(E_SUM_PKTERRS | INFINIPATH_E_PKTERRS);
682 * We don't want to print these two as they happen, or we can make
683 * the situation even worse, because it takes so long to print
684 * messages to serial consoles. Kernel ports get printed from
685 * fast_stats, no more than every 5 seconds, user ports get printed
688 if (errs & INFINIPATH_E_RRCVHDRFULL) {
690 ipath_stats.sps_hdrqfull++;
691 for (i = 0; i < dd->ipath_cfgports; i++) {
692 struct ipath_portdata *pd = dd->ipath_pd[i];
695 tl = (u32) le64_to_cpu(
696 *dd->ipath_hdrqtailptr);
697 } else if (pd && pd->port_cnt &&
698 pd->port_rcvhdrtail_kvaddr) {
700 * don't report same point multiple times,
703 tl = *(u64 *) pd->port_rcvhdrtail_kvaddr;
704 if (tl == pd->port_lastrcvhdrqtail)
706 hd = ipath_read_ureg32(dd, ur_rcvhdrhead,
710 if (hd == (tl + 1) ||
711 (!hd && tl == dd->ipath_hdrqlast)) {
714 pd->port_lastrcvhdrqtail = tl;
716 /* flush hdrqfull so that poll() sees it */
718 wake_up_interruptible(&pd->port_wait);
722 if (errs & INFINIPATH_E_RRCVEGRFULL) {
723 struct ipath_portdata *pd = dd->ipath_pd[0];
726 * since this is of less importance and not likely to
727 * happen without also getting hdrfull, only count
728 * occurrences; don't check each port (or even the kernel
731 ipath_stats.sps_etidfull++;
733 (u32) le64_to_cpu(*dd->ipath_hdrqtailptr))
738 * do this before IBSTATUSCHANGED, in case both bits set in a single
739 * interrupt; we want the STATUSCHANGE to "win", so we do our
740 * internal copy of state machine correctly
742 if (errs & INFINIPATH_E_RIBLOSTLINK) {
744 * force through block below
746 errs |= INFINIPATH_E_IBSTATUSCHANGED;
747 ipath_stats.sps_iblink++;
748 dd->ipath_flags |= IPATH_LINKDOWN;
749 dd->ipath_flags &= ~(IPATH_LINKUNK | IPATH_LINKINIT
750 | IPATH_LINKARMED | IPATH_LINKACTIVE);
751 *dd->ipath_statusp &= ~IPATH_STATUS_IB_READY;
753 ipath_dbg("Lost link, link now down (%s)\n",
754 ipath_ibcstatus_str[ipath_read_kreg64(dd,
755 dd->ipath_kregs->kr_ibcstatus) & 0xf]);
757 if (errs & INFINIPATH_E_IBSTATUSCHANGED)
758 handle_e_ibstatuschanged(dd, errs);
760 if (errs & INFINIPATH_E_RESET) {
762 ipath_dev_err(dd, "Got reset, requires re-init "
763 "(unload and reload driver)\n");
764 dd->ipath_flags &= ~IPATH_INITTED; /* needs re-init */
765 /* mark as having had error */
766 *dd->ipath_statusp |= IPATH_STATUS_HWERROR;
767 *dd->ipath_statusp &= ~IPATH_STATUS_IB_CONF;
770 if (!noprint && *msg) {
772 ipath_dev_err(dd, "%s error\n", msg);
774 dev_info(&dd->pcidev->dev, "%s packet problems\n",
777 if (dd->ipath_state_wanted & dd->ipath_flags) {
778 ipath_cdbg(VERBOSE, "driver wanted state %x, iflags now %x, "
779 "waking\n", dd->ipath_state_wanted,
781 wake_up_interruptible(&ipath_state_wait);
789 * try to cleanup as much as possible for anything that might have gone
790 * wrong while in freeze mode, such as pio buffers being written by user
791 * processes (causing armlaunch), send errors due to going into freeze mode,
792 * etc., and try to avoid causing extra interrupts while doing so.
793 * Forcibly update the in-memory pioavail register copies after cleanup
794 * because the chip won't do it for anything changing while in freeze mode
795 * (we don't want to wait for the next pio buffer state change).
796 * Make sure that we don't lose any important interrupts by using the chip
797 * feature that says that writing 0 to a bit in *clear that is set in
798 * *status will cause an interrupt to be generated again (if allowed by
801 void ipath_clear_freeze(struct ipath_devdata *dd)
807 /* disable error interrupts, to avoid confusion */
808 ipath_write_kreg(dd, dd->ipath_kregs->kr_errormask, 0ULL);
810 /* also disable interrupts; errormask is sometimes overwriten */
811 ipath_write_kreg(dd, dd->ipath_kregs->kr_intmask, 0ULL);
814 * clear all sends, because they have may been
815 * completed by usercode while in freeze mode, and
816 * therefore would not be sent, and eventually
817 * might cause the process to run out of bufs
819 ipath_cancel_sends(dd, 0);
820 ipath_write_kreg(dd, dd->ipath_kregs->kr_control,
823 /* ensure pio avail updates continue */
824 spin_lock_irqsave(&dd->ipath_sendctrl_lock, flags);
825 ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl,
826 dd->ipath_sendctrl & ~INFINIPATH_S_PIOBUFAVAILUPD);
827 ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
828 ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl,
830 ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
831 spin_unlock_irqrestore(&dd->ipath_sendctrl_lock, flags);
834 * We just enabled pioavailupdate, so dma copy is almost certainly
835 * not yet right, so read the registers directly. Similar to init
837 for (i = 0; i < dd->ipath_pioavregs; i++) {
838 /* deal with 6110 chip bug */
839 im = (i > 3 && (dd->ipath_flags & IPATH_SWAP_PIOBUFS)) ?
841 val = ipath_read_kreg64(dd, (0x1000 / sizeof(u64)) + im);
842 dd->ipath_pioavailregs_dma[i] = cpu_to_le64(val);
843 dd->ipath_pioavailshadow[i] = val;
847 * force new interrupt if any hwerr, error or interrupt bits are
848 * still set, and clear "safe" send packet errors related to freeze
849 * and cancelling sends. Re-enable error interrupts before possible
850 * force of re-interrupt on pending interrupts.
852 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrclear, 0ULL);
853 ipath_write_kreg(dd, dd->ipath_kregs->kr_errorclear,
855 ipath_write_kreg(dd, dd->ipath_kregs->kr_errormask,
856 dd->ipath_errormask);
857 ipath_write_kreg(dd, dd->ipath_kregs->kr_intmask, -1LL);
858 ipath_write_kreg(dd, dd->ipath_kregs->kr_intclear, 0ULL);
862 /* this is separate to allow for better optimization of ipath_intr() */
864 static noinline void ipath_bad_intr(struct ipath_devdata *dd, u32 *unexpectp)
867 * sometimes happen during driver init and unload, don't want
868 * to process any interrupts at that point
871 /* this is just a bandaid, not a fix, if something goes badly
873 if (++*unexpectp > 100) {
874 if (++*unexpectp > 105) {
876 * ok, we must be taking somebody else's interrupts,
877 * due to a messed up mptable and/or PIRQ table, so
878 * unregister the interrupt. We've seen this during
879 * linuxbios development work, and it may happen in
882 if (dd->pcidev && dd->ipath_irq) {
883 ipath_dev_err(dd, "Now %u unexpected "
884 "interrupts, unregistering "
885 "interrupt handler\n",
887 ipath_dbg("free_irq of irq %d\n",
889 dd->ipath_f_free_irq(dd);
892 if (ipath_read_ireg(dd, dd->ipath_kregs->kr_intmask)) {
893 ipath_dev_err(dd, "%u unexpected interrupts, "
894 "disabling interrupts completely\n",
897 * disable all interrupts, something is very wrong
899 ipath_write_kreg(dd, dd->ipath_kregs->kr_intmask,
902 } else if (*unexpectp > 1)
903 ipath_dbg("Interrupt when not ready, should not happen, "
907 static noinline void ipath_bad_regread(struct ipath_devdata *dd)
911 /* separate routine, for better optimization of ipath_intr() */
914 * We print the message and disable interrupts, in hope of
915 * having a better chance of debugging the problem.
918 "Read of interrupt status failed (all bits set)\n");
920 /* disable all interrupts, something is very wrong */
921 ipath_write_kreg(dd, dd->ipath_kregs->kr_intmask, 0ULL);
923 ipath_dev_err(dd, "Still bad interrupt status, "
924 "unregistering interrupt\n");
925 dd->ipath_f_free_irq(dd);
926 } else if (allbits > 2) {
927 if ((allbits % 10000) == 0)
930 ipath_dev_err(dd, "Disabling interrupts, "
931 "multiple errors\n");
935 static void handle_layer_pioavail(struct ipath_devdata *dd)
940 ret = ipath_ib_piobufavail(dd->verbs_dev);
946 spin_lock_irqsave(&dd->ipath_sendctrl_lock, flags);
947 dd->ipath_sendctrl |= INFINIPATH_S_PIOINTBUFAVAIL;
948 ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl,
950 ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
951 spin_unlock_irqrestore(&dd->ipath_sendctrl_lock, flags);
955 * Handle receive interrupts for user ports; this means a user
956 * process was waiting for a packet to arrive, and didn't want
959 static void handle_urcv(struct ipath_devdata *dd, u32 istat)
966 * test_and_clear_bit(IPATH_PORT_WAITING_RCV) and
967 * test_and_clear_bit(IPATH_PORT_WAITING_URG) below
968 * would both like timely updates of the bits so that
969 * we don't pass them by unnecessarily. the rmb()
970 * here ensures that we see them promptly -- the
971 * corresponding wmb()'s are in ipath_poll_urgent()
972 * and ipath_poll_next()...
975 portr = ((istat >> INFINIPATH_I_RCVAVAIL_SHIFT) &
976 dd->ipath_i_rcvavail_mask)
977 | ((istat >> INFINIPATH_I_RCVURG_SHIFT) &
978 dd->ipath_i_rcvurg_mask);
979 for (i = 1; i < dd->ipath_cfgports; i++) {
980 struct ipath_portdata *pd = dd->ipath_pd[i];
981 if (portr & (1 << i) && pd && pd->port_cnt) {
982 if (test_and_clear_bit(IPATH_PORT_WAITING_RCV,
984 clear_bit(i + dd->ipath_r_intravail_shift,
986 wake_up_interruptible(&pd->port_wait);
988 } else if (test_and_clear_bit(IPATH_PORT_WAITING_URG,
991 wake_up_interruptible(&pd->port_wait);
996 /* only want to take one interrupt, so turn off the rcv
997 * interrupt for all the ports that we did the wakeup on
998 * (but never for kernel port)
1000 ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvctrl,
1005 irqreturn_t ipath_intr(int irq, void *data)
1007 struct ipath_devdata *dd = data;
1008 u32 istat, chk0rcv = 0;
1009 ipath_err_t estat = 0;
1011 static unsigned unexpected = 0;
1012 static const u32 port0rbits = (1U<<INFINIPATH_I_RCVAVAIL_SHIFT) |
1013 (1U<<INFINIPATH_I_RCVURG_SHIFT);
1015 ipath_stats.sps_ints++;
1017 if (dd->ipath_int_counter != (u32) -1)
1018 dd->ipath_int_counter++;
1020 if (!(dd->ipath_flags & IPATH_PRESENT)) {
1022 * This return value is not great, but we do not want the
1023 * interrupt core code to remove our interrupt handler
1024 * because we don't appear to be handling an interrupt
1025 * during a chip reset.
1031 * this needs to be flags&initted, not statusp, so we keep
1032 * taking interrupts even after link goes down, etc.
1033 * Also, we *must* clear the interrupt at some point, or we won't
1034 * take it again, which can be real bad for errors, etc...
1037 if (!(dd->ipath_flags & IPATH_INITTED)) {
1038 ipath_bad_intr(dd, &unexpected);
1043 istat = ipath_read_ireg(dd, dd->ipath_kregs->kr_intstatus);
1045 if (unlikely(!istat)) {
1046 ipath_stats.sps_nullintr++;
1047 ret = IRQ_NONE; /* not our interrupt, or already handled */
1050 if (unlikely(istat == -1)) {
1051 ipath_bad_regread(dd);
1052 /* don't know if it was our interrupt or not */
1060 if (unlikely(istat & ~dd->ipath_i_bitsextant))
1062 "interrupt with unknown interrupts %x set\n",
1063 istat & (u32) ~ dd->ipath_i_bitsextant);
1065 ipath_cdbg(VERBOSE, "intr stat=0x%x\n", istat);
1067 if (unlikely(istat & INFINIPATH_I_ERROR)) {
1068 ipath_stats.sps_errints++;
1069 estat = ipath_read_kreg64(dd,
1070 dd->ipath_kregs->kr_errorstatus);
1072 dev_info(&dd->pcidev->dev, "error interrupt (%x), "
1073 "but no error bits set!\n", istat);
1074 else if (estat == -1LL)
1076 * should we try clearing all, or hope next read
1079 ipath_dev_err(dd, "Read of error status failed "
1080 "(all bits set); ignoring\n");
1082 if (handle_errors(dd, estat))
1083 /* force calling ipath_kreceive() */
1087 if (istat & INFINIPATH_I_GPIO) {
1089 * GPIO interrupts fall in two broad classes:
1090 * GPIO_2 indicates (on some HT4xx boards) that a packet
1091 * has arrived for Port 0. Checking for this
1092 * is controlled by flag IPATH_GPIO_INTR.
1093 * GPIO_3..5 on IBA6120 Rev2 and IBA6110 Rev4 chips indicate
1094 * errors that we need to count. Checking for this
1095 * is controlled by flag IPATH_GPIO_ERRINTRS.
1100 gpiostatus = ipath_read_kreg32(
1101 dd, dd->ipath_kregs->kr_gpio_status);
1102 /* First the error-counter case.
1104 if ((gpiostatus & IPATH_GPIO_ERRINTR_MASK) &&
1105 (dd->ipath_flags & IPATH_GPIO_ERRINTRS)) {
1106 /* want to clear the bits we see asserted. */
1107 to_clear |= (gpiostatus & IPATH_GPIO_ERRINTR_MASK);
1110 * Count appropriately, clear bits out of our copy,
1111 * as they have been "handled".
1113 if (gpiostatus & (1 << IPATH_GPIO_RXUVL_BIT)) {
1114 ipath_dbg("FlowCtl on UnsupVL\n");
1115 dd->ipath_rxfc_unsupvl_errs++;
1117 if (gpiostatus & (1 << IPATH_GPIO_OVRUN_BIT)) {
1118 ipath_dbg("Overrun Threshold exceeded\n");
1119 dd->ipath_overrun_thresh_errs++;
1121 if (gpiostatus & (1 << IPATH_GPIO_LLI_BIT)) {
1122 ipath_dbg("Local Link Integrity error\n");
1123 dd->ipath_lli_errs++;
1125 gpiostatus &= ~IPATH_GPIO_ERRINTR_MASK;
1127 /* Now the Port0 Receive case */
1128 if ((gpiostatus & (1 << IPATH_GPIO_PORT0_BIT)) &&
1129 (dd->ipath_flags & IPATH_GPIO_INTR)) {
1131 * GPIO status bit 2 is set, and we expected it.
1132 * clear it and indicate in p0bits.
1133 * This probably only happens if a Port0 pkt
1134 * arrives at _just_ the wrong time, and we
1135 * handle that by seting chk0rcv;
1137 to_clear |= (1 << IPATH_GPIO_PORT0_BIT);
1138 gpiostatus &= ~(1 << IPATH_GPIO_PORT0_BIT);
1143 * Some unexpected bits remain. If they could have
1144 * caused the interrupt, complain and clear.
1145 * To avoid repetition of this condition, also clear
1146 * the mask. It is almost certainly due to error.
1148 const u32 mask = (u32) dd->ipath_gpio_mask;
1150 if (mask & gpiostatus) {
1151 ipath_dbg("Unexpected GPIO IRQ bits %x\n",
1153 to_clear |= (gpiostatus & mask);
1154 dd->ipath_gpio_mask &= ~(gpiostatus & mask);
1155 ipath_write_kreg(dd,
1156 dd->ipath_kregs->kr_gpio_mask,
1157 dd->ipath_gpio_mask);
1161 ipath_write_kreg(dd, dd->ipath_kregs->kr_gpio_clear,
1165 chk0rcv |= istat & port0rbits;
1168 * Clear the interrupt bits we found set, unless they are receive
1169 * related, in which case we already cleared them above, and don't
1170 * want to clear them again, because we might lose an interrupt.
1171 * Clear it early, so we "know" know the chip will have seen this by
1172 * the time we process the queue, and will re-interrupt if necessary.
1173 * The processor itself won't take the interrupt again until we return.
1175 ipath_write_kreg(dd, dd->ipath_kregs->kr_intclear, istat);
1178 * handle port0 receive before checking for pio buffers available,
1179 * since receives can overflow; piobuf waiters can afford a few
1180 * extra cycles, since they were waiting anyway, and user's waiting
1181 * for receive are at the bottom.
1184 ipath_kreceive(dd->ipath_pd[0]);
1185 istat &= ~port0rbits;
1188 if (istat & ((dd->ipath_i_rcvavail_mask <<
1189 INFINIPATH_I_RCVAVAIL_SHIFT)
1190 | (dd->ipath_i_rcvurg_mask <<
1191 INFINIPATH_I_RCVURG_SHIFT)))
1192 handle_urcv(dd, istat);
1194 if (istat & INFINIPATH_I_SPIOBUFAVAIL) {
1195 unsigned long flags;
1197 spin_lock_irqsave(&dd->ipath_sendctrl_lock, flags);
1198 dd->ipath_sendctrl &= ~INFINIPATH_S_PIOINTBUFAVAIL;
1199 ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl,
1200 dd->ipath_sendctrl);
1201 ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
1202 spin_unlock_irqrestore(&dd->ipath_sendctrl_lock, flags);
1204 handle_layer_pioavail(dd);