drivers/kvm/svm.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * AMD SVM support
   5  *
   6  * Copyright (C) 2006 Qumranet, Inc.
   7  *
   8  * Authors:
   9  *   Yaniv Kamay  <yaniv@qumranet.com>
  10  *   Avi Kivity   <avi@qumranet.com>
  11  *
  12  * This work is licensed under the terms of the GNU GPL, version 2.  See
  13  * the COPYING file in the top-level directory.
  14  *
  15  */
  16
  17 #include "kvm_svm.h"
  18 #include "x86_emulate.h"
  19 #include "irq.h"
  20
  21 #include <linux/module.h>
  22 #include <linux/kernel.h>
  23 #include <linux/vmalloc.h>
  24 #include <linux/highmem.h>
  25 #include <linux/sched.h>
  26
  27 #include <asm/desc.h>
  28
  29 MODULE_AUTHOR("Qumranet");
  30 MODULE_LICENSE("GPL");
  31
  32 #define IOPM_ALLOC_ORDER 2
  33 #define MSRPM_ALLOC_ORDER 1
  34
  35 #define DB_VECTOR 1
  36 #define UD_VECTOR 6
  37 #define GP_VECTOR 13
  38
  39 #define DR7_GD_MASK (1 << 13)
  40 #define DR6_BD_MASK (1 << 13)
  41
  42 #define SEG_TYPE_LDT 2
  43 #define SEG_TYPE_BUSY_TSS16 3
  44
  45 #define KVM_EFER_LMA (1 << 10)
  46 #define KVM_EFER_LME (1 << 8)
  47
  48 #define SVM_FEATURE_NPT  (1 << 0)
  49 #define SVM_FEATURE_LBRV (1 << 1)
  50 #define SVM_DEATURE_SVML (1 << 2)
  51
  52 static void kvm_reput_irq(struct vcpu_svm *svm);
  53
  54 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
  55 {
  56         return container_of(vcpu, struct vcpu_svm, vcpu);
  57 }
  58
  59 unsigned long iopm_base;
  60 unsigned long msrpm_base;
  61
  62 struct kvm_ldttss_desc {
  63         u16 limit0;
  64         u16 base0;
  65         unsigned base1 : 8, type : 5, dpl : 2, p : 1;
  66         unsigned limit1 : 4, zero0 : 3, g : 1, base2 : 8;
  67         u32 base3;
  68         u32 zero1;
  69 } __attribute__((packed));
  70
  71 struct svm_cpu_data {
  72         int cpu;
  73
  74         u64 asid_generation;
  75         u32 max_asid;
  76         u32 next_asid;
  77         struct kvm_ldttss_desc *tss_desc;
  78
  79         struct page *save_area;
  80 };
  81
  82 static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
  83 static uint32_t svm_features;
  84
  85 struct svm_init_data {
  86         int cpu;
  87         int r;
  88 };
  89
  90 static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
  91
  92 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
  93 #define MSRS_RANGE_SIZE 2048
  94 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
  95
  96 #define MAX_INST_SIZE 15
  97
  98 static inline u32 svm_has(u32 feat)
  99 {
 100         return svm_features & feat;
 101 }
 102
 103 static inline u8 pop_irq(struct kvm_vcpu *vcpu)
 104 {
 105         int word_index = __ffs(vcpu->irq_summary);
 106         int bit_index = __ffs(vcpu->irq_pending[word_index]);
 107         int irq = word_index * BITS_PER_LONG + bit_index;
 108
 109         clear_bit(bit_index, &vcpu->irq_pending[word_index]);
 110         if (!vcpu->irq_pending[word_index])
 111                 clear_bit(word_index, &vcpu->irq_summary);
 112         return irq;
 113 }
 114
 115 static inline void push_irq(struct kvm_vcpu *vcpu, u8 irq)
 116 {
 117         set_bit(irq, vcpu->irq_pending);
 118         set_bit(irq / BITS_PER_LONG, &vcpu->irq_summary);
 119 }
 120
 121 static inline void clgi(void)
 122 {
 123         asm volatile (SVM_CLGI);
 124 }
 125
 126 static inline void stgi(void)
 127 {
 128         asm volatile (SVM_STGI);
 129 }
 130
 131 static inline void invlpga(unsigned long addr, u32 asid)
 132 {
 133         asm volatile (SVM_INVLPGA :: "a"(addr), "c"(asid));
 134 }
 135
 136 static inline unsigned long kvm_read_cr2(void)
 137 {
 138         unsigned long cr2;
 139
 140         asm volatile ("mov %%cr2, %0" : "=r" (cr2));
 141         return cr2;
 142 }
 143
 144 static inline void kvm_write_cr2(unsigned long val)
 145 {
 146         asm volatile ("mov %0, %%cr2" :: "r" (val));
 147 }
 148
 149 static inline unsigned long read_dr6(void)
 150 {
 151         unsigned long dr6;
 152
 153         asm volatile ("mov %%dr6, %0" : "=r" (dr6));
 154         return dr6;
 155 }
 156
 157 static inline void write_dr6(unsigned long val)
 158 {
 159         asm volatile ("mov %0, %%dr6" :: "r" (val));
 160 }
 161
 162 static inline unsigned long read_dr7(void)
 163 {
 164         unsigned long dr7;
 165
 166         asm volatile ("mov %%dr7, %0" : "=r" (dr7));
 167         return dr7;
 168 }
 169
 170 static inline void write_dr7(unsigned long val)
 171 {
 172         asm volatile ("mov %0, %%dr7" :: "r" (val));
 173 }
 174
 175 static inline void force_new_asid(struct kvm_vcpu *vcpu)
 176 {
 177         to_svm(vcpu)->asid_generation--;
 178 }
 179
 180 static inline void flush_guest_tlb(struct kvm_vcpu *vcpu)
 181 {
 182         force_new_asid(vcpu);
 183 }
 184
 185 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
 186 {
 187         if (!(efer & KVM_EFER_LMA))
 188                 efer &= ~KVM_EFER_LME;
 189
 190         to_svm(vcpu)->vmcb->save.efer = efer | MSR_EFER_SVME_MASK;
 191         vcpu->shadow_efer = efer;
 192 }
 193
 194 static void svm_inject_gp(struct kvm_vcpu *vcpu, unsigned error_code)
 195 {
 196         struct vcpu_svm *svm = to_svm(vcpu);
 197
 198         svm->vmcb->control.event_inj =          SVM_EVTINJ_VALID |
 199                                                 SVM_EVTINJ_VALID_ERR |
 200                                                 SVM_EVTINJ_TYPE_EXEPT |
 201                                                 GP_VECTOR;
 202         svm->vmcb->control.event_inj_err = error_code;
 203 }
 204
 205 static void inject_ud(struct kvm_vcpu *vcpu)
 206 {
 207         to_svm(vcpu)->vmcb->control.event_inj = SVM_EVTINJ_VALID |
 208                                                 SVM_EVTINJ_TYPE_EXEPT |
 209                                                 UD_VECTOR;
 210 }
 211
 212 static int is_page_fault(uint32_t info)
 213 {
 214         info &= SVM_EVTINJ_VEC_MASK | SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
 215         return info == (PF_VECTOR | SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_EXEPT);
 216 }
 217
 218 static int is_external_interrupt(u32 info)
 219 {
 220         info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
 221         return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
 222 }
 223
 224 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
 225 {
 226         struct vcpu_svm *svm = to_svm(vcpu);
 227
 228         if (!svm->next_rip) {
 229                 printk(KERN_DEBUG "%s: NOP\n", __FUNCTION__);
 230                 return;
 231         }
 232         if (svm->next_rip - svm->vmcb->save.rip > MAX_INST_SIZE) {
 233                 printk(KERN_ERR "%s: ip 0x%llx next 0x%llx\n",
 234                        __FUNCTION__,
 235                        svm->vmcb->save.rip,
 236                        svm->next_rip);
 237         }
 238
 239         vcpu->rip = svm->vmcb->save.rip = svm->next_rip;
 240         svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
 241
 242         vcpu->interrupt_window_open = 1;
 243 }
 244
 245 static int has_svm(void)
 246 {
 247         uint32_t eax, ebx, ecx, edx;
 248
 249         if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD) {
 250                 printk(KERN_INFO "has_svm: not amd\n");
 251                 return 0;
 252         }
 253
 254         cpuid(0x80000000, &eax, &ebx, &ecx, &edx);
 255         if (eax < SVM_CPUID_FUNC) {
 256                 printk(KERN_INFO "has_svm: can't execute cpuid_8000000a\n");
 257                 return 0;
 258         }
 259
 260         cpuid(0x80000001, &eax, &ebx, &ecx, &edx);
 261         if (!(ecx & (1 << SVM_CPUID_FEATURE_SHIFT))) {
 262                 printk(KERN_DEBUG "has_svm: svm not available\n");
 263                 return 0;
 264         }
 265         return 1;
 266 }
 267
 268 static void svm_hardware_disable(void *garbage)
 269 {
 270         struct svm_cpu_data *svm_data
 271                 = per_cpu(svm_data, raw_smp_processor_id());
 272
 273         if (svm_data) {
 274                 uint64_t efer;
 275
 276                 wrmsrl(MSR_VM_HSAVE_PA, 0);
 277                 rdmsrl(MSR_EFER, efer);
 278                 wrmsrl(MSR_EFER, efer & ~MSR_EFER_SVME_MASK);
 279                 per_cpu(svm_data, raw_smp_processor_id()) = NULL;
 280                 __free_page(svm_data->save_area);
 281                 kfree(svm_data);
 282         }
 283 }
 284
 285 static void svm_hardware_enable(void *garbage)
 286 {
 287
 288         struct svm_cpu_data *svm_data;
 289         uint64_t efer;
 290 #ifdef CONFIG_X86_64
 291         struct desc_ptr gdt_descr;
 292 #else
 293         struct Xgt_desc_struct gdt_descr;
 294 #endif
 295         struct desc_struct *gdt;
 296         int me = raw_smp_processor_id();
 297
 298         if (!has_svm()) {
 299                 printk(KERN_ERR "svm_cpu_init: err EOPNOTSUPP on %d\n", me);
 300                 return;
 301         }
 302         svm_data = per_cpu(svm_data, me);
 303
 304         if (!svm_data) {
 305                 printk(KERN_ERR "svm_cpu_init: svm_data is NULL on %d\n",
 306                        me);
 307                 return;
 308         }
 309
 310         svm_data->asid_generation = 1;
 311         svm_data->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
 312         svm_data->next_asid = svm_data->max_asid + 1;
 313         svm_features = cpuid_edx(SVM_CPUID_FUNC);
 314
 315         asm volatile ( "sgdt %0" : "=m"(gdt_descr) );
 316         gdt = (struct desc_struct *)gdt_descr.address;
 317         svm_data->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
 318
 319         rdmsrl(MSR_EFER, efer);
 320         wrmsrl(MSR_EFER, efer | MSR_EFER_SVME_MASK);
 321
 322         wrmsrl(MSR_VM_HSAVE_PA,
 323                page_to_pfn(svm_data->save_area) << PAGE_SHIFT);
 324 }
 325
 326 static int svm_cpu_init(int cpu)
 327 {
 328         struct svm_cpu_data *svm_data;
 329         int r;
 330
 331         svm_data = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
 332         if (!svm_data)
 333                 return -ENOMEM;
 334         svm_data->cpu = cpu;
 335         svm_data->save_area = alloc_page(GFP_KERNEL);
 336         r = -ENOMEM;
 337         if (!svm_data->save_area)
 338                 goto err_1;
 339
 340         per_cpu(svm_data, cpu) = svm_data;
 341
 342         return 0;
 343
 344 err_1:
 345         kfree(svm_data);
 346         return r;
 347
 348 }
 349
 350 static void set_msr_interception(u32 *msrpm, unsigned msr,
 351                                  int read, int write)
 352 {
 353         int i;
 354
 355         for (i = 0; i < NUM_MSR_MAPS; i++) {
 356                 if (msr >= msrpm_ranges[i] &&
 357                     msr < msrpm_ranges[i] + MSRS_IN_RANGE) {
 358                         u32 msr_offset = (i * MSRS_IN_RANGE + msr -
 359                                           msrpm_ranges[i]) * 2;
 360
 361                         u32 *base = msrpm + (msr_offset / 32);
 362                         u32 msr_shift = msr_offset % 32;
 363                         u32 mask = ((write) ? 0 : 2) | ((read) ? 0 : 1);
 364                         *base = (*base & ~(0x3 << msr_shift)) |
 365                                 (mask << msr_shift);
 366                         return;
 367                 }
 368         }
 369         BUG();
 370 }
 371
 372 static __init int svm_hardware_setup(void)
 373 {
 374         int cpu;
 375         struct page *iopm_pages;
 376         struct page *msrpm_pages;
 377         void *iopm_va, *msrpm_va;
 378         int r;
 379
 380         iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
 381
 382         if (!iopm_pages)
 383                 return -ENOMEM;
 384
 385         iopm_va = page_address(iopm_pages);
 386         memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
 387         clear_bit(0x80, iopm_va); /* allow direct access to PC debug port */
 388         iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
 389
 390
 391         msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
 392
 393         r = -ENOMEM;
 394         if (!msrpm_pages)
 395                 goto err_1;
 396
 397         msrpm_va = page_address(msrpm_pages);
 398         memset(msrpm_va, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
 399         msrpm_base = page_to_pfn(msrpm_pages) << PAGE_SHIFT;
 400
 401 #ifdef CONFIG_X86_64
 402         set_msr_interception(msrpm_va, MSR_GS_BASE, 1, 1);
 403         set_msr_interception(msrpm_va, MSR_FS_BASE, 1, 1);
 404         set_msr_interception(msrpm_va, MSR_KERNEL_GS_BASE, 1, 1);
 405         set_msr_interception(msrpm_va, MSR_LSTAR, 1, 1);
 406         set_msr_interception(msrpm_va, MSR_CSTAR, 1, 1);
 407         set_msr_interception(msrpm_va, MSR_SYSCALL_MASK, 1, 1);
 408 #endif
 409         set_msr_interception(msrpm_va, MSR_K6_STAR, 1, 1);
 410         set_msr_interception(msrpm_va, MSR_IA32_SYSENTER_CS, 1, 1);
 411         set_msr_interception(msrpm_va, MSR_IA32_SYSENTER_ESP, 1, 1);
 412         set_msr_interception(msrpm_va, MSR_IA32_SYSENTER_EIP, 1, 1);
 413
 414         for_each_online_cpu(cpu) {
 415                 r = svm_cpu_init(cpu);
 416                 if (r)
 417                         goto err_2;
 418         }
 419         return 0;
 420
 421 err_2:
 422         __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER);
 423         msrpm_base = 0;
 424 err_1:
 425         __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
 426         iopm_base = 0;
 427         return r;
 428 }
 429
 430 static __exit void svm_hardware_unsetup(void)
 431 {
 432         __free_pages(pfn_to_page(msrpm_base >> PAGE_SHIFT), MSRPM_ALLOC_ORDER);
 433         __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
 434         iopm_base = msrpm_base = 0;
 435 }
 436
 437 static void init_seg(struct vmcb_seg *seg)
 438 {
 439         seg->selector = 0;
 440         seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
 441                 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
 442         seg->limit = 0xffff;
 443         seg->base = 0;
 444 }
 445
 446 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
 447 {
 448         seg->selector = 0;
 449         seg->attrib = SVM_SELECTOR_P_MASK | type;
 450         seg->limit = 0xffff;
 451         seg->base = 0;
 452 }
 453
 454 static void init_vmcb(struct vmcb *vmcb)
 455 {
 456         struct vmcb_control_area *control = &vmcb->control;
 457         struct vmcb_save_area *save = &vmcb->save;
 458
 459         control->intercept_cr_read =    INTERCEPT_CR0_MASK |
 460                                         INTERCEPT_CR3_MASK |
 461                                         INTERCEPT_CR4_MASK;
 462
 463         control->intercept_cr_write =   INTERCEPT_CR0_MASK |
 464                                         INTERCEPT_CR3_MASK |
 465                                         INTERCEPT_CR4_MASK;
 466
 467         control->intercept_dr_read =    INTERCEPT_DR0_MASK |
 468                                         INTERCEPT_DR1_MASK |
 469                                         INTERCEPT_DR2_MASK |
 470                                         INTERCEPT_DR3_MASK;
 471
 472         control->intercept_dr_write =   INTERCEPT_DR0_MASK |
 473                                         INTERCEPT_DR1_MASK |
 474                                         INTERCEPT_DR2_MASK |
 475                                         INTERCEPT_DR3_MASK |
 476                                         INTERCEPT_DR5_MASK |
 477                                         INTERCEPT_DR7_MASK;
 478
 479         control->intercept_exceptions = 1 << PF_VECTOR;
 480
 481
 482         control->intercept =    (1ULL << INTERCEPT_INTR) |
 483                                 (1ULL << INTERCEPT_NMI) |
 484                                 (1ULL << INTERCEPT_SMI) |
 485                 /*
 486                  * selective cr0 intercept bug?
 487                  *      0:   0f 22 d8                mov    %eax,%cr3
 488                  *      3:   0f 20 c0                mov    %cr0,%eax
 489                  *      6:   0d 00 00 00 80          or     $0x80000000,%eax
 490                  *      b:   0f 22 c0                mov    %eax,%cr0
 491                  * set cr3 ->interception
 492                  * get cr0 ->interception
 493                  * set cr0 -> no interception
 494                  */
 495                 /*              (1ULL << INTERCEPT_SELECTIVE_CR0) | */
 496                                 (1ULL << INTERCEPT_CPUID) |
 497                                 (1ULL << INTERCEPT_HLT) |
 498                                 (1ULL << INTERCEPT_INVLPGA) |
 499                                 (1ULL << INTERCEPT_IOIO_PROT) |
 500                                 (1ULL << INTERCEPT_MSR_PROT) |
 501                                 (1ULL << INTERCEPT_TASK_SWITCH) |
 502                                 (1ULL << INTERCEPT_SHUTDOWN) |
 503                                 (1ULL << INTERCEPT_VMRUN) |
 504                                 (1ULL << INTERCEPT_VMMCALL) |
 505                                 (1ULL << INTERCEPT_VMLOAD) |
 506                                 (1ULL << INTERCEPT_VMSAVE) |
 507                                 (1ULL << INTERCEPT_STGI) |
 508                                 (1ULL << INTERCEPT_CLGI) |
 509                                 (1ULL << INTERCEPT_SKINIT) |
 510                                 (1ULL << INTERCEPT_MONITOR) |
 511                                 (1ULL << INTERCEPT_MWAIT);
 512
 513         control->iopm_base_pa = iopm_base;
 514         control->msrpm_base_pa = msrpm_base;
 515         control->tsc_offset = 0;
 516         control->int_ctl = V_INTR_MASKING_MASK;
 517
 518         init_seg(&save->es);
 519         init_seg(&save->ss);
 520         init_seg(&save->ds);
 521         init_seg(&save->fs);
 522         init_seg(&save->gs);
 523
 524         save->cs.selector = 0xf000;
 525         /* Executable/Readable Code Segment */
 526         save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
 527                 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
 528         save->cs.limit = 0xffff;
 529         /*
 530          * cs.base should really be 0xffff0000, but vmx can't handle that, so
 531          * be consistent with it.
 532          *
 533          * Replace when we have real mode working for vmx.
 534          */
 535         save->cs.base = 0xf0000;
 536
 537         save->gdtr.limit = 0xffff;
 538         save->idtr.limit = 0xffff;
 539
 540         init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
 541         init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
 542
 543         save->efer = MSR_EFER_SVME_MASK;
 544
 545         save->dr6 = 0xffff0ff0;
 546         save->dr7 = 0x400;
 547         save->rflags = 2;
 548         save->rip = 0x0000fff0;
 549
 550         /*
 551          * cr0 val on cpu init should be 0x60000010, we enable cpu
 552          * cache by default. the orderly way is to enable cache in bios.
 553          */
 554         save->cr0 = 0x00000010 | X86_CR0_PG | X86_CR0_WP;
 555         save->cr4 = X86_CR4_PAE;
 556         /* rdx = ?? */
 557 }
 558
 559 static void svm_vcpu_reset(struct kvm_vcpu *vcpu)
 560 {
 561         struct vcpu_svm *svm = to_svm(vcpu);
 562
 563         init_vmcb(svm->vmcb);
 564 }
 565
 566 static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
 567 {
 568         struct vcpu_svm *svm;
 569         struct page *page;
 570         int err;
 571
 572         svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
 573         if (!svm) {
 574                 err = -ENOMEM;
 575                 goto out;
 576         }
 577
 578         err = kvm_vcpu_init(&svm->vcpu, kvm, id);
 579         if (err)
 580                 goto free_svm;
 581
 582         if (irqchip_in_kernel(kvm)) {
 583                 err = kvm_create_lapic(&svm->vcpu);
 584                 if (err < 0)
 585                         goto free_svm;
 586         }
 587
 588         page = alloc_page(GFP_KERNEL);
 589         if (!page) {
 590                 err = -ENOMEM;
 591                 goto uninit;
 592         }
 593
 594         svm->vmcb = page_address(page);
 595         clear_page(svm->vmcb);
 596         svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
 597         svm->asid_generation = 0;
 598         memset(svm->db_regs, 0, sizeof(svm->db_regs));
 599         init_vmcb(svm->vmcb);
 600
 601         fx_init(&svm->vcpu);
 602         svm->vcpu.fpu_active = 1;
 603         svm->vcpu.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
 604         if (svm->vcpu.vcpu_id == 0)
 605                 svm->vcpu.apic_base |= MSR_IA32_APICBASE_BSP;
 606
 607         return &svm->vcpu;
 608
 609 uninit:
 610         kvm_vcpu_uninit(&svm->vcpu);
 611 free_svm:
 612         kmem_cache_free(kvm_vcpu_cache, svm);
 613 out:
 614         return ERR_PTR(err);
 615 }
 616
 617 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
 618 {
 619         struct vcpu_svm *svm = to_svm(vcpu);
 620
 621         __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
 622         kvm_vcpu_uninit(vcpu);
 623         kmem_cache_free(kvm_vcpu_cache, svm);
 624 }
 625
 626 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
 627 {
 628         struct vcpu_svm *svm = to_svm(vcpu);
 629         int i;
 630
 631         if (unlikely(cpu != vcpu->cpu)) {
 632                 u64 tsc_this, delta;
 633
 634                 /*
 635                  * Make sure that the guest sees a monotonically
 636                  * increasing TSC.
 637                  */
 638                 rdtscll(tsc_this);
 639                 delta = vcpu->host_tsc - tsc_this;
 640                 svm->vmcb->control.tsc_offset += delta;
 641                 vcpu->cpu = cpu;
 642                 kvm_migrate_apic_timer(vcpu);
 643         }
 644
 645         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
 646                 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
 647 }
 648
 649 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
 650 {
 651         struct vcpu_svm *svm = to_svm(vcpu);
 652         int i;
 653
 654         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
 655                 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
 656
 657         rdtscll(vcpu->host_tsc);
 658 }
 659
 660 static void svm_vcpu_decache(struct kvm_vcpu *vcpu)
 661 {
 662 }
 663
 664 static void svm_cache_regs(struct kvm_vcpu *vcpu)
 665 {
 666         struct vcpu_svm *svm = to_svm(vcpu);
 667
 668         vcpu->regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
 669         vcpu->regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
 670         vcpu->rip = svm->vmcb->save.rip;
 671 }
 672
 673 static void svm_decache_regs(struct kvm_vcpu *vcpu)
 674 {
 675         struct vcpu_svm *svm = to_svm(vcpu);
 676         svm->vmcb->save.rax = vcpu->regs[VCPU_REGS_RAX];
 677         svm->vmcb->save.rsp = vcpu->regs[VCPU_REGS_RSP];
 678         svm->vmcb->save.rip = vcpu->rip;
 679 }
 680
 681 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
 682 {
 683         return to_svm(vcpu)->vmcb->save.rflags;
 684 }
 685
 686 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
 687 {
 688         to_svm(vcpu)->vmcb->save.rflags = rflags;
 689 }
 690
 691 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
 692 {
 693         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
 694
 695         switch (seg) {
 696         case VCPU_SREG_CS: return &save->cs;
 697         case VCPU_SREG_DS: return &save->ds;
 698         case VCPU_SREG_ES: return &save->es;
 699         case VCPU_SREG_FS: return &save->fs;
 700         case VCPU_SREG_GS: return &save->gs;
 701         case VCPU_SREG_SS: return &save->ss;
 702         case VCPU_SREG_TR: return &save->tr;
 703         case VCPU_SREG_LDTR: return &save->ldtr;
 704         }
 705         BUG();
 706         return NULL;
 707 }
 708
 709 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
 710 {
 711         struct vmcb_seg *s = svm_seg(vcpu, seg);
 712
 713         return s->base;
 714 }
 715
 716 static void svm_get_segment(struct kvm_vcpu *vcpu,
 717                             struct kvm_segment *var, int seg)
 718 {
 719         struct vmcb_seg *s = svm_seg(vcpu, seg);
 720
 721         var->base = s->base;
 722         var->limit = s->limit;
 723         var->selector = s->selector;
 724         var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
 725         var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
 726         var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
 727         var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
 728         var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
 729         var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
 730         var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
 731         var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
 732         var->unusable = !var->present;
 733 }
 734
 735 static void svm_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
 736 {
 737         struct vcpu_svm *svm = to_svm(vcpu);
 738
 739         dt->limit = svm->vmcb->save.idtr.limit;
 740         dt->base = svm->vmcb->save.idtr.base;
 741 }
 742
 743 static void svm_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
 744 {
 745         struct vcpu_svm *svm = to_svm(vcpu);
 746
 747         svm->vmcb->save.idtr.limit = dt->limit;
 748         svm->vmcb->save.idtr.base = dt->base ;
 749 }
 750
 751 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
 752 {
 753         struct vcpu_svm *svm = to_svm(vcpu);
 754
 755         dt->limit = svm->vmcb->save.gdtr.limit;
 756         dt->base = svm->vmcb->save.gdtr.base;
 757 }
 758
 759 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
 760 {
 761         struct vcpu_svm *svm = to_svm(vcpu);
 762
 763         svm->vmcb->save.gdtr.limit = dt->limit;
 764         svm->vmcb->save.gdtr.base = dt->base ;
 765 }
 766
 767 static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
 768 {
 769 }
 770
 771 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
 772 {
 773         struct vcpu_svm *svm = to_svm(vcpu);
 774
 775 #ifdef CONFIG_X86_64
 776         if (vcpu->shadow_efer & KVM_EFER_LME) {
 777                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
 778                         vcpu->shadow_efer |= KVM_EFER_LMA;
 779                         svm->vmcb->save.efer |= KVM_EFER_LMA | KVM_EFER_LME;
 780                 }
 781
 782                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG) ) {
 783                         vcpu->shadow_efer &= ~KVM_EFER_LMA;
 784                         svm->vmcb->save.efer &= ~(KVM_EFER_LMA | KVM_EFER_LME);
 785                 }
 786         }
 787 #endif
 788         if ((vcpu->cr0 & X86_CR0_TS) && !(cr0 & X86_CR0_TS)) {
 789                 svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
 790                 vcpu->fpu_active = 1;
 791         }
 792
 793         vcpu->cr0 = cr0;
 794         cr0 |= X86_CR0_PG | X86_CR0_WP;
 795         cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
 796         svm->vmcb->save.cr0 = cr0;
 797 }
 798
 799 static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
 800 {
 801        vcpu->cr4 = cr4;
 802        to_svm(vcpu)->vmcb->save.cr4 = cr4 | X86_CR4_PAE;
 803 }
 804
 805 static void svm_set_segment(struct kvm_vcpu *vcpu,
 806                             struct kvm_segment *var, int seg)
 807 {
 808         struct vcpu_svm *svm = to_svm(vcpu);
 809         struct vmcb_seg *s = svm_seg(vcpu, seg);
 810
 811         s->base = var->base;
 812         s->limit = var->limit;
 813         s->selector = var->selector;
 814         if (var->unusable)
 815                 s->attrib = 0;
 816         else {
 817                 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
 818                 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
 819                 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
 820                 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
 821                 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
 822                 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
 823                 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
 824                 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
 825         }
 826         if (seg == VCPU_SREG_CS)
 827                 svm->vmcb->save.cpl
 828                         = (svm->vmcb->save.cs.attrib
 829                            >> SVM_SELECTOR_DPL_SHIFT) & 3;
 830
 831 }
 832
 833 /* FIXME:
 834
 835         svm(vcpu)->vmcb->control.int_ctl &= ~V_TPR_MASK;
 836         svm(vcpu)->vmcb->control.int_ctl |= (sregs->cr8 & V_TPR_MASK);
 837
 838 */
 839
 840 static int svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_debug_guest *dbg)
 841 {
 842         return -EOPNOTSUPP;
 843 }
 844
 845 static int svm_get_irq(struct kvm_vcpu *vcpu)
 846 {
 847         struct vcpu_svm *svm = to_svm(vcpu);
 848         u32 exit_int_info = svm->vmcb->control.exit_int_info;
 849
 850         if (is_external_interrupt(exit_int_info))
 851                 return exit_int_info & SVM_EVTINJ_VEC_MASK;
 852         return -1;
 853 }
 854
 855 static void load_host_msrs(struct kvm_vcpu *vcpu)
 856 {
 857 #ifdef CONFIG_X86_64
 858         wrmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
 859 #endif
 860 }
 861
 862 static void save_host_msrs(struct kvm_vcpu *vcpu)
 863 {
 864 #ifdef CONFIG_X86_64
 865         rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
 866 #endif
 867 }
 868
 869 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *svm_data)
 870 {
 871         if (svm_data->next_asid > svm_data->max_asid) {
 872                 ++svm_data->asid_generation;
 873                 svm_data->next_asid = 1;
 874                 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
 875         }
 876
 877         svm->vcpu.cpu = svm_data->cpu;
 878         svm->asid_generation = svm_data->asid_generation;
 879         svm->vmcb->control.asid = svm_data->next_asid++;
 880 }
 881
 882 static unsigned long svm_get_dr(struct kvm_vcpu *vcpu, int dr)
 883 {
 884         return to_svm(vcpu)->db_regs[dr];
 885 }
 886
 887 static void svm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long value,
 888                        int *exception)
 889 {
 890         struct vcpu_svm *svm = to_svm(vcpu);
 891
 892         *exception = 0;
 893
 894         if (svm->vmcb->save.dr7 & DR7_GD_MASK) {
 895                 svm->vmcb->save.dr7 &= ~DR7_GD_MASK;
 896                 svm->vmcb->save.dr6 |= DR6_BD_MASK;
 897                 *exception = DB_VECTOR;
 898                 return;
 899         }
 900
 901         switch (dr) {
 902         case 0 ... 3:
 903                 svm->db_regs[dr] = value;
 904                 return;
 905         case 4 ... 5:
 906                 if (vcpu->cr4 & X86_CR4_DE) {
 907                         *exception = UD_VECTOR;
 908                         return;
 909                 }
 910         case 7: {
 911                 if (value & ~((1ULL << 32) - 1)) {
 912                         *exception = GP_VECTOR;
 913                         return;
 914                 }
 915                 svm->vmcb->save.dr7 = value;
 916                 return;
 917         }
 918         default:
 919                 printk(KERN_DEBUG "%s: unexpected dr %u\n",
 920                        __FUNCTION__, dr);
 921                 *exception = UD_VECTOR;
 922                 return;
 923         }
 924 }
 925
 926 static int pf_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
 927 {
 928         u32 exit_int_info = svm->vmcb->control.exit_int_info;
 929         struct kvm *kvm = svm->vcpu.kvm;
 930         u64 fault_address;
 931         u32 error_code;
 932         enum emulation_result er;
 933         int r;
 934
 935         if (!irqchip_in_kernel(kvm) &&
 936                 is_external_interrupt(exit_int_info))
 937                 push_irq(&svm->vcpu, exit_int_info & SVM_EVTINJ_VEC_MASK);
 938
 939         mutex_lock(&kvm->lock);
 940
 941         fault_address  = svm->vmcb->control.exit_info_2;
 942         error_code = svm->vmcb->control.exit_info_1;
 943         r = kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code);
 944         if (r < 0) {
 945                 mutex_unlock(&kvm->lock);
 946                 return r;
 947         }
 948         if (!r) {
 949                 mutex_unlock(&kvm->lock);
 950                 return 1;
 951         }
 952         er = emulate_instruction(&svm->vcpu, kvm_run, fault_address,
 953                                  error_code);
 954         mutex_unlock(&kvm->lock);
 955
 956         switch (er) {
 957         case EMULATE_DONE:
 958                 return 1;
 959         case EMULATE_DO_MMIO:
 960                 ++svm->vcpu.stat.mmio_exits;
 961                 return 0;
 962         case EMULATE_FAIL:
 963                 kvm_report_emulation_failure(&svm->vcpu, "pagetable");
 964                 break;
 965         default:
 966                 BUG();
 967         }
 968
 969         kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
 970         return 0;
 971 }
 972
 973 static int nm_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
 974 {
 975         svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
 976         if (!(svm->vcpu.cr0 & X86_CR0_TS))
 977                 svm->vmcb->save.cr0 &= ~X86_CR0_TS;
 978         svm->vcpu.fpu_active = 1;
 979
 980         return 1;
 981 }
 982
 983 static int shutdown_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
 984 {
 985         /*
 986          * VMCB is undefined after a SHUTDOWN intercept
 987          * so reinitialize it.
 988          */
 989         clear_page(svm->vmcb);
 990         init_vmcb(svm->vmcb);
 991
 992         kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
 993         return 0;
 994 }
 995
 996 static int io_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
 997 {
 998         u32 io_info = svm->vmcb->control.exit_info_1; //address size bug?
 999         int size, down, in, string, rep;
1000         unsigned port;
1001
1002         ++svm->vcpu.stat.io_exits;
1003
1004         svm->next_rip = svm->vmcb->control.exit_info_2;
1005
1006         string = (io_info & SVM_IOIO_STR_MASK) != 0;
1007
1008         if (string) {
1009                 if (emulate_instruction(&svm->vcpu, kvm_run, 0, 0) == EMULATE_DO_MMIO)
1010                         return 0;
1011                 return 1;
1012         }
1013
1014         in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
1015         port = io_info >> 16;
1016         size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
1017         rep = (io_info & SVM_IOIO_REP_MASK) != 0;
1018         down = (svm->vmcb->save.rflags & X86_EFLAGS_DF) != 0;
1019
1020         return kvm_emulate_pio(&svm->vcpu, kvm_run, in, size, port);
1021 }
1022
1023 static int nop_on_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1024 {
1025         return 1;
1026 }
1027
1028 static int halt_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1029 {
1030         svm->next_rip = svm->vmcb->save.rip + 1;
1031         skip_emulated_instruction(&svm->vcpu);
1032         return kvm_emulate_halt(&svm->vcpu);
1033 }
1034
1035 static int vmmcall_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1036 {
1037         svm->next_rip = svm->vmcb->save.rip + 3;
1038         skip_emulated_instruction(&svm->vcpu);
1039         return kvm_hypercall(&svm->vcpu, kvm_run);
1040 }
1041
1042 static int invalid_op_interception(struct vcpu_svm *svm,
1043                                    struct kvm_run *kvm_run)
1044 {
1045         inject_ud(&svm->vcpu);
1046         return 1;
1047 }
1048
1049 static int task_switch_interception(struct vcpu_svm *svm,
1050                                     struct kvm_run *kvm_run)
1051 {
1052         pr_unimpl(&svm->vcpu, "%s: task switch is unsupported\n", __FUNCTION__);
1053         kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
1054         return 0;
1055 }
1056
1057 static int cpuid_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1058 {
1059         svm->next_rip = svm->vmcb->save.rip + 2;
1060         kvm_emulate_cpuid(&svm->vcpu);
1061         return 1;
1062 }
1063
1064 static int emulate_on_interception(struct vcpu_svm *svm,
1065                                    struct kvm_run *kvm_run)
1066 {
1067         if (emulate_instruction(&svm->vcpu, NULL, 0, 0) != EMULATE_DONE)
1068                 pr_unimpl(&svm->vcpu, "%s: failed\n", __FUNCTION__);
1069         return 1;
1070 }
1071
1072 static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
1073 {
1074         struct vcpu_svm *svm = to_svm(vcpu);
1075
1076         switch (ecx) {
1077         case MSR_IA32_TIME_STAMP_COUNTER: {
1078                 u64 tsc;
1079
1080                 rdtscll(tsc);
1081                 *data = svm->vmcb->control.tsc_offset + tsc;
1082                 break;
1083         }
1084         case MSR_K6_STAR:
1085                 *data = svm->vmcb->save.star;
1086                 break;
1087 #ifdef CONFIG_X86_64
1088         case MSR_LSTAR:
1089                 *data = svm->vmcb->save.lstar;
1090                 break;
1091         case MSR_CSTAR:
1092                 *data = svm->vmcb->save.cstar;
1093                 break;
1094         case MSR_KERNEL_GS_BASE:
1095                 *data = svm->vmcb->save.kernel_gs_base;
1096                 break;
1097         case MSR_SYSCALL_MASK:
1098                 *data = svm->vmcb->save.sfmask;
1099                 break;
1100 #endif
1101         case MSR_IA32_SYSENTER_CS:
1102                 *data = svm->vmcb->save.sysenter_cs;
1103                 break;
1104         case MSR_IA32_SYSENTER_EIP:
1105                 *data = svm->vmcb->save.sysenter_eip;
1106                 break;
1107         case MSR_IA32_SYSENTER_ESP:
1108                 *data = svm->vmcb->save.sysenter_esp;
1109                 break;
1110         default:
1111                 return kvm_get_msr_common(vcpu, ecx, data);
1112         }
1113         return 0;
1114 }
1115
1116 static int rdmsr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1117 {
1118         u32 ecx = svm->vcpu.regs[VCPU_REGS_RCX];
1119         u64 data;
1120
1121         if (svm_get_msr(&svm->vcpu, ecx, &data))
1122                 svm_inject_gp(&svm->vcpu, 0);
1123         else {
1124                 svm->vmcb->save.rax = data & 0xffffffff;
1125                 svm->vcpu.regs[VCPU_REGS_RDX] = data >> 32;
1126                 svm->next_rip = svm->vmcb->save.rip + 2;
1127                 skip_emulated_instruction(&svm->vcpu);
1128         }
1129         return 1;
1130 }
1131
1132 static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
1133 {
1134         struct vcpu_svm *svm = to_svm(vcpu);
1135
1136         switch (ecx) {
1137         case MSR_IA32_TIME_STAMP_COUNTER: {
1138                 u64 tsc;
1139
1140                 rdtscll(tsc);
1141                 svm->vmcb->control.tsc_offset = data - tsc;
1142                 break;
1143         }
1144         case MSR_K6_STAR:
1145                 svm->vmcb->save.star = data;
1146                 break;
1147 #ifdef CONFIG_X86_64
1148         case MSR_LSTAR:
1149                 svm->vmcb->save.lstar = data;
1150                 break;
1151         case MSR_CSTAR:
1152                 svm->vmcb->save.cstar = data;
1153                 break;
1154         case MSR_KERNEL_GS_BASE:
1155                 svm->vmcb->save.kernel_gs_base = data;
1156                 break;
1157         case MSR_SYSCALL_MASK:
1158                 svm->vmcb->save.sfmask = data;
1159                 break;
1160 #endif
1161         case MSR_IA32_SYSENTER_CS:
1162                 svm->vmcb->save.sysenter_cs = data;
1163                 break;
1164         case MSR_IA32_SYSENTER_EIP:
1165                 svm->vmcb->save.sysenter_eip = data;
1166                 break;
1167         case MSR_IA32_SYSENTER_ESP:
1168                 svm->vmcb->save.sysenter_esp = data;
1169                 break;
1170         default:
1171                 return kvm_set_msr_common(vcpu, ecx, data);
1172         }
1173         return 0;
1174 }
1175
1176 static int wrmsr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1177 {
1178         u32 ecx = svm->vcpu.regs[VCPU_REGS_RCX];
1179         u64 data = (svm->vmcb->save.rax & -1u)
1180                 | ((u64)(svm->vcpu.regs[VCPU_REGS_RDX] & -1u) << 32);
1181         svm->next_rip = svm->vmcb->save.rip + 2;
1182         if (svm_set_msr(&svm->vcpu, ecx, data))
1183                 svm_inject_gp(&svm->vcpu, 0);
1184         else
1185                 skip_emulated_instruction(&svm->vcpu);
1186         return 1;
1187 }
1188
1189 static int msr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1190 {
1191         if (svm->vmcb->control.exit_info_1)
1192                 return wrmsr_interception(svm, kvm_run);
1193         else
1194                 return rdmsr_interception(svm, kvm_run);
1195 }
1196
1197 static int interrupt_window_interception(struct vcpu_svm *svm,
1198                                    struct kvm_run *kvm_run)
1199 {
1200         svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VINTR);
1201         svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
1202         /*
1203          * If the user space waits to inject interrupts, exit as soon as
1204          * possible
1205          */
1206         if (kvm_run->request_interrupt_window &&
1207             !svm->vcpu.irq_summary) {
1208                 ++svm->vcpu.stat.irq_window_exits;
1209                 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
1210                 return 0;
1211         }
1212
1213         return 1;
1214 }
1215
1216 static int (*svm_exit_handlers[])(struct vcpu_svm *svm,
1217                                       struct kvm_run *kvm_run) = {
1218         [SVM_EXIT_READ_CR0]                     = emulate_on_interception,
1219         [SVM_EXIT_READ_CR3]                     = emulate_on_interception,
1220         [SVM_EXIT_READ_CR4]                     = emulate_on_interception,
1221         /* for now: */
1222         [SVM_EXIT_WRITE_CR0]                    = emulate_on_interception,
1223         [SVM_EXIT_WRITE_CR3]                    = emulate_on_interception,
1224         [SVM_EXIT_WRITE_CR4]                    = emulate_on_interception,
1225         [SVM_EXIT_READ_DR0]                     = emulate_on_interception,
1226         [SVM_EXIT_READ_DR1]                     = emulate_on_interception,
1227         [SVM_EXIT_READ_DR2]                     = emulate_on_interception,
1228         [SVM_EXIT_READ_DR3]                     = emulate_on_interception,
1229         [SVM_EXIT_WRITE_DR0]                    = emulate_on_interception,
1230         [SVM_EXIT_WRITE_DR1]                    = emulate_on_interception,
1231         [SVM_EXIT_WRITE_DR2]                    = emulate_on_interception,
1232         [SVM_EXIT_WRITE_DR3]                    = emulate_on_interception,
1233         [SVM_EXIT_WRITE_DR5]                    = emulate_on_interception,
1234         [SVM_EXIT_WRITE_DR7]                    = emulate_on_interception,
1235         [SVM_EXIT_EXCP_BASE + PF_VECTOR]        = pf_interception,
1236         [SVM_EXIT_EXCP_BASE + NM_VECTOR]        = nm_interception,
1237         [SVM_EXIT_INTR]                         = nop_on_interception,
1238         [SVM_EXIT_NMI]                          = nop_on_interception,
1239         [SVM_EXIT_SMI]                          = nop_on_interception,
1240         [SVM_EXIT_INIT]                         = nop_on_interception,
1241         [SVM_EXIT_VINTR]                        = interrupt_window_interception,
1242         /* [SVM_EXIT_CR0_SEL_WRITE]             = emulate_on_interception, */
1243         [SVM_EXIT_CPUID]                        = cpuid_interception,
1244         [SVM_EXIT_HLT]                          = halt_interception,
1245         [SVM_EXIT_INVLPG]                       = emulate_on_interception,
1246         [SVM_EXIT_INVLPGA]                      = invalid_op_interception,
1247         [SVM_EXIT_IOIO]                         = io_interception,
1248         [SVM_EXIT_MSR]                          = msr_interception,
1249         [SVM_EXIT_TASK_SWITCH]                  = task_switch_interception,
1250         [SVM_EXIT_SHUTDOWN]                     = shutdown_interception,
1251         [SVM_EXIT_VMRUN]                        = invalid_op_interception,
1252         [SVM_EXIT_VMMCALL]                      = vmmcall_interception,
1253         [SVM_EXIT_VMLOAD]                       = invalid_op_interception,
1254         [SVM_EXIT_VMSAVE]                       = invalid_op_interception,
1255         [SVM_EXIT_STGI]                         = invalid_op_interception,
1256         [SVM_EXIT_CLGI]                         = invalid_op_interception,
1257         [SVM_EXIT_SKINIT]                       = invalid_op_interception,
1258         [SVM_EXIT_MONITOR]                      = invalid_op_interception,
1259         [SVM_EXIT_MWAIT]                        = invalid_op_interception,
1260 };
1261
1262
1263 static int handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
1264 {
1265         struct vcpu_svm *svm = to_svm(vcpu);
1266         u32 exit_code = svm->vmcb->control.exit_code;
1267
1268         kvm_reput_irq(svm);
1269
1270         if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
1271                 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
1272                 kvm_run->fail_entry.hardware_entry_failure_reason
1273                         = svm->vmcb->control.exit_code;
1274                 return 0;
1275         }
1276
1277         if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
1278             exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR)
1279                 printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x "
1280                        "exit_code 0x%x\n",
1281                        __FUNCTION__, svm->vmcb->control.exit_int_info,
1282                        exit_code);
1283
1284         if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
1285             || svm_exit_handlers[exit_code] == 0) {
1286                 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
1287                 kvm_run->hw.hardware_exit_reason = exit_code;
1288                 return 0;
1289         }
1290
1291         return svm_exit_handlers[exit_code](svm, kvm_run);
1292 }
1293
1294 static void reload_tss(struct kvm_vcpu *vcpu)
1295 {
1296         int cpu = raw_smp_processor_id();
1297
1298         struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu);
1299         svm_data->tss_desc->type = 9; //available 32/64-bit TSS
1300         load_TR_desc();
1301 }
1302
1303 static void pre_svm_run(struct vcpu_svm *svm)
1304 {
1305         int cpu = raw_smp_processor_id();
1306
1307         struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu);
1308
1309         svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
1310         if (svm->vcpu.cpu != cpu ||
1311             svm->asid_generation != svm_data->asid_generation)
1312                 new_asid(svm, svm_data);
1313 }
1314
1315
1316 static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
1317 {
1318         struct vmcb_control_area *control;
1319
1320         control = &svm->vmcb->control;
1321         control->int_vector = irq;
1322         control->int_ctl &= ~V_INTR_PRIO_MASK;
1323         control->int_ctl |= V_IRQ_MASK |
1324                 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
1325 }
1326
1327 static void svm_set_irq(struct kvm_vcpu *vcpu, int irq)
1328 {
1329         struct vcpu_svm *svm = to_svm(vcpu);
1330
1331         svm_inject_irq(svm, irq);
1332 }
1333
1334 static void svm_intr_assist(struct kvm_vcpu *vcpu)
1335 {
1336         struct vcpu_svm *svm = to_svm(vcpu);
1337         struct vmcb *vmcb = svm->vmcb;
1338         int intr_vector = -1;
1339
1340         kvm_inject_pending_timer_irqs(vcpu);
1341         if ((vmcb->control.exit_int_info & SVM_EVTINJ_VALID) &&
1342             ((vmcb->control.exit_int_info & SVM_EVTINJ_TYPE_MASK) == 0)) {
1343                 intr_vector = vmcb->control.exit_int_info &
1344                               SVM_EVTINJ_VEC_MASK;
1345                 vmcb->control.exit_int_info = 0;
1346                 svm_inject_irq(svm, intr_vector);
1347                 return;
1348         }
1349
1350         if (vmcb->control.int_ctl & V_IRQ_MASK)
1351                 return;
1352
1353         if (!kvm_cpu_has_interrupt(vcpu))
1354                 return;
1355
1356         if (!(vmcb->save.rflags & X86_EFLAGS_IF) ||
1357             (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) ||
1358             (vmcb->control.event_inj & SVM_EVTINJ_VALID)) {
1359                 /* unable to deliver irq, set pending irq */
1360                 vmcb->control.intercept |= (1ULL << INTERCEPT_VINTR);
1361                 svm_inject_irq(svm, 0x0);
1362                 return;
1363         }
1364         /* Okay, we can deliver the interrupt: grab it and update PIC state. */
1365         intr_vector = kvm_cpu_get_interrupt(vcpu);
1366         svm_inject_irq(svm, intr_vector);
1367         kvm_timer_intr_post(vcpu, intr_vector);
1368 }
1369
1370 static void kvm_reput_irq(struct vcpu_svm *svm)
1371 {
1372         struct vmcb_control_area *control = &svm->vmcb->control;
1373
1374         if ((control->int_ctl & V_IRQ_MASK)
1375             && !irqchip_in_kernel(svm->vcpu.kvm)) {
1376                 control->int_ctl &= ~V_IRQ_MASK;
1377                 push_irq(&svm->vcpu, control->int_vector);
1378         }
1379
1380         svm->vcpu.interrupt_window_open =
1381                 !(control->int_state & SVM_INTERRUPT_SHADOW_MASK);
1382 }
1383
1384 static void svm_do_inject_vector(struct vcpu_svm *svm)
1385 {
1386         struct kvm_vcpu *vcpu = &svm->vcpu;
1387         int word_index = __ffs(vcpu->irq_summary);
1388         int bit_index = __ffs(vcpu->irq_pending[word_index]);
1389         int irq = word_index * BITS_PER_LONG + bit_index;
1390
1391         clear_bit(bit_index, &vcpu->irq_pending[word_index]);
1392         if (!vcpu->irq_pending[word_index])
1393                 clear_bit(word_index, &vcpu->irq_summary);
1394         svm_inject_irq(svm, irq);
1395 }
1396
1397 static void do_interrupt_requests(struct kvm_vcpu *vcpu,
1398                                        struct kvm_run *kvm_run)
1399 {
1400         struct vcpu_svm *svm = to_svm(vcpu);
1401         struct vmcb_control_area *control = &svm->vmcb->control;
1402
1403         svm->vcpu.interrupt_window_open =
1404                 (!(control->int_state & SVM_INTERRUPT_SHADOW_MASK) &&
1405                  (svm->vmcb->save.rflags & X86_EFLAGS_IF));
1406
1407         if (svm->vcpu.interrupt_window_open && svm->vcpu.irq_summary)
1408                 /*
1409                  * If interrupts enabled, and not blocked by sti or mov ss. Good.
1410                  */
1411                 svm_do_inject_vector(svm);
1412
1413         /*
1414          * Interrupts blocked.  Wait for unblock.
1415          */
1416         if (!svm->vcpu.interrupt_window_open &&
1417             (svm->vcpu.irq_summary || kvm_run->request_interrupt_window)) {
1418                 control->intercept |= 1ULL << INTERCEPT_VINTR;
1419         } else
1420                 control->intercept &= ~(1ULL << INTERCEPT_VINTR);
1421 }
1422
1423 static void save_db_regs(unsigned long *db_regs)
1424 {
1425         asm volatile ("mov %%dr0, %0" : "=r"(db_regs[0]));
1426         asm volatile ("mov %%dr1, %0" : "=r"(db_regs[1]));
1427         asm volatile ("mov %%dr2, %0" : "=r"(db_regs[2]));
1428         asm volatile ("mov %%dr3, %0" : "=r"(db_regs[3]));
1429 }
1430
1431 static void load_db_regs(unsigned long *db_regs)
1432 {
1433         asm volatile ("mov %0, %%dr0" : : "r"(db_regs[0]));
1434         asm volatile ("mov %0, %%dr1" : : "r"(db_regs[1]));
1435         asm volatile ("mov %0, %%dr2" : : "r"(db_regs[2]));
1436         asm volatile ("mov %0, %%dr3" : : "r"(db_regs[3]));
1437 }
1438
1439 static void svm_flush_tlb(struct kvm_vcpu *vcpu)
1440 {
1441         force_new_asid(vcpu);
1442 }
1443
1444 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
1445 {
1446 }
1447
1448 static void svm_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1449 {
1450         struct vcpu_svm *svm = to_svm(vcpu);
1451         u16 fs_selector;
1452         u16 gs_selector;
1453         u16 ldt_selector;
1454
1455         pre_svm_run(svm);
1456
1457         save_host_msrs(vcpu);
1458         fs_selector = read_fs();
1459         gs_selector = read_gs();
1460         ldt_selector = read_ldt();
1461         svm->host_cr2 = kvm_read_cr2();
1462         svm->host_dr6 = read_dr6();
1463         svm->host_dr7 = read_dr7();
1464         svm->vmcb->save.cr2 = vcpu->cr2;
1465
1466         if (svm->vmcb->save.dr7 & 0xff) {
1467                 write_dr7(0);
1468                 save_db_regs(svm->host_db_regs);
1469                 load_db_regs(svm->db_regs);
1470         }
1471
1472         clgi();
1473
1474         local_irq_enable();
1475
1476         asm volatile (
1477 #ifdef CONFIG_X86_64
1478                 "push %%rbx; push %%rcx; push %%rdx;"
1479                 "push %%rsi; push %%rdi; push %%rbp;"
1480                 "push %%r8;  push %%r9;  push %%r10; push %%r11;"
1481                 "push %%r12; push %%r13; push %%r14; push %%r15;"
1482 #else
1483                 "push %%ebx; push %%ecx; push %%edx;"
1484                 "push %%esi; push %%edi; push %%ebp;"
1485 #endif
1486
1487 #ifdef CONFIG_X86_64
1488                 "mov %c[rbx](%[svm]), %%rbx \n\t"
1489                 "mov %c[rcx](%[svm]), %%rcx \n\t"
1490                 "mov %c[rdx](%[svm]), %%rdx \n\t"
1491                 "mov %c[rsi](%[svm]), %%rsi \n\t"
1492                 "mov %c[rdi](%[svm]), %%rdi \n\t"
1493                 "mov %c[rbp](%[svm]), %%rbp \n\t"
1494                 "mov %c[r8](%[svm]),  %%r8  \n\t"
1495                 "mov %c[r9](%[svm]),  %%r9  \n\t"
1496                 "mov %c[r10](%[svm]), %%r10 \n\t"
1497                 "mov %c[r11](%[svm]), %%r11 \n\t"
1498                 "mov %c[r12](%[svm]), %%r12 \n\t"
1499                 "mov %c[r13](%[svm]), %%r13 \n\t"
1500                 "mov %c[r14](%[svm]), %%r14 \n\t"
1501                 "mov %c[r15](%[svm]), %%r15 \n\t"
1502 #else
1503                 "mov %c[rbx](%[svm]), %%ebx \n\t"
1504                 "mov %c[rcx](%[svm]), %%ecx \n\t"
1505                 "mov %c[rdx](%[svm]), %%edx \n\t"
1506                 "mov %c[rsi](%[svm]), %%esi \n\t"
1507                 "mov %c[rdi](%[svm]), %%edi \n\t"
1508                 "mov %c[rbp](%[svm]), %%ebp \n\t"
1509 #endif
1510
1511 #ifdef CONFIG_X86_64
1512                 /* Enter guest mode */
1513                 "push %%rax \n\t"
1514                 "mov %c[vmcb](%[svm]), %%rax \n\t"
1515                 SVM_VMLOAD "\n\t"
1516                 SVM_VMRUN "\n\t"
1517                 SVM_VMSAVE "\n\t"
1518                 "pop %%rax \n\t"
1519 #else
1520                 /* Enter guest mode */
1521                 "push %%eax \n\t"
1522                 "mov %c[vmcb](%[svm]), %%eax \n\t"
1523                 SVM_VMLOAD "\n\t"
1524                 SVM_VMRUN "\n\t"
1525                 SVM_VMSAVE "\n\t"
1526                 "pop %%eax \n\t"
1527 #endif
1528
1529                 /* Save guest registers, load host registers */
1530 #ifdef CONFIG_X86_64
1531                 "mov %%rbx, %c[rbx](%[svm]) \n\t"
1532                 "mov %%rcx, %c[rcx](%[svm]) \n\t"
1533                 "mov %%rdx, %c[rdx](%[svm]) \n\t"
1534                 "mov %%rsi, %c[rsi](%[svm]) \n\t"
1535                 "mov %%rdi, %c[rdi](%[svm]) \n\t"
1536                 "mov %%rbp, %c[rbp](%[svm]) \n\t"
1537                 "mov %%r8,  %c[r8](%[svm]) \n\t"
1538                 "mov %%r9,  %c[r9](%[svm]) \n\t"
1539                 "mov %%r10, %c[r10](%[svm]) \n\t"
1540                 "mov %%r11, %c[r11](%[svm]) \n\t"
1541                 "mov %%r12, %c[r12](%[svm]) \n\t"
1542                 "mov %%r13, %c[r13](%[svm]) \n\t"
1543                 "mov %%r14, %c[r14](%[svm]) \n\t"
1544                 "mov %%r15, %c[r15](%[svm]) \n\t"
1545
1546                 "pop  %%r15; pop  %%r14; pop  %%r13; pop  %%r12;"
1547                 "pop  %%r11; pop  %%r10; pop  %%r9;  pop  %%r8;"
1548                 "pop  %%rbp; pop  %%rdi; pop  %%rsi;"
1549                 "pop  %%rdx; pop  %%rcx; pop  %%rbx; \n\t"
1550 #else
1551                 "mov %%ebx, %c[rbx](%[svm]) \n\t"
1552                 "mov %%ecx, %c[rcx](%[svm]) \n\t"
1553                 "mov %%edx, %c[rdx](%[svm]) \n\t"
1554                 "mov %%esi, %c[rsi](%[svm]) \n\t"
1555                 "mov %%edi, %c[rdi](%[svm]) \n\t"
1556                 "mov %%ebp, %c[rbp](%[svm]) \n\t"
1557
1558                 "pop  %%ebp; pop  %%edi; pop  %%esi;"
1559                 "pop  %%edx; pop  %%ecx; pop  %%ebx; \n\t"
1560 #endif
1561                 :
1562                 : [svm]"a"(svm),
1563                   [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
1564                   [rbx]"i"(offsetof(struct vcpu_svm,vcpu.regs[VCPU_REGS_RBX])),
1565                   [rcx]"i"(offsetof(struct vcpu_svm,vcpu.regs[VCPU_REGS_RCX])),
1566                   [rdx]"i"(offsetof(struct vcpu_svm,vcpu.regs[VCPU_REGS_RDX])),
1567                   [rsi]"i"(offsetof(struct vcpu_svm,vcpu.regs[VCPU_REGS_RSI])),
1568                   [rdi]"i"(offsetof(struct vcpu_svm,vcpu.regs[VCPU_REGS_RDI])),
1569                   [rbp]"i"(offsetof(struct vcpu_svm,vcpu.regs[VCPU_REGS_RBP]))
1570 #ifdef CONFIG_X86_64
1571                   ,[r8 ]"i"(offsetof(struct vcpu_svm,vcpu.regs[VCPU_REGS_R8])),
1572                   [r9 ]"i"(offsetof(struct vcpu_svm,vcpu.regs[VCPU_REGS_R9 ])),
1573                   [r10]"i"(offsetof(struct vcpu_svm,vcpu.regs[VCPU_REGS_R10])),
1574                   [r11]"i"(offsetof(struct vcpu_svm,vcpu.regs[VCPU_REGS_R11])),
1575                   [r12]"i"(offsetof(struct vcpu_svm,vcpu.regs[VCPU_REGS_R12])),
1576                   [r13]"i"(offsetof(struct vcpu_svm,vcpu.regs[VCPU_REGS_R13])),
1577                   [r14]"i"(offsetof(struct vcpu_svm,vcpu.regs[VCPU_REGS_R14])),
1578                   [r15]"i"(offsetof(struct vcpu_svm,vcpu.regs[VCPU_REGS_R15]))
1579 #endif
1580                 : "cc", "memory" );
1581
1582         local_irq_disable();
1583
1584         stgi();
1585
1586         if ((svm->vmcb->save.dr7 & 0xff))
1587                 load_db_regs(svm->host_db_regs);
1588
1589         vcpu->cr2 = svm->vmcb->save.cr2;
1590
1591         write_dr6(svm->host_dr6);
1592         write_dr7(svm->host_dr7);
1593         kvm_write_cr2(svm->host_cr2);
1594
1595         load_fs(fs_selector);
1596         load_gs(gs_selector);
1597         load_ldt(ldt_selector);
1598         load_host_msrs(vcpu);
1599
1600         reload_tss(vcpu);
1601
1602         svm->next_rip = 0;
1603 }
1604
1605 static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
1606 {
1607         struct vcpu_svm *svm = to_svm(vcpu);
1608
1609         svm->vmcb->save.cr3 = root;
1610         force_new_asid(vcpu);
1611
1612         if (vcpu->fpu_active) {
1613                 svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR);
1614                 svm->vmcb->save.cr0 |= X86_CR0_TS;
1615                 vcpu->fpu_active = 0;
1616         }
1617 }
1618
1619 static void svm_inject_page_fault(struct kvm_vcpu *vcpu,
1620                                   unsigned long  addr,
1621                                   uint32_t err_code)
1622 {
1623         struct vcpu_svm *svm = to_svm(vcpu);
1624         uint32_t exit_int_info = svm->vmcb->control.exit_int_info;
1625
1626         ++vcpu->stat.pf_guest;
1627
1628         if (is_page_fault(exit_int_info)) {
1629
1630                 svm->vmcb->control.event_inj_err = 0;
1631                 svm->vmcb->control.event_inj =  SVM_EVTINJ_VALID |
1632                                                 SVM_EVTINJ_VALID_ERR |
1633                                                 SVM_EVTINJ_TYPE_EXEPT |
1634                                                 DF_VECTOR;
1635                 return;
1636         }
1637         vcpu->cr2 = addr;
1638         svm->vmcb->save.cr2 = addr;
1639         svm->vmcb->control.event_inj =  SVM_EVTINJ_VALID |
1640                                         SVM_EVTINJ_VALID_ERR |
1641                                         SVM_EVTINJ_TYPE_EXEPT |
1642                                         PF_VECTOR;
1643         svm->vmcb->control.event_inj_err = err_code;
1644 }
1645
1646
1647 static int is_disabled(void)
1648 {
1649         u64 vm_cr;
1650
1651         rdmsrl(MSR_VM_CR, vm_cr);
1652         if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
1653                 return 1;
1654
1655         return 0;
1656 }
1657
1658 static void
1659 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
1660 {
1661         /*
1662          * Patch in the VMMCALL instruction:
1663          */
1664         hypercall[0] = 0x0f;
1665         hypercall[1] = 0x01;
1666         hypercall[2] = 0xd9;
1667         hypercall[3] = 0xc3;
1668 }
1669
1670 static void svm_check_processor_compat(void *rtn)
1671 {
1672         *(int *)rtn = 0;
1673 }
1674
1675 static struct kvm_x86_ops svm_x86_ops = {
1676         .cpu_has_kvm_support = has_svm,
1677         .disabled_by_bios = is_disabled,
1678         .hardware_setup = svm_hardware_setup,
1679         .hardware_unsetup = svm_hardware_unsetup,
1680         .check_processor_compatibility = svm_check_processor_compat,
1681         .hardware_enable = svm_hardware_enable,
1682         .hardware_disable = svm_hardware_disable,
1683
1684         .vcpu_create = svm_create_vcpu,
1685         .vcpu_free = svm_free_vcpu,
1686         .vcpu_reset = svm_vcpu_reset,
1687
1688         .prepare_guest_switch = svm_prepare_guest_switch,
1689         .vcpu_load = svm_vcpu_load,
1690         .vcpu_put = svm_vcpu_put,
1691         .vcpu_decache = svm_vcpu_decache,
1692
1693         .set_guest_debug = svm_guest_debug,
1694         .get_msr = svm_get_msr,
1695         .set_msr = svm_set_msr,
1696         .get_segment_base = svm_get_segment_base,
1697         .get_segment = svm_get_segment,
1698         .set_segment = svm_set_segment,
1699         .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
1700         .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
1701         .set_cr0 = svm_set_cr0,
1702         .set_cr3 = svm_set_cr3,
1703         .set_cr4 = svm_set_cr4,
1704         .set_efer = svm_set_efer,
1705         .get_idt = svm_get_idt,
1706         .set_idt = svm_set_idt,
1707         .get_gdt = svm_get_gdt,
1708         .set_gdt = svm_set_gdt,
1709         .get_dr = svm_get_dr,
1710         .set_dr = svm_set_dr,
1711         .cache_regs = svm_cache_regs,
1712         .decache_regs = svm_decache_regs,
1713         .get_rflags = svm_get_rflags,
1714         .set_rflags = svm_set_rflags,
1715
1716         .tlb_flush = svm_flush_tlb,
1717         .inject_page_fault = svm_inject_page_fault,
1718
1719         .inject_gp = svm_inject_gp,
1720
1721         .run = svm_vcpu_run,
1722         .handle_exit = handle_exit,
1723         .skip_emulated_instruction = skip_emulated_instruction,
1724         .patch_hypercall = svm_patch_hypercall,
1725         .get_irq = svm_get_irq,
1726         .set_irq = svm_set_irq,
1727         .inject_pending_irq = svm_intr_assist,
1728         .inject_pending_vectors = do_interrupt_requests,
1729 };
1730
1731 static int __init svm_init(void)
1732 {
1733         return kvm_init_x86(&svm_x86_ops, sizeof(struct vcpu_svm),
1734                               THIS_MODULE);
1735 }
1736
1737 static void __exit svm_exit(void)
1738 {
1739         kvm_exit_x86();
1740 }
1741
1742 module_init(svm_init)
1743 module_exit(svm_exit)