drivers/kvm/vmx.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * This module enables machines with Intel VT-x extensions to run virtual
   5  * machines without emulation or binary translation.
   6  *
   7  * Copyright (C) 2006 Qumranet, Inc.
   8  *
   9  * Authors:
  10  *   Avi Kivity   <avi@qumranet.com>
  11  *   Yaniv Kamay  <yaniv@qumranet.com>
  12  *
  13  * This work is licensed under the terms of the GNU GPL, version 2.  See
  14  * the COPYING file in the top-level directory.
  15  *
  16  */
  17
  18 #include "kvm.h"
  19 #include "x86.h"
  20 #include "x86_emulate.h"
  21 #include "irq.h"
  22 #include "vmx.h"
  23 #include "segment_descriptor.h"
  24
  25 #include <linux/module.h>
  26 #include <linux/kernel.h>
  27 #include <linux/mm.h>
  28 #include <linux/highmem.h>
  29 #include <linux/sched.h>
  30 #include <linux/moduleparam.h>
  31
  32 #include <asm/io.h>
  33 #include <asm/desc.h>
  34
  35 MODULE_AUTHOR("Qumranet");
  36 MODULE_LICENSE("GPL");
  37
  38 static int bypass_guest_pf = 1;
  39 module_param(bypass_guest_pf, bool, 0);
  40
  41 struct vmcs {
  42         u32 revision_id;
  43         u32 abort;
  44         char data[0];
  45 };
  46
  47 struct vcpu_vmx {
  48         struct kvm_vcpu       vcpu;
  49         int                   launched;
  50         u8                    fail;
  51         u32                   idt_vectoring_info;
  52         struct kvm_msr_entry *guest_msrs;
  53         struct kvm_msr_entry *host_msrs;
  54         int                   nmsrs;
  55         int                   save_nmsrs;
  56         int                   msr_offset_efer;
  57 #ifdef CONFIG_X86_64
  58         int                   msr_offset_kernel_gs_base;
  59 #endif
  60         struct vmcs          *vmcs;
  61         struct {
  62                 int           loaded;
  63                 u16           fs_sel, gs_sel, ldt_sel;
  64                 int           gs_ldt_reload_needed;
  65                 int           fs_reload_needed;
  66                 int           guest_efer_loaded;
  67         } host_state;
  68         struct {
  69                 struct {
  70                         bool pending;
  71                         u8 vector;
  72                         unsigned rip;
  73                 } irq;
  74         } rmode;
  75 };
  76
  77 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
  78 {
  79         return container_of(vcpu, struct vcpu_vmx, vcpu);
  80 }
  81
  82 static int init_rmode_tss(struct kvm *kvm);
  83
  84 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
  85 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
  86
  87 static struct page *vmx_io_bitmap_a;
  88 static struct page *vmx_io_bitmap_b;
  89
  90 static struct vmcs_config {
  91         int size;
  92         int order;
  93         u32 revision_id;
  94         u32 pin_based_exec_ctrl;
  95         u32 cpu_based_exec_ctrl;
  96         u32 cpu_based_2nd_exec_ctrl;
  97         u32 vmexit_ctrl;
  98         u32 vmentry_ctrl;
  99 } vmcs_config;
 100
 101 #define VMX_SEGMENT_FIELD(seg)                                  \
 102         [VCPU_SREG_##seg] = {                                   \
 103                 .selector = GUEST_##seg##_SELECTOR,             \
 104                 .base = GUEST_##seg##_BASE,                     \
 105                 .limit = GUEST_##seg##_LIMIT,                   \
 106                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
 107         }
 108
 109 static struct kvm_vmx_segment_field {
 110         unsigned selector;
 111         unsigned base;
 112         unsigned limit;
 113         unsigned ar_bytes;
 114 } kvm_vmx_segment_fields[] = {
 115         VMX_SEGMENT_FIELD(CS),
 116         VMX_SEGMENT_FIELD(DS),
 117         VMX_SEGMENT_FIELD(ES),
 118         VMX_SEGMENT_FIELD(FS),
 119         VMX_SEGMENT_FIELD(GS),
 120         VMX_SEGMENT_FIELD(SS),
 121         VMX_SEGMENT_FIELD(TR),
 122         VMX_SEGMENT_FIELD(LDTR),
 123 };
 124
 125 /*
 126  * Keep MSR_K6_STAR at the end, as setup_msrs() will try to optimize it
 127  * away by decrementing the array size.
 128  */
 129 static const u32 vmx_msr_index[] = {
 130 #ifdef CONFIG_X86_64
 131         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR, MSR_KERNEL_GS_BASE,
 132 #endif
 133         MSR_EFER, MSR_K6_STAR,
 134 };
 135 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
 136
 137 static void load_msrs(struct kvm_msr_entry *e, int n)
 138 {
 139         int i;
 140
 141         for (i = 0; i < n; ++i)
 142                 wrmsrl(e[i].index, e[i].data);
 143 }
 144
 145 static void save_msrs(struct kvm_msr_entry *e, int n)
 146 {
 147         int i;
 148
 149         for (i = 0; i < n; ++i)
 150                 rdmsrl(e[i].index, e[i].data);
 151 }
 152
 153 static inline int is_page_fault(u32 intr_info)
 154 {
 155         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 156                              INTR_INFO_VALID_MASK)) ==
 157                 (INTR_TYPE_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
 158 }
 159
 160 static inline int is_no_device(u32 intr_info)
 161 {
 162         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 163                              INTR_INFO_VALID_MASK)) ==
 164                 (INTR_TYPE_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
 165 }
 166
 167 static inline int is_invalid_opcode(u32 intr_info)
 168 {
 169         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 170                              INTR_INFO_VALID_MASK)) ==
 171                 (INTR_TYPE_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
 172 }
 173
 174 static inline int is_external_interrupt(u32 intr_info)
 175 {
 176         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
 177                 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
 178 }
 179
 180 static inline int cpu_has_vmx_tpr_shadow(void)
 181 {
 182         return (vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW);
 183 }
 184
 185 static inline int vm_need_tpr_shadow(struct kvm *kvm)
 186 {
 187         return ((cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm)));
 188 }
 189
 190 static inline int cpu_has_secondary_exec_ctrls(void)
 191 {
 192         return (vmcs_config.cpu_based_exec_ctrl &
 193                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS);
 194 }
 195
 196 static inline int cpu_has_vmx_virtualize_apic_accesses(void)
 197 {
 198         return (vmcs_config.cpu_based_2nd_exec_ctrl &
 199                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
 200 }
 201
 202 static inline int vm_need_virtualize_apic_accesses(struct kvm *kvm)
 203 {
 204         return ((cpu_has_vmx_virtualize_apic_accesses()) &&
 205                 (irqchip_in_kernel(kvm)));
 206 }
 207
 208 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
 209 {
 210         int i;
 211
 212         for (i = 0; i < vmx->nmsrs; ++i)
 213                 if (vmx->guest_msrs[i].index == msr)
 214                         return i;
 215         return -1;
 216 }
 217
 218 static struct kvm_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
 219 {
 220         int i;
 221
 222         i = __find_msr_index(vmx, msr);
 223         if (i >= 0)
 224                 return &vmx->guest_msrs[i];
 225         return NULL;
 226 }
 227
 228 static void vmcs_clear(struct vmcs *vmcs)
 229 {
 230         u64 phys_addr = __pa(vmcs);
 231         u8 error;
 232
 233         asm volatile (ASM_VMX_VMCLEAR_RAX "; setna %0"
 234                       : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
 235                       : "cc", "memory");
 236         if (error)
 237                 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
 238                        vmcs, phys_addr);
 239 }
 240
 241 static void __vcpu_clear(void *arg)
 242 {
 243         struct vcpu_vmx *vmx = arg;
 244         int cpu = raw_smp_processor_id();
 245
 246         if (vmx->vcpu.cpu == cpu)
 247                 vmcs_clear(vmx->vmcs);
 248         if (per_cpu(current_vmcs, cpu) == vmx->vmcs)
 249                 per_cpu(current_vmcs, cpu) = NULL;
 250         rdtscll(vmx->vcpu.host_tsc);
 251 }
 252
 253 static void vcpu_clear(struct vcpu_vmx *vmx)
 254 {
 255         if (vmx->vcpu.cpu == -1)
 256                 return;
 257         smp_call_function_single(vmx->vcpu.cpu, __vcpu_clear, vmx, 0, 1);
 258         vmx->launched = 0;
 259 }
 260
 261 static unsigned long vmcs_readl(unsigned long field)
 262 {
 263         unsigned long value;
 264
 265         asm volatile (ASM_VMX_VMREAD_RDX_RAX
 266                       : "=a"(value) : "d"(field) : "cc");
 267         return value;
 268 }
 269
 270 static u16 vmcs_read16(unsigned long field)
 271 {
 272         return vmcs_readl(field);
 273 }
 274
 275 static u32 vmcs_read32(unsigned long field)
 276 {
 277         return vmcs_readl(field);
 278 }
 279
 280 static u64 vmcs_read64(unsigned long field)
 281 {
 282 #ifdef CONFIG_X86_64
 283         return vmcs_readl(field);
 284 #else
 285         return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
 286 #endif
 287 }
 288
 289 static noinline void vmwrite_error(unsigned long field, unsigned long value)
 290 {
 291         printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
 292                field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
 293         dump_stack();
 294 }
 295
 296 static void vmcs_writel(unsigned long field, unsigned long value)
 297 {
 298         u8 error;
 299
 300         asm volatile (ASM_VMX_VMWRITE_RAX_RDX "; setna %0"
 301                        : "=q"(error) : "a"(value), "d"(field) : "cc");
 302         if (unlikely(error))
 303                 vmwrite_error(field, value);
 304 }
 305
 306 static void vmcs_write16(unsigned long field, u16 value)
 307 {
 308         vmcs_writel(field, value);
 309 }
 310
 311 static void vmcs_write32(unsigned long field, u32 value)
 312 {
 313         vmcs_writel(field, value);
 314 }
 315
 316 static void vmcs_write64(unsigned long field, u64 value)
 317 {
 318 #ifdef CONFIG_X86_64
 319         vmcs_writel(field, value);
 320 #else
 321         vmcs_writel(field, value);
 322         asm volatile ("");
 323         vmcs_writel(field+1, value >> 32);
 324 #endif
 325 }
 326
 327 static void vmcs_clear_bits(unsigned long field, u32 mask)
 328 {
 329         vmcs_writel(field, vmcs_readl(field) & ~mask);
 330 }
 331
 332 static void vmcs_set_bits(unsigned long field, u32 mask)
 333 {
 334         vmcs_writel(field, vmcs_readl(field) | mask);
 335 }
 336
 337 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
 338 {
 339         u32 eb;
 340
 341         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR);
 342         if (!vcpu->fpu_active)
 343                 eb |= 1u << NM_VECTOR;
 344         if (vcpu->guest_debug.enabled)
 345                 eb |= 1u << 1;
 346         if (vcpu->rmode.active)
 347                 eb = ~0;
 348         vmcs_write32(EXCEPTION_BITMAP, eb);
 349 }
 350
 351 static void reload_tss(void)
 352 {
 353 #ifndef CONFIG_X86_64
 354
 355         /*
 356          * VT restores TR but not its size.  Useless.
 357          */
 358         struct descriptor_table gdt;
 359         struct segment_descriptor *descs;
 360
 361         get_gdt(&gdt);
 362         descs = (void *)gdt.base;
 363         descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
 364         load_TR_desc();
 365 #endif
 366 }
 367
 368 static void load_transition_efer(struct vcpu_vmx *vmx)
 369 {
 370         int efer_offset = vmx->msr_offset_efer;
 371         u64 host_efer = vmx->host_msrs[efer_offset].data;
 372         u64 guest_efer = vmx->guest_msrs[efer_offset].data;
 373         u64 ignore_bits;
 374
 375         if (efer_offset < 0)
 376                 return;
 377         /*
 378          * NX is emulated; LMA and LME handled by hardware; SCE meaninless
 379          * outside long mode
 380          */
 381         ignore_bits = EFER_NX | EFER_SCE;
 382 #ifdef CONFIG_X86_64
 383         ignore_bits |= EFER_LMA | EFER_LME;
 384         /* SCE is meaningful only in long mode on Intel */
 385         if (guest_efer & EFER_LMA)
 386                 ignore_bits &= ~(u64)EFER_SCE;
 387 #endif
 388         if ((guest_efer & ~ignore_bits) == (host_efer & ~ignore_bits))
 389                 return;
 390
 391         vmx->host_state.guest_efer_loaded = 1;
 392         guest_efer &= ~ignore_bits;
 393         guest_efer |= host_efer & ignore_bits;
 394         wrmsrl(MSR_EFER, guest_efer);
 395         vmx->vcpu.stat.efer_reload++;
 396 }
 397
 398 static void reload_host_efer(struct vcpu_vmx *vmx)
 399 {
 400         if (vmx->host_state.guest_efer_loaded) {
 401                 vmx->host_state.guest_efer_loaded = 0;
 402                 load_msrs(vmx->host_msrs + vmx->msr_offset_efer, 1);
 403         }
 404 }
 405
 406 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
 407 {
 408         struct vcpu_vmx *vmx = to_vmx(vcpu);
 409
 410         if (vmx->host_state.loaded)
 411                 return;
 412
 413         vmx->host_state.loaded = 1;
 414         /*
 415          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
 416          * allow segment selectors with cpl > 0 or ti == 1.
 417          */
 418         vmx->host_state.ldt_sel = read_ldt();
 419         vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
 420         vmx->host_state.fs_sel = read_fs();
 421         if (!(vmx->host_state.fs_sel & 7)) {
 422                 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
 423                 vmx->host_state.fs_reload_needed = 0;
 424         } else {
 425                 vmcs_write16(HOST_FS_SELECTOR, 0);
 426                 vmx->host_state.fs_reload_needed = 1;
 427         }
 428         vmx->host_state.gs_sel = read_gs();
 429         if (!(vmx->host_state.gs_sel & 7))
 430                 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
 431         else {
 432                 vmcs_write16(HOST_GS_SELECTOR, 0);
 433                 vmx->host_state.gs_ldt_reload_needed = 1;
 434         }
 435
 436 #ifdef CONFIG_X86_64
 437         vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
 438         vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
 439 #else
 440         vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
 441         vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
 442 #endif
 443
 444 #ifdef CONFIG_X86_64
 445         if (is_long_mode(&vmx->vcpu))
 446                 save_msrs(vmx->host_msrs +
 447                           vmx->msr_offset_kernel_gs_base, 1);
 448
 449 #endif
 450         load_msrs(vmx->guest_msrs, vmx->save_nmsrs);
 451         load_transition_efer(vmx);
 452 }
 453
 454 static void vmx_load_host_state(struct vcpu_vmx *vmx)
 455 {
 456         unsigned long flags;
 457
 458         if (!vmx->host_state.loaded)
 459                 return;
 460
 461         ++vmx->vcpu.stat.host_state_reload;
 462         vmx->host_state.loaded = 0;
 463         if (vmx->host_state.fs_reload_needed)
 464                 load_fs(vmx->host_state.fs_sel);
 465         if (vmx->host_state.gs_ldt_reload_needed) {
 466                 load_ldt(vmx->host_state.ldt_sel);
 467                 /*
 468                  * If we have to reload gs, we must take care to
 469                  * preserve our gs base.
 470                  */
 471                 local_irq_save(flags);
 472                 load_gs(vmx->host_state.gs_sel);
 473 #ifdef CONFIG_X86_64
 474                 wrmsrl(MSR_GS_BASE, vmcs_readl(HOST_GS_BASE));
 475 #endif
 476                 local_irq_restore(flags);
 477         }
 478         reload_tss();
 479         save_msrs(vmx->guest_msrs, vmx->save_nmsrs);
 480         load_msrs(vmx->host_msrs, vmx->save_nmsrs);
 481         reload_host_efer(vmx);
 482 }
 483
 484 /*
 485  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
 486  * vcpu mutex is already taken.
 487  */
 488 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
 489 {
 490         struct vcpu_vmx *vmx = to_vmx(vcpu);
 491         u64 phys_addr = __pa(vmx->vmcs);
 492         u64 tsc_this, delta;
 493
 494         if (vcpu->cpu != cpu) {
 495                 vcpu_clear(vmx);
 496                 kvm_migrate_apic_timer(vcpu);
 497         }
 498
 499         if (per_cpu(current_vmcs, cpu) != vmx->vmcs) {
 500                 u8 error;
 501
 502                 per_cpu(current_vmcs, cpu) = vmx->vmcs;
 503                 asm volatile (ASM_VMX_VMPTRLD_RAX "; setna %0"
 504                               : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
 505                               : "cc");
 506                 if (error)
 507                         printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
 508                                vmx->vmcs, phys_addr);
 509         }
 510
 511         if (vcpu->cpu != cpu) {
 512                 struct descriptor_table dt;
 513                 unsigned long sysenter_esp;
 514
 515                 vcpu->cpu = cpu;
 516                 /*
 517                  * Linux uses per-cpu TSS and GDT, so set these when switching
 518                  * processors.
 519                  */
 520                 vmcs_writel(HOST_TR_BASE, read_tr_base()); /* 22.2.4 */
 521                 get_gdt(&dt);
 522                 vmcs_writel(HOST_GDTR_BASE, dt.base);   /* 22.2.4 */
 523
 524                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
 525                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
 526
 527                 /*
 528                  * Make sure the time stamp counter is monotonous.
 529                  */
 530                 rdtscll(tsc_this);
 531                 delta = vcpu->host_tsc - tsc_this;
 532                 vmcs_write64(TSC_OFFSET, vmcs_read64(TSC_OFFSET) + delta);
 533         }
 534 }
 535
 536 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
 537 {
 538         vmx_load_host_state(to_vmx(vcpu));
 539 }
 540
 541 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
 542 {
 543         if (vcpu->fpu_active)
 544                 return;
 545         vcpu->fpu_active = 1;
 546         vmcs_clear_bits(GUEST_CR0, X86_CR0_TS);
 547         if (vcpu->cr0 & X86_CR0_TS)
 548                 vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
 549         update_exception_bitmap(vcpu);
 550 }
 551
 552 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
 553 {
 554         if (!vcpu->fpu_active)
 555                 return;
 556         vcpu->fpu_active = 0;
 557         vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
 558         update_exception_bitmap(vcpu);
 559 }
 560
 561 static void vmx_vcpu_decache(struct kvm_vcpu *vcpu)
 562 {
 563         vcpu_clear(to_vmx(vcpu));
 564 }
 565
 566 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
 567 {
 568         return vmcs_readl(GUEST_RFLAGS);
 569 }
 570
 571 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
 572 {
 573         if (vcpu->rmode.active)
 574                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
 575         vmcs_writel(GUEST_RFLAGS, rflags);
 576 }
 577
 578 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
 579 {
 580         unsigned long rip;
 581         u32 interruptibility;
 582
 583         rip = vmcs_readl(GUEST_RIP);
 584         rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
 585         vmcs_writel(GUEST_RIP, rip);
 586
 587         /*
 588          * We emulated an instruction, so temporary interrupt blocking
 589          * should be removed, if set.
 590          */
 591         interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
 592         if (interruptibility & 3)
 593                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
 594                              interruptibility & ~3);
 595         vcpu->interrupt_window_open = 1;
 596 }
 597
 598 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
 599                                 bool has_error_code, u32 error_code)
 600 {
 601         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
 602                      nr | INTR_TYPE_EXCEPTION
 603                      | (has_error_code ? INTR_INFO_DELIEVER_CODE_MASK : 0)
 604                      | INTR_INFO_VALID_MASK);
 605         if (has_error_code)
 606                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
 607 }
 608
 609 static bool vmx_exception_injected(struct kvm_vcpu *vcpu)
 610 {
 611         struct vcpu_vmx *vmx = to_vmx(vcpu);
 612
 613         return !(vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
 614 }
 615
 616 static void vmx_inject_ud(struct kvm_vcpu *vcpu)
 617 {
 618         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
 619                      UD_VECTOR |
 620                      INTR_TYPE_EXCEPTION |
 621                      INTR_INFO_VALID_MASK);
 622 }
 623
 624 /*
 625  * Swap MSR entry in host/guest MSR entry array.
 626  */
 627 #ifdef CONFIG_X86_64
 628 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
 629 {
 630         struct kvm_msr_entry tmp;
 631
 632         tmp = vmx->guest_msrs[to];
 633         vmx->guest_msrs[to] = vmx->guest_msrs[from];
 634         vmx->guest_msrs[from] = tmp;
 635         tmp = vmx->host_msrs[to];
 636         vmx->host_msrs[to] = vmx->host_msrs[from];
 637         vmx->host_msrs[from] = tmp;
 638 }
 639 #endif
 640
 641 /*
 642  * Set up the vmcs to automatically save and restore system
 643  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
 644  * mode, as fiddling with msrs is very expensive.
 645  */
 646 static void setup_msrs(struct vcpu_vmx *vmx)
 647 {
 648         int save_nmsrs;
 649
 650         save_nmsrs = 0;
 651 #ifdef CONFIG_X86_64
 652         if (is_long_mode(&vmx->vcpu)) {
 653                 int index;
 654
 655                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
 656                 if (index >= 0)
 657                         move_msr_up(vmx, index, save_nmsrs++);
 658                 index = __find_msr_index(vmx, MSR_LSTAR);
 659                 if (index >= 0)
 660                         move_msr_up(vmx, index, save_nmsrs++);
 661                 index = __find_msr_index(vmx, MSR_CSTAR);
 662                 if (index >= 0)
 663                         move_msr_up(vmx, index, save_nmsrs++);
 664                 index = __find_msr_index(vmx, MSR_KERNEL_GS_BASE);
 665                 if (index >= 0)
 666                         move_msr_up(vmx, index, save_nmsrs++);
 667                 /*
 668                  * MSR_K6_STAR is only needed on long mode guests, and only
 669                  * if efer.sce is enabled.
 670                  */
 671                 index = __find_msr_index(vmx, MSR_K6_STAR);
 672                 if ((index >= 0) && (vmx->vcpu.shadow_efer & EFER_SCE))
 673                         move_msr_up(vmx, index, save_nmsrs++);
 674         }
 675 #endif
 676         vmx->save_nmsrs = save_nmsrs;
 677
 678 #ifdef CONFIG_X86_64
 679         vmx->msr_offset_kernel_gs_base =
 680                 __find_msr_index(vmx, MSR_KERNEL_GS_BASE);
 681 #endif
 682         vmx->msr_offset_efer = __find_msr_index(vmx, MSR_EFER);
 683 }
 684
 685 /*
 686  * reads and returns guest's timestamp counter "register"
 687  * guest_tsc = host_tsc + tsc_offset    -- 21.3
 688  */
 689 static u64 guest_read_tsc(void)
 690 {
 691         u64 host_tsc, tsc_offset;
 692
 693         rdtscll(host_tsc);
 694         tsc_offset = vmcs_read64(TSC_OFFSET);
 695         return host_tsc + tsc_offset;
 696 }
 697
 698 /*
 699  * writes 'guest_tsc' into guest's timestamp counter "register"
 700  * guest_tsc = host_tsc + tsc_offset ==> tsc_offset = guest_tsc - host_tsc
 701  */
 702 static void guest_write_tsc(u64 guest_tsc)
 703 {
 704         u64 host_tsc;
 705
 706         rdtscll(host_tsc);
 707         vmcs_write64(TSC_OFFSET, guest_tsc - host_tsc);
 708 }
 709
 710 /*
 711  * Reads an msr value (of 'msr_index') into 'pdata'.
 712  * Returns 0 on success, non-0 otherwise.
 713  * Assumes vcpu_load() was already called.
 714  */
 715 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
 716 {
 717         u64 data;
 718         struct kvm_msr_entry *msr;
 719
 720         if (!pdata) {
 721                 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
 722                 return -EINVAL;
 723         }
 724
 725         switch (msr_index) {
 726 #ifdef CONFIG_X86_64
 727         case MSR_FS_BASE:
 728                 data = vmcs_readl(GUEST_FS_BASE);
 729                 break;
 730         case MSR_GS_BASE:
 731                 data = vmcs_readl(GUEST_GS_BASE);
 732                 break;
 733         case MSR_EFER:
 734                 return kvm_get_msr_common(vcpu, msr_index, pdata);
 735 #endif
 736         case MSR_IA32_TIME_STAMP_COUNTER:
 737                 data = guest_read_tsc();
 738                 break;
 739         case MSR_IA32_SYSENTER_CS:
 740                 data = vmcs_read32(GUEST_SYSENTER_CS);
 741                 break;
 742         case MSR_IA32_SYSENTER_EIP:
 743                 data = vmcs_readl(GUEST_SYSENTER_EIP);
 744                 break;
 745         case MSR_IA32_SYSENTER_ESP:
 746                 data = vmcs_readl(GUEST_SYSENTER_ESP);
 747                 break;
 748         default:
 749                 msr = find_msr_entry(to_vmx(vcpu), msr_index);
 750                 if (msr) {
 751                         data = msr->data;
 752                         break;
 753                 }
 754                 return kvm_get_msr_common(vcpu, msr_index, pdata);
 755         }
 756
 757         *pdata = data;
 758         return 0;
 759 }
 760
 761 /*
 762  * Writes msr value into into the appropriate "register".
 763  * Returns 0 on success, non-0 otherwise.
 764  * Assumes vcpu_load() was already called.
 765  */
 766 static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
 767 {
 768         struct vcpu_vmx *vmx = to_vmx(vcpu);
 769         struct kvm_msr_entry *msr;
 770         int ret = 0;
 771
 772         switch (msr_index) {
 773 #ifdef CONFIG_X86_64
 774         case MSR_EFER:
 775                 ret = kvm_set_msr_common(vcpu, msr_index, data);
 776                 if (vmx->host_state.loaded) {
 777                         reload_host_efer(vmx);
 778                         load_transition_efer(vmx);
 779                 }
 780                 break;
 781         case MSR_FS_BASE:
 782                 vmcs_writel(GUEST_FS_BASE, data);
 783                 break;
 784         case MSR_GS_BASE:
 785                 vmcs_writel(GUEST_GS_BASE, data);
 786                 break;
 787 #endif
 788         case MSR_IA32_SYSENTER_CS:
 789                 vmcs_write32(GUEST_SYSENTER_CS, data);
 790                 break;
 791         case MSR_IA32_SYSENTER_EIP:
 792                 vmcs_writel(GUEST_SYSENTER_EIP, data);
 793                 break;
 794         case MSR_IA32_SYSENTER_ESP:
 795                 vmcs_writel(GUEST_SYSENTER_ESP, data);
 796                 break;
 797         case MSR_IA32_TIME_STAMP_COUNTER:
 798                 guest_write_tsc(data);
 799                 break;
 800         default:
 801                 msr = find_msr_entry(vmx, msr_index);
 802                 if (msr) {
 803                         msr->data = data;
 804                         if (vmx->host_state.loaded)
 805                                 load_msrs(vmx->guest_msrs, vmx->save_nmsrs);
 806                         break;
 807                 }
 808                 ret = kvm_set_msr_common(vcpu, msr_index, data);
 809         }
 810
 811         return ret;
 812 }
 813
 814 /*
 815  * Sync the rsp and rip registers into the vcpu structure.  This allows
 816  * registers to be accessed by indexing vcpu->regs.
 817  */
 818 static void vcpu_load_rsp_rip(struct kvm_vcpu *vcpu)
 819 {
 820         vcpu->regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
 821         vcpu->rip = vmcs_readl(GUEST_RIP);
 822 }
 823
 824 /*
 825  * Syncs rsp and rip back into the vmcs.  Should be called after possible
 826  * modification.
 827  */
 828 static void vcpu_put_rsp_rip(struct kvm_vcpu *vcpu)
 829 {
 830         vmcs_writel(GUEST_RSP, vcpu->regs[VCPU_REGS_RSP]);
 831         vmcs_writel(GUEST_RIP, vcpu->rip);
 832 }
 833
 834 static int set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_debug_guest *dbg)
 835 {
 836         unsigned long dr7 = 0x400;
 837         int old_singlestep;
 838
 839         old_singlestep = vcpu->guest_debug.singlestep;
 840
 841         vcpu->guest_debug.enabled = dbg->enabled;
 842         if (vcpu->guest_debug.enabled) {
 843                 int i;
 844
 845                 dr7 |= 0x200;  /* exact */
 846                 for (i = 0; i < 4; ++i) {
 847                         if (!dbg->breakpoints[i].enabled)
 848                                 continue;
 849                         vcpu->guest_debug.bp[i] = dbg->breakpoints[i].address;
 850                         dr7 |= 2 << (i*2);    /* global enable */
 851                         dr7 |= 0 << (i*4+16); /* execution breakpoint */
 852                 }
 853
 854                 vcpu->guest_debug.singlestep = dbg->singlestep;
 855         } else
 856                 vcpu->guest_debug.singlestep = 0;
 857
 858         if (old_singlestep && !vcpu->guest_debug.singlestep) {
 859                 unsigned long flags;
 860
 861                 flags = vmcs_readl(GUEST_RFLAGS);
 862                 flags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
 863                 vmcs_writel(GUEST_RFLAGS, flags);
 864         }
 865
 866         update_exception_bitmap(vcpu);
 867         vmcs_writel(GUEST_DR7, dr7);
 868
 869         return 0;
 870 }
 871
 872 static int vmx_get_irq(struct kvm_vcpu *vcpu)
 873 {
 874         struct vcpu_vmx *vmx = to_vmx(vcpu);
 875         u32 idtv_info_field;
 876
 877         idtv_info_field = vmx->idt_vectoring_info;
 878         if (idtv_info_field & INTR_INFO_VALID_MASK) {
 879                 if (is_external_interrupt(idtv_info_field))
 880                         return idtv_info_field & VECTORING_INFO_VECTOR_MASK;
 881                 else
 882                         printk(KERN_DEBUG "pending exception: not handled yet\n");
 883         }
 884         return -1;
 885 }
 886
 887 static __init int cpu_has_kvm_support(void)
 888 {
 889         unsigned long ecx = cpuid_ecx(1);
 890         return test_bit(5, &ecx); /* CPUID.1:ECX.VMX[bit 5] -> VT */
 891 }
 892
 893 static __init int vmx_disabled_by_bios(void)
 894 {
 895         u64 msr;
 896
 897         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
 898         return (msr & (MSR_IA32_FEATURE_CONTROL_LOCKED |
 899                        MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED))
 900             == MSR_IA32_FEATURE_CONTROL_LOCKED;
 901         /* locked but not enabled */
 902 }
 903
 904 static void hardware_enable(void *garbage)
 905 {
 906         int cpu = raw_smp_processor_id();
 907         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
 908         u64 old;
 909
 910         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
 911         if ((old & (MSR_IA32_FEATURE_CONTROL_LOCKED |
 912                     MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED))
 913             != (MSR_IA32_FEATURE_CONTROL_LOCKED |
 914                 MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED))
 915                 /* enable and lock */
 916                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old |
 917                        MSR_IA32_FEATURE_CONTROL_LOCKED |
 918                        MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED);
 919         write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
 920         asm volatile (ASM_VMX_VMXON_RAX : : "a"(&phys_addr), "m"(phys_addr)
 921                       : "memory", "cc");
 922 }
 923
 924 static void hardware_disable(void *garbage)
 925 {
 926         asm volatile (ASM_VMX_VMXOFF : : : "cc");
 927 }
 928
 929 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
 930                                       u32 msr, u32 *result)
 931 {
 932         u32 vmx_msr_low, vmx_msr_high;
 933         u32 ctl = ctl_min | ctl_opt;
 934
 935         rdmsr(msr, vmx_msr_low, vmx_msr_high);
 936
 937         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
 938         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
 939
 940         /* Ensure minimum (required) set of control bits are supported. */
 941         if (ctl_min & ~ctl)
 942                 return -EIO;
 943
 944         *result = ctl;
 945         return 0;
 946 }
 947
 948 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
 949 {
 950         u32 vmx_msr_low, vmx_msr_high;
 951         u32 min, opt;
 952         u32 _pin_based_exec_control = 0;
 953         u32 _cpu_based_exec_control = 0;
 954         u32 _cpu_based_2nd_exec_control = 0;
 955         u32 _vmexit_control = 0;
 956         u32 _vmentry_control = 0;
 957
 958         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
 959         opt = 0;
 960         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
 961                                 &_pin_based_exec_control) < 0)
 962                 return -EIO;
 963
 964         min = CPU_BASED_HLT_EXITING |
 965 #ifdef CONFIG_X86_64
 966               CPU_BASED_CR8_LOAD_EXITING |
 967               CPU_BASED_CR8_STORE_EXITING |
 968 #endif
 969               CPU_BASED_USE_IO_BITMAPS |
 970               CPU_BASED_MOV_DR_EXITING |
 971               CPU_BASED_USE_TSC_OFFSETING;
 972         opt = CPU_BASED_TPR_SHADOW |
 973               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
 974         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
 975                                 &_cpu_based_exec_control) < 0)
 976                 return -EIO;
 977 #ifdef CONFIG_X86_64
 978         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
 979                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
 980                                            ~CPU_BASED_CR8_STORE_EXITING;
 981 #endif
 982         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
 983                 min = 0;
 984                 opt = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
 985                         SECONDARY_EXEC_WBINVD_EXITING;
 986                 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS2,
 987                                         &_cpu_based_2nd_exec_control) < 0)
 988                         return -EIO;
 989         }
 990 #ifndef CONFIG_X86_64
 991         if (!(_cpu_based_2nd_exec_control &
 992                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
 993                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
 994 #endif
 995
 996         min = 0;
 997 #ifdef CONFIG_X86_64
 998         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
 999 #endif
1000         opt = 0;
1001         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
1002                                 &_vmexit_control) < 0)
1003                 return -EIO;
1004
1005         min = opt = 0;
1006         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
1007                                 &_vmentry_control) < 0)
1008                 return -EIO;
1009
1010         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1011
1012         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
1013         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
1014                 return -EIO;
1015
1016 #ifdef CONFIG_X86_64
1017         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
1018         if (vmx_msr_high & (1u<<16))
1019                 return -EIO;
1020 #endif
1021
1022         /* Require Write-Back (WB) memory type for VMCS accesses. */
1023         if (((vmx_msr_high >> 18) & 15) != 6)
1024                 return -EIO;
1025
1026         vmcs_conf->size = vmx_msr_high & 0x1fff;
1027         vmcs_conf->order = get_order(vmcs_config.size);
1028         vmcs_conf->revision_id = vmx_msr_low;
1029
1030         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
1031         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
1032         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
1033         vmcs_conf->vmexit_ctrl         = _vmexit_control;
1034         vmcs_conf->vmentry_ctrl        = _vmentry_control;
1035
1036         return 0;
1037 }
1038
1039 static struct vmcs *alloc_vmcs_cpu(int cpu)
1040 {
1041         int node = cpu_to_node(cpu);
1042         struct page *pages;
1043         struct vmcs *vmcs;
1044
1045         pages = alloc_pages_node(node, GFP_KERNEL, vmcs_config.order);
1046         if (!pages)
1047                 return NULL;
1048         vmcs = page_address(pages);
1049         memset(vmcs, 0, vmcs_config.size);
1050         vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
1051         return vmcs;
1052 }
1053
1054 static struct vmcs *alloc_vmcs(void)
1055 {
1056         return alloc_vmcs_cpu(raw_smp_processor_id());
1057 }
1058
1059 static void free_vmcs(struct vmcs *vmcs)
1060 {
1061         free_pages((unsigned long)vmcs, vmcs_config.order);
1062 }
1063
1064 static void free_kvm_area(void)
1065 {
1066         int cpu;
1067
1068         for_each_online_cpu(cpu)
1069                 free_vmcs(per_cpu(vmxarea, cpu));
1070 }
1071
1072 static __init int alloc_kvm_area(void)
1073 {
1074         int cpu;
1075
1076         for_each_online_cpu(cpu) {
1077                 struct vmcs *vmcs;
1078
1079                 vmcs = alloc_vmcs_cpu(cpu);
1080                 if (!vmcs) {
1081                         free_kvm_area();
1082                         return -ENOMEM;
1083                 }
1084
1085                 per_cpu(vmxarea, cpu) = vmcs;
1086         }
1087         return 0;
1088 }
1089
1090 static __init int hardware_setup(void)
1091 {
1092         if (setup_vmcs_config(&vmcs_config) < 0)
1093                 return -EIO;
1094         return alloc_kvm_area();
1095 }
1096
1097 static __exit void hardware_unsetup(void)
1098 {
1099         free_kvm_area();
1100 }
1101
1102 static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
1103 {
1104         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1105
1106         if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
1107                 vmcs_write16(sf->selector, save->selector);
1108                 vmcs_writel(sf->base, save->base);
1109                 vmcs_write32(sf->limit, save->limit);
1110                 vmcs_write32(sf->ar_bytes, save->ar);
1111         } else {
1112                 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
1113                         << AR_DPL_SHIFT;
1114                 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
1115         }
1116 }
1117
1118 static void enter_pmode(struct kvm_vcpu *vcpu)
1119 {
1120         unsigned long flags;
1121
1122         vcpu->rmode.active = 0;
1123
1124         vmcs_writel(GUEST_TR_BASE, vcpu->rmode.tr.base);
1125         vmcs_write32(GUEST_TR_LIMIT, vcpu->rmode.tr.limit);
1126         vmcs_write32(GUEST_TR_AR_BYTES, vcpu->rmode.tr.ar);
1127
1128         flags = vmcs_readl(GUEST_RFLAGS);
1129         flags &= ~(X86_EFLAGS_IOPL | X86_EFLAGS_VM);
1130         flags |= (vcpu->rmode.save_iopl << IOPL_SHIFT);
1131         vmcs_writel(GUEST_RFLAGS, flags);
1132
1133         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
1134                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
1135
1136         update_exception_bitmap(vcpu);
1137
1138         fix_pmode_dataseg(VCPU_SREG_ES, &vcpu->rmode.es);
1139         fix_pmode_dataseg(VCPU_SREG_DS, &vcpu->rmode.ds);
1140         fix_pmode_dataseg(VCPU_SREG_GS, &vcpu->rmode.gs);
1141         fix_pmode_dataseg(VCPU_SREG_FS, &vcpu->rmode.fs);
1142
1143         vmcs_write16(GUEST_SS_SELECTOR, 0);
1144         vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
1145
1146         vmcs_write16(GUEST_CS_SELECTOR,
1147                      vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
1148         vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1149 }
1150
1151 static gva_t rmode_tss_base(struct kvm *kvm)
1152 {
1153         if (!kvm->tss_addr) {
1154                 gfn_t base_gfn = kvm->memslots[0].base_gfn +
1155                                  kvm->memslots[0].npages - 3;
1156                 return base_gfn << PAGE_SHIFT;
1157         }
1158         return kvm->tss_addr;
1159 }
1160
1161 static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
1162 {
1163         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1164
1165         save->selector = vmcs_read16(sf->selector);
1166         save->base = vmcs_readl(sf->base);
1167         save->limit = vmcs_read32(sf->limit);
1168         save->ar = vmcs_read32(sf->ar_bytes);
1169         vmcs_write16(sf->selector, save->base >> 4);
1170         vmcs_write32(sf->base, save->base & 0xfffff);
1171         vmcs_write32(sf->limit, 0xffff);
1172         vmcs_write32(sf->ar_bytes, 0xf3);
1173 }
1174
1175 static void enter_rmode(struct kvm_vcpu *vcpu)
1176 {
1177         unsigned long flags;
1178
1179         vcpu->rmode.active = 1;
1180
1181         vcpu->rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
1182         vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
1183
1184         vcpu->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
1185         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
1186
1187         vcpu->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
1188         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1189
1190         flags = vmcs_readl(GUEST_RFLAGS);
1191         vcpu->rmode.save_iopl = (flags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
1192
1193         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1194
1195         vmcs_writel(GUEST_RFLAGS, flags);
1196         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
1197         update_exception_bitmap(vcpu);
1198
1199         vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
1200         vmcs_write32(GUEST_SS_LIMIT, 0xffff);
1201         vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
1202
1203         vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
1204         vmcs_write32(GUEST_CS_LIMIT, 0xffff);
1205         if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
1206                 vmcs_writel(GUEST_CS_BASE, 0xf0000);
1207         vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
1208
1209         fix_rmode_seg(VCPU_SREG_ES, &vcpu->rmode.es);
1210         fix_rmode_seg(VCPU_SREG_DS, &vcpu->rmode.ds);
1211         fix_rmode_seg(VCPU_SREG_GS, &vcpu->rmode.gs);
1212         fix_rmode_seg(VCPU_SREG_FS, &vcpu->rmode.fs);
1213
1214         kvm_mmu_reset_context(vcpu);
1215         init_rmode_tss(vcpu->kvm);
1216 }
1217
1218 #ifdef CONFIG_X86_64
1219
1220 static void enter_lmode(struct kvm_vcpu *vcpu)
1221 {
1222         u32 guest_tr_ar;
1223
1224         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
1225         if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
1226                 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
1227                        __FUNCTION__);
1228                 vmcs_write32(GUEST_TR_AR_BYTES,
1229                              (guest_tr_ar & ~AR_TYPE_MASK)
1230                              | AR_TYPE_BUSY_64_TSS);
1231         }
1232
1233         vcpu->shadow_efer |= EFER_LMA;
1234
1235         find_msr_entry(to_vmx(vcpu), MSR_EFER)->data |= EFER_LMA | EFER_LME;
1236         vmcs_write32(VM_ENTRY_CONTROLS,
1237                      vmcs_read32(VM_ENTRY_CONTROLS)
1238                      | VM_ENTRY_IA32E_MODE);
1239 }
1240
1241 static void exit_lmode(struct kvm_vcpu *vcpu)
1242 {
1243         vcpu->shadow_efer &= ~EFER_LMA;
1244
1245         vmcs_write32(VM_ENTRY_CONTROLS,
1246                      vmcs_read32(VM_ENTRY_CONTROLS)
1247                      & ~VM_ENTRY_IA32E_MODE);
1248 }
1249
1250 #endif
1251
1252 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1253 {
1254         vcpu->cr4 &= KVM_GUEST_CR4_MASK;
1255         vcpu->cr4 |= vmcs_readl(GUEST_CR4) & ~KVM_GUEST_CR4_MASK;
1256 }
1257
1258 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1259 {
1260         vmx_fpu_deactivate(vcpu);
1261
1262         if (vcpu->rmode.active && (cr0 & X86_CR0_PE))
1263                 enter_pmode(vcpu);
1264
1265         if (!vcpu->rmode.active && !(cr0 & X86_CR0_PE))
1266                 enter_rmode(vcpu);
1267
1268 #ifdef CONFIG_X86_64
1269         if (vcpu->shadow_efer & EFER_LME) {
1270                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
1271                         enter_lmode(vcpu);
1272                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
1273                         exit_lmode(vcpu);
1274         }
1275 #endif
1276
1277         vmcs_writel(CR0_READ_SHADOW, cr0);
1278         vmcs_writel(GUEST_CR0,
1279                     (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON);
1280         vcpu->cr0 = cr0;
1281
1282         if (!(cr0 & X86_CR0_TS) || !(cr0 & X86_CR0_PE))
1283                 vmx_fpu_activate(vcpu);
1284 }
1285
1286 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1287 {
1288         vmcs_writel(GUEST_CR3, cr3);
1289         if (vcpu->cr0 & X86_CR0_PE)
1290                 vmx_fpu_deactivate(vcpu);
1291 }
1292
1293 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1294 {
1295         vmcs_writel(CR4_READ_SHADOW, cr4);
1296         vmcs_writel(GUEST_CR4, cr4 | (vcpu->rmode.active ?
1297                     KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON));
1298         vcpu->cr4 = cr4;
1299 }
1300
1301 #ifdef CONFIG_X86_64
1302
1303 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
1304 {
1305         struct vcpu_vmx *vmx = to_vmx(vcpu);
1306         struct kvm_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
1307
1308         vcpu->shadow_efer = efer;
1309         if (efer & EFER_LMA) {
1310                 vmcs_write32(VM_ENTRY_CONTROLS,
1311                                      vmcs_read32(VM_ENTRY_CONTROLS) |
1312                                      VM_ENTRY_IA32E_MODE);
1313                 msr->data = efer;
1314
1315         } else {
1316                 vmcs_write32(VM_ENTRY_CONTROLS,
1317                                      vmcs_read32(VM_ENTRY_CONTROLS) &
1318                                      ~VM_ENTRY_IA32E_MODE);
1319
1320                 msr->data = efer & ~EFER_LME;
1321         }
1322         setup_msrs(vmx);
1323 }
1324
1325 #endif
1326
1327 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1328 {
1329         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1330
1331         return vmcs_readl(sf->base);
1332 }
1333
1334 static void vmx_get_segment(struct kvm_vcpu *vcpu,
1335                             struct kvm_segment *var, int seg)
1336 {
1337         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1338         u32 ar;
1339
1340         var->base = vmcs_readl(sf->base);
1341         var->limit = vmcs_read32(sf->limit);
1342         var->selector = vmcs_read16(sf->selector);
1343         ar = vmcs_read32(sf->ar_bytes);
1344         if (ar & AR_UNUSABLE_MASK)
1345                 ar = 0;
1346         var->type = ar & 15;
1347         var->s = (ar >> 4) & 1;
1348         var->dpl = (ar >> 5) & 3;
1349         var->present = (ar >> 7) & 1;
1350         var->avl = (ar >> 12) & 1;
1351         var->l = (ar >> 13) & 1;
1352         var->db = (ar >> 14) & 1;
1353         var->g = (ar >> 15) & 1;
1354         var->unusable = (ar >> 16) & 1;
1355 }
1356
1357 static u32 vmx_segment_access_rights(struct kvm_segment *var)
1358 {
1359         u32 ar;
1360
1361         if (var->unusable)
1362                 ar = 1 << 16;
1363         else {
1364                 ar = var->type & 15;
1365                 ar |= (var->s & 1) << 4;
1366                 ar |= (var->dpl & 3) << 5;
1367                 ar |= (var->present & 1) << 7;
1368                 ar |= (var->avl & 1) << 12;
1369                 ar |= (var->l & 1) << 13;
1370                 ar |= (var->db & 1) << 14;
1371                 ar |= (var->g & 1) << 15;
1372         }
1373         if (ar == 0) /* a 0 value means unusable */
1374                 ar = AR_UNUSABLE_MASK;
1375
1376         return ar;
1377 }
1378
1379 static void vmx_set_segment(struct kvm_vcpu *vcpu,
1380                             struct kvm_segment *var, int seg)
1381 {
1382         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1383         u32 ar;
1384
1385         if (vcpu->rmode.active && seg == VCPU_SREG_TR) {
1386                 vcpu->rmode.tr.selector = var->selector;
1387                 vcpu->rmode.tr.base = var->base;
1388                 vcpu->rmode.tr.limit = var->limit;
1389                 vcpu->rmode.tr.ar = vmx_segment_access_rights(var);
1390                 return;
1391         }
1392         vmcs_writel(sf->base, var->base);
1393         vmcs_write32(sf->limit, var->limit);
1394         vmcs_write16(sf->selector, var->selector);
1395         if (vcpu->rmode.active && var->s) {
1396                 /*
1397                  * Hack real-mode segments into vm86 compatibility.
1398                  */
1399                 if (var->base == 0xffff0000 && var->selector == 0xf000)
1400                         vmcs_writel(sf->base, 0xf0000);
1401                 ar = 0xf3;
1402         } else
1403                 ar = vmx_segment_access_rights(var);
1404         vmcs_write32(sf->ar_bytes, ar);
1405 }
1406
1407 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
1408 {
1409         u32 ar = vmcs_read32(GUEST_CS_AR_BYTES);
1410
1411         *db = (ar >> 14) & 1;
1412         *l = (ar >> 13) & 1;
1413 }
1414
1415 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1416 {
1417         dt->limit = vmcs_read32(GUEST_IDTR_LIMIT);
1418         dt->base = vmcs_readl(GUEST_IDTR_BASE);
1419 }
1420
1421 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1422 {
1423         vmcs_write32(GUEST_IDTR_LIMIT, dt->limit);
1424         vmcs_writel(GUEST_IDTR_BASE, dt->base);
1425 }
1426
1427 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1428 {
1429         dt->limit = vmcs_read32(GUEST_GDTR_LIMIT);
1430         dt->base = vmcs_readl(GUEST_GDTR_BASE);
1431 }
1432
1433 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1434 {
1435         vmcs_write32(GUEST_GDTR_LIMIT, dt->limit);
1436         vmcs_writel(GUEST_GDTR_BASE, dt->base);
1437 }
1438
1439 static int init_rmode_tss(struct kvm *kvm)
1440 {
1441         gfn_t fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
1442         u16 data = 0;
1443         int r;
1444
1445         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
1446         if (r < 0)
1447                 return 0;
1448         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
1449         r = kvm_write_guest_page(kvm, fn++, &data, 0x66, sizeof(u16));
1450         if (r < 0)
1451                 return 0;
1452         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
1453         if (r < 0)
1454                 return 0;
1455         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
1456         if (r < 0)
1457                 return 0;
1458         data = ~0;
1459         r = kvm_write_guest_page(kvm, fn, &data, RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
1460                         sizeof(u8));
1461         if (r < 0)
1462                 return 0;
1463         return 1;
1464 }
1465
1466 static void seg_setup(int seg)
1467 {
1468         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1469
1470         vmcs_write16(sf->selector, 0);
1471         vmcs_writel(sf->base, 0);
1472         vmcs_write32(sf->limit, 0xffff);
1473         vmcs_write32(sf->ar_bytes, 0x93);
1474 }
1475
1476 static int alloc_apic_access_page(struct kvm *kvm)
1477 {
1478         struct kvm_userspace_memory_region kvm_userspace_mem;
1479         int r = 0;
1480
1481         mutex_lock(&kvm->lock);
1482         if (kvm->apic_access_page)
1483                 goto out;
1484         kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
1485         kvm_userspace_mem.flags = 0;
1486         kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
1487         kvm_userspace_mem.memory_size = PAGE_SIZE;
1488         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
1489         if (r)
1490                 goto out;
1491         kvm->apic_access_page = gfn_to_page(kvm, 0xfee00);
1492 out:
1493         mutex_unlock(&kvm->lock);
1494         return r;
1495 }
1496
1497 /*
1498  * Sets up the vmcs for emulated real mode.
1499  */
1500 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
1501 {
1502         u32 host_sysenter_cs;
1503         u32 junk;
1504         unsigned long a;
1505         struct descriptor_table dt;
1506         int i;
1507         unsigned long kvm_vmx_return;
1508         u32 exec_control;
1509
1510         /* I/O */
1511         vmcs_write64(IO_BITMAP_A, page_to_phys(vmx_io_bitmap_a));
1512         vmcs_write64(IO_BITMAP_B, page_to_phys(vmx_io_bitmap_b));
1513
1514         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
1515
1516         /* Control */
1517         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
1518                 vmcs_config.pin_based_exec_ctrl);
1519
1520         exec_control = vmcs_config.cpu_based_exec_ctrl;
1521         if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
1522                 exec_control &= ~CPU_BASED_TPR_SHADOW;
1523 #ifdef CONFIG_X86_64
1524                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
1525                                 CPU_BASED_CR8_LOAD_EXITING;
1526 #endif
1527         }
1528         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
1529
1530         if (cpu_has_secondary_exec_ctrls()) {
1531                 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
1532                 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
1533                         exec_control &=
1534                                 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
1535                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
1536         }
1537
1538         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, !!bypass_guest_pf);
1539         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, !!bypass_guest_pf);
1540         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
1541
1542         vmcs_writel(HOST_CR0, read_cr0());  /* 22.2.3 */
1543         vmcs_writel(HOST_CR4, read_cr4());  /* 22.2.3, 22.2.5 */
1544         vmcs_writel(HOST_CR3, read_cr3());  /* 22.2.3  FIXME: shadow tables */
1545
1546         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
1547         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
1548         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
1549         vmcs_write16(HOST_FS_SELECTOR, read_fs());    /* 22.2.4 */
1550         vmcs_write16(HOST_GS_SELECTOR, read_gs());    /* 22.2.4 */
1551         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
1552 #ifdef CONFIG_X86_64
1553         rdmsrl(MSR_FS_BASE, a);
1554         vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
1555         rdmsrl(MSR_GS_BASE, a);
1556         vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
1557 #else
1558         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
1559         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
1560 #endif
1561
1562         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
1563
1564         get_idt(&dt);
1565         vmcs_writel(HOST_IDTR_BASE, dt.base);   /* 22.2.4 */
1566
1567         asm("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return));
1568         vmcs_writel(HOST_RIP, kvm_vmx_return); /* 22.2.5 */
1569         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
1570         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
1571         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
1572
1573         rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk);
1574         vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs);
1575         rdmsrl(MSR_IA32_SYSENTER_ESP, a);
1576         vmcs_writel(HOST_IA32_SYSENTER_ESP, a);   /* 22.2.3 */
1577         rdmsrl(MSR_IA32_SYSENTER_EIP, a);
1578         vmcs_writel(HOST_IA32_SYSENTER_EIP, a);   /* 22.2.3 */
1579
1580         for (i = 0; i < NR_VMX_MSR; ++i) {
1581                 u32 index = vmx_msr_index[i];
1582                 u32 data_low, data_high;
1583                 u64 data;
1584                 int j = vmx->nmsrs;
1585
1586                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
1587                         continue;
1588                 if (wrmsr_safe(index, data_low, data_high) < 0)
1589                         continue;
1590                 data = data_low | ((u64)data_high << 32);
1591                 vmx->host_msrs[j].index = index;
1592                 vmx->host_msrs[j].reserved = 0;
1593                 vmx->host_msrs[j].data = data;
1594                 vmx->guest_msrs[j] = vmx->host_msrs[j];
1595                 ++vmx->nmsrs;
1596         }
1597
1598         vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
1599
1600         /* 22.2.1, 20.8.1 */
1601         vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
1602
1603         vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
1604         vmcs_writel(CR4_GUEST_HOST_MASK, KVM_GUEST_CR4_MASK);
1605
1606         if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
1607                 if (alloc_apic_access_page(vmx->vcpu.kvm) != 0)
1608                         return -ENOMEM;
1609
1610         return 0;
1611 }
1612
1613 static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
1614 {
1615         struct vcpu_vmx *vmx = to_vmx(vcpu);
1616         u64 msr;
1617         int ret;
1618
1619         if (!init_rmode_tss(vmx->vcpu.kvm)) {
1620                 ret = -ENOMEM;
1621                 goto out;
1622         }
1623
1624         vmx->vcpu.rmode.active = 0;
1625
1626         vmx->vcpu.regs[VCPU_REGS_RDX] = get_rdx_init_val();
1627         set_cr8(&vmx->vcpu, 0);
1628         msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
1629         if (vmx->vcpu.vcpu_id == 0)
1630                 msr |= MSR_IA32_APICBASE_BSP;
1631         kvm_set_apic_base(&vmx->vcpu, msr);
1632
1633         fx_init(&vmx->vcpu);
1634
1635         /*
1636          * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
1637          * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4.  Sigh.
1638          */
1639         if (vmx->vcpu.vcpu_id == 0) {
1640                 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
1641                 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
1642         } else {
1643                 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.sipi_vector << 8);
1644                 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.sipi_vector << 12);
1645         }
1646         vmcs_write32(GUEST_CS_LIMIT, 0xffff);
1647         vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1648
1649         seg_setup(VCPU_SREG_DS);
1650         seg_setup(VCPU_SREG_ES);
1651         seg_setup(VCPU_SREG_FS);
1652         seg_setup(VCPU_SREG_GS);
1653         seg_setup(VCPU_SREG_SS);
1654
1655         vmcs_write16(GUEST_TR_SELECTOR, 0);
1656         vmcs_writel(GUEST_TR_BASE, 0);
1657         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
1658         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1659
1660         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
1661         vmcs_writel(GUEST_LDTR_BASE, 0);
1662         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
1663         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
1664
1665         vmcs_write32(GUEST_SYSENTER_CS, 0);
1666         vmcs_writel(GUEST_SYSENTER_ESP, 0);
1667         vmcs_writel(GUEST_SYSENTER_EIP, 0);
1668
1669         vmcs_writel(GUEST_RFLAGS, 0x02);
1670         if (vmx->vcpu.vcpu_id == 0)
1671                 vmcs_writel(GUEST_RIP, 0xfff0);
1672         else
1673                 vmcs_writel(GUEST_RIP, 0);
1674         vmcs_writel(GUEST_RSP, 0);
1675
1676         /* todo: dr0 = dr1 = dr2 = dr3 = 0; dr6 = 0xffff0ff0 */
1677         vmcs_writel(GUEST_DR7, 0x400);
1678
1679         vmcs_writel(GUEST_GDTR_BASE, 0);
1680         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
1681
1682         vmcs_writel(GUEST_IDTR_BASE, 0);
1683         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
1684
1685         vmcs_write32(GUEST_ACTIVITY_STATE, 0);
1686         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
1687         vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
1688
1689         guest_write_tsc(0);
1690
1691         /* Special registers */
1692         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
1693
1694         setup_msrs(vmx);
1695
1696         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
1697
1698         if (cpu_has_vmx_tpr_shadow()) {
1699                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
1700                 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
1701                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
1702                                      page_to_phys(vmx->vcpu.apic->regs_page));
1703                 vmcs_write32(TPR_THRESHOLD, 0);
1704         }
1705
1706         if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
1707                 vmcs_write64(APIC_ACCESS_ADDR,
1708                              page_to_phys(vmx->vcpu.kvm->apic_access_page));
1709
1710         vmx->vcpu.cr0 = 0x60000010;
1711         vmx_set_cr0(&vmx->vcpu, vmx->vcpu.cr0); /* enter rmode */
1712         vmx_set_cr4(&vmx->vcpu, 0);
1713 #ifdef CONFIG_X86_64
1714         vmx_set_efer(&vmx->vcpu, 0);
1715 #endif
1716         vmx_fpu_activate(&vmx->vcpu);
1717         update_exception_bitmap(&vmx->vcpu);
1718
1719         return 0;
1720
1721 out:
1722         return ret;
1723 }
1724
1725 static void vmx_inject_irq(struct kvm_vcpu *vcpu, int irq)
1726 {
1727         struct vcpu_vmx *vmx = to_vmx(vcpu);
1728
1729         if (vcpu->rmode.active) {
1730                 vmx->rmode.irq.pending = true;
1731                 vmx->rmode.irq.vector = irq;
1732                 vmx->rmode.irq.rip = vmcs_readl(GUEST_RIP);
1733                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
1734                              irq | INTR_TYPE_SOFT_INTR | INTR_INFO_VALID_MASK);
1735                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
1736                 vmcs_writel(GUEST_RIP, vmx->rmode.irq.rip - 1);
1737                 return;
1738         }
1739         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
1740                         irq | INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
1741 }
1742
1743 static void kvm_do_inject_irq(struct kvm_vcpu *vcpu)
1744 {
1745         int word_index = __ffs(vcpu->irq_summary);
1746         int bit_index = __ffs(vcpu->irq_pending[word_index]);
1747         int irq = word_index * BITS_PER_LONG + bit_index;
1748
1749         clear_bit(bit_index, &vcpu->irq_pending[word_index]);
1750         if (!vcpu->irq_pending[word_index])
1751                 clear_bit(word_index, &vcpu->irq_summary);
1752         vmx_inject_irq(vcpu, irq);
1753 }
1754
1755
1756 static void do_interrupt_requests(struct kvm_vcpu *vcpu,
1757                                        struct kvm_run *kvm_run)
1758 {
1759         u32 cpu_based_vm_exec_control;
1760
1761         vcpu->interrupt_window_open =
1762                 ((vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
1763                  (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 3) == 0);
1764
1765         if (vcpu->interrupt_window_open &&
1766             vcpu->irq_summary &&
1767             !(vmcs_read32(VM_ENTRY_INTR_INFO_FIELD) & INTR_INFO_VALID_MASK))
1768                 /*
1769                  * If interrupts enabled, and not blocked by sti or mov ss. Good.
1770                  */
1771                 kvm_do_inject_irq(vcpu);
1772
1773         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
1774         if (!vcpu->interrupt_window_open &&
1775             (vcpu->irq_summary || kvm_run->request_interrupt_window))
1776                 /*
1777                  * Interrupts blocked.  Wait for unblock.
1778                  */
1779                 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
1780         else
1781                 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
1782         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
1783 }
1784
1785 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
1786 {
1787         int ret;
1788         struct kvm_userspace_memory_region tss_mem = {
1789                 .slot = 8,
1790                 .guest_phys_addr = addr,
1791                 .memory_size = PAGE_SIZE * 3,
1792                 .flags = 0,
1793         };
1794
1795         ret = kvm_set_memory_region(kvm, &tss_mem, 0);
1796         if (ret)
1797                 return ret;
1798         kvm->tss_addr = addr;
1799         return 0;
1800 }
1801
1802 static void kvm_guest_debug_pre(struct kvm_vcpu *vcpu)
1803 {
1804         struct kvm_guest_debug *dbg = &vcpu->guest_debug;
1805
1806         set_debugreg(dbg->bp[0], 0);
1807         set_debugreg(dbg->bp[1], 1);
1808         set_debugreg(dbg->bp[2], 2);
1809         set_debugreg(dbg->bp[3], 3);
1810
1811         if (dbg->singlestep) {
1812                 unsigned long flags;
1813
1814                 flags = vmcs_readl(GUEST_RFLAGS);
1815                 flags |= X86_EFLAGS_TF | X86_EFLAGS_RF;
1816                 vmcs_writel(GUEST_RFLAGS, flags);
1817         }
1818 }
1819
1820 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
1821                                   int vec, u32 err_code)
1822 {
1823         if (!vcpu->rmode.active)
1824                 return 0;
1825
1826         /*
1827          * Instruction with address size override prefix opcode 0x67
1828          * Cause the #SS fault with 0 error code in VM86 mode.
1829          */
1830         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
1831                 if (emulate_instruction(vcpu, NULL, 0, 0, 0) == EMULATE_DONE)
1832                         return 1;
1833         return 0;
1834 }
1835
1836 static int handle_exception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1837 {
1838         struct vcpu_vmx *vmx = to_vmx(vcpu);
1839         u32 intr_info, error_code;
1840         unsigned long cr2, rip;
1841         u32 vect_info;
1842         enum emulation_result er;
1843
1844         vect_info = vmx->idt_vectoring_info;
1845         intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
1846
1847         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
1848                                                 !is_page_fault(intr_info))
1849                 printk(KERN_ERR "%s: unexpected, vectoring info 0x%x "
1850                        "intr info 0x%x\n", __FUNCTION__, vect_info, intr_info);
1851
1852         if (!irqchip_in_kernel(vcpu->kvm) && is_external_interrupt(vect_info)) {
1853                 int irq = vect_info & VECTORING_INFO_VECTOR_MASK;
1854                 set_bit(irq, vcpu->irq_pending);
1855                 set_bit(irq / BITS_PER_LONG, &vcpu->irq_summary);
1856         }
1857
1858         if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == 0x200) /* nmi */
1859                 return 1;  /* already handled by vmx_vcpu_run() */
1860
1861         if (is_no_device(intr_info)) {
1862                 vmx_fpu_activate(vcpu);
1863                 return 1;
1864         }
1865
1866         if (is_invalid_opcode(intr_info)) {
1867                 er = emulate_instruction(vcpu, kvm_run, 0, 0, 0);
1868                 if (er != EMULATE_DONE)
1869                         vmx_inject_ud(vcpu);
1870
1871                 return 1;
1872         }
1873
1874         error_code = 0;
1875         rip = vmcs_readl(GUEST_RIP);
1876         if (intr_info & INTR_INFO_DELIEVER_CODE_MASK)
1877                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
1878         if (is_page_fault(intr_info)) {
1879                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
1880                 return kvm_mmu_page_fault(vcpu, cr2, error_code);
1881         }
1882
1883         if (vcpu->rmode.active &&
1884             handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
1885                                                                 error_code)) {
1886                 if (vcpu->halt_request) {
1887                         vcpu->halt_request = 0;
1888                         return kvm_emulate_halt(vcpu);
1889                 }
1890                 return 1;
1891         }
1892
1893         if ((intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK)) ==
1894             (INTR_TYPE_EXCEPTION | 1)) {
1895                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1896                 return 0;
1897         }
1898         kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
1899         kvm_run->ex.exception = intr_info & INTR_INFO_VECTOR_MASK;
1900         kvm_run->ex.error_code = error_code;
1901         return 0;
1902 }
1903
1904 static int handle_external_interrupt(struct kvm_vcpu *vcpu,
1905                                      struct kvm_run *kvm_run)
1906 {
1907         ++vcpu->stat.irq_exits;
1908         return 1;
1909 }
1910
1911 static int handle_triple_fault(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1912 {
1913         kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1914         return 0;
1915 }
1916
1917 static int handle_io(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1918 {
1919         unsigned long exit_qualification;
1920         int size, down, in, string, rep;
1921         unsigned port;
1922
1923         ++vcpu->stat.io_exits;
1924         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
1925         string = (exit_qualification & 16) != 0;
1926
1927         if (string) {
1928                 if (emulate_instruction(vcpu,
1929                                         kvm_run, 0, 0, 0) == EMULATE_DO_MMIO)
1930                         return 0;
1931                 return 1;
1932         }
1933
1934         size = (exit_qualification & 7) + 1;
1935         in = (exit_qualification & 8) != 0;
1936         down = (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_DF) != 0;
1937         rep = (exit_qualification & 32) != 0;
1938         port = exit_qualification >> 16;
1939
1940         return kvm_emulate_pio(vcpu, kvm_run, in, size, port);
1941 }
1942
1943 static void
1944 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
1945 {
1946         /*
1947          * Patch in the VMCALL instruction:
1948          */
1949         hypercall[0] = 0x0f;
1950         hypercall[1] = 0x01;
1951         hypercall[2] = 0xc1;
1952 }
1953
1954 static int handle_cr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1955 {
1956         unsigned long exit_qualification;
1957         int cr;
1958         int reg;
1959
1960         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
1961         cr = exit_qualification & 15;
1962         reg = (exit_qualification >> 8) & 15;
1963         switch ((exit_qualification >> 4) & 3) {
1964         case 0: /* mov to cr */
1965                 switch (cr) {
1966                 case 0:
1967                         vcpu_load_rsp_rip(vcpu);
1968                         set_cr0(vcpu, vcpu->regs[reg]);
1969                         skip_emulated_instruction(vcpu);
1970                         return 1;
1971                 case 3:
1972                         vcpu_load_rsp_rip(vcpu);
1973                         set_cr3(vcpu, vcpu->regs[reg]);
1974                         skip_emulated_instruction(vcpu);
1975                         return 1;
1976                 case 4:
1977                         vcpu_load_rsp_rip(vcpu);
1978                         set_cr4(vcpu, vcpu->regs[reg]);
1979                         skip_emulated_instruction(vcpu);
1980                         return 1;
1981                 case 8:
1982                         vcpu_load_rsp_rip(vcpu);
1983                         set_cr8(vcpu, vcpu->regs[reg]);
1984                         skip_emulated_instruction(vcpu);
1985                         kvm_run->exit_reason = KVM_EXIT_SET_TPR;
1986                         return 0;
1987                 };
1988                 break;
1989         case 2: /* clts */
1990                 vcpu_load_rsp_rip(vcpu);
1991                 vmx_fpu_deactivate(vcpu);
1992                 vcpu->cr0 &= ~X86_CR0_TS;
1993                 vmcs_writel(CR0_READ_SHADOW, vcpu->cr0);
1994                 vmx_fpu_activate(vcpu);
1995                 skip_emulated_instruction(vcpu);
1996                 return 1;
1997         case 1: /*mov from cr*/
1998                 switch (cr) {
1999                 case 3:
2000                         vcpu_load_rsp_rip(vcpu);
2001                         vcpu->regs[reg] = vcpu->cr3;
2002                         vcpu_put_rsp_rip(vcpu);
2003                         skip_emulated_instruction(vcpu);
2004                         return 1;
2005                 case 8:
2006                         vcpu_load_rsp_rip(vcpu);
2007                         vcpu->regs[reg] = get_cr8(vcpu);
2008                         vcpu_put_rsp_rip(vcpu);
2009                         skip_emulated_instruction(vcpu);
2010                         return 1;
2011                 }
2012                 break;
2013         case 3: /* lmsw */
2014                 lmsw(vcpu, (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f);
2015
2016                 skip_emulated_instruction(vcpu);
2017                 return 1;
2018         default:
2019                 break;
2020         }
2021         kvm_run->exit_reason = 0;
2022         pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
2023                (int)(exit_qualification >> 4) & 3, cr);
2024         return 0;
2025 }
2026
2027 static int handle_dr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2028 {
2029         unsigned long exit_qualification;
2030         unsigned long val;
2031         int dr, reg;
2032
2033         /*
2034          * FIXME: this code assumes the host is debugging the guest.
2035          *        need to deal with guest debugging itself too.
2036          */
2037         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2038         dr = exit_qualification & 7;
2039         reg = (exit_qualification >> 8) & 15;
2040         vcpu_load_rsp_rip(vcpu);
2041         if (exit_qualification & 16) {
2042                 /* mov from dr */
2043                 switch (dr) {
2044                 case 6:
2045                         val = 0xffff0ff0;
2046                         break;
2047                 case 7:
2048                         val = 0x400;
2049                         break;
2050                 default:
2051                         val = 0;
2052                 }
2053                 vcpu->regs[reg] = val;
2054         } else {
2055                 /* mov to dr */
2056         }
2057         vcpu_put_rsp_rip(vcpu);
2058         skip_emulated_instruction(vcpu);
2059         return 1;
2060 }
2061
2062 static int handle_cpuid(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2063 {
2064         kvm_emulate_cpuid(vcpu);
2065         return 1;
2066 }
2067
2068 static int handle_rdmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2069 {
2070         u32 ecx = vcpu->regs[VCPU_REGS_RCX];
2071         u64 data;
2072
2073         if (vmx_get_msr(vcpu, ecx, &data)) {
2074                 kvm_inject_gp(vcpu, 0);
2075                 return 1;
2076         }
2077
2078         /* FIXME: handling of bits 32:63 of rax, rdx */
2079         vcpu->regs[VCPU_REGS_RAX] = data & -1u;
2080         vcpu->regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
2081         skip_emulated_instruction(vcpu);
2082         return 1;
2083 }
2084
2085 static int handle_wrmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2086 {
2087         u32 ecx = vcpu->regs[VCPU_REGS_RCX];
2088         u64 data = (vcpu->regs[VCPU_REGS_RAX] & -1u)
2089                 | ((u64)(vcpu->regs[VCPU_REGS_RDX] & -1u) << 32);
2090
2091         if (vmx_set_msr(vcpu, ecx, data) != 0) {
2092                 kvm_inject_gp(vcpu, 0);
2093                 return 1;
2094         }
2095
2096         skip_emulated_instruction(vcpu);
2097         return 1;
2098 }
2099
2100 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu,
2101                                       struct kvm_run *kvm_run)
2102 {
2103         return 1;
2104 }
2105
2106 static int handle_interrupt_window(struct kvm_vcpu *vcpu,
2107                                    struct kvm_run *kvm_run)
2108 {
2109         u32 cpu_based_vm_exec_control;
2110
2111         /* clear pending irq */
2112         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2113         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
2114         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2115         /*
2116          * If the user space waits to inject interrupts, exit as soon as
2117          * possible
2118          */
2119         if (kvm_run->request_interrupt_window &&
2120             !vcpu->irq_summary) {
2121                 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
2122                 ++vcpu->stat.irq_window_exits;
2123                 return 0;
2124         }
2125         return 1;
2126 }
2127
2128 static int handle_halt(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2129 {
2130         skip_emulated_instruction(vcpu);
2131         return kvm_emulate_halt(vcpu);
2132 }
2133
2134 static int handle_vmcall(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2135 {
2136         skip_emulated_instruction(vcpu);
2137         kvm_emulate_hypercall(vcpu);
2138         return 1;
2139 }
2140
2141 static int handle_wbinvd(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2142 {
2143         skip_emulated_instruction(vcpu);
2144         /* TODO: Add support for VT-d/pass-through device */
2145         return 1;
2146 }
2147
2148 static int handle_apic_access(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2149 {
2150         u64 exit_qualification;
2151         enum emulation_result er;
2152         unsigned long offset;
2153
2154         exit_qualification = vmcs_read64(EXIT_QUALIFICATION);
2155         offset = exit_qualification & 0xffful;
2156
2157         er = emulate_instruction(vcpu, kvm_run, 0, 0, 0);
2158
2159         if (er !=  EMULATE_DONE) {
2160                 printk(KERN_ERR
2161                        "Fail to handle apic access vmexit! Offset is 0x%lx\n",
2162                        offset);
2163                 return -ENOTSUPP;
2164         }
2165         return 1;
2166 }
2167
2168 /*
2169  * The exit handlers return 1 if the exit was handled fully and guest execution
2170  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
2171  * to be done to userspace and return 0.
2172  */
2173 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu,
2174                                       struct kvm_run *kvm_run) = {
2175         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception,
2176         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
2177         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
2178         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
2179         [EXIT_REASON_CR_ACCESS]               = handle_cr,
2180         [EXIT_REASON_DR_ACCESS]               = handle_dr,
2181         [EXIT_REASON_CPUID]                   = handle_cpuid,
2182         [EXIT_REASON_MSR_READ]                = handle_rdmsr,
2183         [EXIT_REASON_MSR_WRITE]               = handle_wrmsr,
2184         [EXIT_REASON_PENDING_INTERRUPT]       = handle_interrupt_window,
2185         [EXIT_REASON_HLT]                     = handle_halt,
2186         [EXIT_REASON_VMCALL]                  = handle_vmcall,
2187         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
2188         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
2189         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
2190 };
2191
2192 static const int kvm_vmx_max_exit_handlers =
2193         ARRAY_SIZE(kvm_vmx_exit_handlers);
2194
2195 /*
2196  * The guest has exited.  See if we can fix it or if we need userspace
2197  * assistance.
2198  */
2199 static int kvm_handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
2200 {
2201         u32 exit_reason = vmcs_read32(VM_EXIT_REASON);
2202         struct vcpu_vmx *vmx = to_vmx(vcpu);
2203         u32 vectoring_info = vmx->idt_vectoring_info;
2204
2205         if (unlikely(vmx->fail)) {
2206                 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
2207                 kvm_run->fail_entry.hardware_entry_failure_reason
2208                         = vmcs_read32(VM_INSTRUCTION_ERROR);
2209                 return 0;
2210         }
2211
2212         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
2213                                 exit_reason != EXIT_REASON_EXCEPTION_NMI)
2214                 printk(KERN_WARNING "%s: unexpected, valid vectoring info and "
2215                        "exit reason is 0x%x\n", __FUNCTION__, exit_reason);
2216         if (exit_reason < kvm_vmx_max_exit_handlers
2217             && kvm_vmx_exit_handlers[exit_reason])
2218                 return kvm_vmx_exit_handlers[exit_reason](vcpu, kvm_run);
2219         else {
2220                 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
2221                 kvm_run->hw.hardware_exit_reason = exit_reason;
2222         }
2223         return 0;
2224 }
2225
2226 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
2227 {
2228 }
2229
2230 static void update_tpr_threshold(struct kvm_vcpu *vcpu)
2231 {
2232         int max_irr, tpr;
2233
2234         if (!vm_need_tpr_shadow(vcpu->kvm))
2235                 return;
2236
2237         if (!kvm_lapic_enabled(vcpu) ||
2238             ((max_irr = kvm_lapic_find_highest_irr(vcpu)) == -1)) {
2239                 vmcs_write32(TPR_THRESHOLD, 0);
2240                 return;
2241         }
2242
2243         tpr = (kvm_lapic_get_cr8(vcpu) & 0x0f) << 4;
2244         vmcs_write32(TPR_THRESHOLD, (max_irr > tpr) ? tpr >> 4 : max_irr >> 4);
2245 }
2246
2247 static void enable_irq_window(struct kvm_vcpu *vcpu)
2248 {
2249         u32 cpu_based_vm_exec_control;
2250
2251         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2252         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
2253         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2254 }
2255
2256 static void vmx_intr_assist(struct kvm_vcpu *vcpu)
2257 {
2258         struct vcpu_vmx *vmx = to_vmx(vcpu);
2259         u32 idtv_info_field, intr_info_field;
2260         int has_ext_irq, interrupt_window_open;
2261         int vector;
2262
2263         update_tpr_threshold(vcpu);
2264
2265         has_ext_irq = kvm_cpu_has_interrupt(vcpu);
2266         intr_info_field = vmcs_read32(VM_ENTRY_INTR_INFO_FIELD);
2267         idtv_info_field = vmx->idt_vectoring_info;
2268         if (intr_info_field & INTR_INFO_VALID_MASK) {
2269                 if (idtv_info_field & INTR_INFO_VALID_MASK) {
2270                         /* TODO: fault when IDT_Vectoring */
2271                         printk(KERN_ERR "Fault when IDT_Vectoring\n");
2272                 }
2273                 if (has_ext_irq)
2274                         enable_irq_window(vcpu);
2275                 return;
2276         }
2277         if (unlikely(idtv_info_field & INTR_INFO_VALID_MASK)) {
2278                 if ((idtv_info_field & VECTORING_INFO_TYPE_MASK)
2279                     == INTR_TYPE_EXT_INTR
2280                     && vcpu->rmode.active) {
2281                         u8 vect = idtv_info_field & VECTORING_INFO_VECTOR_MASK;
2282
2283                         vmx_inject_irq(vcpu, vect);
2284                         if (unlikely(has_ext_irq))
2285                                 enable_irq_window(vcpu);
2286                         return;
2287                 }
2288
2289                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, idtv_info_field);
2290                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2291                                 vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
2292
2293                 if (unlikely(idtv_info_field & INTR_INFO_DELIEVER_CODE_MASK))
2294                         vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
2295                                 vmcs_read32(IDT_VECTORING_ERROR_CODE));
2296                 if (unlikely(has_ext_irq))
2297                         enable_irq_window(vcpu);
2298                 return;
2299         }
2300         if (!has_ext_irq)
2301                 return;
2302         interrupt_window_open =
2303                 ((vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
2304                  (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 3) == 0);
2305         if (interrupt_window_open) {
2306                 vector = kvm_cpu_get_interrupt(vcpu);
2307                 vmx_inject_irq(vcpu, vector);
2308                 kvm_timer_intr_post(vcpu, vector);
2309         } else
2310                 enable_irq_window(vcpu);
2311 }
2312
2313 /*
2314  * Failure to inject an interrupt should give us the information
2315  * in IDT_VECTORING_INFO_FIELD.  However, if the failure occurs
2316  * when fetching the interrupt redirection bitmap in the real-mode
2317  * tss, this doesn't happen.  So we do it ourselves.
2318  */
2319 static void fixup_rmode_irq(struct vcpu_vmx *vmx)
2320 {
2321         vmx->rmode.irq.pending = 0;
2322         if (vmcs_readl(GUEST_RIP) + 1 != vmx->rmode.irq.rip)
2323                 return;
2324         vmcs_writel(GUEST_RIP, vmx->rmode.irq.rip);
2325         if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) {
2326                 vmx->idt_vectoring_info &= ~VECTORING_INFO_TYPE_MASK;
2327                 vmx->idt_vectoring_info |= INTR_TYPE_EXT_INTR;
2328                 return;
2329         }
2330         vmx->idt_vectoring_info =
2331                 VECTORING_INFO_VALID_MASK
2332                 | INTR_TYPE_EXT_INTR
2333                 | vmx->rmode.irq.vector;
2334 }
2335
2336 static void vmx_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2337 {
2338         struct vcpu_vmx *vmx = to_vmx(vcpu);
2339         u32 intr_info;
2340
2341         /*
2342          * Loading guest fpu may have cleared host cr0.ts
2343          */
2344         vmcs_writel(HOST_CR0, read_cr0());
2345
2346         asm(
2347                 /* Store host registers */
2348 #ifdef CONFIG_X86_64
2349                 "push %%rdx; push %%rbp;"
2350                 "push %%rcx \n\t"
2351 #else
2352                 "push %%edx; push %%ebp;"
2353                 "push %%ecx \n\t"
2354 #endif
2355                 ASM_VMX_VMWRITE_RSP_RDX "\n\t"
2356                 /* Check if vmlaunch of vmresume is needed */
2357                 "cmpl $0, %c[launched](%0) \n\t"
2358                 /* Load guest registers.  Don't clobber flags. */
2359 #ifdef CONFIG_X86_64
2360                 "mov %c[cr2](%0), %%rax \n\t"
2361                 "mov %%rax, %%cr2 \n\t"
2362                 "mov %c[rax](%0), %%rax \n\t"
2363                 "mov %c[rbx](%0), %%rbx \n\t"
2364                 "mov %c[rdx](%0), %%rdx \n\t"
2365                 "mov %c[rsi](%0), %%rsi \n\t"
2366                 "mov %c[rdi](%0), %%rdi \n\t"
2367                 "mov %c[rbp](%0), %%rbp \n\t"
2368                 "mov %c[r8](%0),  %%r8  \n\t"
2369                 "mov %c[r9](%0),  %%r9  \n\t"
2370                 "mov %c[r10](%0), %%r10 \n\t"
2371                 "mov %c[r11](%0), %%r11 \n\t"
2372                 "mov %c[r12](%0), %%r12 \n\t"
2373                 "mov %c[r13](%0), %%r13 \n\t"
2374                 "mov %c[r14](%0), %%r14 \n\t"
2375                 "mov %c[r15](%0), %%r15 \n\t"
2376                 "mov %c[rcx](%0), %%rcx \n\t" /* kills %0 (rcx) */
2377 #else
2378                 "mov %c[cr2](%0), %%eax \n\t"
2379                 "mov %%eax,   %%cr2 \n\t"
2380                 "mov %c[rax](%0), %%eax \n\t"
2381                 "mov %c[rbx](%0), %%ebx \n\t"
2382                 "mov %c[rdx](%0), %%edx \n\t"
2383                 "mov %c[rsi](%0), %%esi \n\t"
2384                 "mov %c[rdi](%0), %%edi \n\t"
2385                 "mov %c[rbp](%0), %%ebp \n\t"
2386                 "mov %c[rcx](%0), %%ecx \n\t" /* kills %0 (ecx) */
2387 #endif
2388                 /* Enter guest mode */
2389                 "jne .Llaunched \n\t"
2390                 ASM_VMX_VMLAUNCH "\n\t"
2391                 "jmp .Lkvm_vmx_return \n\t"
2392                 ".Llaunched: " ASM_VMX_VMRESUME "\n\t"
2393                 ".Lkvm_vmx_return: "
2394                 /* Save guest registers, load host registers, keep flags */
2395 #ifdef CONFIG_X86_64
2396                 "xchg %0,     (%%rsp) \n\t"
2397                 "mov %%rax, %c[rax](%0) \n\t"
2398                 "mov %%rbx, %c[rbx](%0) \n\t"
2399                 "pushq (%%rsp); popq %c[rcx](%0) \n\t"
2400                 "mov %%rdx, %c[rdx](%0) \n\t"
2401                 "mov %%rsi, %c[rsi](%0) \n\t"
2402                 "mov %%rdi, %c[rdi](%0) \n\t"
2403                 "mov %%rbp, %c[rbp](%0) \n\t"
2404                 "mov %%r8,  %c[r8](%0) \n\t"
2405                 "mov %%r9,  %c[r9](%0) \n\t"
2406                 "mov %%r10, %c[r10](%0) \n\t"
2407                 "mov %%r11, %c[r11](%0) \n\t"
2408                 "mov %%r12, %c[r12](%0) \n\t"
2409                 "mov %%r13, %c[r13](%0) \n\t"
2410                 "mov %%r14, %c[r14](%0) \n\t"
2411                 "mov %%r15, %c[r15](%0) \n\t"
2412                 "mov %%cr2, %%rax   \n\t"
2413                 "mov %%rax, %c[cr2](%0) \n\t"
2414
2415                 "pop  %%rbp; pop  %%rbp; pop  %%rdx \n\t"
2416 #else
2417                 "xchg %0, (%%esp) \n\t"
2418                 "mov %%eax, %c[rax](%0) \n\t"
2419                 "mov %%ebx, %c[rbx](%0) \n\t"
2420                 "pushl (%%esp); popl %c[rcx](%0) \n\t"
2421                 "mov %%edx, %c[rdx](%0) \n\t"
2422                 "mov %%esi, %c[rsi](%0) \n\t"
2423                 "mov %%edi, %c[rdi](%0) \n\t"
2424                 "mov %%ebp, %c[rbp](%0) \n\t"
2425                 "mov %%cr2, %%eax  \n\t"
2426                 "mov %%eax, %c[cr2](%0) \n\t"
2427
2428                 "pop %%ebp; pop %%ebp; pop %%edx \n\t"
2429 #endif
2430                 "setbe %c[fail](%0) \n\t"
2431               : : "c"(vmx), "d"((unsigned long)HOST_RSP),
2432                 [launched]"i"(offsetof(struct vcpu_vmx, launched)),
2433                 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
2434                 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.regs[VCPU_REGS_RAX])),
2435                 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.regs[VCPU_REGS_RBX])),
2436                 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.regs[VCPU_REGS_RCX])),
2437                 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.regs[VCPU_REGS_RDX])),
2438                 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.regs[VCPU_REGS_RSI])),
2439                 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.regs[VCPU_REGS_RDI])),
2440                 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.regs[VCPU_REGS_RBP])),
2441 #ifdef CONFIG_X86_64
2442                 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.regs[VCPU_REGS_R8])),
2443                 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.regs[VCPU_REGS_R9])),
2444                 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.regs[VCPU_REGS_R10])),
2445                 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.regs[VCPU_REGS_R11])),
2446                 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.regs[VCPU_REGS_R12])),
2447                 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.regs[VCPU_REGS_R13])),
2448                 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.regs[VCPU_REGS_R14])),
2449                 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.regs[VCPU_REGS_R15])),
2450 #endif
2451                 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.cr2))
2452               : "cc", "memory"
2453 #ifdef CONFIG_X86_64
2454                 , "rbx", "rdi", "rsi"
2455                 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
2456 #else
2457                 , "ebx", "edi", "rsi"
2458 #endif
2459               );
2460
2461         vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
2462         if (vmx->rmode.irq.pending)
2463                 fixup_rmode_irq(vmx);
2464
2465         vcpu->interrupt_window_open =
2466                 (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 3) == 0;
2467
2468         asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
2469         vmx->launched = 1;
2470
2471         intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
2472
2473         /* We need to handle NMIs before interrupts are enabled */
2474         if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == 0x200) /* nmi */
2475                 asm("int $2");
2476 }
2477
2478 static void vmx_free_vmcs(struct kvm_vcpu *vcpu)
2479 {
2480         struct vcpu_vmx *vmx = to_vmx(vcpu);
2481
2482         if (vmx->vmcs) {
2483                 on_each_cpu(__vcpu_clear, vmx, 0, 1);
2484                 free_vmcs(vmx->vmcs);
2485                 vmx->vmcs = NULL;
2486         }
2487 }
2488
2489 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
2490 {
2491         struct vcpu_vmx *vmx = to_vmx(vcpu);
2492
2493         vmx_free_vmcs(vcpu);
2494         kfree(vmx->host_msrs);
2495         kfree(vmx->guest_msrs);
2496         kvm_vcpu_uninit(vcpu);
2497         kmem_cache_free(kvm_vcpu_cache, vmx);
2498 }
2499
2500 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
2501 {
2502         int err;
2503         struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
2504         int cpu;
2505
2506         if (!vmx)
2507                 return ERR_PTR(-ENOMEM);
2508
2509         err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
2510         if (err)
2511                 goto free_vcpu;
2512
2513         vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
2514         if (!vmx->guest_msrs) {
2515                 err = -ENOMEM;
2516                 goto uninit_vcpu;
2517         }
2518
2519         vmx->host_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
2520         if (!vmx->host_msrs)
2521                 goto free_guest_msrs;
2522
2523         vmx->vmcs = alloc_vmcs();
2524         if (!vmx->vmcs)
2525                 goto free_msrs;
2526
2527         vmcs_clear(vmx->vmcs);
2528
2529         cpu = get_cpu();
2530         vmx_vcpu_load(&vmx->vcpu, cpu);
2531         err = vmx_vcpu_setup(vmx);
2532         vmx_vcpu_put(&vmx->vcpu);
2533         put_cpu();
2534         if (err)
2535                 goto free_vmcs;
2536
2537         return &vmx->vcpu;
2538
2539 free_vmcs:
2540         free_vmcs(vmx->vmcs);
2541 free_msrs:
2542         kfree(vmx->host_msrs);
2543 free_guest_msrs:
2544         kfree(vmx->guest_msrs);
2545 uninit_vcpu:
2546         kvm_vcpu_uninit(&vmx->vcpu);
2547 free_vcpu:
2548         kmem_cache_free(kvm_vcpu_cache, vmx);
2549         return ERR_PTR(err);
2550 }
2551
2552 static void __init vmx_check_processor_compat(void *rtn)
2553 {
2554         struct vmcs_config vmcs_conf;
2555
2556         *(int *)rtn = 0;
2557         if (setup_vmcs_config(&vmcs_conf) < 0)
2558                 *(int *)rtn = -EIO;
2559         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
2560                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
2561                                 smp_processor_id());
2562                 *(int *)rtn = -EIO;
2563         }
2564 }
2565
2566 static struct kvm_x86_ops vmx_x86_ops = {
2567         .cpu_has_kvm_support = cpu_has_kvm_support,
2568         .disabled_by_bios = vmx_disabled_by_bios,
2569         .hardware_setup = hardware_setup,
2570         .hardware_unsetup = hardware_unsetup,
2571         .check_processor_compatibility = vmx_check_processor_compat,
2572         .hardware_enable = hardware_enable,
2573         .hardware_disable = hardware_disable,
2574
2575         .vcpu_create = vmx_create_vcpu,
2576         .vcpu_free = vmx_free_vcpu,
2577         .vcpu_reset = vmx_vcpu_reset,
2578
2579         .prepare_guest_switch = vmx_save_host_state,
2580         .vcpu_load = vmx_vcpu_load,
2581         .vcpu_put = vmx_vcpu_put,
2582         .vcpu_decache = vmx_vcpu_decache,
2583
2584         .set_guest_debug = set_guest_debug,
2585         .guest_debug_pre = kvm_guest_debug_pre,
2586         .get_msr = vmx_get_msr,
2587         .set_msr = vmx_set_msr,
2588         .get_segment_base = vmx_get_segment_base,
2589         .get_segment = vmx_get_segment,
2590         .set_segment = vmx_set_segment,
2591         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
2592         .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
2593         .set_cr0 = vmx_set_cr0,
2594         .set_cr3 = vmx_set_cr3,
2595         .set_cr4 = vmx_set_cr4,
2596 #ifdef CONFIG_X86_64
2597         .set_efer = vmx_set_efer,
2598 #endif
2599         .get_idt = vmx_get_idt,
2600         .set_idt = vmx_set_idt,
2601         .get_gdt = vmx_get_gdt,
2602         .set_gdt = vmx_set_gdt,
2603         .cache_regs = vcpu_load_rsp_rip,
2604         .decache_regs = vcpu_put_rsp_rip,
2605         .get_rflags = vmx_get_rflags,
2606         .set_rflags = vmx_set_rflags,
2607
2608         .tlb_flush = vmx_flush_tlb,
2609
2610         .run = vmx_vcpu_run,
2611         .handle_exit = kvm_handle_exit,
2612         .skip_emulated_instruction = skip_emulated_instruction,
2613         .patch_hypercall = vmx_patch_hypercall,
2614         .get_irq = vmx_get_irq,
2615         .set_irq = vmx_inject_irq,
2616         .queue_exception = vmx_queue_exception,
2617         .exception_injected = vmx_exception_injected,
2618         .inject_pending_irq = vmx_intr_assist,
2619         .inject_pending_vectors = do_interrupt_requests,
2620
2621         .set_tss_addr = vmx_set_tss_addr,
2622 };
2623
2624 static int __init vmx_init(void)
2625 {
2626         void *iova;
2627         int r;
2628
2629         vmx_io_bitmap_a = alloc_page(GFP_KERNEL | __GFP_HIGHMEM);
2630         if (!vmx_io_bitmap_a)
2631                 return -ENOMEM;
2632
2633         vmx_io_bitmap_b = alloc_page(GFP_KERNEL | __GFP_HIGHMEM);
2634         if (!vmx_io_bitmap_b) {
2635                 r = -ENOMEM;
2636                 goto out;
2637         }
2638
2639         /*
2640          * Allow direct access to the PC debug port (it is often used for I/O
2641          * delays, but the vmexits simply slow things down).
2642          */
2643         iova = kmap(vmx_io_bitmap_a);
2644         memset(iova, 0xff, PAGE_SIZE);
2645         clear_bit(0x80, iova);
2646         kunmap(vmx_io_bitmap_a);
2647
2648         iova = kmap(vmx_io_bitmap_b);
2649         memset(iova, 0xff, PAGE_SIZE);
2650         kunmap(vmx_io_bitmap_b);
2651
2652         r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx), THIS_MODULE);
2653         if (r)
2654                 goto out1;
2655
2656         if (bypass_guest_pf)
2657                 kvm_mmu_set_nonpresent_ptes(~0xffeull, 0ull);
2658
2659         return 0;
2660
2661 out1:
2662         __free_page(vmx_io_bitmap_b);
2663 out:
2664         __free_page(vmx_io_bitmap_a);
2665         return r;
2666 }
2667
2668 static void __exit vmx_exit(void)
2669 {
2670         __free_page(vmx_io_bitmap_b);
2671         __free_page(vmx_io_bitmap_a);
2672
2673         kvm_exit();
2674 }
2675
2676 module_init(vmx_init)
2677 module_exit(vmx_exit)