2 Conexant cx24123/cx24109 - DVB QPSK Satellite demod/tuner driver
4 Copyright (C) 2005 Steven Toth <stoth@hauppauge.com>
6 Support for KWorld DVB-S 100 by Vadim Catana <skystar@moldova.cc>
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 #include <linux/slab.h>
24 #include <linux/kernel.h>
25 #include <linux/module.h>
26 #include <linux/moduleparam.h>
27 #include <linux/init.h>
29 #include "dvb_frontend.h"
35 #define dprintk(args...) \
37 if (debug) printk (KERN_DEBUG "cx24123: " args); \
42 struct i2c_adapter* i2c;
43 struct dvb_frontend_ops ops;
44 const struct cx24123_config* config;
46 struct dvb_frontend frontend;
52 /* Some PLL specifics for tuning */
59 /* The Demod/Tuner can't easily provide these, we cache them */
61 u32 currentsymbolrate;
64 /* Various tuner defaults need to be established for a given symbol rate Sps */
72 } cx24123_AGC_vals[] =
75 .symbolrate_low = 1000000,
76 .symbolrate_high = 4999999,
77 /* the specs recommend other values for VGA offsets,
78 but tests show they are wrong */
79 .VGAprogdata = (1 << 19) | (0x180 << 9) | 0x1e0,
80 .VCAprogdata = (2 << 19) | (0x07 << 9) | 0x07,
81 .FILTune = 0x27f /* 0.41 V */
84 .symbolrate_low = 5000000,
85 .symbolrate_high = 14999999,
86 .VGAprogdata = (1 << 19) | (0x180 << 9) | 0x1e0,
87 .VCAprogdata = (2 << 19) | (0x07 << 9) | 0x1f,
88 .FILTune = 0x317 /* 0.90 V */
91 .symbolrate_low = 15000000,
92 .symbolrate_high = 45000000,
93 .VGAprogdata = (1 << 19) | (0x100 << 9) | 0x180,
94 .VCAprogdata = (2 << 19) | (0x07 << 9) | 0x3f,
95 .FILTune = 0x145 /* 2.70 V */
100 * Various tuner defaults need to be established for a given frequency kHz.
101 * fixme: The bounds on the bands do not match the doc in real life.
102 * fixme: Some of them have been moved, other might need adjustment.
110 } cx24123_bandselect_vals[] =
114 .freq_high = 1018999,
116 .progdata = (0 << 18) | (0 << 9) | 0x40,
120 .freq_high = 1074999,
122 .progdata = (0 << 18) | (0 << 9) | 0x80,
126 .freq_high = 1227999,
128 .progdata = (0 << 18) | (1 << 9) | 0x01,
132 .freq_high = 1349999,
134 .progdata = (0 << 18) | (1 << 9) | 0x02,
138 .freq_high = 1481999,
140 .progdata = (0 << 18) | (1 << 9) | 0x04,
144 .freq_high = 1595999,
146 .progdata = (0 << 18) | (1 << 9) | 0x08,
150 .freq_high = 1717999,
152 .progdata = (0 << 18) | (1 << 9) | 0x10,
156 .freq_high = 1855999,
158 .progdata = (0 << 18) | (1 << 9) | 0x20,
162 .freq_high = 2035999,
164 .progdata = (0 << 18) | (1 << 9) | 0x40,
168 .freq_high = 2149999,
170 .progdata = (0 << 18) | (1 << 9) | 0x80,
177 } cx24123_regdata[] =
179 {0x00, 0x03}, /* Reset system */
180 {0x00, 0x00}, /* Clear reset */
181 {0x03, 0x07}, /* QPSK, DVB, Auto Acquisition (default) */
182 {0x04, 0x10}, /* MPEG */
183 {0x05, 0x04}, /* MPEG */
184 {0x06, 0x31}, /* MPEG (default) */
185 {0x0b, 0x00}, /* Freq search start point (default) */
186 {0x0c, 0x00}, /* Demodulator sample gain (default) */
187 {0x0d, 0x02}, /* Frequency search range = Fsymbol / 4 (default) */
188 {0x0e, 0x03}, /* Default non-inverted, FEC 3/4 (default) */
189 {0x0f, 0xfe}, /* FEC search mask (all supported codes) */
190 {0x10, 0x01}, /* Default search inversion, no repeat (default) */
191 {0x16, 0x00}, /* Enable reading of frequency */
192 {0x17, 0x01}, /* Enable EsNO Ready Counter */
193 {0x1c, 0x80}, /* Enable error counter */
194 {0x20, 0x00}, /* Tuner burst clock rate = 500KHz */
195 {0x21, 0x15}, /* Tuner burst mode, word length = 0x15 */
196 {0x28, 0x00}, /* Enable FILTERV with positive pol., DiSEqC 2.x off */
197 {0x29, 0x00}, /* DiSEqC LNB_DC off */
198 {0x2a, 0xb0}, /* DiSEqC Parameters (default) */
199 {0x2b, 0x73}, /* DiSEqC Tone Frequency (default) */
200 {0x2c, 0x00}, /* DiSEqC Message (0x2c - 0x31) */
206 {0x32, 0x8c}, /* DiSEqC Parameters (default) */
207 {0x33, 0x00}, /* Interrupts off (0x33 - 0x34) */
209 {0x35, 0x03}, /* DiSEqC Tone Amplitude (default) */
210 {0x36, 0x02}, /* DiSEqC Parameters (default) */
211 {0x37, 0x3a}, /* DiSEqC Parameters (default) */
212 {0x3a, 0x00}, /* Enable AGC accumulator (for signal strength) */
213 {0x44, 0x00}, /* Constellation (default) */
214 {0x45, 0x00}, /* Symbol count (default) */
215 {0x46, 0x0d}, /* Symbol rate estimator on (default) */
216 {0x56, 0x41}, /* Various (default) */
217 {0x57, 0xff}, /* Error Counter Window (default) */
218 {0x67, 0x83}, /* Non-DCII symbol clock */
221 static int cx24123_writereg(struct cx24123_state* state, int reg, int data)
223 u8 buf[] = { reg, data };
224 struct i2c_msg msg = { .addr = state->config->demod_address, .flags = 0, .buf = buf, .len = 2 };
228 printk("cx24123: %s: write reg 0x%02x, value 0x%02x\n",
229 __FUNCTION__,reg, data);
231 if ((err = i2c_transfer(state->i2c, &msg, 1)) != 1) {
232 printk("%s: writereg error(err == %i, reg == 0x%02x,"
233 " data == 0x%02x)\n", __FUNCTION__, err, reg, data);
240 static int cx24123_writelnbreg(struct cx24123_state* state, int reg, int data)
242 u8 buf[] = { reg, data };
243 /* fixme: put the intersil addr int the config */
244 struct i2c_msg msg = { .addr = 0x08, .flags = 0, .buf = buf, .len = 2 };
248 printk("cx24123: %s: writeln addr=0x08, reg 0x%02x, value 0x%02x\n",
249 __FUNCTION__,reg, data);
251 if ((err = i2c_transfer(state->i2c, &msg, 1)) != 1) {
252 printk("%s: writelnbreg error (err == %i, reg == 0x%02x,"
253 " data == 0x%02x)\n", __FUNCTION__, err, reg, data);
257 /* cache the write, no way to read back */
258 state->lnbreg = data;
263 static int cx24123_readreg(struct cx24123_state* state, u8 reg)
268 struct i2c_msg msg[] = {
269 { .addr = state->config->demod_address, .flags = 0, .buf = b0, .len = 1 },
270 { .addr = state->config->demod_address, .flags = I2C_M_RD, .buf = b1, .len = 1 }
273 ret = i2c_transfer(state->i2c, msg, 2);
276 printk("%s: reg=0x%x (error=%d)\n", __FUNCTION__, reg, ret);
281 printk("cx24123: read reg 0x%02x, value 0x%02x\n",reg, ret);
286 static int cx24123_readlnbreg(struct cx24123_state* state, u8 reg)
288 return state->lnbreg;
291 static int cx24123_set_inversion(struct cx24123_state* state, fe_spectral_inversion_t inversion)
293 u8 nom_reg = cx24123_readreg(state, 0x0e);
294 u8 auto_reg = cx24123_readreg(state, 0x10);
298 dprintk("%s: inversion off\n",__FUNCTION__);
299 cx24123_writereg(state, 0x0e, nom_reg & ~0x80);
300 cx24123_writereg(state, 0x10, auto_reg | 0x80);
303 dprintk("%s: inversion on\n",__FUNCTION__);
304 cx24123_writereg(state, 0x0e, nom_reg | 0x80);
305 cx24123_writereg(state, 0x10, auto_reg | 0x80);
308 dprintk("%s: inversion auto\n",__FUNCTION__);
309 cx24123_writereg(state, 0x10, auto_reg & ~0x80);
318 static int cx24123_get_inversion(struct cx24123_state* state, fe_spectral_inversion_t *inversion)
322 val = cx24123_readreg(state, 0x1b) >> 7;
325 dprintk("%s: read inversion off\n",__FUNCTION__);
326 *inversion = INVERSION_OFF;
328 dprintk("%s: read inversion on\n",__FUNCTION__);
329 *inversion = INVERSION_ON;
335 static int cx24123_set_fec(struct cx24123_state* state, fe_code_rate_t fec)
337 u8 nom_reg = cx24123_readreg(state, 0x0e) & ~0x07;
339 if ( (fec < FEC_NONE) || (fec > FEC_AUTO) )
344 dprintk("%s: set FEC to 1/2\n",__FUNCTION__);
345 cx24123_writereg(state, 0x0e, nom_reg | 0x01);
346 cx24123_writereg(state, 0x0f, 0x02);
349 dprintk("%s: set FEC to 2/3\n",__FUNCTION__);
350 cx24123_writereg(state, 0x0e, nom_reg | 0x02);
351 cx24123_writereg(state, 0x0f, 0x04);
354 dprintk("%s: set FEC to 3/4\n",__FUNCTION__);
355 cx24123_writereg(state, 0x0e, nom_reg | 0x03);
356 cx24123_writereg(state, 0x0f, 0x08);
359 dprintk("%s: set FEC to 4/5\n",__FUNCTION__);
360 cx24123_writereg(state, 0x0e, nom_reg | 0x04);
361 cx24123_writereg(state, 0x0f, 0x10);
364 dprintk("%s: set FEC to 5/6\n",__FUNCTION__);
365 cx24123_writereg(state, 0x0e, nom_reg | 0x05);
366 cx24123_writereg(state, 0x0f, 0x20);
369 dprintk("%s: set FEC to 6/7\n",__FUNCTION__);
370 cx24123_writereg(state, 0x0e, nom_reg | 0x06);
371 cx24123_writereg(state, 0x0f, 0x40);
374 dprintk("%s: set FEC to 7/8\n",__FUNCTION__);
375 cx24123_writereg(state, 0x0e, nom_reg | 0x07);
376 cx24123_writereg(state, 0x0f, 0x80);
379 dprintk("%s: set FEC to auto\n",__FUNCTION__);
380 cx24123_writereg(state, 0x0f, 0xfe);
389 static int cx24123_get_fec(struct cx24123_state* state, fe_code_rate_t *fec)
393 ret = cx24123_readreg (state, 0x1b);
421 /* this can happen when there's no lock */
428 /* Approximation of closest integer of log2(a/b). It actually gives the
429 lowest integer i such that 2^i >= round(a/b) */
430 static u32 cx24123_int_log2(u32 a, u32 b)
432 u32 exp, nearest = 0;
434 if(a % b >= b / 2) ++div;
437 for(exp = 1; div > exp; nearest++)
443 static int cx24123_set_symbolrate(struct cx24123_state* state, u32 srate)
445 u32 tmp, sample_rate, ratio, sample_gain;
448 /* check if symbol rate is within limits */
449 if ((srate > state->ops.info.symbol_rate_max) ||
450 (srate < state->ops.info.symbol_rate_min))
453 /* choose the sampling rate high enough for the required operation,
454 while optimizing the power consumed by the demodulator */
455 if (srate < (XTAL*2)/2)
457 else if (srate < (XTAL*3)/2)
459 else if (srate < (XTAL*4)/2)
461 else if (srate < (XTAL*5)/2)
463 else if (srate < (XTAL*6)/2)
465 else if (srate < (XTAL*7)/2)
467 else if (srate < (XTAL*8)/2)
473 sample_rate = pll_mult * XTAL;
476 SYSSymbolRate[21:0] = (srate << 23) / sample_rate
478 We have to use 32 bit unsigned arithmetic without precision loss.
479 The maximum srate is 45000000 or 0x02AEA540. This number has
480 only 6 clear bits on top, hence we can shift it left only 6 bits
481 at a time. Borrowed from cx24110.c
485 ratio = tmp / sample_rate;
487 tmp = (tmp % sample_rate) << 6;
488 ratio = (ratio << 6) + (tmp / sample_rate);
490 tmp = (tmp % sample_rate) << 6;
491 ratio = (ratio << 6) + (tmp / sample_rate);
493 tmp = (tmp % sample_rate) << 5;
494 ratio = (ratio << 5) + (tmp / sample_rate);
497 cx24123_writereg(state, 0x01, pll_mult * 6);
499 cx24123_writereg(state, 0x08, (ratio >> 16) & 0x3f );
500 cx24123_writereg(state, 0x09, (ratio >> 8) & 0xff );
501 cx24123_writereg(state, 0x0a, (ratio ) & 0xff );
503 /* also set the demodulator sample gain */
504 sample_gain = cx24123_int_log2(sample_rate, srate);
505 tmp = cx24123_readreg(state, 0x0c) & ~0xe0;
506 cx24123_writereg(state, 0x0c, tmp | sample_gain << 5);
508 dprintk("%s: srate=%d, ratio=0x%08x, sample_rate=%i sample_gain=%d\n", __FUNCTION__, srate, ratio, sample_rate, sample_gain);
514 * Based on the required frequency and symbolrate, the tuner AGC has to be configured
515 * and the correct band selected. Calculate those values
517 static int cx24123_pll_calculate(struct dvb_frontend* fe, struct dvb_frontend_parameters *p)
519 struct cx24123_state *state = fe->demodulator_priv;
520 u32 ndiv = 0, adiv = 0, vco_div = 0;
524 /* Defaults for low freq, low rate */
525 state->VCAarg = cx24123_AGC_vals[0].VCAprogdata;
526 state->VGAarg = cx24123_AGC_vals[0].VGAprogdata;
527 state->bandselectarg = cx24123_bandselect_vals[0].progdata;
528 vco_div = cx24123_bandselect_vals[0].VCOdivider;
530 /* For the given symbol rate, determine the VCA, VGA and FILTUNE programming bits */
531 for (i = 0; i < sizeof(cx24123_AGC_vals) / sizeof(cx24123_AGC_vals[0]); i++)
533 if ((cx24123_AGC_vals[i].symbolrate_low <= p->u.qpsk.symbol_rate) &&
534 (cx24123_AGC_vals[i].symbolrate_high >= p->u.qpsk.symbol_rate) ) {
535 state->VCAarg = cx24123_AGC_vals[i].VCAprogdata;
536 state->VGAarg = cx24123_AGC_vals[i].VGAprogdata;
537 state->FILTune = cx24123_AGC_vals[i].FILTune;
541 /* For the given frequency, determine the bandselect programming bits */
542 for (i = 0; i < sizeof(cx24123_bandselect_vals) / sizeof(cx24123_bandselect_vals[0]); i++)
544 if ((cx24123_bandselect_vals[i].freq_low <= p->frequency) &&
545 (cx24123_bandselect_vals[i].freq_high >= p->frequency) ) {
546 state->bandselectarg = cx24123_bandselect_vals[i].progdata;
547 vco_div = cx24123_bandselect_vals[i].VCOdivider;
549 /* determine the charge pump current */
550 if ( p->frequency < (cx24123_bandselect_vals[i].freq_low + cx24123_bandselect_vals[i].freq_high)/2 )
557 /* Determine the N/A dividers for the requested lband freq (in kHz). */
558 /* Note: the reference divider R=10, frequency is in KHz, XTAL is in Hz */
559 ndiv = ( ((p->frequency * vco_div * 10) / (2 * XTAL / 1000)) / 32) & 0x1ff;
560 adiv = ( ((p->frequency * vco_div * 10) / (2 * XTAL / 1000)) % 32) & 0x1f;
565 /* control bits 11, refdiv 11, charge pump polarity 1, charge pump current, ndiv, adiv */
566 state->pllarg = (3 << 19) | (3 << 17) | (1 << 16) | (pump << 14) | (ndiv << 5) | adiv;
572 * Tuner data is 21 bits long, must be left-aligned in data.
573 * Tuner cx24109 is written through a dedicated 3wire interface on the demod chip.
575 static int cx24123_pll_writereg(struct dvb_frontend* fe, struct dvb_frontend_parameters *p, u32 data)
577 struct cx24123_state *state = fe->demodulator_priv;
578 unsigned long timeout;
580 dprintk("%s: pll writereg called, data=0x%08x\n",__FUNCTION__,data);
582 /* align the 21 bytes into to bit23 boundary */
585 /* Reset the demod pll word length to 0x15 bits */
586 cx24123_writereg(state, 0x21, 0x15);
588 /* write the msb 8 bits, wait for the send to be completed */
589 timeout = jiffies + msecs_to_jiffies(40);
590 cx24123_writereg(state, 0x22, (data >> 16) & 0xff);
591 while ((cx24123_readreg(state, 0x20) & 0x40) == 0) {
592 if (time_after(jiffies, timeout)) {
593 printk("%s: demodulator is not responding, possibly hung, aborting.\n", __FUNCTION__);
599 /* send another 8 bytes, wait for the send to be completed */
600 timeout = jiffies + msecs_to_jiffies(40);
601 cx24123_writereg(state, 0x22, (data>>8) & 0xff );
602 while ((cx24123_readreg(state, 0x20) & 0x40) == 0) {
603 if (time_after(jiffies, timeout)) {
604 printk("%s: demodulator is not responding, possibly hung, aborting.\n", __FUNCTION__);
610 /* send the lower 5 bits of this byte, padded with 3 LBB, wait for the send to be completed */
611 timeout = jiffies + msecs_to_jiffies(40);
612 cx24123_writereg(state, 0x22, (data) & 0xff );
613 while ((cx24123_readreg(state, 0x20) & 0x80)) {
614 if (time_after(jiffies, timeout)) {
615 printk("%s: demodulator is not responding, possibly hung, aborting.\n", __FUNCTION__);
621 /* Trigger the demod to configure the tuner */
622 cx24123_writereg(state, 0x20, cx24123_readreg(state, 0x20) | 2);
623 cx24123_writereg(state, 0x20, cx24123_readreg(state, 0x20) & 0xfd);
628 static int cx24123_pll_tune(struct dvb_frontend* fe, struct dvb_frontend_parameters *p)
630 struct cx24123_state *state = fe->demodulator_priv;
633 dprintk("frequency=%i\n", p->frequency);
635 if (cx24123_pll_calculate(fe, p) != 0) {
636 printk("%s: cx24123_pll_calcutate failed\n",__FUNCTION__);
640 /* Write the new VCO/VGA */
641 cx24123_pll_writereg(fe, p, state->VCAarg);
642 cx24123_pll_writereg(fe, p, state->VGAarg);
644 /* Write the new bandselect and pll args */
645 cx24123_pll_writereg(fe, p, state->bandselectarg);
646 cx24123_pll_writereg(fe, p, state->pllarg);
648 /* set the FILTUNE voltage */
649 val = cx24123_readreg(state, 0x28) & ~0x3;
650 cx24123_writereg(state, 0x27, state->FILTune >> 2);
651 cx24123_writereg(state, 0x28, val | (state->FILTune & 0x3));
653 dprintk("%s: pll tune VCA=%d, band=%d, pll=%d\n",__FUNCTION__,state->VCAarg,
654 state->bandselectarg,state->pllarg);
659 static int cx24123_initfe(struct dvb_frontend* fe)
661 struct cx24123_state *state = fe->demodulator_priv;
664 dprintk("%s: init frontend\n",__FUNCTION__);
666 /* Configure the demod to a good set of defaults */
667 for (i = 0; i < sizeof(cx24123_regdata) / sizeof(cx24123_regdata[0]); i++)
668 cx24123_writereg(state, cx24123_regdata[i].reg, cx24123_regdata[i].data);
670 if (state->config->pll_init)
671 state->config->pll_init(fe);
673 /* Configure the LNB for 14V */
674 if (state->config->use_isl6421)
675 cx24123_writelnbreg(state, 0x0, 0x2a);
680 static int cx24123_set_voltage(struct dvb_frontend* fe, fe_sec_voltage_t voltage)
682 struct cx24123_state *state = fe->demodulator_priv;
685 switch (state->config->use_isl6421) {
689 val = cx24123_readlnbreg(state, 0x0);
693 dprintk("%s: isl6421 voltage = 13V\n",__FUNCTION__);
694 return cx24123_writelnbreg(state, 0x0, val & 0x32); /* V 13v */
696 dprintk("%s: isl6421 voltage = 18V\n",__FUNCTION__);
697 return cx24123_writelnbreg(state, 0x0, val | 0x04); /* H 18v */
698 case SEC_VOLTAGE_OFF:
699 dprintk("%s: isl5421 voltage off\n",__FUNCTION__);
700 return cx24123_writelnbreg(state, 0x0, val & 0x30);
707 val = cx24123_readreg(state, 0x29);
711 dprintk("%s: setting voltage 13V\n", __FUNCTION__);
712 if (state->config->enable_lnb_voltage)
713 state->config->enable_lnb_voltage(fe, 1);
714 return cx24123_writereg(state, 0x29, val | 0x80);
716 dprintk("%s: setting voltage 18V\n", __FUNCTION__);
717 if (state->config->enable_lnb_voltage)
718 state->config->enable_lnb_voltage(fe, 1);
719 return cx24123_writereg(state, 0x29, val & 0x7f);
720 case SEC_VOLTAGE_OFF:
721 dprintk("%s: setting voltage off\n", __FUNCTION__);
722 if (state->config->enable_lnb_voltage)
723 state->config->enable_lnb_voltage(fe, 0);
733 /* wait for diseqc queue to become ready (or timeout) */
734 static void cx24123_wait_for_diseqc(struct cx24123_state *state)
736 unsigned long timeout = jiffies + msecs_to_jiffies(200);
737 while (!(cx24123_readreg(state, 0x29) & 0x40)) {
738 if(time_after(jiffies, timeout)) {
739 printk("%s: diseqc queue not ready, command may be lost.\n", __FUNCTION__);
746 static int cx24123_send_diseqc_msg(struct dvb_frontend* fe, struct dvb_diseqc_master_cmd *cmd)
748 struct cx24123_state *state = fe->demodulator_priv;
751 dprintk("%s:\n",__FUNCTION__);
753 /* check if continuous tone has been stopped */
754 if (state->config->use_isl6421)
755 val = cx24123_readlnbreg(state, 0x00) & 0x10;
757 val = cx24123_readreg(state, 0x29) & 0x10;
761 printk("%s: ERROR: attempt to send diseqc command before tone is off\n", __FUNCTION__);
765 /* wait for diseqc queue ready */
766 cx24123_wait_for_diseqc(state);
768 /* select tone mode */
769 cx24123_writereg(state, 0x2a, cx24123_readreg(state, 0x2a) & 0xf8);
771 for (i = 0; i < cmd->msg_len; i++)
772 cx24123_writereg(state, 0x2C + i, cmd->msg[i]);
774 val = cx24123_readreg(state, 0x29);
775 cx24123_writereg(state, 0x29, ((val & 0x90) | 0x40) | ((cmd->msg_len-3) & 3));
777 /* wait for diseqc message to finish sending */
778 cx24123_wait_for_diseqc(state);
783 static int cx24123_diseqc_send_burst(struct dvb_frontend* fe, fe_sec_mini_cmd_t burst)
785 struct cx24123_state *state = fe->demodulator_priv;
788 dprintk("%s:\n", __FUNCTION__);
790 /* check if continuous tone has been stoped */
791 if (state->config->use_isl6421)
792 val = cx24123_readlnbreg(state, 0x00) & 0x10;
794 val = cx24123_readreg(state, 0x29) & 0x10;
798 printk("%s: ERROR: attempt to send diseqc command before tone is off\n", __FUNCTION__);
802 cx24123_wait_for_diseqc(state);
804 /* select tone mode */
805 val = cx24123_readreg(state, 0x2a) & 0xf8;
806 cx24123_writereg(state, 0x2a, val | 0x04);
808 val = cx24123_readreg(state, 0x29);
810 if (burst == SEC_MINI_A)
811 cx24123_writereg(state, 0x29, ((val & 0x90) | 0x40 | 0x00));
812 else if (burst == SEC_MINI_B)
813 cx24123_writereg(state, 0x29, ((val & 0x90) | 0x40 | 0x08));
817 cx24123_wait_for_diseqc(state);
822 static int cx24123_read_status(struct dvb_frontend* fe, fe_status_t* status)
824 struct cx24123_state *state = fe->demodulator_priv;
826 int sync = cx24123_readreg(state, 0x14);
827 int lock = cx24123_readreg(state, 0x20);
831 *status |= FE_HAS_SIGNAL;
833 *status |= FE_HAS_CARRIER;
835 *status |= FE_HAS_VITERBI;
837 *status |= FE_HAS_SYNC;
839 *status |= FE_HAS_LOCK;
845 * Configured to return the measurement of errors in blocks, because no UCBLOCKS value
846 * is available, so this value doubles up to satisfy both measurements
848 static int cx24123_read_ber(struct dvb_frontend* fe, u32* ber)
850 struct cx24123_state *state = fe->demodulator_priv;
853 ((cx24123_readreg(state, 0x1c) & 0x3f) << 16) |
854 (cx24123_readreg(state, 0x1d) << 8 |
855 cx24123_readreg(state, 0x1e));
857 /* Do the signal quality processing here, it's derived from the BER. */
858 /* Scale the BER from a 24bit to a SNR 16 bit where higher = better */
859 if (state->lastber < 5000)
860 state->snr = 655*100;
861 else if ( (state->lastber >= 5000) && (state->lastber < 55000) )
863 else if ( (state->lastber >= 55000) && (state->lastber < 150000) )
865 else if ( (state->lastber >= 150000) && (state->lastber < 250000) )
867 else if ( (state->lastber >= 250000) && (state->lastber < 450000) )
872 dprintk("%s: BER = %d, S/N index = %d\n",__FUNCTION__,state->lastber, state->snr);
874 *ber = state->lastber;
879 static int cx24123_read_signal_strength(struct dvb_frontend* fe, u16* signal_strength)
881 struct cx24123_state *state = fe->demodulator_priv;
882 *signal_strength = cx24123_readreg(state, 0x3b) << 8; /* larger = better */
884 dprintk("%s: Signal strength = %d\n",__FUNCTION__,*signal_strength);
889 static int cx24123_read_snr(struct dvb_frontend* fe, u16* snr)
891 struct cx24123_state *state = fe->demodulator_priv;
894 dprintk("%s: read S/N index = %d\n",__FUNCTION__,*snr);
899 static int cx24123_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks)
901 struct cx24123_state *state = fe->demodulator_priv;
902 *ucblocks = state->lastber;
904 dprintk("%s: ucblocks (ber) = %d\n",__FUNCTION__,*ucblocks);
909 static int cx24123_set_frontend(struct dvb_frontend* fe, struct dvb_frontend_parameters *p)
911 struct cx24123_state *state = fe->demodulator_priv;
913 dprintk("%s: set_frontend\n",__FUNCTION__);
915 if (state->config->set_ts_params)
916 state->config->set_ts_params(fe, 0);
918 state->currentfreq=p->frequency;
919 state->currentsymbolrate = p->u.qpsk.symbol_rate;
921 cx24123_set_inversion(state, p->inversion);
922 cx24123_set_fec(state, p->u.qpsk.fec_inner);
923 cx24123_set_symbolrate(state, p->u.qpsk.symbol_rate);
924 cx24123_pll_tune(fe, p);
926 /* Enable automatic aquisition and reset cycle */
927 cx24123_writereg(state, 0x03, (cx24123_readreg(state, 0x03) | 0x07));
928 cx24123_writereg(state, 0x00, 0x10);
929 cx24123_writereg(state, 0x00, 0);
934 static int cx24123_get_frontend(struct dvb_frontend* fe, struct dvb_frontend_parameters *p)
936 struct cx24123_state *state = fe->demodulator_priv;
938 dprintk("%s: get_frontend\n",__FUNCTION__);
940 if (cx24123_get_inversion(state, &p->inversion) != 0) {
941 printk("%s: Failed to get inversion status\n",__FUNCTION__);
944 if (cx24123_get_fec(state, &p->u.qpsk.fec_inner) != 0) {
945 printk("%s: Failed to get fec status\n",__FUNCTION__);
948 p->frequency = state->currentfreq;
949 p->u.qpsk.symbol_rate = state->currentsymbolrate;
954 static int cx24123_set_tone(struct dvb_frontend* fe, fe_sec_tone_mode_t tone)
956 struct cx24123_state *state = fe->demodulator_priv;
959 switch (state->config->use_isl6421) {
962 val = cx24123_readlnbreg(state, 0x0);
966 dprintk("%s: isl6421 sec tone on\n",__FUNCTION__);
967 return cx24123_writelnbreg(state, 0x0, val | 0x10);
969 dprintk("%s: isl6421 sec tone off\n",__FUNCTION__);
970 return cx24123_writelnbreg(state, 0x0, val & 0x2f);
972 printk("%s: CASE reached default with tone=%d\n", __FUNCTION__, tone);
978 val = cx24123_readreg(state, 0x29);
982 dprintk("%s: setting tone on\n", __FUNCTION__);
983 return cx24123_writereg(state, 0x29, val | 0x10);
985 dprintk("%s: setting tone off\n",__FUNCTION__);
986 return cx24123_writereg(state, 0x29, val & 0xef);
988 printk("%s: CASE reached default with tone=%d\n", __FUNCTION__, tone);
996 static void cx24123_release(struct dvb_frontend* fe)
998 struct cx24123_state* state = fe->demodulator_priv;
999 dprintk("%s\n",__FUNCTION__);
1003 static struct dvb_frontend_ops cx24123_ops;
1005 struct dvb_frontend* cx24123_attach(const struct cx24123_config* config,
1006 struct i2c_adapter* i2c)
1008 struct cx24123_state* state = NULL;
1011 dprintk("%s\n",__FUNCTION__);
1013 /* allocate memory for the internal state */
1014 state = kmalloc(sizeof(struct cx24123_state), GFP_KERNEL);
1015 if (state == NULL) {
1016 printk("Unable to kmalloc\n");
1020 /* setup the state */
1021 state->config = config;
1023 memcpy(&state->ops, &cx24123_ops, sizeof(struct dvb_frontend_ops));
1029 state->bandselectarg = 0;
1031 state->currentfreq = 0;
1032 state->currentsymbolrate = 0;
1034 /* check if the demod is there */
1035 ret = cx24123_readreg(state, 0x00);
1036 if ((ret != 0xd1) && (ret != 0xe1)) {
1037 printk("Version != d1 or e1\n");
1041 /* create dvb_frontend */
1042 state->frontend.ops = &state->ops;
1043 state->frontend.demodulator_priv = state;
1044 return &state->frontend;
1052 static struct dvb_frontend_ops cx24123_ops = {
1055 .name = "Conexant CX24123/CX24109",
1057 .frequency_min = 950000,
1058 .frequency_max = 2150000,
1059 .frequency_stepsize = 1011, /* kHz for QPSK frontends */
1060 .frequency_tolerance = 5000,
1061 .symbol_rate_min = 1000000,
1062 .symbol_rate_max = 45000000,
1063 .caps = FE_CAN_INVERSION_AUTO |
1064 FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
1065 FE_CAN_FEC_4_5 | FE_CAN_FEC_5_6 | FE_CAN_FEC_6_7 |
1066 FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
1067 FE_CAN_QPSK | FE_CAN_RECOVER
1070 .release = cx24123_release,
1072 .init = cx24123_initfe,
1073 .set_frontend = cx24123_set_frontend,
1074 .get_frontend = cx24123_get_frontend,
1075 .read_status = cx24123_read_status,
1076 .read_ber = cx24123_read_ber,
1077 .read_signal_strength = cx24123_read_signal_strength,
1078 .read_snr = cx24123_read_snr,
1079 .read_ucblocks = cx24123_read_ucblocks,
1080 .diseqc_send_master_cmd = cx24123_send_diseqc_msg,
1081 .diseqc_send_burst = cx24123_diseqc_send_burst,
1082 .set_tone = cx24123_set_tone,
1083 .set_voltage = cx24123_set_voltage,
1086 module_param(debug, int, 0644);
1087 MODULE_PARM_DESC(debug, "Activates frontend debugging (default:0)");
1089 MODULE_DESCRIPTION("DVB Frontend module for Conexant cx24123/cx24109 hardware");
1090 MODULE_AUTHOR("Steven Toth");
1091 MODULE_LICENSE("GPL");
1093 EXPORT_SYMBOL(cx24123_attach);