2 Driver for Zarlink VP310/MT312 Satellite Channel Decoder
4 Copyright (C) 2003 Andreas Oberritter <obi@linuxtv.org>
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2 of the License, or
9 (at your option) any later version.
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 http://products.zarlink.com/product_profiles/MT312.htm
23 http://products.zarlink.com/product_profiles/SL1935.htm
26 #include <linux/delay.h>
27 #include <linux/errno.h>
28 #include <linux/init.h>
29 #include <linux/kernel.h>
30 #include <linux/module.h>
31 #include <linux/string.h>
32 #include <linux/slab.h>
34 #include "dvb_frontend.h"
35 #include "mt312_priv.h"
40 struct i2c_adapter *i2c;
41 /* configuration settings */
42 const struct mt312_config *config;
43 struct dvb_frontend frontend;
50 #define dprintk(args...) \
53 printk(KERN_DEBUG "mt312: " args); \
56 #define MT312_SYS_CLK 90000000UL /* 90 MHz */
57 #define MT312_LPOWER_SYS_CLK 60000000UL /* 60 MHz */
58 #define MT312_PLL_CLK 10000000UL /* 10 MHz */
60 static int mt312_read(struct mt312_state *state, const enum mt312_reg_addr reg,
61 u8 *buf, const size_t count)
64 struct i2c_msg msg[2];
65 u8 regbuf[1] = { reg };
67 msg[0].addr = state->config->demod_address;
71 msg[1].addr = state->config->demod_address;
72 msg[1].flags = I2C_M_RD;
76 ret = i2c_transfer(state->i2c, msg, 2);
79 printk(KERN_ERR "%s: ret == %d\n", __func__, ret);
85 dprintk("R(%d):", reg & 0x7f);
86 for (i = 0; i < count; i++)
87 printk(" %02x", buf[i]);
94 static int mt312_write(struct mt312_state *state, const enum mt312_reg_addr reg,
95 const u8 *src, const size_t count)
103 dprintk("W(%d):", reg & 0x7f);
104 for (i = 0; i < count; i++)
105 printk(" %02x", src[i]);
110 memcpy(&buf[1], src, count);
112 msg.addr = state->config->demod_address;
117 ret = i2c_transfer(state->i2c, &msg, 1);
120 dprintk("%s: ret == %d\n", __func__, ret);
127 static inline int mt312_readreg(struct mt312_state *state,
128 const enum mt312_reg_addr reg, u8 *val)
130 return mt312_read(state, reg, val, 1);
133 static inline int mt312_writereg(struct mt312_state *state,
134 const enum mt312_reg_addr reg, const u8 val)
136 return mt312_write(state, reg, &val, 1);
139 static inline u32 mt312_div(u32 a, u32 b)
141 return (a + (b / 2)) / b;
144 static int mt312_reset(struct mt312_state *state, const u8 full)
146 return mt312_writereg(state, RESET, full ? 0x80 : 0x40);
149 static int mt312_get_inversion(struct mt312_state *state,
150 fe_spectral_inversion_t *i)
155 ret = mt312_readreg(state, VIT_MODE, &vit_mode);
159 if (vit_mode & 0x80) /* auto inversion was used */
160 *i = (vit_mode & 0x40) ? INVERSION_ON : INVERSION_OFF;
165 static int mt312_get_symbol_rate(struct mt312_state *state, u32 *sr)
174 ret = mt312_readreg(state, SYM_RATE_H, &sym_rate_h);
178 if (sym_rate_h & 0x80) {
179 /* symbol rate search was used */
180 ret = mt312_writereg(state, MON_CTRL, 0x03);
184 ret = mt312_read(state, MONITOR_H, buf, sizeof(buf));
188 monitor = (buf[0] << 8) | buf[1];
190 dprintk("sr(auto) = %u\n",
191 mt312_div(monitor * 15625, 4));
193 ret = mt312_writereg(state, MON_CTRL, 0x05);
197 ret = mt312_read(state, MONITOR_H, buf, sizeof(buf));
201 dec_ratio = ((buf[0] >> 5) & 0x07) * 32;
203 ret = mt312_read(state, SYM_RAT_OP_H, buf, sizeof(buf));
207 sym_rat_op = (buf[0] << 8) | buf[1];
209 dprintk("sym_rat_op=%d dec_ratio=%d\n",
210 sym_rat_op, dec_ratio);
211 dprintk("*sr(manual) = %lu\n",
212 (((MT312_PLL_CLK * 8192) / (sym_rat_op + 8192)) *
219 static int mt312_get_code_rate(struct mt312_state *state, fe_code_rate_t *cr)
221 const fe_code_rate_t fec_tab[8] =
222 { FEC_1_2, FEC_2_3, FEC_3_4, FEC_5_6, FEC_6_7, FEC_7_8,
223 FEC_AUTO, FEC_AUTO };
228 ret = mt312_readreg(state, FEC_STATUS, &fec_status);
232 *cr = fec_tab[(fec_status >> 4) & 0x07];
237 static int mt312_initfe(struct dvb_frontend *fe)
239 struct mt312_state *state = fe->demodulator_priv;
244 ret = mt312_writereg(state, CONFIG,
245 (state->frequency == 60 ? 0x88 : 0x8c));
249 /* wait at least 150 usec */
253 ret = mt312_reset(state, 1);
257 /* Per datasheet, write correct values. 09/28/03 ACCJr.
258 * If we don't do this, we won't get FE_HAS_VITERBI in the VP310. */
260 u8 buf_def[8] = { 0x14, 0x12, 0x03, 0x02,
261 0x01, 0x00, 0x00, 0x00 };
263 ret = mt312_write(state, VIT_SETUP, buf_def, sizeof(buf_def));
269 buf[0] = mt312_div((state->frequency == 60 ? MT312_LPOWER_SYS_CLK :
270 MT312_SYS_CLK) * 2, 1000000);
273 buf[1] = mt312_div(MT312_PLL_CLK, 22000 * 4);
275 ret = mt312_write(state, SYS_CLK, buf, sizeof(buf));
279 ret = mt312_writereg(state, SNR_THS_HIGH, 0x32);
283 ret = mt312_writereg(state, OP_CTRL, 0x53);
291 ret = mt312_write(state, TS_SW_LIM_L, buf, sizeof(buf));
295 ret = mt312_writereg(state, CS_SW_LIM, 0x69);
302 static int mt312_send_master_cmd(struct dvb_frontend *fe,
303 struct dvb_diseqc_master_cmd *c)
305 struct mt312_state *state = fe->demodulator_priv;
309 if ((c->msg_len == 0) || (c->msg_len > sizeof(c->msg)))
312 ret = mt312_readreg(state, DISEQC_MODE, &diseqc_mode);
316 ret = mt312_write(state, (0x80 | DISEQC_INSTR), c->msg, c->msg_len);
320 ret = mt312_writereg(state, DISEQC_MODE,
321 (diseqc_mode & 0x40) | ((c->msg_len - 1) << 3)
326 /* is there a better way to wait for message to be transmitted */
329 /* set DISEQC_MODE[2:0] to zero if a return message is expected */
330 if (c->msg[0] & 0x02) {
331 ret = mt312_writereg(state, DISEQC_MODE, (diseqc_mode & 0x40));
339 static int mt312_send_burst(struct dvb_frontend *fe, const fe_sec_mini_cmd_t c)
341 struct mt312_state *state = fe->demodulator_priv;
342 const u8 mini_tab[2] = { 0x02, 0x03 };
350 ret = mt312_readreg(state, DISEQC_MODE, &diseqc_mode);
354 ret = mt312_writereg(state, DISEQC_MODE,
355 (diseqc_mode & 0x40) | mini_tab[c]);
362 static int mt312_set_tone(struct dvb_frontend *fe, const fe_sec_tone_mode_t t)
364 struct mt312_state *state = fe->demodulator_priv;
365 const u8 tone_tab[2] = { 0x01, 0x00 };
370 if (t > SEC_TONE_OFF)
373 ret = mt312_readreg(state, DISEQC_MODE, &diseqc_mode);
377 ret = mt312_writereg(state, DISEQC_MODE,
378 (diseqc_mode & 0x40) | tone_tab[t]);
385 static int mt312_set_voltage(struct dvb_frontend *fe, const fe_sec_voltage_t v)
387 struct mt312_state *state = fe->demodulator_priv;
388 const u8 volt_tab[3] = { 0x00, 0x40, 0x00 };
390 if (v > SEC_VOLTAGE_OFF)
393 return mt312_writereg(state, DISEQC_MODE, volt_tab[v]);
396 static int mt312_read_status(struct dvb_frontend *fe, fe_status_t *s)
398 struct mt312_state *state = fe->demodulator_priv;
404 ret = mt312_read(state, QPSK_STAT_H, status, sizeof(status));
408 dprintk("QPSK_STAT_H: 0x%02x, QPSK_STAT_L: 0x%02x,"
409 " FEC_STATUS: 0x%02x\n", status[0], status[1], status[2]);
411 if (status[0] & 0xc0)
412 *s |= FE_HAS_SIGNAL; /* signal noise ratio */
413 if (status[0] & 0x04)
414 *s |= FE_HAS_CARRIER; /* qpsk carrier lock */
415 if (status[2] & 0x02)
416 *s |= FE_HAS_VITERBI; /* viterbi lock */
417 if (status[2] & 0x04)
418 *s |= FE_HAS_SYNC; /* byte align lock */
419 if (status[0] & 0x01)
420 *s |= FE_HAS_LOCK; /* qpsk lock */
425 static int mt312_read_ber(struct dvb_frontend *fe, u32 *ber)
427 struct mt312_state *state = fe->demodulator_priv;
431 ret = mt312_read(state, RS_BERCNT_H, buf, 3);
435 *ber = ((buf[0] << 16) | (buf[1] << 8) | buf[2]) * 64;
440 static int mt312_read_signal_strength(struct dvb_frontend *fe,
441 u16 *signal_strength)
443 struct mt312_state *state = fe->demodulator_priv;
449 ret = mt312_read(state, AGC_H, buf, sizeof(buf));
453 agc = (buf[0] << 6) | (buf[1] >> 2);
454 err_db = (s16) (((buf[1] & 0x03) << 14) | buf[2] << 6) >> 6;
456 *signal_strength = agc;
458 dprintk("agc=%08x err_db=%hd\n", agc, err_db);
463 static int mt312_read_snr(struct dvb_frontend *fe, u16 *snr)
465 struct mt312_state *state = fe->demodulator_priv;
469 ret = mt312_read(state, M_SNR_H, buf, sizeof(buf));
473 *snr = 0xFFFF - ((((buf[0] & 0x7f) << 8) | buf[1]) << 1);
478 static int mt312_read_ucblocks(struct dvb_frontend *fe, u32 *ubc)
480 struct mt312_state *state = fe->demodulator_priv;
484 ret = mt312_read(state, RS_UBC_H, buf, sizeof(buf));
488 *ubc = (buf[0] << 8) | buf[1];
493 static int mt312_set_frontend(struct dvb_frontend *fe,
494 struct dvb_frontend_parameters *p)
496 struct mt312_state *state = fe->demodulator_priv;
498 u8 buf[5], config_val;
501 const u8 fec_tab[10] =
502 { 0x00, 0x01, 0x02, 0x04, 0x3f, 0x08, 0x10, 0x20, 0x3f, 0x3f };
503 const u8 inv_tab[3] = { 0x00, 0x40, 0x80 };
505 dprintk("%s: Freq %d\n", __func__, p->frequency);
507 if ((p->frequency < fe->ops.info.frequency_min)
508 || (p->frequency > fe->ops.info.frequency_max))
511 if ((p->inversion < INVERSION_OFF)
512 || (p->inversion > INVERSION_ON))
515 if ((p->u.qpsk.symbol_rate < fe->ops.info.symbol_rate_min)
516 || (p->u.qpsk.symbol_rate > fe->ops.info.symbol_rate_max))
519 if ((p->u.qpsk.fec_inner < FEC_NONE)
520 || (p->u.qpsk.fec_inner > FEC_AUTO))
523 if ((p->u.qpsk.fec_inner == FEC_4_5)
524 || (p->u.qpsk.fec_inner == FEC_8_9))
529 /* For now we will do this only for the VP310.
530 * It should be better for the mt312 as well,
531 * but tuning will be slower. ACCJr 09/29/03
533 ret = mt312_readreg(state, CONFIG, &config_val);
536 if (p->u.qpsk.symbol_rate >= 30000000) {
537 /* Note that 30MS/s should use 90MHz */
538 if ((config_val & 0x0c) == 0x08) {
539 /* We are running 60MHz */
540 state->frequency = 90;
541 ret = mt312_initfe(fe);
546 if ((config_val & 0x0c) == 0x0C) {
547 /* We are running 90MHz */
548 state->frequency = 60;
549 ret = mt312_initfe(fe);
563 if (fe->ops.tuner_ops.set_params) {
564 fe->ops.tuner_ops.set_params(fe, p);
565 if (fe->ops.i2c_gate_ctrl)
566 fe->ops.i2c_gate_ctrl(fe, 0);
569 /* sr = (u16)(sr * 256.0 / 1000000.0) */
570 sr = mt312_div(p->u.qpsk.symbol_rate * 4, 15625);
573 buf[0] = (sr >> 8) & 0x3f;
574 buf[1] = (sr >> 0) & 0xff;
577 buf[2] = inv_tab[p->inversion] | fec_tab[p->u.qpsk.fec_inner];
580 buf[3] = 0x40; /* swap I and Q before QPSK demodulation */
582 if (p->u.qpsk.symbol_rate < 10000000)
583 buf[3] |= 0x04; /* use afc mode */
588 ret = mt312_write(state, SYM_RATE_H, buf, sizeof(buf));
592 mt312_reset(state, 0);
597 static int mt312_get_frontend(struct dvb_frontend *fe,
598 struct dvb_frontend_parameters *p)
600 struct mt312_state *state = fe->demodulator_priv;
603 ret = mt312_get_inversion(state, &p->inversion);
607 ret = mt312_get_symbol_rate(state, &p->u.qpsk.symbol_rate);
611 ret = mt312_get_code_rate(state, &p->u.qpsk.fec_inner);
618 static int mt312_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
620 struct mt312_state *state = fe->demodulator_priv;
623 return mt312_writereg(state, GPP_CTRL, 0x40);
625 return mt312_writereg(state, GPP_CTRL, 0x00);
629 static int mt312_sleep(struct dvb_frontend *fe)
631 struct mt312_state *state = fe->demodulator_priv;
635 /* reset all registers to defaults */
636 ret = mt312_reset(state, 1);
640 ret = mt312_readreg(state, CONFIG, &config);
645 ret = mt312_writereg(state, CONFIG, config & 0x7f);
652 static int mt312_get_tune_settings(struct dvb_frontend *fe,
653 struct dvb_frontend_tune_settings *fesettings)
655 fesettings->min_delay_ms = 50;
656 fesettings->step_size = 0;
657 fesettings->max_drift = 0;
661 static void mt312_release(struct dvb_frontend *fe)
663 struct mt312_state *state = fe->demodulator_priv;
667 static struct dvb_frontend_ops vp310_mt312_ops = {
670 .name = "Zarlink ???? DVB-S",
672 .frequency_min = 950000,
673 .frequency_max = 2150000,
674 .frequency_stepsize = (MT312_PLL_CLK / 1000) / 128,
675 .symbol_rate_min = MT312_SYS_CLK / 128,
676 .symbol_rate_max = MT312_SYS_CLK / 2,
678 FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 |
679 FE_CAN_FEC_3_4 | FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 |
680 FE_CAN_FEC_AUTO | FE_CAN_QPSK | FE_CAN_MUTE_TS |
684 .release = mt312_release,
686 .init = mt312_initfe,
687 .sleep = mt312_sleep,
688 .i2c_gate_ctrl = mt312_i2c_gate_ctrl,
690 .set_frontend = mt312_set_frontend,
691 .get_frontend = mt312_get_frontend,
692 .get_tune_settings = mt312_get_tune_settings,
694 .read_status = mt312_read_status,
695 .read_ber = mt312_read_ber,
696 .read_signal_strength = mt312_read_signal_strength,
697 .read_snr = mt312_read_snr,
698 .read_ucblocks = mt312_read_ucblocks,
700 .diseqc_send_master_cmd = mt312_send_master_cmd,
701 .diseqc_send_burst = mt312_send_burst,
702 .set_tone = mt312_set_tone,
703 .set_voltage = mt312_set_voltage,
706 struct dvb_frontend *vp310_mt312_attach(const struct mt312_config *config,
707 struct i2c_adapter *i2c)
709 struct mt312_state *state = NULL;
711 /* allocate memory for the internal state */
712 state = kmalloc(sizeof(struct mt312_state), GFP_KERNEL);
716 /* setup the state */
717 state->config = config;
720 /* check if the demod is there */
721 if (mt312_readreg(state, ID, &state->id) < 0)
724 /* create dvb_frontend */
725 memcpy(&state->frontend.ops, &vp310_mt312_ops,
726 sizeof(struct dvb_frontend_ops));
727 state->frontend.demodulator_priv = state;
731 strcpy(state->frontend.ops.info.name, "Zarlink VP310 DVB-S");
732 state->frequency = 90;
735 strcpy(state->frontend.ops.info.name, "Zarlink MT312 DVB-S");
736 state->frequency = 60;
739 printk(KERN_WARNING "Only Zarlink VP310/MT312"
740 " are supported chips.\n");
744 return &state->frontend;
750 EXPORT_SYMBOL(vp310_mt312_attach);
752 module_param(debug, int, 0644);
753 MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off).");
755 MODULE_DESCRIPTION("Zarlink VP310/MT312 DVB-S Demodulator driver");
756 MODULE_AUTHOR("Andreas Oberritter <obi@linuxtv.org>");
757 MODULE_LICENSE("GPL");