drivers/media/dvb/frontends/stb0899_algo.c

   1 /*
   2         STB0899 Multistandard Frontend driver
   3         Copyright (C) Manu Abraham (abraham.manu@gmail.com)
   4
   5         Copyright (C) ST Microelectronics
   6
   7         This program is free software; you can redistribute it and/or modify
   8         it under the terms of the GNU General Public License as published by
   9         the Free Software Foundation; either version 2 of the License, or
  10         (at your option) any later version.
  11
  12         This program is distributed in the hope that it will be useful,
  13         but WITHOUT ANY WARRANTY; without even the implied warranty of
  14         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15         GNU General Public License for more details.
  16
  17         You should have received a copy of the GNU General Public License
  18         along with this program; if not, write to the Free Software
  19         Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  20 */
  21
  22 #include "stb0899_drv.h"
  23 #include "stb0899_priv.h"
  24 #include "stb0899_reg.h"
  25
  26 /*
  27  * BinaryFloatDiv
  28  * float division with integer
  29  */
  30 static long BinaryFloatDiv(long n1, long n2, int precision)
  31 {
  32         int i = 0;
  33         long result = 0;
  34
  35         while (i <= precision) {
  36                 if (n1 < n2) {
  37                         result *= 2;
  38                         n1 *= 2;
  39                 } else {
  40                         result = result * 2 + 1;
  41                         n1 = (n1 - n2) * 2;
  42                 }
  43                 i++;
  44         }
  45
  46         return result;
  47 }
  48
  49 /*
  50  * stb0899_calc_srate
  51  * Compute symbol rate
  52  */
  53 static u32 stb0899_calc_srate(u32 master_clk, u8 *sfr)
  54 {
  55         u32 tmp, tmp2, mclk;
  56
  57         mclk  =  master_clk / 4096L; /* MasterClock * 10 / 2^20 */
  58         tmp  = (((u32) sfr[0] << 12) + ((u32) sfr[1] << 4)) / 16;
  59
  60         tmp *= mclk;
  61         tmp /= 16;
  62         tmp2 = ((u32) sfr[2] * mclk) / 256;
  63         tmp += tmp2;
  64
  65         return tmp;
  66 }
  67
  68 /*
  69  * stb0899_get_srate
  70  * Get the current symbol rate
  71  */
  72 u32 stb0899_get_srate(struct stb0899_state *state)
  73 {
  74         struct stb0899_internal *internal = &state->internal;
  75         u8 sfr[4];
  76
  77         stb0899_read_regs(state, STB0899_SFRH, sfr, 3);
  78
  79         return stb0899_calc_srate(internal->master_clk, sfr);
  80 }
  81
  82 /*
  83  * stb0899_set_srate
  84  * Set symbol frequency
  85  * MasterClock: master clock frequency (hz)
  86  * SymbolRate: symbol rate (bauds)
  87  * return symbol frequency
  88  */
  89 static u32 stb0899_set_srate(struct stb0899_state *state, u32 master_clk, u32 srate)
  90 {
  91         u32 tmp, tmp_up, srate_up;
  92         u8 sfr_up[3], sfr[3];
  93
  94         srate_up = srate;
  95         dprintk(state->verbose, FE_DEBUG, 1, "-->");
  96         /*
  97          * in order to have the maximum precision, the symbol rate entered into
  98          * the chip is computed as the closest value of the "true value".
  99          * In this purpose, the symbol rate value is rounded (1 is added on the bit
 100          * below the LSB )
 101          */
 102         srate_up += (srate_up * 3) / 100;
 103
 104         tmp = BinaryFloatDiv(srate, master_clk, 20);
 105         tmp_up = BinaryFloatDiv(srate_up, master_clk, 20);
 106
 107         sfr_up[0] = (tmp_up >> 12) & 0xff;
 108         sfr_up[1] = (tmp_up >>  4) & 0xff;
 109         sfr_up[2] =  tmp_up & 0x0f;
 110
 111         sfr[0] = (tmp >> 12) & 0xff;
 112         sfr[1] = (tmp >>  4) & 0xff;
 113         sfr[2] =  tmp & 0x0f;
 114
 115         stb0899_write_regs(state, STB0899_SFRUPH, sfr_up, 3);
 116         stb0899_write_regs(state, STB0899_SFRH, sfr, 3);
 117
 118         return srate;
 119 }
 120
 121 /*
 122  * stb0899_calc_loop_time
 123  * Compute the amount of time needed by the timing loop to lock
 124  * SymbolRate: Symbol rate
 125  * return: timing loop time constant (ms)
 126  */
 127 static long stb0899_calc_loop_time(long srate)
 128 {
 129         if (srate > 0)
 130                 return (100000 / (srate / 1000));
 131         else
 132                 return 0;
 133 }
 134
 135 /*
 136  * stb0899_calc_derot_time
 137  * Compute the amount of time needed by the derotator to lock
 138  * SymbolRate: Symbol rate
 139  * return: derotator time constant (ms)
 140  */
 141 static long stb0899_calc_derot_time(long srate)
 142 {
 143         if (srate > 0)
 144                 return (100000 / (srate / 1000));
 145         else
 146                 return 0;
 147 }
 148
 149 /*
 150  * stb0899_carr_width
 151  * Compute the width of the carrier
 152  * return: width of carrier (kHz or Mhz)
 153  */
 154 long stb0899_carr_width(struct stb0899_state *state)
 155 {
 156         struct stb0899_internal *internal = &state->internal;
 157
 158         return (internal->srate + (internal->srate * internal->rolloff) / 100);
 159 }
 160
 161 /*
 162  * stb0899_first_subrange
 163  * Compute the first subrange of the search
 164  */
 165 static void stb0899_first_subrange(struct stb0899_state *state)
 166 {
 167         struct stb0899_internal *internal       = &state->internal;
 168         struct stb0899_params *params           = &state->params;
 169         struct stb0899_config *config           =  state->config;
 170
 171         int range = 0;
 172         u32 bandwidth = 0;
 173
 174         if (config->tuner_get_bandwidth) {
 175                 config->tuner_get_bandwidth(&state->frontend, &bandwidth);
 176                 range = bandwidth - stb0899_carr_width(state) / 2;
 177         }
 178
 179         if (range > 0)
 180                 internal->sub_range = MIN(internal->srch_range, range);
 181         else
 182                 internal->sub_range = 0;
 183
 184         internal->freq = params->freq;
 185         internal->tuner_offst = 0L;
 186         internal->sub_dir = 1;
 187 }
 188
 189 /*
 190  * stb0899_check_tmg
 191  * check for timing lock
 192  * internal.Ttiming: time to wait for loop lock
 193  */
 194 static enum stb0899_status stb0899_check_tmg(struct stb0899_state *state)
 195 {
 196         struct stb0899_internal *internal = &state->internal;
 197         int lock, timing;
 198         u8 reg;
 199
 200         msleep(internal->t_timing);
 201
 202         reg = stb0899_read_reg(state, STB0899_RTF);
 203         STB0899_SETFIELD_VAL(RTF_TIMING_LOOP_FREQ, reg, 0xf2);
 204         stb0899_write_reg(state, STB0899_RTF, reg);
 205         reg = stb0899_read_reg(state, STB0899_TLIR);
 206         lock = STB0899_GETFIELD(TLIR_TMG_LOCK_IND, reg);
 207         timing = stb0899_read_reg(state, STB0899_RTF);
 208
 209         if (lock >= 42) {
 210                 if ((lock > 48) && (timing >= 110)) {
 211                         internal->status = ANALOGCARRIER;
 212                         dprintk(state->verbose, FE_DEBUG, 1, "-->ANALOG Carrier !");
 213                 } else {
 214                         internal->status = TIMINGOK;
 215                         dprintk(state->verbose, FE_DEBUG, 1, "------->TIMING OK !");
 216                 }
 217         } else {
 218                 internal->status = NOTIMING;
 219                 dprintk(state->verbose, FE_DEBUG, 1, "-->NO TIMING !");
 220         }
 221         return internal->status;
 222 }
 223
 224 /*
 225  * stb0899_search_tmg
 226  * perform a fs/2 zig-zag to find timing
 227  */
 228 static enum stb0899_status stb0899_search_tmg(struct stb0899_state *state)
 229 {
 230         struct stb0899_internal *internal = &state->internal;
 231         struct stb0899_params *params = &state->params;
 232
 233         short int derot_step, derot_freq = 0, derot_limit, next_loop = 3;
 234         int index = 0;
 235         u8 cfr[2];
 236
 237         internal->status = NOTIMING;
 238
 239         /* timing loop computation & symbol rate optimisation   */
 240         derot_limit = (internal->sub_range / 2L) / internal->mclk;
 241         derot_step = (params->srate / 2L) / internal->mclk;
 242
 243         while ((stb0899_check_tmg(state) != TIMINGOK) && next_loop) {
 244                 index++;
 245                 derot_freq += index * internal->direction * derot_step; /* next derot zig zag position  */
 246
 247                 if (ABS(derot_freq) > derot_limit)
 248                         next_loop--;
 249
 250                 if (next_loop) {
 251                         STB0899_SETFIELD_VAL(CFRM, cfr[0], MSB(state->config->inversion * derot_freq));
 252                         STB0899_SETFIELD_VAL(CFRL, cfr[1], LSB(state->config->inversion * derot_freq));
 253                         stb0899_write_regs(state, STB0899_CFRM, cfr, 2); /* derotator frequency         */
 254                 }
 255                 internal->direction = -internal->direction;     /* Change zigzag direction              */
 256         }
 257
 258         if (internal->status == TIMINGOK) {
 259                 stb0899_read_regs(state, STB0899_CFRM, cfr, 2); /* get derotator frequency              */
 260                 internal->derot_freq = state->config->inversion * MAKEWORD16(cfr[0], cfr[1]);
 261                 dprintk(state->verbose, FE_DEBUG, 1, "------->TIMING OK ! Derot Freq = %d", internal->derot_freq);
 262         }
 263
 264         return internal->status;
 265 }
 266
 267 /*
 268  * stb0899_check_carrier
 269  * Check for carrier found
 270  */
 271 static enum stb0899_status stb0899_check_carrier(struct stb0899_state *state)
 272 {
 273         struct stb0899_internal *internal = &state->internal;
 274         u8 reg;
 275
 276         msleep(internal->t_derot); /* wait for derotator ok     */
 277
 278         reg = stb0899_read_reg(state, STB0899_CFD);
 279         STB0899_SETFIELD_VAL(CFD_ON, reg, 1);
 280         stb0899_write_reg(state, STB0899_CFD, reg);
 281
 282         reg = stb0899_read_reg(state, STB0899_DSTATUS);
 283         dprintk(state->verbose, FE_DEBUG, 1, "--------------------> STB0899_DSTATUS=[0x%02x]", reg);
 284         if (STB0899_GETFIELD(CARRIER_FOUND, reg)) {
 285                 internal->status = CARRIEROK;
 286                 dprintk(state->verbose, FE_DEBUG, 1, "-------------> CARRIEROK !");
 287         } else {
 288                 internal->status = NOCARRIER;
 289                 dprintk(state->verbose, FE_DEBUG, 1, "-------------> NOCARRIER !");
 290         }
 291
 292         return internal->status;
 293 }
 294
 295 /*
 296  * stb0899_search_carrier
 297  * Search for a QPSK carrier with the derotator
 298  */
 299 static enum stb0899_status stb0899_search_carrier(struct stb0899_state *state)
 300 {
 301         struct stb0899_internal *internal = &state->internal;
 302
 303         short int derot_freq = 0, last_derot_freq = 0, derot_limit, next_loop = 3;
 304         int index = 0;
 305         u8 cfr[2];
 306         u8 reg;
 307
 308         internal->status = NOCARRIER;
 309         derot_limit = (internal->sub_range / 2L) / internal->mclk;
 310         derot_freq = internal->derot_freq;
 311
 312         reg = stb0899_read_reg(state, STB0899_CFD);
 313         STB0899_SETFIELD_VAL(CFD_ON, reg, 1);
 314         stb0899_write_reg(state, STB0899_CFD, reg);
 315
 316         do {
 317                 dprintk(state->verbose, FE_DEBUG, 1, "Derot Freq=%d, mclk=%d", derot_freq, internal->mclk);
 318                 if (stb0899_check_carrier(state) == NOCARRIER) {
 319                         index++;
 320                         last_derot_freq = derot_freq;
 321                         derot_freq += index * internal->direction * internal->derot_step; /* next zig zag derotator position    */
 322
 323                         if(ABS(derot_freq) > derot_limit)
 324                                 next_loop--;
 325
 326                         if (next_loop) {
 327                                 reg = stb0899_read_reg(state, STB0899_CFD);
 328                                 STB0899_SETFIELD_VAL(CFD_ON, reg, 1);
 329                                 stb0899_write_reg(state, STB0899_CFD, reg);
 330
 331                                 STB0899_SETFIELD_VAL(CFRM, cfr[0], MSB(state->config->inversion * derot_freq));
 332                                 STB0899_SETFIELD_VAL(CFRL, cfr[1], LSB(state->config->inversion * derot_freq));
 333                                 stb0899_write_regs(state, STB0899_CFRM, cfr, 2); /* derotator frequency */
 334                         }
 335                 }
 336
 337                 internal->direction = -internal->direction; /* Change zigzag direction  */
 338         } while ((internal->status != CARRIEROK) && next_loop);
 339
 340         if (internal->status == CARRIEROK) {
 341                 stb0899_read_regs(state, STB0899_CFRM, cfr, 2); /* get derotator frequency      */
 342                 internal->derot_freq = state->config->inversion * MAKEWORD16(cfr[0], cfr[1]);
 343                 dprintk(state->verbose, FE_DEBUG, 1, "----> CARRIER OK !, Derot Freq=%d", internal->derot_freq);
 344         } else {
 345                 internal->derot_freq = last_derot_freq;
 346         }
 347
 348         return internal->status;
 349 }
 350
 351 /*
 352  * stb0899_check_data
 353  * Check for data found
 354  */
 355 static enum stb0899_status stb0899_check_data(struct stb0899_state *state)
 356 {
 357         struct stb0899_internal *internal = &state->internal;
 358         struct stb0899_params *params = &state->params;
 359
 360         int lock = 0, index = 0, dataTime = 500, loop;
 361         u8 reg;
 362
 363         internal->status = NODATA;
 364
 365         /* RESET FEC    */
 366         reg = stb0899_read_reg(state, STB0899_TSTRES);
 367         STB0899_SETFIELD_VAL(FRESACS, reg, 1);
 368         stb0899_write_reg(state, STB0899_TSTRES, reg);
 369         msleep(1);
 370         reg = stb0899_read_reg(state, STB0899_TSTRES);
 371         STB0899_SETFIELD_VAL(FRESACS, reg, 0);
 372         stb0899_write_reg(state, STB0899_TSTRES, reg);
 373
 374         if (params->srate <= 2000000)
 375                 dataTime = 2000;
 376         else if (params->srate <= 5000000)
 377                 dataTime = 1500;
 378         else if (params->srate <= 15000000)
 379                 dataTime = 1000;
 380         else
 381                 dataTime = 500;
 382
 383         stb0899_write_reg(state, STB0899_DSTATUS2, 0x00); /* force search loop  */
 384         while (1) {
 385                 /* WARNING! VIT LOCKED has to be tested before VIT_END_LOOOP    */
 386                 reg = stb0899_read_reg(state, STB0899_VSTATUS);
 387                 lock = STB0899_GETFIELD(VSTATUS_LOCKEDVIT, reg);
 388                 loop = STB0899_GETFIELD(VSTATUS_END_LOOPVIT, reg);
 389
 390                 if (lock || loop || (index > dataTime))
 391                         break;
 392                 index++;
 393         }
 394
 395         if (lock) {     /* DATA LOCK indicator  */
 396                 internal->status = DATAOK;
 397                 dprintk(state->verbose, FE_DEBUG, 1, "-----------------> DATA OK !");
 398         }
 399
 400         return internal->status;
 401 }
 402
 403 /*
 404  * stb0899_search_data
 405  * Search for a QPSK carrier with the derotator
 406  */
 407 static enum stb0899_status stb0899_search_data(struct stb0899_state *state)
 408 {
 409         short int derot_freq, derot_step, derot_limit, next_loop = 3;
 410         u8 cfr[2];
 411         u8 reg;
 412         int index = 1;
 413
 414         struct stb0899_internal *internal = &state->internal;
 415         struct stb0899_params *params = &state->params;
 416
 417         derot_step = (params->srate / 4L) / internal->mclk;
 418         derot_limit = (internal->sub_range / 2L) / internal->mclk;
 419         derot_freq = internal->derot_freq;
 420
 421         do {
 422                 if ((internal->status != CARRIEROK) || (stb0899_check_data(state) != DATAOK)) {
 423
 424                         derot_freq += index * internal->direction * derot_step; /* next zig zag derotator position      */
 425                         if (ABS(derot_freq) > derot_limit)
 426                                 next_loop--;
 427
 428                         if (next_loop) {
 429                                 dprintk(state->verbose, FE_DEBUG, 1, "Derot freq=%d, mclk=%d", derot_freq, internal->mclk);
 430                                 reg = stb0899_read_reg(state, STB0899_CFD);
 431                                 STB0899_SETFIELD_VAL(CFD_ON, reg, 1);
 432                                 stb0899_write_reg(state, STB0899_CFD, reg);
 433
 434                                 STB0899_SETFIELD_VAL(CFRM, cfr[0], MSB(state->config->inversion * derot_freq));
 435                                 STB0899_SETFIELD_VAL(CFRL, cfr[1], LSB(state->config->inversion * derot_freq));
 436                                 stb0899_write_regs(state, STB0899_CFRM, cfr, 2); /* derotator frequency */
 437
 438                                 stb0899_check_carrier(state);
 439                                 index++;
 440                         }
 441                 }
 442                 internal->direction = -internal->direction; /* change zig zag direction         */
 443         } while ((internal->status != DATAOK) && next_loop);
 444
 445         if (internal->status == DATAOK) {
 446                 stb0899_read_regs(state, STB0899_CFRM, cfr, 2); /* get derotator frequency      */
 447                 internal->derot_freq = state->config->inversion * MAKEWORD16(cfr[0], cfr[1]);
 448                 dprintk(state->verbose, FE_DEBUG, 1, "------> DATAOK ! Derot Freq=%d", internal->derot_freq);
 449         }
 450
 451         return internal->status;
 452 }
 453
 454 /*
 455  * stb0899_check_range
 456  * check if the found frequency is in the correct range
 457  */
 458 static enum stb0899_status stb0899_check_range(struct stb0899_state *state)
 459 {
 460         struct stb0899_internal *internal = &state->internal;
 461         struct stb0899_params *params = &state->params;
 462
 463         int range_offst, tp_freq;
 464
 465         range_offst = internal->srch_range / 2000;
 466         tp_freq = internal->freq + (internal->derot_freq * internal->mclk) / 1000;
 467
 468         if ((tp_freq >= params->freq - range_offst) && (tp_freq <= params->freq + range_offst)) {
 469                 internal->status = RANGEOK;
 470                 dprintk(state->verbose, FE_DEBUG, 1, "----> RANGEOK !");
 471         } else {
 472                 internal->status = OUTOFRANGE;
 473                 dprintk(state->verbose, FE_DEBUG, 1, "----> OUT OF RANGE !");
 474         }
 475
 476         return internal->status;
 477 }
 478
 479 /*
 480  * NextSubRange
 481  * Compute the next subrange of the search
 482  */
 483 static void next_sub_range(struct stb0899_state *state)
 484 {
 485         struct stb0899_internal *internal = &state->internal;
 486         struct stb0899_params *params = &state->params;
 487
 488         long old_sub_range;
 489
 490         if (internal->sub_dir > 0) {
 491                 old_sub_range = internal->sub_range;
 492                 internal->sub_range = MIN((internal->srch_range / 2) -
 493                                           (internal->tuner_offst + internal->sub_range / 2),
 494                                            internal->sub_range);
 495
 496                 if (internal->sub_range < 0)
 497                         internal->sub_range = 0;
 498
 499                 internal->tuner_offst += (old_sub_range + internal->sub_range) / 2;
 500         }
 501
 502         internal->freq = params->freq + (internal->sub_dir * internal->tuner_offst) / 1000;
 503         internal->sub_dir = -internal->sub_dir;
 504 }
 505
 506 /*
 507  * stb0899_dvbs_algo
 508  * Search for a signal, timing, carrier and data for a
 509  * given frequency in a given range
 510  */
 511 enum stb0899_status stb0899_dvbs_algo(struct stb0899_state *state)
 512 {
 513         struct stb0899_params *params           = &state->params;
 514         struct stb0899_internal *internal       = &state->internal;
 515         struct stb0899_config *config           = state->config;
 516
 517         u8 bclc, reg;
 518         u8 cfr[1];
 519         u8 eq_const[10];
 520         s32 clnI = 3;
 521         u32 bandwidth = 0;
 522
 523         /* BETA values rated @ 99MHz    */
 524         s32 betaTab[5][4] = {
 525                /*  5   10   20   30MBps */
 526                 { 37,  34,  32,  31 }, /* QPSK 1/2      */
 527                 { 37,  35,  33,  31 }, /* QPSK 2/3      */
 528                 { 37,  35,  33,  31 }, /* QPSK 3/4      */
 529                 { 37,  36,  33,  32 }, /* QPSK 5/6      */
 530                 { 37,  36,  33,  32 }  /* QPSK 7/8      */
 531         };
 532
 533         internal->direction = 1;
 534
 535         stb0899_set_srate(state, internal->master_clk, params->srate);
 536         /* Carrier loop optimization versus symbol rate for acquisition*/
 537         if (params->srate <= 5000000) {
 538                 stb0899_write_reg(state, STB0899_ACLC, 0x89);
 539                 bclc = stb0899_read_reg(state, STB0899_BCLC);
 540                 STB0899_SETFIELD_VAL(BETA, bclc, 0x1c);
 541                 stb0899_write_reg(state, STB0899_BCLC, bclc);
 542                 clnI = 0;
 543         } else if (params->srate <= 15000000) {
 544                 stb0899_write_reg(state, STB0899_ACLC, 0xc9);
 545                 bclc = stb0899_read_reg(state, STB0899_BCLC);
 546                 STB0899_SETFIELD_VAL(BETA, bclc, 0x22);
 547                 stb0899_write_reg(state, STB0899_BCLC, bclc);
 548                 clnI = 1;
 549         } else if(params->srate <= 25000000) {
 550                 stb0899_write_reg(state, STB0899_ACLC, 0x89);
 551                 bclc = stb0899_read_reg(state, STB0899_BCLC);
 552                 STB0899_SETFIELD_VAL(BETA, bclc, 0x27);
 553                 stb0899_write_reg(state, STB0899_BCLC, bclc);
 554                 clnI = 2;
 555         } else {
 556                 stb0899_write_reg(state, STB0899_ACLC, 0xc8);
 557                 bclc = stb0899_read_reg(state, STB0899_BCLC);
 558                 STB0899_SETFIELD_VAL(BETA, bclc, 0x29);
 559                 stb0899_write_reg(state, STB0899_BCLC, bclc);
 560                 clnI = 3;
 561         }
 562
 563         dprintk(state->verbose, FE_DEBUG, 1, "Set the timing loop to acquisition");
 564         /* Set the timing loop to acquisition   */
 565         stb0899_write_reg(state, STB0899_RTC, 0x46);
 566         stb0899_write_reg(state, STB0899_CFD, 0xee);
 567
 568         /* !! WARNING !!
 569          * Do not read any status variables while acquisition,
 570          * If any needed, read before the acquisition starts
 571          * querying status while acquiring causes the
 572          * acquisition to go bad and hence no locks.
 573          */
 574         dprintk(state->verbose, FE_DEBUG, 1, "Derot Percent=%d Srate=%d mclk=%d",
 575                 internal->derot_percent, params->srate, internal->mclk);
 576
 577         /* Initial calculations */
 578         internal->derot_step = internal->derot_percent * (params->srate / 1000L) / internal->mclk; /* DerotStep/1000 * Fsymbol  */
 579         internal->t_timing = stb0899_calc_loop_time(params->srate);
 580         internal->t_derot = stb0899_calc_derot_time(params->srate);
 581         internal->t_data = 500;
 582
 583         dprintk(state->verbose, FE_DEBUG, 1, "RESET stream merger");
 584         /* RESET Stream merger  */
 585         reg = stb0899_read_reg(state, STB0899_TSTRES);
 586         STB0899_SETFIELD_VAL(FRESRS, reg, 1);
 587         stb0899_write_reg(state, STB0899_TSTRES, reg);
 588
 589         /*
 590          * Set KDIVIDER to an intermediate value between
 591          * 1/2 and 7/8 for acquisition
 592          */
 593         reg = stb0899_read_reg(state, STB0899_DEMAPVIT);
 594         STB0899_SETFIELD_VAL(DEMAPVIT_KDIVIDER, reg, 60);
 595         stb0899_write_reg(state, STB0899_DEMAPVIT, reg);
 596
 597         stb0899_write_reg(state, STB0899_EQON, 0x01); /* Equalizer OFF while acquiring  */
 598         stb0899_write_reg(state, STB0899_VITSYNC, 0x19);
 599
 600         stb0899_first_subrange(state);
 601         do {
 602                 /* Initialisations      */
 603                 cfr[0] = cfr[1] = 0;
 604                 stb0899_write_regs(state, STB0899_CFRM, cfr, 2); /* RESET derotator frequency   */
 605
 606                 reg = stb0899_read_reg(state, STB0899_RTF);
 607                 STB0899_SETFIELD_VAL(RTF_TIMING_LOOP_FREQ, reg, 0);
 608                 stb0899_write_reg(state, STB0899_RTF, reg);
 609                 reg = stb0899_read_reg(state, STB0899_CFD);
 610                 STB0899_SETFIELD_VAL(CFD_ON, reg, 1);
 611                 stb0899_write_reg(state, STB0899_CFD, reg);
 612
 613                 internal->derot_freq = 0;
 614                 internal->status = NOAGC1;
 615
 616                 /* Move tuner to frequency      */
 617                 dprintk(state->verbose, FE_DEBUG, 1, "Tuner set frequency");
 618                 if (state->config->tuner_set_frequency)
 619                         state->config->tuner_set_frequency(&state->frontend, internal->freq);
 620
 621                 msleep(100);
 622
 623                 if (state->config->tuner_get_frequency)
 624                         state->config->tuner_get_frequency(&state->frontend, &internal->freq);
 625
 626                 msleep(internal->t_agc1 + internal->t_agc2 + internal->t_timing); /* AGC1, AGC2 and timing loop */
 627                 dprintk(state->verbose, FE_DEBUG, 1, "current derot freq=%d", internal->derot_freq);
 628                 internal->status = AGC1OK;
 629
 630                 /* There is signal in the band  */
 631                 if (config->tuner_get_bandwidth)
 632                         config->tuner_get_bandwidth(&state->frontend, &bandwidth);
 633                 if (params->srate <= bandwidth / 2)
 634                         stb0899_search_tmg(state); /* For low rates (SCPC)      */
 635                 else
 636                         stb0899_check_tmg(state); /* For high rates (MCPC)      */
 637
 638                 if (internal->status == TIMINGOK) {
 639                         dprintk(state->verbose, FE_DEBUG, 1,
 640                                 "TIMING OK ! Derot freq=%d, mclk=%d",
 641                                 internal->derot_freq, internal->mclk);
 642
 643                         if (stb0899_search_carrier(state) == CARRIEROK) {       /* Search for carrier   */
 644                                 dprintk(state->verbose, FE_DEBUG, 1,
 645                                         "CARRIER OK ! Derot freq=%d, mclk=%d",
 646                                         internal->derot_freq, internal->mclk);
 647
 648                                 if (stb0899_search_data(state) == DATAOK) {     /* Check for data       */
 649                                         dprintk(state->verbose, FE_DEBUG, 1,
 650                                                 "DATA OK ! Derot freq=%d, mclk=%d",
 651                                                 internal->derot_freq, internal->mclk);
 652
 653                                         if (stb0899_check_range(state) == RANGEOK) {
 654                                                 dprintk(state->verbose, FE_DEBUG, 1,
 655                                                         "RANGE OK ! derot freq=%d, mclk=%d",
 656                                                         internal->derot_freq, internal->mclk);
 657
 658                                                 internal->freq = params->freq + ((internal->derot_freq * internal->mclk) / 1000);
 659                                                 reg = stb0899_read_reg(state, STB0899_PLPARM);
 660                                                 internal->fecrate = STB0899_GETFIELD(VITCURPUN, reg);
 661                                                 dprintk(state->verbose, FE_DEBUG, 1,
 662                                                         "freq=%d, internal resultant freq=%d",
 663                                                         params->freq, internal->freq);
 664
 665                                                 dprintk(state->verbose, FE_DEBUG, 1,
 666                                                         "internal puncture rate=%d",
 667                                                         internal->fecrate);
 668                                         }
 669                                 }
 670                         }
 671                 }
 672                 if (internal->status != RANGEOK)
 673                         next_sub_range(state);
 674
 675         } while (internal->sub_range && internal->status != RANGEOK);
 676
 677         /* Set the timing loop to tracking      */
 678         stb0899_write_reg(state, STB0899_RTC, 0x33);
 679         stb0899_write_reg(state, STB0899_CFD, 0xf7);
 680         reg = 0;
 681         /* if locked and range ok, set Kdiv     */
 682         if (internal->status == RANGEOK) {
 683                 dprintk(state->verbose, FE_DEBUG, 1, "Locked & Range OK !");
 684                 stb0899_write_reg(state, STB0899_EQON, 0x41);           /* Equalizer OFF while acquiring        */
 685                 stb0899_write_reg(state, STB0899_VITSYNC, 0x39);        /* SN to b'11 for acquisition           */
 686
 687                 /*
 688                  * Carrier loop optimization versus
 689                  * symbol Rate/Puncture Rate for Tracking
 690                  */
 691                 switch (internal->fecrate) {
 692                 case STB0899_FEC_1_2:           /* 13   */
 693                         STB0899_SETFIELD_VAL(DEMAPVIT_KDIVIDER, reg, 0x1a);
 694                         stb0899_write_reg(state, STB0899_DEMAPVIT, reg);
 695                         reg = 0;
 696                         STB0899_SETFIELD_VAL(BETA, reg, betaTab[0][clnI]);
 697                         stb0899_write_reg(state, STB0899_BCLC, reg);
 698                         break;
 699                 case STB0899_FEC_2_3:           /* 18   */
 700                         STB0899_SETFIELD_VAL(DEMAPVIT_KDIVIDER, reg, 44);
 701                         stb0899_write_reg(state, STB0899_DEMAPVIT, reg);
 702                         reg = 0;
 703                         STB0899_SETFIELD_VAL(BETA, reg, betaTab[1][clnI]);
 704                         stb0899_write_reg(state, STB0899_BCLC, reg);
 705                         break;
 706                 case STB0899_FEC_3_4:           /* 21   */
 707                         STB0899_SETFIELD_VAL(DEMAPVIT_KDIVIDER, reg, 60);
 708                         stb0899_write_reg(state, STB0899_DEMAPVIT, reg);
 709                         reg = 0;
 710                         STB0899_SETFIELD_VAL(BETA, reg, betaTab[2][clnI]);
 711                         stb0899_write_reg(state, STB0899_BCLC, reg);
 712                         break;
 713                 case STB0899_FEC_5_6:           /* 24   */
 714                         STB0899_SETFIELD_VAL(DEMAPVIT_KDIVIDER, reg, 75);
 715                         stb0899_write_reg(state, STB0899_DEMAPVIT, reg);
 716                         reg = 0;
 717                         STB0899_SETFIELD_VAL(BETA, reg, betaTab[3][clnI]);
 718                         stb0899_write_reg(state, STB0899_BCLC, reg);
 719                         break;
 720                 case STB0899_FEC_6_7:           /* 25   */
 721                         STB0899_SETFIELD_VAL(DEMAPVIT_KDIVIDER, reg, 88);
 722                         stb0899_write_reg(state, STB0899_DEMAPVIT, reg);
 723                         stb0899_write_reg(state, STB0899_ACLC, 0x88);
 724                         stb0899_write_reg(state, STB0899_BCLC, 0x9a);
 725                         break;
 726                 case STB0899_FEC_7_8:           /* 26   */
 727                         STB0899_SETFIELD_VAL(DEMAPVIT_KDIVIDER, reg, 94);
 728                         stb0899_write_reg(state, STB0899_DEMAPVIT, reg);
 729                         reg = 0;
 730                         STB0899_SETFIELD_VAL(BETA, reg, betaTab[4][clnI]);
 731                         stb0899_write_reg(state, STB0899_BCLC, reg);
 732                         break;
 733                 default:
 734                         dprintk(state->verbose, FE_DEBUG, 1, "Unsupported Puncture Rate");
 735                         break;
 736                 }
 737                 /* release stream merger RESET  */
 738                 reg = stb0899_read_reg(state, STB0899_TSTRES);
 739                 STB0899_SETFIELD_VAL(FRESRS, reg, 0);
 740                 stb0899_write_reg(state, STB0899_TSTRES, reg);
 741
 742                 /* disable carrier detector     */
 743                 reg = stb0899_read_reg(state, STB0899_CFD);
 744                 STB0899_SETFIELD_VAL(CFD_ON, reg, 0);
 745                 stb0899_write_reg(state, STB0899_CFD, reg);
 746
 747                 stb0899_read_regs(state, STB0899_EQUAI1, eq_const, 10);
 748         }
 749
 750         return internal->status;
 751 }
 752
 753 /*
 754  * stb0899_dvbs2_config_uwp
 755  * Configure UWP state machine
 756  */
 757 static void stb0899_dvbs2_config_uwp(struct stb0899_state *state)
 758 {
 759         struct stb0899_internal *internal = &state->internal;
 760         struct stb0899_config *config = state->config;
 761         u32 uwp1, uwp2, uwp3, reg;
 762
 763         uwp1 = STB0899_READ_S2REG(STB0899_S2DEMOD, UWP_CNTRL1);
 764         uwp2 = STB0899_READ_S2REG(STB0899_S2DEMOD, UWP_CNTRL2);
 765         uwp3 = STB0899_READ_S2REG(STB0899_S2DEMOD, UWP_CNTRL3);
 766
 767         STB0899_SETFIELD_VAL(UWP_ESN0_AVE, uwp1, config->esno_ave);
 768         STB0899_SETFIELD_VAL(UWP_ESN0_QUANT, uwp1, config->esno_quant);
 769         STB0899_SETFIELD_VAL(UWP_TH_SOF, uwp1, config->uwp_threshold_sof);
 770
 771         STB0899_SETFIELD_VAL(FE_COARSE_TRK, uwp2, internal->av_frame_coarse);
 772         STB0899_SETFIELD_VAL(FE_FINE_TRK, uwp2, internal->av_frame_fine);
 773         STB0899_SETFIELD_VAL(UWP_MISS_TH, uwp2, config->miss_threshold);
 774
 775         STB0899_SETFIELD_VAL(UWP_TH_ACQ, uwp3, config->uwp_threshold_acq);
 776         STB0899_SETFIELD_VAL(UWP_TH_TRACK, uwp3, config->uwp_threshold_track);
 777
 778         stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_UWP_CNTRL1, STB0899_OFF0_UWP_CNTRL1, uwp1);
 779         stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_UWP_CNTRL2, STB0899_OFF0_UWP_CNTRL2, uwp2);
 780         stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_UWP_CNTRL3, STB0899_OFF0_UWP_CNTRL3, uwp3);
 781
 782         reg = STB0899_READ_S2REG(STB0899_S2DEMOD, SOF_SRCH_TO);
 783         STB0899_SETFIELD_VAL(SOF_SEARCH_TIMEOUT, reg, config->sof_search_timeout);
 784         stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_SOF_SRCH_TO, STB0899_OFF0_SOF_SRCH_TO, reg);
 785 }
 786
 787 /*
 788  * stb0899_dvbs2_config_csm_auto
 789  * Set CSM to AUTO mode
 790  */
 791 static void stb0899_dvbs2_config_csm_auto(struct stb0899_state *state)
 792 {
 793         u32 reg;
 794
 795         reg = STB0899_READ_S2REG(STB0899_S2DEMOD, CSM_CNTRL1);
 796         STB0899_SETFIELD_VAL(CSM_AUTO_PARAM, reg, 1);
 797         stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CSM_CNTRL1, STB0899_OFF0_CSM_CNTRL1, reg);
 798 }
 799
 800 long Log2Int(int number)
 801 {
 802         int i;
 803
 804         i = 0;
 805         while ((1 << i) <= ABS(number))
 806                 i++;
 807
 808         if (number == 0)
 809                 i = 1;
 810
 811         return i - 1;
 812 }
 813
 814 /*
 815  * stb0899_dvbs2_calc_srate
 816  * compute BTR_NOM_FREQ for the symbol rate
 817  */
 818 static u32 stb0899_dvbs2_calc_srate(struct stb0899_state *state)
 819 {
 820         struct stb0899_internal *internal       = &state->internal;
 821         struct stb0899_config *config           = state->config;
 822
 823         u32 dec_ratio, dec_rate, decim, remain, intval, btr_nom_freq;
 824         u32 master_clk, srate;
 825
 826         dec_ratio = (internal->master_clk * 2) / (5 * internal->srate);
 827         dec_ratio = (dec_ratio == 0) ? 1 : dec_ratio;
 828         dec_rate = Log2Int(dec_ratio);
 829         decim = 1 << dec_rate;
 830         master_clk = internal->master_clk / 1000;
 831         srate = internal->srate / 1000;
 832
 833         if (decim <= 4) {
 834                 intval = (decim * (1 << (config->btr_nco_bits - 1))) / master_clk;
 835                 remain = (decim * (1 << (config->btr_nco_bits - 1))) % master_clk;
 836         } else {
 837                 intval = (1 << (config->btr_nco_bits - 1)) / (master_clk / 100) * decim / 100;
 838                 remain = (decim * (1 << (config->btr_nco_bits - 1))) % master_clk;
 839         }
 840         btr_nom_freq = (intval * srate) + ((remain * srate) / master_clk);
 841
 842         return btr_nom_freq;
 843 }
 844
 845 /*
 846  * stb0899_dvbs2_calc_dev
 847  * compute the correction to be applied to symbol rate
 848  */
 849 static u32 stb0899_dvbs2_calc_dev(struct stb0899_state *state)
 850 {
 851         struct stb0899_internal *internal = &state->internal;
 852         u32 dec_ratio, correction, master_clk, srate;
 853
 854         dec_ratio = (internal->master_clk * 2) / (5 * internal->srate);
 855         dec_ratio = (dec_ratio == 0) ? 1 : dec_ratio;
 856
 857         master_clk = internal->master_clk / 1000;       /* for integer Caculation*/
 858         srate = internal->srate / 1000; /* for integer Caculation*/
 859         correction = (512 * master_clk) / (2 * dec_ratio * srate);
 860
 861         return  correction;
 862 }
 863
 864 /*
 865  * stb0899_dvbs2_set_srate
 866  * Set DVBS2 symbol rate
 867  */
 868 static void stb0899_dvbs2_set_srate(struct stb0899_state *state)
 869 {
 870         struct stb0899_internal *internal = &state->internal;
 871
 872         u32 dec_ratio, dec_rate, win_sel, decim, f_sym, btr_nom_freq;
 873         u32 correction, freq_adj, band_lim, decim_cntrl, reg;
 874         u8 anti_alias;
 875
 876         /*set decimation to 1*/
 877         dec_ratio = (internal->master_clk * 2) / (5 * internal->srate);
 878         dec_ratio = (dec_ratio == 0) ? 1 : dec_ratio;
 879         dec_rate = Log2Int(dec_ratio);
 880
 881         win_sel = 0;
 882         if (dec_rate >= 5)
 883                 win_sel = dec_rate - 4;
 884
 885         decim = (1 << dec_rate);
 886         /* (FSamp/Fsymbol *100) for integer Caculation */
 887         f_sym = internal->master_clk / ((decim * internal->srate) / 1000);
 888
 889         if (f_sym <= 2250)      /* don't band limit signal going into btr block*/
 890                 band_lim = 1;
 891         else
 892                 band_lim = 0;   /* band limit signal going into btr block*/
 893
 894         decim_cntrl = ((win_sel << 3) & 0x18) + ((band_lim << 5) & 0x20) + (dec_rate & 0x7);
 895         stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_DECIM_CNTRL, STB0899_OFF0_DECIM_CNTRL, decim_cntrl);
 896
 897         if (f_sym <= 3450)
 898                 anti_alias = 0;
 899         else if (f_sym <= 4250)
 900                 anti_alias = 1;
 901         else
 902                 anti_alias = 2;
 903
 904         stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_ANTI_ALIAS_SEL, STB0899_OFF0_ANTI_ALIAS_SEL, anti_alias);
 905         btr_nom_freq = stb0899_dvbs2_calc_srate(state);
 906         stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_BTR_NOM_FREQ, STB0899_OFF0_BTR_NOM_FREQ, btr_nom_freq);
 907
 908         correction = stb0899_dvbs2_calc_dev(state);
 909         reg = STB0899_READ_S2REG(STB0899_S2DEMOD, BTR_CNTRL);
 910         STB0899_SETFIELD_VAL(BTR_FREQ_CORR, reg, correction);
 911         stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_BTR_CNTRL, STB0899_OFF0_BTR_CNTRL, reg);
 912
 913         /* scale UWP+CSM frequency to sample rate*/
 914         freq_adj =  internal->srate / (internal->master_clk / 4096);
 915         stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_FREQ_ADJ_SCALE, STB0899_OFF0_FREQ_ADJ_SCALE, freq_adj);
 916 }
 917
 918 /*
 919  * stb0899_dvbs2_set_btr_loopbw
 920  * set bit timing loop bandwidth as a percentage of the symbol rate
 921  */
 922 static void stb0899_dvbs2_set_btr_loopbw(struct stb0899_state *state)
 923 {
 924         struct stb0899_internal *internal       = &state->internal;
 925         struct stb0899_config *config           = state->config;
 926
 927         u32 sym_peak = 23, zeta = 707, loopbw_percent = 60;
 928         s32 dec_ratio, dec_rate, k_btr1_rshft, k_btr1, k_btr0_rshft;
 929         s32 k_btr0, k_btr2_rshft, k_direct_shift, k_indirect_shift;
 930         u32 decim, K, wn, k_direct, k_indirect;
 931         u32 reg;
 932
 933         dec_ratio = (internal->master_clk * 2) / (5 * internal->srate);
 934         dec_ratio = (dec_ratio == 0) ? 1 : dec_ratio;
 935         dec_rate = Log2Int(dec_ratio);
 936         decim = (1 << dec_rate);
 937
 938         sym_peak *= 576000;
 939         K = (1 << config->btr_nco_bits) / (internal->master_clk / 1000);
 940         K *= (internal->srate / 1000000) * decim; /*k=k 10^-8*/
 941
 942         if (K != 0) {
 943                 K = sym_peak / K;
 944                 wn = (4 * zeta * zeta) + 1000000;
 945                 wn = (2 * (loopbw_percent * 1000) * 40 * zeta) /wn;  /*wn =wn 10^-8*/
 946
 947                 k_indirect = (wn * wn) / K;
 948                 k_indirect = k_indirect;          /*kindirect = kindirect 10^-6*/
 949                 k_direct   = (2 * wn * zeta) / K;       /*kDirect = kDirect 10^-2*/
 950                 k_direct  *= 100;
 951
 952                 k_direct_shift = Log2Int(k_direct) - Log2Int(10000) - 2;
 953                 k_btr1_rshft = (-1 * k_direct_shift) + config->btr_gain_shift_offset;
 954                 k_btr1 = k_direct / (1 << k_direct_shift);
 955                 k_btr1 /= 10000;
 956
 957                 k_indirect_shift = Log2Int(k_indirect + 15) - 20 /*- 2*/;
 958                 k_btr0_rshft = (-1 * k_indirect_shift) + config->btr_gain_shift_offset;
 959                 k_btr0 = k_indirect * (1 << (-k_indirect_shift));
 960                 k_btr0 /= 1000000;
 961
 962                 k_btr2_rshft = 0;
 963                 if (k_btr0_rshft > 15) {
 964                         k_btr2_rshft = k_btr0_rshft - 15;
 965                         k_btr0_rshft = 15;
 966                 }
 967                 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, BTR_LOOP_GAIN);
 968                 STB0899_SETFIELD_VAL(KBTR0_RSHFT, reg, k_btr0_rshft);
 969                 STB0899_SETFIELD_VAL(KBTR0, reg, k_btr0);
 970                 STB0899_SETFIELD_VAL(KBTR1_RSHFT, reg, k_btr1_rshft);
 971                 STB0899_SETFIELD_VAL(KBTR1, reg, k_btr1);
 972                 STB0899_SETFIELD_VAL(KBTR2_RSHFT, reg, k_btr2_rshft);
 973                 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_BTR_LOOP_GAIN, STB0899_OFF0_BTR_LOOP_GAIN, reg);
 974         } else
 975                 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_BTR_LOOP_GAIN, STB0899_OFF0_BTR_LOOP_GAIN, 0xc4c4f);
 976 }
 977
 978 /*
 979  * stb0899_dvbs2_set_carr_freq
 980  * set nominal frequency for carrier search
 981  */
 982 static void stb0899_dvbs2_set_carr_freq(struct stb0899_state *state, s32 carr_freq, u32 master_clk)
 983 {
 984         struct stb0899_config *config = state->config;
 985         s32 crl_nom_freq;
 986         u32 reg;
 987
 988         crl_nom_freq = (1 << config->crl_nco_bits) / master_clk;
 989         crl_nom_freq *= carr_freq;
 990         reg = STB0899_READ_S2REG(STB0899_S2DEMOD, CRL_NOM_FREQ);
 991         STB0899_SETFIELD_VAL(CRL_NOM_FREQ, reg, crl_nom_freq);
 992         stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CRL_NOM_FREQ, STB0899_OFF0_CRL_NOM_FREQ, reg);
 993 }
 994
 995 /*
 996  * stb0899_dvbs2_init_calc
 997  * Initialize DVBS2 UWP, CSM, carrier and timing loops
 998  */
 999 static void stb0899_dvbs2_init_calc(struct stb0899_state *state)
1000 {
1001         struct stb0899_internal *internal = &state->internal;
1002         s32 steps, step_size;
1003         u32 range, reg;
1004
1005         /* config uwp and csm */
1006         stb0899_dvbs2_config_uwp(state);
1007         stb0899_dvbs2_config_csm_auto(state);
1008
1009         /* initialize BTR       */
1010         stb0899_dvbs2_set_srate(state);
1011         stb0899_dvbs2_set_btr_loopbw(state);
1012
1013         if (internal->srate / 1000000 >= 15)
1014                 step_size = (1 << 17) / 5;
1015         else if (internal->srate / 1000000 >= 10)
1016                 step_size = (1 << 17) / 7;
1017         else if (internal->srate / 1000000 >= 5)
1018                 step_size = (1 << 17) / 10;
1019         else
1020                 step_size = (1 << 17) / 4;
1021
1022         range = internal->srch_range / 1000000;
1023         steps = (10 * range * (1 << 17)) / (step_size * (internal->srate / 1000000));
1024         steps = (steps + 6) / 10;
1025         steps = (steps == 0) ? 1 : steps;
1026         if (steps % 2 == 0)
1027                 stb0899_dvbs2_set_carr_freq(state, internal->center_freq -
1028                                            (internal->step_size * (internal->srate / 20000000)),
1029                                            (internal->master_clk) / 1000000);
1030         else
1031                 stb0899_dvbs2_set_carr_freq(state, internal->center_freq, (internal->master_clk) / 1000000);
1032
1033         /*Set Carrier Search params (zigzag, num steps and freq step size*/
1034         reg = STB0899_READ_S2REG(STB0899_S2DEMOD, ACQ_CNTRL2);
1035         STB0899_SETFIELD_VAL(ZIGZAG, reg, 1);
1036         STB0899_SETFIELD_VAL(NUM_STEPS, reg, steps);
1037         STB0899_SETFIELD_VAL(FREQ_STEPSIZE, reg, step_size);
1038         stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_ACQ_CNTRL2, STB0899_OFF0_ACQ_CNTRL2, reg);
1039 }
1040
1041 /*
1042  * stb0899_dvbs2_btr_init
1043  * initialize the timing loop
1044  */
1045 static void stb0899_dvbs2_btr_init(struct stb0899_state *state)
1046 {
1047         u32 reg;
1048
1049         /* set enable BTR loopback      */
1050         reg = STB0899_READ_S2REG(STB0899_S2DEMOD, BTR_CNTRL);
1051         STB0899_SETFIELD_VAL(INTRP_PHS_SENSE, reg, 1);
1052         STB0899_SETFIELD_VAL(BTR_ERR_ENA, reg, 1);
1053         stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_BTR_CNTRL, STB0899_OFF0_BTR_CNTRL, reg);
1054
1055         /* fix btr freq accum at 0      */
1056         stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_BTR_FREQ_INIT, STB0899_OFF0_BTR_FREQ_INIT, 0x10000000);
1057         stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_BTR_FREQ_INIT, STB0899_OFF0_BTR_FREQ_INIT, 0x00000000);
1058
1059         /* fix btr freq accum at 0      */
1060         stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_BTR_PHS_INIT, STB0899_OFF0_BTR_PHS_INIT, 0x10000000);
1061         stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_BTR_PHS_INIT, STB0899_OFF0_BTR_PHS_INIT, 0x00000000);
1062 }
1063
1064 /*
1065  * stb0899_dvbs2_reacquire
1066  * trigger a DVB-S2 acquisition
1067  */
1068 static void stb0899_dvbs2_reacquire(struct stb0899_state *state)
1069 {
1070         u32 reg = 0;
1071
1072         /* demod soft reset     */
1073         STB0899_SETFIELD_VAL(DVBS2_RESET, reg, 1);
1074         stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_RESET_CNTRL, STB0899_OFF0_RESET_CNTRL, reg);
1075
1076         /*Reset Timing Loop     */
1077         stb0899_dvbs2_btr_init(state);
1078
1079         /* reset Carrier loop   */
1080         stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CRL_FREQ_INIT, STB0899_OFF0_CRL_FREQ_INIT, (1 << 30));
1081         stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CRL_FREQ_INIT, STB0899_OFF0_CRL_FREQ_INIT, 0);
1082         stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CRL_LOOP_GAIN, STB0899_OFF0_CRL_LOOP_GAIN, 0);
1083         stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CRL_PHS_INIT, STB0899_OFF0_CRL_PHS_INIT, (1 << 30));
1084         stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CRL_PHS_INIT, STB0899_OFF0_CRL_PHS_INIT, 0);
1085
1086         /*release demod soft reset      */
1087         reg = 0;
1088         STB0899_SETFIELD_VAL(DVBS2_RESET, reg, 0);
1089         stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_RESET_CNTRL, STB0899_OFF0_RESET_CNTRL, reg);
1090
1091         /* start acquisition process    */
1092         stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_ACQUIRE_TRIG, STB0899_OFF0_ACQUIRE_TRIG, 1);
1093         stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_LOCK_LOST, STB0899_OFF0_LOCK_LOST, 0);
1094
1095         /* equalizer Init       */
1096         stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_EQUALIZER_INIT, STB0899_OFF0_EQUALIZER_INIT, 1);
1097
1098         /*Start equilizer       */
1099         stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_EQUALIZER_INIT, STB0899_OFF0_EQUALIZER_INIT, 0);
1100
1101         reg = STB0899_READ_S2REG(STB0899_S2DEMOD, EQ_CNTRL);
1102         STB0899_SETFIELD_VAL(EQ_SHIFT, reg, 0);
1103         STB0899_SETFIELD_VAL(EQ_DISABLE_UPDATE, reg, 0);
1104         STB0899_SETFIELD_VAL(EQ_DELAY, reg, 0x05);
1105         STB0899_SETFIELD_VAL(EQ_ADAPT_MODE, reg, 0x01);
1106         stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_EQ_CNTRL, STB0899_OFF0_EQ_CNTRL, reg);
1107
1108         /* RESET Packet delineator      */
1109         stb0899_write_reg(state, STB0899_PDELCTRL, 0x4a);
1110 }
1111
1112 /*
1113  * stb0899_dvbs2_get_dmd_status
1114  * get DVB-S2 Demod LOCK status
1115  */
1116 static enum stb0899_status stb0899_dvbs2_get_dmd_status(struct stb0899_state *state, int timeout)
1117 {
1118         int time = -10, lock = 0, uwp, csm;
1119         u32 reg;
1120
1121         do {
1122                 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, DMD_STATUS);
1123                 dprintk(state->verbose, FE_DEBUG, 1, "DMD_STATUS=[0x%02x]", reg);
1124                 if (STB0899_GETFIELD(IF_AGC_LOCK, reg))
1125                         dprintk(state->verbose, FE_DEBUG, 1, "------------->IF AGC LOCKED !");
1126                 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, DMD_STAT2);
1127                 dprintk(state->verbose, FE_DEBUG, 1, "----------->DMD STAT2=[0x%02x]", reg);
1128                 uwp = STB0899_GETFIELD(UWP_LOCK, reg);
1129                 csm = STB0899_GETFIELD(CSM_LOCK, reg);
1130                 if (uwp && csm)
1131                         lock = 1;
1132
1133                 time += 10;
1134                 msleep(10);
1135
1136         } while ((!lock) && (time <= timeout));
1137
1138         if (lock) {
1139                 dprintk(state->verbose, FE_DEBUG, 1, "----------------> DVB-S2 LOCK !");
1140                 return DVBS2_DEMOD_LOCK;
1141         } else {
1142                 return DVBS2_DEMOD_NOLOCK;
1143         }
1144 }
1145
1146 /*
1147  * stb0899_dvbs2_get_data_lock
1148  * get FEC status
1149  */
1150 static int stb0899_dvbs2_get_data_lock(struct stb0899_state *state, int timeout)
1151 {
1152         int time = 0, lock = 0;
1153         u8 reg;
1154
1155         while ((!lock) && (time < timeout)) {
1156                 reg = stb0899_read_reg(state, STB0899_CFGPDELSTATUS1);
1157                 dprintk(state->verbose, FE_DEBUG, 1, "---------> CFGPDELSTATUS=[0x%02x]", reg);
1158                 lock = STB0899_GETFIELD(CFGPDELSTATUS_LOCK, reg);
1159                 time++;
1160         }
1161
1162         return lock;
1163 }
1164
1165 /*
1166  * stb0899_dvbs2_get_fec_status
1167  * get DVB-S2 FEC LOCK status
1168  */
1169 static enum stb0899_status stb0899_dvbs2_get_fec_status(struct stb0899_state *state, int timeout)
1170 {
1171         int time = 0, Locked;
1172
1173         do {
1174                 Locked = stb0899_dvbs2_get_data_lock(state, 1);
1175                 time++;
1176                 msleep(1);
1177
1178         } while ((!Locked) && (time < timeout));
1179
1180         if (Locked) {
1181                 dprintk(state->verbose, FE_DEBUG, 1, "---------->DVB-S2 FEC LOCK !");
1182                 return DVBS2_FEC_LOCK;
1183         } else {
1184                 return DVBS2_FEC_NOLOCK;
1185         }
1186 }
1187
1188
1189 /*
1190  * stb0899_dvbs2_init_csm
1191  * set parameters for manual mode
1192  */
1193 static void stb0899_dvbs2_init_csm(struct stb0899_state *state, int pilots, enum stb0899_modcod modcod)
1194 {
1195         struct stb0899_internal *internal = &state->internal;
1196
1197         s32 dvt_tbl = 1, two_pass = 0, agc_gain = 6, agc_shift = 0, loop_shift = 0, phs_diff_thr = 0x80;
1198         s32 gamma_acq, gamma_rho_acq, gamma_trk, gamma_rho_trk, lock_count_thr;
1199         u32 csm1, csm2, csm3, csm4;
1200
1201         if (((internal->master_clk / internal->srate) <= 4) && (modcod <= 11) && (pilots == 1)) {
1202                 switch (modcod) {
1203                 case STB0899_QPSK_12:
1204                         gamma_acq               = 25;
1205                         gamma_rho_acq           = 2700;
1206                         gamma_trk               = 12;
1207                         gamma_rho_trk           = 180;
1208                         lock_count_thr          = 8;
1209                         break;
1210                 case STB0899_QPSK_35:
1211                         gamma_acq               = 38;
1212                         gamma_rho_acq           = 7182;
1213                         gamma_trk               = 14;
1214                         gamma_rho_trk           = 308;
1215                         lock_count_thr          = 8;
1216                         break;
1217                 case STB0899_QPSK_23:
1218                         gamma_acq               = 42;
1219                         gamma_rho_acq           = 9408;
1220                         gamma_trk               = 17;
1221                         gamma_rho_trk           = 476;
1222                         lock_count_thr          = 8;
1223                         break;
1224                 case STB0899_QPSK_34:
1225                         gamma_acq               = 53;
1226                         gamma_rho_acq           = 16642;
1227                         gamma_trk               = 19;
1228                         gamma_rho_trk           = 646;
1229                         lock_count_thr          = 8;
1230                         break;
1231                 case STB0899_QPSK_45:
1232                         gamma_acq               = 53;
1233                         gamma_rho_acq           = 17119;
1234                         gamma_trk               = 22;
1235                         gamma_rho_trk           = 880;
1236                         lock_count_thr          = 8;
1237                         break;
1238                 case STB0899_QPSK_56:
1239                         gamma_acq               = 55;
1240                         gamma_rho_acq           = 19250;
1241                         gamma_trk               = 23;
1242                         gamma_rho_trk           = 989;
1243                         lock_count_thr          = 8;
1244                         break;
1245                 case STB0899_QPSK_89:
1246                         gamma_acq               = 60;
1247                         gamma_rho_acq           = 24240;
1248                         gamma_trk               = 24;
1249                         gamma_rho_trk           = 1176;
1250                         lock_count_thr          = 8;
1251                         break;
1252                 case STB0899_QPSK_910:
1253                         gamma_acq               = 66;
1254                         gamma_rho_acq           = 29634;
1255                         gamma_trk               = 24;
1256                         gamma_rho_trk           = 1176;
1257                         lock_count_thr          = 8;
1258                         break;
1259                 default:
1260                         gamma_acq               = 66;
1261                         gamma_rho_acq           = 29634;
1262                         gamma_trk               = 24;
1263                         gamma_rho_trk           = 1176;
1264                         lock_count_thr          = 8;
1265                         break;
1266                 }
1267
1268                 csm1 = STB0899_READ_S2REG(STB0899_S2DEMOD, CSM_CNTRL1);
1269                 STB0899_SETFIELD_VAL(CSM_AUTO_PARAM, csm1, 0);
1270                 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CSM_CNTRL1, STB0899_OFF0_CSM_CNTRL1, csm1);
1271
1272                 csm1 = STB0899_READ_S2REG(STB0899_S2DEMOD, CSM_CNTRL1);
1273                 csm2 = STB0899_READ_S2REG(STB0899_S2DEMOD, CSM_CNTRL2);
1274                 csm3 = STB0899_READ_S2REG(STB0899_S2DEMOD, CSM_CNTRL3);
1275                 csm4 = STB0899_READ_S2REG(STB0899_S2DEMOD, CSM_CNTRL4);
1276
1277                 STB0899_SETFIELD_VAL(CSM_DVT_TABLE, csm1, dvt_tbl);
1278                 STB0899_SETFIELD_VAL(CSM_TWO_PASS, csm1, two_pass);
1279                 STB0899_SETFIELD_VAL(CSM_AGC_GAIN, csm1, agc_gain);
1280                 STB0899_SETFIELD_VAL(CSM_AGC_SHIFT, csm1, agc_shift);
1281                 STB0899_SETFIELD_VAL(FE_LOOP_SHIFT, csm1, loop_shift);
1282                 STB0899_SETFIELD_VAL(CSM_GAMMA_ACQ, csm2, gamma_acq);
1283                 STB0899_SETFIELD_VAL(CSM_GAMMA_RHOACQ, csm2, gamma_rho_acq);
1284                 STB0899_SETFIELD_VAL(CSM_GAMMA_TRACK, csm3, gamma_trk);
1285                 STB0899_SETFIELD_VAL(CSM_GAMMA_RHOTRACK, csm3, gamma_rho_trk);
1286                 STB0899_SETFIELD_VAL(CSM_LOCKCOUNT_THRESH, csm4, lock_count_thr);
1287                 STB0899_SETFIELD_VAL(CSM_PHASEDIFF_THRESH, csm4, phs_diff_thr);
1288
1289                 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CSM_CNTRL1, STB0899_OFF0_CSM_CNTRL1, csm1);
1290                 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CSM_CNTRL2, STB0899_OFF0_CSM_CNTRL2, csm2);
1291                 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CSM_CNTRL3, STB0899_OFF0_CSM_CNTRL3, csm3);
1292                 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CSM_CNTRL4, STB0899_OFF0_CSM_CNTRL4, csm4);
1293         }
1294 }
1295
1296 /*
1297  * stb0899_dvbs2_get_srate
1298  * get DVB-S2 Symbol Rate
1299  */
1300 static u32 stb0899_dvbs2_get_srate(struct stb0899_state *state)
1301 {
1302         struct stb0899_internal *internal = &state->internal;
1303         struct stb0899_config *config = state->config;
1304
1305         u32 bTrNomFreq, srate, decimRate, intval1, intval2, reg;
1306         int div1, div2, rem1, rem2;
1307
1308         div1 = config->btr_nco_bits / 2;
1309         div2 = config->btr_nco_bits - div1 - 1;
1310
1311         bTrNomFreq = STB0899_READ_S2REG(STB0899_S2DEMOD, BTR_NOM_FREQ);
1312
1313         reg = STB0899_READ_S2REG(STB0899_S2DEMOD, DECIM_CNTRL);
1314         decimRate = STB0899_GETFIELD(DECIM_RATE, reg);
1315         decimRate = (1 << decimRate);
1316
1317         intval1 = internal->master_clk / (1 << div1);
1318         intval2 = bTrNomFreq / (1 << div2);
1319
1320         rem1 = internal->master_clk % (1 << div1);
1321         rem2 = bTrNomFreq % (1 << div2);
1322         /* only for integer calculation */
1323         srate = (intval1 * intval2) + ((intval1 * rem2) / (1 << div2)) + ((intval2 * rem1) / (1 << div1));
1324         srate /= decimRate;     /*symbrate = (btrnomfreq_register_val*MasterClock)/2^(27+decim_rate_field) */
1325
1326         return  srate;
1327 }
1328
1329 /*
1330  * stb0899_dvbs2_algo
1331  * Search for signal, timing, carrier and data for a given
1332  * frequency in a given range
1333  */
1334 enum stb0899_status stb0899_dvbs2_algo(struct stb0899_state *state)
1335 {
1336         struct stb0899_internal *internal = &state->internal;
1337         enum stb0899_modcod modcod;
1338
1339         s32 offsetfreq, searchTime, FecLockTime, pilots, iqSpectrum;
1340         int i = 0;
1341         u32 reg, csm1;
1342
1343         if (internal->srate <= 2000000) {
1344                 searchTime      = 5000; /* 5000 ms max time to lock UWP and CSM, SYMB <= 2Mbs           */
1345                 FecLockTime     = 350;  /* 350  ms max time to lock FEC, SYMB <= 2Mbs                   */
1346         } else if (internal->srate <= 5000000) {
1347                 searchTime      = 2500; /* 2500 ms max time to lock UWP and CSM, 2Mbs < SYMB <= 5Mbs    */
1348                 FecLockTime     = 170;  /* 170  ms max time to lock FEC, 2Mbs< SYMB <= 5Mbs             */
1349         } else if (internal->srate <= 10000000) {
1350                 searchTime      = 1500; /* 1500 ms max time to lock UWP and CSM, 5Mbs <SYMB <= 10Mbs    */
1351                 FecLockTime     = 80;   /* 80  ms max time to lock FEC, 5Mbs< SYMB <= 10Mbs             */
1352         } else if (internal->srate <= 15000000) {
1353                 searchTime      = 500;  /* 500 ms max time to lock UWP and CSM, 10Mbs <SYMB <= 15Mbs    */
1354                 FecLockTime     = 50;   /* 50  ms max time to lock FEC, 10Mbs< SYMB <= 15Mbs            */
1355         } else if (internal->srate <= 20000000) {
1356                 searchTime      = 300;  /* 300 ms max time to lock UWP and CSM, 15Mbs < SYMB <= 20Mbs   */
1357                 FecLockTime     = 30;   /* 50  ms max time to lock FEC, 15Mbs< SYMB <= 20Mbs            */
1358         } else if (internal->srate <= 25000000) {
1359                 searchTime      = 250;  /* 250 ms max time to lock UWP and CSM, 20 Mbs < SYMB <= 25Mbs  */
1360                 FecLockTime     = 25;   /* 25 ms max time to lock FEC, 20Mbs< SYMB <= 25Mbs             */
1361         } else {
1362                 searchTime      = 150;  /* 150 ms max time to lock UWP and CSM, SYMB > 25Mbs            */
1363                 FecLockTime     = 20;   /* 20 ms max time to lock FEC, 20Mbs< SYMB <= 25Mbs             */
1364         }
1365
1366         /* Maintain Stream Merger in reset during acquisition   */
1367         reg = stb0899_read_reg(state, STB0899_TSTRES);
1368         STB0899_SETFIELD_VAL(FRESRS, reg, 1);
1369         stb0899_write_reg(state, STB0899_TSTRES, reg);
1370
1371         /* Move tuner to frequency      */
1372         if (state->config->tuner_set_frequency)
1373                 state->config->tuner_set_frequency(&state->frontend, internal->freq);
1374         if (state->config->tuner_get_frequency)
1375                 state->config->tuner_get_frequency(&state->frontend, &internal->freq);
1376
1377         /* Set IF AGC to acquisition    */
1378         reg = STB0899_READ_S2REG(STB0899_S2DEMOD, IF_AGC_CNTRL);
1379         STB0899_SETFIELD_VAL(IF_LOOP_GAIN, reg,  4);
1380         STB0899_SETFIELD_VAL(IF_AGC_REF, reg, 32);
1381         stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_IF_AGC_CNTRL, STB0899_OFF0_IF_AGC_CNTRL, reg);
1382
1383         reg = STB0899_READ_S2REG(STB0899_S2DEMOD, IF_AGC_CNTRL2);
1384         STB0899_SETFIELD_VAL(IF_AGC_DUMP_PER, reg, 0);
1385         stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_IF_AGC_CNTRL2, STB0899_OFF0_IF_AGC_CNTRL2, reg);
1386
1387         /* Initialisation       */
1388         stb0899_dvbs2_init_calc(state);
1389
1390         reg = STB0899_READ_S2REG(STB0899_S2DEMOD, DMD_CNTRL2);
1391         switch (internal->inversion) {
1392         case IQ_SWAP_OFF:
1393                 STB0899_SETFIELD_VAL(SPECTRUM_INVERT, reg, 0);
1394                 break;
1395         case IQ_SWAP_ON:
1396                 STB0899_SETFIELD_VAL(SPECTRUM_INVERT, reg, 1);
1397                 break;
1398         case IQ_SWAP_AUTO:      /* use last successful search first     */
1399                 STB0899_SETFIELD_VAL(SPECTRUM_INVERT, reg, 1);
1400                 break;
1401         }
1402         stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_DMD_CNTRL2, STB0899_OFF0_DMD_CNTRL2, reg);
1403         stb0899_dvbs2_reacquire(state);
1404
1405         /* Wait for demod lock (UWP and CSM)    */
1406         internal->status = stb0899_dvbs2_get_dmd_status(state, searchTime);
1407
1408         if (internal->status == DVBS2_DEMOD_LOCK) {
1409                 dprintk(state->verbose, FE_DEBUG, 1, "------------> DVB-S2 DEMOD LOCK !");
1410                 i = 0;
1411                 /* Demod Locked, check FEC status       */
1412                 internal->status = stb0899_dvbs2_get_fec_status(state, FecLockTime);
1413
1414                 /*If false lock (UWP and CSM Locked but no FEC) try 3 time max*/
1415                 while ((internal->status != DVBS2_FEC_LOCK) && (i < 3)) {
1416                         /*      Read the frequency offset*/
1417                         offsetfreq = STB0899_READ_S2REG(STB0899_S2DEMOD, CRL_FREQ);
1418
1419                         /* Set the Nominal frequency to the found frequency offset for the next reacquire*/
1420                         reg = STB0899_READ_S2REG(STB0899_S2DEMOD, CRL_NOM_FREQ);
1421                         STB0899_SETFIELD_VAL(CRL_NOM_FREQ, reg, offsetfreq);
1422                         stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CRL_NOM_FREQ, STB0899_OFF0_CRL_NOM_FREQ, reg);
1423                         stb0899_dvbs2_reacquire(state);
1424                         internal->status = stb0899_dvbs2_get_fec_status(state, searchTime);
1425                         i++;
1426                 }
1427         }
1428
1429         if (internal->status != DVBS2_FEC_LOCK) {
1430                 if (internal->inversion == IQ_SWAP_AUTO) {
1431                         reg = STB0899_READ_S2REG(STB0899_S2DEMOD, DMD_CNTRL2);
1432                         iqSpectrum = STB0899_GETFIELD(SPECTRUM_INVERT, reg);
1433                         /* IQ Spectrum Inversion        */
1434                         STB0899_SETFIELD_VAL(SPECTRUM_INVERT, reg, !iqSpectrum);
1435                         stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_DMD_CNTRL2, STB0899_OFF0_DMD_CNTRL2, reg);
1436                         /* start acquistion process     */
1437                         stb0899_dvbs2_reacquire(state);
1438
1439                         /* Wait for demod lock (UWP and CSM)    */
1440                         internal->status = stb0899_dvbs2_get_dmd_status(state, searchTime);
1441                         if (internal->status == DVBS2_DEMOD_LOCK) {
1442                                 i = 0;
1443                                 /* Demod Locked, check FEC      */
1444                                 internal->status = stb0899_dvbs2_get_fec_status(state, FecLockTime);
1445                                 /*try thrice for false locks, (UWP and CSM Locked but no FEC)   */
1446                                 while ((internal->status != DVBS2_FEC_LOCK) && (i < 3)) {
1447                                         /*      Read the frequency offset*/
1448                                         offsetfreq = STB0899_READ_S2REG(STB0899_S2DEMOD, CRL_FREQ);
1449
1450                                         /* Set the Nominal frequency to the found frequency offset for the next reacquire*/
1451                                         reg = STB0899_READ_S2REG(STB0899_S2DEMOD, CRL_NOM_FREQ);
1452                                         STB0899_SETFIELD_VAL(CRL_NOM_FREQ, reg, offsetfreq);
1453                                         stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CRL_NOM_FREQ, STB0899_OFF0_CRL_NOM_FREQ, reg);
1454
1455                                         stb0899_dvbs2_reacquire(state);
1456                                         internal->status = stb0899_dvbs2_get_fec_status(state, searchTime);
1457                                         i++;
1458                                 }
1459                         }
1460 /*
1461                         if (pParams->DVBS2State == FE_DVBS2_FEC_LOCKED)
1462                                 pParams->IQLocked = !iqSpectrum;
1463 */
1464                 }
1465         }
1466         if (internal->status == DVBS2_FEC_LOCK) {
1467                 dprintk(state->verbose, FE_DEBUG, 1, "----------------> DVB-S2 FEC Lock !");
1468                 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, UWP_STAT2);
1469                 modcod = STB0899_GETFIELD(UWP_DECODE_MOD, reg) >> 2;
1470                 pilots = STB0899_GETFIELD(UWP_DECODE_MOD, reg) & 0x01;
1471
1472                 if ((((10 * internal->master_clk) / (internal->srate / 10)) <= 410) &&
1473                       (INRANGE(STB0899_QPSK_23, modcod, STB0899_QPSK_910)) &&
1474                       (pilots == 1)) {
1475
1476                         stb0899_dvbs2_init_csm(state, pilots, modcod);
1477                         /* Wait for UWP,CSM and data LOCK 20ms max      */
1478                         internal->status = stb0899_dvbs2_get_fec_status(state, FecLockTime);
1479
1480                         i = 0;
1481                         while ((internal->status != DVBS2_FEC_LOCK) && (i < 3)) {
1482                                 csm1 = STB0899_READ_S2REG(STB0899_S2DEMOD, CSM_CNTRL1);
1483                                 STB0899_SETFIELD_VAL(CSM_TWO_PASS, csm1, 1);
1484                                 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CSM_CNTRL1, STB0899_OFF0_CSM_CNTRL1, csm1);
1485                                 csm1 = STB0899_READ_S2REG(STB0899_S2DEMOD, CSM_CNTRL1);
1486                                 STB0899_SETFIELD_VAL(CSM_TWO_PASS, csm1, 0);
1487                                 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CSM_CNTRL1, STB0899_OFF0_CSM_CNTRL1, csm1);
1488
1489                                 internal->status = stb0899_dvbs2_get_fec_status(state, FecLockTime);
1490                                 i++;
1491                         }
1492                 }
1493
1494                 if ((((10 * internal->master_clk) / (internal->srate / 10)) <= 410) &&
1495                       (INRANGE(STB0899_QPSK_12, modcod, STB0899_QPSK_35)) &&
1496                       (pilots == 1)) {
1497
1498                         /* Equalizer Disable update      */
1499                         reg = STB0899_READ_S2REG(STB0899_S2DEMOD, EQ_CNTRL);
1500                         STB0899_SETFIELD_VAL(EQ_DISABLE_UPDATE, reg, 1);
1501                         stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_EQ_CNTRL, STB0899_OFF0_EQ_CNTRL, reg);
1502                 }
1503
1504                 /* slow down the Equalizer once locked  */
1505                 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, EQ_CNTRL);
1506                 STB0899_SETFIELD_VAL(EQ_SHIFT, reg, 0x02);
1507                 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_EQ_CNTRL, STB0899_OFF0_EQ_CNTRL, reg);
1508
1509                 /* Store signal parameters      */
1510                 offsetfreq = STB0899_READ_S2REG(STB0899_S2DEMOD, CRL_FREQ);
1511
1512                 offsetfreq = offsetfreq / ((1 << 30) / 1000);
1513                 offsetfreq *= (internal->master_clk / 1000000);
1514                 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, DMD_CNTRL2);
1515                 if (STB0899_GETFIELD(SPECTRUM_INVERT, reg))
1516                         offsetfreq *= -1;
1517
1518                 internal->freq = internal->freq - offsetfreq;
1519                 internal->srate = stb0899_dvbs2_get_srate(state);
1520
1521                 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, UWP_STAT2);
1522                 internal->modcod = STB0899_GETFIELD(UWP_DECODE_MOD, reg) >> 2;
1523                 internal->pilots = STB0899_GETFIELD(UWP_DECODE_MOD, reg) & 0x01;
1524                 internal->frame_length = (STB0899_GETFIELD(UWP_DECODE_MOD, reg) >> 1) & 0x01;
1525
1526                  /* Set IF AGC to tracking      */
1527                 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, IF_AGC_CNTRL);
1528                 STB0899_SETFIELD_VAL(IF_LOOP_GAIN, reg,  3);
1529
1530                 /* if QPSK 1/2,QPSK 3/5 or QPSK 2/3 set IF AGC reference to 16 otherwise 32*/
1531                 if (INRANGE(STB0899_QPSK_12, internal->modcod, STB0899_QPSK_23))
1532                         STB0899_SETFIELD_VAL(IF_AGC_REF, reg, 16);
1533
1534                 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_IF_AGC_CNTRL, STB0899_OFF0_IF_AGC_CNTRL, reg);
1535
1536                 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, IF_AGC_CNTRL2);
1537                 STB0899_SETFIELD_VAL(IF_AGC_DUMP_PER, reg, 7);
1538                 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_IF_AGC_CNTRL2, STB0899_OFF0_IF_AGC_CNTRL2, reg);
1539         }
1540
1541         /* Release Stream Merger Reset          */
1542         reg = stb0899_read_reg(state, STB0899_TSTRES);
1543         STB0899_SETFIELD_VAL(FRESRS, reg, 0);
1544         stb0899_write_reg(state, STB0899_TSTRES, reg);
1545
1546         return internal->status;
1547 }