drivers/media/dvb/frontends/stb0899_algo.c

   1 /*
   2         STB0899 Multistandard Frontend driver
   3         Copyright (C) Manu Abraham (abraham.manu@gmail.com)
   4
   5         Copyright (C) ST Microelectronics
   6
   7         This program is free software; you can redistribute it and/or modify
   8         it under the terms of the GNU General Public License as published by
   9         the Free Software Foundation; either version 2 of the License, or
  10         (at your option) any later version.
  11
  12         This program is distributed in the hope that it will be useful,
  13         but WITHOUT ANY WARRANTY; without even the implied warranty of
  14         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15         GNU General Public License for more details.
  16
  17         You should have received a copy of the GNU General Public License
  18         along with this program; if not, write to the Free Software
  19         Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  20 */
  21
  22 #include "stb0899_drv.h"
  23 #include "stb0899_priv.h"
  24 #include "stb0899_reg.h"
  25
  26 /*
  27  * BinaryFloatDiv
  28  * float division with integer
  29  */
  30 static long BinaryFloatDiv(long n1, long n2, int precision)
  31 {
  32         int i = 0;
  33         long result = 0;
  34
  35         while (i <= precision) {
  36                 if (n1 < n2) {
  37                         result *= 2;
  38                         n1 *= 2;
  39                 } else {
  40                         result = result * 2 + 1;
  41                         n1 = (n1 - n2) * 2;
  42                 }
  43                 i++;
  44         }
  45
  46         return result;
  47 }
  48
  49 /*
  50  * stb0899_calc_srate
  51  * Compute symbol rate
  52  */
  53 static u32 stb0899_calc_srate(u32 master_clk, u8 *sfr)
  54 {
  55         u32 tmp, tmp2, mclk;
  56
  57         mclk  =  master_clk / 4096L; /* MasterClock * 10 / 2^20 */
  58         tmp  = (((u32) sfr[0] << 12) + ((u32) sfr[1] << 4)) / 16;
  59
  60         tmp *= mclk;
  61         tmp /= 16;
  62         tmp2 = ((u32) sfr[2] * mclk) / 256;
  63         tmp += tmp2;
  64
  65         return tmp;
  66 }
  67
  68 /*
  69  * stb0899_get_srate
  70  * Get the current symbol rate
  71  */
  72 u32 stb0899_get_srate(struct stb0899_state *state)
  73 {
  74         struct stb0899_internal *internal = &state->internal;
  75         u8 sfr[4];
  76
  77         stb0899_read_regs(state, STB0899_SFRH, sfr, 3);
  78
  79         return stb0899_calc_srate(internal->master_clk, sfr);
  80 }
  81
  82 /*
  83  * stb0899_set_srate
  84  * Set symbol frequency
  85  * MasterClock: master clock frequency (hz)
  86  * SymbolRate: symbol rate (bauds)
  87  * return symbol frequency
  88  */
  89 static u32 stb0899_set_srate(struct stb0899_state *state, u32 master_clk, u32 srate)
  90 {
  91         u32 tmp, tmp_up, srate_up;
  92         u8 sfr_up[3], sfr[3];
  93
  94 //      srate_up = srate;
  95         dprintk(state->verbose, FE_DEBUG, 1, "-->");
  96         /*
  97          * in order to have the maximum precision, the symbol rate entered into
  98          * the chip is computed as the closest value of the "true value".
  99          * In this purpose, the symbol rate value is rounded (1 is added on the bit
 100          * below the LSB )
 101          */
 102 //      srate_up += (srate_up * 3) / 100;
 103
 104         tmp = BinaryFloatDiv(srate, master_clk, 20);
 105 //      tmp_up = BinaryFloatDiv(srate_up, master_clk, 20);
 106
 107 //      sfr_up[0] = (tmp_up >> 12) & 0xff;
 108 //      sfr_up[1] = (tmp_up >>  4) & 0xff;
 109 //      sfr_up[2] =  tmp_up & 0x0f;
 110
 111         sfr[0] = (tmp >> 12) & 0xff;
 112         sfr[1] = (tmp >>  4) & 0xff;
 113         sfr[2] =  tmp & 0xf0;
 114
 115 //      stb0899_write_regs(state, STB0899_SFRUPH, sfr_up, 3);
 116         stb0899_write_regs(state, STB0899_SFRH, sfr, 3);
 117
 118         return srate;
 119 }
 120
 121 /*
 122  * stb0899_calc_loop_time
 123  * Compute the amount of time needed by the timing loop to lock
 124  * SymbolRate: Symbol rate
 125  * return: timing loop time constant (ms)
 126  */
 127 static long stb0899_calc_loop_time(long srate)
 128 {
 129         if (srate > 0)
 130                 return (100000 / (srate / 1000));
 131         else
 132                 return 0;
 133 }
 134
 135 /*
 136  * stb0899_calc_derot_time
 137  * Compute the amount of time needed by the derotator to lock
 138  * SymbolRate: Symbol rate
 139  * return: derotator time constant (ms)
 140  */
 141 static long stb0899_calc_derot_time(long srate)
 142 {
 143         if (srate > 0)
 144                 return (100000 / (srate / 1000));
 145         else
 146                 return 0;
 147 }
 148
 149 /*
 150  * stb0899_carr_width
 151  * Compute the width of the carrier
 152  * return: width of carrier (kHz or Mhz)
 153  */
 154 long stb0899_carr_width(struct stb0899_state *state)
 155 {
 156         struct stb0899_internal *internal = &state->internal;
 157
 158         return (internal->srate + (internal->srate * internal->rolloff) / 100);
 159 }
 160
 161 /*
 162  * stb0899_first_subrange
 163  * Compute the first subrange of the search
 164  */
 165 static void stb0899_first_subrange(struct stb0899_state *state)
 166 {
 167         struct stb0899_internal *internal       = &state->internal;
 168         struct stb0899_params *params           = &state->params;
 169         struct stb0899_config *config           =  state->config;
 170
 171         int range = 0;
 172         u32 bandwidth = 0;
 173
 174         if (config->tuner_get_bandwidth) {
 175                 config->tuner_get_bandwidth(&state->frontend, &bandwidth);
 176                 range = bandwidth - stb0899_carr_width(state) / 2;
 177         }
 178
 179         if (range > 0)
 180                 internal->sub_range = MIN(internal->srch_range, range);
 181         else
 182                 internal->sub_range = 0;
 183
 184         internal->freq = params->freq;
 185         internal->tuner_offst = 0L;
 186         internal->sub_dir = 1;
 187 }
 188
 189 /*
 190  * stb0899_check_tmg
 191  * check for timing lock
 192  * internal.Ttiming: time to wait for loop lock
 193  */
 194 static enum stb0899_status stb0899_check_tmg(struct stb0899_state *state)
 195 {
 196         struct stb0899_internal *internal = &state->internal;
 197         int lock;
 198         u8 reg;
 199         s8 timing;
 200
 201         msleep(internal->t_timing);
 202
 203         reg = stb0899_read_reg(state, STB0899_RTF);
 204         STB0899_SETFIELD_VAL(RTF_TIMING_LOOP_FREQ, reg, 0xf2);
 205         stb0899_write_reg(state, STB0899_RTF, reg);
 206         reg = stb0899_read_reg(state, STB0899_TLIR);
 207         lock = STB0899_GETFIELD(TLIR_TMG_LOCK_IND, reg);
 208         timing = stb0899_read_reg(state, STB0899_RTF);
 209
 210         if (lock >= 42) {
 211                 if ((lock > 48) && (ABS(timing) >= 110)) {
 212                         internal->status = ANALOGCARRIER;
 213                         dprintk(state->verbose, FE_DEBUG, 1, "-->ANALOG Carrier !");
 214                 } else {
 215                         internal->status = TIMINGOK;
 216                         dprintk(state->verbose, FE_DEBUG, 1, "------->TIMING OK !");
 217                 }
 218         } else {
 219                 internal->status = NOTIMING;
 220                 dprintk(state->verbose, FE_DEBUG, 1, "-->NO TIMING !");
 221         }
 222         return internal->status;
 223 }
 224
 225 /*
 226  * stb0899_search_tmg
 227  * perform a fs/2 zig-zag to find timing
 228  */
 229 static enum stb0899_status stb0899_search_tmg(struct stb0899_state *state)
 230 {
 231         struct stb0899_internal *internal = &state->internal;
 232         struct stb0899_params *params = &state->params;
 233
 234         short int derot_step, derot_freq = 0, derot_limit, next_loop = 3;
 235         int index = 0;
 236         u8 cfr[2];
 237
 238         internal->status = NOTIMING;
 239
 240         /* timing loop computation & symbol rate optimisation   */
 241         derot_limit = (internal->sub_range / 2L) / internal->mclk;
 242         derot_step = (params->srate / 2L) / internal->mclk;
 243
 244         while ((stb0899_check_tmg(state) != TIMINGOK) && next_loop) {
 245                 index++;
 246                 derot_freq += index * internal->direction * derot_step; /* next derot zig zag position  */
 247
 248                 if (ABS(derot_freq) > derot_limit)
 249                         next_loop--;
 250
 251                 if (next_loop) {
 252                         STB0899_SETFIELD_VAL(CFRM, cfr[0], MSB(state->config->inversion * derot_freq));
 253                         STB0899_SETFIELD_VAL(CFRL, cfr[1], LSB(state->config->inversion * derot_freq));
 254                         stb0899_write_regs(state, STB0899_CFRM, cfr, 2); /* derotator frequency         */
 255                 }
 256                 internal->direction = -internal->direction;     /* Change zigzag direction              */
 257         }
 258
 259         if (internal->status == TIMINGOK) {
 260                 stb0899_read_regs(state, STB0899_CFRM, cfr, 2); /* get derotator frequency              */
 261                 internal->derot_freq = state->config->inversion * MAKEWORD16(cfr[0], cfr[1]);
 262                 dprintk(state->verbose, FE_DEBUG, 1, "------->TIMING OK ! Derot Freq = %d", internal->derot_freq);
 263         }
 264
 265         return internal->status;
 266 }
 267
 268 /*
 269  * stb0899_check_carrier
 270  * Check for carrier found
 271  */
 272 static enum stb0899_status stb0899_check_carrier(struct stb0899_state *state)
 273 {
 274         struct stb0899_internal *internal = &state->internal;
 275         u8 reg;
 276
 277         msleep(internal->t_derot); /* wait for derotator ok     */
 278
 279         reg = stb0899_read_reg(state, STB0899_CFD);
 280         STB0899_SETFIELD_VAL(CFD_ON, reg, 1);
 281         stb0899_write_reg(state, STB0899_CFD, reg);
 282
 283         reg = stb0899_read_reg(state, STB0899_DSTATUS);
 284         dprintk(state->verbose, FE_DEBUG, 1, "--------------------> STB0899_DSTATUS=[0x%02x]", reg);
 285         if (STB0899_GETFIELD(CARRIER_FOUND, reg)) {
 286                 internal->status = CARRIEROK;
 287                 dprintk(state->verbose, FE_DEBUG, 1, "-------------> CARRIEROK !");
 288         } else {
 289                 internal->status = NOCARRIER;
 290                 dprintk(state->verbose, FE_DEBUG, 1, "-------------> NOCARRIER !");
 291         }
 292
 293         return internal->status;
 294 }
 295
 296 /*
 297  * stb0899_search_carrier
 298  * Search for a QPSK carrier with the derotator
 299  */
 300 static enum stb0899_status stb0899_search_carrier(struct stb0899_state *state)
 301 {
 302         struct stb0899_internal *internal = &state->internal;
 303
 304         short int derot_freq = 0, last_derot_freq = 0, derot_limit, next_loop = 3;
 305         int index = 0;
 306         u8 cfr[2];
 307         u8 reg;
 308
 309         internal->status = NOCARRIER;
 310         derot_limit = (internal->sub_range / 2L) / internal->mclk;
 311         derot_freq = internal->derot_freq;
 312
 313         reg = stb0899_read_reg(state, STB0899_CFD);
 314         STB0899_SETFIELD_VAL(CFD_ON, reg, 1);
 315         stb0899_write_reg(state, STB0899_CFD, reg);
 316
 317         do {
 318                 dprintk(state->verbose, FE_DEBUG, 1, "Derot Freq=%d, mclk=%d", derot_freq, internal->mclk);
 319                 if (stb0899_check_carrier(state) == NOCARRIER) {
 320                         index++;
 321                         last_derot_freq = derot_freq;
 322                         derot_freq += index * internal->direction * internal->derot_step; /* next zig zag derotator position    */
 323
 324                         if(ABS(derot_freq) > derot_limit)
 325                                 next_loop--;
 326
 327                         if (next_loop) {
 328                                 reg = stb0899_read_reg(state, STB0899_CFD);
 329                                 STB0899_SETFIELD_VAL(CFD_ON, reg, 1);
 330                                 stb0899_write_reg(state, STB0899_CFD, reg);
 331
 332                                 STB0899_SETFIELD_VAL(CFRM, cfr[0], MSB(state->config->inversion * derot_freq));
 333                                 STB0899_SETFIELD_VAL(CFRL, cfr[1], LSB(state->config->inversion * derot_freq));
 334                                 stb0899_write_regs(state, STB0899_CFRM, cfr, 2); /* derotator frequency */
 335                         }
 336                 }
 337
 338                 internal->direction = -internal->direction; /* Change zigzag direction  */
 339         } while ((internal->status != CARRIEROK) && next_loop);
 340
 341         if (internal->status == CARRIEROK) {
 342                 stb0899_read_regs(state, STB0899_CFRM, cfr, 2); /* get derotator frequency      */
 343                 internal->derot_freq = state->config->inversion * MAKEWORD16(cfr[0], cfr[1]);
 344                 dprintk(state->verbose, FE_DEBUG, 1, "----> CARRIER OK !, Derot Freq=%d", internal->derot_freq);
 345         } else {
 346                 internal->derot_freq = last_derot_freq;
 347         }
 348
 349         return internal->status;
 350 }
 351
 352 /*
 353  * stb0899_check_data
 354  * Check for data found
 355  */
 356 static enum stb0899_status stb0899_check_data(struct stb0899_state *state)
 357 {
 358         struct stb0899_internal *internal = &state->internal;
 359         struct stb0899_params *params = &state->params;
 360
 361         int lock = 0, index = 0, dataTime = 500, loop;
 362         u8 reg;
 363
 364         internal->status = NODATA;
 365
 366         /* RESET FEC    */
 367         reg = stb0899_read_reg(state, STB0899_TSTRES);
 368         STB0899_SETFIELD_VAL(FRESACS, reg, 1);
 369         stb0899_write_reg(state, STB0899_TSTRES, reg);
 370         msleep(1);
 371         reg = stb0899_read_reg(state, STB0899_TSTRES);
 372         STB0899_SETFIELD_VAL(FRESACS, reg, 0);
 373         stb0899_write_reg(state, STB0899_TSTRES, reg);
 374
 375         if (params->srate <= 2000000)
 376                 dataTime = 2000;
 377         else if (params->srate <= 5000000)
 378                 dataTime = 1500;
 379         else if (params->srate <= 15000000)
 380                 dataTime = 1000;
 381         else
 382                 dataTime = 500;
 383
 384         stb0899_write_reg(state, STB0899_DSTATUS2, 0x00); /* force search loop  */
 385         while (1) {
 386                 /* WARNING! VIT LOCKED has to be tested before VIT_END_LOOOP    */
 387                 reg = stb0899_read_reg(state, STB0899_VSTATUS);
 388                 lock = STB0899_GETFIELD(VSTATUS_LOCKEDVIT, reg);
 389                 loop = STB0899_GETFIELD(VSTATUS_END_LOOPVIT, reg);
 390
 391                 if (lock || loop || (index > dataTime))
 392                         break;
 393                 index++;
 394         }
 395
 396         if (lock) {     /* DATA LOCK indicator  */
 397                 internal->status = DATAOK;
 398                 dprintk(state->verbose, FE_DEBUG, 1, "-----------------> DATA OK !");
 399         }
 400
 401         return internal->status;
 402 }
 403
 404 /*
 405  * stb0899_search_data
 406  * Search for a QPSK carrier with the derotator
 407  */
 408 static enum stb0899_status stb0899_search_data(struct stb0899_state *state)
 409 {
 410         short int derot_freq, derot_step, derot_limit, next_loop = 3;
 411         u8 cfr[2];
 412         u8 reg;
 413         int index = 1;
 414
 415         struct stb0899_internal *internal = &state->internal;
 416         struct stb0899_params *params = &state->params;
 417
 418         derot_step = (params->srate / 4L) / internal->mclk;
 419         derot_limit = (internal->sub_range / 2L) / internal->mclk;
 420         derot_freq = internal->derot_freq;
 421
 422         do {
 423                 if ((internal->status != CARRIEROK) || (stb0899_check_data(state) != DATAOK)) {
 424
 425                         derot_freq += index * internal->direction * derot_step; /* next zig zag derotator position      */
 426                         if (ABS(derot_freq) > derot_limit)
 427                                 next_loop--;
 428
 429                         if (next_loop) {
 430                                 dprintk(state->verbose, FE_DEBUG, 1, "Derot freq=%d, mclk=%d", derot_freq, internal->mclk);
 431                                 reg = stb0899_read_reg(state, STB0899_CFD);
 432                                 STB0899_SETFIELD_VAL(CFD_ON, reg, 1);
 433                                 stb0899_write_reg(state, STB0899_CFD, reg);
 434
 435                                 STB0899_SETFIELD_VAL(CFRM, cfr[0], MSB(state->config->inversion * derot_freq));
 436                                 STB0899_SETFIELD_VAL(CFRL, cfr[1], LSB(state->config->inversion * derot_freq));
 437                                 stb0899_write_regs(state, STB0899_CFRM, cfr, 2); /* derotator frequency */
 438
 439                                 stb0899_check_carrier(state);
 440                                 index++;
 441                         }
 442                 }
 443                 internal->direction = -internal->direction; /* change zig zag direction         */
 444         } while ((internal->status != DATAOK) && next_loop);
 445
 446         if (internal->status == DATAOK) {
 447                 stb0899_read_regs(state, STB0899_CFRM, cfr, 2); /* get derotator frequency      */
 448                 internal->derot_freq = state->config->inversion * MAKEWORD16(cfr[0], cfr[1]);
 449                 dprintk(state->verbose, FE_DEBUG, 1, "------> DATAOK ! Derot Freq=%d", internal->derot_freq);
 450         }
 451
 452         return internal->status;
 453 }
 454
 455 /*
 456  * stb0899_check_range
 457  * check if the found frequency is in the correct range
 458  */
 459 static enum stb0899_status stb0899_check_range(struct stb0899_state *state)
 460 {
 461         struct stb0899_internal *internal = &state->internal;
 462         struct stb0899_params *params = &state->params;
 463
 464         int range_offst, tp_freq;
 465
 466         range_offst = internal->srch_range / 2000;
 467         tp_freq = internal->freq + (internal->derot_freq * internal->mclk) / 1000;
 468
 469         if ((tp_freq >= params->freq - range_offst) && (tp_freq <= params->freq + range_offst)) {
 470                 internal->status = RANGEOK;
 471                 dprintk(state->verbose, FE_DEBUG, 1, "----> RANGEOK !");
 472         } else {
 473                 internal->status = OUTOFRANGE;
 474                 dprintk(state->verbose, FE_DEBUG, 1, "----> OUT OF RANGE !");
 475         }
 476
 477         return internal->status;
 478 }
 479
 480 /*
 481  * NextSubRange
 482  * Compute the next subrange of the search
 483  */
 484 static void next_sub_range(struct stb0899_state *state)
 485 {
 486         struct stb0899_internal *internal = &state->internal;
 487         struct stb0899_params *params = &state->params;
 488
 489         long old_sub_range;
 490
 491         if (internal->sub_dir > 0) {
 492                 old_sub_range = internal->sub_range;
 493                 internal->sub_range = MIN((internal->srch_range / 2) -
 494                                           (internal->tuner_offst + internal->sub_range / 2),
 495                                            internal->sub_range);
 496
 497                 if (internal->sub_range < 0)
 498                         internal->sub_range = 0;
 499
 500                 internal->tuner_offst += (old_sub_range + internal->sub_range) / 2;
 501         }
 502
 503         internal->freq = params->freq + (internal->sub_dir * internal->tuner_offst) / 1000;
 504         internal->sub_dir = -internal->sub_dir;
 505 }
 506
 507 /*
 508  * stb0899_dvbs_algo
 509  * Search for a signal, timing, carrier and data for a
 510  * given frequency in a given range
 511  */
 512 enum stb0899_status stb0899_dvbs_algo(struct stb0899_state *state)
 513 {
 514         struct stb0899_params *params           = &state->params;
 515         struct stb0899_internal *internal       = &state->internal;
 516         struct stb0899_config *config           = state->config;
 517
 518         u8 bclc, reg;
 519         u8 cfr[2];
 520         u8 eq_const[10];
 521         s32 clnI = 3;
 522         u32 bandwidth = 0;
 523
 524         /* BETA values rated @ 99MHz    */
 525         s32 betaTab[5][4] = {
 526                /*  5   10   20   30MBps */
 527                 { 37,  34,  32,  31 }, /* QPSK 1/2      */
 528                 { 37,  35,  33,  31 }, /* QPSK 2/3      */
 529                 { 37,  35,  33,  31 }, /* QPSK 3/4      */
 530                 { 37,  36,  33,  32 }, /* QPSK 5/6      */
 531                 { 37,  36,  33,  32 }  /* QPSK 7/8      */
 532         };
 533
 534         internal->direction = 1;
 535
 536         stb0899_set_srate(state, internal->master_clk, params->srate);
 537         /* Carrier loop optimization versus symbol rate for acquisition*/
 538         if (params->srate <= 5000000) {
 539                 stb0899_write_reg(state, STB0899_ACLC, 0x89);
 540                 bclc = stb0899_read_reg(state, STB0899_BCLC);
 541                 STB0899_SETFIELD_VAL(BETA, bclc, 0x1c);
 542                 stb0899_write_reg(state, STB0899_BCLC, bclc);
 543                 clnI = 0;
 544         } else if (params->srate <= 15000000) {
 545                 stb0899_write_reg(state, STB0899_ACLC, 0xc9);
 546                 bclc = stb0899_read_reg(state, STB0899_BCLC);
 547                 STB0899_SETFIELD_VAL(BETA, bclc, 0x22);
 548                 stb0899_write_reg(state, STB0899_BCLC, bclc);
 549                 clnI = 1;
 550         } else if(params->srate <= 25000000) {
 551                 stb0899_write_reg(state, STB0899_ACLC, 0x89);
 552                 bclc = stb0899_read_reg(state, STB0899_BCLC);
 553                 STB0899_SETFIELD_VAL(BETA, bclc, 0x27);
 554                 stb0899_write_reg(state, STB0899_BCLC, bclc);
 555                 clnI = 2;
 556         } else {
 557                 stb0899_write_reg(state, STB0899_ACLC, 0xc8);
 558                 bclc = stb0899_read_reg(state, STB0899_BCLC);
 559                 STB0899_SETFIELD_VAL(BETA, bclc, 0x29);
 560                 stb0899_write_reg(state, STB0899_BCLC, bclc);
 561                 clnI = 3;
 562         }
 563
 564         dprintk(state->verbose, FE_DEBUG, 1, "Set the timing loop to acquisition");
 565         /* Set the timing loop to acquisition   */
 566         stb0899_write_reg(state, STB0899_RTC, 0x46);
 567         stb0899_write_reg(state, STB0899_CFD, 0xee);
 568
 569         /* !! WARNING !!
 570          * Do not read any status variables while acquisition,
 571          * If any needed, read before the acquisition starts
 572          * querying status while acquiring causes the
 573          * acquisition to go bad and hence no locks.
 574          */
 575         dprintk(state->verbose, FE_DEBUG, 1, "Derot Percent=%d Srate=%d mclk=%d",
 576                 internal->derot_percent, params->srate, internal->mclk);
 577
 578         /* Initial calculations */
 579         internal->derot_step = internal->derot_percent * (params->srate / 1000L) / internal->mclk; /* DerotStep/1000 * Fsymbol  */
 580         internal->t_timing = stb0899_calc_loop_time(params->srate);
 581         internal->t_derot = stb0899_calc_derot_time(params->srate);
 582         internal->t_data = 500;
 583
 584         dprintk(state->verbose, FE_DEBUG, 1, "RESET stream merger");
 585         /* RESET Stream merger  */
 586         reg = stb0899_read_reg(state, STB0899_TSTRES);
 587         STB0899_SETFIELD_VAL(FRESRS, reg, 1);
 588         stb0899_write_reg(state, STB0899_TSTRES, reg);
 589
 590         /*
 591          * Set KDIVIDER to an intermediate value between
 592          * 1/2 and 7/8 for acquisition
 593          */
 594         reg = stb0899_read_reg(state, STB0899_DEMAPVIT);
 595         STB0899_SETFIELD_VAL(DEMAPVIT_KDIVIDER, reg, 60);
 596         stb0899_write_reg(state, STB0899_DEMAPVIT, reg);
 597
 598         stb0899_write_reg(state, STB0899_EQON, 0x01); /* Equalizer OFF while acquiring  */
 599         stb0899_write_reg(state, STB0899_VITSYNC, 0x19);
 600
 601         stb0899_first_subrange(state);
 602         do {
 603                 /* Initialisations      */
 604                 cfr[0] = cfr[1] = 0;
 605                 stb0899_write_regs(state, STB0899_CFRM, cfr, 2); /* RESET derotator frequency   */
 606
 607                 reg = stb0899_read_reg(state, STB0899_RTF);
 608                 STB0899_SETFIELD_VAL(RTF_TIMING_LOOP_FREQ, reg, 0);
 609                 stb0899_write_reg(state, STB0899_RTF, reg);
 610                 reg = stb0899_read_reg(state, STB0899_CFD);
 611                 STB0899_SETFIELD_VAL(CFD_ON, reg, 1);
 612                 stb0899_write_reg(state, STB0899_CFD, reg);
 613
 614                 internal->derot_freq = 0;
 615                 internal->status = NOAGC1;
 616
 617                 /* Move tuner to frequency      */
 618                 dprintk(state->verbose, FE_DEBUG, 1, "Tuner set frequency");
 619                 if (state->config->tuner_set_frequency)
 620                         state->config->tuner_set_frequency(&state->frontend, internal->freq);
 621
 622                 if (state->config->tuner_get_frequency)
 623                         state->config->tuner_get_frequency(&state->frontend, &internal->freq);
 624
 625                 msleep(internal->t_agc1 + internal->t_agc2 + internal->t_timing); /* AGC1, AGC2 and timing loop */
 626                 dprintk(state->verbose, FE_DEBUG, 1, "current derot freq=%d", internal->derot_freq);
 627                 internal->status = AGC1OK;
 628
 629                 /* There is signal in the band  */
 630                 if (config->tuner_get_bandwidth)
 631                         config->tuner_get_bandwidth(&state->frontend, &bandwidth);
 632                 if (params->srate <= bandwidth / 2)
 633                         stb0899_search_tmg(state); /* For low rates (SCPC)      */
 634                 else
 635                         stb0899_check_tmg(state); /* For high rates (MCPC)      */
 636
 637                 if (internal->status == TIMINGOK) {
 638                         dprintk(state->verbose, FE_DEBUG, 1,
 639                                 "TIMING OK ! Derot freq=%d, mclk=%d",
 640                                 internal->derot_freq, internal->mclk);
 641
 642                         if (stb0899_search_carrier(state) == CARRIEROK) {       /* Search for carrier   */
 643                                 dprintk(state->verbose, FE_DEBUG, 1,
 644                                         "CARRIER OK ! Derot freq=%d, mclk=%d",
 645                                         internal->derot_freq, internal->mclk);
 646
 647                                 if (stb0899_search_data(state) == DATAOK) {     /* Check for data       */
 648                                         dprintk(state->verbose, FE_DEBUG, 1,
 649                                                 "DATA OK ! Derot freq=%d, mclk=%d",
 650                                                 internal->derot_freq, internal->mclk);
 651
 652                                         if (stb0899_check_range(state) == RANGEOK) {
 653                                                 dprintk(state->verbose, FE_DEBUG, 1,
 654                                                         "RANGE OK ! derot freq=%d, mclk=%d",
 655                                                         internal->derot_freq, internal->mclk);
 656
 657                                                 internal->freq = params->freq + ((internal->derot_freq * internal->mclk) / 1000);
 658                                                 reg = stb0899_read_reg(state, STB0899_PLPARM);
 659                                                 internal->fecrate = STB0899_GETFIELD(VITCURPUN, reg);
 660                                                 dprintk(state->verbose, FE_DEBUG, 1,
 661                                                         "freq=%d, internal resultant freq=%d",
 662                                                         params->freq, internal->freq);
 663
 664                                                 dprintk(state->verbose, FE_DEBUG, 1,
 665                                                         "internal puncture rate=%d",
 666                                                         internal->fecrate);
 667                                         }
 668                                 }
 669                         }
 670                 }
 671                 if (internal->status != RANGEOK)
 672                         next_sub_range(state);
 673
 674         } while (internal->sub_range && internal->status != RANGEOK);
 675
 676         /* Set the timing loop to tracking      */
 677         stb0899_write_reg(state, STB0899_RTC, 0x33);
 678         stb0899_write_reg(state, STB0899_CFD, 0xf7);
 679         /* if locked and range ok, set Kdiv     */
 680         if (internal->status == RANGEOK) {
 681                 dprintk(state->verbose, FE_DEBUG, 1, "Locked & Range OK !");
 682                 stb0899_write_reg(state, STB0899_EQON, 0x41);           /* Equalizer OFF while acquiring        */
 683                 stb0899_write_reg(state, STB0899_VITSYNC, 0x39);        /* SN to b'11 for acquisition           */
 684
 685                 /*
 686                  * Carrier loop optimization versus
 687                  * symbol Rate/Puncture Rate for Tracking
 688                  */
 689                 reg = stb0899_read_reg(state, STB0899_BCLC);
 690                 switch (internal->fecrate) {
 691                 case STB0899_FEC_1_2:           /* 13   */
 692                         stb0899_write_reg(state, STB0899_DEMAPVIT, 0x1a);
 693                         STB0899_SETFIELD_VAL(BETA, reg, betaTab[0][clnI]);
 694                         stb0899_write_reg(state, STB0899_BCLC, reg);
 695                         break;
 696                 case STB0899_FEC_2_3:           /* 18   */
 697                         stb0899_write_reg(state, STB0899_DEMAPVIT, 44);
 698                         STB0899_SETFIELD_VAL(BETA, reg, betaTab[1][clnI]);
 699                         stb0899_write_reg(state, STB0899_BCLC, reg);
 700                         break;
 701                 case STB0899_FEC_3_4:           /* 21   */
 702                         stb0899_write_reg(state, STB0899_DEMAPVIT, 60);
 703                         STB0899_SETFIELD_VAL(BETA, reg, betaTab[2][clnI]);
 704                         stb0899_write_reg(state, STB0899_BCLC, reg);
 705                         break;
 706                 case STB0899_FEC_5_6:           /* 24   */
 707                         stb0899_write_reg(state, STB0899_DEMAPVIT, 75);
 708                         STB0899_SETFIELD_VAL(BETA, reg, betaTab[3][clnI]);
 709                         stb0899_write_reg(state, STB0899_BCLC, reg);
 710                         break;
 711                 case STB0899_FEC_6_7:           /* 25   */
 712                         stb0899_write_reg(state, STB0899_DEMAPVIT, 88);
 713                         stb0899_write_reg(state, STB0899_ACLC, 0x88);
 714                         stb0899_write_reg(state, STB0899_BCLC, 0x9a);
 715                         break;
 716                 case STB0899_FEC_7_8:           /* 26   */
 717                         stb0899_write_reg(state, STB0899_DEMAPVIT, 94);
 718                         STB0899_SETFIELD_VAL(BETA, reg, betaTab[4][clnI]);
 719                         stb0899_write_reg(state, STB0899_BCLC, reg);
 720                         break;
 721                 default:
 722                         dprintk(state->verbose, FE_DEBUG, 1, "Unsupported Puncture Rate");
 723                         break;
 724                 }
 725                 /* release stream merger RESET  */
 726                 reg = stb0899_read_reg(state, STB0899_TSTRES);
 727                 STB0899_SETFIELD_VAL(FRESRS, reg, 0);
 728                 stb0899_write_reg(state, STB0899_TSTRES, reg);
 729
 730                 /* disable carrier detector     */
 731                 reg = stb0899_read_reg(state, STB0899_CFD);
 732                 STB0899_SETFIELD_VAL(CFD_ON, reg, 0);
 733                 stb0899_write_reg(state, STB0899_CFD, reg);
 734
 735                 stb0899_read_regs(state, STB0899_EQUAI1, eq_const, 10);
 736         }
 737
 738         return internal->status;
 739 }
 740
 741 /*
 742  * stb0899_dvbs2_config_uwp
 743  * Configure UWP state machine
 744  */
 745 static void stb0899_dvbs2_config_uwp(struct stb0899_state *state)
 746 {
 747         struct stb0899_internal *internal = &state->internal;
 748         struct stb0899_config *config = state->config;
 749         u32 uwp1, uwp2, uwp3, reg;
 750
 751         uwp1 = STB0899_READ_S2REG(STB0899_S2DEMOD, UWP_CNTRL1);
 752         uwp2 = STB0899_READ_S2REG(STB0899_S2DEMOD, UWP_CNTRL2);
 753         uwp3 = STB0899_READ_S2REG(STB0899_S2DEMOD, UWP_CNTRL3);
 754
 755         STB0899_SETFIELD_VAL(UWP_ESN0_AVE, uwp1, config->esno_ave);
 756         STB0899_SETFIELD_VAL(UWP_ESN0_QUANT, uwp1, config->esno_quant);
 757         STB0899_SETFIELD_VAL(UWP_TH_SOF, uwp1, config->uwp_threshold_sof);
 758
 759         STB0899_SETFIELD_VAL(FE_COARSE_TRK, uwp2, internal->av_frame_coarse);
 760         STB0899_SETFIELD_VAL(FE_FINE_TRK, uwp2, internal->av_frame_fine);
 761         STB0899_SETFIELD_VAL(UWP_MISS_TH, uwp2, config->miss_threshold);
 762
 763         STB0899_SETFIELD_VAL(UWP_TH_ACQ, uwp3, config->uwp_threshold_acq);
 764         STB0899_SETFIELD_VAL(UWP_TH_TRACK, uwp3, config->uwp_threshold_track);
 765
 766         stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_UWP_CNTRL1, STB0899_OFF0_UWP_CNTRL1, uwp1);
 767         stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_UWP_CNTRL2, STB0899_OFF0_UWP_CNTRL2, uwp2);
 768         stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_UWP_CNTRL3, STB0899_OFF0_UWP_CNTRL3, uwp3);
 769
 770         reg = STB0899_READ_S2REG(STB0899_S2DEMOD, SOF_SRCH_TO);
 771         STB0899_SETFIELD_VAL(SOF_SEARCH_TIMEOUT, reg, config->sof_search_timeout);
 772         stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_SOF_SRCH_TO, STB0899_OFF0_SOF_SRCH_TO, reg);
 773 }
 774
 775 /*
 776  * stb0899_dvbs2_config_csm_auto
 777  * Set CSM to AUTO mode
 778  */
 779 static void stb0899_dvbs2_config_csm_auto(struct stb0899_state *state)
 780 {
 781         u32 reg;
 782
 783         reg = STB0899_READ_S2REG(STB0899_S2DEMOD, CSM_CNTRL1);
 784         STB0899_SETFIELD_VAL(CSM_AUTO_PARAM, reg, 1);
 785         stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CSM_CNTRL1, STB0899_OFF0_CSM_CNTRL1, reg);
 786 }
 787
 788 long Log2Int(int number)
 789 {
 790         int i;
 791
 792         i = 0;
 793         while ((1 << i) <= ABS(number))
 794                 i++;
 795
 796         if (number == 0)
 797                 i = 1;
 798
 799         return i - 1;
 800 }
 801
 802 /*
 803  * stb0899_dvbs2_calc_srate
 804  * compute BTR_NOM_FREQ for the symbol rate
 805  */
 806 static u32 stb0899_dvbs2_calc_srate(struct stb0899_state *state)
 807 {
 808         struct stb0899_internal *internal       = &state->internal;
 809         struct stb0899_config *config           = state->config;
 810
 811         u32 dec_ratio, dec_rate, decim, remain, intval, btr_nom_freq;
 812         u32 master_clk, srate;
 813
 814         dec_ratio = (internal->master_clk * 2) / (5 * internal->srate);
 815         dec_ratio = (dec_ratio == 0) ? 1 : dec_ratio;
 816         dec_rate = Log2Int(dec_ratio);
 817         decim = 1 << dec_rate;
 818         master_clk = internal->master_clk / 1000;
 819         srate = internal->srate / 1000;
 820
 821         if (decim <= 4) {
 822                 intval = (decim * (1 << (config->btr_nco_bits - 1))) / master_clk;
 823                 remain = (decim * (1 << (config->btr_nco_bits - 1))) % master_clk;
 824         } else {
 825                 intval = (1 << (config->btr_nco_bits - 1)) / (master_clk / 100) * decim / 100;
 826                 remain = (decim * (1 << (config->btr_nco_bits - 1))) % master_clk;
 827         }
 828         btr_nom_freq = (intval * srate) + ((remain * srate) / master_clk);
 829
 830         return btr_nom_freq;
 831 }
 832
 833 /*
 834  * stb0899_dvbs2_calc_dev
 835  * compute the correction to be applied to symbol rate
 836  */
 837 static u32 stb0899_dvbs2_calc_dev(struct stb0899_state *state)
 838 {
 839         struct stb0899_internal *internal = &state->internal;
 840         u32 dec_ratio, correction, master_clk, srate;
 841
 842         dec_ratio = (internal->master_clk * 2) / (5 * internal->srate);
 843         dec_ratio = (dec_ratio == 0) ? 1 : dec_ratio;
 844
 845         master_clk = internal->master_clk / 1000;       /* for integer Caculation*/
 846         srate = internal->srate / 1000; /* for integer Caculation*/
 847         correction = (512 * master_clk) / (2 * dec_ratio * srate);
 848
 849         return  correction;
 850 }
 851
 852 /*
 853  * stb0899_dvbs2_set_srate
 854  * Set DVBS2 symbol rate
 855  */
 856 static void stb0899_dvbs2_set_srate(struct stb0899_state *state)
 857 {
 858         struct stb0899_internal *internal = &state->internal;
 859
 860         u32 dec_ratio, dec_rate, win_sel, decim, f_sym, btr_nom_freq;
 861         u32 correction, freq_adj, band_lim, decim_cntrl, reg;
 862         u8 anti_alias;
 863
 864         /*set decimation to 1*/
 865         dec_ratio = (internal->master_clk * 2) / (5 * internal->srate);
 866         dec_ratio = (dec_ratio == 0) ? 1 : dec_ratio;
 867         dec_rate = Log2Int(dec_ratio);
 868
 869         win_sel = 0;
 870         if (dec_rate >= 5)
 871                 win_sel = dec_rate - 4;
 872
 873         decim = (1 << dec_rate);
 874         /* (FSamp/Fsymbol *100) for integer Caculation */
 875         f_sym = internal->master_clk / ((decim * internal->srate) / 1000);
 876
 877         if (f_sym <= 2250)      /* don't band limit signal going into btr block*/
 878                 band_lim = 1;
 879         else
 880                 band_lim = 0;   /* band limit signal going into btr block*/
 881
 882         decim_cntrl = ((win_sel << 3) & 0x18) + ((band_lim << 5) & 0x20) + (dec_rate & 0x7);
 883         stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_DECIM_CNTRL, STB0899_OFF0_DECIM_CNTRL, decim_cntrl);
 884
 885         if (f_sym <= 3450)
 886                 anti_alias = 0;
 887         else if (f_sym <= 4250)
 888                 anti_alias = 1;
 889         else
 890                 anti_alias = 2;
 891
 892         stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_ANTI_ALIAS_SEL, STB0899_OFF0_ANTI_ALIAS_SEL, anti_alias);
 893         btr_nom_freq = stb0899_dvbs2_calc_srate(state);
 894         stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_BTR_NOM_FREQ, STB0899_OFF0_BTR_NOM_FREQ, btr_nom_freq);
 895
 896         correction = stb0899_dvbs2_calc_dev(state);
 897         reg = STB0899_READ_S2REG(STB0899_S2DEMOD, BTR_CNTRL);
 898         STB0899_SETFIELD_VAL(BTR_FREQ_CORR, reg, correction);
 899         stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_BTR_CNTRL, STB0899_OFF0_BTR_CNTRL, reg);
 900
 901         /* scale UWP+CSM frequency to sample rate*/
 902         freq_adj =  internal->srate / (internal->master_clk / 4096);
 903         stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_FREQ_ADJ_SCALE, STB0899_OFF0_FREQ_ADJ_SCALE, freq_adj);
 904 }
 905
 906 /*
 907  * stb0899_dvbs2_set_btr_loopbw
 908  * set bit timing loop bandwidth as a percentage of the symbol rate
 909  */
 910 static void stb0899_dvbs2_set_btr_loopbw(struct stb0899_state *state)
 911 {
 912         struct stb0899_internal *internal       = &state->internal;
 913         struct stb0899_config *config           = state->config;
 914
 915         u32 sym_peak = 23, zeta = 707, loopbw_percent = 60;
 916         s32 dec_ratio, dec_rate, k_btr1_rshft, k_btr1, k_btr0_rshft;
 917         s32 k_btr0, k_btr2_rshft, k_direct_shift, k_indirect_shift;
 918         u32 decim, K, wn, k_direct, k_indirect;
 919         u32 reg;
 920
 921         dec_ratio = (internal->master_clk * 2) / (5 * internal->srate);
 922         dec_ratio = (dec_ratio == 0) ? 1 : dec_ratio;
 923         dec_rate = Log2Int(dec_ratio);
 924         decim = (1 << dec_rate);
 925
 926         sym_peak *= 576000;
 927         K = (1 << config->btr_nco_bits) / (internal->master_clk / 1000);
 928         K *= (internal->srate / 1000000) * decim; /*k=k 10^-8*/
 929
 930         if (K != 0) {
 931                 K = sym_peak / K;
 932                 wn = (4 * zeta * zeta) + 1000000;
 933                 wn = (2 * (loopbw_percent * 1000) * 40 * zeta) /wn;  /*wn =wn 10^-8*/
 934
 935                 k_indirect = (wn * wn) / K;
 936                 k_indirect = k_indirect;          /*kindirect = kindirect 10^-6*/
 937                 k_direct   = (2 * wn * zeta) / K;       /*kDirect = kDirect 10^-2*/
 938                 k_direct  *= 100;
 939
 940                 k_direct_shift = Log2Int(k_direct) - Log2Int(10000) - 2;
 941                 k_btr1_rshft = (-1 * k_direct_shift) + config->btr_gain_shift_offset;
 942                 k_btr1 = k_direct / (1 << k_direct_shift);
 943                 k_btr1 /= 10000;
 944
 945                 k_indirect_shift = Log2Int(k_indirect + 15) - 20 /*- 2*/;
 946                 k_btr0_rshft = (-1 * k_indirect_shift) + config->btr_gain_shift_offset;
 947                 k_btr0 = k_indirect * (1 << (-k_indirect_shift));
 948                 k_btr0 /= 1000000;
 949
 950                 k_btr2_rshft = 0;
 951                 if (k_btr0_rshft > 15) {
 952                         k_btr2_rshft = k_btr0_rshft - 15;
 953                         k_btr0_rshft = 15;
 954                 }
 955                 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, BTR_LOOP_GAIN);
 956                 STB0899_SETFIELD_VAL(KBTR0_RSHFT, reg, k_btr0_rshft);
 957                 STB0899_SETFIELD_VAL(KBTR0, reg, k_btr0);
 958                 STB0899_SETFIELD_VAL(KBTR1_RSHFT, reg, k_btr1_rshft);
 959                 STB0899_SETFIELD_VAL(KBTR1, reg, k_btr1);
 960                 STB0899_SETFIELD_VAL(KBTR2_RSHFT, reg, k_btr2_rshft);
 961                 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_BTR_LOOP_GAIN, STB0899_OFF0_BTR_LOOP_GAIN, reg);
 962         } else
 963                 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_BTR_LOOP_GAIN, STB0899_OFF0_BTR_LOOP_GAIN, 0xc4c4f);
 964 }
 965
 966 /*
 967  * stb0899_dvbs2_set_carr_freq
 968  * set nominal frequency for carrier search
 969  */
 970 static void stb0899_dvbs2_set_carr_freq(struct stb0899_state *state, s32 carr_freq, u32 master_clk)
 971 {
 972         struct stb0899_config *config = state->config;
 973         s32 crl_nom_freq;
 974         u32 reg;
 975
 976         crl_nom_freq = (1 << config->crl_nco_bits) / master_clk;
 977         crl_nom_freq *= carr_freq;
 978         reg = STB0899_READ_S2REG(STB0899_S2DEMOD, CRL_NOM_FREQ);
 979         STB0899_SETFIELD_VAL(CRL_NOM_FREQ, reg, crl_nom_freq);
 980         stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CRL_NOM_FREQ, STB0899_OFF0_CRL_NOM_FREQ, reg);
 981 }
 982
 983 /*
 984  * stb0899_dvbs2_init_calc
 985  * Initialize DVBS2 UWP, CSM, carrier and timing loops
 986  */
 987 static void stb0899_dvbs2_init_calc(struct stb0899_state *state)
 988 {
 989         struct stb0899_internal *internal = &state->internal;
 990         s32 steps, step_size;
 991         u32 range, reg;
 992
 993         /* config uwp and csm */
 994         stb0899_dvbs2_config_uwp(state);
 995         stb0899_dvbs2_config_csm_auto(state);
 996
 997         /* initialize BTR       */
 998         stb0899_dvbs2_set_srate(state);
 999         stb0899_dvbs2_set_btr_loopbw(state);
1000
1001         if (internal->srate / 1000000 >= 15)
1002                 step_size = (1 << 17) / 5;
1003         else if (internal->srate / 1000000 >= 10)
1004                 step_size = (1 << 17) / 7;
1005         else if (internal->srate / 1000000 >= 5)
1006                 step_size = (1 << 17) / 10;
1007         else
1008                 step_size = (1 << 17) / 4;
1009
1010         range = internal->srch_range / 1000000;
1011         steps = (10 * range * (1 << 17)) / (step_size * (internal->srate / 1000000));
1012         steps = (steps + 6) / 10;
1013         steps = (steps == 0) ? 1 : steps;
1014         if (steps % 2 == 0)
1015                 stb0899_dvbs2_set_carr_freq(state, internal->center_freq -
1016                                            (internal->step_size * (internal->srate / 20000000)),
1017                                            (internal->master_clk) / 1000000);
1018         else
1019                 stb0899_dvbs2_set_carr_freq(state, internal->center_freq, (internal->master_clk) / 1000000);
1020
1021         /*Set Carrier Search params (zigzag, num steps and freq step size*/
1022         reg = STB0899_READ_S2REG(STB0899_S2DEMOD, ACQ_CNTRL2);
1023         STB0899_SETFIELD_VAL(ZIGZAG, reg, 1);
1024         STB0899_SETFIELD_VAL(NUM_STEPS, reg, steps);
1025         STB0899_SETFIELD_VAL(FREQ_STEPSIZE, reg, step_size);
1026         stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_ACQ_CNTRL2, STB0899_OFF0_ACQ_CNTRL2, reg);
1027 }
1028
1029 /*
1030  * stb0899_dvbs2_btr_init
1031  * initialize the timing loop
1032  */
1033 static void stb0899_dvbs2_btr_init(struct stb0899_state *state)
1034 {
1035         u32 reg;
1036
1037         /* set enable BTR loopback      */
1038         reg = STB0899_READ_S2REG(STB0899_S2DEMOD, BTR_CNTRL);
1039         STB0899_SETFIELD_VAL(INTRP_PHS_SENSE, reg, 1);
1040         STB0899_SETFIELD_VAL(BTR_ERR_ENA, reg, 1);
1041         stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_BTR_CNTRL, STB0899_OFF0_BTR_CNTRL, reg);
1042
1043         /* fix btr freq accum at 0      */
1044         stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_BTR_FREQ_INIT, STB0899_OFF0_BTR_FREQ_INIT, 0x10000000);
1045         stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_BTR_FREQ_INIT, STB0899_OFF0_BTR_FREQ_INIT, 0x00000000);
1046
1047         /* fix btr freq accum at 0      */
1048         stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_BTR_PHS_INIT, STB0899_OFF0_BTR_PHS_INIT, 0x10000000);
1049         stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_BTR_PHS_INIT, STB0899_OFF0_BTR_PHS_INIT, 0x00000000);
1050 }
1051
1052 /*
1053  * stb0899_dvbs2_reacquire
1054  * trigger a DVB-S2 acquisition
1055  */
1056 static void stb0899_dvbs2_reacquire(struct stb0899_state *state)
1057 {
1058         u32 reg = 0;
1059
1060         /* demod soft reset     */
1061         STB0899_SETFIELD_VAL(DVBS2_RESET, reg, 1);
1062         stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_RESET_CNTRL, STB0899_OFF0_RESET_CNTRL, reg);
1063
1064         /*Reset Timing Loop     */
1065         stb0899_dvbs2_btr_init(state);
1066
1067         /* reset Carrier loop   */
1068         stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CRL_FREQ_INIT, STB0899_OFF0_CRL_FREQ_INIT, (1 << 30));
1069         stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CRL_FREQ_INIT, STB0899_OFF0_CRL_FREQ_INIT, 0);
1070         stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CRL_LOOP_GAIN, STB0899_OFF0_CRL_LOOP_GAIN, 0);
1071         stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CRL_PHS_INIT, STB0899_OFF0_CRL_PHS_INIT, (1 << 30));
1072         stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CRL_PHS_INIT, STB0899_OFF0_CRL_PHS_INIT, 0);
1073
1074         /*release demod soft reset      */
1075         reg = 0;
1076         STB0899_SETFIELD_VAL(DVBS2_RESET, reg, 0);
1077         stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_RESET_CNTRL, STB0899_OFF0_RESET_CNTRL, reg);
1078
1079         /* start acquisition process    */
1080         stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_ACQUIRE_TRIG, STB0899_OFF0_ACQUIRE_TRIG, 1);
1081         stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_LOCK_LOST, STB0899_OFF0_LOCK_LOST, 0);
1082
1083         /* equalizer Init       */
1084         stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_EQUALIZER_INIT, STB0899_OFF0_EQUALIZER_INIT, 1);
1085
1086         /*Start equilizer       */
1087         stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_EQUALIZER_INIT, STB0899_OFF0_EQUALIZER_INIT, 0);
1088
1089         reg = STB0899_READ_S2REG(STB0899_S2DEMOD, EQ_CNTRL);
1090         STB0899_SETFIELD_VAL(EQ_SHIFT, reg, 0);
1091         STB0899_SETFIELD_VAL(EQ_DISABLE_UPDATE, reg, 0);
1092         STB0899_SETFIELD_VAL(EQ_DELAY, reg, 0x05);
1093         STB0899_SETFIELD_VAL(EQ_ADAPT_MODE, reg, 0x01);
1094         stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_EQ_CNTRL, STB0899_OFF0_EQ_CNTRL, reg);
1095
1096         /* RESET Packet delineator      */
1097         stb0899_write_reg(state, STB0899_PDELCTRL, 0x4a);
1098 }
1099
1100 /*
1101  * stb0899_dvbs2_get_dmd_status
1102  * get DVB-S2 Demod LOCK status
1103  */
1104 static enum stb0899_status stb0899_dvbs2_get_dmd_status(struct stb0899_state *state, int timeout)
1105 {
1106         int time = -10, lock = 0, uwp, csm;
1107         u32 reg;
1108
1109         do {
1110                 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, DMD_STATUS);
1111                 dprintk(state->verbose, FE_DEBUG, 1, "DMD_STATUS=[0x%02x]", reg);
1112                 if (STB0899_GETFIELD(IF_AGC_LOCK, reg))
1113                         dprintk(state->verbose, FE_DEBUG, 1, "------------->IF AGC LOCKED !");
1114                 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, DMD_STAT2);
1115                 dprintk(state->verbose, FE_DEBUG, 1, "----------->DMD STAT2=[0x%02x]", reg);
1116                 uwp = STB0899_GETFIELD(UWP_LOCK, reg);
1117                 csm = STB0899_GETFIELD(CSM_LOCK, reg);
1118                 if (uwp && csm)
1119                         lock = 1;
1120
1121                 time += 10;
1122                 msleep(10);
1123
1124         } while ((!lock) && (time <= timeout));
1125
1126         if (lock) {
1127                 dprintk(state->verbose, FE_DEBUG, 1, "----------------> DVB-S2 LOCK !");
1128                 return DVBS2_DEMOD_LOCK;
1129         } else {
1130                 return DVBS2_DEMOD_NOLOCK;
1131         }
1132 }
1133
1134 /*
1135  * stb0899_dvbs2_get_data_lock
1136  * get FEC status
1137  */
1138 static int stb0899_dvbs2_get_data_lock(struct stb0899_state *state, int timeout)
1139 {
1140         int time = 0, lock = 0;
1141         u8 reg;
1142
1143         while ((!lock) && (time < timeout)) {
1144                 reg = stb0899_read_reg(state, STB0899_CFGPDELSTATUS1);
1145                 dprintk(state->verbose, FE_DEBUG, 1, "---------> CFGPDELSTATUS=[0x%02x]", reg);
1146                 lock = STB0899_GETFIELD(CFGPDELSTATUS_LOCK, reg);
1147                 time++;
1148         }
1149
1150         return lock;
1151 }
1152
1153 /*
1154  * stb0899_dvbs2_get_fec_status
1155  * get DVB-S2 FEC LOCK status
1156  */
1157 static enum stb0899_status stb0899_dvbs2_get_fec_status(struct stb0899_state *state, int timeout)
1158 {
1159         int time = 0, Locked;
1160
1161         do {
1162                 Locked = stb0899_dvbs2_get_data_lock(state, 1);
1163                 time++;
1164                 msleep(1);
1165
1166         } while ((!Locked) && (time < timeout));
1167
1168         if (Locked) {
1169                 dprintk(state->verbose, FE_DEBUG, 1, "---------->DVB-S2 FEC LOCK !");
1170                 return DVBS2_FEC_LOCK;
1171         } else {
1172                 return DVBS2_FEC_NOLOCK;
1173         }
1174 }
1175
1176
1177 /*
1178  * stb0899_dvbs2_init_csm
1179  * set parameters for manual mode
1180  */
1181 static void stb0899_dvbs2_init_csm(struct stb0899_state *state, int pilots, enum stb0899_modcod modcod)
1182 {
1183         struct stb0899_internal *internal = &state->internal;
1184
1185         s32 dvt_tbl = 1, two_pass = 0, agc_gain = 6, agc_shift = 0, loop_shift = 0, phs_diff_thr = 0x80;
1186         s32 gamma_acq, gamma_rho_acq, gamma_trk, gamma_rho_trk, lock_count_thr;
1187         u32 csm1, csm2, csm3, csm4;
1188
1189         if (((internal->master_clk / internal->srate) <= 4) && (modcod <= 11) && (pilots == 1)) {
1190                 switch (modcod) {
1191                 case STB0899_QPSK_12:
1192                         gamma_acq               = 25;
1193                         gamma_rho_acq           = 2700;
1194                         gamma_trk               = 12;
1195                         gamma_rho_trk           = 180;
1196                         lock_count_thr          = 8;
1197                         break;
1198                 case STB0899_QPSK_35:
1199                         gamma_acq               = 38;
1200                         gamma_rho_acq           = 7182;
1201                         gamma_trk               = 14;
1202                         gamma_rho_trk           = 308;
1203                         lock_count_thr          = 8;
1204                         break;
1205                 case STB0899_QPSK_23:
1206                         gamma_acq               = 42;
1207                         gamma_rho_acq           = 9408;
1208                         gamma_trk               = 17;
1209                         gamma_rho_trk           = 476;
1210                         lock_count_thr          = 8;
1211                         break;
1212                 case STB0899_QPSK_34:
1213                         gamma_acq               = 53;
1214                         gamma_rho_acq           = 16642;
1215                         gamma_trk               = 19;
1216                         gamma_rho_trk           = 646;
1217                         lock_count_thr          = 8;
1218                         break;
1219                 case STB0899_QPSK_45:
1220                         gamma_acq               = 53;
1221                         gamma_rho_acq           = 17119;
1222                         gamma_trk               = 22;
1223                         gamma_rho_trk           = 880;
1224                         lock_count_thr          = 8;
1225                         break;
1226                 case STB0899_QPSK_56:
1227                         gamma_acq               = 55;
1228                         gamma_rho_acq           = 19250;
1229                         gamma_trk               = 23;
1230                         gamma_rho_trk           = 989;
1231                         lock_count_thr          = 8;
1232                         break;
1233                 case STB0899_QPSK_89:
1234                         gamma_acq               = 60;
1235                         gamma_rho_acq           = 24240;
1236                         gamma_trk               = 24;
1237                         gamma_rho_trk           = 1176;
1238                         lock_count_thr          = 8;
1239                         break;
1240                 case STB0899_QPSK_910:
1241                         gamma_acq               = 66;
1242                         gamma_rho_acq           = 29634;
1243                         gamma_trk               = 24;
1244                         gamma_rho_trk           = 1176;
1245                         lock_count_thr          = 8;
1246                         break;
1247                 default:
1248                         gamma_acq               = 66;
1249                         gamma_rho_acq           = 29634;
1250                         gamma_trk               = 24;
1251                         gamma_rho_trk           = 1176;
1252                         lock_count_thr          = 8;
1253                         break;
1254                 }
1255
1256                 csm1 = STB0899_READ_S2REG(STB0899_S2DEMOD, CSM_CNTRL1);
1257                 STB0899_SETFIELD_VAL(CSM_AUTO_PARAM, csm1, 0);
1258                 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CSM_CNTRL1, STB0899_OFF0_CSM_CNTRL1, csm1);
1259
1260                 csm1 = STB0899_READ_S2REG(STB0899_S2DEMOD, CSM_CNTRL1);
1261                 csm2 = STB0899_READ_S2REG(STB0899_S2DEMOD, CSM_CNTRL2);
1262                 csm3 = STB0899_READ_S2REG(STB0899_S2DEMOD, CSM_CNTRL3);
1263                 csm4 = STB0899_READ_S2REG(STB0899_S2DEMOD, CSM_CNTRL4);
1264
1265                 STB0899_SETFIELD_VAL(CSM_DVT_TABLE, csm1, dvt_tbl);
1266                 STB0899_SETFIELD_VAL(CSM_TWO_PASS, csm1, two_pass);
1267                 STB0899_SETFIELD_VAL(CSM_AGC_GAIN, csm1, agc_gain);
1268                 STB0899_SETFIELD_VAL(CSM_AGC_SHIFT, csm1, agc_shift);
1269                 STB0899_SETFIELD_VAL(FE_LOOP_SHIFT, csm1, loop_shift);
1270                 STB0899_SETFIELD_VAL(CSM_GAMMA_ACQ, csm2, gamma_acq);
1271                 STB0899_SETFIELD_VAL(CSM_GAMMA_RHOACQ, csm2, gamma_rho_acq);
1272                 STB0899_SETFIELD_VAL(CSM_GAMMA_TRACK, csm3, gamma_trk);
1273                 STB0899_SETFIELD_VAL(CSM_GAMMA_RHOTRACK, csm3, gamma_rho_trk);
1274                 STB0899_SETFIELD_VAL(CSM_LOCKCOUNT_THRESH, csm4, lock_count_thr);
1275                 STB0899_SETFIELD_VAL(CSM_PHASEDIFF_THRESH, csm4, phs_diff_thr);
1276
1277                 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CSM_CNTRL1, STB0899_OFF0_CSM_CNTRL1, csm1);
1278                 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CSM_CNTRL2, STB0899_OFF0_CSM_CNTRL2, csm2);
1279                 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CSM_CNTRL3, STB0899_OFF0_CSM_CNTRL3, csm3);
1280                 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CSM_CNTRL4, STB0899_OFF0_CSM_CNTRL4, csm4);
1281         }
1282 }
1283
1284 /*
1285  * stb0899_dvbs2_get_srate
1286  * get DVB-S2 Symbol Rate
1287  */
1288 static u32 stb0899_dvbs2_get_srate(struct stb0899_state *state)
1289 {
1290         struct stb0899_internal *internal = &state->internal;
1291         struct stb0899_config *config = state->config;
1292
1293         u32 bTrNomFreq, srate, decimRate, intval1, intval2, reg;
1294         int div1, div2, rem1, rem2;
1295
1296         div1 = config->btr_nco_bits / 2;
1297         div2 = config->btr_nco_bits - div1 - 1;
1298
1299         bTrNomFreq = STB0899_READ_S2REG(STB0899_S2DEMOD, BTR_NOM_FREQ);
1300
1301         reg = STB0899_READ_S2REG(STB0899_S2DEMOD, DECIM_CNTRL);
1302         decimRate = STB0899_GETFIELD(DECIM_RATE, reg);
1303         decimRate = (1 << decimRate);
1304
1305         intval1 = internal->master_clk / (1 << div1);
1306         intval2 = bTrNomFreq / (1 << div2);
1307
1308         rem1 = internal->master_clk % (1 << div1);
1309         rem2 = bTrNomFreq % (1 << div2);
1310         /* only for integer calculation */
1311         srate = (intval1 * intval2) + ((intval1 * rem2) / (1 << div2)) + ((intval2 * rem1) / (1 << div1));
1312         srate /= decimRate;     /*symbrate = (btrnomfreq_register_val*MasterClock)/2^(27+decim_rate_field) */
1313
1314         return  srate;
1315 }
1316
1317 /*
1318  * stb0899_dvbs2_algo
1319  * Search for signal, timing, carrier and data for a given
1320  * frequency in a given range
1321  */
1322 enum stb0899_status stb0899_dvbs2_algo(struct stb0899_state *state)
1323 {
1324         struct stb0899_internal *internal = &state->internal;
1325         enum stb0899_modcod modcod;
1326
1327         s32 offsetfreq, searchTime, FecLockTime, pilots, iqSpectrum;
1328         int i = 0;
1329         u32 reg, csm1;
1330
1331         if (internal->srate <= 2000000) {
1332                 searchTime      = 5000; /* 5000 ms max time to lock UWP and CSM, SYMB <= 2Mbs           */
1333                 FecLockTime     = 350;  /* 350  ms max time to lock FEC, SYMB <= 2Mbs                   */
1334         } else if (internal->srate <= 5000000) {
1335                 searchTime      = 2500; /* 2500 ms max time to lock UWP and CSM, 2Mbs < SYMB <= 5Mbs    */
1336                 FecLockTime     = 170;  /* 170  ms max time to lock FEC, 2Mbs< SYMB <= 5Mbs             */
1337         } else if (internal->srate <= 10000000) {
1338                 searchTime      = 1500; /* 1500 ms max time to lock UWP and CSM, 5Mbs <SYMB <= 10Mbs    */
1339                 FecLockTime     = 80;   /* 80  ms max time to lock FEC, 5Mbs< SYMB <= 10Mbs             */
1340         } else if (internal->srate <= 15000000) {
1341                 searchTime      = 500;  /* 500 ms max time to lock UWP and CSM, 10Mbs <SYMB <= 15Mbs    */
1342                 FecLockTime     = 50;   /* 50  ms max time to lock FEC, 10Mbs< SYMB <= 15Mbs            */
1343         } else if (internal->srate <= 20000000) {
1344                 searchTime      = 300;  /* 300 ms max time to lock UWP and CSM, 15Mbs < SYMB <= 20Mbs   */
1345                 FecLockTime     = 30;   /* 50  ms max time to lock FEC, 15Mbs< SYMB <= 20Mbs            */
1346         } else if (internal->srate <= 25000000) {
1347                 searchTime      = 250;  /* 250 ms max time to lock UWP and CSM, 20 Mbs < SYMB <= 25Mbs  */
1348                 FecLockTime     = 25;   /* 25 ms max time to lock FEC, 20Mbs< SYMB <= 25Mbs             */
1349         } else {
1350                 searchTime      = 150;  /* 150 ms max time to lock UWP and CSM, SYMB > 25Mbs            */
1351                 FecLockTime     = 20;   /* 20 ms max time to lock FEC, 20Mbs< SYMB <= 25Mbs             */
1352         }
1353
1354         /* Maintain Stream Merger in reset during acquisition   */
1355         reg = stb0899_read_reg(state, STB0899_TSTRES);
1356         STB0899_SETFIELD_VAL(FRESRS, reg, 1);
1357         stb0899_write_reg(state, STB0899_TSTRES, reg);
1358
1359         /* Move tuner to frequency      */
1360         if (state->config->tuner_set_frequency)
1361                 state->config->tuner_set_frequency(&state->frontend, internal->freq);
1362         if (state->config->tuner_get_frequency)
1363                 state->config->tuner_get_frequency(&state->frontend, &internal->freq);
1364
1365         /* Set IF AGC to acquisition    */
1366         reg = STB0899_READ_S2REG(STB0899_S2DEMOD, IF_AGC_CNTRL);
1367         STB0899_SETFIELD_VAL(IF_LOOP_GAIN, reg,  4);
1368         STB0899_SETFIELD_VAL(IF_AGC_REF, reg, 32);
1369         stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_IF_AGC_CNTRL, STB0899_OFF0_IF_AGC_CNTRL, reg);
1370
1371         reg = STB0899_READ_S2REG(STB0899_S2DEMOD, IF_AGC_CNTRL2);
1372         STB0899_SETFIELD_VAL(IF_AGC_DUMP_PER, reg, 0);
1373         stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_IF_AGC_CNTRL2, STB0899_OFF0_IF_AGC_CNTRL2, reg);
1374
1375         /* Initialisation       */
1376         stb0899_dvbs2_init_calc(state);
1377
1378         reg = STB0899_READ_S2REG(STB0899_S2DEMOD, DMD_CNTRL2);
1379         switch (internal->inversion) {
1380         case IQ_SWAP_OFF:
1381                 STB0899_SETFIELD_VAL(SPECTRUM_INVERT, reg, 0);
1382                 break;
1383         case IQ_SWAP_ON:
1384                 STB0899_SETFIELD_VAL(SPECTRUM_INVERT, reg, 1);
1385                 break;
1386         case IQ_SWAP_AUTO:      /* use last successful search first     */
1387                 STB0899_SETFIELD_VAL(SPECTRUM_INVERT, reg, 1);
1388                 break;
1389         }
1390         stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_DMD_CNTRL2, STB0899_OFF0_DMD_CNTRL2, reg);
1391         stb0899_dvbs2_reacquire(state);
1392
1393         /* Wait for demod lock (UWP and CSM)    */
1394         internal->status = stb0899_dvbs2_get_dmd_status(state, searchTime);
1395
1396         if (internal->status == DVBS2_DEMOD_LOCK) {
1397                 dprintk(state->verbose, FE_DEBUG, 1, "------------> DVB-S2 DEMOD LOCK !");
1398                 i = 0;
1399                 /* Demod Locked, check FEC status       */
1400                 internal->status = stb0899_dvbs2_get_fec_status(state, FecLockTime);
1401
1402                 /*If false lock (UWP and CSM Locked but no FEC) try 3 time max*/
1403                 while ((internal->status != DVBS2_FEC_LOCK) && (i < 3)) {
1404                         /*      Read the frequency offset*/
1405                         offsetfreq = STB0899_READ_S2REG(STB0899_S2DEMOD, CRL_FREQ);
1406
1407                         /* Set the Nominal frequency to the found frequency offset for the next reacquire*/
1408                         reg = STB0899_READ_S2REG(STB0899_S2DEMOD, CRL_NOM_FREQ);
1409                         STB0899_SETFIELD_VAL(CRL_NOM_FREQ, reg, offsetfreq);
1410                         stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CRL_NOM_FREQ, STB0899_OFF0_CRL_NOM_FREQ, reg);
1411                         stb0899_dvbs2_reacquire(state);
1412                         internal->status = stb0899_dvbs2_get_fec_status(state, searchTime);
1413                         i++;
1414                 }
1415         }
1416
1417         if (internal->status != DVBS2_FEC_LOCK) {
1418                 if (internal->inversion == IQ_SWAP_AUTO) {
1419                         reg = STB0899_READ_S2REG(STB0899_S2DEMOD, DMD_CNTRL2);
1420                         iqSpectrum = STB0899_GETFIELD(SPECTRUM_INVERT, reg);
1421                         /* IQ Spectrum Inversion        */
1422                         STB0899_SETFIELD_VAL(SPECTRUM_INVERT, reg, !iqSpectrum);
1423                         stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_DMD_CNTRL2, STB0899_OFF0_DMD_CNTRL2, reg);
1424                         /* start acquistion process     */
1425                         stb0899_dvbs2_reacquire(state);
1426
1427                         /* Wait for demod lock (UWP and CSM)    */
1428                         internal->status = stb0899_dvbs2_get_dmd_status(state, searchTime);
1429                         if (internal->status == DVBS2_DEMOD_LOCK) {
1430                                 i = 0;
1431                                 /* Demod Locked, check FEC      */
1432                                 internal->status = stb0899_dvbs2_get_fec_status(state, FecLockTime);
1433                                 /*try thrice for false locks, (UWP and CSM Locked but no FEC)   */
1434                                 while ((internal->status != DVBS2_FEC_LOCK) && (i < 3)) {
1435                                         /*      Read the frequency offset*/
1436                                         offsetfreq = STB0899_READ_S2REG(STB0899_S2DEMOD, CRL_FREQ);
1437
1438                                         /* Set the Nominal frequency to the found frequency offset for the next reacquire*/
1439                                         reg = STB0899_READ_S2REG(STB0899_S2DEMOD, CRL_NOM_FREQ);
1440                                         STB0899_SETFIELD_VAL(CRL_NOM_FREQ, reg, offsetfreq);
1441                                         stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CRL_NOM_FREQ, STB0899_OFF0_CRL_NOM_FREQ, reg);
1442
1443                                         stb0899_dvbs2_reacquire(state);
1444                                         internal->status = stb0899_dvbs2_get_fec_status(state, searchTime);
1445                                         i++;
1446                                 }
1447                         }
1448 /*
1449                         if (pParams->DVBS2State == FE_DVBS2_FEC_LOCKED)
1450                                 pParams->IQLocked = !iqSpectrum;
1451 */
1452                 }
1453         }
1454         if (internal->status == DVBS2_FEC_LOCK) {
1455                 dprintk(state->verbose, FE_DEBUG, 1, "----------------> DVB-S2 FEC Lock !");
1456                 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, UWP_STAT2);
1457                 modcod = STB0899_GETFIELD(UWP_DECODE_MOD, reg) >> 2;
1458                 pilots = STB0899_GETFIELD(UWP_DECODE_MOD, reg) & 0x01;
1459
1460                 if ((((10 * internal->master_clk) / (internal->srate / 10)) <= 410) &&
1461                       (INRANGE(STB0899_QPSK_23, modcod, STB0899_QPSK_910)) &&
1462                       (pilots == 1)) {
1463
1464                         stb0899_dvbs2_init_csm(state, pilots, modcod);
1465                         /* Wait for UWP,CSM and data LOCK 20ms max      */
1466                         internal->status = stb0899_dvbs2_get_fec_status(state, FecLockTime);
1467
1468                         i = 0;
1469                         while ((internal->status != DVBS2_FEC_LOCK) && (i < 3)) {
1470                                 csm1 = STB0899_READ_S2REG(STB0899_S2DEMOD, CSM_CNTRL1);
1471                                 STB0899_SETFIELD_VAL(CSM_TWO_PASS, csm1, 1);
1472                                 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CSM_CNTRL1, STB0899_OFF0_CSM_CNTRL1, csm1);
1473                                 csm1 = STB0899_READ_S2REG(STB0899_S2DEMOD, CSM_CNTRL1);
1474                                 STB0899_SETFIELD_VAL(CSM_TWO_PASS, csm1, 0);
1475                                 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CSM_CNTRL1, STB0899_OFF0_CSM_CNTRL1, csm1);
1476
1477                                 internal->status = stb0899_dvbs2_get_fec_status(state, FecLockTime);
1478                                 i++;
1479                         }
1480                 }
1481
1482                 if ((((10 * internal->master_clk) / (internal->srate / 10)) <= 410) &&
1483                       (INRANGE(STB0899_QPSK_12, modcod, STB0899_QPSK_35)) &&
1484                       (pilots == 1)) {
1485
1486                         /* Equalizer Disable update      */
1487                         reg = STB0899_READ_S2REG(STB0899_S2DEMOD, EQ_CNTRL);
1488                         STB0899_SETFIELD_VAL(EQ_DISABLE_UPDATE, reg, 1);
1489                         stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_EQ_CNTRL, STB0899_OFF0_EQ_CNTRL, reg);
1490                 }
1491
1492                 /* slow down the Equalizer once locked  */
1493                 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, EQ_CNTRL);
1494                 STB0899_SETFIELD_VAL(EQ_SHIFT, reg, 0x02);
1495                 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_EQ_CNTRL, STB0899_OFF0_EQ_CNTRL, reg);
1496
1497                 /* Store signal parameters      */
1498                 offsetfreq = STB0899_READ_S2REG(STB0899_S2DEMOD, CRL_FREQ);
1499
1500                 offsetfreq = offsetfreq / ((1 << 30) / 1000);
1501                 offsetfreq *= (internal->master_clk / 1000000);
1502                 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, DMD_CNTRL2);
1503                 if (STB0899_GETFIELD(SPECTRUM_INVERT, reg))
1504                         offsetfreq *= -1;
1505
1506                 internal->freq = internal->freq - offsetfreq;
1507                 internal->srate = stb0899_dvbs2_get_srate(state);
1508
1509                 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, UWP_STAT2);
1510                 internal->modcod = STB0899_GETFIELD(UWP_DECODE_MOD, reg) >> 2;
1511                 internal->pilots = STB0899_GETFIELD(UWP_DECODE_MOD, reg) & 0x01;
1512                 internal->frame_length = (STB0899_GETFIELD(UWP_DECODE_MOD, reg) >> 1) & 0x01;
1513
1514                  /* Set IF AGC to tracking      */
1515                 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, IF_AGC_CNTRL);
1516                 STB0899_SETFIELD_VAL(IF_LOOP_GAIN, reg,  3);
1517
1518                 /* if QPSK 1/2,QPSK 3/5 or QPSK 2/3 set IF AGC reference to 16 otherwise 32*/
1519                 if (INRANGE(STB0899_QPSK_12, internal->modcod, STB0899_QPSK_23))
1520                         STB0899_SETFIELD_VAL(IF_AGC_REF, reg, 16);
1521
1522                 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_IF_AGC_CNTRL, STB0899_OFF0_IF_AGC_CNTRL, reg);
1523
1524                 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, IF_AGC_CNTRL2);
1525                 STB0899_SETFIELD_VAL(IF_AGC_DUMP_PER, reg, 7);
1526                 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_IF_AGC_CNTRL2, STB0899_OFF0_IF_AGC_CNTRL2, reg);
1527         }
1528
1529         /* Release Stream Merger Reset          */
1530         reg = stb0899_read_reg(state, STB0899_TSTRES);
1531         STB0899_SETFIELD_VAL(FRESRS, reg, 0);
1532         stb0899_write_reg(state, STB0899_TSTRES, reg);
1533
1534         return internal->status;
1535 }