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V4L/DVB (9375): Add STB0899 support
[linux-2.6-omap-h63xx.git] / drivers / media / dvb / frontends / stb0899_algo.c
1 /*
2         STB0899 Multistandard Frontend driver
3         Copyright (C) Manu Abraham (abraham.manu@gmail.com)
4
5         Copyright (C) ST Microelectronics
6
7         This program is free software; you can redistribute it and/or modify
8         it under the terms of the GNU General Public License as published by
9         the Free Software Foundation; either version 2 of the License, or
10         (at your option) any later version.
11
12         This program is distributed in the hope that it will be useful,
13         but WITHOUT ANY WARRANTY; without even the implied warranty of
14         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15         GNU General Public License for more details.
16
17         You should have received a copy of the GNU General Public License
18         along with this program; if not, write to the Free Software
19         Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20 */
21
22 #include "stb0899_drv.h"
23 #include "stb0899_priv.h"
24 #include "stb0899_reg.h"
25
26 /*
27  * BinaryFloatDiv
28  * float division with integer
29  */
30 static long BinaryFloatDiv(long n1, long n2, int precision)
31 {
32         int i = 0;
33         long result = 0;
34
35         while (i <= precision) {
36                 if (n1 < n2) {
37                         result *= 2;
38                         n1 *= 2;
39                 } else {
40                         result = result * 2 + 1;
41                         n1 = (n1 - n2) * 2;
42                 }
43                 i++;
44         }
45
46         return result;
47 }
48
49 /*
50  * stb0899_calc_srate
51  * Compute symbol rate
52  */
53 static u32 stb0899_calc_srate(u32 master_clk, u8 *sfr)
54 {
55         u32 tmp, tmp2, mclk;
56
57         mclk  =  master_clk / 4096L; /* MasterClock * 10 / 2^20 */
58         tmp  = (((u32) sfr[0] << 12) + ((u32) sfr[1] << 4)) / 16;
59
60         tmp *= mclk;
61         tmp /= 16;
62         tmp2 = ((u32) sfr[2] * mclk) / 256;
63         tmp += tmp2;
64
65         return tmp;
66 }
67
68 /*
69  * stb0899_get_srate
70  * Get the current symbol rate
71  */
72 u32 stb0899_get_srate(struct stb0899_state *state)
73 {
74         struct stb0899_internal *internal = &state->internal;
75         u8 sfr[4];
76
77         stb0899_read_regs(state, STB0899_SFRH, sfr, 3);
78
79         return stb0899_calc_srate(internal->master_clk, sfr);
80 }
81
82 /*
83  * stb0899_set_srate
84  * Set symbol frequency
85  * MasterClock: master clock frequency (hz)
86  * SymbolRate: symbol rate (bauds)
87  * return symbol frequency
88  */
89 static u32 stb0899_set_srate(struct stb0899_state *state, u32 master_clk, u32 srate)
90 {
91         u32 tmp, tmp_up, srate_up;
92         u8 sfr_up[3], sfr[3];
93
94         srate_up = srate;
95         dprintk(state->verbose, FE_DEBUG, 1, "-->");
96         /*
97          * in order to have the maximum precision, the symbol rate entered into
98          * the chip is computed as the closest value of the "true value".
99          * In this purpose, the symbol rate value is rounded (1 is added on the bit
100          * below the LSB )
101          */
102         srate_up += (srate_up * 3) / 100;
103
104         tmp = BinaryFloatDiv(srate, master_clk, 20);
105         tmp_up = BinaryFloatDiv(srate_up, master_clk, 20);
106
107         sfr_up[0] = (tmp_up >> 12) & 0xff;
108         sfr_up[1] = (tmp_up >>  4) & 0xff;
109         sfr_up[2] =  tmp_up & 0x0f;
110
111         sfr[0] = (tmp >> 12) & 0xff;
112         sfr[1] = (tmp >>  4) & 0xff;
113         sfr[2] =  tmp & 0x0f;
114
115         stb0899_write_regs(state, STB0899_SFRUPH, sfr_up, 3);
116         stb0899_write_regs(state, STB0899_SFRH, sfr, 3);
117
118         return srate;
119 }
120
121 /*
122  * stb0899_calc_loop_time
123  * Compute the amount of time needed by the timing loop to lock
124  * SymbolRate: Symbol rate
125  * return: timing loop time constant (ms)
126  */
127 static long stb0899_calc_loop_time(long srate)
128 {
129         if (srate > 0)
130                 return (100000 / (srate / 1000));
131         else
132                 return 0;
133 }
134
135 /*
136  * stb0899_calc_derot_time
137  * Compute the amount of time needed by the derotator to lock
138  * SymbolRate: Symbol rate
139  * return: derotator time constant (ms)
140  */
141 static long stb0899_calc_derot_time(long srate)
142 {
143         if (srate > 0)
144                 return (100000 / (srate / 1000));
145         else
146                 return 0;
147 }
148
149 /*
150  * stb0899_carr_width
151  * Compute the width of the carrier
152  * return: width of carrier (kHz or Mhz)
153  */
154 long stb0899_carr_width(struct stb0899_state *state)
155 {
156         struct stb0899_internal *internal = &state->internal;
157
158         return (internal->srate + (internal->srate * internal->rolloff) / 100);
159 }
160
161 /*
162  * stb0899_first_subrange
163  * Compute the first subrange of the search
164  */
165 static void stb0899_first_subrange(struct stb0899_state *state)
166 {
167         struct stb0899_internal *internal       = &state->internal;
168         struct stb0899_params *params           = &state->params;
169         struct stb0899_config *config           =  state->config;
170
171         int range = 0;
172         u32 bandwidth = 0;
173
174         if (config->tuner_get_bandwidth) {
175                 config->tuner_get_bandwidth(&state->frontend, &bandwidth);
176                 range = bandwidth - stb0899_carr_width(state) / 2;
177         }
178
179         if (range > 0)
180                 internal->sub_range = MIN(internal->srch_range, range);
181         else
182                 internal->sub_range = 0;
183
184         internal->freq = params->freq;
185         internal->tuner_offst = 0L;
186         internal->sub_dir = 1;
187 }
188
189 /*
190  * stb0899_check_tmg
191  * check for timing lock
192  * internal.Ttiming: time to wait for loop lock
193  */
194 static enum stb0899_status stb0899_check_tmg(struct stb0899_state *state)
195 {
196         struct stb0899_internal *internal = &state->internal;
197         int lock, timing;
198         u8 reg;
199
200         msleep(internal->t_timing);
201
202         reg = stb0899_read_reg(state, STB0899_RTF);
203         STB0899_SETFIELD_VAL(RTF_TIMING_LOOP_FREQ, reg, 0xf2);
204         stb0899_write_reg(state, STB0899_RTF, reg);
205         reg = stb0899_read_reg(state, STB0899_TLIR);
206         lock = STB0899_GETFIELD(TLIR_TMG_LOCK_IND, reg);
207         timing = stb0899_read_reg(state, STB0899_RTF);
208
209         if (lock >= 42) {
210                 if ((lock > 48) && (timing >= 110)) {
211                         internal->status = ANALOGCARRIER;
212                         dprintk(state->verbose, FE_DEBUG, 1, "-->ANALOG Carrier !");
213                 } else {
214                         internal->status = TIMINGOK;
215                         dprintk(state->verbose, FE_DEBUG, 1, "------->TIMING OK !");
216                 }
217         } else {
218                 internal->status = NOTIMING;
219                 dprintk(state->verbose, FE_DEBUG, 1, "-->NO TIMING !");
220         }
221         return internal->status;
222 }
223
224 /*
225  * stb0899_search_tmg
226  * perform a fs/2 zig-zag to find timing
227  */
228 static enum stb0899_status stb0899_search_tmg(struct stb0899_state *state)
229 {
230         struct stb0899_internal *internal = &state->internal;
231         struct stb0899_params *params = &state->params;
232
233         short int derot_step, derot_freq = 0, derot_limit, next_loop = 3;
234         int index = 0;
235         u8 cfr[2];
236
237         internal->status = NOTIMING;
238
239         /* timing loop computation & symbol rate optimisation   */
240         derot_limit = (internal->sub_range / 2L) / internal->mclk;
241         derot_step = (params->srate / 2L) / internal->mclk;
242
243         while ((stb0899_check_tmg(state) != TIMINGOK) && next_loop) {
244                 index++;
245                 derot_freq += index * internal->direction * derot_step; /* next derot zig zag position  */
246
247                 if (ABS(derot_freq) > derot_limit)
248                         next_loop--;
249
250                 if (next_loop) {
251                         STB0899_SETFIELD_VAL(CFRM, cfr[0], MSB(state->config->inversion * derot_freq));
252                         STB0899_SETFIELD_VAL(CFRL, cfr[1], LSB(state->config->inversion * derot_freq));
253                         stb0899_write_regs(state, STB0899_CFRM, cfr, 2); /* derotator frequency         */
254                 }
255                 internal->direction = -internal->direction;     /* Change zigzag direction              */
256         }
257
258         if (internal->status == TIMINGOK) {
259                 stb0899_read_regs(state, STB0899_CFRM, cfr, 2); /* get derotator frequency              */
260                 internal->derot_freq = state->config->inversion * MAKEWORD16(cfr[0], cfr[1]);
261                 dprintk(state->verbose, FE_DEBUG, 1, "------->TIMING OK ! Derot Freq = %d", internal->derot_freq);
262         }
263
264         return internal->status;
265 }
266
267 /*
268  * stb0899_check_carrier
269  * Check for carrier found
270  */
271 static enum stb0899_status stb0899_check_carrier(struct stb0899_state *state)
272 {
273         struct stb0899_internal *internal = &state->internal;
274         u8 reg;
275
276         msleep(internal->t_derot); /* wait for derotator ok     */
277
278         reg = stb0899_read_reg(state, STB0899_CFD);
279         STB0899_SETFIELD_VAL(CFD_ON, reg, 1);
280         stb0899_write_reg(state, STB0899_RTF, reg);
281
282         reg = stb0899_read_reg(state, STB0899_DSTATUS);
283         dprintk(state->verbose, FE_DEBUG, 1, "--------------------> STB0899_DSTATUS=[0x%02x]", reg);
284         if (STB0899_GETFIELD(CARRIER_FOUND, reg)) {
285                 internal->status = CARRIEROK;
286                 dprintk(state->verbose, FE_DEBUG, 1, "-------------> CARRIEROK !");
287         } else {
288                 internal->status = NOCARRIER;
289                 dprintk(state->verbose, FE_DEBUG, 1, "-------------> NOCARRIER !");
290         }
291
292         return internal->status;
293 }
294
295 /*
296  * stb0899_search_carrier
297  * Search for a QPSK carrier with the derotator
298  */
299 static enum stb0899_status stb0899_search_carrier(struct stb0899_state *state)
300 {
301         struct stb0899_internal *internal = &state->internal;
302
303         short int derot_freq = 0, last_derot_freq = 0, derot_limit, next_loop = 3;
304         int index = 0;
305         u8 cfr[2];
306         u8 reg;
307
308         internal->status = NOCARRIER;
309         derot_limit = (internal->sub_range / 2L) / internal->mclk;
310         derot_freq = internal->derot_freq;
311
312         reg = stb0899_read_reg(state, STB0899_CFD);
313         STB0899_SETFIELD_VAL(CFD_ON, reg, 1);
314         stb0899_write_reg(state, STB0899_RTF, reg);
315
316         do {
317                 dprintk(state->verbose, FE_DEBUG, 1, "Derot Freq=%d, mclk=%d", derot_freq, internal->mclk);
318                 if (stb0899_check_carrier(state) == NOCARRIER) {
319                         index++;
320                         last_derot_freq = derot_freq;
321                         derot_freq += index * internal->direction * internal->derot_step; /* next zig zag derotator position    */
322
323                         if(ABS(derot_freq) > derot_limit)
324                                 next_loop--;
325
326                         if (next_loop) {
327                                 reg = stb0899_read_reg(state, STB0899_CFD);
328                                 STB0899_SETFIELD_VAL(CFD_ON, reg, 1);
329                                 stb0899_write_reg(state, STB0899_RTF, reg);
330
331                                 STB0899_SETFIELD_VAL(CFRM, cfr[0], MSB(state->config->inversion * derot_freq));
332                                 STB0899_SETFIELD_VAL(CFRL, cfr[1], LSB(state->config->inversion * derot_freq));
333                                 stb0899_write_regs(state, STB0899_CFRM, cfr, 2); /* derotator frequency */
334                         }
335                 }
336
337                 internal->direction = -internal->direction; /* Change zigzag direction  */
338         } while ((internal->status != CARRIEROK) && next_loop);
339
340         if (internal->status == CARRIEROK) {
341                 stb0899_read_regs(state, STB0899_CFRM, cfr, 2); /* get derotator frequency      */
342                 internal->derot_freq = state->config->inversion * MAKEWORD16(cfr[0], cfr[1]);
343                 dprintk(state->verbose, FE_DEBUG, 1, "----> CARRIER OK !, Derot Freq=%d", internal->derot_freq);
344         } else {
345                 internal->derot_freq = last_derot_freq;
346         }
347
348         return internal->status;
349 }
350
351 /*
352  * stb0899_check_data
353  * Check for data found
354  */
355 static enum stb0899_status stb0899_check_data(struct stb0899_state *state)
356 {
357         struct stb0899_internal *internal = &state->internal;
358         struct stb0899_params *params = &state->params;
359
360         int lock = 0, index = 0, dataTime = 500, loop;
361         u8 reg;
362
363         internal->status = NODATA;
364
365         /* RESET FEC    */
366         reg = stb0899_read_reg(state, STB0899_TSTRES);
367         STB0899_SETFIELD_VAL(FRESACS, reg, 1);
368         stb0899_write_reg(state, STB0899_TSTRES, reg);
369         msleep(1);
370         reg = stb0899_read_reg(state, STB0899_TSTRES);
371         STB0899_SETFIELD_VAL(FRESACS, reg, 0);
372         stb0899_write_reg(state, STB0899_TSTRES, reg);
373
374         if (params->srate <= 2000000)
375                 dataTime = 2000;
376         else if (params->srate <= 5000000)
377                 dataTime = 1500;
378         else if (params->srate <= 15000000)
379                 dataTime = 1000;
380         else
381                 dataTime = 500;
382
383         stb0899_write_reg(state, STB0899_DSTATUS2, 0x00); /* force search loop  */
384         while (1) {
385                 /* WARNING! VIT LOCKED has to be tested before VIT_END_LOOOP    */
386                 reg = stb0899_read_reg(state, STB0899_VSTATUS);
387                 lock = STB0899_GETFIELD(VSTATUS_LOCKEDVIT, reg);
388                 loop = STB0899_GETFIELD(VSTATUS_END_LOOPVIT, reg);
389
390                 if (lock || loop || (index > dataTime))
391                         break;
392                 index++;
393         }
394
395         if (lock) {     /* DATA LOCK indicator  */
396                 internal->status = DATAOK;
397                 dprintk(state->verbose, FE_DEBUG, 1, "-----------------> DATA OK !");
398         }
399
400         return internal->status;
401 }
402
403 /*
404  * stb0899_search_data
405  * Search for a QPSK carrier with the derotator
406  */
407 static enum stb0899_status stb0899_search_data(struct stb0899_state *state)
408 {
409         short int derot_freq, derot_step, derot_limit, next_loop = 3;
410         u8 cfr[2];
411         u8 reg;
412         int index = 1;
413
414         struct stb0899_internal *internal = &state->internal;
415         struct stb0899_params *params = &state->params;
416
417         derot_step = (params->srate / 4L) / internal->mclk;
418         derot_limit = (internal->sub_range / 2L) / internal->mclk;
419         derot_freq = internal->derot_freq;
420
421         do {
422                 if ((internal->status != CARRIEROK) || (stb0899_check_data(state) != DATAOK)) {
423
424                         derot_freq += index * internal->direction * derot_step; /* next zig zag derotator position      */
425                         if (ABS(derot_freq) > derot_limit)
426                                 next_loop--;
427
428                         if (next_loop) {
429                                 dprintk(state->verbose, FE_DEBUG, 1, "Derot freq=%d, mclk=%d", derot_freq, internal->mclk);
430                                 reg = stb0899_read_reg(state, STB0899_CFD);
431                                 STB0899_SETFIELD_VAL(CFD_ON, reg, 1);
432                                 stb0899_write_reg(state, STB0899_RTF, reg);
433
434                                 STB0899_SETFIELD_VAL(CFRM, cfr[0], MSB(state->config->inversion * derot_freq));
435                                 STB0899_SETFIELD_VAL(CFRL, cfr[1], LSB(state->config->inversion * derot_freq));
436                                 stb0899_write_regs(state, STB0899_CFRM, cfr, 2); /* derotator frequency */
437
438                                 stb0899_check_carrier(state);
439                                 index++;
440                         }
441                 }
442                 internal->direction = -internal->direction; /* change zig zag direction         */
443         } while ((internal->status != DATAOK) && next_loop);
444
445         if (internal->status == DATAOK) {
446                 stb0899_read_regs(state, STB0899_CFRM, cfr, 2); /* get derotator frequency      */
447                 internal->derot_freq = state->config->inversion * MAKEWORD16(cfr[0], cfr[1]);
448                 dprintk(state->verbose, FE_DEBUG, 1, "------> DATAOK ! Derot Freq=%d", internal->derot_freq);
449         }
450
451         return internal->status;
452 }
453
454 /*
455  * stb0899_check_range
456  * check if the found frequency is in the correct range
457  */
458 static enum stb0899_status stb0899_check_range(struct stb0899_state *state)
459 {
460         struct stb0899_internal *internal = &state->internal;
461         struct stb0899_params *params = &state->params;
462
463         int range_offst, tp_freq;
464
465         range_offst = internal->srch_range / 2000;
466         tp_freq = internal->freq + (internal->derot_freq * internal->mclk) / 1000;
467
468         if ((tp_freq >= params->freq - range_offst) && (tp_freq <= params->freq + range_offst)) {
469                 internal->status = RANGEOK;
470                 dprintk(state->verbose, FE_DEBUG, 1, "----> RANGEOK !");
471         } else {
472                 internal->status = OUTOFRANGE;
473                 dprintk(state->verbose, FE_DEBUG, 1, "----> OUT OF RANGE !");
474         }
475
476         return internal->status;
477 }
478
479 /*
480  * NextSubRange
481  * Compute the next subrange of the search
482  */
483 static void next_sub_range(struct stb0899_state *state)
484 {
485         struct stb0899_internal *internal = &state->internal;
486         struct stb0899_params *params = &state->params;
487
488         long old_sub_range;
489
490         if (internal->sub_dir > 0) {
491                 old_sub_range = internal->sub_range;
492                 internal->sub_range = MIN((internal->srch_range / 2) -
493                                           (internal->tuner_offst + internal->sub_range / 2),
494                                            internal->sub_range);
495
496                 if (internal->sub_range < 0)
497                         internal->sub_range = 0;
498
499                 internal->tuner_offst += (old_sub_range + internal->sub_range) / 2;
500         }
501
502         internal->freq = params->freq + (internal->sub_dir * internal->tuner_offst) / 1000;
503         internal->sub_dir = -internal->sub_dir;
504 }
505
506 /*
507  * stb0899_dvbs_algo
508  * Search for a signal, timing, carrier and data for a
509  * given frequency in a given range
510  */
511 enum stb0899_status stb0899_dvbs_algo(struct stb0899_state *state)
512 {
513         struct stb0899_params *params           = &state->params;
514         struct stb0899_internal *internal       = &state->internal;
515         struct stb0899_config *config           = state->config;
516
517         u8 bclc, reg;
518         u8 cfr[1];
519         u8 eq_const[10];
520         s32 clnI = 3;
521         u32 bandwidth = 0;
522
523         /* BETA values rated @ 99MHz    */
524         s32 betaTab[5][4] = {
525                /*  5   10   20   30MBps */
526                 { 37,  34,  32,  31 }, /* QPSK 1/2      */
527                 { 37,  35,  33,  31 }, /* QPSK 2/3      */
528                 { 37,  35,  33,  31 }, /* QPSK 3/4      */
529                 { 37,  36,  33,  32 }, /* QPSK 5/6      */
530                 { 37,  36,  33,  32 }  /* QPSK 7/8      */
531         };
532
533         internal->direction = 1;
534
535         stb0899_set_srate(state, internal->master_clk, params->srate);
536         /* Carrier loop optimization versus symbol rate for acquisition*/
537         if (params->srate <= 5000000) {
538                 stb0899_write_reg(state, STB0899_ACLC, 0x89);
539                 bclc = stb0899_read_reg(state, STB0899_BCLC);
540                 STB0899_SETFIELD_VAL(BETA, bclc, 0x1c);
541                 stb0899_write_reg(state, STB0899_BCLC, bclc);
542                 clnI = 0;
543         } else if (params->srate <= 15000000) {
544                 stb0899_write_reg(state, STB0899_ACLC, 0xc9);
545                 bclc = stb0899_read_reg(state, STB0899_BCLC);
546                 STB0899_SETFIELD_VAL(BETA, bclc, 0x22);
547                 stb0899_write_reg(state, STB0899_BCLC, bclc);
548                 clnI = 1;
549         } else if(params->srate <= 25000000) {
550                 stb0899_write_reg(state, STB0899_ACLC, 0x89);
551                 bclc = stb0899_read_reg(state, STB0899_BCLC);
552                 STB0899_SETFIELD_VAL(BETA, bclc, 0x27);
553                 stb0899_write_reg(state, STB0899_BCLC, bclc);
554                 clnI = 2;
555         } else {
556                 stb0899_write_reg(state, STB0899_ACLC, 0xc8);
557                 bclc = stb0899_read_reg(state, STB0899_BCLC);
558                 STB0899_SETFIELD_VAL(BETA, bclc, 0x29);
559                 stb0899_write_reg(state, STB0899_BCLC, bclc);
560                 clnI = 3;
561         }
562
563         dprintk(state->verbose, FE_DEBUG, 1, "Set the timing loop to acquisition");
564         /* Set the timing loop to acquisition   */
565         stb0899_write_reg(state, STB0899_RTC, 0x46);
566         stb0899_write_reg(state, STB0899_CFD, 0xee);
567
568         /* !! WARNING !!
569          * Do not read any status variables while acquisition,
570          * If any needed, read before the acquisition starts
571          * querying status while acquiring causes the
572          * acquisition to go bad and hence no locks.
573          */
574         dprintk(state->verbose, FE_DEBUG, 1, "Derot Percent=%d Srate=%d mclk=%d",
575                 internal->derot_percent, params->srate, internal->mclk);
576
577         /* Initial calculations */
578         internal->derot_step = internal->derot_percent * (params->srate / 1000L) / internal->mclk; /* DerotStep/1000 * Fsymbol  */
579         internal->t_timing = stb0899_calc_loop_time(params->srate);
580         internal->t_derot = stb0899_calc_derot_time(params->srate);
581         internal->t_data = 500;
582
583         dprintk(state->verbose, FE_DEBUG, 1, "RESET stream merger");
584         /* RESET Stream merger  */
585         reg = stb0899_read_reg(state, STB0899_TSTRES);
586         STB0899_SETFIELD_VAL(FRESRS, reg, 1);
587         stb0899_write_reg(state, STB0899_TSTRES, reg);
588
589         /*
590          * Set KDIVIDER to an intermediate value between
591          * 1/2 and 7/8 for acquisition
592          */
593         reg = stb0899_read_reg(state, STB0899_DEMAPVIT);
594         STB0899_SETFIELD_VAL(DEMAPVIT_KDIVIDER, reg, 60);
595         stb0899_write_reg(state, STB0899_DEMAPVIT, reg);
596
597         stb0899_write_reg(state, STB0899_EQON, 0x01); /* Equalizer OFF while acquiring  */
598         stb0899_write_reg(state, STB0899_VITSYNC, 0x19);
599
600         stb0899_first_subrange(state);
601         do {
602                 /* Initialisations      */
603                 cfr[0] = cfr[1] = 0;
604                 stb0899_write_regs(state, STB0899_CFRM, cfr, 2); /* RESET derotator frequency   */
605
606                 reg = stb0899_read_reg(state, STB0899_RTF);
607                 STB0899_SETFIELD_VAL(RTF_TIMING_LOOP_FREQ, reg, 0);
608                 stb0899_write_reg(state, STB0899_RTF, reg);
609                 reg = stb0899_read_reg(state, STB0899_CFD);
610                 STB0899_SETFIELD_VAL(CFD_ON, reg, 1);
611                 stb0899_write_reg(state, STB0899_RTF, reg);
612
613                 internal->derot_freq = 0;
614                 internal->status = NOAGC1;
615
616                 /* Move tuner to frequency      */
617                 dprintk(state->verbose, FE_DEBUG, 1, "Tuner set frequency");
618                 if (state->config->tuner_set_frequency)
619                         state->config->tuner_set_frequency(&state->frontend, internal->freq);
620
621                 msleep(100);
622
623                 if (state->config->tuner_get_frequency)
624                         state->config->tuner_get_frequency(&state->frontend, &internal->freq);
625
626                 msleep(internal->t_agc1 + internal->t_agc2 + internal->t_timing); /* AGC1, AGC2 and timing loop */
627                 dprintk(state->verbose, FE_DEBUG, 1, "current derot freq=%d", internal->derot_freq);
628                 internal->status = AGC1OK;
629
630                 /* There is signal in the band  */
631                 if (config->tuner_get_bandwidth)
632                         config->tuner_get_bandwidth(&state->frontend, &bandwidth);
633                 if (params->srate <= bandwidth / 2)
634                         stb0899_search_tmg(state); /* For low rates (SCPC)      */
635                 else
636                         stb0899_check_tmg(state); /* For high rates (MCPC)      */
637
638                 if (internal->status == TIMINGOK) {
639                         dprintk(state->verbose, FE_DEBUG, 1,
640                                 "TIMING OK ! Derot freq=%d, mclk=%d",
641                                 internal->derot_freq, internal->mclk);
642
643                         if (stb0899_search_carrier(state) == CARRIEROK) {       /* Search for carrier   */
644                                 dprintk(state->verbose, FE_DEBUG, 1,
645                                         "CARRIER OK ! Derot freq=%d, mclk=%d",
646                                         internal->derot_freq, internal->mclk);
647
648                                 if (stb0899_search_data(state) == DATAOK) {     /* Check for data       */
649                                         dprintk(state->verbose, FE_DEBUG, 1,
650                                                 "DATA OK ! Derot freq=%d, mclk=%d",
651                                                 internal->derot_freq, internal->mclk);
652
653                                         if (stb0899_check_range(state) == RANGEOK) {
654                                                 dprintk(state->verbose, FE_DEBUG, 1,
655                                                         "RANGE OK ! derot freq=%d, mclk=%d",
656                                                         internal->derot_freq, internal->mclk);
657
658                                                 internal->freq = params->freq + ((internal->derot_freq * internal->mclk) / 1000);
659                                                 reg = stb0899_read_reg(state, STB0899_PLPARM);
660                                                 internal->fecrate = STB0899_GETFIELD(VITCURPUN, reg);
661                                                 dprintk(state->verbose, FE_DEBUG, 1,
662                                                         "freq=%d, internal resultant freq=%d",
663                                                         params->freq, internal->freq);
664
665                                                 dprintk(state->verbose, FE_DEBUG, 1,
666                                                         "internal puncture rate=%d",
667                                                         internal->fecrate);
668                                         }
669                                 }
670                         }
671                 }
672                 if (internal->status != RANGEOK)
673                         next_sub_range(state);
674
675         } while (internal->sub_range && internal->status != RANGEOK);
676
677         /* Set the timing loop to tracking      */
678         stb0899_write_reg(state, STB0899_RTC, 0x33);
679         stb0899_write_reg(state, STB0899_CFD, 0xf7);
680         reg = 0;
681         /* if locked and range ok, set Kdiv     */
682         if (internal->status == RANGEOK) {
683                 dprintk(state->verbose, FE_DEBUG, 1, "Locked & Range OK !");
684                 stb0899_write_reg(state, STB0899_EQON, 0x41);           /* Equalizer OFF while acquiring        */
685                 stb0899_write_reg(state, STB0899_VITSYNC, 0x39);        /* SN to b'11 for acquisition           */
686
687                 /*
688                  * Carrier loop optimization versus
689                  * symbol Rate/Puncture Rate for Tracking
690                  */
691                 switch (internal->fecrate) {
692                 case STB0899_FEC_1_2:           /* 13   */
693                         STB0899_SETFIELD_VAL(DEMAPVIT_KDIVIDER, reg, 0x1a);
694                         stb0899_write_reg(state, STB0899_DEMAPVIT, reg);
695                         STB0899_SETFIELD_VAL(BETA, reg, betaTab[0][clnI]);
696                         stb0899_write_reg(state, STB0899_BCLC, reg);
697                         break;
698                 case STB0899_FEC_2_3:           /* 18   */
699                         STB0899_SETFIELD_VAL(DEMAPVIT_KDIVIDER, reg, 44);
700                         stb0899_write_reg(state, STB0899_DEMAPVIT, reg);
701                         STB0899_SETFIELD_VAL(BETA, reg, betaTab[1][clnI]);
702                         stb0899_write_reg(state, STB0899_BCLC, reg);
703                         break;
704                 case STB0899_FEC_3_4:           /* 21   */
705                         STB0899_SETFIELD_VAL(DEMAPVIT_KDIVIDER, reg, 60);
706                         stb0899_write_reg(state, STB0899_DEMAPVIT, reg);
707                         STB0899_SETFIELD_VAL(BETA, reg, betaTab[2][clnI]);
708                         stb0899_write_reg(state, STB0899_BCLC, reg);
709                         break;
710                 case STB0899_FEC_5_6:           /* 24   */
711                         STB0899_SETFIELD_VAL(DEMAPVIT_KDIVIDER, reg, 75);
712                         stb0899_write_reg(state, STB0899_DEMAPVIT, reg);
713                         STB0899_SETFIELD_VAL(BETA, reg, betaTab[3][clnI]);
714                         stb0899_write_reg(state, STB0899_BCLC, reg);
715                         break;
716                 case STB0899_FEC_6_7:           /* 25   */
717                         STB0899_SETFIELD_VAL(DEMAPVIT_KDIVIDER, reg, 88);
718                         stb0899_write_reg(state, STB0899_DEMAPVIT, reg);
719                         stb0899_write_reg(state, STB0899_ACLC, 0x88);
720                         stb0899_write_reg(state, STB0899_BCLC, 0x9a);
721                         break;
722                 case STB0899_FEC_7_8:           /* 26   */
723                         STB0899_SETFIELD_VAL(DEMAPVIT_KDIVIDER, reg, 94);
724                         stb0899_write_reg(state, STB0899_DEMAPVIT, reg);
725                         STB0899_SETFIELD_VAL(BETA, reg, betaTab[4][clnI]);
726                         stb0899_write_reg(state, STB0899_BCLC, reg);
727                         break;
728                 default:
729                         dprintk(state->verbose, FE_DEBUG, 1, "Unsupported Puncture Rate");
730                         break;
731                 }
732                 /* release stream merger RESET  */
733                 reg = stb0899_read_reg(state, STB0899_TSTRES);
734                 STB0899_SETFIELD_VAL(FRESRS, reg, 0);
735                 stb0899_write_reg(state, STB0899_TSTRES, reg);
736
737                 /* disable carrier detector     */
738                 reg = stb0899_read_reg(state, STB0899_CFD);
739                 STB0899_SETFIELD_VAL(CFD_ON, reg, 0);
740                 stb0899_write_reg(state, STB0899_RTF, reg);
741
742                 stb0899_read_regs(state, STB0899_EQUAI1, eq_const, 10);
743         }
744
745         return internal->status;
746 }
747
748 /*
749  * stb0899_dvbs2_config_uwp
750  * Configure UWP state machine
751  */
752 static void stb0899_dvbs2_config_uwp(struct stb0899_state *state)
753 {
754         struct stb0899_internal *internal = &state->internal;
755         struct stb0899_config *config = state->config;
756         u32 uwp1, uwp2, uwp3, reg;
757
758         uwp1 = STB0899_READ_S2REG(STB0899_S2DEMOD, UWP_CNTRL1);
759         uwp2 = STB0899_READ_S2REG(STB0899_S2DEMOD, UWP_CNTRL2);
760         uwp3 = STB0899_READ_S2REG(STB0899_S2DEMOD, UWP_CNTRL3);
761
762         STB0899_SETFIELD_VAL(UWP_ESN0_AVE, uwp1, config->esno_ave);
763         STB0899_SETFIELD_VAL(UWP_ESN0_QUANT, uwp1, config->esno_quant);
764         STB0899_SETFIELD_VAL(UWP_TH_SOF, uwp1, config->uwp_threshold_sof);
765
766         STB0899_SETFIELD_VAL(FE_COARSE_TRK, uwp2, internal->av_frame_coarse);
767         STB0899_SETFIELD_VAL(FE_FINE_TRK, uwp2, internal->av_frame_fine);
768         STB0899_SETFIELD_VAL(UWP_MISS_TH, uwp2, config->miss_threshold);
769
770         STB0899_SETFIELD_VAL(UWP_TH_ACQ, uwp3, config->uwp_threshold_acq);
771         STB0899_SETFIELD_VAL(UWP_TH_TRACK, uwp3, config->uwp_threshold_track);
772
773         stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_UWP_CNTRL1, STB0899_OFF0_UWP_CNTRL1, uwp1);
774         stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_UWP_CNTRL2, STB0899_OFF0_UWP_CNTRL2, uwp2);
775         stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_UWP_CNTRL3, STB0899_OFF0_UWP_CNTRL3, uwp3);
776
777         reg = STB0899_READ_S2REG(STB0899_S2DEMOD, SOF_SRCH_TO);
778         STB0899_SETFIELD_VAL(SOF_SEARCH_TIMEOUT, reg, config->sof_search_timeout);
779         stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_SOF_SRCH_TO, STB0899_OFF0_SOF_SRCH_TO, reg);
780 }
781
782 /*
783  * stb0899_dvbs2_config_csm_auto
784  * Set CSM to AUTO mode
785  */
786 static void stb0899_dvbs2_config_csm_auto(struct stb0899_state *state)
787 {
788         u32 reg;
789
790         reg = STB0899_READ_S2REG(STB0899_S2DEMOD, CSM_CNTRL1);
791         STB0899_SETFIELD_VAL(CSM_AUTO_PARAM, reg, 1);
792         stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CSM_CNTRL1, STB0899_OFF0_CSM_CNTRL1, reg);
793 }
794
795 long Log2Int(int number)
796 {
797         int i;
798
799         i = 0;
800         while ((1 << i) <= ABS(number))
801                 i++;
802
803         if (number == 0)
804                 i = 1;
805
806         return i - 1;
807 }
808
809 /*
810  * stb0899_dvbs2_calc_srate
811  * compute BTR_NOM_FREQ for the symbol rate
812  */
813 static u32 stb0899_dvbs2_calc_srate(struct stb0899_state *state)
814 {
815         struct stb0899_internal *internal       = &state->internal;
816         struct stb0899_config *config           = state->config;
817
818         u32 dec_ratio, dec_rate, decim, remain, intval, btr_nom_freq;
819         u32 master_clk, srate;
820
821         dec_ratio = (internal->master_clk * 2) / (5 * internal->srate);
822         dec_ratio = (dec_ratio == 0) ? 1 : dec_ratio;
823         dec_rate = Log2Int(dec_ratio);
824         decim = 1 << dec_rate;
825         master_clk = internal->master_clk / 1000;
826         srate = internal->srate / 1000;
827
828         if (decim <= 4) {
829                 intval = (decim * (1 << (config->btr_nco_bits - 1))) / master_clk;
830                 remain = (decim * (1 << (config->btr_nco_bits - 1))) % master_clk;
831         } else {
832                 intval = (1 << (config->btr_nco_bits - 1)) / (master_clk / 100) * decim / 100;
833                 remain = (decim * (1 << (config->btr_nco_bits - 1))) % master_clk;
834         }
835         btr_nom_freq = (intval * srate) + ((remain * srate) / master_clk);
836
837         return btr_nom_freq;
838 }
839
840 /*
841  * stb0899_dvbs2_calc_dev
842  * compute the correction to be applied to symbol rate
843  */
844 static u32 stb0899_dvbs2_calc_dev(struct stb0899_state *state)
845 {
846         struct stb0899_internal *internal = &state->internal;
847         u32 dec_ratio, correction, master_clk, srate;
848
849         dec_ratio = (internal->master_clk * 2) / (5 * internal->srate);
850         dec_ratio = (dec_ratio == 0) ? 1 : dec_ratio;
851
852         master_clk = internal->master_clk / 1000;       /* for integer Caculation*/
853         srate = internal->srate / 1000; /* for integer Caculation*/
854         correction = (512 * master_clk) / (2 * dec_ratio * srate);
855
856         return  correction;
857 }
858
859 /*
860  * stb0899_dvbs2_set_srate
861  * Set DVBS2 symbol rate
862  */
863 static void stb0899_dvbs2_set_srate(struct stb0899_state *state)
864 {
865         struct stb0899_internal *internal = &state->internal;
866
867         u32 dec_ratio, dec_rate, win_sel, decim, f_sym, btr_nom_freq;
868         u32 correction, freq_adj, band_lim, decim_cntrl, reg;
869         u8 anti_alias;
870
871         /*set decimation to 1*/
872         dec_ratio = (internal->master_clk * 2) / (5 * internal->srate);
873         dec_ratio = (dec_ratio == 0) ? 1 : dec_ratio;
874         dec_rate = Log2Int(dec_ratio);
875
876         win_sel = 0;
877         if (dec_rate >= 5)
878                 win_sel = dec_rate - 4;
879
880         decim = (1 << dec_rate);
881         /* (FSamp/Fsymbol *100) for integer Caculation */
882         f_sym = internal->master_clk / ((decim * internal->srate) / 1000);
883
884         if (f_sym <= 2250)      /* don't band limit signal going into btr block*/
885                 band_lim = 1;
886         else
887                 band_lim = 0;   /* band limit signal going into btr block*/
888
889         decim_cntrl = ((win_sel << 3) & 0x18) + ((band_lim << 5) & 0x20) + (dec_rate & 0x7);
890         stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_DECIM_CNTRL, STB0899_OFF0_DECIM_CNTRL, decim_cntrl);
891
892         if (f_sym <= 3450)
893                 anti_alias = 0;
894         else if (f_sym <= 4250)
895                 anti_alias = 1;
896         else
897                 anti_alias = 2;
898
899         stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_ANTI_ALIAS_SEL, STB0899_OFF0_ANTI_ALIAS_SEL, anti_alias);
900         btr_nom_freq = stb0899_dvbs2_calc_srate(state);
901         stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_BTR_NOM_FREQ, STB0899_OFF0_BTR_NOM_FREQ, btr_nom_freq);
902
903         correction = stb0899_dvbs2_calc_dev(state);
904         reg = STB0899_READ_S2REG(STB0899_S2DEMOD, BTR_CNTRL);
905         STB0899_SETFIELD_VAL(BTR_FREQ_CORR, reg, correction);
906         stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_BTR_CNTRL, STB0899_OFF0_BTR_CNTRL, reg);
907
908         /* scale UWP+CSM frequency to sample rate*/
909         freq_adj =  internal->srate / (internal->master_clk / 4096);
910         stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_FREQ_ADJ_SCALE, STB0899_OFF0_FREQ_ADJ_SCALE, freq_adj);
911 }
912
913 /*
914  * stb0899_dvbs2_set_btr_loopbw
915  * set bit timing loop bandwidth as a percentage of the symbol rate
916  */
917 static void stb0899_dvbs2_set_btr_loopbw(struct stb0899_state *state)
918 {
919         struct stb0899_internal *internal       = &state->internal;
920         struct stb0899_config *config           = state->config;
921
922         u32 sym_peak = 23, zeta = 707, loopbw_percent = 60;
923         s32 dec_ratio, dec_rate, k_btr1_rshft, k_btr1, k_btr0_rshft;
924         s32 k_btr0, k_btr2_rshft, k_direct_shift, k_indirect_shift;
925         u32 decim, K, wn, k_direct, k_indirect;
926         u32 reg;
927
928         dec_ratio = (internal->master_clk * 2) / (5 * internal->srate);
929         dec_ratio = (dec_ratio == 0) ? 1 : dec_ratio;
930         dec_rate = Log2Int(dec_ratio);
931         decim = (1 << dec_rate);
932
933         sym_peak *= 576000;
934         K = (1 << config->btr_nco_bits) / (internal->master_clk / 1000);
935         K *= (internal->srate / 1000000) * decim; /*k=k 10^-8*/
936         K = sym_peak / K;
937
938         if (K != 0) {
939                 wn = (4 * zeta * zeta) + 1000000;
940                 wn = (2 * (loopbw_percent * 1000) * 40 * zeta) /wn;  /*wn =wn 10^-8*/
941
942                 k_indirect = (wn * wn) / K;
943                 k_indirect = k_indirect;          /*kindirect = kindirect 10^-6*/
944                 k_direct   = (2 * wn * zeta) / K;       /*kDirect = kDirect 10^-2*/
945                 k_direct  *= 100;
946
947                 k_direct_shift = Log2Int(k_direct) - Log2Int(10000) - 2;
948                 k_btr1_rshft = (-1 * k_direct_shift) + config->btr_gain_shift_offset;
949                 k_btr1 = k_direct / (1 << k_direct_shift);
950                 k_btr1 /= 10000;
951
952                 k_indirect_shift = Log2Int(k_indirect + 15) - 20 /*- 2*/;
953                 k_btr0_rshft = (-1 * k_indirect_shift) + config->btr_gain_shift_offset;
954                 k_btr0 = k_indirect * (1 << (-k_indirect_shift));
955                 k_btr0 /= 1000000;
956
957                 k_btr2_rshft = 0;
958                 if (k_btr0_rshft > 15) {
959                         k_btr2_rshft = k_btr0_rshft - 15;
960                         k_btr0_rshft = 15;
961                 }
962                 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, BTR_LOOP_GAIN);
963                 STB0899_SETFIELD_VAL(KBTR0_RSHFT, reg, k_btr0_rshft);
964                 STB0899_SETFIELD_VAL(KBTR0, reg, k_btr0);
965                 STB0899_SETFIELD_VAL(KBTR1_RSHFT, reg, k_btr1_rshft);
966                 STB0899_SETFIELD_VAL(KBTR1, reg, k_btr1);
967                 STB0899_SETFIELD_VAL(KBTR2_RSHFT, reg, k_btr2_rshft);
968                 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_BTR_LOOP_GAIN, STB0899_OFF0_BTR_LOOP_GAIN, reg);
969         } else
970                 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_BTR_LOOP_GAIN, STB0899_OFF0_BTR_LOOP_GAIN, 0xc4c4f);
971 }
972
973 /*
974  * stb0899_dvbs2_set_carr_freq
975  * set nominal frequency for carrier search
976  */
977 static void stb0899_dvbs2_set_carr_freq(struct stb0899_state *state, s32 carr_freq, u32 master_clk)
978 {
979         struct stb0899_config *config = state->config;
980         s32 crl_nom_freq;
981         u32 reg;
982
983         crl_nom_freq = (1 << config->crl_nco_bits) / master_clk;
984         crl_nom_freq *= carr_freq;
985         reg = STB0899_READ_S2REG(STB0899_S2DEMOD, CRL_NOM_FREQ);
986         STB0899_SETFIELD_VAL(CRL_NOM_FREQ, reg, crl_nom_freq);
987         stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CRL_NOM_FREQ, STB0899_OFF0_CRL_NOM_FREQ, reg);
988 }
989
990 /*
991  * stb0899_dvbs2_init_calc
992  * Initialize DVBS2 UWP, CSM, carrier and timing loops
993  */
994 static void stb0899_dvbs2_init_calc(struct stb0899_state *state)
995 {
996         struct stb0899_internal *internal = &state->internal;
997         s32 steps, step_size;
998         u32 range, reg;
999
1000         /* config uwp and csm */
1001         stb0899_dvbs2_config_uwp(state);
1002         stb0899_dvbs2_config_csm_auto(state);
1003
1004         /* initialize BTR       */
1005         stb0899_dvbs2_set_srate(state);
1006         stb0899_dvbs2_set_btr_loopbw(state);
1007
1008         if (internal->srate / 1000000 >= 15)
1009                 step_size = (1 << 17) / 5;
1010         else if (internal->srate / 1000000 >= 10)
1011                 step_size = (1 << 17) / 7;
1012         else if (internal->srate / 1000000 >= 5)
1013                 step_size = (1 << 17) / 10;
1014         else
1015                 step_size = (1 << 17) / 4;
1016
1017         range = internal->srch_range / 1000000;
1018         steps = (10 * range * (1 << 17)) / (step_size * (internal->srate / 1000000));
1019         steps = (steps + 6) / 10;
1020         steps = (steps == 0) ? 1 : steps;
1021         if (steps % 2 == 0)
1022                 stb0899_dvbs2_set_carr_freq(state, internal->center_freq -
1023                                            (internal->step_size * (internal->srate / 20000000)),
1024                                            (internal->master_clk) / 1000000);
1025         else
1026                 stb0899_dvbs2_set_carr_freq(state, internal->center_freq, (internal->master_clk) / 1000000);
1027
1028         /*Set Carrier Search params (zigzag, num steps and freq step size*/
1029         reg = STB0899_READ_S2REG(STB0899_S2DEMOD, ACQ_CNTRL2);
1030         STB0899_SETFIELD_VAL(ZIGZAG, reg, 1);
1031         STB0899_SETFIELD_VAL(NUM_STEPS, reg, steps);
1032         STB0899_SETFIELD_VAL(FREQ_STEPSIZE, reg, step_size);
1033         stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_ACQ_CNTRL2, STB0899_OFF0_ACQ_CNTRL2, reg);
1034 }
1035
1036 /*
1037  * stb0899_dvbs2_btr_init
1038  * initialize the timing loop
1039  */
1040 static void stb0899_dvbs2_btr_init(struct stb0899_state *state)
1041 {
1042         u32 reg;
1043
1044         /* set enable BTR loopback      */
1045         reg = STB0899_READ_S2REG(STB0899_S2DEMOD, BTR_CNTRL);
1046         STB0899_SETFIELD_VAL(INTRP_PHS_SENSE, reg, 1);
1047         STB0899_SETFIELD_VAL(BTR_ERR_ENA, reg, 1);
1048         stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_BTR_CNTRL, STB0899_OFF0_BTR_CNTRL, reg);
1049
1050         /* fix btr freq accum at 0      */
1051         stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_BTR_FREQ_INIT, STB0899_OFF0_BTR_FREQ_INIT, 0x10000000);
1052         stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_BTR_FREQ_INIT, STB0899_OFF0_BTR_FREQ_INIT, 0x00000000);
1053
1054         /* fix btr freq accum at 0      */
1055         stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_BTR_PHS_INIT, STB0899_OFF0_BTR_PHS_INIT, 0x10000000);
1056         stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_BTR_PHS_INIT, STB0899_OFF0_BTR_PHS_INIT, 0x00000000);
1057 }
1058
1059 /*
1060  * stb0899_dvbs2_reacquire
1061  * trigger a DVB-S2 acquisition
1062  */
1063 static void stb0899_dvbs2_reacquire(struct stb0899_state *state)
1064 {
1065         u32 reg = 0;
1066
1067         /* demod soft reset     */
1068         STB0899_SETFIELD_VAL(DVBS2_RESET, reg, 1);
1069         stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_RESET_CNTRL, STB0899_OFF0_RESET_CNTRL, reg);
1070
1071         /*Reset Timing Loop     */
1072         stb0899_dvbs2_btr_init(state);
1073
1074         /* reset Carrier loop   */
1075         stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CRL_FREQ_INIT, STB0899_OFF0_CRL_FREQ_INIT, (1 << 30));
1076         stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CRL_FREQ_INIT, STB0899_OFF0_CRL_FREQ_INIT, 0);
1077         stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CRL_LOOP_GAIN, STB0899_OFF0_CRL_LOOP_GAIN, 0);
1078         stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CRL_PHS_INIT, STB0899_OFF0_CRL_PHS_INIT, (1 << 30));
1079         stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CRL_PHS_INIT, STB0899_OFF0_CRL_PHS_INIT, 0);
1080
1081         /*release demod soft reset      */
1082         reg = 0;
1083         STB0899_SETFIELD_VAL(DVBS2_RESET, reg, 0);
1084         stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_RESET_CNTRL, STB0899_OFF0_RESET_CNTRL, reg);
1085
1086         /* start acquisition process    */
1087         stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_ACQUIRE_TRIG, STB0899_OFF0_ACQUIRE_TRIG, 1);
1088         stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_LOCK_LOST, STB0899_OFF0_LOCK_LOST, 0);
1089
1090         /* equalizer Init       */
1091         stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_EQUALIZER_INIT, STB0899_OFF0_EQUALIZER_INIT, 1);
1092
1093         /*Start equilizer       */
1094         stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_EQUALIZER_INIT, STB0899_OFF0_EQUALIZER_INIT, 0);
1095
1096         reg = STB0899_READ_S2REG(STB0899_S2DEMOD, EQ_CNTRL);
1097         STB0899_SETFIELD_VAL(EQ_SHIFT, reg, 0);
1098         STB0899_SETFIELD_VAL(EQ_DISABLE_UPDATE, reg, 0);
1099         STB0899_SETFIELD_VAL(EQ_DELAY, reg, 0x05);
1100         STB0899_SETFIELD_VAL(EQ_ADAPT_MODE, reg, 0x01);
1101         stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_EQ_CNTRL, STB0899_OFF0_EQ_CNTRL, reg);
1102
1103         /* RESET Packet delineator      */
1104         stb0899_write_reg(state, STB0899_PDELCTRL, 0x4a);
1105 }
1106
1107 /*
1108  * stb0899_dvbs2_get_dmd_status
1109  * get DVB-S2 Demod LOCK status
1110  */
1111 static enum stb0899_status stb0899_dvbs2_get_dmd_status(struct stb0899_state *state, int timeout)
1112 {
1113         int time = -10, lock = 0, uwp, csm;
1114         u32 reg;
1115
1116         do {
1117                 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, DMD_STATUS);
1118                 dprintk(state->verbose, FE_DEBUG, 1, "DMD_STATUS=[0x%02x]", reg);
1119                 if (STB0899_GETFIELD(IF_AGC_LOCK, reg))
1120                         dprintk(state->verbose, FE_DEBUG, 1, "------------->IF AGC LOCKED !");
1121                 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, DMD_STAT2);
1122                 dprintk(state->verbose, FE_DEBUG, 1, "----------->DMD STAT2=[0x%02x]", reg);
1123                 uwp = STB0899_GETFIELD(UWP_LOCK, reg);
1124                 csm = STB0899_GETFIELD(CSM_LOCK, reg);
1125                 if (uwp && csm)
1126                         lock = 1;
1127
1128                 time += 10;
1129                 msleep(10);
1130
1131         } while ((!lock) && (time <= timeout));
1132
1133         if (lock) {
1134                 dprintk(state->verbose, FE_DEBUG, 1, "----------------> DVB-S2 LOCK !");
1135                 return DVBS2_DEMOD_LOCK;
1136         } else {
1137                 return DVBS2_DEMOD_NOLOCK;
1138         }
1139 }
1140
1141 /*
1142  * stb0899_dvbs2_get_data_lock
1143  * get FEC status
1144  */
1145 static int stb0899_dvbs2_get_data_lock(struct stb0899_state *state, int timeout)
1146 {
1147         int time = 0, lock = 0;
1148         u8 reg;
1149
1150         while ((!lock) && (time < timeout)) {
1151                 reg = stb0899_read_reg(state, STB0899_CFGPDELSTATUS1);
1152                 dprintk(state->verbose, FE_DEBUG, 1, "---------> CFGPDELSTATUS=[0x%02x]", reg);
1153                 lock = STB0899_GETFIELD(CFGPDELSTATUS_LOCK, reg);
1154                 time++;
1155         }
1156
1157         return lock;
1158 }
1159
1160 /*
1161  * stb0899_dvbs2_get_fec_status
1162  * get DVB-S2 FEC LOCK status
1163  */
1164 static enum stb0899_status stb0899_dvbs2_get_fec_status(struct stb0899_state *state, int timeout)
1165 {
1166         int time = 0, Locked;
1167
1168         do {
1169                 Locked = stb0899_dvbs2_get_data_lock(state, 1);
1170                 time++;
1171                 msleep(1);
1172
1173         } while ((!Locked) && (time < timeout));
1174
1175         if (Locked) {
1176                 dprintk(state->verbose, FE_DEBUG, 1, "---------->DVB-S2 FEC LOCK !");
1177                 return DVBS2_FEC_LOCK;
1178         } else {
1179                 return DVBS2_FEC_NOLOCK;
1180         }
1181 }
1182
1183
1184 /*
1185  * stb0899_dvbs2_init_csm
1186  * set parameters for manual mode
1187  */
1188 static void stb0899_dvbs2_init_csm(struct stb0899_state *state, int pilots, enum stb0899_modcod modcod)
1189 {
1190         struct stb0899_internal *internal = &state->internal;
1191
1192         s32 dvt_tbl = 1, two_pass = 0, agc_gain = 6, agc_shift = 0, loop_shift = 0, phs_diff_thr = 0x80;
1193         s32 gamma_acq, gamma_rho_acq, gamma_trk, gamma_rho_trk, lock_count_thr;
1194         u32 csm1, csm2, csm3, csm4;
1195
1196         if (((internal->master_clk / internal->srate) <= 4) && (modcod <= 11) && (pilots == 1)) {
1197                 switch (modcod) {
1198                 case STB0899_QPSK_12:
1199                         gamma_acq               = 25;
1200                         gamma_rho_acq           = 2700;
1201                         gamma_trk               = 12;
1202                         gamma_rho_trk           = 180;
1203                         lock_count_thr          = 8;
1204                         break;
1205                 case STB0899_QPSK_35:
1206                         gamma_acq               = 38;
1207                         gamma_rho_acq           = 7182;
1208                         gamma_trk               = 14;
1209                         gamma_rho_trk           = 308;
1210                         lock_count_thr          = 8;
1211                         break;
1212                 case STB0899_QPSK_23:
1213                         gamma_acq               = 42;
1214                         gamma_rho_acq           = 9408;
1215                         gamma_trk               = 17;
1216                         gamma_rho_trk           = 476;
1217                         lock_count_thr          = 8;
1218                         break;
1219                 case STB0899_QPSK_34:
1220                         gamma_acq               = 53;
1221                         gamma_rho_acq           = 16642;
1222                         gamma_trk               = 19;
1223                         gamma_rho_trk           = 646;
1224                         lock_count_thr          = 8;
1225                         break;
1226                 case STB0899_QPSK_45:
1227                         gamma_acq               = 53;
1228                         gamma_rho_acq           = 17119;
1229                         gamma_trk               = 22;
1230                         gamma_rho_trk           = 880;
1231                         lock_count_thr          = 8;
1232                         break;
1233                 case STB0899_QPSK_56:
1234                         gamma_acq               = 55;
1235                         gamma_rho_acq           = 19250;
1236                         gamma_trk               = 23;
1237                         gamma_rho_trk           = 989;
1238                         lock_count_thr          = 8;
1239                         break;
1240                 case STB0899_QPSK_89:
1241                         gamma_acq               = 60;
1242                         gamma_rho_acq           = 24240;
1243                         gamma_trk               = 24;
1244                         gamma_rho_trk           = 1176;
1245                         lock_count_thr          = 8;
1246                         break;
1247                 case STB0899_QPSK_910:
1248                         gamma_acq               = 66;
1249                         gamma_rho_acq           = 29634;
1250                         gamma_trk               = 24;
1251                         gamma_rho_trk           = 1176;
1252                         lock_count_thr          = 8;
1253                         break;
1254                 default:
1255                         gamma_acq               = 66;
1256                         gamma_rho_acq           = 29634;
1257                         gamma_trk               = 24;
1258                         gamma_rho_trk           = 1176;
1259                         lock_count_thr          = 8;
1260                         break;
1261                 }
1262
1263                 csm1 = STB0899_READ_S2REG(STB0899_S2DEMOD, CSM_CNTRL1);
1264                 STB0899_SETFIELD_VAL(CSM_AUTO_PARAM, csm1, 0);
1265                 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CSM_CNTRL1, STB0899_OFF0_CSM_CNTRL1, csm1);
1266
1267                 csm1 = STB0899_READ_S2REG(STB0899_S2DEMOD, CSM_CNTRL1);
1268                 csm2 = STB0899_READ_S2REG(STB0899_S2DEMOD, CSM_CNTRL2);
1269                 csm3 = STB0899_READ_S2REG(STB0899_S2DEMOD, CSM_CNTRL3);
1270                 csm4 = STB0899_READ_S2REG(STB0899_S2DEMOD, CSM_CNTRL4);
1271
1272                 STB0899_SETFIELD_VAL(CSM_DVT_TABLE, csm1, dvt_tbl);
1273                 STB0899_SETFIELD_VAL(CSM_TWO_PASS, csm1, two_pass);
1274                 STB0899_SETFIELD_VAL(CSM_AGC_GAIN, csm1, agc_gain);
1275                 STB0899_SETFIELD_VAL(CSM_AGC_SHIFT, csm1, agc_shift);
1276                 STB0899_SETFIELD_VAL(FE_LOOP_SHIFT, csm1, loop_shift);
1277                 STB0899_SETFIELD_VAL(CSM_GAMMA_ACQ, csm2, gamma_acq);
1278                 STB0899_SETFIELD_VAL(CSM_GAMMA_RHOACQ, csm2, gamma_rho_acq);
1279                 STB0899_SETFIELD_VAL(CSM_GAMMA_TRACK, csm3, gamma_trk);
1280                 STB0899_SETFIELD_VAL(CSM_GAMMA_RHOTRACK, csm3, gamma_rho_trk);
1281                 STB0899_SETFIELD_VAL(CSM_LOCKCOUNT_THRESH, csm4, lock_count_thr);
1282                 STB0899_SETFIELD_VAL(CSM_PHASEDIFF_THRESH, csm4, phs_diff_thr);
1283
1284                 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CSM_CNTRL1, STB0899_OFF0_CSM_CNTRL1, csm1);
1285                 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CSM_CNTRL2, STB0899_OFF0_CSM_CNTRL2, csm2);
1286                 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CSM_CNTRL3, STB0899_OFF0_CSM_CNTRL3, csm3);
1287                 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CSM_CNTRL4, STB0899_OFF0_CSM_CNTRL4, csm4);
1288         }
1289 }
1290
1291 /*
1292  * stb0899_dvbs2_get_srate
1293  * get DVB-S2 Symbol Rate
1294  */
1295 static u32 stb0899_dvbs2_get_srate(struct stb0899_state *state)
1296 {
1297         struct stb0899_internal *internal = &state->internal;
1298         struct stb0899_config *config = state->config;
1299
1300         u32 bTrNomFreq, srate, decimRate, intval1, intval2, reg;
1301         int div1, div2, rem1, rem2;
1302
1303         div1 = config->btr_nco_bits / 2;
1304         div2 = config->btr_nco_bits - div1 - 1;
1305
1306         bTrNomFreq = STB0899_READ_S2REG(STB0899_S2DEMOD, BTR_NOM_FREQ);
1307
1308         reg = STB0899_READ_S2REG(STB0899_S2DEMOD, DECIM_CNTRL);
1309         decimRate = STB0899_GETFIELD(DECIM_RATE, reg);
1310         decimRate = (1 << decimRate);
1311
1312         intval1 = internal->master_clk / (1 << div1);
1313         intval2 = bTrNomFreq / (1 << div2);
1314
1315         rem1 = internal->master_clk % (1 << div1);
1316         rem2 = bTrNomFreq % (1 << div2);
1317         /* only for integer calculation */
1318         srate = (intval1 * intval2) + ((intval1 * rem2) / (1 << div2)) + ((intval2 * rem1) / (1 << div1));
1319         srate /= decimRate;     /*symbrate = (btrnomfreq_register_val*MasterClock)/2^(27+decim_rate_field) */
1320
1321         return  srate;
1322 }
1323
1324 /*
1325  * stb0899_dvbs2_algo
1326  * Search for signal, timing, carrier and data for a given
1327  * frequency in a given range
1328  */
1329 enum stb0899_status stb0899_dvbs2_algo(struct stb0899_state *state)
1330 {
1331         struct stb0899_internal *internal = &state->internal;
1332         enum stb0899_modcod modcod;
1333
1334         s32 offsetfreq, searchTime, FecLockTime, pilots, iqSpectrum;
1335         int i = 0;
1336         u32 reg, csm1;
1337
1338         if (internal->srate <= 2000000) {
1339                 searchTime      = 5000; /* 5000 ms max time to lock UWP and CSM, SYMB <= 2Mbs           */
1340                 FecLockTime     = 350;  /* 350  ms max time to lock FEC, SYMB <= 2Mbs                   */
1341         } else if (internal->srate <= 5000000) {
1342                 searchTime      = 2500; /* 2500 ms max time to lock UWP and CSM, 2Mbs < SYMB <= 5Mbs    */
1343                 FecLockTime     = 170;  /* 170  ms max time to lock FEC, 2Mbs< SYMB <= 5Mbs             */
1344         } else if (internal->srate <= 10000000) {
1345                 searchTime      = 1500; /* 1500 ms max time to lock UWP and CSM, 5Mbs <SYMB <= 10Mbs    */
1346                 FecLockTime     = 80;   /* 80  ms max time to lock FEC, 5Mbs< SYMB <= 10Mbs             */
1347         } else if (internal->srate <= 15000000) {
1348                 searchTime      = 500;  /* 500 ms max time to lock UWP and CSM, 10Mbs <SYMB <= 15Mbs    */
1349                 FecLockTime     = 50;   /* 50  ms max time to lock FEC, 10Mbs< SYMB <= 15Mbs            */
1350         } else if (internal->srate <= 20000000) {
1351                 searchTime      = 300;  /* 300 ms max time to lock UWP and CSM, 15Mbs < SYMB <= 20Mbs   */
1352                 FecLockTime     = 30;   /* 50  ms max time to lock FEC, 15Mbs< SYMB <= 20Mbs            */
1353         } else if (internal->srate <= 25000000) {
1354                 searchTime      = 250;  /* 250 ms max time to lock UWP and CSM, 20 Mbs < SYMB <= 25Mbs  */
1355                 FecLockTime     = 25;   /* 25 ms max time to lock FEC, 20Mbs< SYMB <= 25Mbs             */
1356         } else {
1357                 searchTime      = 150;  /* 150 ms max time to lock UWP and CSM, SYMB > 25Mbs            */
1358                 FecLockTime     = 20;   /* 20 ms max time to lock FEC, 20Mbs< SYMB <= 25Mbs             */
1359         }
1360
1361         /* Maintain Stream Merger in reset during acquisition   */
1362         reg = stb0899_read_reg(state, STB0899_TSTRES);
1363         STB0899_SETFIELD_VAL(FRESRS, reg, 1);
1364         stb0899_write_reg(state, STB0899_TSTRES, reg);
1365
1366         /* Move tuner to frequency      */
1367         if (state->config->tuner_set_frequency)
1368                 state->config->tuner_set_frequency(&state->frontend, internal->freq);
1369         if (state->config->tuner_get_frequency)
1370                 state->config->tuner_get_frequency(&state->frontend, &internal->freq);
1371
1372         /* Set IF AGC to acquisition    */
1373         reg = STB0899_READ_S2REG(STB0899_S2DEMOD, IF_AGC_CNTRL);
1374         STB0899_SETFIELD_VAL(IF_LOOP_GAIN, reg,  4);
1375         STB0899_SETFIELD_VAL(IF_AGC_REF, reg, 32);
1376         stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_IF_AGC_CNTRL, STB0899_OFF0_IF_AGC_CNTRL, reg);
1377
1378         reg = STB0899_READ_S2REG(STB0899_S2DEMOD, IF_AGC_CNTRL2);
1379         STB0899_SETFIELD_VAL(IF_AGC_DUMP_PER, reg, 0);
1380         stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_IF_AGC_CNTRL2, STB0899_OFF0_IF_AGC_CNTRL2, reg);
1381
1382         /* Initialisation       */
1383         stb0899_dvbs2_init_calc(state);
1384
1385         reg = STB0899_READ_S2REG(STB0899_S2DEMOD, DMD_CNTRL2);
1386         switch (internal->inversion) {
1387         case IQ_SWAP_OFF:
1388                 STB0899_SETFIELD_VAL(SPECTRUM_INVERT, reg, 0);
1389                 break;
1390         case IQ_SWAP_ON:
1391                 STB0899_SETFIELD_VAL(SPECTRUM_INVERT, reg, 1);
1392                 break;
1393         case IQ_SWAP_AUTO:      /* use last successful search first     */
1394                 STB0899_SETFIELD_VAL(SPECTRUM_INVERT, reg, 1);
1395                 break;
1396         }
1397         stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_DMD_CNTRL2, STB0899_OFF0_DMD_CNTRL2, reg);
1398         stb0899_dvbs2_reacquire(state);
1399
1400         /* Wait for demod lock (UWP and CSM)    */
1401         internal->status = stb0899_dvbs2_get_dmd_status(state, searchTime);
1402
1403         if (internal->status == DVBS2_DEMOD_LOCK) {
1404                 dprintk(state->verbose, FE_DEBUG, 1, "------------> DVB-S2 DEMOD LOCK !");
1405                 i = 0;
1406                 /* Demod Locked, check FEC status       */
1407                 internal->status = stb0899_dvbs2_get_fec_status(state, FecLockTime);
1408
1409                 /*If false lock (UWP and CSM Locked but no FEC) try 3 time max*/
1410                 while ((internal->status != DVBS2_FEC_LOCK) && (i < 3)) {
1411                         /*      Read the frequency offset*/
1412                         offsetfreq = STB0899_READ_S2REG(STB0899_S2DEMOD, CRL_FREQ);
1413
1414                         /* Set the Nominal frequency to the found frequency offset for the next reacquire*/
1415                         reg = STB0899_READ_S2REG(STB0899_S2DEMOD, CRL_NOM_FREQ);
1416                         STB0899_SETFIELD_VAL(CRL_NOM_FREQ, reg, offsetfreq);
1417                         stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CRL_NOM_FREQ, STB0899_OFF0_CRL_NOM_FREQ, offsetfreq);
1418                         stb0899_dvbs2_reacquire(state);
1419                         internal->status = stb0899_dvbs2_get_fec_status(state, searchTime);
1420                         i++;
1421                 }
1422         }
1423
1424         if (internal->status != DVBS2_FEC_LOCK) {
1425                 if (internal->inversion == IQ_SWAP_AUTO) {
1426                         reg = STB0899_READ_S2REG(STB0899_S2DEMOD, DMD_CNTRL2);
1427                         iqSpectrum = STB0899_GETFIELD(SPECTRUM_INVERT, reg);
1428                         /* IQ Spectrum Inversion        */
1429                         STB0899_SETFIELD_VAL(SPECTRUM_INVERT, reg, !iqSpectrum);
1430                         stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_DMD_CNTRL2, STB0899_OFF0_DMD_CNTRL2, reg);
1431                         /* start acquistion process     */
1432                         stb0899_dvbs2_reacquire(state);
1433
1434                         /* Wait for demod lock (UWP and CSM)    */
1435                         internal->status = stb0899_dvbs2_get_dmd_status(state, searchTime);
1436                         if (internal->status == DVBS2_DEMOD_LOCK) {
1437                                 i = 0;
1438                                 /* Demod Locked, check FEC      */
1439                                 internal->status = stb0899_dvbs2_get_fec_status(state, FecLockTime);
1440                                 /*try thrice for false locks, (UWP and CSM Locked but no FEC)   */
1441                                 while ((internal->status != DVBS2_FEC_LOCK) && (i < 3)) {
1442                                         /*      Read the frequency offset*/
1443                                         offsetfreq = STB0899_READ_S2REG(STB0899_S2DEMOD, CRL_FREQ);
1444
1445                                         /* Set the Nominal frequency to the found frequency offset for the next reacquire*/
1446                                         reg = STB0899_READ_S2REG(STB0899_S2DEMOD, CRL_NOM_FREQ);
1447                                         STB0899_SETFIELD_VAL(CRL_NOM_FREQ, reg, offsetfreq);
1448                                         stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CRL_NOM_FREQ, STB0899_OFF0_CRL_NOM_FREQ, offsetfreq);
1449
1450                                         stb0899_dvbs2_reacquire(state);
1451                                         internal->status = stb0899_dvbs2_get_fec_status(state, searchTime);
1452                                         i++;
1453                                 }
1454                         }
1455 /*
1456                         if (pParams->DVBS2State == FE_DVBS2_FEC_LOCKED)
1457                                 pParams->IQLocked = !iqSpectrum;
1458 */
1459                 }
1460         }
1461         if (internal->status == DVBS2_FEC_LOCK) {
1462                 dprintk(state->verbose, FE_DEBUG, 1, "----------------> DVB-S2 FEC Lock !");
1463                 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, UWP_STAT2);
1464                 modcod = STB0899_GETFIELD(UWP_DECODE_MOD, reg) >> 2;
1465                 pilots = STB0899_GETFIELD(UWP_DECODE_MOD, reg) & 0x01;
1466
1467                 if ((((10 * internal->master_clk) / (internal->srate / 10)) <= 410) &&
1468                       (INRANGE(STB0899_QPSK_23, modcod, STB0899_QPSK_910)) &&
1469                       (pilots == 1)) {
1470
1471                         stb0899_dvbs2_init_csm(state, pilots, modcod);
1472                         /* Wait for UWP,CSM and data LOCK 20ms max      */
1473                         internal->status = stb0899_dvbs2_get_fec_status(state, FecLockTime);
1474
1475                         i = 0;
1476                         while ((internal->status != DVBS2_FEC_LOCK) && (i < 3)) {
1477                                 csm1 = STB0899_READ_S2REG(STB0899_S2DEMOD, CSM_CNTRL1);
1478                                 STB0899_SETFIELD_VAL(CSM_TWO_PASS, csm1, 1);
1479                                 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CSM_CNTRL1, STB0899_OFF0_CSM_CNTRL1, csm1);
1480                                 csm1 = STB0899_READ_S2REG(STB0899_S2DEMOD, CSM_CNTRL1);
1481                                 STB0899_SETFIELD_VAL(CSM_TWO_PASS, csm1, 0);
1482                                 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CSM_CNTRL1, STB0899_OFF0_CSM_CNTRL1, csm1);
1483
1484                                 internal->status = stb0899_dvbs2_get_fec_status(state, FecLockTime);
1485                                 i++;
1486                         }
1487                 }
1488
1489                 if ((((10 * internal->master_clk) / (internal->srate / 10)) <= 410) &&
1490                       (INRANGE(STB0899_QPSK_12, modcod, STB0899_QPSK_35)) &&
1491                       (pilots == 1)) {
1492
1493                         /* Equalizer Disable update      */
1494                         reg = STB0899_READ_S2REG(STB0899_S2DEMOD, EQ_CNTRL);
1495                         STB0899_SETFIELD_VAL(EQ_DISABLE_UPDATE, reg, 1);
1496                         stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_EQ_CNTRL, STB0899_OFF0_EQ_CNTRL, reg);
1497                 }
1498
1499                 /* slow down the Equalizer once locked  */
1500                 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, EQ_CNTRL);
1501                 STB0899_SETFIELD_VAL(EQ_SHIFT, reg, 0x02);
1502                 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_EQ_CNTRL, STB0899_OFF0_EQ_CNTRL, reg);
1503
1504                 /* Store signal parameters      */
1505                 offsetfreq = STB0899_READ_S2REG(STB0899_S2DEMOD, CRL_FREQ);
1506
1507                 offsetfreq = offsetfreq / ((1 << 30) / 1000);
1508                 offsetfreq *= (internal->master_clk / 1000000);
1509                 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, DMD_CNTRL2);
1510                 if (STB0899_GETFIELD(SPECTRUM_INVERT, reg))
1511                         offsetfreq *= -1;
1512
1513                 internal->freq = internal->freq - offsetfreq;
1514                 internal->srate = stb0899_dvbs2_get_srate(state);
1515
1516                 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, UWP_STAT2);
1517                 internal->modcod = STB0899_GETFIELD(UWP_DECODE_MOD, reg) >> 2;
1518                 internal->pilots = STB0899_GETFIELD(UWP_DECODE_MOD, reg) & 0x01;
1519                 internal->frame_length = (STB0899_GETFIELD(UWP_DECODE_MOD, reg) >> 1) & 0x01;
1520
1521                  /* Set IF AGC to tracking      */
1522                 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, IF_AGC_CNTRL);
1523                 STB0899_SETFIELD_VAL(IF_LOOP_GAIN, reg,  3);
1524
1525                 /* if QPSK 1/2,QPSK 3/5 or QPSK 2/3 set IF AGC reference to 16 otherwise 32*/
1526                 if (INRANGE(STB0899_QPSK_12, internal->modcod, STB0899_QPSK_23))
1527                         STB0899_SETFIELD_VAL(IF_AGC_REF, reg, 16);
1528
1529                 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_IF_AGC_CNTRL, STB0899_OFF0_IF_AGC_CNTRL, reg);
1530
1531                 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, IF_AGC_CNTRL2);
1532                 STB0899_SETFIELD_VAL(IF_AGC_DUMP_PER, reg, 7);
1533                 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_IF_AGC_CNTRL2, STB0899_OFF0_IF_AGC_CNTRL2, reg);
1534         }
1535
1536         /* Release Stream Merger Reset          */
1537         reg = stb0899_read_reg(state, STB0899_TSTRES);
1538         STB0899_SETFIELD_VAL(FRESRS, reg, 0);
1539         stb0899_write_reg(state, STB0899_TSTRES, reg);
1540
1541         return internal->status;
1542 }