2 Driver for STV0297 demodulator
4 Copyright (C) 2004 Andrew de Quincey <adq_dvb@lidskialf.net>
5 Copyright (C) 2003-2004 Dennis Noermann <dennis.noermann@noernet.de>
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 #include <linux/init.h>
23 #include <linux/kernel.h>
24 #include <linux/module.h>
25 #include <linux/string.h>
26 #include <linux/delay.h>
27 #include <linux/jiffies.h>
28 #include <linux/slab.h>
30 #include "dvb_frontend.h"
33 struct stv0297_state {
34 struct i2c_adapter *i2c;
35 const struct stv0297_config *config;
36 struct dvb_frontend frontend;
38 unsigned long base_freq;
42 #define dprintk(x...) printk(x)
47 #define STV0297_CLOCK_KHZ 28900
50 static int stv0297_writereg(struct stv0297_state *state, u8 reg, u8 data)
53 u8 buf[] = { reg, data };
54 struct i2c_msg msg = {.addr = state->config->demod_address,.flags = 0,.buf = buf,.len = 2 };
56 ret = i2c_transfer(state->i2c, &msg, 1);
59 dprintk("%s: writereg error (reg == 0x%02x, val == 0x%02x, "
60 "ret == %i)\n", __FUNCTION__, reg, data, ret);
62 return (ret != 1) ? -1 : 0;
65 static int stv0297_readreg(struct stv0297_state *state, u8 reg)
70 struct i2c_msg msg[] = { {.addr = state->config->demod_address,.flags = 0,.buf = b0,.len = 1},
71 {.addr = state->config->demod_address,.flags = I2C_M_RD,.buf = b1,.len = 1}
74 // this device needs a STOP between the register and data
75 if (state->config->stop_during_read) {
76 if ((ret = i2c_transfer(state->i2c, &msg[0], 1)) != 1) {
77 dprintk("%s: readreg error (reg == 0x%02x, ret == %i)\n", __FUNCTION__, reg, ret);
80 if ((ret = i2c_transfer(state->i2c, &msg[1], 1)) != 1) {
81 dprintk("%s: readreg error (reg == 0x%02x, ret == %i)\n", __FUNCTION__, reg, ret);
85 if ((ret = i2c_transfer(state->i2c, msg, 2)) != 2) {
86 dprintk("%s: readreg error (reg == 0x%02x, ret == %i)\n", __FUNCTION__, reg, ret);
94 static int stv0297_writereg_mask(struct stv0297_state *state, u8 reg, u8 mask, u8 data)
98 val = stv0297_readreg(state, reg);
100 val |= (data & mask);
101 stv0297_writereg(state, reg, val);
106 static int stv0297_readregs(struct stv0297_state *state, u8 reg1, u8 * b, u8 len)
109 struct i2c_msg msg[] = { {.addr = state->config->demod_address,.flags = 0,.buf =
111 {.addr = state->config->demod_address,.flags = I2C_M_RD,.buf = b,.len = len}
114 // this device needs a STOP between the register and data
115 if (state->config->stop_during_read) {
116 if ((ret = i2c_transfer(state->i2c, &msg[0], 1)) != 1) {
117 dprintk("%s: readreg error (reg == 0x%02x, ret == %i)\n", __FUNCTION__, reg1, ret);
120 if ((ret = i2c_transfer(state->i2c, &msg[1], 1)) != 1) {
121 dprintk("%s: readreg error (reg == 0x%02x, ret == %i)\n", __FUNCTION__, reg1, ret);
125 if ((ret = i2c_transfer(state->i2c, msg, 2)) != 2) {
126 dprintk("%s: readreg error (reg == 0x%02x, ret == %i)\n", __FUNCTION__, reg1, ret);
134 static u32 stv0297_get_symbolrate(struct stv0297_state *state)
138 tmp = stv0297_readreg(state, 0x55);
139 tmp |= stv0297_readreg(state, 0x56) << 8;
140 tmp |= stv0297_readreg(state, 0x57) << 16;
141 tmp |= stv0297_readreg(state, 0x58) << 24;
143 tmp *= STV0297_CLOCK_KHZ;
149 static void stv0297_set_symbolrate(struct stv0297_state *state, u32 srate)
153 tmp = 131072L * srate; /* 131072 = 2^17 */
154 tmp = tmp / (STV0297_CLOCK_KHZ / 4); /* 1/4 = 2^-2 */
155 tmp = tmp * 8192L; /* 8192 = 2^13 */
157 stv0297_writereg(state, 0x55, (unsigned char) (tmp & 0xFF));
158 stv0297_writereg(state, 0x56, (unsigned char) (tmp >> 8));
159 stv0297_writereg(state, 0x57, (unsigned char) (tmp >> 16));
160 stv0297_writereg(state, 0x58, (unsigned char) (tmp >> 24));
163 static void stv0297_set_sweeprate(struct stv0297_state *state, short fshift, long symrate)
167 tmp = (long) fshift *262144L; /* 262144 = 2*18 */
169 tmp *= 1024; /* 1024 = 2*10 */
179 stv0297_writereg(state, 0x60, tmp & 0xFF);
180 stv0297_writereg_mask(state, 0x69, 0xF0, (tmp >> 4) & 0xf0);
183 static void stv0297_set_carrieroffset(struct stv0297_state *state, long offset)
187 /* symrate is hardcoded to 10000 */
188 tmp = offset * 26844L; /* (2**28)/10000 */
193 stv0297_writereg(state, 0x66, (unsigned char) (tmp & 0xFF));
194 stv0297_writereg(state, 0x67, (unsigned char) (tmp >> 8));
195 stv0297_writereg(state, 0x68, (unsigned char) (tmp >> 16));
196 stv0297_writereg_mask(state, 0x69, 0x0F, (tmp >> 24) & 0x0f);
200 static long stv0297_get_carrieroffset(struct stv0297_state *state)
204 stv0297_writereg(state, 0x6B, 0x00);
206 tmp = stv0297_readreg(state, 0x66);
207 tmp |= (stv0297_readreg(state, 0x67) << 8);
208 tmp |= (stv0297_readreg(state, 0x68) << 16);
209 tmp |= (stv0297_readreg(state, 0x69) & 0x0F) << 24;
211 tmp *= stv0297_get_symbolrate(state);
218 static void stv0297_set_initialdemodfreq(struct stv0297_state *state, long freq)
223 freq -= STV0297_CLOCK_KHZ;
225 tmp = (STV0297_CLOCK_KHZ * 1000) / (1 << 16);
226 tmp = (freq * 1000) / tmp;
230 stv0297_writereg_mask(state, 0x25, 0x80, 0x80);
231 stv0297_writereg(state, 0x21, tmp >> 8);
232 stv0297_writereg(state, 0x20, tmp);
235 static int stv0297_set_qam(struct stv0297_state *state, fe_modulation_t modulation)
239 switch (modulation) {
264 stv0297_writereg_mask(state, 0x00, 0x70, val << 4);
269 static int stv0297_set_inversion(struct stv0297_state *state, fe_spectral_inversion_t inversion)
286 stv0297_writereg_mask(state, 0x83, 0x08, val << 3);
291 static int stv0297_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
293 struct stv0297_state *state = fe->demodulator_priv;
296 stv0297_writereg(state, 0x87, 0x78);
297 stv0297_writereg(state, 0x86, 0xc8);
303 static int stv0297_init(struct dvb_frontend *fe)
305 struct stv0297_state *state = fe->demodulator_priv;
308 /* load init table */
309 for (i=0; !(state->config->inittab[i] == 0xff && state->config->inittab[i+1] == 0xff); i+=2)
310 stv0297_writereg(state, state->config->inittab[i], state->config->inittab[i+1]);
316 static int stv0297_sleep(struct dvb_frontend *fe)
318 struct stv0297_state *state = fe->demodulator_priv;
320 stv0297_writereg_mask(state, 0x80, 1, 1);
325 static int stv0297_read_status(struct dvb_frontend *fe, fe_status_t * status)
327 struct stv0297_state *state = fe->demodulator_priv;
329 u8 sync = stv0297_readreg(state, 0xDF);
334 FE_HAS_SYNC | FE_HAS_SIGNAL | FE_HAS_CARRIER | FE_HAS_VITERBI | FE_HAS_LOCK;
338 static int stv0297_read_ber(struct dvb_frontend *fe, u32 * ber)
340 struct stv0297_state *state = fe->demodulator_priv;
343 stv0297_writereg(state, 0xA0, 0x80); // Start Counting bit errors for 4096 Bytes
344 mdelay(25); // Hopefully got 4096 Bytes
345 stv0297_readregs(state, 0xA0, BER, 3);
347 *ber = (BER[2] << 8 | BER[1]) / (8 * 4096);
353 static int stv0297_read_signal_strength(struct dvb_frontend *fe, u16 * strength)
355 struct stv0297_state *state = fe->demodulator_priv;
358 stv0297_readregs(state, 0x41, STRENGTH, 2);
359 *strength = (STRENGTH[1] & 0x03) << 8 | STRENGTH[0];
364 static int stv0297_read_snr(struct dvb_frontend *fe, u16 * snr)
366 struct stv0297_state *state = fe->demodulator_priv;
369 stv0297_readregs(state, 0x07, SNR, 2);
370 *snr = SNR[1] << 8 | SNR[0];
375 static int stv0297_read_ucblocks(struct dvb_frontend *fe, u32 * ucblocks)
377 struct stv0297_state *state = fe->demodulator_priv;
379 *ucblocks = (stv0297_readreg(state, 0xD5) << 8)
380 | stv0297_readreg(state, 0xD4);
385 static int stv0297_set_frontend(struct dvb_frontend *fe, struct dvb_frontend_parameters *p)
387 struct stv0297_state *state = fe->demodulator_priv;
394 unsigned long starttime;
395 unsigned long timeout;
396 fe_spectral_inversion_t inversion;
398 switch (p->u.qam.modulation) {
416 // determine inversion dependant parameters
417 inversion = p->inversion;
418 if (state->config->invert)
419 inversion = (inversion == INVERSION_ON) ? INVERSION_OFF : INVERSION_ON;
420 carrieroffset = -330;
426 sweeprate = -sweeprate;
427 carrieroffset = -carrieroffset;
435 if (fe->ops.tuner_ops.set_params) {
436 fe->ops.tuner_ops.set_params(fe, p);
437 if (fe->ops.i2c_gate_ctrl) fe->ops.i2c_gate_ctrl(fe, 0);
440 /* clear software interrupts */
441 stv0297_writereg(state, 0x82, 0x0);
443 /* set initial demodulation frequency */
444 stv0297_set_initialdemodfreq(state, 7250);
447 stv0297_writereg_mask(state, 0x43, 0x10, 0x00);
448 stv0297_writereg(state, 0x41, 0x00);
449 stv0297_writereg_mask(state, 0x42, 0x03, 0x01);
450 stv0297_writereg_mask(state, 0x36, 0x60, 0x00);
451 stv0297_writereg_mask(state, 0x36, 0x18, 0x00);
452 stv0297_writereg_mask(state, 0x71, 0x80, 0x80);
453 stv0297_writereg(state, 0x72, 0x00);
454 stv0297_writereg(state, 0x73, 0x00);
455 stv0297_writereg_mask(state, 0x74, 0x0F, 0x00);
456 stv0297_writereg_mask(state, 0x43, 0x08, 0x00);
457 stv0297_writereg_mask(state, 0x71, 0x80, 0x00);
460 stv0297_writereg_mask(state, 0x5a, 0x20, 0x20);
461 stv0297_writereg_mask(state, 0x5b, 0x02, 0x02);
462 stv0297_writereg_mask(state, 0x5b, 0x02, 0x00);
463 stv0297_writereg_mask(state, 0x5b, 0x01, 0x00);
464 stv0297_writereg_mask(state, 0x5a, 0x40, 0x40);
466 /* disable frequency sweep */
467 stv0297_writereg_mask(state, 0x6a, 0x01, 0x00);
469 /* reset deinterleaver */
470 stv0297_writereg_mask(state, 0x81, 0x01, 0x01);
471 stv0297_writereg_mask(state, 0x81, 0x01, 0x00);
474 stv0297_writereg_mask(state, 0x83, 0x20, 0x20);
475 stv0297_writereg_mask(state, 0x83, 0x20, 0x00);
477 /* reset equaliser */
478 u_threshold = stv0297_readreg(state, 0x00) & 0xf;
479 initial_u = stv0297_readreg(state, 0x01) >> 4;
480 blind_u = stv0297_readreg(state, 0x01) & 0xf;
481 stv0297_writereg_mask(state, 0x84, 0x01, 0x01);
482 stv0297_writereg_mask(state, 0x84, 0x01, 0x00);
483 stv0297_writereg_mask(state, 0x00, 0x0f, u_threshold);
484 stv0297_writereg_mask(state, 0x01, 0xf0, initial_u << 4);
485 stv0297_writereg_mask(state, 0x01, 0x0f, blind_u);
487 /* data comes from internal A/D */
488 stv0297_writereg_mask(state, 0x87, 0x80, 0x00);
490 /* clear phase registers */
491 stv0297_writereg(state, 0x63, 0x00);
492 stv0297_writereg(state, 0x64, 0x00);
493 stv0297_writereg(state, 0x65, 0x00);
494 stv0297_writereg(state, 0x66, 0x00);
495 stv0297_writereg(state, 0x67, 0x00);
496 stv0297_writereg(state, 0x68, 0x00);
497 stv0297_writereg_mask(state, 0x69, 0x0f, 0x00);
500 stv0297_set_qam(state, p->u.qam.modulation);
501 stv0297_set_symbolrate(state, p->u.qam.symbol_rate / 1000);
502 stv0297_set_sweeprate(state, sweeprate, p->u.qam.symbol_rate / 1000);
503 stv0297_set_carrieroffset(state, carrieroffset);
504 stv0297_set_inversion(state, inversion);
507 /* Disable corner detection for higher QAMs */
508 if (p->u.qam.modulation == QAM_128 ||
509 p->u.qam.modulation == QAM_256)
510 stv0297_writereg_mask(state, 0x88, 0x08, 0x00);
512 stv0297_writereg_mask(state, 0x88, 0x08, 0x08);
514 stv0297_writereg_mask(state, 0x5a, 0x20, 0x00);
515 stv0297_writereg_mask(state, 0x6a, 0x01, 0x01);
516 stv0297_writereg_mask(state, 0x43, 0x40, 0x40);
517 stv0297_writereg_mask(state, 0x5b, 0x30, 0x00);
518 stv0297_writereg_mask(state, 0x03, 0x0c, 0x0c);
519 stv0297_writereg_mask(state, 0x03, 0x03, 0x03);
520 stv0297_writereg_mask(state, 0x43, 0x10, 0x10);
522 /* wait for WGAGC lock */
524 timeout = jiffies + msecs_to_jiffies(2000);
525 while (time_before(jiffies, timeout)) {
527 if (stv0297_readreg(state, 0x43) & 0x08)
530 if (time_after(jiffies, timeout)) {
535 /* wait for equaliser partial convergence */
536 timeout = jiffies + msecs_to_jiffies(500);
537 while (time_before(jiffies, timeout)) {
540 if (stv0297_readreg(state, 0x82) & 0x04) {
544 if (time_after(jiffies, timeout)) {
548 /* wait for equaliser full convergence */
549 timeout = jiffies + msecs_to_jiffies(delay);
550 while (time_before(jiffies, timeout)) {
553 if (stv0297_readreg(state, 0x82) & 0x08) {
557 if (time_after(jiffies, timeout)) {
562 stv0297_writereg_mask(state, 0x6a, 1, 0);
563 stv0297_writereg_mask(state, 0x88, 8, 0);
565 /* wait for main lock */
566 timeout = jiffies + msecs_to_jiffies(20);
567 while (time_before(jiffies, timeout)) {
570 if (stv0297_readreg(state, 0xDF) & 0x80) {
574 if (time_after(jiffies, timeout)) {
579 /* is it still locked after that delay? */
580 if (!(stv0297_readreg(state, 0xDF) & 0x80)) {
585 stv0297_writereg_mask(state, 0x5a, 0x40, 0x00);
586 state->base_freq = p->frequency;
590 stv0297_writereg_mask(state, 0x6a, 0x01, 0x00);
594 static int stv0297_get_frontend(struct dvb_frontend *fe, struct dvb_frontend_parameters *p)
596 struct stv0297_state *state = fe->demodulator_priv;
599 reg_00 = stv0297_readreg(state, 0x00);
600 reg_83 = stv0297_readreg(state, 0x83);
602 p->frequency = state->base_freq;
603 p->inversion = (reg_83 & 0x08) ? INVERSION_ON : INVERSION_OFF;
604 if (state->config->invert)
605 p->inversion = (p->inversion == INVERSION_ON) ? INVERSION_OFF : INVERSION_ON;
606 p->u.qam.symbol_rate = stv0297_get_symbolrate(state) * 1000;
607 p->u.qam.fec_inner = FEC_NONE;
609 switch ((reg_00 >> 4) & 0x7) {
611 p->u.qam.modulation = QAM_16;
614 p->u.qam.modulation = QAM_32;
617 p->u.qam.modulation = QAM_128;
620 p->u.qam.modulation = QAM_256;
623 p->u.qam.modulation = QAM_64;
630 static void stv0297_release(struct dvb_frontend *fe)
632 struct stv0297_state *state = fe->demodulator_priv;
636 static struct dvb_frontend_ops stv0297_ops;
638 struct dvb_frontend *stv0297_attach(const struct stv0297_config *config,
639 struct i2c_adapter *i2c)
641 struct stv0297_state *state = NULL;
643 /* allocate memory for the internal state */
644 state = kmalloc(sizeof(struct stv0297_state), GFP_KERNEL);
648 /* setup the state */
649 state->config = config;
651 state->base_freq = 0;
653 /* check if the demod is there */
654 if ((stv0297_readreg(state, 0x80) & 0x70) != 0x20)
657 /* create dvb_frontend */
658 memcpy(&state->frontend.ops, &stv0297_ops, sizeof(struct dvb_frontend_ops));
659 state->frontend.demodulator_priv = state;
660 return &state->frontend;
667 static struct dvb_frontend_ops stv0297_ops = {
670 .name = "ST STV0297 DVB-C",
672 .frequency_min = 64000000,
673 .frequency_max = 1300000000,
674 .frequency_stepsize = 62500,
675 .symbol_rate_min = 870000,
676 .symbol_rate_max = 11700000,
677 .caps = FE_CAN_QAM_16 | FE_CAN_QAM_32 | FE_CAN_QAM_64 |
678 FE_CAN_QAM_128 | FE_CAN_QAM_256 | FE_CAN_FEC_AUTO},
680 .release = stv0297_release,
682 .init = stv0297_init,
683 .sleep = stv0297_sleep,
684 .i2c_gate_ctrl = stv0297_i2c_gate_ctrl,
686 .set_frontend = stv0297_set_frontend,
687 .get_frontend = stv0297_get_frontend,
689 .read_status = stv0297_read_status,
690 .read_ber = stv0297_read_ber,
691 .read_signal_strength = stv0297_read_signal_strength,
692 .read_snr = stv0297_read_snr,
693 .read_ucblocks = stv0297_read_ucblocks,
696 MODULE_DESCRIPTION("ST STV0297 DVB-C Demodulator driver");
697 MODULE_AUTHOR("Dennis Noermann and Andrew de Quincey");
698 MODULE_LICENSE("GPL");
700 EXPORT_SYMBOL(stv0297_attach);