drivers/media/video/cx18/cx18-firmware.c

   1 /*
   2  *  cx18 firmware functions
   3  *
   4  *  Copyright (C) 2007  Hans Verkuil <hverkuil@xs4all.nl>
   5  *
   6  *  This program is free software; you can redistribute it and/or modify
   7  *  it under the terms of the GNU General Public License as published by
   8  *  the Free Software Foundation; either version 2 of the License, or
   9  *  (at your option) any later version.
  10  *
  11  *  This program is distributed in the hope that it will be useful,
  12  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  *  GNU General Public License for more details.
  15  *
  16  *  You should have received a copy of the GNU General Public License
  17  *  along with this program; if not, write to the Free Software
  18  *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
  19  *  02111-1307  USA
  20  */
  21
  22 #include "cx18-driver.h"
  23 #include "cx18-scb.h"
  24 #include "cx18-irq.h"
  25 #include "cx18-firmware.h"
  26 #include "cx18-cards.h"
  27 #include <linux/firmware.h>
  28
  29 #define CX18_PROC_SOFT_RESET            0xc70010
  30 #define CX18_DDR_SOFT_RESET             0xc70014
  31 #define CX18_CLOCK_SELECT1              0xc71000
  32 #define CX18_CLOCK_SELECT2              0xc71004
  33 #define CX18_HALF_CLOCK_SELECT1         0xc71008
  34 #define CX18_HALF_CLOCK_SELECT2         0xc7100C
  35 #define CX18_CLOCK_POLARITY1            0xc71010
  36 #define CX18_CLOCK_POLARITY2            0xc71014
  37 #define CX18_ADD_DELAY_ENABLE1          0xc71018
  38 #define CX18_ADD_DELAY_ENABLE2          0xc7101C
  39 #define CX18_CLOCK_ENABLE1              0xc71020
  40 #define CX18_CLOCK_ENABLE2              0xc71024
  41
  42 #define CX18_REG_BUS_TIMEOUT_EN         0xc72024
  43
  44 #define CX18_FAST_CLOCK_PLL_INT         0xc78000
  45 #define CX18_FAST_CLOCK_PLL_FRAC        0xc78004
  46 #define CX18_FAST_CLOCK_PLL_POST        0xc78008
  47 #define CX18_FAST_CLOCK_PLL_PRESCALE    0xc7800C
  48 #define CX18_FAST_CLOCK_PLL_ADJUST_BANDWIDTH 0xc78010
  49
  50 #define CX18_SLOW_CLOCK_PLL_INT         0xc78014
  51 #define CX18_SLOW_CLOCK_PLL_FRAC        0xc78018
  52 #define CX18_SLOW_CLOCK_PLL_POST        0xc7801C
  53 #define CX18_MPEG_CLOCK_PLL_INT         0xc78040
  54 #define CX18_MPEG_CLOCK_PLL_FRAC        0xc78044
  55 #define CX18_MPEG_CLOCK_PLL_POST        0xc78048
  56 #define CX18_PLL_POWER_DOWN             0xc78088
  57 #define CX18_SW1_INT_STATUS             0xc73104
  58 #define CX18_SW1_INT_ENABLE_PCI         0xc7311C
  59 #define CX18_SW2_INT_SET                0xc73140
  60 #define CX18_SW2_INT_STATUS             0xc73144
  61 #define CX18_ADEC_CONTROL               0xc78120
  62
  63 #define CX18_DDR_REQUEST_ENABLE         0xc80000
  64 #define CX18_DDR_CHIP_CONFIG            0xc80004
  65 #define CX18_DDR_REFRESH                0xc80008
  66 #define CX18_DDR_TIMING1                0xc8000C
  67 #define CX18_DDR_TIMING2                0xc80010
  68 #define CX18_DDR_POWER_REG              0xc8001C
  69
  70 #define CX18_DDR_TUNE_LANE              0xc80048
  71 #define CX18_DDR_INITIAL_EMRS           0xc80054
  72 #define CX18_DDR_MB_PER_ROW_7           0xc8009C
  73 #define CX18_DDR_BASE_63_ADDR           0xc804FC
  74
  75 #define CX18_WMB_CLIENT02               0xc90108
  76 #define CX18_WMB_CLIENT05               0xc90114
  77 #define CX18_WMB_CLIENT06               0xc90118
  78 #define CX18_WMB_CLIENT07               0xc9011C
  79 #define CX18_WMB_CLIENT08               0xc90120
  80 #define CX18_WMB_CLIENT09               0xc90124
  81 #define CX18_WMB_CLIENT10               0xc90128
  82 #define CX18_WMB_CLIENT11               0xc9012C
  83 #define CX18_WMB_CLIENT12               0xc90130
  84 #define CX18_WMB_CLIENT13               0xc90134
  85 #define CX18_WMB_CLIENT14               0xc90138
  86
  87 #define CX18_DSP0_INTERRUPT_MASK        0xd0004C
  88
  89 #define APU_ROM_SYNC1 0x6D676553 /* "mgeS" */
  90 #define APU_ROM_SYNC2 0x72646548 /* "rdeH" */
  91
  92 struct cx18_apu_rom_seghdr {
  93         u32 sync1;
  94         u32 sync2;
  95         u32 addr;
  96         u32 size;
  97 };
  98
  99 static int load_cpu_fw_direct(const char *fn, u8 __iomem *mem, struct cx18 *cx)
 100 {
 101         const struct firmware *fw = NULL;
 102         int i, j;
 103         unsigned size;
 104         u32 __iomem *dst = (u32 __iomem *)mem;
 105         const u32 *src;
 106
 107         if (request_firmware(&fw, fn, &cx->dev->dev)) {
 108                 CX18_ERR("Unable to open firmware %s\n", fn);
 109                 CX18_ERR("Did you put the firmware in the hotplug firmware directory?\n");
 110                 return -ENOMEM;
 111         }
 112
 113         src = (const u32 *)fw->data;
 114
 115         for (i = 0; i < fw->size; i += 4096) {
 116                 setup_page(i);
 117                 for (j = i; j < fw->size && j < i + 4096; j += 4) {
 118                         /* no need for endianness conversion on the ppc */
 119                         __raw_writel(*src, dst);
 120                         if (__raw_readl(dst) != *src) {
 121                                 CX18_ERR("Mismatch at offset %x\n", i);
 122                                 release_firmware(fw);
 123                                 return -EIO;
 124                         }
 125                         dst++;
 126                         src++;
 127                 }
 128         }
 129         if (!test_bit(CX18_F_I_LOADED_FW, &cx->i_flags))
 130                 CX18_INFO("loaded %s firmware (%zd bytes)\n", fn, fw->size);
 131         size = fw->size;
 132         release_firmware(fw);
 133         return size;
 134 }
 135
 136 static int load_apu_fw_direct(const char *fn, u8 __iomem *dst, struct cx18 *cx)
 137 {
 138         const struct firmware *fw = NULL;
 139         int i, j;
 140         unsigned size;
 141         const u32 *src;
 142         struct cx18_apu_rom_seghdr seghdr;
 143         const u8 *vers;
 144         u32 offset = 0;
 145         u32 apu_version = 0;
 146         int sz;
 147
 148         if (request_firmware(&fw, fn, &cx->dev->dev)) {
 149                 CX18_ERR("unable to open firmware %s\n", fn);
 150                 CX18_ERR("did you put the firmware in the hotplug firmware directory?\n");
 151                 return -ENOMEM;
 152         }
 153
 154         src = (const u32 *)fw->data;
 155         vers = fw->data + sizeof(seghdr);
 156         sz = fw->size;
 157
 158         apu_version = (vers[0] << 24) | (vers[4] << 16) | vers[32];
 159         while (offset + sizeof(seghdr) < fw->size) {
 160                 /* TODO: byteswapping */
 161                 memcpy(&seghdr, src + offset / 4, sizeof(seghdr));
 162                 offset += sizeof(seghdr);
 163                 if (seghdr.sync1 != APU_ROM_SYNC1 ||
 164                     seghdr.sync2 != APU_ROM_SYNC2) {
 165                         offset += seghdr.size;
 166                         continue;
 167                 }
 168                 CX18_DEBUG_INFO("load segment %x-%x\n", seghdr.addr,
 169                                 seghdr.addr + seghdr.size - 1);
 170                 if (offset + seghdr.size > sz)
 171                         break;
 172                 for (i = 0; i < seghdr.size; i += 4096) {
 173                         setup_page(offset + i);
 174                         for (j = i; j < seghdr.size && j < i + 4096; j += 4) {
 175                                 /* no need for endianness conversion on the ppc */
 176                                 __raw_writel(src[(offset + j) / 4], dst + seghdr.addr + j);
 177                                 if (__raw_readl(dst + seghdr.addr + j) != src[(offset + j) / 4]) {
 178                                         CX18_ERR("Mismatch at offset %x\n", offset + j);
 179                                         release_firmware(fw);
 180                                         return -EIO;
 181                                 }
 182                         }
 183                 }
 184                 offset += seghdr.size;
 185         }
 186         if (!test_bit(CX18_F_I_LOADED_FW, &cx->i_flags))
 187                 CX18_INFO("loaded %s firmware V%08x (%zd bytes)\n",
 188                                 fn, apu_version, fw->size);
 189         size = fw->size;
 190         release_firmware(fw);
 191         /* Clear bit0 for APU to start from 0 */
 192         write_reg(read_reg(0xc72030) & ~1, 0xc72030);
 193         return size;
 194 }
 195
 196 void cx18_halt_firmware(struct cx18 *cx)
 197 {
 198         CX18_DEBUG_INFO("Preparing for firmware halt.\n");
 199         write_reg(0x000F000F, CX18_PROC_SOFT_RESET); /* stop the fw */
 200         write_reg(0x00020002, CX18_ADEC_CONTROL);
 201 }
 202
 203 void cx18_init_power(struct cx18 *cx, int lowpwr)
 204 {
 205         /* power-down Spare and AOM PLLs */
 206         /* power-up fast, slow and mpeg PLLs */
 207         write_reg(0x00000008, CX18_PLL_POWER_DOWN);
 208
 209         /* ADEC out of sleep */
 210         write_reg(0x00020000, CX18_ADEC_CONTROL);
 211
 212         /* The fast clock is at 200/245 MHz */
 213         write_reg(lowpwr ? 0xD : 0x11, CX18_FAST_CLOCK_PLL_INT);
 214         write_reg(lowpwr ? 0x1EFBF37 : 0x038E3D7, CX18_FAST_CLOCK_PLL_FRAC);
 215
 216         write_reg(2, CX18_FAST_CLOCK_PLL_POST);
 217         write_reg(1, CX18_FAST_CLOCK_PLL_PRESCALE);
 218         write_reg(4, CX18_FAST_CLOCK_PLL_ADJUST_BANDWIDTH);
 219
 220         /* set slow clock to 125/120 MHz */
 221         write_reg(lowpwr ? 0x11 : 0x10, CX18_SLOW_CLOCK_PLL_INT);
 222         write_reg(lowpwr ? 0xEBAF05 : 0x18618A8, CX18_SLOW_CLOCK_PLL_FRAC);
 223         write_reg(4, CX18_SLOW_CLOCK_PLL_POST);
 224
 225         /* mpeg clock pll 54MHz */
 226         write_reg(0xF, CX18_MPEG_CLOCK_PLL_INT);
 227         write_reg(0x2BCFEF, CX18_MPEG_CLOCK_PLL_FRAC);
 228         write_reg(8, CX18_MPEG_CLOCK_PLL_POST);
 229
 230         /* Defaults */
 231         /* APU = SC or SC/2 = 125/62.5 */
 232         /* EPU = SC = 125 */
 233         /* DDR = FC = 180 */
 234         /* ENC = SC = 125 */
 235         /* AI1 = SC = 125 */
 236         /* VIM2 = disabled */
 237         /* PCI = FC/2 = 90 */
 238         /* AI2 = disabled */
 239         /* DEMUX = disabled */
 240         /* AO = SC/2 = 62.5 */
 241         /* SER = 54MHz */
 242         /* VFC = disabled */
 243         /* USB = disabled */
 244
 245         write_reg(lowpwr ? 0xFFFF0020 : 0x00060004, CX18_CLOCK_SELECT1);
 246         write_reg(lowpwr ? 0xFFFF0004 : 0x00060006, CX18_CLOCK_SELECT2);
 247
 248         write_reg(0xFFFF0002, CX18_HALF_CLOCK_SELECT1);
 249         write_reg(0xFFFF0104, CX18_HALF_CLOCK_SELECT2);
 250
 251         write_reg(0xFFFF9026, CX18_CLOCK_ENABLE1);
 252         write_reg(0xFFFF3105, CX18_CLOCK_ENABLE2);
 253 }
 254
 255 void cx18_init_memory(struct cx18 *cx)
 256 {
 257         cx18_msleep_timeout(10, 0);
 258         write_reg(0x10000, CX18_DDR_SOFT_RESET);
 259         cx18_msleep_timeout(10, 0);
 260
 261         write_reg(cx->card->ddr.chip_config, CX18_DDR_CHIP_CONFIG);
 262
 263         cx18_msleep_timeout(10, 0);
 264
 265         write_reg(cx->card->ddr.refresh, CX18_DDR_REFRESH);
 266         write_reg(cx->card->ddr.timing1, CX18_DDR_TIMING1);
 267         write_reg(cx->card->ddr.timing2, CX18_DDR_TIMING2);
 268
 269         cx18_msleep_timeout(10, 0);
 270
 271         /* Initialize DQS pad time */
 272         write_reg(cx->card->ddr.tune_lane, CX18_DDR_TUNE_LANE);
 273         write_reg(cx->card->ddr.initial_emrs, CX18_DDR_INITIAL_EMRS);
 274
 275         cx18_msleep_timeout(10, 0);
 276
 277         write_reg(0x20000, CX18_DDR_SOFT_RESET);
 278         cx18_msleep_timeout(10, 0);
 279
 280         /* use power-down mode when idle */
 281         write_reg(0x00000010, CX18_DDR_POWER_REG);
 282
 283         write_reg(0x10001, CX18_REG_BUS_TIMEOUT_EN);
 284
 285         write_reg(0x48, CX18_DDR_MB_PER_ROW_7);
 286         write_reg(0xE0000, CX18_DDR_BASE_63_ADDR);
 287
 288         write_reg(0x00000101, CX18_WMB_CLIENT02);  /* AO */
 289         write_reg(0x00000101, CX18_WMB_CLIENT09);  /* AI2 */
 290         write_reg(0x00000101, CX18_WMB_CLIENT05);  /* VIM1 */
 291         write_reg(0x00000101, CX18_WMB_CLIENT06);  /* AI1 */
 292         write_reg(0x00000101, CX18_WMB_CLIENT07);  /* 3D comb */
 293         write_reg(0x00000101, CX18_WMB_CLIENT10);  /* ME */
 294         write_reg(0x00000101, CX18_WMB_CLIENT12);  /* ENC */
 295         write_reg(0x00000101, CX18_WMB_CLIENT13);  /* PK */
 296         write_reg(0x00000101, CX18_WMB_CLIENT11);  /* RC */
 297         write_reg(0x00000101, CX18_WMB_CLIENT14);  /* AVO */
 298 }
 299
 300 int cx18_firmware_init(struct cx18 *cx)
 301 {
 302         /* Allow chip to control CLKRUN */
 303         write_reg(0x5, CX18_DSP0_INTERRUPT_MASK);
 304
 305         write_reg(0x000F000F, CX18_PROC_SOFT_RESET); /* stop the fw */
 306
 307         cx18_msleep_timeout(1, 0);
 308
 309         sw1_irq_enable(IRQ_CPU_TO_EPU | IRQ_APU_TO_EPU);
 310         sw2_irq_enable(IRQ_CPU_TO_EPU_ACK | IRQ_APU_TO_EPU_ACK);
 311
 312         /* Only if the processor is not running */
 313         if (read_reg(CX18_PROC_SOFT_RESET) & 8) {
 314                 int sz = load_apu_fw_direct("v4l-cx23418-apu.fw",
 315                                cx->enc_mem, cx);
 316
 317                 write_enc(0xE51FF004, 0);
 318                 write_enc(0xa00000, 4);  /* todo: not hardcoded */
 319                 write_reg(0x00010000, CX18_PROC_SOFT_RESET); /* Start APU */
 320                 cx18_msleep_timeout(500, 0);
 321
 322                 sz = sz <= 0 ? sz : load_cpu_fw_direct("v4l-cx23418-cpu.fw",
 323                                         cx->enc_mem, cx);
 324
 325                 if (sz > 0) {
 326                         int retries = 0;
 327
 328                         /* start the CPU */
 329                         write_reg(0x00080000, CX18_PROC_SOFT_RESET);
 330                         while (retries++ < 50) { /* Loop for max 500mS */
 331                                 if ((read_reg(CX18_PROC_SOFT_RESET) & 1) == 0)
 332                                         break;
 333                                 cx18_msleep_timeout(10, 0);
 334                         }
 335                         cx18_msleep_timeout(200, 0);
 336                         if (retries == 51) {
 337                                 CX18_ERR("Could not start the CPU\n");
 338                                 return -EIO;
 339                         }
 340                 }
 341                 if (sz <= 0)
 342                         return -EIO;
 343         }
 344         /* initialize GPIO */
 345         write_reg(0x14001400, 0xC78110);
 346         return 0;
 347 }