2 * cx18 firmware functions
4 * Copyright (C) 2007 Hans Verkuil <hverkuil@xs4all.nl>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
22 #include "cx18-driver.h"
26 #include "cx18-firmware.h"
27 #include "cx18-cards.h"
28 #include <linux/firmware.h>
30 #define CX18_PROC_SOFT_RESET 0xc70010
31 #define CX18_DDR_SOFT_RESET 0xc70014
32 #define CX18_CLOCK_SELECT1 0xc71000
33 #define CX18_CLOCK_SELECT2 0xc71004
34 #define CX18_HALF_CLOCK_SELECT1 0xc71008
35 #define CX18_HALF_CLOCK_SELECT2 0xc7100C
36 #define CX18_CLOCK_POLARITY1 0xc71010
37 #define CX18_CLOCK_POLARITY2 0xc71014
38 #define CX18_ADD_DELAY_ENABLE1 0xc71018
39 #define CX18_ADD_DELAY_ENABLE2 0xc7101C
40 #define CX18_CLOCK_ENABLE1 0xc71020
41 #define CX18_CLOCK_ENABLE2 0xc71024
43 #define CX18_REG_BUS_TIMEOUT_EN 0xc72024
45 #define CX18_FAST_CLOCK_PLL_INT 0xc78000
46 #define CX18_FAST_CLOCK_PLL_FRAC 0xc78004
47 #define CX18_FAST_CLOCK_PLL_POST 0xc78008
48 #define CX18_FAST_CLOCK_PLL_PRESCALE 0xc7800C
49 #define CX18_FAST_CLOCK_PLL_ADJUST_BANDWIDTH 0xc78010
51 #define CX18_SLOW_CLOCK_PLL_INT 0xc78014
52 #define CX18_SLOW_CLOCK_PLL_FRAC 0xc78018
53 #define CX18_SLOW_CLOCK_PLL_POST 0xc7801C
54 #define CX18_MPEG_CLOCK_PLL_INT 0xc78040
55 #define CX18_MPEG_CLOCK_PLL_FRAC 0xc78044
56 #define CX18_MPEG_CLOCK_PLL_POST 0xc78048
57 #define CX18_PLL_POWER_DOWN 0xc78088
58 #define CX18_SW1_INT_STATUS 0xc73104
59 #define CX18_SW1_INT_ENABLE_PCI 0xc7311C
60 #define CX18_SW2_INT_SET 0xc73140
61 #define CX18_SW2_INT_STATUS 0xc73144
62 #define CX18_ADEC_CONTROL 0xc78120
64 #define CX18_DDR_REQUEST_ENABLE 0xc80000
65 #define CX18_DDR_CHIP_CONFIG 0xc80004
66 #define CX18_DDR_REFRESH 0xc80008
67 #define CX18_DDR_TIMING1 0xc8000C
68 #define CX18_DDR_TIMING2 0xc80010
69 #define CX18_DDR_POWER_REG 0xc8001C
71 #define CX18_DDR_TUNE_LANE 0xc80048
72 #define CX18_DDR_INITIAL_EMRS 0xc80054
73 #define CX18_DDR_MB_PER_ROW_7 0xc8009C
74 #define CX18_DDR_BASE_63_ADDR 0xc804FC
76 #define CX18_WMB_CLIENT02 0xc90108
77 #define CX18_WMB_CLIENT05 0xc90114
78 #define CX18_WMB_CLIENT06 0xc90118
79 #define CX18_WMB_CLIENT07 0xc9011C
80 #define CX18_WMB_CLIENT08 0xc90120
81 #define CX18_WMB_CLIENT09 0xc90124
82 #define CX18_WMB_CLIENT10 0xc90128
83 #define CX18_WMB_CLIENT11 0xc9012C
84 #define CX18_WMB_CLIENT12 0xc90130
85 #define CX18_WMB_CLIENT13 0xc90134
86 #define CX18_WMB_CLIENT14 0xc90138
88 #define CX18_DSP0_INTERRUPT_MASK 0xd0004C
90 #define APU_ROM_SYNC1 0x6D676553 /* "mgeS" */
91 #define APU_ROM_SYNC2 0x72646548 /* "rdeH" */
93 struct cx18_apu_rom_seghdr {
100 static int load_cpu_fw_direct(const char *fn, u8 __iomem *mem, struct cx18 *cx)
102 const struct firmware *fw = NULL;
105 u32 __iomem *dst = (u32 __iomem *)mem;
108 if (request_firmware(&fw, fn, &cx->dev->dev)) {
109 CX18_ERR("Unable to open firmware %s\n", fn);
110 CX18_ERR("Did you put the firmware in the hotplug firmware directory?\n");
114 src = (const u32 *)fw->data;
116 for (i = 0; i < fw->size; i += 4096) {
117 cx18_setup_page(cx, i);
118 for (j = i; j < fw->size && j < i + 4096; j += 4) {
119 /* no need for endianness conversion on the ppc */
120 cx18_raw_writel(cx, *src, dst);
121 if (cx18_raw_readl(cx, dst) != *src) {
122 CX18_ERR("Mismatch at offset %x\n", i);
123 release_firmware(fw);
130 if (!test_bit(CX18_F_I_LOADED_FW, &cx->i_flags))
131 CX18_INFO("loaded %s firmware (%zd bytes)\n", fn, fw->size);
133 release_firmware(fw);
137 static int load_apu_fw_direct(const char *fn, u8 __iomem *dst, struct cx18 *cx,
140 const struct firmware *fw = NULL;
144 struct cx18_apu_rom_seghdr seghdr;
150 if (request_firmware(&fw, fn, &cx->dev->dev)) {
151 CX18_ERR("unable to open firmware %s\n", fn);
152 CX18_ERR("did you put the firmware in the hotplug firmware directory?\n");
157 src = (const u32 *)fw->data;
158 vers = fw->data + sizeof(seghdr);
161 apu_version = (vers[0] << 24) | (vers[4] << 16) | vers[32];
162 while (offset + sizeof(seghdr) < fw->size) {
163 /* TODO: byteswapping */
164 memcpy(&seghdr, src + offset / 4, sizeof(seghdr));
165 offset += sizeof(seghdr);
166 if (seghdr.sync1 != APU_ROM_SYNC1 ||
167 seghdr.sync2 != APU_ROM_SYNC2) {
168 offset += seghdr.size;
171 CX18_DEBUG_INFO("load segment %x-%x\n", seghdr.addr,
172 seghdr.addr + seghdr.size - 1);
173 if (*entry_addr == 0)
174 *entry_addr = seghdr.addr;
175 if (offset + seghdr.size > sz)
177 for (i = 0; i < seghdr.size; i += 4096) {
178 cx18_setup_page(cx, seghdr.addr + i);
179 for (j = i; j < seghdr.size && j < i + 4096; j += 4) {
180 /* no need for endianness conversion on the ppc */
181 cx18_raw_writel(cx, src[(offset + j) / 4],
182 dst + seghdr.addr + j);
183 if (cx18_raw_readl(cx, dst + seghdr.addr + j)
184 != src[(offset + j) / 4]) {
185 CX18_ERR("Mismatch at offset %x\n",
187 release_firmware(fw);
192 offset += seghdr.size;
194 if (!test_bit(CX18_F_I_LOADED_FW, &cx->i_flags))
195 CX18_INFO("loaded %s firmware V%08x (%zd bytes)\n",
196 fn, apu_version, fw->size);
198 release_firmware(fw);
202 void cx18_halt_firmware(struct cx18 *cx)
204 CX18_DEBUG_INFO("Preparing for firmware halt.\n");
205 cx18_write_reg_expect(cx, 0x000F000F, CX18_PROC_SOFT_RESET,
206 0x0000000F, 0x000F000F);
207 cx18_write_reg_expect(cx, 0x00020002, CX18_ADEC_CONTROL,
208 0x00000002, 0x00020002);
211 void cx18_init_power(struct cx18 *cx, int lowpwr)
213 /* power-down Spare and AOM PLLs */
214 /* power-up fast, slow and mpeg PLLs */
215 cx18_write_reg(cx, 0x00000008, CX18_PLL_POWER_DOWN);
217 /* ADEC out of sleep */
218 cx18_write_reg_expect(cx, 0x00020000, CX18_ADEC_CONTROL,
219 0x00000000, 0x00020002);
221 /* The fast clock is at 200/245 MHz */
222 cx18_write_reg(cx, lowpwr ? 0xD : 0x11, CX18_FAST_CLOCK_PLL_INT);
223 cx18_write_reg(cx, lowpwr ? 0x1EFBF37 : 0x038E3D7,
224 CX18_FAST_CLOCK_PLL_FRAC);
226 cx18_write_reg(cx, 2, CX18_FAST_CLOCK_PLL_POST);
227 cx18_write_reg(cx, 1, CX18_FAST_CLOCK_PLL_PRESCALE);
228 cx18_write_reg(cx, 4, CX18_FAST_CLOCK_PLL_ADJUST_BANDWIDTH);
230 /* set slow clock to 125/120 MHz */
231 cx18_write_reg(cx, lowpwr ? 0x11 : 0x10, CX18_SLOW_CLOCK_PLL_INT);
232 cx18_write_reg(cx, lowpwr ? 0xEBAF05 : 0x18618A8,
233 CX18_SLOW_CLOCK_PLL_FRAC);
234 cx18_write_reg(cx, 4, CX18_SLOW_CLOCK_PLL_POST);
236 /* mpeg clock pll 54MHz */
237 cx18_write_reg(cx, 0xF, CX18_MPEG_CLOCK_PLL_INT);
238 cx18_write_reg(cx, 0x2BCFEF, CX18_MPEG_CLOCK_PLL_FRAC);
239 cx18_write_reg(cx, 8, CX18_MPEG_CLOCK_PLL_POST);
242 /* APU = SC or SC/2 = 125/62.5 */
247 /* VIM2 = disabled */
248 /* PCI = FC/2 = 90 */
250 /* DEMUX = disabled */
251 /* AO = SC/2 = 62.5 */
257 cx18_write_reg_expect(cx, 0xFFFF0020, CX18_CLOCK_SELECT1,
258 0x00000020, 0xFFFFFFFF);
259 cx18_write_reg_expect(cx, 0xFFFF0004, CX18_CLOCK_SELECT2,
260 0x00000004, 0xFFFFFFFF);
262 /* This doesn't explicitly set every clock select */
263 cx18_write_reg_expect(cx, 0x00060004, CX18_CLOCK_SELECT1,
264 0x00000004, 0x00060006);
265 cx18_write_reg_expect(cx, 0x00060006, CX18_CLOCK_SELECT2,
266 0x00000006, 0x00060006);
269 cx18_write_reg_expect(cx, 0xFFFF0002, CX18_HALF_CLOCK_SELECT1,
270 0x00000002, 0xFFFFFFFF);
271 cx18_write_reg_expect(cx, 0xFFFF0104, CX18_HALF_CLOCK_SELECT2,
272 0x00000104, 0xFFFFFFFF);
273 cx18_write_reg_expect(cx, 0xFFFF9026, CX18_CLOCK_ENABLE1,
274 0x00009026, 0xFFFFFFFF);
275 cx18_write_reg_expect(cx, 0xFFFF3105, CX18_CLOCK_ENABLE2,
276 0x00003105, 0xFFFFFFFF);
279 void cx18_init_memory(struct cx18 *cx)
281 cx18_msleep_timeout(10, 0);
282 cx18_write_reg_expect(cx, 0x00010000, CX18_DDR_SOFT_RESET,
283 0x00000000, 0x00010001);
284 cx18_msleep_timeout(10, 0);
286 cx18_write_reg(cx, cx->card->ddr.chip_config, CX18_DDR_CHIP_CONFIG);
288 cx18_msleep_timeout(10, 0);
290 cx18_write_reg(cx, cx->card->ddr.refresh, CX18_DDR_REFRESH);
291 cx18_write_reg(cx, cx->card->ddr.timing1, CX18_DDR_TIMING1);
292 cx18_write_reg(cx, cx->card->ddr.timing2, CX18_DDR_TIMING2);
294 cx18_msleep_timeout(10, 0);
296 /* Initialize DQS pad time */
297 cx18_write_reg(cx, cx->card->ddr.tune_lane, CX18_DDR_TUNE_LANE);
298 cx18_write_reg(cx, cx->card->ddr.initial_emrs, CX18_DDR_INITIAL_EMRS);
300 cx18_msleep_timeout(10, 0);
302 cx18_write_reg_expect(cx, 0x00020000, CX18_DDR_SOFT_RESET,
303 0x00000000, 0x00020002);
304 cx18_msleep_timeout(10, 0);
306 /* use power-down mode when idle */
307 cx18_write_reg(cx, 0x00000010, CX18_DDR_POWER_REG);
309 cx18_write_reg_expect(cx, 0x00010001, CX18_REG_BUS_TIMEOUT_EN,
310 0x00000001, 0x00010001);
312 cx18_write_reg(cx, 0x48, CX18_DDR_MB_PER_ROW_7);
313 cx18_write_reg(cx, 0xE0000, CX18_DDR_BASE_63_ADDR);
315 cx18_write_reg(cx, 0x00000101, CX18_WMB_CLIENT02); /* AO */
316 cx18_write_reg(cx, 0x00000101, CX18_WMB_CLIENT09); /* AI2 */
317 cx18_write_reg(cx, 0x00000101, CX18_WMB_CLIENT05); /* VIM1 */
318 cx18_write_reg(cx, 0x00000101, CX18_WMB_CLIENT06); /* AI1 */
319 cx18_write_reg(cx, 0x00000101, CX18_WMB_CLIENT07); /* 3D comb */
320 cx18_write_reg(cx, 0x00000101, CX18_WMB_CLIENT10); /* ME */
321 cx18_write_reg(cx, 0x00000101, CX18_WMB_CLIENT12); /* ENC */
322 cx18_write_reg(cx, 0x00000101, CX18_WMB_CLIENT13); /* PK */
323 cx18_write_reg(cx, 0x00000101, CX18_WMB_CLIENT11); /* RC */
324 cx18_write_reg(cx, 0x00000101, CX18_WMB_CLIENT14); /* AVO */
327 int cx18_firmware_init(struct cx18 *cx)
329 /* Allow chip to control CLKRUN */
330 cx18_write_reg(cx, 0x5, CX18_DSP0_INTERRUPT_MASK);
332 /* Stop the firmware */
333 cx18_write_reg_expect(cx, 0x000F000F, CX18_PROC_SOFT_RESET,
334 0x0000000F, 0x000F000F);
336 cx18_msleep_timeout(1, 0);
338 cx18_sw1_irq_enable(cx, IRQ_CPU_TO_EPU | IRQ_APU_TO_EPU);
339 cx18_sw2_irq_enable(cx, IRQ_CPU_TO_EPU_ACK | IRQ_APU_TO_EPU_ACK);
341 /* Only if the processor is not running */
342 if (cx18_read_reg(cx, CX18_PROC_SOFT_RESET) & 8) {
343 u32 fw_entry_addr = 0;
344 int sz = load_apu_fw_direct("v4l-cx23418-apu.fw",
345 cx->enc_mem, cx, &fw_entry_addr);
350 /* Clear bit0 for APU to start from 0 */
351 cx18_write_reg(cx, cx18_read_reg(cx, 0xc72030) & ~1, 0xc72030);
353 cx18_write_enc(cx, 0xE51FF004, 0); /* ldr pc, [pc, #-4] */
354 cx18_write_enc(cx, fw_entry_addr, 4);
357 cx18_write_reg_expect(cx, 0x00010000, CX18_PROC_SOFT_RESET,
358 0x00000000, 0x00010001);
359 cx18_msleep_timeout(500, 0);
361 sz = sz <= 0 ? sz : load_cpu_fw_direct("v4l-cx23418-cpu.fw",
368 cx18_write_reg_expect(cx,
369 0x00080000, CX18_PROC_SOFT_RESET,
370 0x00000000, 0x00080008);
371 while (retries++ < 50) { /* Loop for max 500mS */
372 if ((cx18_read_reg(cx, CX18_PROC_SOFT_RESET)
375 cx18_msleep_timeout(10, 0);
377 cx18_msleep_timeout(200, 0);
379 CX18_ERR("Could not start the CPU\n");
388 * The CPU firmware apparently sets up to receive an interrupt for it's
389 * outgoing IRQ_CPU_TO_EPU_ACK to us (*boggle*). We get an interrupt
390 * when it sends us an ack, but by the time we process it, that flag in
391 * the SW2 status register has been cleared by the CPU firmware.
392 * We'll prevent that not so useful behavior by clearing the CPU's
393 * interrupt enables for Ack IRQ's we want to process.
395 cx18_sw2_irq_disable_cpu(cx, IRQ_CPU_TO_EPU_ACK | IRQ_APU_TO_EPU_ACK);
397 /* initialize GPIO */
398 cx18_write_reg_expect(cx, 0x14001400, 0xc78110, 0x00001400, 0x14001400);