2 * Driver for the Conexant CX23885 PCIe bridge
4 * Copyright (c) 2006 Steven Toth <stoth@hauppauge.com>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 #ifndef _CX23885_REG_H_
23 #define _CX23885_REG_H_
28 0x00000000 -> 0x00009000 TX SRAM (Fifos)
29 0x00010000 -> 0x00013c00 RX SRAM CMDS + CDT
31 EACH CMDS struct is 0x80 bytes long
33 DMAx_PTR1 = 0x03040 address of first cluster
34 DMAx_PTR2 = 0x10600 address of the CDT
35 DMAx_CNT1 = cluster size in (bytes >> 4) -1
36 DMAx_CNT2 = total cdt size for all entries >> 3
38 Cluster Descriptor entry = 4 DWORDS
39 DWORD 0 -> ptr to cluster
44 Channel manager Data Structure entry = 20 DWORD
45 0 IntialProgramCounterLow
46 1 IntialProgramCounterHigh
47 2 ClusterDescriptorTableBase
48 3 ClusterDescriptorTableSize
49 4 InstructionQueueBase
50 5 InstructionQueueSize
57 /* Risc Instructions */
58 #define RISC_CNT_INC 0x00010000
59 #define RISC_CNT_RESET 0x00030000
60 #define RISC_IRQ1 0x01000000
61 #define RISC_IRQ2 0x02000000
62 #define RISC_EOL 0x04000000
63 #define RISC_SOL 0x08000000
64 #define RISC_WRITE 0x10000000
65 #define RISC_SKIP 0x20000000
66 #define RISC_JUMP 0x70000000
67 #define RISC_SYNC 0x80000000
68 #define RISC_RESYNC 0x80008000
69 #define RISC_READ 0x90000000
70 #define RISC_WRITERM 0xB0000000
71 #define RISC_WRITECM 0xC0000000
72 #define RISC_WRITECR 0xD0000000
74 //#define RISC_SYNC_ODD 0x80000000
75 //#define RISC_SYNC_EVEN 0x80000200
76 //#define RISC_RESYNC_ODD 0x80008000
77 //#define RISC_RESYNC_EVEN 0x80008200
80 #define RISC_WRITEC 0x50000000
81 #define RISC_READC 0xA0000000
84 #define RISC_IMM 0x00000001
86 //#define RISC_CNT_NONE 0x00000000
87 //#define RISC_CNT_RSVR 0x00020000
88 //#define RISC_JMP_SRP 0x01
90 /* Audio and Video Core */
91 #define HOST_REG1 0x00000000
92 #define HOST_REG2 0x00000001
93 #define HOST_REG3 0x00000002
95 /* Chip Configuration Registers */
96 #define CHIP_CTRL 0x00000100
97 #define AFE_CTRL 0x00000104
98 #define VID_PLL_INT_POST 0x00000108
99 #define VID_PLL_FRAC 0x0000010C
100 #define AUX_PLL_INT_POST 0x00000110
101 #define AUX_PLL_FRAC 0x00000114
102 #define SYS_PLL_INT_POST 0x00000118
103 #define SYS_PLL_FRAC 0x0000011C
104 #define PIN_CTRL 0x00000120
105 #define AUD_IO_CTRL 0x00000124
106 #define AUD_LOCK1 0x00000128
107 #define AUD_LOCK2 0x0000012C
108 #define POWER_CTRL 0x00000130
109 #define AFE_DIAG_CTRL1 0x00000134
110 #define AFE_DIAG_CTRL3 0x0000013C
111 #define PLL_DIAG_CTRL 0x00000140
112 #define AFE_CLK_OUT_CTRL 0x00000144
113 #define DLL1_DIAG_CTRL 0x0000015C
115 /* GPIO[23:19] Output Enable */
116 #define GPIO2_OUT_EN_REG 0x00000160
117 /* GPIO[23:19] Data Registers */
118 #define GPIO2 0x00000164
120 #define IFADC_CTRL 0x00000180
122 /* Infrared Remote Registers */
123 #define IR_CNTRL_REG 0x00000200
124 #define IR_TXCLK_REG 0x00000204
125 #define IR_RXCLK_REG 0x00000208
126 #define IR_CDUTY_REG 0x0000020C
127 #define IR_STAT_REG 0x00000210
128 #define IR_IRQEN_REG 0x00000214
129 #define IR_FILTR_REG 0x00000218
130 #define IR_FIFO_REG 0x0000023C
132 /* Video Decoder Registers */
133 #define MODE_CTRL 0x00000400
134 #define OUT_CTRL1 0x00000404
135 #define OUT_CTRL2 0x00000408
136 #define GEN_STAT 0x0000040C
137 #define INT_STAT_MASK 0x00000410
138 #define LUMA_CTRL 0x00000414
139 #define HSCALE_CTRL 0x00000418
140 #define VSCALE_CTRL 0x0000041C
141 #define CHROMA_CTRL 0x00000420
142 #define VBI_LINE_CTRL1 0x00000424
143 #define VBI_LINE_CTRL2 0x00000428
144 #define VBI_LINE_CTRL3 0x0000042C
145 #define VBI_LINE_CTRL4 0x00000430
146 #define VBI_LINE_CTRL5 0x00000434
147 #define VBI_FC_CFG 0x00000438
148 #define VBI_MISC_CFG1 0x0000043C
149 #define VBI_MISC_CFG2 0x00000440
150 #define VBI_PAY1 0x00000444
151 #define VBI_PAY2 0x00000448
152 #define VBI_CUST1_CFG1 0x0000044C
153 #define VBI_CUST1_CFG2 0x00000450
154 #define VBI_CUST1_CFG3 0x00000454
155 #define VBI_CUST2_CFG1 0x00000458
156 #define VBI_CUST2_CFG2 0x0000045C
157 #define VBI_CUST2_CFG3 0x00000460
158 #define VBI_CUST3_CFG1 0x00000464
159 #define VBI_CUST3_CFG2 0x00000468
160 #define VBI_CUST3_CFG3 0x0000046C
161 #define HORIZ_TIM_CTRL 0x00000470
162 #define VERT_TIM_CTRL 0x00000474
163 #define SRC_COMB_CFG 0x00000478
164 #define CHROMA_VBIOFF_CFG 0x0000047C
165 #define FIELD_COUNT 0x00000480
166 #define MISC_TIM_CTRL 0x00000484
167 #define DFE_CTRL1 0x00000488
168 #define DFE_CTRL2 0x0000048C
169 #define DFE_CTRL3 0x00000490
170 #define PLL_CTRL 0x00000494
171 #define HTL_CTRL 0x00000498
172 #define COMB_CTRL 0x0000049C
173 #define CRUSH_CTRL 0x000004A0
174 #define SOFT_RST_CTRL 0x000004A4
175 #define CX885_VERSION 0x000004B4
176 #define VBI_PASS_CTRL 0x000004BC
178 /* Audio Decoder Registers */
179 /* 8051 Configuration */
180 #define DL_CTL 0x00000800
181 #define STD_DET_STATUS 0x00000804
182 #define STD_DET_CTL 0x00000808
183 #define DW8051_INT 0x0000080C
184 #define GENERAL_CTL 0x00000810
185 #define AAGC_CTL 0x00000814
186 #define DEMATRIX_CTL 0x000008CC
187 #define PATH1_CTL1 0x000008D0
188 #define PATH1_VOL_CTL 0x000008D4
189 #define PATH1_EQ_CTL 0x000008D8
190 #define PATH1_SC_CTL 0x000008DC
191 #define PATH2_CTL1 0x000008E0
192 #define PATH2_VOL_CTL 0x000008E4
193 #define PATH2_EQ_CTL 0x000008E8
194 #define PATH2_SC_CTL 0x000008EC
196 /* Sample Rate Converter */
197 #define SRC_CTL 0x000008F0
198 #define SRC_LF_COEF 0x000008F4
199 #define SRC1_CTL 0x000008F8
200 #define SRC2_CTL 0x000008FC
201 #define SRC3_CTL 0x00000900
202 #define SRC4_CTL 0x00000904
203 #define SRC5_CTL 0x00000908
204 #define SRC6_CTL 0x0000090C
205 #define BAND_OUT_SEL 0x00000910
206 #define I2S_N_CTL 0x00000914
207 #define I2S_OUT_CTL 0x00000918
208 #define AUTOCONFIG_REG 0x000009C4
210 /* Audio ADC Registers */
211 #define DSM_CTRL1 0x00000000
212 #define DSM_CTRL2 0x00000001
213 #define CHP_EN_CTRL 0x00000002
214 #define CHP_CLK_CTRL1 0x00000004
215 #define CHP_CLK_CTRL2 0x00000005
216 #define BG_REF_CTRL 0x00000006
217 #define SD2_SW_CTRL1 0x00000008
218 #define SD2_SW_CTRL2 0x00000009
219 #define SD2_BIAS_CTRL 0x0000000A
220 #define AMP_BIAS_CTRL 0x0000000C
221 #define CH_PWR_CTRL1 0x0000000E
222 #define CH_PWR_CTRL2 0x0000000F
223 #define DSM_STATUS1 0x00000010
224 #define DSM_STATUS2 0x00000011
225 #define DIG_CTL1 0x00000012
226 #define DIG_CTL2 0x00000013
227 #define I2S_TX_CFG 0x0000001A
229 #define DEV_CNTRL2 0x00040000
230 #define PCI_INT_MSK 0x00040010
231 #define PCI_MSK_APB_DMA (1 << 12)
232 #define PCI_MSK_AL_WR (1 << 11)
233 #define PCI_MSK_AL_RD (1 << 10)
234 #define PCI_MSK_RISC_WR (1 << 9)
235 #define PCI_MSK_RISC_RD (1 << 8)
236 #define PCI_MSK_AUD_EXT (1 << 4)
237 #define PCI_MSK_AUD_INT (1 << 3)
238 #define PCI_MSK_VID_C (1 << 2)
239 #define PCI_MSK_VID_B (1 << 1)
240 #define PCI_MSK_VID_A 1
241 #define PCI_INT_STAT 0x00040014
242 #define PCI_INT_MSTAT 0x00040018
244 #define VID_A_INT_MSK 0x00040020
245 #define VID_A_INT_STAT 0x00040024
246 #define VID_A_INT_MSTAT 0x00040028
247 #define VID_A_INT_SSTAT 0x0004002C
249 #define VID_B_INT_MSK 0x00040030
250 #define VID_B_INT_STAT 0x00040034
251 #define VID_B_INT_MSTAT 0x00040038
252 #define VID_B_INT_SSTAT 0x0004003C
254 #define VID_C_INT_MSK 0x00040040
255 #define VID_C_MSK_BAD_PKT (1 << 20)
256 #define VID_C_MSK_OPC_ERR (1 << 16)
257 #define VID_C_MSK_SYNC (1 << 12)
258 #define VID_C_MSK_OF (1 << 8)
259 #define VID_C_MSK_RISCI2 (1 << 4)
260 #define VID_C_MSK_RISCI1 1
261 #define VID_C_INT_STAT 0x00040044
262 #define VID_C_INT_MSTAT 0x00040048
263 #define VID_C_INT_SSTAT 0x0004004C
265 #define AUDIO_INT_INT_MSK 0x00040050
266 #define AUDIO_INT_INT_STAT 0x00040054
267 #define AUDIO_INT_INT_MSTAT 0x00040058
268 #define AUDIO_INT_INT_SSTAT 0x0004005C
270 #define AUDIO_EXT_INT_MSK 0x00040060
271 #define AUDIO_EXT_INT_STAT 0x00040064
272 #define AUDIO_EXT_INT_MSTAT 0x00040068
273 #define AUDIO_EXT_INT_SSTAT 0x0004006C
275 #define RDR_CFG0 0x00050000
276 #define RDR_CFG1 0x00050004
277 #define RDR_TLCTL0 0x00050318
279 /* APB DMAC Current Buffer Pointer */
280 #define DMA1_PTR1 0x00100000
281 #define DMA2_PTR1 0x00100004
282 #define DMA3_PTR1 0x00100008
283 #define DMA4_PTR1 0x0010000C
284 #define DMA5_PTR1 0x00100010
285 #define DMA6_PTR1 0x00100014
286 #define DMA7_PTR1 0x00100018
287 #define DMA8_PTR1 0x0010001C
289 /* APB DMAC Current Table Pointer */
290 #define DMA1_PTR2 0x00100040
291 #define DMA2_PTR2 0x00100044
292 #define DMA3_PTR2 0x00100048
293 #define DMA4_PTR2 0x0010004C
294 #define DMA5_PTR2 0x00100050
295 #define DMA6_PTR2 0x00100054
296 #define DMA7_PTR2 0x00100058
297 #define DMA8_PTR2 0x0010005C
299 /* APB DMAC Buffer Limit */
300 #define DMA1_CNT1 0x00100080
301 #define DMA2_CNT1 0x00100084
302 #define DMA3_CNT1 0x00100088
303 #define DMA4_CNT1 0x0010008C
304 #define DMA5_CNT1 0x00100090
305 #define DMA6_CNT1 0x00100094
306 #define DMA7_CNT1 0x00100098
307 #define DMA8_CNT1 0x0010009C
309 /* APB DMAC Table Size */
310 #define DMA1_CNT2 0x001000C0
311 #define DMA2_CNT2 0x001000C4
312 #define DMA3_CNT2 0x001000C8
313 #define DMA4_CNT2 0x001000CC
314 #define DMA5_CNT2 0x001000D0
315 #define DMA6_CNT2 0x001000D4
316 #define DMA7_CNT2 0x001000D8
317 #define DMA8_CNT2 0x001000DC
320 #define TM_CNT_LDW 0x00110000
321 #define TM_CNT_UW 0x00110004
322 #define TM_LMT_LDW 0x00110008
323 #define TM_LMT_UW 0x0011000C
326 #define GP0_IO 0x00110010
327 #define GPIO_ISM 0x00110014
328 #define SOFT_RESET 0x0011001C
330 /* GPIO (417 Microsoftcontroller) RW Data */
331 #define MC417_RWD 0x00110020
333 /* GPIO (417 Microsoftcontroller) Output Enable, Low Active */
334 #define MC417_OEN 0x00110024
335 #define MC417_CTL 0x00110028
336 #define CLK_DELAY 0x00110048
337 #define PAD_CTRL 0x0011004C
339 /* Video A Interface */
340 #define VID_A_GPCNT 0x00130020
341 #define VBI_A_GPCNT 0x00130024
342 #define VID_A_GPCNT_CTL 0x00130030
343 #define VBI_A_GPCNT_CTL 0x00130034
344 #define VID_A_DMA_CTL 0x00130040
345 #define VID_A_VIP_CTRL 0x00130080
346 #define VID_A_PIXEL_FRMT 0x00130084
347 #define VID_A_VBI_CTRL 0x00130088
349 /* Video B Interface */
350 #define VID_B_DMA 0x00130100
351 #define VBI_B_DMA 0x00130108
352 #define VID_B_GPCNT 0x00130120
353 #define VBI_B_GPCNT 0x00130124
354 #define VID_B_GPCNT_CTL 0x00130130
355 #define VBI_B_GPCNT_CTL 0x00130134
356 #define VID_B_DMA_CTL 0x00130140
357 #define VID_B_SRC_SEL 0x00130144
358 #define VID_B_LNGTH 0x00130150
359 #define VID_B_HW_SOP_CTL 0x00130154
360 #define VID_B_GEN_CTL 0x00130158
361 #define VID_B_BD_PKT_STATUS 0x0013015C
362 #define VID_B_SOP_STATUS 0x00130160
363 #define VID_B_FIFO_OVFL_STAT 0x00130164
364 #define VID_B_VLD_MISC 0x00130168
365 #define VID_B_TS_CLK_EN 0x0013016C
366 #define VID_B_VIP_CTRL 0x00130180
367 #define VID_B_PIXEL_FRMT 0x00130184
369 /* Video C Interface */
370 #define VID_C_GPCNT 0x00130220
371 #define VID_C_GPCNT_CTL 0x00130230
372 #define VBI_C_GPCNT_CTL 0x00130234
373 #define VID_C_DMA_CTL 0x00130240
374 #define VID_C_LNGTH 0x00130250
375 #define VID_C_HW_SOP_CTL 0x00130254
376 #define VID_C_GEN_CTL 0x00130258
377 #define VID_C_BD_PKT_STATUS 0x0013025C
378 #define VID_C_SOP_STATUS 0x00130260
379 #define VID_C_FIFO_OVFL_STAT 0x00130264
380 #define VID_C_VLD_MISC 0x00130268
381 #define VID_C_TS_CLK_EN 0x0013026C
383 /* Internal Audio Interface */
384 #define AUD_INT_A_GPCNT 0x00140020
385 #define AUD_INT_B_GPCNT 0x00140024
386 #define AUD_INT_A_GPCNT_CTL 0x00140030
387 #define AUD_INT_B_GPCNT_CTL 0x00140034
388 #define AUD_INT_DMA_CTL 0x00140040
389 #define AUD_INT_A_LNGTH 0x00140050
390 #define AUD_INT_B_LNGTH 0x00140054
391 #define AUD_INT_A_MODE 0x00140058
392 #define AUD_INT_B_MODE 0x0014005C
394 /* External Audio Interface */
395 #define AUD_EXT_DMA 0x00140100
396 #define AUD_EXT_GPCNT 0x00140120
397 #define AUD_EXT_GPCNT_CTL 0x00140130
398 #define AUD_EXT_DMA_CTL 0x00140140
399 #define AUD_EXT_LNGTH 0x00140150
400 #define AUD_EXT_A_MODE 0x00140158
403 #define I2C1_ADDR 0x00180000
404 #define I2C1_WDATA 0x00180004
405 #define I2C1_CTRL 0x00180008
406 #define I2C1_RDATA 0x0018000C
407 #define I2C1_STAT 0x00180010
410 #define I2C2_ADDR 0x00190000
411 #define I2C2_WDATA 0x00190004
412 #define I2C2_CTRL 0x00190008
413 #define I2C2_RDATA 0x0019000C
414 #define I2C2_STAT 0x00190010
417 #define I2C3_ADDR 0x001A0000
418 #define I2C3_WDATA 0x001A0004
419 #define I2C3_CTRL 0x001A0008
420 #define I2C3_RDATA 0x001A000C
421 #define I2C3_STAT 0x001A0010
424 #define UART_CTL 0x001B0000
425 #define UART_BRD 0x001B0004
426 #define UART_ISR 0x001B000C
427 #define UART_CNT 0x001B0010
429 #endif /* _CX23885_REG_H_ */