drivers/media/video/pvrusb2/pvrusb2-hdw.c

   1 /*
   2  *
   3  *  $Id$
   4  *
   5  *  Copyright (C) 2005 Mike Isely <isely@pobox.com>
   6  *
   7  *  This program is free software; you can redistribute it and/or modify
   8  *  it under the terms of the GNU General Public License as published by
   9  *  the Free Software Foundation; either version 2 of the License
  10  *
  11  *  This program is distributed in the hope that it will be useful,
  12  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  *  GNU General Public License for more details.
  15  *
  16  *  You should have received a copy of the GNU General Public License
  17  *  along with this program; if not, write to the Free Software
  18  *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  19  *
  20  */
  21
  22 #include <linux/errno.h>
  23 #include <linux/string.h>
  24 #include <linux/slab.h>
  25 #include <linux/firmware.h>
  26 #include <linux/videodev2.h>
  27 #include <asm/semaphore.h>
  28 #include "pvrusb2.h"
  29 #include "pvrusb2-std.h"
  30 #include "pvrusb2-util.h"
  31 #include "pvrusb2-hdw.h"
  32 #include "pvrusb2-i2c-core.h"
  33 #include "pvrusb2-tuner.h"
  34 #include "pvrusb2-eeprom.h"
  35 #include "pvrusb2-hdw-internal.h"
  36 #include "pvrusb2-encoder.h"
  37 #include "pvrusb2-debug.h"
  38
  39 struct usb_device_id pvr2_device_table[] = {
  40         [PVR2_HDW_TYPE_29XXX] = { USB_DEVICE(0x2040, 0x2900) },
  41 #ifdef CONFIG_VIDEO_PVRUSB2_24XXX
  42         [PVR2_HDW_TYPE_24XXX] = { USB_DEVICE(0x2040, 0x2400) },
  43 #endif
  44         { }
  45 };
  46
  47 MODULE_DEVICE_TABLE(usb, pvr2_device_table);
  48
  49 static const char *pvr2_device_names[] = {
  50         [PVR2_HDW_TYPE_29XXX] = "WinTV PVR USB2 Model Category 29xxxx",
  51 #ifdef CONFIG_VIDEO_PVRUSB2_24XXX
  52         [PVR2_HDW_TYPE_24XXX] = "WinTV PVR USB2 Model Category 24xxxx",
  53 #endif
  54 };
  55
  56 struct pvr2_string_table {
  57         const char **lst;
  58         unsigned int cnt;
  59 };
  60
  61 #ifdef CONFIG_VIDEO_PVRUSB2_24XXX
  62 // Names of other client modules to request for 24xxx model hardware
  63 static const char *pvr2_client_24xxx[] = {
  64         "cx25840",
  65         "tuner",
  66         "wm8775",
  67 };
  68 #endif
  69
  70 // Names of other client modules to request for 29xxx model hardware
  71 static const char *pvr2_client_29xxx[] = {
  72         "msp3400",
  73         "saa7115",
  74         "tuner",
  75 };
  76
  77 static struct pvr2_string_table pvr2_client_lists[] = {
  78         [PVR2_HDW_TYPE_29XXX] = {
  79                 pvr2_client_29xxx,
  80                 sizeof(pvr2_client_29xxx)/sizeof(pvr2_client_29xxx[0]),
  81         },
  82 #ifdef CONFIG_VIDEO_PVRUSB2_24XXX
  83         [PVR2_HDW_TYPE_24XXX] = {
  84                 pvr2_client_24xxx,
  85                 sizeof(pvr2_client_24xxx)/sizeof(pvr2_client_24xxx[0]),
  86         },
  87 #endif
  88 };
  89
  90 static struct pvr2_hdw *unit_pointers[PVR_NUM] = {[ 0 ... PVR_NUM-1 ] = NULL};
  91 static DECLARE_MUTEX(pvr2_unit_sem);
  92
  93 static int ctlchg = 0;
  94 static int initusbreset = 1;
  95 static int procreload = 0;
  96 static int tuner[PVR_NUM] = { [0 ... PVR_NUM-1] = -1 };
  97 static int tolerance[PVR_NUM] = { [0 ... PVR_NUM-1] = 0 };
  98 static int video_std[PVR_NUM] = { [0 ... PVR_NUM-1] = 0 };
  99 static int init_pause_msec = 0;
 100
 101 module_param(ctlchg, int, S_IRUGO|S_IWUSR);
 102 MODULE_PARM_DESC(ctlchg, "0=optimize ctl change 1=always accept new ctl value");
 103 module_param(init_pause_msec, int, S_IRUGO|S_IWUSR);
 104 MODULE_PARM_DESC(init_pause_msec, "hardware initialization settling delay");
 105 module_param(initusbreset, int, S_IRUGO|S_IWUSR);
 106 MODULE_PARM_DESC(initusbreset, "Do USB reset device on probe");
 107 module_param(procreload, int, S_IRUGO|S_IWUSR);
 108 MODULE_PARM_DESC(procreload,
 109                  "Attempt init failure recovery with firmware reload");
 110 module_param_array(tuner,    int, NULL, 0444);
 111 MODULE_PARM_DESC(tuner,"specify installed tuner type");
 112 module_param_array(video_std,    int, NULL, 0444);
 113 MODULE_PARM_DESC(video_std,"specify initial video standard");
 114 module_param_array(tolerance,    int, NULL, 0444);
 115 MODULE_PARM_DESC(tolerance,"specify stream error tolerance");
 116
 117 #define PVR2_CTL_WRITE_ENDPOINT  0x01
 118 #define PVR2_CTL_READ_ENDPOINT   0x81
 119
 120 #define PVR2_GPIO_IN 0x9008
 121 #define PVR2_GPIO_OUT 0x900c
 122 #define PVR2_GPIO_DIR 0x9020
 123
 124 #define trace_firmware(...) pvr2_trace(PVR2_TRACE_FIRMWARE,__VA_ARGS__)
 125
 126 #define PVR2_FIRMWARE_ENDPOINT   0x02
 127
 128 /* size of a firmware chunk */
 129 #define FIRMWARE_CHUNK_SIZE 0x2000
 130
 131 /* Define the list of additional controls we'll dynamically construct based
 132    on query of the cx2341x module. */
 133 struct pvr2_mpeg_ids {
 134         const char *strid;
 135         int id;
 136 };
 137 static const struct pvr2_mpeg_ids mpeg_ids[] = {
 138         {
 139                 .strid = "audio_layer",
 140                 .id = V4L2_CID_MPEG_AUDIO_ENCODING,
 141         },{
 142                 .strid = "audio_bitrate",
 143                 .id = V4L2_CID_MPEG_AUDIO_L2_BITRATE,
 144         },{
 145                 /* Already using audio_mode elsewhere :-( */
 146                 .strid = "mpeg_audio_mode",
 147                 .id = V4L2_CID_MPEG_AUDIO_MODE,
 148         },{
 149                 .strid = "mpeg_audio_mode_extension",
 150                 .id = V4L2_CID_MPEG_AUDIO_MODE_EXTENSION,
 151         },{
 152                 .strid = "audio_emphasis",
 153                 .id = V4L2_CID_MPEG_AUDIO_EMPHASIS,
 154         },{
 155                 .strid = "audio_crc",
 156                 .id = V4L2_CID_MPEG_AUDIO_CRC,
 157         },{
 158                 .strid = "video_aspect",
 159                 .id = V4L2_CID_MPEG_VIDEO_ASPECT,
 160         },{
 161                 .strid = "video_b_frames",
 162                 .id = V4L2_CID_MPEG_VIDEO_B_FRAMES,
 163         },{
 164                 .strid = "video_gop_size",
 165                 .id = V4L2_CID_MPEG_VIDEO_GOP_SIZE,
 166         },{
 167                 .strid = "video_gop_closure",
 168                 .id = V4L2_CID_MPEG_VIDEO_GOP_CLOSURE,
 169         },{
 170                 .strid = "video_pulldown",
 171                 .id = V4L2_CID_MPEG_VIDEO_PULLDOWN,
 172         },{
 173                 .strid = "video_bitrate_mode",
 174                 .id = V4L2_CID_MPEG_VIDEO_BITRATE_MODE,
 175         },{
 176                 .strid = "video_bitrate",
 177                 .id = V4L2_CID_MPEG_VIDEO_BITRATE,
 178         },{
 179                 .strid = "video_bitrate_peak",
 180                 .id = V4L2_CID_MPEG_VIDEO_BITRATE_PEAK,
 181         },{
 182                 .strid = "video_temporal_decimation",
 183                 .id = V4L2_CID_MPEG_VIDEO_TEMPORAL_DECIMATION,
 184         },{
 185                 .strid = "stream_type",
 186                 .id = V4L2_CID_MPEG_STREAM_TYPE,
 187         },{
 188                 .strid = "video_spatial_filter_mode",
 189                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER_MODE,
 190         },{
 191                 .strid = "video_spatial_filter",
 192                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER,
 193         },{
 194                 .strid = "video_luma_spatial_filter_type",
 195                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_SPATIAL_FILTER_TYPE,
 196         },{
 197                 .strid = "video_chroma_spatial_filter_type",
 198                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_SPATIAL_FILTER_TYPE,
 199         },{
 200                 .strid = "video_temporal_filter_mode",
 201                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER_MODE,
 202         },{
 203                 .strid = "video_temporal_filter",
 204                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER,
 205         },{
 206                 .strid = "video_median_filter_type",
 207                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_MEDIAN_FILTER_TYPE,
 208         },{
 209                 .strid = "video_luma_median_filter_top",
 210                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_TOP,
 211         },{
 212                 .strid = "video_luma_median_filter_bottom",
 213                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_BOTTOM,
 214         },{
 215                 .strid = "video_chroma_median_filter_top",
 216                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_TOP,
 217         },{
 218                 .strid = "video_chroma_median_filter_bottom",
 219                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_BOTTOM,
 220         }
 221 };
 222 #define MPEGDEF_COUNT (sizeof(mpeg_ids)/sizeof(mpeg_ids[0]))
 223
 224
 225 static const char *control_values_srate[] = {
 226         [V4L2_MPEG_AUDIO_SAMPLING_FREQ_44100]   = "44.1 kHz",
 227         [V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000]   = "48 kHz",
 228         [V4L2_MPEG_AUDIO_SAMPLING_FREQ_32000]   = "32 kHz",
 229 };
 230
 231
 232
 233 static const char *control_values_input[] = {
 234         [PVR2_CVAL_INPUT_TV]        = "television",  /*xawtv needs this name*/
 235         [PVR2_CVAL_INPUT_RADIO]     = "radio",
 236         [PVR2_CVAL_INPUT_SVIDEO]    = "s-video",
 237         [PVR2_CVAL_INPUT_COMPOSITE] = "composite",
 238 };
 239
 240
 241 static const char *control_values_audiomode[] = {
 242         [V4L2_TUNER_MODE_MONO]   = "Mono",
 243         [V4L2_TUNER_MODE_STEREO] = "Stereo",
 244         [V4L2_TUNER_MODE_LANG1]  = "Lang1",
 245         [V4L2_TUNER_MODE_LANG2]  = "Lang2",
 246         [V4L2_TUNER_MODE_LANG1_LANG2] = "Lang1+Lang2",
 247 };
 248
 249
 250 static const char *control_values_hsm[] = {
 251         [PVR2_CVAL_HSM_FAIL] = "Fail",
 252         [PVR2_CVAL_HSM_HIGH] = "High",
 253         [PVR2_CVAL_HSM_FULL] = "Full",
 254 };
 255
 256
 257 static const char *control_values_subsystem[] = {
 258         [PVR2_SUBSYS_B_ENC_FIRMWARE]  = "enc_firmware",
 259         [PVR2_SUBSYS_B_ENC_CFG] = "enc_config",
 260         [PVR2_SUBSYS_B_DIGITIZER_RUN] = "digitizer_run",
 261         [PVR2_SUBSYS_B_USBSTREAM_RUN] = "usbstream_run",
 262         [PVR2_SUBSYS_B_ENC_RUN] = "enc_run",
 263 };
 264
 265 static int pvr2_hdw_cmd_usbstream(struct pvr2_hdw *hdw,int runFl);
 266 static int pvr2_hdw_commit_ctl_internal(struct pvr2_hdw *hdw);
 267 static int pvr2_hdw_get_eeprom_addr(struct pvr2_hdw *hdw);
 268 static unsigned int pvr2_hdw_get_signal_status_internal(struct pvr2_hdw *hdw);
 269 static void pvr2_hdw_internal_find_stdenum(struct pvr2_hdw *hdw);
 270 static void pvr2_hdw_internal_set_std_avail(struct pvr2_hdw *hdw);
 271 static void pvr2_hdw_render_useless_unlocked(struct pvr2_hdw *hdw);
 272 static void pvr2_hdw_subsys_bit_chg_no_lock(struct pvr2_hdw *hdw,
 273                                             unsigned long msk,
 274                                             unsigned long val);
 275 static void pvr2_hdw_subsys_stream_bit_chg_no_lock(struct pvr2_hdw *hdw,
 276                                                    unsigned long msk,
 277                                                    unsigned long val);
 278 static int pvr2_send_request_ex(struct pvr2_hdw *hdw,
 279                                 unsigned int timeout,int probe_fl,
 280                                 void *write_data,unsigned int write_len,
 281                                 void *read_data,unsigned int read_len);
 282 static int pvr2_write_u16(struct pvr2_hdw *hdw, u16 data, int res);
 283 static int pvr2_write_u8(struct pvr2_hdw *hdw, u8 data, int res);
 284
 285 static int ctrl_channelfreq_get(struct pvr2_ctrl *cptr,int *vp)
 286 {
 287         struct pvr2_hdw *hdw = cptr->hdw;
 288         if ((hdw->freqProgSlot > 0) && (hdw->freqProgSlot <= FREQTABLE_SIZE)) {
 289                 *vp = hdw->freqTable[hdw->freqProgSlot-1];
 290         } else {
 291                 *vp = 0;
 292         }
 293         return 0;
 294 }
 295
 296 static int ctrl_channelfreq_set(struct pvr2_ctrl *cptr,int m,int v)
 297 {
 298         struct pvr2_hdw *hdw = cptr->hdw;
 299         if ((hdw->freqProgSlot > 0) && (hdw->freqProgSlot <= FREQTABLE_SIZE)) {
 300                 hdw->freqTable[hdw->freqProgSlot-1] = v;
 301         }
 302         return 0;
 303 }
 304
 305 static int ctrl_channelprog_get(struct pvr2_ctrl *cptr,int *vp)
 306 {
 307         *vp = cptr->hdw->freqProgSlot;
 308         return 0;
 309 }
 310
 311 static int ctrl_channelprog_set(struct pvr2_ctrl *cptr,int m,int v)
 312 {
 313         struct pvr2_hdw *hdw = cptr->hdw;
 314         if ((v >= 0) && (v <= FREQTABLE_SIZE)) {
 315                 hdw->freqProgSlot = v;
 316         }
 317         return 0;
 318 }
 319
 320 static int ctrl_channel_get(struct pvr2_ctrl *cptr,int *vp)
 321 {
 322         *vp = cptr->hdw->freqSlot;
 323         return 0;
 324 }
 325
 326 static int ctrl_channel_set(struct pvr2_ctrl *cptr,int m,int v)
 327 {
 328         unsigned freq = 0;
 329         struct pvr2_hdw *hdw = cptr->hdw;
 330         hdw->freqSlot = v;
 331         if ((hdw->freqSlot > 0) && (hdw->freqSlot <= FREQTABLE_SIZE)) {
 332                 freq = hdw->freqTable[hdw->freqSlot-1];
 333         }
 334         if (freq && (freq != hdw->freqVal)) {
 335                 hdw->freqVal = freq;
 336                 hdw->freqDirty = !0;
 337         }
 338         return 0;
 339 }
 340
 341 static int ctrl_freq_get(struct pvr2_ctrl *cptr,int *vp)
 342 {
 343         *vp = cptr->hdw->freqVal;
 344         return 0;
 345 }
 346
 347 static int ctrl_freq_is_dirty(struct pvr2_ctrl *cptr)
 348 {
 349         return cptr->hdw->freqDirty != 0;
 350 }
 351
 352 static void ctrl_freq_clear_dirty(struct pvr2_ctrl *cptr)
 353 {
 354         cptr->hdw->freqDirty = 0;
 355 }
 356
 357 static int ctrl_freq_set(struct pvr2_ctrl *cptr,int m,int v)
 358 {
 359         struct pvr2_hdw *hdw = cptr->hdw;
 360         hdw->freqVal = v;
 361         hdw->freqDirty = !0;
 362         hdw->freqSlot = 0;
 363         return 0;
 364 }
 365
 366 #ifdef CONFIG_VIDEO_PVRUSB2_24XXX
 367 static int ctrl_hres_max_get(struct pvr2_ctrl *cptr,int *vp)
 368 {
 369         /* If we're dealing with a 24xxx device, force the horizontal
 370            maximum to be 720 no matter what, since we can't get the device
 371            to work properly with any other value.  Otherwise just return
 372            the normal value. */
 373         *vp = cptr->info->def.type_int.max_value;
 374         if (cptr->hdw->hdw_type == PVR2_HDW_TYPE_24XXX) *vp = 720;
 375         return 0;
 376 }
 377
 378 static int ctrl_hres_min_get(struct pvr2_ctrl *cptr,int *vp)
 379 {
 380         /* If we're dealing with a 24xxx device, force the horizontal
 381            minimum to be 720 no matter what, since we can't get the device
 382            to work properly with any other value.  Otherwise just return
 383            the normal value. */
 384         *vp = cptr->info->def.type_int.min_value;
 385         if (cptr->hdw->hdw_type == PVR2_HDW_TYPE_24XXX) *vp = 720;
 386         return 0;
 387 }
 388 #endif
 389
 390 static int ctrl_cx2341x_is_dirty(struct pvr2_ctrl *cptr)
 391 {
 392         return cptr->hdw->enc_stale != 0;
 393 }
 394
 395 static void ctrl_cx2341x_clear_dirty(struct pvr2_ctrl *cptr)
 396 {
 397         cptr->hdw->enc_stale = 0;
 398 }
 399
 400 static int ctrl_cx2341x_get(struct pvr2_ctrl *cptr,int *vp)
 401 {
 402         int ret;
 403         struct v4l2_ext_controls cs;
 404         struct v4l2_ext_control c1;
 405         memset(&cs,0,sizeof(cs));
 406         memset(&c1,0,sizeof(c1));
 407         cs.controls = &c1;
 408         cs.count = 1;
 409         c1.id = cptr->info->v4l_id;
 410         ret = cx2341x_ext_ctrls(&cptr->hdw->enc_ctl_state,&cs,
 411                                 VIDIOC_G_EXT_CTRLS);
 412         if (ret) return ret;
 413         *vp = c1.value;
 414         return 0;
 415 }
 416
 417 static int ctrl_cx2341x_set(struct pvr2_ctrl *cptr,int m,int v)
 418 {
 419         int ret;
 420         struct v4l2_ext_controls cs;
 421         struct v4l2_ext_control c1;
 422         memset(&cs,0,sizeof(cs));
 423         memset(&c1,0,sizeof(c1));
 424         cs.controls = &c1;
 425         cs.count = 1;
 426         c1.id = cptr->info->v4l_id;
 427         c1.value = v;
 428         ret = cx2341x_ext_ctrls(&cptr->hdw->enc_ctl_state,&cs,
 429                                 VIDIOC_S_EXT_CTRLS);
 430         if (ret) return ret;
 431         cptr->hdw->enc_stale = !0;
 432         return 0;
 433 }
 434
 435 static unsigned int ctrl_cx2341x_getv4lflags(struct pvr2_ctrl *cptr)
 436 {
 437         struct v4l2_queryctrl qctrl;
 438         struct pvr2_ctl_info *info;
 439         qctrl.id = cptr->info->v4l_id;
 440         cx2341x_ctrl_query(&cptr->hdw->enc_ctl_state,&qctrl);
 441         /* Strip out the const so we can adjust a function pointer.  It's
 442            OK to do this here because we know this is a dynamically created
 443            control, so the underlying storage for the info pointer is (a)
 444            private to us, and (b) not in read-only storage.  Either we do
 445            this or we significantly complicate the underlying control
 446            implementation. */
 447         info = (struct pvr2_ctl_info *)(cptr->info);
 448         if (qctrl.flags & V4L2_CTRL_FLAG_READ_ONLY) {
 449                 if (info->set_value) {
 450                         info->set_value = NULL;
 451                 }
 452         } else {
 453                 if (!(info->set_value)) {
 454                         info->set_value = ctrl_cx2341x_set;
 455                 }
 456         }
 457         return qctrl.flags;
 458 }
 459
 460 static int ctrl_streamingenabled_get(struct pvr2_ctrl *cptr,int *vp)
 461 {
 462         *vp = cptr->hdw->flag_streaming_enabled;
 463         return 0;
 464 }
 465
 466 static int ctrl_hsm_get(struct pvr2_ctrl *cptr,int *vp)
 467 {
 468         int result = pvr2_hdw_is_hsm(cptr->hdw);
 469         *vp = PVR2_CVAL_HSM_FULL;
 470         if (result < 0) *vp = PVR2_CVAL_HSM_FAIL;
 471         if (result) *vp = PVR2_CVAL_HSM_HIGH;
 472         return 0;
 473 }
 474
 475 static int ctrl_stdavail_get(struct pvr2_ctrl *cptr,int *vp)
 476 {
 477         *vp = cptr->hdw->std_mask_avail;
 478         return 0;
 479 }
 480
 481 static int ctrl_stdavail_set(struct pvr2_ctrl *cptr,int m,int v)
 482 {
 483         struct pvr2_hdw *hdw = cptr->hdw;
 484         v4l2_std_id ns;
 485         ns = hdw->std_mask_avail;
 486         ns = (ns & ~m) | (v & m);
 487         if (ns == hdw->std_mask_avail) return 0;
 488         hdw->std_mask_avail = ns;
 489         pvr2_hdw_internal_set_std_avail(hdw);
 490         pvr2_hdw_internal_find_stdenum(hdw);
 491         return 0;
 492 }
 493
 494 static int ctrl_std_val_to_sym(struct pvr2_ctrl *cptr,int msk,int val,
 495                                char *bufPtr,unsigned int bufSize,
 496                                unsigned int *len)
 497 {
 498         *len = pvr2_std_id_to_str(bufPtr,bufSize,msk & val);
 499         return 0;
 500 }
 501
 502 static int ctrl_std_sym_to_val(struct pvr2_ctrl *cptr,
 503                                const char *bufPtr,unsigned int bufSize,
 504                                int *mskp,int *valp)
 505 {
 506         int ret;
 507         v4l2_std_id id;
 508         ret = pvr2_std_str_to_id(&id,bufPtr,bufSize);
 509         if (ret < 0) return ret;
 510         if (mskp) *mskp = id;
 511         if (valp) *valp = id;
 512         return 0;
 513 }
 514
 515 static int ctrl_stdcur_get(struct pvr2_ctrl *cptr,int *vp)
 516 {
 517         *vp = cptr->hdw->std_mask_cur;
 518         return 0;
 519 }
 520
 521 static int ctrl_stdcur_set(struct pvr2_ctrl *cptr,int m,int v)
 522 {
 523         struct pvr2_hdw *hdw = cptr->hdw;
 524         v4l2_std_id ns;
 525         ns = hdw->std_mask_cur;
 526         ns = (ns & ~m) | (v & m);
 527         if (ns == hdw->std_mask_cur) return 0;
 528         hdw->std_mask_cur = ns;
 529         hdw->std_dirty = !0;
 530         pvr2_hdw_internal_find_stdenum(hdw);
 531         return 0;
 532 }
 533
 534 static int ctrl_stdcur_is_dirty(struct pvr2_ctrl *cptr)
 535 {
 536         return cptr->hdw->std_dirty != 0;
 537 }
 538
 539 static void ctrl_stdcur_clear_dirty(struct pvr2_ctrl *cptr)
 540 {
 541         cptr->hdw->std_dirty = 0;
 542 }
 543
 544 static int ctrl_signal_get(struct pvr2_ctrl *cptr,int *vp)
 545 {
 546         *vp = ((pvr2_hdw_get_signal_status_internal(cptr->hdw) &
 547                 PVR2_SIGNAL_OK) ? 1 : 0);
 548         return 0;
 549 }
 550
 551 static int ctrl_subsys_get(struct pvr2_ctrl *cptr,int *vp)
 552 {
 553         *vp = cptr->hdw->subsys_enabled_mask;
 554         return 0;
 555 }
 556
 557 static int ctrl_subsys_set(struct pvr2_ctrl *cptr,int m,int v)
 558 {
 559         pvr2_hdw_subsys_bit_chg_no_lock(cptr->hdw,m,v);
 560         return 0;
 561 }
 562
 563 static int ctrl_subsys_stream_get(struct pvr2_ctrl *cptr,int *vp)
 564 {
 565         *vp = cptr->hdw->subsys_stream_mask;
 566         return 0;
 567 }
 568
 569 static int ctrl_subsys_stream_set(struct pvr2_ctrl *cptr,int m,int v)
 570 {
 571         pvr2_hdw_subsys_stream_bit_chg_no_lock(cptr->hdw,m,v);
 572         return 0;
 573 }
 574
 575 static int ctrl_stdenumcur_set(struct pvr2_ctrl *cptr,int m,int v)
 576 {
 577         struct pvr2_hdw *hdw = cptr->hdw;
 578         if (v < 0) return -EINVAL;
 579         if (v > hdw->std_enum_cnt) return -EINVAL;
 580         hdw->std_enum_cur = v;
 581         if (!v) return 0;
 582         v--;
 583         if (hdw->std_mask_cur == hdw->std_defs[v].id) return 0;
 584         hdw->std_mask_cur = hdw->std_defs[v].id;
 585         hdw->std_dirty = !0;
 586         return 0;
 587 }
 588
 589
 590 static int ctrl_stdenumcur_get(struct pvr2_ctrl *cptr,int *vp)
 591 {
 592         *vp = cptr->hdw->std_enum_cur;
 593         return 0;
 594 }
 595
 596
 597 static int ctrl_stdenumcur_is_dirty(struct pvr2_ctrl *cptr)
 598 {
 599         return cptr->hdw->std_dirty != 0;
 600 }
 601
 602
 603 static void ctrl_stdenumcur_clear_dirty(struct pvr2_ctrl *cptr)
 604 {
 605         cptr->hdw->std_dirty = 0;
 606 }
 607
 608
 609 #define DEFINT(vmin,vmax) \
 610         .type = pvr2_ctl_int, \
 611         .def.type_int.min_value = vmin, \
 612         .def.type_int.max_value = vmax
 613
 614 #define DEFENUM(tab) \
 615         .type = pvr2_ctl_enum, \
 616         .def.type_enum.count = (sizeof(tab)/sizeof((tab)[0])), \
 617         .def.type_enum.value_names = tab
 618
 619 #define DEFBOOL \
 620         .type = pvr2_ctl_bool
 621
 622 #define DEFMASK(msk,tab) \
 623         .type = pvr2_ctl_bitmask, \
 624         .def.type_bitmask.valid_bits = msk, \
 625         .def.type_bitmask.bit_names = tab
 626
 627 #define DEFREF(vname) \
 628         .set_value = ctrl_set_##vname, \
 629         .get_value = ctrl_get_##vname, \
 630         .is_dirty = ctrl_isdirty_##vname, \
 631         .clear_dirty = ctrl_cleardirty_##vname
 632
 633
 634 #define VCREATE_FUNCS(vname) \
 635 static int ctrl_get_##vname(struct pvr2_ctrl *cptr,int *vp) \
 636 {*vp = cptr->hdw->vname##_val; return 0;} \
 637 static int ctrl_set_##vname(struct pvr2_ctrl *cptr,int m,int v) \
 638 {cptr->hdw->vname##_val = v; cptr->hdw->vname##_dirty = !0; return 0;} \
 639 static int ctrl_isdirty_##vname(struct pvr2_ctrl *cptr) \
 640 {return cptr->hdw->vname##_dirty != 0;} \
 641 static void ctrl_cleardirty_##vname(struct pvr2_ctrl *cptr) \
 642 {cptr->hdw->vname##_dirty = 0;}
 643
 644 VCREATE_FUNCS(brightness)
 645 VCREATE_FUNCS(contrast)
 646 VCREATE_FUNCS(saturation)
 647 VCREATE_FUNCS(hue)
 648 VCREATE_FUNCS(volume)
 649 VCREATE_FUNCS(balance)
 650 VCREATE_FUNCS(bass)
 651 VCREATE_FUNCS(treble)
 652 VCREATE_FUNCS(mute)
 653 VCREATE_FUNCS(input)
 654 VCREATE_FUNCS(audiomode)
 655 VCREATE_FUNCS(res_hor)
 656 VCREATE_FUNCS(res_ver)
 657 VCREATE_FUNCS(srate)
 658
 659 #define MIN_FREQ 55250000L
 660 #define MAX_FREQ 850000000L
 661
 662 /* Table definition of all controls which can be manipulated */
 663 static const struct pvr2_ctl_info control_defs[] = {
 664         {
 665                 .v4l_id = V4L2_CID_BRIGHTNESS,
 666                 .desc = "Brightness",
 667                 .name = "brightness",
 668                 .default_value = 128,
 669                 DEFREF(brightness),
 670                 DEFINT(0,255),
 671         },{
 672                 .v4l_id = V4L2_CID_CONTRAST,
 673                 .desc = "Contrast",
 674                 .name = "contrast",
 675                 .default_value = 68,
 676                 DEFREF(contrast),
 677                 DEFINT(0,127),
 678         },{
 679                 .v4l_id = V4L2_CID_SATURATION,
 680                 .desc = "Saturation",
 681                 .name = "saturation",
 682                 .default_value = 64,
 683                 DEFREF(saturation),
 684                 DEFINT(0,127),
 685         },{
 686                 .v4l_id = V4L2_CID_HUE,
 687                 .desc = "Hue",
 688                 .name = "hue",
 689                 .default_value = 0,
 690                 DEFREF(hue),
 691                 DEFINT(-128,127),
 692         },{
 693                 .v4l_id = V4L2_CID_AUDIO_VOLUME,
 694                 .desc = "Volume",
 695                 .name = "volume",
 696                 .default_value = 65535,
 697                 DEFREF(volume),
 698                 DEFINT(0,65535),
 699         },{
 700                 .v4l_id = V4L2_CID_AUDIO_BALANCE,
 701                 .desc = "Balance",
 702                 .name = "balance",
 703                 .default_value = 0,
 704                 DEFREF(balance),
 705                 DEFINT(-32768,32767),
 706         },{
 707                 .v4l_id = V4L2_CID_AUDIO_BASS,
 708                 .desc = "Bass",
 709                 .name = "bass",
 710                 .default_value = 0,
 711                 DEFREF(bass),
 712                 DEFINT(-32768,32767),
 713         },{
 714                 .v4l_id = V4L2_CID_AUDIO_TREBLE,
 715                 .desc = "Treble",
 716                 .name = "treble",
 717                 .default_value = 0,
 718                 DEFREF(treble),
 719                 DEFINT(-32768,32767),
 720         },{
 721                 .v4l_id = V4L2_CID_AUDIO_MUTE,
 722                 .desc = "Mute",
 723                 .name = "mute",
 724                 .default_value = 0,
 725                 DEFREF(mute),
 726                 DEFBOOL,
 727         },{
 728                 .desc = "Video Source",
 729                 .name = "input",
 730                 .internal_id = PVR2_CID_INPUT,
 731                 .default_value = PVR2_CVAL_INPUT_TV,
 732                 DEFREF(input),
 733                 DEFENUM(control_values_input),
 734         },{
 735                 .desc = "Audio Mode",
 736                 .name = "audio_mode",
 737                 .internal_id = PVR2_CID_AUDIOMODE,
 738                 .default_value = V4L2_TUNER_MODE_STEREO,
 739                 DEFREF(audiomode),
 740                 DEFENUM(control_values_audiomode),
 741         },{
 742                 .desc = "Horizontal capture resolution",
 743                 .name = "resolution_hor",
 744                 .internal_id = PVR2_CID_HRES,
 745                 .default_value = 720,
 746                 DEFREF(res_hor),
 747                 DEFINT(320,720),
 748 #ifdef CONFIG_VIDEO_PVRUSB2_24XXX
 749                 /* Hook in check for clamp on horizontal resolution in
 750                    order to avoid unsolved problem involving cx25840. */
 751                 .get_max_value = ctrl_hres_max_get,
 752                 .get_min_value = ctrl_hres_min_get,
 753 #endif
 754         },{
 755                 .desc = "Vertical capture resolution",
 756                 .name = "resolution_ver",
 757                 .internal_id = PVR2_CID_VRES,
 758                 .default_value = 480,
 759                 DEFREF(res_ver),
 760                 DEFINT(200,625),
 761         },{
 762                 .v4l_id = V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ,
 763                 .default_value = V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000,
 764                 .desc = "Audio Sampling Frequency",
 765                 .name = "srate",
 766                 DEFREF(srate),
 767                 DEFENUM(control_values_srate),
 768         },{
 769                 .desc = "Tuner Frequency (Hz)",
 770                 .name = "frequency",
 771                 .internal_id = PVR2_CID_FREQUENCY,
 772                 .default_value = 175250000L,
 773                 .set_value = ctrl_freq_set,
 774                 .get_value = ctrl_freq_get,
 775                 .is_dirty = ctrl_freq_is_dirty,
 776                 .clear_dirty = ctrl_freq_clear_dirty,
 777                 DEFINT(MIN_FREQ,MAX_FREQ),
 778         },{
 779                 .desc = "Channel",
 780                 .name = "channel",
 781                 .set_value = ctrl_channel_set,
 782                 .get_value = ctrl_channel_get,
 783                 DEFINT(0,FREQTABLE_SIZE),
 784         },{
 785                 .desc = "Channel Program Frequency",
 786                 .name = "freq_table_value",
 787                 .set_value = ctrl_channelfreq_set,
 788                 .get_value = ctrl_channelfreq_get,
 789                 DEFINT(MIN_FREQ,MAX_FREQ),
 790         },{
 791                 .desc = "Channel Program ID",
 792                 .name = "freq_table_channel",
 793                 .set_value = ctrl_channelprog_set,
 794                 .get_value = ctrl_channelprog_get,
 795                 DEFINT(0,FREQTABLE_SIZE),
 796         },{
 797                 .desc = "Streaming Enabled",
 798                 .name = "streaming_enabled",
 799                 .get_value = ctrl_streamingenabled_get,
 800                 DEFBOOL,
 801         },{
 802                 .desc = "USB Speed",
 803                 .name = "usb_speed",
 804                 .get_value = ctrl_hsm_get,
 805                 DEFENUM(control_values_hsm),
 806         },{
 807                 .desc = "Signal Present",
 808                 .name = "signal_present",
 809                 .get_value = ctrl_signal_get,
 810                 DEFBOOL,
 811         },{
 812                 .desc = "Video Standards Available Mask",
 813                 .name = "video_standard_mask_available",
 814                 .internal_id = PVR2_CID_STDAVAIL,
 815                 .skip_init = !0,
 816                 .get_value = ctrl_stdavail_get,
 817                 .set_value = ctrl_stdavail_set,
 818                 .val_to_sym = ctrl_std_val_to_sym,
 819                 .sym_to_val = ctrl_std_sym_to_val,
 820                 .type = pvr2_ctl_bitmask,
 821         },{
 822                 .desc = "Video Standards In Use Mask",
 823                 .name = "video_standard_mask_active",
 824                 .internal_id = PVR2_CID_STDCUR,
 825                 .skip_init = !0,
 826                 .get_value = ctrl_stdcur_get,
 827                 .set_value = ctrl_stdcur_set,
 828                 .is_dirty = ctrl_stdcur_is_dirty,
 829                 .clear_dirty = ctrl_stdcur_clear_dirty,
 830                 .val_to_sym = ctrl_std_val_to_sym,
 831                 .sym_to_val = ctrl_std_sym_to_val,
 832                 .type = pvr2_ctl_bitmask,
 833         },{
 834                 .desc = "Subsystem enabled mask",
 835                 .name = "debug_subsys_mask",
 836                 .skip_init = !0,
 837                 .get_value = ctrl_subsys_get,
 838                 .set_value = ctrl_subsys_set,
 839                 DEFMASK(PVR2_SUBSYS_ALL,control_values_subsystem),
 840         },{
 841                 .desc = "Subsystem stream mask",
 842                 .name = "debug_subsys_stream_mask",
 843                 .skip_init = !0,
 844                 .get_value = ctrl_subsys_stream_get,
 845                 .set_value = ctrl_subsys_stream_set,
 846                 DEFMASK(PVR2_SUBSYS_ALL,control_values_subsystem),
 847         },{
 848                 .desc = "Video Standard Name",
 849                 .name = "video_standard",
 850                 .internal_id = PVR2_CID_STDENUM,
 851                 .skip_init = !0,
 852                 .get_value = ctrl_stdenumcur_get,
 853                 .set_value = ctrl_stdenumcur_set,
 854                 .is_dirty = ctrl_stdenumcur_is_dirty,
 855                 .clear_dirty = ctrl_stdenumcur_clear_dirty,
 856                 .type = pvr2_ctl_enum,
 857         }
 858 };
 859
 860 #define CTRLDEF_COUNT (sizeof(control_defs)/sizeof(control_defs[0]))
 861
 862
 863 const char *pvr2_config_get_name(enum pvr2_config cfg)
 864 {
 865         switch (cfg) {
 866         case pvr2_config_empty: return "empty";
 867         case pvr2_config_mpeg: return "mpeg";
 868         case pvr2_config_vbi: return "vbi";
 869         case pvr2_config_radio: return "radio";
 870         }
 871         return "<unknown>";
 872 }
 873
 874
 875 struct usb_device *pvr2_hdw_get_dev(struct pvr2_hdw *hdw)
 876 {
 877         return hdw->usb_dev;
 878 }
 879
 880
 881 unsigned long pvr2_hdw_get_sn(struct pvr2_hdw *hdw)
 882 {
 883         return hdw->serial_number;
 884 }
 885
 886 int pvr2_hdw_get_unit_number(struct pvr2_hdw *hdw)
 887 {
 888         return hdw->unit_number;
 889 }
 890
 891
 892 /* Attempt to locate one of the given set of files.  Messages are logged
 893    appropriate to what has been found.  The return value will be 0 or
 894    greater on success (it will be the index of the file name found) and
 895    fw_entry will be filled in.  Otherwise a negative error is returned on
 896    failure.  If the return value is -ENOENT then no viable firmware file
 897    could be located. */
 898 static int pvr2_locate_firmware(struct pvr2_hdw *hdw,
 899                                 const struct firmware **fw_entry,
 900                                 const char *fwtypename,
 901                                 unsigned int fwcount,
 902                                 const char *fwnames[])
 903 {
 904         unsigned int idx;
 905         int ret = -EINVAL;
 906         for (idx = 0; idx < fwcount; idx++) {
 907                 ret = request_firmware(fw_entry,
 908                                        fwnames[idx],
 909                                        &hdw->usb_dev->dev);
 910                 if (!ret) {
 911                         trace_firmware("Located %s firmware: %s;"
 912                                        " uploading...",
 913                                        fwtypename,
 914                                        fwnames[idx]);
 915                         return idx;
 916                 }
 917                 if (ret == -ENOENT) continue;
 918                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
 919                            "request_firmware fatal error with code=%d",ret);
 920                 return ret;
 921         }
 922         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
 923                    "***WARNING***"
 924                    " Device %s firmware"
 925                    " seems to be missing.",
 926                    fwtypename);
 927         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
 928                    "Did you install the pvrusb2 firmware files"
 929                    " in their proper location?");
 930         if (fwcount == 1) {
 931                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
 932                            "request_firmware unable to locate %s file %s",
 933                            fwtypename,fwnames[0]);
 934         } else {
 935                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
 936                            "request_firmware unable to locate"
 937                            " one of the following %s files:",
 938                            fwtypename);
 939                 for (idx = 0; idx < fwcount; idx++) {
 940                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
 941                                    "request_firmware: Failed to find %s",
 942                                    fwnames[idx]);
 943                 }
 944         }
 945         return ret;
 946 }
 947
 948
 949 /*
 950  * pvr2_upload_firmware1().
 951  *
 952  * Send the 8051 firmware to the device.  After the upload, arrange for
 953  * device to re-enumerate.
 954  *
 955  * NOTE : the pointer to the firmware data given by request_firmware()
 956  * is not suitable for an usb transaction.
 957  *
 958  */
 959 static int pvr2_upload_firmware1(struct pvr2_hdw *hdw)
 960 {
 961         const struct firmware *fw_entry = NULL;
 962         void  *fw_ptr;
 963         unsigned int pipe;
 964         int ret;
 965         u16 address;
 966         static const char *fw_files_29xxx[] = {
 967                 "v4l-pvrusb2-29xxx-01.fw",
 968         };
 969 #ifdef CONFIG_VIDEO_PVRUSB2_24XXX
 970         static const char *fw_files_24xxx[] = {
 971                 "v4l-pvrusb2-24xxx-01.fw",
 972         };
 973 #endif
 974         static const struct pvr2_string_table fw_file_defs[] = {
 975                 [PVR2_HDW_TYPE_29XXX] = {
 976                         fw_files_29xxx,
 977                         sizeof(fw_files_29xxx)/sizeof(fw_files_29xxx[0]),
 978                 },
 979 #ifdef CONFIG_VIDEO_PVRUSB2_24XXX
 980                 [PVR2_HDW_TYPE_24XXX] = {
 981                         fw_files_24xxx,
 982                         sizeof(fw_files_24xxx)/sizeof(fw_files_24xxx[0]),
 983                 },
 984 #endif
 985         };
 986         hdw->fw1_state = FW1_STATE_FAILED; // default result
 987
 988         trace_firmware("pvr2_upload_firmware1");
 989
 990         ret = pvr2_locate_firmware(hdw,&fw_entry,"fx2 controller",
 991                                    fw_file_defs[hdw->hdw_type].cnt,
 992                                    fw_file_defs[hdw->hdw_type].lst);
 993         if (ret < 0) {
 994                 if (ret == -ENOENT) hdw->fw1_state = FW1_STATE_MISSING;
 995                 return ret;
 996         }
 997
 998         usb_settoggle(hdw->usb_dev, 0 & 0xf, !(0 & USB_DIR_IN), 0);
 999         usb_clear_halt(hdw->usb_dev, usb_sndbulkpipe(hdw->usb_dev, 0 & 0x7f));
1000
1001         pipe = usb_sndctrlpipe(hdw->usb_dev, 0);
1002
1003         if (fw_entry->size != 0x2000){
1004                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,"wrong fx2 firmware size");
1005                 release_firmware(fw_entry);
1006                 return -ENOMEM;
1007         }
1008
1009         fw_ptr = kmalloc(0x800, GFP_KERNEL);
1010         if (fw_ptr == NULL){
1011                 release_firmware(fw_entry);
1012                 return -ENOMEM;
1013         }
1014
1015         /* We have to hold the CPU during firmware upload. */
1016         pvr2_hdw_cpureset_assert(hdw,1);
1017
1018         /* upload the firmware to address 0000-1fff in 2048 (=0x800) bytes
1019            chunk. */
1020
1021         ret = 0;
1022         for(address = 0; address < fw_entry->size; address += 0x800) {
1023                 memcpy(fw_ptr, fw_entry->data + address, 0x800);
1024                 ret += usb_control_msg(hdw->usb_dev, pipe, 0xa0, 0x40, address,
1025                                        0, fw_ptr, 0x800, HZ);
1026         }
1027
1028         trace_firmware("Upload done, releasing device's CPU");
1029
1030         /* Now release the CPU.  It will disconnect and reconnect later. */
1031         pvr2_hdw_cpureset_assert(hdw,0);
1032
1033         kfree(fw_ptr);
1034         release_firmware(fw_entry);
1035
1036         trace_firmware("Upload done (%d bytes sent)",ret);
1037
1038         /* We should have written 8192 bytes */
1039         if (ret == 8192) {
1040                 hdw->fw1_state = FW1_STATE_RELOAD;
1041                 return 0;
1042         }
1043
1044         return -EIO;
1045 }
1046
1047
1048 /*
1049  * pvr2_upload_firmware2()
1050  *
1051  * This uploads encoder firmware on endpoint 2.
1052  *
1053  */
1054
1055 int pvr2_upload_firmware2(struct pvr2_hdw *hdw)
1056 {
1057         const struct firmware *fw_entry = NULL;
1058         void  *fw_ptr;
1059         unsigned int pipe, fw_len, fw_done;
1060         int actual_length;
1061         int ret = 0;
1062         int fwidx;
1063         static const char *fw_files[] = {
1064                 CX2341X_FIRM_ENC_FILENAME,
1065         };
1066
1067         trace_firmware("pvr2_upload_firmware2");
1068
1069         ret = pvr2_locate_firmware(hdw,&fw_entry,"encoder",
1070                                    sizeof(fw_files)/sizeof(fw_files[0]),
1071                                    fw_files);
1072         if (ret < 0) return ret;
1073         fwidx = ret;
1074         ret = 0;
1075         /* Since we're about to completely reinitialize the encoder,
1076            invalidate our cached copy of its configuration state.  Next
1077            time we configure the encoder, then we'll fully configure it. */
1078         hdw->enc_cur_valid = 0;
1079
1080         /* First prepare firmware loading */
1081         ret |= pvr2_write_register(hdw, 0x0048, 0xffffffff); /*interrupt mask*/
1082         ret |= pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000088); /*gpio dir*/
1083         ret |= pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000008); /*gpio output state*/
1084         ret |= pvr2_hdw_cmd_deep_reset(hdw);
1085         ret |= pvr2_write_register(hdw, 0xa064, 0x00000000); /*APU command*/
1086         ret |= pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000408); /*gpio dir*/
1087         ret |= pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000008); /*gpio output state*/
1088         ret |= pvr2_write_register(hdw, 0x9058, 0xffffffed); /*VPU ctrl*/
1089         ret |= pvr2_write_register(hdw, 0x9054, 0xfffffffd); /*reset hw blocks*/
1090         ret |= pvr2_write_register(hdw, 0x07f8, 0x80000800); /*encoder SDRAM refresh*/
1091         ret |= pvr2_write_register(hdw, 0x07fc, 0x0000001a); /*encoder SDRAM pre-charge*/
1092         ret |= pvr2_write_register(hdw, 0x0700, 0x00000000); /*I2C clock*/
1093         ret |= pvr2_write_register(hdw, 0xaa00, 0x00000000); /*unknown*/
1094         ret |= pvr2_write_register(hdw, 0xaa04, 0x00057810); /*unknown*/
1095         ret |= pvr2_write_register(hdw, 0xaa10, 0x00148500); /*unknown*/
1096         ret |= pvr2_write_register(hdw, 0xaa18, 0x00840000); /*unknown*/
1097         ret |= pvr2_write_u8(hdw, 0x52, 0);
1098         ret |= pvr2_write_u16(hdw, 0x0600, 0);
1099
1100         if (ret) {
1101                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1102                            "firmware2 upload prep failed, ret=%d",ret);
1103                 release_firmware(fw_entry);
1104                 return ret;
1105         }
1106
1107         /* Now send firmware */
1108
1109         fw_len = fw_entry->size;
1110
1111         if (fw_len % FIRMWARE_CHUNK_SIZE) {
1112                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1113                            "size of %s firmware"
1114                            " must be a multiple of 8192B",
1115                            fw_files[fwidx]);
1116                 release_firmware(fw_entry);
1117                 return -1;
1118         }
1119
1120         fw_ptr = kmalloc(FIRMWARE_CHUNK_SIZE, GFP_KERNEL);
1121         if (fw_ptr == NULL){
1122                 release_firmware(fw_entry);
1123                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1124                            "failed to allocate memory for firmware2 upload");
1125                 return -ENOMEM;
1126         }
1127
1128         pipe = usb_sndbulkpipe(hdw->usb_dev, PVR2_FIRMWARE_ENDPOINT);
1129
1130         for (fw_done = 0 ; (fw_done < fw_len) && !ret ;
1131              fw_done += FIRMWARE_CHUNK_SIZE ) {
1132                 int i;
1133                 memcpy(fw_ptr, fw_entry->data + fw_done, FIRMWARE_CHUNK_SIZE);
1134                 /* Usbsnoop log  shows that we must swap bytes... */
1135                 for (i = 0; i < FIRMWARE_CHUNK_SIZE/4 ; i++)
1136                         ((u32 *)fw_ptr)[i] = ___swab32(((u32 *)fw_ptr)[i]);
1137
1138                 ret |= usb_bulk_msg(hdw->usb_dev, pipe, fw_ptr,
1139                                     FIRMWARE_CHUNK_SIZE,
1140                                     &actual_length, HZ);
1141                 ret |= (actual_length != FIRMWARE_CHUNK_SIZE);
1142         }
1143
1144         trace_firmware("upload of %s : %i / %i ",
1145                        fw_files[fwidx],fw_done,fw_len);
1146
1147         kfree(fw_ptr);
1148         release_firmware(fw_entry);
1149
1150         if (ret) {
1151                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1152                            "firmware2 upload transfer failure");
1153                 return ret;
1154         }
1155
1156         /* Finish upload */
1157
1158         ret |= pvr2_write_register(hdw, 0x9054, 0xffffffff); /*reset hw blocks*/
1159         ret |= pvr2_write_register(hdw, 0x9058, 0xffffffe8); /*VPU ctrl*/
1160         ret |= pvr2_write_u16(hdw, 0x0600, 0);
1161
1162         if (ret) {
1163                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1164                            "firmware2 upload post-proc failure");
1165         } else {
1166                 hdw->subsys_enabled_mask |= (1<<PVR2_SUBSYS_B_ENC_FIRMWARE);
1167         }
1168         return ret;
1169 }
1170
1171
1172 #define FIRMWARE_RECOVERY_BITS \
1173         ((1<<PVR2_SUBSYS_B_ENC_CFG) | \
1174          (1<<PVR2_SUBSYS_B_ENC_RUN) | \
1175          (1<<PVR2_SUBSYS_B_ENC_FIRMWARE) | \
1176          (1<<PVR2_SUBSYS_B_USBSTREAM_RUN))
1177
1178 /*
1179
1180   This single function is key to pretty much everything.  The pvrusb2
1181   device can logically be viewed as a series of subsystems which can be
1182   stopped / started or unconfigured / configured.  To get things streaming,
1183   one must configure everything and start everything, but there may be
1184   various reasons over time to deconfigure something or stop something.
1185   This function handles all of this activity.  Everything EVERYWHERE that
1186   must affect a subsystem eventually comes here to do the work.
1187
1188   The current state of all subsystems is represented by a single bit mask,
1189   known as subsys_enabled_mask.  The bit positions are defined by the
1190   PVR2_SUBSYS_xxxx macros, with one subsystem per bit position.  At any
1191   time the set of configured or active subsystems can be queried just by
1192   looking at that mask.  To change bits in that mask, this function here
1193   must be called.  The "msk" argument indicates which bit positions to
1194   change, and the "val" argument defines the new values for the positions
1195   defined by "msk".
1196
1197   There is a priority ordering of starting / stopping things, and for
1198   multiple requested changes, this function implements that ordering.
1199   (Thus we will act on a request to load encoder firmware before we
1200   configure the encoder.)  In addition to priority ordering, there is a
1201   recovery strategy implemented here.  If a particular step fails and we
1202   detect that failure, this function will clear the affected subsystem bits
1203   and restart.  Thus we have a means for recovering from a dead encoder:
1204   Clear all bits that correspond to subsystems that we need to restart /
1205   reconfigure and start over.
1206
1207 */
1208 static void pvr2_hdw_subsys_bit_chg_no_lock(struct pvr2_hdw *hdw,
1209                                             unsigned long msk,
1210                                             unsigned long val)
1211 {
1212         unsigned long nmsk;
1213         unsigned long vmsk;
1214         int ret;
1215         unsigned int tryCount = 0;
1216
1217         if (!hdw->flag_ok) return;
1218
1219         msk &= PVR2_SUBSYS_ALL;
1220         nmsk = (hdw->subsys_enabled_mask & ~msk) | (val & msk);
1221         nmsk &= PVR2_SUBSYS_ALL;
1222
1223         for (;;) {
1224                 tryCount++;
1225                 if (!((nmsk ^ hdw->subsys_enabled_mask) &
1226                       PVR2_SUBSYS_ALL)) break;
1227                 if (tryCount > 4) {
1228                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1229                                    "Too many retries when configuring device;"
1230                                    " giving up");
1231                         pvr2_hdw_render_useless(hdw);
1232                         break;
1233                 }
1234                 if (tryCount > 1) {
1235                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1236                                    "Retrying device reconfiguration");
1237                 }
1238                 pvr2_trace(PVR2_TRACE_INIT,
1239                            "subsys mask changing 0x%lx:0x%lx"
1240                            " from 0x%lx to 0x%lx",
1241                            msk,val,hdw->subsys_enabled_mask,nmsk);
1242
1243                 vmsk = (nmsk ^ hdw->subsys_enabled_mask) &
1244                         hdw->subsys_enabled_mask;
1245                 if (vmsk) {
1246                         if (vmsk & (1<<PVR2_SUBSYS_B_ENC_RUN)) {
1247                                 pvr2_trace(PVR2_TRACE_CTL,
1248                                            "/*---TRACE_CTL----*/"
1249                                            " pvr2_encoder_stop");
1250                                 ret = pvr2_encoder_stop(hdw);
1251                                 if (ret) {
1252                                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1253                                                    "Error recovery initiated");
1254                                         hdw->subsys_enabled_mask &=
1255                                                 ~FIRMWARE_RECOVERY_BITS;
1256                                         continue;
1257                                 }
1258                         }
1259                         if (vmsk & (1<<PVR2_SUBSYS_B_USBSTREAM_RUN)) {
1260                                 pvr2_trace(PVR2_TRACE_CTL,
1261                                            "/*---TRACE_CTL----*/"
1262                                            " pvr2_hdw_cmd_usbstream(0)");
1263                                 pvr2_hdw_cmd_usbstream(hdw,0);
1264                         }
1265                         if (vmsk & (1<<PVR2_SUBSYS_B_DIGITIZER_RUN)) {
1266                                 pvr2_trace(PVR2_TRACE_CTL,
1267                                            "/*---TRACE_CTL----*/"
1268                                            " decoder disable");
1269                                 if (hdw->decoder_ctrl) {
1270                                         hdw->decoder_ctrl->enable(
1271                                                 hdw->decoder_ctrl->ctxt,0);
1272                                 } else {
1273                                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1274                                                    "WARNING:"
1275                                                    " No decoder present");
1276                                 }
1277                                 hdw->subsys_enabled_mask &=
1278                                         ~(1<<PVR2_SUBSYS_B_DIGITIZER_RUN);
1279                         }
1280                         if (vmsk & PVR2_SUBSYS_CFG_ALL) {
1281                                 hdw->subsys_enabled_mask &=
1282                                         ~(vmsk & PVR2_SUBSYS_CFG_ALL);
1283                         }
1284                 }
1285                 vmsk = (nmsk ^ hdw->subsys_enabled_mask) & nmsk;
1286                 if (vmsk) {
1287                         if (vmsk & (1<<PVR2_SUBSYS_B_ENC_FIRMWARE)) {
1288                                 pvr2_trace(PVR2_TRACE_CTL,
1289                                            "/*---TRACE_CTL----*/"
1290                                            " pvr2_upload_firmware2");
1291                                 ret = pvr2_upload_firmware2(hdw);
1292                                 if (ret) {
1293                                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1294                                                    "Failure uploading encoder"
1295                                                    " firmware");
1296                                         pvr2_hdw_render_useless(hdw);
1297                                         break;
1298                                 }
1299                         }
1300                         if (vmsk & (1<<PVR2_SUBSYS_B_ENC_CFG)) {
1301                                 pvr2_trace(PVR2_TRACE_CTL,
1302                                            "/*---TRACE_CTL----*/"
1303                                            " pvr2_encoder_configure");
1304                                 ret = pvr2_encoder_configure(hdw);
1305                                 if (ret) {
1306                                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1307                                                    "Error recovery initiated");
1308                                         hdw->subsys_enabled_mask &=
1309                                                 ~FIRMWARE_RECOVERY_BITS;
1310                                         continue;
1311                                 }
1312                         }
1313                         if (vmsk & (1<<PVR2_SUBSYS_B_DIGITIZER_RUN)) {
1314                                 pvr2_trace(PVR2_TRACE_CTL,
1315                                            "/*---TRACE_CTL----*/"
1316                                            " decoder enable");
1317                                 if (hdw->decoder_ctrl) {
1318                                         hdw->decoder_ctrl->enable(
1319                                                 hdw->decoder_ctrl->ctxt,!0);
1320                                 } else {
1321                                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1322                                                    "WARNING:"
1323                                                    " No decoder present");
1324                                 }
1325                                 hdw->subsys_enabled_mask |=
1326                                         (1<<PVR2_SUBSYS_B_DIGITIZER_RUN);
1327                         }
1328                         if (vmsk & (1<<PVR2_SUBSYS_B_USBSTREAM_RUN)) {
1329                                 pvr2_trace(PVR2_TRACE_CTL,
1330                                            "/*---TRACE_CTL----*/"
1331                                            " pvr2_hdw_cmd_usbstream(1)");
1332                                 pvr2_hdw_cmd_usbstream(hdw,!0);
1333                         }
1334                         if (vmsk & (1<<PVR2_SUBSYS_B_ENC_RUN)) {
1335                                 pvr2_trace(PVR2_TRACE_CTL,
1336                                            "/*---TRACE_CTL----*/"
1337                                            " pvr2_encoder_start");
1338                                 ret = pvr2_encoder_start(hdw);
1339                                 if (ret) {
1340                                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1341                                                    "Error recovery initiated");
1342                                         hdw->subsys_enabled_mask &=
1343                                                 ~FIRMWARE_RECOVERY_BITS;
1344                                         continue;
1345                                 }
1346                         }
1347                 }
1348         }
1349 }
1350
1351
1352 void pvr2_hdw_subsys_bit_chg(struct pvr2_hdw *hdw,
1353                              unsigned long msk,unsigned long val)
1354 {
1355         LOCK_TAKE(hdw->big_lock); do {
1356                 pvr2_hdw_subsys_bit_chg_no_lock(hdw,msk,val);
1357         } while (0); LOCK_GIVE(hdw->big_lock);
1358 }
1359
1360
1361 unsigned long pvr2_hdw_subsys_get(struct pvr2_hdw *hdw)
1362 {
1363         return hdw->subsys_enabled_mask;
1364 }
1365
1366
1367 unsigned long pvr2_hdw_subsys_stream_get(struct pvr2_hdw *hdw)
1368 {
1369         return hdw->subsys_stream_mask;
1370 }
1371
1372
1373 static void pvr2_hdw_subsys_stream_bit_chg_no_lock(struct pvr2_hdw *hdw,
1374                                                    unsigned long msk,
1375                                                    unsigned long val)
1376 {
1377         unsigned long val2;
1378         msk &= PVR2_SUBSYS_ALL;
1379         val2 = ((hdw->subsys_stream_mask & ~msk) | (val & msk));
1380         pvr2_trace(PVR2_TRACE_INIT,
1381                    "stream mask changing 0x%lx:0x%lx from 0x%lx to 0x%lx",
1382                    msk,val,hdw->subsys_stream_mask,val2);
1383         hdw->subsys_stream_mask = val2;
1384 }
1385
1386
1387 void pvr2_hdw_subsys_stream_bit_chg(struct pvr2_hdw *hdw,
1388                                     unsigned long msk,
1389                                     unsigned long val)
1390 {
1391         LOCK_TAKE(hdw->big_lock); do {
1392                 pvr2_hdw_subsys_stream_bit_chg_no_lock(hdw,msk,val);
1393         } while (0); LOCK_GIVE(hdw->big_lock);
1394 }
1395
1396
1397 static int pvr2_hdw_set_streaming_no_lock(struct pvr2_hdw *hdw,int enableFl)
1398 {
1399         if ((!enableFl) == !(hdw->flag_streaming_enabled)) return 0;
1400         if (enableFl) {
1401                 pvr2_trace(PVR2_TRACE_START_STOP,
1402                            "/*--TRACE_STREAM--*/ enable");
1403                 pvr2_hdw_subsys_bit_chg_no_lock(hdw,~0,~0);
1404         } else {
1405                 pvr2_trace(PVR2_TRACE_START_STOP,
1406                            "/*--TRACE_STREAM--*/ disable");
1407                 pvr2_hdw_subsys_bit_chg_no_lock(hdw,hdw->subsys_stream_mask,0);
1408         }
1409         if (!hdw->flag_ok) return -EIO;
1410         hdw->flag_streaming_enabled = enableFl != 0;
1411         return 0;
1412 }
1413
1414
1415 int pvr2_hdw_get_streaming(struct pvr2_hdw *hdw)
1416 {
1417         return hdw->flag_streaming_enabled != 0;
1418 }
1419
1420
1421 int pvr2_hdw_set_streaming(struct pvr2_hdw *hdw,int enable_flag)
1422 {
1423         int ret;
1424         LOCK_TAKE(hdw->big_lock); do {
1425                 ret = pvr2_hdw_set_streaming_no_lock(hdw,enable_flag);
1426         } while (0); LOCK_GIVE(hdw->big_lock);
1427         return ret;
1428 }
1429
1430
1431 static int pvr2_hdw_set_stream_type_no_lock(struct pvr2_hdw *hdw,
1432                                             enum pvr2_config config)
1433 {
1434         unsigned long sm = hdw->subsys_enabled_mask;
1435         if (!hdw->flag_ok) return -EIO;
1436         pvr2_hdw_subsys_bit_chg_no_lock(hdw,hdw->subsys_stream_mask,0);
1437         hdw->config = config;
1438         pvr2_hdw_subsys_bit_chg_no_lock(hdw,~0,sm);
1439         return 0;
1440 }
1441
1442
1443 int pvr2_hdw_set_stream_type(struct pvr2_hdw *hdw,enum pvr2_config config)
1444 {
1445         int ret;
1446         if (!hdw->flag_ok) return -EIO;
1447         LOCK_TAKE(hdw->big_lock);
1448         ret = pvr2_hdw_set_stream_type_no_lock(hdw,config);
1449         LOCK_GIVE(hdw->big_lock);
1450         return ret;
1451 }
1452
1453
1454 static int get_default_tuner_type(struct pvr2_hdw *hdw)
1455 {
1456         int unit_number = hdw->unit_number;
1457         int tp = -1;
1458         if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1459                 tp = tuner[unit_number];
1460         }
1461         if (tp < 0) return -EINVAL;
1462         hdw->tuner_type = tp;
1463         return 0;
1464 }
1465
1466
1467 static v4l2_std_id get_default_standard(struct pvr2_hdw *hdw)
1468 {
1469         int unit_number = hdw->unit_number;
1470         int tp = 0;
1471         if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1472                 tp = video_std[unit_number];
1473         }
1474         return tp;
1475 }
1476
1477
1478 static unsigned int get_default_error_tolerance(struct pvr2_hdw *hdw)
1479 {
1480         int unit_number = hdw->unit_number;
1481         int tp = 0;
1482         if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1483                 tp = tolerance[unit_number];
1484         }
1485         return tp;
1486 }
1487
1488
1489 static int pvr2_hdw_check_firmware(struct pvr2_hdw *hdw)
1490 {
1491         /* Try a harmless request to fetch the eeprom's address over
1492            endpoint 1.  See what happens.  Only the full FX2 image can
1493            respond to this.  If this probe fails then likely the FX2
1494            firmware needs be loaded. */
1495         int result;
1496         LOCK_TAKE(hdw->ctl_lock); do {
1497                 hdw->cmd_buffer[0] = 0xeb;
1498                 result = pvr2_send_request_ex(hdw,HZ*1,!0,
1499                                            hdw->cmd_buffer,1,
1500                                            hdw->cmd_buffer,1);
1501                 if (result < 0) break;
1502         } while(0); LOCK_GIVE(hdw->ctl_lock);
1503         if (result) {
1504                 pvr2_trace(PVR2_TRACE_INIT,
1505                            "Probe of device endpoint 1 result status %d",
1506                            result);
1507         } else {
1508                 pvr2_trace(PVR2_TRACE_INIT,
1509                            "Probe of device endpoint 1 succeeded");
1510         }
1511         return result == 0;
1512 }
1513
1514 static void pvr2_hdw_setup_std(struct pvr2_hdw *hdw)
1515 {
1516         char buf[40];
1517         unsigned int bcnt;
1518         v4l2_std_id std1,std2;
1519
1520         std1 = get_default_standard(hdw);
1521
1522         bcnt = pvr2_std_id_to_str(buf,sizeof(buf),hdw->std_mask_eeprom);
1523         pvr2_trace(PVR2_TRACE_INIT,
1524                    "Supported video standard(s) reported by eeprom: %.*s",
1525                    bcnt,buf);
1526
1527         hdw->std_mask_avail = hdw->std_mask_eeprom;
1528
1529         std2 = std1 & ~hdw->std_mask_avail;
1530         if (std2) {
1531                 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std2);
1532                 pvr2_trace(PVR2_TRACE_INIT,
1533                            "Expanding supported video standards"
1534                            " to include: %.*s",
1535                            bcnt,buf);
1536                 hdw->std_mask_avail |= std2;
1537         }
1538
1539         pvr2_hdw_internal_set_std_avail(hdw);
1540
1541         if (std1) {
1542                 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std1);
1543                 pvr2_trace(PVR2_TRACE_INIT,
1544                            "Initial video standard forced to %.*s",
1545                            bcnt,buf);
1546                 hdw->std_mask_cur = std1;
1547                 hdw->std_dirty = !0;
1548                 pvr2_hdw_internal_find_stdenum(hdw);
1549                 return;
1550         }
1551
1552         if (hdw->std_enum_cnt > 1) {
1553                 // Autoselect the first listed standard
1554                 hdw->std_enum_cur = 1;
1555                 hdw->std_mask_cur = hdw->std_defs[hdw->std_enum_cur-1].id;
1556                 hdw->std_dirty = !0;
1557                 pvr2_trace(PVR2_TRACE_INIT,
1558                            "Initial video standard auto-selected to %s",
1559                            hdw->std_defs[hdw->std_enum_cur-1].name);
1560                 return;
1561         }
1562
1563         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1564                    "Unable to select a viable initial video standard");
1565 }
1566
1567
1568 static void pvr2_hdw_setup_low(struct pvr2_hdw *hdw)
1569 {
1570         int ret;
1571         unsigned int idx;
1572         struct pvr2_ctrl *cptr;
1573         int reloadFl = 0;
1574         if (!reloadFl) {
1575                 reloadFl = (hdw->usb_intf->cur_altsetting->desc.bNumEndpoints
1576                             == 0);
1577                 if (reloadFl) {
1578                         pvr2_trace(PVR2_TRACE_INIT,
1579                                    "USB endpoint config looks strange"
1580                                    "; possibly firmware needs to be loaded");
1581                 }
1582         }
1583         if (!reloadFl) {
1584                 reloadFl = !pvr2_hdw_check_firmware(hdw);
1585                 if (reloadFl) {
1586                         pvr2_trace(PVR2_TRACE_INIT,
1587                                    "Check for FX2 firmware failed"
1588                                    "; possibly firmware needs to be loaded");
1589                 }
1590         }
1591         if (reloadFl) {
1592                 if (pvr2_upload_firmware1(hdw) != 0) {
1593                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1594                                    "Failure uploading firmware1");
1595                 }
1596                 return;
1597         }
1598         hdw->fw1_state = FW1_STATE_OK;
1599
1600         if (initusbreset) {
1601                 pvr2_hdw_device_reset(hdw);
1602         }
1603         if (!pvr2_hdw_dev_ok(hdw)) return;
1604
1605         for (idx = 0; idx < pvr2_client_lists[hdw->hdw_type].cnt; idx++) {
1606                 request_module(pvr2_client_lists[hdw->hdw_type].lst[idx]);
1607         }
1608
1609         pvr2_hdw_cmd_powerup(hdw);
1610         if (!pvr2_hdw_dev_ok(hdw)) return;
1611
1612         if (pvr2_upload_firmware2(hdw)){
1613                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,"device unstable!!");
1614                 pvr2_hdw_render_useless(hdw);
1615                 return;
1616         }
1617
1618         // This step MUST happen after the earlier powerup step.
1619         pvr2_i2c_core_init(hdw);
1620         if (!pvr2_hdw_dev_ok(hdw)) return;
1621
1622         for (idx = 0; idx < CTRLDEF_COUNT; idx++) {
1623                 cptr = hdw->controls + idx;
1624                 if (cptr->info->skip_init) continue;
1625                 if (!cptr->info->set_value) continue;
1626                 cptr->info->set_value(cptr,~0,cptr->info->default_value);
1627         }
1628
1629         // Do not use pvr2_reset_ctl_endpoints() here.  It is not
1630         // thread-safe against the normal pvr2_send_request() mechanism.
1631         // (We should make it thread safe).
1632
1633         ret = pvr2_hdw_get_eeprom_addr(hdw);
1634         if (!pvr2_hdw_dev_ok(hdw)) return;
1635         if (ret < 0) {
1636                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1637                            "Unable to determine location of eeprom, skipping");
1638         } else {
1639                 hdw->eeprom_addr = ret;
1640                 pvr2_eeprom_analyze(hdw);
1641                 if (!pvr2_hdw_dev_ok(hdw)) return;
1642         }
1643
1644         pvr2_hdw_setup_std(hdw);
1645
1646         if (!get_default_tuner_type(hdw)) {
1647                 pvr2_trace(PVR2_TRACE_INIT,
1648                            "pvr2_hdw_setup: Tuner type overridden to %d",
1649                            hdw->tuner_type);
1650         }
1651
1652         hdw->tuner_updated = !0;
1653         pvr2_i2c_core_check_stale(hdw);
1654         hdw->tuner_updated = 0;
1655
1656         if (!pvr2_hdw_dev_ok(hdw)) return;
1657
1658         pvr2_hdw_commit_ctl_internal(hdw);
1659         if (!pvr2_hdw_dev_ok(hdw)) return;
1660
1661         hdw->vid_stream = pvr2_stream_create();
1662         if (!pvr2_hdw_dev_ok(hdw)) return;
1663         pvr2_trace(PVR2_TRACE_INIT,
1664                    "pvr2_hdw_setup: video stream is %p",hdw->vid_stream);
1665         if (hdw->vid_stream) {
1666                 idx = get_default_error_tolerance(hdw);
1667                 if (idx) {
1668                         pvr2_trace(PVR2_TRACE_INIT,
1669                                    "pvr2_hdw_setup: video stream %p"
1670                                    " setting tolerance %u",
1671                                    hdw->vid_stream,idx);
1672                 }
1673                 pvr2_stream_setup(hdw->vid_stream,hdw->usb_dev,
1674                                   PVR2_VID_ENDPOINT,idx);
1675         }
1676
1677         if (!pvr2_hdw_dev_ok(hdw)) return;
1678
1679         /* Make sure everything is up to date */
1680         pvr2_i2c_core_sync(hdw);
1681
1682         if (!pvr2_hdw_dev_ok(hdw)) return;
1683
1684         hdw->flag_init_ok = !0;
1685 }
1686
1687
1688 int pvr2_hdw_setup(struct pvr2_hdw *hdw)
1689 {
1690         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_setup(hdw=%p) begin",hdw);
1691         LOCK_TAKE(hdw->big_lock); do {
1692                 pvr2_hdw_setup_low(hdw);
1693                 pvr2_trace(PVR2_TRACE_INIT,
1694                            "pvr2_hdw_setup(hdw=%p) done, ok=%d init_ok=%d",
1695                            hdw,hdw->flag_ok,hdw->flag_init_ok);
1696                 if (pvr2_hdw_dev_ok(hdw)) {
1697                         if (pvr2_hdw_init_ok(hdw)) {
1698                                 pvr2_trace(
1699                                         PVR2_TRACE_INFO,
1700                                         "Device initialization"
1701                                         " completed successfully.");
1702                                 break;
1703                         }
1704                         if (hdw->fw1_state == FW1_STATE_RELOAD) {
1705                                 pvr2_trace(
1706                                         PVR2_TRACE_INFO,
1707                                         "Device microcontroller firmware"
1708                                         " (re)loaded; it should now reset"
1709                                         " and reconnect.");
1710                                 break;
1711                         }
1712                         pvr2_trace(
1713                                 PVR2_TRACE_ERROR_LEGS,
1714                                 "Device initialization was not successful.");
1715                         if (hdw->fw1_state == FW1_STATE_MISSING) {
1716                                 pvr2_trace(
1717                                         PVR2_TRACE_ERROR_LEGS,
1718                                         "Giving up since device"
1719                                         " microcontroller firmware"
1720                                         " appears to be missing.");
1721                                 break;
1722                         }
1723                 }
1724                 if (procreload) {
1725                         pvr2_trace(
1726                                 PVR2_TRACE_ERROR_LEGS,
1727                                 "Attempting pvrusb2 recovery by reloading"
1728                                 " primary firmware.");
1729                         pvr2_trace(
1730                                 PVR2_TRACE_ERROR_LEGS,
1731                                 "If this works, device should disconnect"
1732                                 " and reconnect in a sane state.");
1733                         hdw->fw1_state = FW1_STATE_UNKNOWN;
1734                         pvr2_upload_firmware1(hdw);
1735                 } else {
1736                         pvr2_trace(
1737                                 PVR2_TRACE_ERROR_LEGS,
1738                                 "***WARNING*** pvrusb2 device hardware"
1739                                 " appears to be jammed"
1740                                 " and I can't clear it.");
1741                         pvr2_trace(
1742                                 PVR2_TRACE_ERROR_LEGS,
1743                                 "You might need to power cycle"
1744                                 " the pvrusb2 device"
1745                                 " in order to recover.");
1746                 }
1747         } while (0); LOCK_GIVE(hdw->big_lock);
1748         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_setup(hdw=%p) end",hdw);
1749         return hdw->flag_init_ok;
1750 }
1751
1752
1753 /* Create and return a structure for interacting with the underlying
1754    hardware */
1755 struct pvr2_hdw *pvr2_hdw_create(struct usb_interface *intf,
1756                                  const struct usb_device_id *devid)
1757 {
1758         unsigned int idx,cnt1,cnt2;
1759         struct pvr2_hdw *hdw;
1760         unsigned int hdw_type;
1761         int valid_std_mask;
1762         struct pvr2_ctrl *cptr;
1763         __u8 ifnum;
1764         struct v4l2_queryctrl qctrl;
1765         struct pvr2_ctl_info *ciptr;
1766
1767         hdw_type = devid - pvr2_device_table;
1768         if (hdw_type >=
1769             sizeof(pvr2_device_names)/sizeof(pvr2_device_names[0])) {
1770                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1771                            "Bogus device type of %u reported",hdw_type);
1772                 return NULL;
1773         }
1774
1775         hdw = kmalloc(sizeof(*hdw),GFP_KERNEL);
1776         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_create: hdw=%p, type \"%s\"",
1777                    hdw,pvr2_device_names[hdw_type]);
1778         if (!hdw) goto fail;
1779         memset(hdw,0,sizeof(*hdw));
1780         cx2341x_fill_defaults(&hdw->enc_ctl_state);
1781
1782         hdw->control_cnt = CTRLDEF_COUNT;
1783         hdw->control_cnt += MPEGDEF_COUNT;
1784         hdw->controls = kmalloc(sizeof(struct pvr2_ctrl) * hdw->control_cnt,
1785                                 GFP_KERNEL);
1786         if (!hdw->controls) goto fail;
1787         memset(hdw->controls,0,sizeof(struct pvr2_ctrl) * hdw->control_cnt);
1788         hdw->hdw_type = hdw_type;
1789         for (idx = 0; idx < hdw->control_cnt; idx++) {
1790                 cptr = hdw->controls + idx;
1791                 cptr->hdw = hdw;
1792         }
1793         for (idx = 0; idx < 32; idx++) {
1794                 hdw->std_mask_ptrs[idx] = hdw->std_mask_names[idx];
1795         }
1796         for (idx = 0; idx < CTRLDEF_COUNT; idx++) {
1797                 cptr = hdw->controls + idx;
1798                 cptr->info = control_defs+idx;
1799         }
1800         /* Define and configure additional controls from cx2341x module. */
1801         hdw->mpeg_ctrl_info = kmalloc(
1802                 sizeof(*(hdw->mpeg_ctrl_info)) * MPEGDEF_COUNT, GFP_KERNEL);
1803         if (!hdw->mpeg_ctrl_info) goto fail;
1804         memset(hdw->mpeg_ctrl_info,0,
1805                sizeof(*(hdw->mpeg_ctrl_info)) * MPEGDEF_COUNT);
1806         for (idx = 0; idx < MPEGDEF_COUNT; idx++) {
1807                 cptr = hdw->controls + idx + CTRLDEF_COUNT;
1808                 ciptr = &(hdw->mpeg_ctrl_info[idx].info);
1809                 ciptr->desc = hdw->mpeg_ctrl_info[idx].desc;
1810                 ciptr->name = mpeg_ids[idx].strid;
1811                 ciptr->v4l_id = mpeg_ids[idx].id;
1812                 ciptr->skip_init = !0;
1813                 ciptr->get_value = ctrl_cx2341x_get;
1814                 ciptr->get_v4lflags = ctrl_cx2341x_getv4lflags;
1815                 ciptr->is_dirty = ctrl_cx2341x_is_dirty;
1816                 if (!idx) ciptr->clear_dirty = ctrl_cx2341x_clear_dirty;
1817                 qctrl.id = ciptr->v4l_id;
1818                 cx2341x_ctrl_query(&hdw->enc_ctl_state,&qctrl);
1819                 if (!(qctrl.flags & V4L2_CTRL_FLAG_READ_ONLY)) {
1820                         ciptr->set_value = ctrl_cx2341x_set;
1821                 }
1822                 strncpy(hdw->mpeg_ctrl_info[idx].desc,qctrl.name,
1823                         PVR2_CTLD_INFO_DESC_SIZE);
1824                 hdw->mpeg_ctrl_info[idx].desc[PVR2_CTLD_INFO_DESC_SIZE-1] = 0;
1825                 ciptr->default_value = qctrl.default_value;
1826                 switch (qctrl.type) {
1827                 default:
1828                 case V4L2_CTRL_TYPE_INTEGER:
1829                         ciptr->type = pvr2_ctl_int;
1830                         ciptr->def.type_int.min_value = qctrl.minimum;
1831                         ciptr->def.type_int.max_value = qctrl.maximum;
1832                         break;
1833                 case V4L2_CTRL_TYPE_BOOLEAN:
1834                         ciptr->type = pvr2_ctl_bool;
1835                         break;
1836                 case V4L2_CTRL_TYPE_MENU:
1837                         ciptr->type = pvr2_ctl_enum;
1838                         ciptr->def.type_enum.value_names =
1839                                 cx2341x_ctrl_get_menu(ciptr->v4l_id);
1840                         for (cnt1 = 0;
1841                              ciptr->def.type_enum.value_names[cnt1] != NULL;
1842                              cnt1++) { }
1843                         ciptr->def.type_enum.count = cnt1;
1844                         break;
1845                 }
1846                 cptr->info = ciptr;
1847         }
1848
1849         // Initialize video standard enum dynamic control
1850         cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDENUM);
1851         if (cptr) {
1852                 memcpy(&hdw->std_info_enum,cptr->info,
1853                        sizeof(hdw->std_info_enum));
1854                 cptr->info = &hdw->std_info_enum;
1855
1856         }
1857         // Initialize control data regarding video standard masks
1858         valid_std_mask = pvr2_std_get_usable();
1859         for (idx = 0; idx < 32; idx++) {
1860                 if (!(valid_std_mask & (1 << idx))) continue;
1861                 cnt1 = pvr2_std_id_to_str(
1862                         hdw->std_mask_names[idx],
1863                         sizeof(hdw->std_mask_names[idx])-1,
1864                         1 << idx);
1865                 hdw->std_mask_names[idx][cnt1] = 0;
1866         }
1867         cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDAVAIL);
1868         if (cptr) {
1869                 memcpy(&hdw->std_info_avail,cptr->info,
1870                        sizeof(hdw->std_info_avail));
1871                 cptr->info = &hdw->std_info_avail;
1872                 hdw->std_info_avail.def.type_bitmask.bit_names =
1873                         hdw->std_mask_ptrs;
1874                 hdw->std_info_avail.def.type_bitmask.valid_bits =
1875                         valid_std_mask;
1876         }
1877         cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDCUR);
1878         if (cptr) {
1879                 memcpy(&hdw->std_info_cur,cptr->info,
1880                        sizeof(hdw->std_info_cur));
1881                 cptr->info = &hdw->std_info_cur;
1882                 hdw->std_info_cur.def.type_bitmask.bit_names =
1883                         hdw->std_mask_ptrs;
1884                 hdw->std_info_avail.def.type_bitmask.valid_bits =
1885                         valid_std_mask;
1886         }
1887
1888         hdw->eeprom_addr = -1;
1889         hdw->unit_number = -1;
1890         hdw->v4l_minor_number = -1;
1891         hdw->ctl_write_buffer = kmalloc(PVR2_CTL_BUFFSIZE,GFP_KERNEL);
1892         if (!hdw->ctl_write_buffer) goto fail;
1893         hdw->ctl_read_buffer = kmalloc(PVR2_CTL_BUFFSIZE,GFP_KERNEL);
1894         if (!hdw->ctl_read_buffer) goto fail;
1895         hdw->ctl_write_urb = usb_alloc_urb(0,GFP_KERNEL);
1896         if (!hdw->ctl_write_urb) goto fail;
1897         hdw->ctl_read_urb = usb_alloc_urb(0,GFP_KERNEL);
1898         if (!hdw->ctl_read_urb) goto fail;
1899
1900         down(&pvr2_unit_sem); do {
1901                 for (idx = 0; idx < PVR_NUM; idx++) {
1902                         if (unit_pointers[idx]) continue;
1903                         hdw->unit_number = idx;
1904                         unit_pointers[idx] = hdw;
1905                         break;
1906                 }
1907         } while (0); up(&pvr2_unit_sem);
1908
1909         cnt1 = 0;
1910         cnt2 = scnprintf(hdw->name+cnt1,sizeof(hdw->name)-cnt1,"pvrusb2");
1911         cnt1 += cnt2;
1912         if (hdw->unit_number >= 0) {
1913                 cnt2 = scnprintf(hdw->name+cnt1,sizeof(hdw->name)-cnt1,"_%c",
1914                                  ('a' + hdw->unit_number));
1915                 cnt1 += cnt2;
1916         }
1917         if (cnt1 >= sizeof(hdw->name)) cnt1 = sizeof(hdw->name)-1;
1918         hdw->name[cnt1] = 0;
1919
1920         pvr2_trace(PVR2_TRACE_INIT,"Driver unit number is %d, name is %s",
1921                    hdw->unit_number,hdw->name);
1922
1923         hdw->tuner_type = -1;
1924         hdw->flag_ok = !0;
1925         /* Initialize the mask of subsystems that we will shut down when we
1926            stop streaming. */
1927         hdw->subsys_stream_mask = PVR2_SUBSYS_RUN_ALL;
1928         hdw->subsys_stream_mask |= (1<<PVR2_SUBSYS_B_ENC_CFG);
1929
1930         pvr2_trace(PVR2_TRACE_INIT,"subsys_stream_mask: 0x%lx",
1931                    hdw->subsys_stream_mask);
1932
1933         hdw->usb_intf = intf;
1934         hdw->usb_dev = interface_to_usbdev(intf);
1935
1936         ifnum = hdw->usb_intf->cur_altsetting->desc.bInterfaceNumber;
1937         usb_set_interface(hdw->usb_dev,ifnum,0);
1938
1939         mutex_init(&hdw->ctl_lock_mutex);
1940         mutex_init(&hdw->big_lock_mutex);
1941
1942         return hdw;
1943  fail:
1944         if (hdw) {
1945                 if (hdw->ctl_read_urb) usb_free_urb(hdw->ctl_read_urb);
1946                 if (hdw->ctl_write_urb) usb_free_urb(hdw->ctl_write_urb);
1947                 if (hdw->ctl_read_buffer) kfree(hdw->ctl_read_buffer);
1948                 if (hdw->ctl_write_buffer) kfree(hdw->ctl_write_buffer);
1949                 if (hdw->controls) kfree(hdw->controls);
1950                 if (hdw->mpeg_ctrl_info) kfree(hdw->mpeg_ctrl_info);
1951                 kfree(hdw);
1952         }
1953         return NULL;
1954 }
1955
1956
1957 /* Remove _all_ associations between this driver and the underlying USB
1958    layer. */
1959 static void pvr2_hdw_remove_usb_stuff(struct pvr2_hdw *hdw)
1960 {
1961         if (hdw->flag_disconnected) return;
1962         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_remove_usb_stuff: hdw=%p",hdw);
1963         if (hdw->ctl_read_urb) {
1964                 usb_kill_urb(hdw->ctl_read_urb);
1965                 usb_free_urb(hdw->ctl_read_urb);
1966                 hdw->ctl_read_urb = NULL;
1967         }
1968         if (hdw->ctl_write_urb) {
1969                 usb_kill_urb(hdw->ctl_write_urb);
1970                 usb_free_urb(hdw->ctl_write_urb);
1971                 hdw->ctl_write_urb = NULL;
1972         }
1973         if (hdw->ctl_read_buffer) {
1974                 kfree(hdw->ctl_read_buffer);
1975                 hdw->ctl_read_buffer = NULL;
1976         }
1977         if (hdw->ctl_write_buffer) {
1978                 kfree(hdw->ctl_write_buffer);
1979                 hdw->ctl_write_buffer = NULL;
1980         }
1981         pvr2_hdw_render_useless_unlocked(hdw);
1982         hdw->flag_disconnected = !0;
1983         hdw->usb_dev = NULL;
1984         hdw->usb_intf = NULL;
1985 }
1986
1987
1988 /* Destroy hardware interaction structure */
1989 void pvr2_hdw_destroy(struct pvr2_hdw *hdw)
1990 {
1991         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_destroy: hdw=%p",hdw);
1992         if (hdw->fw_buffer) {
1993                 kfree(hdw->fw_buffer);
1994                 hdw->fw_buffer = NULL;
1995         }
1996         if (hdw->vid_stream) {
1997                 pvr2_stream_destroy(hdw->vid_stream);
1998                 hdw->vid_stream = NULL;
1999         }
2000         if (hdw->audio_stat) {
2001                 hdw->audio_stat->detach(hdw->audio_stat->ctxt);
2002         }
2003         if (hdw->decoder_ctrl) {
2004                 hdw->decoder_ctrl->detach(hdw->decoder_ctrl->ctxt);
2005         }
2006         pvr2_i2c_core_done(hdw);
2007         pvr2_hdw_remove_usb_stuff(hdw);
2008         down(&pvr2_unit_sem); do {
2009                 if ((hdw->unit_number >= 0) &&
2010                     (hdw->unit_number < PVR_NUM) &&
2011                     (unit_pointers[hdw->unit_number] == hdw)) {
2012                         unit_pointers[hdw->unit_number] = NULL;
2013                 }
2014         } while (0); up(&pvr2_unit_sem);
2015         if (hdw->controls) kfree(hdw->controls);
2016         if (hdw->mpeg_ctrl_info) kfree(hdw->mpeg_ctrl_info);
2017         if (hdw->std_defs) kfree(hdw->std_defs);
2018         if (hdw->std_enum_names) kfree(hdw->std_enum_names);
2019         kfree(hdw);
2020 }
2021
2022
2023 int pvr2_hdw_init_ok(struct pvr2_hdw *hdw)
2024 {
2025         return hdw->flag_init_ok;
2026 }
2027
2028
2029 int pvr2_hdw_dev_ok(struct pvr2_hdw *hdw)
2030 {
2031         return (hdw && hdw->flag_ok);
2032 }
2033
2034
2035 /* Called when hardware has been unplugged */
2036 void pvr2_hdw_disconnect(struct pvr2_hdw *hdw)
2037 {
2038         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_disconnect(hdw=%p)",hdw);
2039         LOCK_TAKE(hdw->big_lock);
2040         LOCK_TAKE(hdw->ctl_lock);
2041         pvr2_hdw_remove_usb_stuff(hdw);
2042         LOCK_GIVE(hdw->ctl_lock);
2043         LOCK_GIVE(hdw->big_lock);
2044 }
2045
2046
2047 // Attempt to autoselect an appropriate value for std_enum_cur given
2048 // whatever is currently in std_mask_cur
2049 static void pvr2_hdw_internal_find_stdenum(struct pvr2_hdw *hdw)
2050 {
2051         unsigned int idx;
2052         for (idx = 1; idx < hdw->std_enum_cnt; idx++) {
2053                 if (hdw->std_defs[idx-1].id == hdw->std_mask_cur) {
2054                         hdw->std_enum_cur = idx;
2055                         return;
2056                 }
2057         }
2058         hdw->std_enum_cur = 0;
2059 }
2060
2061
2062 // Calculate correct set of enumerated standards based on currently known
2063 // set of available standards bits.
2064 static void pvr2_hdw_internal_set_std_avail(struct pvr2_hdw *hdw)
2065 {
2066         struct v4l2_standard *newstd;
2067         unsigned int std_cnt;
2068         unsigned int idx;
2069
2070         newstd = pvr2_std_create_enum(&std_cnt,hdw->std_mask_avail);
2071
2072         if (hdw->std_defs) {
2073                 kfree(hdw->std_defs);
2074                 hdw->std_defs = NULL;
2075         }
2076         hdw->std_enum_cnt = 0;
2077         if (hdw->std_enum_names) {
2078                 kfree(hdw->std_enum_names);
2079                 hdw->std_enum_names = NULL;
2080         }
2081
2082         if (!std_cnt) {
2083                 pvr2_trace(
2084                         PVR2_TRACE_ERROR_LEGS,
2085                         "WARNING: Failed to identify any viable standards");
2086         }
2087         hdw->std_enum_names = kmalloc(sizeof(char *)*(std_cnt+1),GFP_KERNEL);
2088         hdw->std_enum_names[0] = "none";
2089         for (idx = 0; idx < std_cnt; idx++) {
2090                 hdw->std_enum_names[idx+1] =
2091                         newstd[idx].name;
2092         }
2093         // Set up the dynamic control for this standard
2094         hdw->std_info_enum.def.type_enum.value_names = hdw->std_enum_names;
2095         hdw->std_info_enum.def.type_enum.count = std_cnt+1;
2096         hdw->std_defs = newstd;
2097         hdw->std_enum_cnt = std_cnt+1;
2098         hdw->std_enum_cur = 0;
2099         hdw->std_info_cur.def.type_bitmask.valid_bits = hdw->std_mask_avail;
2100 }
2101
2102
2103 int pvr2_hdw_get_stdenum_value(struct pvr2_hdw *hdw,
2104                                struct v4l2_standard *std,
2105                                unsigned int idx)
2106 {
2107         int ret = -EINVAL;
2108         if (!idx) return ret;
2109         LOCK_TAKE(hdw->big_lock); do {
2110                 if (idx >= hdw->std_enum_cnt) break;
2111                 idx--;
2112                 memcpy(std,hdw->std_defs+idx,sizeof(*std));
2113                 ret = 0;
2114         } while (0); LOCK_GIVE(hdw->big_lock);
2115         return ret;
2116 }
2117
2118
2119 /* Get the number of defined controls */
2120 unsigned int pvr2_hdw_get_ctrl_count(struct pvr2_hdw *hdw)
2121 {
2122         return hdw->control_cnt;
2123 }
2124
2125
2126 /* Retrieve a control handle given its index (0..count-1) */
2127 struct pvr2_ctrl *pvr2_hdw_get_ctrl_by_index(struct pvr2_hdw *hdw,
2128                                              unsigned int idx)
2129 {
2130         if (idx >= hdw->control_cnt) return NULL;
2131         return hdw->controls + idx;
2132 }
2133
2134
2135 /* Retrieve a control handle given its index (0..count-1) */
2136 struct pvr2_ctrl *pvr2_hdw_get_ctrl_by_id(struct pvr2_hdw *hdw,
2137                                           unsigned int ctl_id)
2138 {
2139         struct pvr2_ctrl *cptr;
2140         unsigned int idx;
2141         int i;
2142
2143         /* This could be made a lot more efficient, but for now... */
2144         for (idx = 0; idx < hdw->control_cnt; idx++) {
2145                 cptr = hdw->controls + idx;
2146                 i = cptr->info->internal_id;
2147                 if (i && (i == ctl_id)) return cptr;
2148         }
2149         return NULL;
2150 }
2151
2152
2153 /* Given a V4L ID, retrieve the control structure associated with it. */
2154 struct pvr2_ctrl *pvr2_hdw_get_ctrl_v4l(struct pvr2_hdw *hdw,unsigned int ctl_id)
2155 {
2156         struct pvr2_ctrl *cptr;
2157         unsigned int idx;
2158         int i;
2159
2160         /* This could be made a lot more efficient, but for now... */
2161         for (idx = 0; idx < hdw->control_cnt; idx++) {
2162                 cptr = hdw->controls + idx;
2163                 i = cptr->info->v4l_id;
2164                 if (i && (i == ctl_id)) return cptr;
2165         }
2166         return NULL;
2167 }
2168
2169
2170 /* Given a V4L ID for its immediate predecessor, retrieve the control
2171    structure associated with it. */
2172 struct pvr2_ctrl *pvr2_hdw_get_ctrl_nextv4l(struct pvr2_hdw *hdw,
2173                                             unsigned int ctl_id)
2174 {
2175         struct pvr2_ctrl *cptr,*cp2;
2176         unsigned int idx;
2177         int i;
2178
2179         /* This could be made a lot more efficient, but for now... */
2180         cp2 = NULL;
2181         for (idx = 0; idx < hdw->control_cnt; idx++) {
2182                 cptr = hdw->controls + idx;
2183                 i = cptr->info->v4l_id;
2184                 if (!i) continue;
2185                 if (i <= ctl_id) continue;
2186                 if (cp2 && (cp2->info->v4l_id < i)) continue;
2187                 cp2 = cptr;
2188         }
2189         return cp2;
2190         return NULL;
2191 }
2192
2193
2194 static const char *get_ctrl_typename(enum pvr2_ctl_type tp)
2195 {
2196         switch (tp) {
2197         case pvr2_ctl_int: return "integer";
2198         case pvr2_ctl_enum: return "enum";
2199         case pvr2_ctl_bool: return "boolean";
2200         case pvr2_ctl_bitmask: return "bitmask";
2201         }
2202         return "";
2203 }
2204
2205
2206 /* Commit all control changes made up to this point.  Subsystems can be
2207    indirectly affected by these changes.  For a given set of things being
2208    committed, we'll clear the affected subsystem bits and then once we're
2209    done committing everything we'll make a request to restore the subsystem
2210    state(s) back to their previous value before this function was called.
2211    Thus we can automatically reconfigure affected pieces of the driver as
2212    controls are changed. */
2213 static int pvr2_hdw_commit_ctl_internal(struct pvr2_hdw *hdw)
2214 {
2215         unsigned long saved_subsys_mask = hdw->subsys_enabled_mask;
2216         unsigned long stale_subsys_mask = 0;
2217         unsigned int idx;
2218         struct pvr2_ctrl *cptr;
2219         int value;
2220         int commit_flag = 0;
2221         char buf[100];
2222         unsigned int bcnt,ccnt;
2223
2224         for (idx = 0; idx < hdw->control_cnt; idx++) {
2225                 cptr = hdw->controls + idx;
2226                 if (cptr->info->is_dirty == 0) continue;
2227                 if (!cptr->info->is_dirty(cptr)) continue;
2228                 if (!commit_flag) {
2229                         commit_flag = !0;
2230                 }
2231
2232                 bcnt = scnprintf(buf,sizeof(buf),"\"%s\" <-- ",
2233                                  cptr->info->name);
2234                 value = 0;
2235                 cptr->info->get_value(cptr,&value);
2236                 pvr2_ctrl_value_to_sym_internal(cptr,~0,value,
2237                                                 buf+bcnt,
2238                                                 sizeof(buf)-bcnt,&ccnt);
2239                 bcnt += ccnt;
2240                 bcnt += scnprintf(buf+bcnt,sizeof(buf)-bcnt," <%s>",
2241                                   get_ctrl_typename(cptr->info->type));
2242                 pvr2_trace(PVR2_TRACE_CTL,
2243                            "/*--TRACE_COMMIT--*/ %.*s",
2244                            bcnt,buf);
2245         }
2246
2247         if (!commit_flag) {
2248                 /* Nothing has changed */
2249                 return 0;
2250         }
2251
2252         /* When video standard changes, reset the hres and vres values -
2253            but if the user has pending changes there, then let the changes
2254            take priority. */
2255         if (hdw->std_dirty) {
2256                 /* Rewrite the vertical resolution to be appropriate to the
2257                    video standard that has been selected. */
2258                 int nvres;
2259                 if (hdw->std_mask_cur & V4L2_STD_525_60) {
2260                         nvres = 480;
2261                 } else {
2262                         nvres = 576;
2263                 }
2264                 if (nvres != hdw->res_ver_val) {
2265                         hdw->res_ver_val = nvres;
2266                         hdw->res_ver_dirty = !0;
2267                 }
2268         }
2269
2270         if (hdw->std_dirty ||
2271             hdw->enc_stale ||
2272             hdw->srate_dirty ||
2273             hdw->res_ver_dirty ||
2274             hdw->res_hor_dirty ||
2275             0) {
2276                 /* If any of this changes, then the encoder needs to be
2277                    reconfigured, and we need to reset the stream. */
2278                 stale_subsys_mask |= (1<<PVR2_SUBSYS_B_ENC_CFG);
2279         }
2280
2281         if (hdw->srate_dirty) {
2282                 /* Write new sample rate into control structure since
2283                  * the master copy is stale.  We must track srate
2284                  * separate from the mpeg control structure because
2285                  * other logic also uses this value. */
2286                 struct v4l2_ext_controls cs;
2287                 struct v4l2_ext_control c1;
2288                 memset(&cs,0,sizeof(cs));
2289                 memset(&c1,0,sizeof(c1));
2290                 cs.controls = &c1;
2291                 cs.count = 1;
2292                 c1.id = V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ;
2293                 c1.value = hdw->srate_val;
2294                 cx2341x_ext_ctrls(&hdw->enc_ctl_state,&cs,VIDIOC_S_EXT_CTRLS);
2295         }
2296
2297         /* Scan i2c core at this point - before we clear all the dirty
2298            bits.  Various parts of the i2c core will notice dirty bits as
2299            appropriate and arrange to broadcast or directly send updates to
2300            the client drivers in order to keep everything in sync */
2301         pvr2_i2c_core_check_stale(hdw);
2302
2303         for (idx = 0; idx < hdw->control_cnt; idx++) {
2304                 cptr = hdw->controls + idx;
2305                 if (!cptr->info->clear_dirty) continue;
2306                 cptr->info->clear_dirty(cptr);
2307         }
2308
2309         /* Now execute i2c core update */
2310         pvr2_i2c_core_sync(hdw);
2311
2312         pvr2_hdw_subsys_bit_chg_no_lock(hdw,stale_subsys_mask,0);
2313         pvr2_hdw_subsys_bit_chg_no_lock(hdw,~0,saved_subsys_mask);
2314
2315         return 0;
2316 }
2317
2318
2319 int pvr2_hdw_commit_ctl(struct pvr2_hdw *hdw)
2320 {
2321         LOCK_TAKE(hdw->big_lock); do {
2322                 pvr2_hdw_commit_ctl_internal(hdw);
2323         } while (0); LOCK_GIVE(hdw->big_lock);
2324         return 0;
2325 }
2326
2327
2328 void pvr2_hdw_poll(struct pvr2_hdw *hdw)
2329 {
2330         LOCK_TAKE(hdw->big_lock); do {
2331                 pvr2_i2c_core_sync(hdw);
2332         } while (0); LOCK_GIVE(hdw->big_lock);
2333 }
2334
2335
2336 void pvr2_hdw_setup_poll_trigger(struct pvr2_hdw *hdw,
2337                                  void (*func)(void *),
2338                                  void *data)
2339 {
2340         LOCK_TAKE(hdw->big_lock); do {
2341                 hdw->poll_trigger_func = func;
2342                 hdw->poll_trigger_data = data;
2343         } while (0); LOCK_GIVE(hdw->big_lock);
2344 }
2345
2346
2347 void pvr2_hdw_poll_trigger_unlocked(struct pvr2_hdw *hdw)
2348 {
2349         if (hdw->poll_trigger_func) {
2350                 hdw->poll_trigger_func(hdw->poll_trigger_data);
2351         }
2352 }
2353
2354 /* Return name for this driver instance */
2355 const char *pvr2_hdw_get_driver_name(struct pvr2_hdw *hdw)
2356 {
2357         return hdw->name;
2358 }
2359
2360
2361 /* Return bit mask indicating signal status */
2362 static unsigned int pvr2_hdw_get_signal_status_internal(struct pvr2_hdw *hdw)
2363 {
2364         unsigned int msk = 0;
2365         switch (hdw->input_val) {
2366         case PVR2_CVAL_INPUT_TV:
2367         case PVR2_CVAL_INPUT_RADIO:
2368                 if (hdw->decoder_ctrl &&
2369                     hdw->decoder_ctrl->tuned(hdw->decoder_ctrl->ctxt)) {
2370                         msk |= PVR2_SIGNAL_OK;
2371                         if (hdw->audio_stat &&
2372                             hdw->audio_stat->status(hdw->audio_stat->ctxt)) {
2373                                 if (hdw->flag_stereo) {
2374                                         msk |= PVR2_SIGNAL_STEREO;
2375                                 }
2376                                 if (hdw->flag_bilingual) {
2377                                         msk |= PVR2_SIGNAL_SAP;
2378                                 }
2379                         }
2380                 }
2381                 break;
2382         default:
2383                 msk |= PVR2_SIGNAL_OK | PVR2_SIGNAL_STEREO;
2384         }
2385         return msk;
2386 }
2387
2388
2389 int pvr2_hdw_is_hsm(struct pvr2_hdw *hdw)
2390 {
2391         int result;
2392         LOCK_TAKE(hdw->ctl_lock); do {
2393                 hdw->cmd_buffer[0] = 0x0b;
2394                 result = pvr2_send_request(hdw,
2395                                            hdw->cmd_buffer,1,
2396                                            hdw->cmd_buffer,1);
2397                 if (result < 0) break;
2398                 result = (hdw->cmd_buffer[0] != 0);
2399         } while(0); LOCK_GIVE(hdw->ctl_lock);
2400         return result;
2401 }
2402
2403
2404 /* Return bit mask indicating signal status */
2405 unsigned int pvr2_hdw_get_signal_status(struct pvr2_hdw *hdw)
2406 {
2407         unsigned int msk = 0;
2408         LOCK_TAKE(hdw->big_lock); do {
2409                 msk = pvr2_hdw_get_signal_status_internal(hdw);
2410         } while (0); LOCK_GIVE(hdw->big_lock);
2411         return msk;
2412 }
2413
2414
2415 /* Get handle to video output stream */
2416 struct pvr2_stream *pvr2_hdw_get_video_stream(struct pvr2_hdw *hp)
2417 {
2418         return hp->vid_stream;
2419 }
2420
2421
2422 void pvr2_hdw_trigger_module_log(struct pvr2_hdw *hdw)
2423 {
2424         int nr = pvr2_hdw_get_unit_number(hdw);
2425         LOCK_TAKE(hdw->big_lock); do {
2426                 hdw->log_requested = !0;
2427                 printk(KERN_INFO "pvrusb2: =================  START STATUS CARD #%d  =================\n", nr);
2428                 pvr2_i2c_core_check_stale(hdw);
2429                 hdw->log_requested = 0;
2430                 pvr2_i2c_core_sync(hdw);
2431                 pvr2_trace(PVR2_TRACE_INFO,"cx2341x config:");
2432                 cx2341x_log_status(&hdw->enc_ctl_state, "pvrusb2");
2433                 printk(KERN_INFO "pvrusb2: ==================  END STATUS CARD #%d  ==================\n", nr);
2434         } while (0); LOCK_GIVE(hdw->big_lock);
2435 }
2436
2437 void pvr2_hdw_cpufw_set_enabled(struct pvr2_hdw *hdw, int enable_flag)
2438 {
2439         int ret;
2440         u16 address;
2441         unsigned int pipe;
2442         LOCK_TAKE(hdw->big_lock); do {
2443                 if ((hdw->fw_buffer == 0) == !enable_flag) break;
2444
2445                 if (!enable_flag) {
2446                         pvr2_trace(PVR2_TRACE_FIRMWARE,
2447                                    "Cleaning up after CPU firmware fetch");
2448                         kfree(hdw->fw_buffer);
2449                         hdw->fw_buffer = NULL;
2450                         hdw->fw_size = 0;
2451                         /* Now release the CPU.  It will disconnect and
2452                            reconnect later. */
2453                         pvr2_hdw_cpureset_assert(hdw,0);
2454                         break;
2455                 }
2456
2457                 pvr2_trace(PVR2_TRACE_FIRMWARE,
2458                            "Preparing to suck out CPU firmware");
2459                 hdw->fw_size = 0x2000;
2460                 hdw->fw_buffer = kmalloc(hdw->fw_size,GFP_KERNEL);
2461                 if (!hdw->fw_buffer) {
2462                         hdw->fw_size = 0;
2463                         break;
2464                 }
2465
2466                 memset(hdw->fw_buffer,0,hdw->fw_size);
2467
2468                 /* We have to hold the CPU during firmware upload. */
2469                 pvr2_hdw_cpureset_assert(hdw,1);
2470
2471                 /* download the firmware from address 0000-1fff in 2048
2472                    (=0x800) bytes chunk. */
2473
2474                 pvr2_trace(PVR2_TRACE_FIRMWARE,"Grabbing CPU firmware");
2475                 pipe = usb_rcvctrlpipe(hdw->usb_dev, 0);
2476                 for(address = 0; address < hdw->fw_size; address += 0x800) {
2477                         ret = usb_control_msg(hdw->usb_dev,pipe,0xa0,0xc0,
2478                                               address,0,
2479                                               hdw->fw_buffer+address,0x800,HZ);
2480                         if (ret < 0) break;
2481                 }
2482
2483                 pvr2_trace(PVR2_TRACE_FIRMWARE,"Done grabbing CPU firmware");
2484
2485         } while (0); LOCK_GIVE(hdw->big_lock);
2486 }
2487
2488
2489 /* Return true if we're in a mode for retrieval CPU firmware */
2490 int pvr2_hdw_cpufw_get_enabled(struct pvr2_hdw *hdw)
2491 {
2492         return hdw->fw_buffer != 0;
2493 }
2494
2495
2496 int pvr2_hdw_cpufw_get(struct pvr2_hdw *hdw,unsigned int offs,
2497                        char *buf,unsigned int cnt)
2498 {
2499         int ret = -EINVAL;
2500         LOCK_TAKE(hdw->big_lock); do {
2501                 if (!buf) break;
2502                 if (!cnt) break;
2503
2504                 if (!hdw->fw_buffer) {
2505                         ret = -EIO;
2506                         break;
2507                 }
2508
2509                 if (offs >= hdw->fw_size) {
2510                         pvr2_trace(PVR2_TRACE_FIRMWARE,
2511                                    "Read firmware data offs=%d EOF",
2512                                    offs);
2513                         ret = 0;
2514                         break;
2515                 }
2516
2517                 if (offs + cnt > hdw->fw_size) cnt = hdw->fw_size - offs;
2518
2519                 memcpy(buf,hdw->fw_buffer+offs,cnt);
2520
2521                 pvr2_trace(PVR2_TRACE_FIRMWARE,
2522                            "Read firmware data offs=%d cnt=%d",
2523                            offs,cnt);
2524                 ret = cnt;
2525         } while (0); LOCK_GIVE(hdw->big_lock);
2526
2527         return ret;
2528 }
2529
2530
2531 int pvr2_hdw_v4l_get_minor_number(struct pvr2_hdw *hdw)
2532 {
2533         return hdw->v4l_minor_number;
2534 }
2535
2536
2537 /* Store the v4l minor device number */
2538 void pvr2_hdw_v4l_store_minor_number(struct pvr2_hdw *hdw,int v)
2539 {
2540         hdw->v4l_minor_number = v;
2541 }
2542
2543
2544 static void pvr2_ctl_write_complete(struct urb *urb, struct pt_regs *regs)
2545 {
2546         struct pvr2_hdw *hdw = urb->context;
2547         hdw->ctl_write_pend_flag = 0;
2548         if (hdw->ctl_read_pend_flag) return;
2549         complete(&hdw->ctl_done);
2550 }
2551
2552
2553 static void pvr2_ctl_read_complete(struct urb *urb, struct pt_regs *regs)
2554 {
2555         struct pvr2_hdw *hdw = urb->context;
2556         hdw->ctl_read_pend_flag = 0;
2557         if (hdw->ctl_write_pend_flag) return;
2558         complete(&hdw->ctl_done);
2559 }
2560
2561
2562 static void pvr2_ctl_timeout(unsigned long data)
2563 {
2564         struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
2565         if (hdw->ctl_write_pend_flag || hdw->ctl_read_pend_flag) {
2566                 hdw->ctl_timeout_flag = !0;
2567                 if (hdw->ctl_write_pend_flag && hdw->ctl_write_urb) {
2568                         usb_unlink_urb(hdw->ctl_write_urb);
2569                 }
2570                 if (hdw->ctl_read_pend_flag && hdw->ctl_read_urb) {
2571                         usb_unlink_urb(hdw->ctl_read_urb);
2572                 }
2573         }
2574 }
2575
2576
2577 /* Issue a command and get a response from the device.  This extended
2578    version includes a probe flag (which if set means that device errors
2579    should not be logged or treated as fatal) and a timeout in jiffies.
2580    This can be used to non-lethally probe the health of endpoint 1. */
2581 static int pvr2_send_request_ex(struct pvr2_hdw *hdw,
2582                                 unsigned int timeout,int probe_fl,
2583                                 void *write_data,unsigned int write_len,
2584                                 void *read_data,unsigned int read_len)
2585 {
2586         unsigned int idx;
2587         int status = 0;
2588         struct timer_list timer;
2589         if (!hdw->ctl_lock_held) {
2590                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2591                            "Attempted to execute control transfer"
2592                            " without lock!!");
2593                 return -EDEADLK;
2594         }
2595         if ((!hdw->flag_ok) && !probe_fl) {
2596                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2597                            "Attempted to execute control transfer"
2598                            " when device not ok");
2599                 return -EIO;
2600         }
2601         if (!(hdw->ctl_read_urb && hdw->ctl_write_urb)) {
2602                 if (!probe_fl) {
2603                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2604                                    "Attempted to execute control transfer"
2605                                    " when USB is disconnected");
2606                 }
2607                 return -ENOTTY;
2608         }
2609
2610         /* Ensure that we have sane parameters */
2611         if (!write_data) write_len = 0;
2612         if (!read_data) read_len = 0;
2613         if (write_len > PVR2_CTL_BUFFSIZE) {
2614                 pvr2_trace(
2615                         PVR2_TRACE_ERROR_LEGS,
2616                         "Attempted to execute %d byte"
2617                         " control-write transfer (limit=%d)",
2618                         write_len,PVR2_CTL_BUFFSIZE);
2619                 return -EINVAL;
2620         }
2621         if (read_len > PVR2_CTL_BUFFSIZE) {
2622                 pvr2_trace(
2623                         PVR2_TRACE_ERROR_LEGS,
2624                         "Attempted to execute %d byte"
2625                         " control-read transfer (limit=%d)",
2626                         write_len,PVR2_CTL_BUFFSIZE);
2627                 return -EINVAL;
2628         }
2629         if ((!write_len) && (!read_len)) {
2630                 pvr2_trace(
2631                         PVR2_TRACE_ERROR_LEGS,
2632                         "Attempted to execute null control transfer?");
2633                 return -EINVAL;
2634         }
2635
2636
2637         hdw->cmd_debug_state = 1;
2638         if (write_len) {
2639                 hdw->cmd_debug_code = ((unsigned char *)write_data)[0];
2640         } else {
2641                 hdw->cmd_debug_code = 0;
2642         }
2643         hdw->cmd_debug_write_len = write_len;
2644         hdw->cmd_debug_read_len = read_len;
2645
2646         /* Initialize common stuff */
2647         init_completion(&hdw->ctl_done);
2648         hdw->ctl_timeout_flag = 0;
2649         hdw->ctl_write_pend_flag = 0;
2650         hdw->ctl_read_pend_flag = 0;
2651         init_timer(&timer);
2652         timer.expires = jiffies + timeout;
2653         timer.data = (unsigned long)hdw;
2654         timer.function = pvr2_ctl_timeout;
2655
2656         if (write_len) {
2657                 hdw->cmd_debug_state = 2;
2658                 /* Transfer write data to internal buffer */
2659                 for (idx = 0; idx < write_len; idx++) {
2660                         hdw->ctl_write_buffer[idx] =
2661                                 ((unsigned char *)write_data)[idx];
2662                 }
2663                 /* Initiate a write request */
2664                 usb_fill_bulk_urb(hdw->ctl_write_urb,
2665                                   hdw->usb_dev,
2666                                   usb_sndbulkpipe(hdw->usb_dev,
2667                                                   PVR2_CTL_WRITE_ENDPOINT),
2668                                   hdw->ctl_write_buffer,
2669                                   write_len,
2670                                   pvr2_ctl_write_complete,
2671                                   hdw);
2672                 hdw->ctl_write_urb->actual_length = 0;
2673                 hdw->ctl_write_pend_flag = !0;
2674                 status = usb_submit_urb(hdw->ctl_write_urb,GFP_KERNEL);
2675                 if (status < 0) {
2676                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2677                                    "Failed to submit write-control"
2678                                    " URB status=%d",status);
2679                         hdw->ctl_write_pend_flag = 0;
2680                         goto done;
2681                 }
2682         }
2683
2684         if (read_len) {
2685                 hdw->cmd_debug_state = 3;
2686                 memset(hdw->ctl_read_buffer,0x43,read_len);
2687                 /* Initiate a read request */
2688                 usb_fill_bulk_urb(hdw->ctl_read_urb,
2689                                   hdw->usb_dev,
2690                                   usb_rcvbulkpipe(hdw->usb_dev,
2691                                                   PVR2_CTL_READ_ENDPOINT),
2692                                   hdw->ctl_read_buffer,
2693                                   read_len,
2694                                   pvr2_ctl_read_complete,
2695                                   hdw);
2696                 hdw->ctl_read_urb->actual_length = 0;
2697                 hdw->ctl_read_pend_flag = !0;
2698                 status = usb_submit_urb(hdw->ctl_read_urb,GFP_KERNEL);
2699                 if (status < 0) {
2700                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2701                                    "Failed to submit read-control"
2702                                    " URB status=%d",status);
2703                         hdw->ctl_read_pend_flag = 0;
2704                         goto done;
2705                 }
2706         }
2707
2708         /* Start timer */
2709         add_timer(&timer);
2710
2711         /* Now wait for all I/O to complete */
2712         hdw->cmd_debug_state = 4;
2713         while (hdw->ctl_write_pend_flag || hdw->ctl_read_pend_flag) {
2714                 wait_for_completion(&hdw->ctl_done);
2715         }
2716         hdw->cmd_debug_state = 5;
2717
2718         /* Stop timer */
2719         del_timer_sync(&timer);
2720
2721         hdw->cmd_debug_state = 6;
2722         status = 0;
2723
2724         if (hdw->ctl_timeout_flag) {
2725                 status = -ETIMEDOUT;
2726                 if (!probe_fl) {
2727                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2728                                    "Timed out control-write");
2729                 }
2730                 goto done;
2731         }
2732
2733         if (write_len) {
2734                 /* Validate results of write request */
2735                 if ((hdw->ctl_write_urb->status != 0) &&
2736                     (hdw->ctl_write_urb->status != -ENOENT) &&
2737                     (hdw->ctl_write_urb->status != -ESHUTDOWN) &&
2738                     (hdw->ctl_write_urb->status != -ECONNRESET)) {
2739                         /* USB subsystem is reporting some kind of failure
2740                            on the write */
2741                         status = hdw->ctl_write_urb->status;
2742                         if (!probe_fl) {
2743                                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2744                                            "control-write URB failure,"
2745                                            " status=%d",
2746                                            status);
2747                         }
2748                         goto done;
2749                 }
2750                 if (hdw->ctl_write_urb->actual_length < write_len) {
2751                         /* Failed to write enough data */
2752                         status = -EIO;
2753                         if (!probe_fl) {
2754                                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2755                                            "control-write URB short,"
2756                                            " expected=%d got=%d",
2757                                            write_len,
2758                                            hdw->ctl_write_urb->actual_length);
2759                         }
2760                         goto done;
2761                 }
2762         }
2763         if (read_len) {
2764                 /* Validate results of read request */
2765                 if ((hdw->ctl_read_urb->status != 0) &&
2766                     (hdw->ctl_read_urb->status != -ENOENT) &&
2767                     (hdw->ctl_read_urb->status != -ESHUTDOWN) &&
2768                     (hdw->ctl_read_urb->status != -ECONNRESET)) {
2769                         /* USB subsystem is reporting some kind of failure
2770                            on the read */
2771                         status = hdw->ctl_read_urb->status;
2772                         if (!probe_fl) {
2773                                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2774                                            "control-read URB failure,"
2775                                            " status=%d",
2776                                            status);
2777                         }
2778                         goto done;
2779                 }
2780                 if (hdw->ctl_read_urb->actual_length < read_len) {
2781                         /* Failed to read enough data */
2782                         status = -EIO;
2783                         if (!probe_fl) {
2784                                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2785                                            "control-read URB short,"
2786                                            " expected=%d got=%d",
2787                                            read_len,
2788                                            hdw->ctl_read_urb->actual_length);
2789                         }
2790                         goto done;
2791                 }
2792                 /* Transfer retrieved data out from internal buffer */
2793                 for (idx = 0; idx < read_len; idx++) {
2794                         ((unsigned char *)read_data)[idx] =
2795                                 hdw->ctl_read_buffer[idx];
2796                 }
2797         }
2798
2799  done:
2800
2801         hdw->cmd_debug_state = 0;
2802         if ((status < 0) && (!probe_fl)) {
2803                 pvr2_hdw_render_useless_unlocked(hdw);
2804         }
2805         return status;
2806 }
2807
2808
2809 int pvr2_send_request(struct pvr2_hdw *hdw,
2810                       void *write_data,unsigned int write_len,
2811                       void *read_data,unsigned int read_len)
2812 {
2813         return pvr2_send_request_ex(hdw,HZ*4,0,
2814                                     write_data,write_len,
2815                                     read_data,read_len);
2816 }
2817
2818 int pvr2_write_register(struct pvr2_hdw *hdw, u16 reg, u32 data)
2819 {
2820         int ret;
2821
2822         LOCK_TAKE(hdw->ctl_lock);
2823
2824         hdw->cmd_buffer[0] = 0x04;  /* write register prefix */
2825         PVR2_DECOMPOSE_LE(hdw->cmd_buffer,1,data);
2826         hdw->cmd_buffer[5] = 0;
2827         hdw->cmd_buffer[6] = (reg >> 8) & 0xff;
2828         hdw->cmd_buffer[7] = reg & 0xff;
2829
2830
2831         ret = pvr2_send_request(hdw, hdw->cmd_buffer, 8, hdw->cmd_buffer, 0);
2832
2833         LOCK_GIVE(hdw->ctl_lock);
2834
2835         return ret;
2836 }
2837
2838
2839 static int pvr2_read_register(struct pvr2_hdw *hdw, u16 reg, u32 *data)
2840 {
2841         int ret = 0;
2842
2843         LOCK_TAKE(hdw->ctl_lock);
2844
2845         hdw->cmd_buffer[0] = 0x05;  /* read register prefix */
2846         hdw->cmd_buffer[1] = 0;
2847         hdw->cmd_buffer[2] = 0;
2848         hdw->cmd_buffer[3] = 0;
2849         hdw->cmd_buffer[4] = 0;
2850         hdw->cmd_buffer[5] = 0;
2851         hdw->cmd_buffer[6] = (reg >> 8) & 0xff;
2852         hdw->cmd_buffer[7] = reg & 0xff;
2853
2854         ret |= pvr2_send_request(hdw, hdw->cmd_buffer, 8, hdw->cmd_buffer, 4);
2855         *data = PVR2_COMPOSE_LE(hdw->cmd_buffer,0);
2856
2857         LOCK_GIVE(hdw->ctl_lock);
2858
2859         return ret;
2860 }
2861
2862
2863 static int pvr2_write_u16(struct pvr2_hdw *hdw, u16 data, int res)
2864 {
2865         int ret;
2866
2867         LOCK_TAKE(hdw->ctl_lock);
2868
2869         hdw->cmd_buffer[0] = (data >> 8) & 0xff;
2870         hdw->cmd_buffer[1] = data & 0xff;
2871
2872         ret = pvr2_send_request(hdw, hdw->cmd_buffer, 2, hdw->cmd_buffer, res);
2873
2874         LOCK_GIVE(hdw->ctl_lock);
2875
2876         return ret;
2877 }
2878
2879
2880 static int pvr2_write_u8(struct pvr2_hdw *hdw, u8 data, int res)
2881 {
2882         int ret;
2883
2884         LOCK_TAKE(hdw->ctl_lock);
2885
2886         hdw->cmd_buffer[0] = data;
2887
2888         ret = pvr2_send_request(hdw, hdw->cmd_buffer, 1, hdw->cmd_buffer, res);
2889
2890         LOCK_GIVE(hdw->ctl_lock);
2891
2892         return ret;
2893 }
2894
2895
2896 static void pvr2_hdw_render_useless_unlocked(struct pvr2_hdw *hdw)
2897 {
2898         if (!hdw->flag_ok) return;
2899         pvr2_trace(PVR2_TRACE_INIT,"render_useless");
2900         hdw->flag_ok = 0;
2901         if (hdw->vid_stream) {
2902                 pvr2_stream_setup(hdw->vid_stream,NULL,0,0);
2903         }
2904         hdw->flag_streaming_enabled = 0;
2905         hdw->subsys_enabled_mask = 0;
2906 }
2907
2908
2909 void pvr2_hdw_render_useless(struct pvr2_hdw *hdw)
2910 {
2911         LOCK_TAKE(hdw->ctl_lock);
2912         pvr2_hdw_render_useless_unlocked(hdw);
2913         LOCK_GIVE(hdw->ctl_lock);
2914 }
2915
2916
2917 void pvr2_hdw_device_reset(struct pvr2_hdw *hdw)
2918 {
2919         int ret;
2920         pvr2_trace(PVR2_TRACE_INIT,"Performing a device reset...");
2921         ret = usb_lock_device_for_reset(hdw->usb_dev,NULL);
2922         if (ret == 1) {
2923                 ret = usb_reset_device(hdw->usb_dev);
2924                 usb_unlock_device(hdw->usb_dev);
2925         } else {
2926                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2927                            "Failed to lock USB device ret=%d",ret);
2928         }
2929         if (init_pause_msec) {
2930                 pvr2_trace(PVR2_TRACE_INFO,
2931                            "Waiting %u msec for hardware to settle",
2932                            init_pause_msec);
2933                 msleep(init_pause_msec);
2934         }
2935
2936 }
2937
2938
2939 void pvr2_hdw_cpureset_assert(struct pvr2_hdw *hdw,int val)
2940 {
2941         char da[1];
2942         unsigned int pipe;
2943         int ret;
2944
2945         if (!hdw->usb_dev) return;
2946
2947         pvr2_trace(PVR2_TRACE_INIT,"cpureset_assert(%d)",val);
2948
2949         da[0] = val ? 0x01 : 0x00;
2950
2951         /* Write the CPUCS register on the 8051.  The lsb of the register
2952            is the reset bit; a 1 asserts reset while a 0 clears it. */
2953         pipe = usb_sndctrlpipe(hdw->usb_dev, 0);
2954         ret = usb_control_msg(hdw->usb_dev,pipe,0xa0,0x40,0xe600,0,da,1,HZ);
2955         if (ret < 0) {
2956                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2957                            "cpureset_assert(%d) error=%d",val,ret);
2958                 pvr2_hdw_render_useless(hdw);
2959         }
2960 }
2961
2962
2963 int pvr2_hdw_cmd_deep_reset(struct pvr2_hdw *hdw)
2964 {
2965         int status;
2966         LOCK_TAKE(hdw->ctl_lock); do {
2967                 pvr2_trace(PVR2_TRACE_INIT,"Requesting uproc hard reset");
2968                 hdw->flag_ok = !0;
2969                 hdw->cmd_buffer[0] = 0xdd;
2970                 status = pvr2_send_request(hdw,hdw->cmd_buffer,1,NULL,0);
2971         } while (0); LOCK_GIVE(hdw->ctl_lock);
2972         return status;
2973 }
2974
2975
2976 int pvr2_hdw_cmd_powerup(struct pvr2_hdw *hdw)
2977 {
2978         int status;
2979         LOCK_TAKE(hdw->ctl_lock); do {
2980                 pvr2_trace(PVR2_TRACE_INIT,"Requesting powerup");
2981                 hdw->cmd_buffer[0] = 0xde;
2982                 status = pvr2_send_request(hdw,hdw->cmd_buffer,1,NULL,0);
2983         } while (0); LOCK_GIVE(hdw->ctl_lock);
2984         return status;
2985 }
2986
2987
2988 int pvr2_hdw_cmd_decoder_reset(struct pvr2_hdw *hdw)
2989 {
2990         if (!hdw->decoder_ctrl) {
2991                 pvr2_trace(PVR2_TRACE_INIT,
2992                            "Unable to reset decoder: nothing attached");
2993                 return -ENOTTY;
2994         }
2995
2996         if (!hdw->decoder_ctrl->force_reset) {
2997                 pvr2_trace(PVR2_TRACE_INIT,
2998                            "Unable to reset decoder: not implemented");
2999                 return -ENOTTY;
3000         }
3001
3002         pvr2_trace(PVR2_TRACE_INIT,
3003                    "Requesting decoder reset");
3004         hdw->decoder_ctrl->force_reset(hdw->decoder_ctrl->ctxt);
3005         return 0;
3006 }
3007
3008
3009 /* Stop / start video stream transport */
3010 static int pvr2_hdw_cmd_usbstream(struct pvr2_hdw *hdw,int runFl)
3011 {
3012         int status;
3013         LOCK_TAKE(hdw->ctl_lock); do {
3014                 hdw->cmd_buffer[0] = (runFl ? 0x36 : 0x37);
3015                 status = pvr2_send_request(hdw,hdw->cmd_buffer,1,NULL,0);
3016         } while (0); LOCK_GIVE(hdw->ctl_lock);
3017         if (!status) {
3018                 hdw->subsys_enabled_mask =
3019                         ((hdw->subsys_enabled_mask &
3020                           ~(1<<PVR2_SUBSYS_B_USBSTREAM_RUN)) |
3021                          (runFl ? (1<<PVR2_SUBSYS_B_USBSTREAM_RUN) : 0));
3022         }
3023         return status;
3024 }
3025
3026
3027 void pvr2_hdw_get_debug_info(const struct pvr2_hdw *hdw,
3028                              struct pvr2_hdw_debug_info *ptr)
3029 {
3030         ptr->big_lock_held = hdw->big_lock_held;
3031         ptr->ctl_lock_held = hdw->ctl_lock_held;
3032         ptr->flag_ok = hdw->flag_ok;
3033         ptr->flag_disconnected = hdw->flag_disconnected;
3034         ptr->flag_init_ok = hdw->flag_init_ok;
3035         ptr->flag_streaming_enabled = hdw->flag_streaming_enabled;
3036         ptr->subsys_flags = hdw->subsys_enabled_mask;
3037         ptr->cmd_debug_state = hdw->cmd_debug_state;
3038         ptr->cmd_code = hdw->cmd_debug_code;
3039         ptr->cmd_debug_write_len = hdw->cmd_debug_write_len;
3040         ptr->cmd_debug_read_len = hdw->cmd_debug_read_len;
3041         ptr->cmd_debug_timeout = hdw->ctl_timeout_flag;
3042         ptr->cmd_debug_write_pend = hdw->ctl_write_pend_flag;
3043         ptr->cmd_debug_read_pend = hdw->ctl_read_pend_flag;
3044         ptr->cmd_debug_rstatus = hdw->ctl_read_urb->status;
3045         ptr->cmd_debug_wstatus = hdw->ctl_read_urb->status;
3046 }
3047
3048
3049 int pvr2_hdw_gpio_get_dir(struct pvr2_hdw *hdw,u32 *dp)
3050 {
3051         return pvr2_read_register(hdw,PVR2_GPIO_DIR,dp);
3052 }
3053
3054
3055 int pvr2_hdw_gpio_get_out(struct pvr2_hdw *hdw,u32 *dp)
3056 {
3057         return pvr2_read_register(hdw,PVR2_GPIO_OUT,dp);
3058 }
3059
3060
3061 int pvr2_hdw_gpio_get_in(struct pvr2_hdw *hdw,u32 *dp)
3062 {
3063         return pvr2_read_register(hdw,PVR2_GPIO_IN,dp);
3064 }
3065
3066
3067 int pvr2_hdw_gpio_chg_dir(struct pvr2_hdw *hdw,u32 msk,u32 val)
3068 {
3069         u32 cval,nval;
3070         int ret;
3071         if (~msk) {
3072                 ret = pvr2_read_register(hdw,PVR2_GPIO_DIR,&cval);
3073                 if (ret) return ret;
3074                 nval = (cval & ~msk) | (val & msk);
3075                 pvr2_trace(PVR2_TRACE_GPIO,
3076                            "GPIO direction changing 0x%x:0x%x"
3077                            " from 0x%x to 0x%x",
3078                            msk,val,cval,nval);
3079         } else {
3080                 nval = val;
3081                 pvr2_trace(PVR2_TRACE_GPIO,
3082                            "GPIO direction changing to 0x%x",nval);
3083         }
3084         return pvr2_write_register(hdw,PVR2_GPIO_DIR,nval);
3085 }
3086
3087
3088 int pvr2_hdw_gpio_chg_out(struct pvr2_hdw *hdw,u32 msk,u32 val)
3089 {
3090         u32 cval,nval;
3091         int ret;
3092         if (~msk) {
3093                 ret = pvr2_read_register(hdw,PVR2_GPIO_OUT,&cval);
3094                 if (ret) return ret;
3095                 nval = (cval & ~msk) | (val & msk);
3096                 pvr2_trace(PVR2_TRACE_GPIO,
3097                            "GPIO output changing 0x%x:0x%x from 0x%x to 0x%x",
3098                            msk,val,cval,nval);
3099         } else {
3100                 nval = val;
3101                 pvr2_trace(PVR2_TRACE_GPIO,
3102                            "GPIO output changing to 0x%x",nval);
3103         }
3104         return pvr2_write_register(hdw,PVR2_GPIO_OUT,nval);
3105 }
3106
3107
3108 /* Find I2C address of eeprom */
3109 static int pvr2_hdw_get_eeprom_addr(struct pvr2_hdw *hdw)
3110 {
3111         int result;
3112         LOCK_TAKE(hdw->ctl_lock); do {
3113                 hdw->cmd_buffer[0] = 0xeb;
3114                 result = pvr2_send_request(hdw,
3115                                            hdw->cmd_buffer,1,
3116                                            hdw->cmd_buffer,1);
3117                 if (result < 0) break;
3118                 result = hdw->cmd_buffer[0];
3119         } while(0); LOCK_GIVE(hdw->ctl_lock);
3120         return result;
3121 }
3122
3123
3124 /*
3125   Stuff for Emacs to see, in order to encourage consistent editing style:
3126   *** Local Variables: ***
3127   *** mode: c ***
3128   *** fill-column: 75 ***
3129   *** tab-width: 8 ***
3130   *** c-basic-offset: 8 ***
3131   *** End: ***
3132   */