drivers/media/video/pvrusb2/pvrusb2-hdw.c

   1 /*
   2  *
   3  *  $Id$
   4  *
   5  *  Copyright (C) 2005 Mike Isely <isely@pobox.com>
   6  *
   7  *  This program is free software; you can redistribute it and/or modify
   8  *  it under the terms of the GNU General Public License as published by
   9  *  the Free Software Foundation; either version 2 of the License
  10  *
  11  *  This program is distributed in the hope that it will be useful,
  12  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  *  GNU General Public License for more details.
  15  *
  16  *  You should have received a copy of the GNU General Public License
  17  *  along with this program; if not, write to the Free Software
  18  *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  19  *
  20  */
  21
  22 #include <linux/errno.h>
  23 #include <linux/string.h>
  24 #include <linux/slab.h>
  25 #include <linux/firmware.h>
  26 #include <linux/videodev2.h>
  27 #include <asm/semaphore.h>
  28 #include "pvrusb2.h"
  29 #include "pvrusb2-std.h"
  30 #include "pvrusb2-util.h"
  31 #include "pvrusb2-hdw.h"
  32 #include "pvrusb2-i2c-core.h"
  33 #include "pvrusb2-tuner.h"
  34 #include "pvrusb2-eeprom.h"
  35 #include "pvrusb2-hdw-internal.h"
  36 #include "pvrusb2-encoder.h"
  37 #include "pvrusb2-debug.h"
  38
  39 struct usb_device_id pvr2_device_table[] = {
  40         [PVR2_HDW_TYPE_29XXX] = { USB_DEVICE(0x2040, 0x2900) },
  41         [PVR2_HDW_TYPE_24XXX] = { USB_DEVICE(0x2040, 0x2400) },
  42         { }
  43 };
  44
  45 MODULE_DEVICE_TABLE(usb, pvr2_device_table);
  46
  47 static const char *pvr2_device_names[] = {
  48         [PVR2_HDW_TYPE_29XXX] = "WinTV PVR USB2 Model Category 29xxxx",
  49         [PVR2_HDW_TYPE_24XXX] = "WinTV PVR USB2 Model Category 24xxxx",
  50 };
  51
  52 struct pvr2_string_table {
  53         const char **lst;
  54         unsigned int cnt;
  55 };
  56
  57 // Names of other client modules to request for 24xxx model hardware
  58 static const char *pvr2_client_24xxx[] = {
  59         "cx25840",
  60         "tuner",
  61         "wm8775",
  62 };
  63
  64 // Names of other client modules to request for 29xxx model hardware
  65 static const char *pvr2_client_29xxx[] = {
  66         "msp3400",
  67         "saa7115",
  68         "tuner",
  69 };
  70
  71 static struct pvr2_string_table pvr2_client_lists[] = {
  72         [PVR2_HDW_TYPE_29XXX] = {
  73                 pvr2_client_29xxx,
  74                 sizeof(pvr2_client_29xxx)/sizeof(pvr2_client_29xxx[0]),
  75         },
  76         [PVR2_HDW_TYPE_24XXX] = {
  77                 pvr2_client_24xxx,
  78                 sizeof(pvr2_client_24xxx)/sizeof(pvr2_client_24xxx[0]),
  79         },
  80 };
  81
  82 static struct pvr2_hdw *unit_pointers[PVR_NUM] = {[ 0 ... PVR_NUM-1 ] = NULL};
  83 static DECLARE_MUTEX(pvr2_unit_sem);
  84
  85 static int ctlchg = 0;
  86 static int initusbreset = 1;
  87 static int procreload = 0;
  88 static int tuner[PVR_NUM] = { [0 ... PVR_NUM-1] = -1 };
  89 static int tolerance[PVR_NUM] = { [0 ... PVR_NUM-1] = 0 };
  90 static int video_std[PVR_NUM] = { [0 ... PVR_NUM-1] = 0 };
  91 static int init_pause_msec = 0;
  92
  93 module_param(ctlchg, int, S_IRUGO|S_IWUSR);
  94 MODULE_PARM_DESC(ctlchg, "0=optimize ctl change 1=always accept new ctl value");
  95 module_param(init_pause_msec, int, S_IRUGO|S_IWUSR);
  96 MODULE_PARM_DESC(init_pause_msec, "hardware initialization settling delay");
  97 module_param(initusbreset, int, S_IRUGO|S_IWUSR);
  98 MODULE_PARM_DESC(initusbreset, "Do USB reset device on probe");
  99 module_param(procreload, int, S_IRUGO|S_IWUSR);
 100 MODULE_PARM_DESC(procreload,
 101                  "Attempt init failure recovery with firmware reload");
 102 module_param_array(tuner,    int, NULL, 0444);
 103 MODULE_PARM_DESC(tuner,"specify installed tuner type");
 104 module_param_array(video_std,    int, NULL, 0444);
 105 MODULE_PARM_DESC(video_std,"specify initial video standard");
 106 module_param_array(tolerance,    int, NULL, 0444);
 107 MODULE_PARM_DESC(tolerance,"specify stream error tolerance");
 108
 109 #define PVR2_CTL_WRITE_ENDPOINT  0x01
 110 #define PVR2_CTL_READ_ENDPOINT   0x81
 111
 112 #define PVR2_GPIO_IN 0x9008
 113 #define PVR2_GPIO_OUT 0x900c
 114 #define PVR2_GPIO_DIR 0x9020
 115
 116 #define trace_firmware(...) pvr2_trace(PVR2_TRACE_FIRMWARE,__VA_ARGS__)
 117
 118 #define PVR2_FIRMWARE_ENDPOINT   0x02
 119
 120 /* size of a firmware chunk */
 121 #define FIRMWARE_CHUNK_SIZE 0x2000
 122
 123 /* Define the list of additional controls we'll dynamically construct based
 124    on query of the cx2341x module. */
 125 struct pvr2_mpeg_ids {
 126         const char *strid;
 127         int id;
 128 };
 129 static const struct pvr2_mpeg_ids mpeg_ids[] = {
 130         {
 131                 .strid = "audio_layer",
 132                 .id = V4L2_CID_MPEG_AUDIO_ENCODING,
 133         },{
 134                 .strid = "audio_bitrate",
 135                 .id = V4L2_CID_MPEG_AUDIO_L2_BITRATE,
 136         },{
 137                 /* Already using audio_mode elsewhere :-( */
 138                 .strid = "mpeg_audio_mode",
 139                 .id = V4L2_CID_MPEG_AUDIO_MODE,
 140         },{
 141                 .strid = "mpeg_audio_mode_extension",
 142                 .id = V4L2_CID_MPEG_AUDIO_MODE_EXTENSION,
 143         },{
 144                 .strid = "audio_emphasis",
 145                 .id = V4L2_CID_MPEG_AUDIO_EMPHASIS,
 146         },{
 147                 .strid = "audio_crc",
 148                 .id = V4L2_CID_MPEG_AUDIO_CRC,
 149         },{
 150                 .strid = "video_aspect",
 151                 .id = V4L2_CID_MPEG_VIDEO_ASPECT,
 152         },{
 153                 .strid = "video_b_frames",
 154                 .id = V4L2_CID_MPEG_VIDEO_B_FRAMES,
 155         },{
 156                 .strid = "video_gop_size",
 157                 .id = V4L2_CID_MPEG_VIDEO_GOP_SIZE,
 158         },{
 159                 .strid = "video_gop_closure",
 160                 .id = V4L2_CID_MPEG_VIDEO_GOP_CLOSURE,
 161         },{
 162                 .strid = "video_pulldown",
 163                 .id = V4L2_CID_MPEG_VIDEO_PULLDOWN,
 164         },{
 165                 .strid = "video_bitrate_mode",
 166                 .id = V4L2_CID_MPEG_VIDEO_BITRATE_MODE,
 167         },{
 168                 .strid = "video_bitrate",
 169                 .id = V4L2_CID_MPEG_VIDEO_BITRATE,
 170         },{
 171                 .strid = "video_bitrate_peak",
 172                 .id = V4L2_CID_MPEG_VIDEO_BITRATE_PEAK,
 173         },{
 174                 .strid = "video_temporal_decimation",
 175                 .id = V4L2_CID_MPEG_VIDEO_TEMPORAL_DECIMATION,
 176         },{
 177                 .strid = "stream_type",
 178                 .id = V4L2_CID_MPEG_STREAM_TYPE,
 179         },{
 180                 .strid = "video_spatial_filter_mode",
 181                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER_MODE,
 182         },{
 183                 .strid = "video_spatial_filter",
 184                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER,
 185         },{
 186                 .strid = "video_luma_spatial_filter_type",
 187                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_SPATIAL_FILTER_TYPE,
 188         },{
 189                 .strid = "video_chroma_spatial_filter_type",
 190                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_SPATIAL_FILTER_TYPE,
 191         },{
 192                 .strid = "video_temporal_filter_mode",
 193                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER_MODE,
 194         },{
 195                 .strid = "video_temporal_filter",
 196                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER,
 197         },{
 198                 .strid = "video_median_filter_type",
 199                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_MEDIAN_FILTER_TYPE,
 200         },{
 201                 .strid = "video_luma_median_filter_top",
 202                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_TOP,
 203         },{
 204                 .strid = "video_luma_median_filter_bottom",
 205                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_BOTTOM,
 206         },{
 207                 .strid = "video_chroma_median_filter_top",
 208                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_TOP,
 209         },{
 210                 .strid = "video_chroma_median_filter_bottom",
 211                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_BOTTOM,
 212         }
 213 };
 214 #define MPEGDEF_COUNT (sizeof(mpeg_ids)/sizeof(mpeg_ids[0]))
 215
 216
 217 static const char *control_values_srate[] = {
 218         [V4L2_MPEG_AUDIO_SAMPLING_FREQ_44100]   = "44.1 kHz",
 219         [V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000]   = "48 kHz",
 220         [V4L2_MPEG_AUDIO_SAMPLING_FREQ_32000]   = "32 kHz",
 221 };
 222
 223
 224
 225 static const char *control_values_input[] = {
 226         [PVR2_CVAL_INPUT_TV]        = "television",  /*xawtv needs this name*/
 227         [PVR2_CVAL_INPUT_RADIO]     = "radio",
 228         [PVR2_CVAL_INPUT_SVIDEO]    = "s-video",
 229         [PVR2_CVAL_INPUT_COMPOSITE] = "composite",
 230 };
 231
 232
 233 static const char *control_values_audiomode[] = {
 234         [V4L2_TUNER_MODE_MONO]   = "Mono",
 235         [V4L2_TUNER_MODE_STEREO] = "Stereo",
 236         [V4L2_TUNER_MODE_LANG1]  = "Lang1",
 237         [V4L2_TUNER_MODE_LANG2]  = "Lang2",
 238         [V4L2_TUNER_MODE_LANG1_LANG2] = "Lang1+Lang2",
 239 };
 240
 241
 242 static const char *control_values_hsm[] = {
 243         [PVR2_CVAL_HSM_FAIL] = "Fail",
 244         [PVR2_CVAL_HSM_HIGH] = "High",
 245         [PVR2_CVAL_HSM_FULL] = "Full",
 246 };
 247
 248
 249 static const char *control_values_subsystem[] = {
 250         [PVR2_SUBSYS_B_ENC_FIRMWARE]  = "enc_firmware",
 251         [PVR2_SUBSYS_B_ENC_CFG] = "enc_config",
 252         [PVR2_SUBSYS_B_DIGITIZER_RUN] = "digitizer_run",
 253         [PVR2_SUBSYS_B_USBSTREAM_RUN] = "usbstream_run",
 254         [PVR2_SUBSYS_B_ENC_RUN] = "enc_run",
 255 };
 256
 257 static int pvr2_hdw_cmd_usbstream(struct pvr2_hdw *hdw,int runFl);
 258 static int pvr2_hdw_commit_ctl_internal(struct pvr2_hdw *hdw);
 259 static int pvr2_hdw_get_eeprom_addr(struct pvr2_hdw *hdw);
 260 static unsigned int pvr2_hdw_get_signal_status_internal(struct pvr2_hdw *hdw);
 261 static void pvr2_hdw_internal_find_stdenum(struct pvr2_hdw *hdw);
 262 static void pvr2_hdw_internal_set_std_avail(struct pvr2_hdw *hdw);
 263 static void pvr2_hdw_render_useless_unlocked(struct pvr2_hdw *hdw);
 264 static void pvr2_hdw_subsys_bit_chg_no_lock(struct pvr2_hdw *hdw,
 265                                             unsigned long msk,
 266                                             unsigned long val);
 267 static void pvr2_hdw_subsys_stream_bit_chg_no_lock(struct pvr2_hdw *hdw,
 268                                                    unsigned long msk,
 269                                                    unsigned long val);
 270 static int pvr2_send_request_ex(struct pvr2_hdw *hdw,
 271                                 unsigned int timeout,int probe_fl,
 272                                 void *write_data,unsigned int write_len,
 273                                 void *read_data,unsigned int read_len);
 274 static int pvr2_write_u16(struct pvr2_hdw *hdw, u16 data, int res);
 275 static int pvr2_write_u8(struct pvr2_hdw *hdw, u8 data, int res);
 276
 277 static int ctrl_channelfreq_get(struct pvr2_ctrl *cptr,int *vp)
 278 {
 279         struct pvr2_hdw *hdw = cptr->hdw;
 280         if ((hdw->freqProgSlot > 0) && (hdw->freqProgSlot <= FREQTABLE_SIZE)) {
 281                 *vp = hdw->freqTable[hdw->freqProgSlot-1];
 282         } else {
 283                 *vp = 0;
 284         }
 285         return 0;
 286 }
 287
 288 static int ctrl_channelfreq_set(struct pvr2_ctrl *cptr,int m,int v)
 289 {
 290         struct pvr2_hdw *hdw = cptr->hdw;
 291         if ((hdw->freqProgSlot > 0) && (hdw->freqProgSlot <= FREQTABLE_SIZE)) {
 292                 hdw->freqTable[hdw->freqProgSlot-1] = v;
 293         }
 294         return 0;
 295 }
 296
 297 static int ctrl_channelprog_get(struct pvr2_ctrl *cptr,int *vp)
 298 {
 299         *vp = cptr->hdw->freqProgSlot;
 300         return 0;
 301 }
 302
 303 static int ctrl_channelprog_set(struct pvr2_ctrl *cptr,int m,int v)
 304 {
 305         struct pvr2_hdw *hdw = cptr->hdw;
 306         if ((v >= 0) && (v <= FREQTABLE_SIZE)) {
 307                 hdw->freqProgSlot = v;
 308         }
 309         return 0;
 310 }
 311
 312 static int ctrl_channel_get(struct pvr2_ctrl *cptr,int *vp)
 313 {
 314         *vp = cptr->hdw->freqSlot;
 315         return 0;
 316 }
 317
 318 static int ctrl_channel_set(struct pvr2_ctrl *cptr,int m,int v)
 319 {
 320         unsigned freq = 0;
 321         struct pvr2_hdw *hdw = cptr->hdw;
 322         hdw->freqSlot = v;
 323         if ((hdw->freqSlot > 0) && (hdw->freqSlot <= FREQTABLE_SIZE)) {
 324                 freq = hdw->freqTable[hdw->freqSlot-1];
 325         }
 326         if (freq && (freq != hdw->freqVal)) {
 327                 hdw->freqVal = freq;
 328                 hdw->freqDirty = !0;
 329         }
 330         return 0;
 331 }
 332
 333 static int ctrl_freq_get(struct pvr2_ctrl *cptr,int *vp)
 334 {
 335         *vp = cptr->hdw->freqVal;
 336         return 0;
 337 }
 338
 339 static int ctrl_freq_is_dirty(struct pvr2_ctrl *cptr)
 340 {
 341         return cptr->hdw->freqDirty != 0;
 342 }
 343
 344 static void ctrl_freq_clear_dirty(struct pvr2_ctrl *cptr)
 345 {
 346         cptr->hdw->freqDirty = 0;
 347 }
 348
 349 static int ctrl_freq_set(struct pvr2_ctrl *cptr,int m,int v)
 350 {
 351         struct pvr2_hdw *hdw = cptr->hdw;
 352         hdw->freqVal = v;
 353         hdw->freqDirty = !0;
 354         hdw->freqSlot = 0;
 355         return 0;
 356 }
 357
 358 static int ctrl_hres_max_get(struct pvr2_ctrl *cptr,int *vp)
 359 {
 360         /* If we're dealing with a 24xxx device, force the horizontal
 361            maximum to be 720 no matter what, since we can't get the device
 362            to work properly with any other value.  Otherwise just return
 363            the normal value. */
 364         *vp = cptr->info->def.type_int.max_value;
 365         if (cptr->hdw->hdw_type == PVR2_HDW_TYPE_24XXX) *vp = 720;
 366         return 0;
 367 }
 368
 369 static int ctrl_hres_min_get(struct pvr2_ctrl *cptr,int *vp)
 370 {
 371         /* If we're dealing with a 24xxx device, force the horizontal
 372            minimum to be 720 no matter what, since we can't get the device
 373            to work properly with any other value.  Otherwise just return
 374            the normal value. */
 375         *vp = cptr->info->def.type_int.min_value;
 376         if (cptr->hdw->hdw_type == PVR2_HDW_TYPE_24XXX) *vp = 720;
 377         return 0;
 378 }
 379
 380 static int ctrl_vres_max_get(struct pvr2_ctrl *cptr,int *vp)
 381 {
 382         /* Actual maximum depends on the video standard in effect. */
 383         if (cptr->hdw->std_mask_cur & V4L2_STD_525_60) {
 384                 *vp = 480;
 385         } else {
 386                 *vp = 576;
 387         }
 388         return 0;
 389 }
 390
 391 static int ctrl_vres_min_get(struct pvr2_ctrl *cptr,int *vp)
 392 {
 393         /* Actual minimum depends on device type. */
 394         if (cptr->hdw->hdw_type == PVR2_HDW_TYPE_24XXX) {
 395                 *vp = 75;
 396         } else {
 397                 *vp = 17;
 398         }
 399         return 0;
 400 }
 401
 402 static int ctrl_cx2341x_is_dirty(struct pvr2_ctrl *cptr)
 403 {
 404         return cptr->hdw->enc_stale != 0;
 405 }
 406
 407 static void ctrl_cx2341x_clear_dirty(struct pvr2_ctrl *cptr)
 408 {
 409         cptr->hdw->enc_stale = 0;
 410 }
 411
 412 static int ctrl_cx2341x_get(struct pvr2_ctrl *cptr,int *vp)
 413 {
 414         int ret;
 415         struct v4l2_ext_controls cs;
 416         struct v4l2_ext_control c1;
 417         memset(&cs,0,sizeof(cs));
 418         memset(&c1,0,sizeof(c1));
 419         cs.controls = &c1;
 420         cs.count = 1;
 421         c1.id = cptr->info->v4l_id;
 422         ret = cx2341x_ext_ctrls(&cptr->hdw->enc_ctl_state,&cs,
 423                                 VIDIOC_G_EXT_CTRLS);
 424         if (ret) return ret;
 425         *vp = c1.value;
 426         return 0;
 427 }
 428
 429 static int ctrl_cx2341x_set(struct pvr2_ctrl *cptr,int m,int v)
 430 {
 431         int ret;
 432         struct v4l2_ext_controls cs;
 433         struct v4l2_ext_control c1;
 434         memset(&cs,0,sizeof(cs));
 435         memset(&c1,0,sizeof(c1));
 436         cs.controls = &c1;
 437         cs.count = 1;
 438         c1.id = cptr->info->v4l_id;
 439         c1.value = v;
 440         ret = cx2341x_ext_ctrls(&cptr->hdw->enc_ctl_state,&cs,
 441                                 VIDIOC_S_EXT_CTRLS);
 442         if (ret) return ret;
 443         cptr->hdw->enc_stale = !0;
 444         return 0;
 445 }
 446
 447 static unsigned int ctrl_cx2341x_getv4lflags(struct pvr2_ctrl *cptr)
 448 {
 449         struct v4l2_queryctrl qctrl;
 450         struct pvr2_ctl_info *info;
 451         qctrl.id = cptr->info->v4l_id;
 452         cx2341x_ctrl_query(&cptr->hdw->enc_ctl_state,&qctrl);
 453         /* Strip out the const so we can adjust a function pointer.  It's
 454            OK to do this here because we know this is a dynamically created
 455            control, so the underlying storage for the info pointer is (a)
 456            private to us, and (b) not in read-only storage.  Either we do
 457            this or we significantly complicate the underlying control
 458            implementation. */
 459         info = (struct pvr2_ctl_info *)(cptr->info);
 460         if (qctrl.flags & V4L2_CTRL_FLAG_READ_ONLY) {
 461                 if (info->set_value) {
 462                         info->set_value = NULL;
 463                 }
 464         } else {
 465                 if (!(info->set_value)) {
 466                         info->set_value = ctrl_cx2341x_set;
 467                 }
 468         }
 469         return qctrl.flags;
 470 }
 471
 472 static int ctrl_streamingenabled_get(struct pvr2_ctrl *cptr,int *vp)
 473 {
 474         *vp = cptr->hdw->flag_streaming_enabled;
 475         return 0;
 476 }
 477
 478 static int ctrl_hsm_get(struct pvr2_ctrl *cptr,int *vp)
 479 {
 480         int result = pvr2_hdw_is_hsm(cptr->hdw);
 481         *vp = PVR2_CVAL_HSM_FULL;
 482         if (result < 0) *vp = PVR2_CVAL_HSM_FAIL;
 483         if (result) *vp = PVR2_CVAL_HSM_HIGH;
 484         return 0;
 485 }
 486
 487 static int ctrl_stdavail_get(struct pvr2_ctrl *cptr,int *vp)
 488 {
 489         *vp = cptr->hdw->std_mask_avail;
 490         return 0;
 491 }
 492
 493 static int ctrl_stdavail_set(struct pvr2_ctrl *cptr,int m,int v)
 494 {
 495         struct pvr2_hdw *hdw = cptr->hdw;
 496         v4l2_std_id ns;
 497         ns = hdw->std_mask_avail;
 498         ns = (ns & ~m) | (v & m);
 499         if (ns == hdw->std_mask_avail) return 0;
 500         hdw->std_mask_avail = ns;
 501         pvr2_hdw_internal_set_std_avail(hdw);
 502         pvr2_hdw_internal_find_stdenum(hdw);
 503         return 0;
 504 }
 505
 506 static int ctrl_std_val_to_sym(struct pvr2_ctrl *cptr,int msk,int val,
 507                                char *bufPtr,unsigned int bufSize,
 508                                unsigned int *len)
 509 {
 510         *len = pvr2_std_id_to_str(bufPtr,bufSize,msk & val);
 511         return 0;
 512 }
 513
 514 static int ctrl_std_sym_to_val(struct pvr2_ctrl *cptr,
 515                                const char *bufPtr,unsigned int bufSize,
 516                                int *mskp,int *valp)
 517 {
 518         int ret;
 519         v4l2_std_id id;
 520         ret = pvr2_std_str_to_id(&id,bufPtr,bufSize);
 521         if (ret < 0) return ret;
 522         if (mskp) *mskp = id;
 523         if (valp) *valp = id;
 524         return 0;
 525 }
 526
 527 static int ctrl_stdcur_get(struct pvr2_ctrl *cptr,int *vp)
 528 {
 529         *vp = cptr->hdw->std_mask_cur;
 530         return 0;
 531 }
 532
 533 static int ctrl_stdcur_set(struct pvr2_ctrl *cptr,int m,int v)
 534 {
 535         struct pvr2_hdw *hdw = cptr->hdw;
 536         v4l2_std_id ns;
 537         ns = hdw->std_mask_cur;
 538         ns = (ns & ~m) | (v & m);
 539         if (ns == hdw->std_mask_cur) return 0;
 540         hdw->std_mask_cur = ns;
 541         hdw->std_dirty = !0;
 542         pvr2_hdw_internal_find_stdenum(hdw);
 543         return 0;
 544 }
 545
 546 static int ctrl_stdcur_is_dirty(struct pvr2_ctrl *cptr)
 547 {
 548         return cptr->hdw->std_dirty != 0;
 549 }
 550
 551 static void ctrl_stdcur_clear_dirty(struct pvr2_ctrl *cptr)
 552 {
 553         cptr->hdw->std_dirty = 0;
 554 }
 555
 556 static int ctrl_signal_get(struct pvr2_ctrl *cptr,int *vp)
 557 {
 558         *vp = ((pvr2_hdw_get_signal_status_internal(cptr->hdw) &
 559                 PVR2_SIGNAL_OK) ? 1 : 0);
 560         return 0;
 561 }
 562
 563 static int ctrl_subsys_get(struct pvr2_ctrl *cptr,int *vp)
 564 {
 565         *vp = cptr->hdw->subsys_enabled_mask;
 566         return 0;
 567 }
 568
 569 static int ctrl_subsys_set(struct pvr2_ctrl *cptr,int m,int v)
 570 {
 571         pvr2_hdw_subsys_bit_chg_no_lock(cptr->hdw,m,v);
 572         return 0;
 573 }
 574
 575 static int ctrl_subsys_stream_get(struct pvr2_ctrl *cptr,int *vp)
 576 {
 577         *vp = cptr->hdw->subsys_stream_mask;
 578         return 0;
 579 }
 580
 581 static int ctrl_subsys_stream_set(struct pvr2_ctrl *cptr,int m,int v)
 582 {
 583         pvr2_hdw_subsys_stream_bit_chg_no_lock(cptr->hdw,m,v);
 584         return 0;
 585 }
 586
 587 static int ctrl_stdenumcur_set(struct pvr2_ctrl *cptr,int m,int v)
 588 {
 589         struct pvr2_hdw *hdw = cptr->hdw;
 590         if (v < 0) return -EINVAL;
 591         if (v > hdw->std_enum_cnt) return -EINVAL;
 592         hdw->std_enum_cur = v;
 593         if (!v) return 0;
 594         v--;
 595         if (hdw->std_mask_cur == hdw->std_defs[v].id) return 0;
 596         hdw->std_mask_cur = hdw->std_defs[v].id;
 597         hdw->std_dirty = !0;
 598         return 0;
 599 }
 600
 601
 602 static int ctrl_stdenumcur_get(struct pvr2_ctrl *cptr,int *vp)
 603 {
 604         *vp = cptr->hdw->std_enum_cur;
 605         return 0;
 606 }
 607
 608
 609 static int ctrl_stdenumcur_is_dirty(struct pvr2_ctrl *cptr)
 610 {
 611         return cptr->hdw->std_dirty != 0;
 612 }
 613
 614
 615 static void ctrl_stdenumcur_clear_dirty(struct pvr2_ctrl *cptr)
 616 {
 617         cptr->hdw->std_dirty = 0;
 618 }
 619
 620
 621 #define DEFINT(vmin,vmax) \
 622         .type = pvr2_ctl_int, \
 623         .def.type_int.min_value = vmin, \
 624         .def.type_int.max_value = vmax
 625
 626 #define DEFENUM(tab) \
 627         .type = pvr2_ctl_enum, \
 628         .def.type_enum.count = (sizeof(tab)/sizeof((tab)[0])), \
 629         .def.type_enum.value_names = tab
 630
 631 #define DEFBOOL \
 632         .type = pvr2_ctl_bool
 633
 634 #define DEFMASK(msk,tab) \
 635         .type = pvr2_ctl_bitmask, \
 636         .def.type_bitmask.valid_bits = msk, \
 637         .def.type_bitmask.bit_names = tab
 638
 639 #define DEFREF(vname) \
 640         .set_value = ctrl_set_##vname, \
 641         .get_value = ctrl_get_##vname, \
 642         .is_dirty = ctrl_isdirty_##vname, \
 643         .clear_dirty = ctrl_cleardirty_##vname
 644
 645
 646 #define VCREATE_FUNCS(vname) \
 647 static int ctrl_get_##vname(struct pvr2_ctrl *cptr,int *vp) \
 648 {*vp = cptr->hdw->vname##_val; return 0;} \
 649 static int ctrl_set_##vname(struct pvr2_ctrl *cptr,int m,int v) \
 650 {cptr->hdw->vname##_val = v; cptr->hdw->vname##_dirty = !0; return 0;} \
 651 static int ctrl_isdirty_##vname(struct pvr2_ctrl *cptr) \
 652 {return cptr->hdw->vname##_dirty != 0;} \
 653 static void ctrl_cleardirty_##vname(struct pvr2_ctrl *cptr) \
 654 {cptr->hdw->vname##_dirty = 0;}
 655
 656 VCREATE_FUNCS(brightness)
 657 VCREATE_FUNCS(contrast)
 658 VCREATE_FUNCS(saturation)
 659 VCREATE_FUNCS(hue)
 660 VCREATE_FUNCS(volume)
 661 VCREATE_FUNCS(balance)
 662 VCREATE_FUNCS(bass)
 663 VCREATE_FUNCS(treble)
 664 VCREATE_FUNCS(mute)
 665 VCREATE_FUNCS(input)
 666 VCREATE_FUNCS(audiomode)
 667 VCREATE_FUNCS(res_hor)
 668 VCREATE_FUNCS(res_ver)
 669 VCREATE_FUNCS(srate)
 670
 671 #define MIN_FREQ 55250000L
 672 #define MAX_FREQ 850000000L
 673
 674 /* Table definition of all controls which can be manipulated */
 675 static const struct pvr2_ctl_info control_defs[] = {
 676         {
 677                 .v4l_id = V4L2_CID_BRIGHTNESS,
 678                 .desc = "Brightness",
 679                 .name = "brightness",
 680                 .default_value = 128,
 681                 DEFREF(brightness),
 682                 DEFINT(0,255),
 683         },{
 684                 .v4l_id = V4L2_CID_CONTRAST,
 685                 .desc = "Contrast",
 686                 .name = "contrast",
 687                 .default_value = 68,
 688                 DEFREF(contrast),
 689                 DEFINT(0,127),
 690         },{
 691                 .v4l_id = V4L2_CID_SATURATION,
 692                 .desc = "Saturation",
 693                 .name = "saturation",
 694                 .default_value = 64,
 695                 DEFREF(saturation),
 696                 DEFINT(0,127),
 697         },{
 698                 .v4l_id = V4L2_CID_HUE,
 699                 .desc = "Hue",
 700                 .name = "hue",
 701                 .default_value = 0,
 702                 DEFREF(hue),
 703                 DEFINT(-128,127),
 704         },{
 705                 .v4l_id = V4L2_CID_AUDIO_VOLUME,
 706                 .desc = "Volume",
 707                 .name = "volume",
 708                 .default_value = 65535,
 709                 DEFREF(volume),
 710                 DEFINT(0,65535),
 711         },{
 712                 .v4l_id = V4L2_CID_AUDIO_BALANCE,
 713                 .desc = "Balance",
 714                 .name = "balance",
 715                 .default_value = 0,
 716                 DEFREF(balance),
 717                 DEFINT(-32768,32767),
 718         },{
 719                 .v4l_id = V4L2_CID_AUDIO_BASS,
 720                 .desc = "Bass",
 721                 .name = "bass",
 722                 .default_value = 0,
 723                 DEFREF(bass),
 724                 DEFINT(-32768,32767),
 725         },{
 726                 .v4l_id = V4L2_CID_AUDIO_TREBLE,
 727                 .desc = "Treble",
 728                 .name = "treble",
 729                 .default_value = 0,
 730                 DEFREF(treble),
 731                 DEFINT(-32768,32767),
 732         },{
 733                 .v4l_id = V4L2_CID_AUDIO_MUTE,
 734                 .desc = "Mute",
 735                 .name = "mute",
 736                 .default_value = 0,
 737                 DEFREF(mute),
 738                 DEFBOOL,
 739         },{
 740                 .desc = "Video Source",
 741                 .name = "input",
 742                 .internal_id = PVR2_CID_INPUT,
 743                 .default_value = PVR2_CVAL_INPUT_TV,
 744                 DEFREF(input),
 745                 DEFENUM(control_values_input),
 746         },{
 747                 .desc = "Audio Mode",
 748                 .name = "audio_mode",
 749                 .internal_id = PVR2_CID_AUDIOMODE,
 750                 .default_value = V4L2_TUNER_MODE_STEREO,
 751                 DEFREF(audiomode),
 752                 DEFENUM(control_values_audiomode),
 753         },{
 754                 .desc = "Horizontal capture resolution",
 755                 .name = "resolution_hor",
 756                 .internal_id = PVR2_CID_HRES,
 757                 .default_value = 720,
 758                 DEFREF(res_hor),
 759                 DEFINT(19,720),
 760                 /* Hook in check for clamp on horizontal resolution in
 761                    order to avoid unsolved problem involving cx25840. */
 762                 .get_max_value = ctrl_hres_max_get,
 763                 .get_min_value = ctrl_hres_min_get,
 764         },{
 765                 .desc = "Vertical capture resolution",
 766                 .name = "resolution_ver",
 767                 .internal_id = PVR2_CID_VRES,
 768                 .default_value = 480,
 769                 DEFREF(res_ver),
 770                 DEFINT(17,576),
 771                 /* Hook in check for video standard and adjust maximum
 772                    depending on the standard. */
 773                 .get_max_value = ctrl_vres_max_get,
 774                 .get_min_value = ctrl_vres_min_get,
 775         },{
 776                 .v4l_id = V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ,
 777                 .default_value = V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000,
 778                 .desc = "Audio Sampling Frequency",
 779                 .name = "srate",
 780                 DEFREF(srate),
 781                 DEFENUM(control_values_srate),
 782         },{
 783                 .desc = "Tuner Frequency (Hz)",
 784                 .name = "frequency",
 785                 .internal_id = PVR2_CID_FREQUENCY,
 786                 .default_value = 175250000L,
 787                 .set_value = ctrl_freq_set,
 788                 .get_value = ctrl_freq_get,
 789                 .is_dirty = ctrl_freq_is_dirty,
 790                 .clear_dirty = ctrl_freq_clear_dirty,
 791                 DEFINT(MIN_FREQ,MAX_FREQ),
 792         },{
 793                 .desc = "Channel",
 794                 .name = "channel",
 795                 .set_value = ctrl_channel_set,
 796                 .get_value = ctrl_channel_get,
 797                 DEFINT(0,FREQTABLE_SIZE),
 798         },{
 799                 .desc = "Channel Program Frequency",
 800                 .name = "freq_table_value",
 801                 .set_value = ctrl_channelfreq_set,
 802                 .get_value = ctrl_channelfreq_get,
 803                 DEFINT(MIN_FREQ,MAX_FREQ),
 804         },{
 805                 .desc = "Channel Program ID",
 806                 .name = "freq_table_channel",
 807                 .set_value = ctrl_channelprog_set,
 808                 .get_value = ctrl_channelprog_get,
 809                 DEFINT(0,FREQTABLE_SIZE),
 810         },{
 811                 .desc = "Streaming Enabled",
 812                 .name = "streaming_enabled",
 813                 .get_value = ctrl_streamingenabled_get,
 814                 DEFBOOL,
 815         },{
 816                 .desc = "USB Speed",
 817                 .name = "usb_speed",
 818                 .get_value = ctrl_hsm_get,
 819                 DEFENUM(control_values_hsm),
 820         },{
 821                 .desc = "Signal Present",
 822                 .name = "signal_present",
 823                 .get_value = ctrl_signal_get,
 824                 DEFBOOL,
 825         },{
 826                 .desc = "Video Standards Available Mask",
 827                 .name = "video_standard_mask_available",
 828                 .internal_id = PVR2_CID_STDAVAIL,
 829                 .skip_init = !0,
 830                 .get_value = ctrl_stdavail_get,
 831                 .set_value = ctrl_stdavail_set,
 832                 .val_to_sym = ctrl_std_val_to_sym,
 833                 .sym_to_val = ctrl_std_sym_to_val,
 834                 .type = pvr2_ctl_bitmask,
 835         },{
 836                 .desc = "Video Standards In Use Mask",
 837                 .name = "video_standard_mask_active",
 838                 .internal_id = PVR2_CID_STDCUR,
 839                 .skip_init = !0,
 840                 .get_value = ctrl_stdcur_get,
 841                 .set_value = ctrl_stdcur_set,
 842                 .is_dirty = ctrl_stdcur_is_dirty,
 843                 .clear_dirty = ctrl_stdcur_clear_dirty,
 844                 .val_to_sym = ctrl_std_val_to_sym,
 845                 .sym_to_val = ctrl_std_sym_to_val,
 846                 .type = pvr2_ctl_bitmask,
 847         },{
 848                 .desc = "Subsystem enabled mask",
 849                 .name = "debug_subsys_mask",
 850                 .skip_init = !0,
 851                 .get_value = ctrl_subsys_get,
 852                 .set_value = ctrl_subsys_set,
 853                 DEFMASK(PVR2_SUBSYS_ALL,control_values_subsystem),
 854         },{
 855                 .desc = "Subsystem stream mask",
 856                 .name = "debug_subsys_stream_mask",
 857                 .skip_init = !0,
 858                 .get_value = ctrl_subsys_stream_get,
 859                 .set_value = ctrl_subsys_stream_set,
 860                 DEFMASK(PVR2_SUBSYS_ALL,control_values_subsystem),
 861         },{
 862                 .desc = "Video Standard Name",
 863                 .name = "video_standard",
 864                 .internal_id = PVR2_CID_STDENUM,
 865                 .skip_init = !0,
 866                 .get_value = ctrl_stdenumcur_get,
 867                 .set_value = ctrl_stdenumcur_set,
 868                 .is_dirty = ctrl_stdenumcur_is_dirty,
 869                 .clear_dirty = ctrl_stdenumcur_clear_dirty,
 870                 .type = pvr2_ctl_enum,
 871         }
 872 };
 873
 874 #define CTRLDEF_COUNT (sizeof(control_defs)/sizeof(control_defs[0]))
 875
 876
 877 const char *pvr2_config_get_name(enum pvr2_config cfg)
 878 {
 879         switch (cfg) {
 880         case pvr2_config_empty: return "empty";
 881         case pvr2_config_mpeg: return "mpeg";
 882         case pvr2_config_vbi: return "vbi";
 883         case pvr2_config_radio: return "radio";
 884         }
 885         return "<unknown>";
 886 }
 887
 888
 889 struct usb_device *pvr2_hdw_get_dev(struct pvr2_hdw *hdw)
 890 {
 891         return hdw->usb_dev;
 892 }
 893
 894
 895 unsigned long pvr2_hdw_get_sn(struct pvr2_hdw *hdw)
 896 {
 897         return hdw->serial_number;
 898 }
 899
 900 int pvr2_hdw_get_unit_number(struct pvr2_hdw *hdw)
 901 {
 902         return hdw->unit_number;
 903 }
 904
 905
 906 /* Attempt to locate one of the given set of files.  Messages are logged
 907    appropriate to what has been found.  The return value will be 0 or
 908    greater on success (it will be the index of the file name found) and
 909    fw_entry will be filled in.  Otherwise a negative error is returned on
 910    failure.  If the return value is -ENOENT then no viable firmware file
 911    could be located. */
 912 static int pvr2_locate_firmware(struct pvr2_hdw *hdw,
 913                                 const struct firmware **fw_entry,
 914                                 const char *fwtypename,
 915                                 unsigned int fwcount,
 916                                 const char *fwnames[])
 917 {
 918         unsigned int idx;
 919         int ret = -EINVAL;
 920         for (idx = 0; idx < fwcount; idx++) {
 921                 ret = request_firmware(fw_entry,
 922                                        fwnames[idx],
 923                                        &hdw->usb_dev->dev);
 924                 if (!ret) {
 925                         trace_firmware("Located %s firmware: %s;"
 926                                        " uploading...",
 927                                        fwtypename,
 928                                        fwnames[idx]);
 929                         return idx;
 930                 }
 931                 if (ret == -ENOENT) continue;
 932                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
 933                            "request_firmware fatal error with code=%d",ret);
 934                 return ret;
 935         }
 936         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
 937                    "***WARNING***"
 938                    " Device %s firmware"
 939                    " seems to be missing.",
 940                    fwtypename);
 941         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
 942                    "Did you install the pvrusb2 firmware files"
 943                    " in their proper location?");
 944         if (fwcount == 1) {
 945                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
 946                            "request_firmware unable to locate %s file %s",
 947                            fwtypename,fwnames[0]);
 948         } else {
 949                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
 950                            "request_firmware unable to locate"
 951                            " one of the following %s files:",
 952                            fwtypename);
 953                 for (idx = 0; idx < fwcount; idx++) {
 954                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
 955                                    "request_firmware: Failed to find %s",
 956                                    fwnames[idx]);
 957                 }
 958         }
 959         return ret;
 960 }
 961
 962
 963 /*
 964  * pvr2_upload_firmware1().
 965  *
 966  * Send the 8051 firmware to the device.  After the upload, arrange for
 967  * device to re-enumerate.
 968  *
 969  * NOTE : the pointer to the firmware data given by request_firmware()
 970  * is not suitable for an usb transaction.
 971  *
 972  */
 973 static int pvr2_upload_firmware1(struct pvr2_hdw *hdw)
 974 {
 975         const struct firmware *fw_entry = NULL;
 976         void  *fw_ptr;
 977         unsigned int pipe;
 978         int ret;
 979         u16 address;
 980         static const char *fw_files_29xxx[] = {
 981                 "v4l-pvrusb2-29xxx-01.fw",
 982         };
 983         static const char *fw_files_24xxx[] = {
 984                 "v4l-pvrusb2-24xxx-01.fw",
 985         };
 986         static const struct pvr2_string_table fw_file_defs[] = {
 987                 [PVR2_HDW_TYPE_29XXX] = {
 988                         fw_files_29xxx,
 989                         sizeof(fw_files_29xxx)/sizeof(fw_files_29xxx[0]),
 990                 },
 991                 [PVR2_HDW_TYPE_24XXX] = {
 992                         fw_files_24xxx,
 993                         sizeof(fw_files_24xxx)/sizeof(fw_files_24xxx[0]),
 994                 },
 995         };
 996         hdw->fw1_state = FW1_STATE_FAILED; // default result
 997
 998         trace_firmware("pvr2_upload_firmware1");
 999
1000         ret = pvr2_locate_firmware(hdw,&fw_entry,"fx2 controller",
1001                                    fw_file_defs[hdw->hdw_type].cnt,
1002                                    fw_file_defs[hdw->hdw_type].lst);
1003         if (ret < 0) {
1004                 if (ret == -ENOENT) hdw->fw1_state = FW1_STATE_MISSING;
1005                 return ret;
1006         }
1007
1008         usb_settoggle(hdw->usb_dev, 0 & 0xf, !(0 & USB_DIR_IN), 0);
1009         usb_clear_halt(hdw->usb_dev, usb_sndbulkpipe(hdw->usb_dev, 0 & 0x7f));
1010
1011         pipe = usb_sndctrlpipe(hdw->usb_dev, 0);
1012
1013         if (fw_entry->size != 0x2000){
1014                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,"wrong fx2 firmware size");
1015                 release_firmware(fw_entry);
1016                 return -ENOMEM;
1017         }
1018
1019         fw_ptr = kmalloc(0x800, GFP_KERNEL);
1020         if (fw_ptr == NULL){
1021                 release_firmware(fw_entry);
1022                 return -ENOMEM;
1023         }
1024
1025         /* We have to hold the CPU during firmware upload. */
1026         pvr2_hdw_cpureset_assert(hdw,1);
1027
1028         /* upload the firmware to address 0000-1fff in 2048 (=0x800) bytes
1029            chunk. */
1030
1031         ret = 0;
1032         for(address = 0; address < fw_entry->size; address += 0x800) {
1033                 memcpy(fw_ptr, fw_entry->data + address, 0x800);
1034                 ret += usb_control_msg(hdw->usb_dev, pipe, 0xa0, 0x40, address,
1035                                        0, fw_ptr, 0x800, HZ);
1036         }
1037
1038         trace_firmware("Upload done, releasing device's CPU");
1039
1040         /* Now release the CPU.  It will disconnect and reconnect later. */
1041         pvr2_hdw_cpureset_assert(hdw,0);
1042
1043         kfree(fw_ptr);
1044         release_firmware(fw_entry);
1045
1046         trace_firmware("Upload done (%d bytes sent)",ret);
1047
1048         /* We should have written 8192 bytes */
1049         if (ret == 8192) {
1050                 hdw->fw1_state = FW1_STATE_RELOAD;
1051                 return 0;
1052         }
1053
1054         return -EIO;
1055 }
1056
1057
1058 /*
1059  * pvr2_upload_firmware2()
1060  *
1061  * This uploads encoder firmware on endpoint 2.
1062  *
1063  */
1064
1065 int pvr2_upload_firmware2(struct pvr2_hdw *hdw)
1066 {
1067         const struct firmware *fw_entry = NULL;
1068         void  *fw_ptr;
1069         unsigned int pipe, fw_len, fw_done;
1070         int actual_length;
1071         int ret = 0;
1072         int fwidx;
1073         static const char *fw_files[] = {
1074                 CX2341X_FIRM_ENC_FILENAME,
1075         };
1076
1077         trace_firmware("pvr2_upload_firmware2");
1078
1079         ret = pvr2_locate_firmware(hdw,&fw_entry,"encoder",
1080                                    sizeof(fw_files)/sizeof(fw_files[0]),
1081                                    fw_files);
1082         if (ret < 0) return ret;
1083         fwidx = ret;
1084         ret = 0;
1085         /* Since we're about to completely reinitialize the encoder,
1086            invalidate our cached copy of its configuration state.  Next
1087            time we configure the encoder, then we'll fully configure it. */
1088         hdw->enc_cur_valid = 0;
1089
1090         /* First prepare firmware loading */
1091         ret |= pvr2_write_register(hdw, 0x0048, 0xffffffff); /*interrupt mask*/
1092         ret |= pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000088); /*gpio dir*/
1093         ret |= pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000008); /*gpio output state*/
1094         ret |= pvr2_hdw_cmd_deep_reset(hdw);
1095         ret |= pvr2_write_register(hdw, 0xa064, 0x00000000); /*APU command*/
1096         ret |= pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000408); /*gpio dir*/
1097         ret |= pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000008); /*gpio output state*/
1098         ret |= pvr2_write_register(hdw, 0x9058, 0xffffffed); /*VPU ctrl*/
1099         ret |= pvr2_write_register(hdw, 0x9054, 0xfffffffd); /*reset hw blocks*/
1100         ret |= pvr2_write_register(hdw, 0x07f8, 0x80000800); /*encoder SDRAM refresh*/
1101         ret |= pvr2_write_register(hdw, 0x07fc, 0x0000001a); /*encoder SDRAM pre-charge*/
1102         ret |= pvr2_write_register(hdw, 0x0700, 0x00000000); /*I2C clock*/
1103         ret |= pvr2_write_register(hdw, 0xaa00, 0x00000000); /*unknown*/
1104         ret |= pvr2_write_register(hdw, 0xaa04, 0x00057810); /*unknown*/
1105         ret |= pvr2_write_register(hdw, 0xaa10, 0x00148500); /*unknown*/
1106         ret |= pvr2_write_register(hdw, 0xaa18, 0x00840000); /*unknown*/
1107         ret |= pvr2_write_u8(hdw, 0x52, 0);
1108         ret |= pvr2_write_u16(hdw, 0x0600, 0);
1109
1110         if (ret) {
1111                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1112                            "firmware2 upload prep failed, ret=%d",ret);
1113                 release_firmware(fw_entry);
1114                 return ret;
1115         }
1116
1117         /* Now send firmware */
1118
1119         fw_len = fw_entry->size;
1120
1121         if (fw_len % FIRMWARE_CHUNK_SIZE) {
1122                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1123                            "size of %s firmware"
1124                            " must be a multiple of 8192B",
1125                            fw_files[fwidx]);
1126                 release_firmware(fw_entry);
1127                 return -1;
1128         }
1129
1130         fw_ptr = kmalloc(FIRMWARE_CHUNK_SIZE, GFP_KERNEL);
1131         if (fw_ptr == NULL){
1132                 release_firmware(fw_entry);
1133                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1134                            "failed to allocate memory for firmware2 upload");
1135                 return -ENOMEM;
1136         }
1137
1138         pipe = usb_sndbulkpipe(hdw->usb_dev, PVR2_FIRMWARE_ENDPOINT);
1139
1140         for (fw_done = 0 ; (fw_done < fw_len) && !ret ;
1141              fw_done += FIRMWARE_CHUNK_SIZE ) {
1142                 int i;
1143                 memcpy(fw_ptr, fw_entry->data + fw_done, FIRMWARE_CHUNK_SIZE);
1144                 /* Usbsnoop log  shows that we must swap bytes... */
1145                 for (i = 0; i < FIRMWARE_CHUNK_SIZE/4 ; i++)
1146                         ((u32 *)fw_ptr)[i] = ___swab32(((u32 *)fw_ptr)[i]);
1147
1148                 ret |= usb_bulk_msg(hdw->usb_dev, pipe, fw_ptr,
1149                                     FIRMWARE_CHUNK_SIZE,
1150                                     &actual_length, HZ);
1151                 ret |= (actual_length != FIRMWARE_CHUNK_SIZE);
1152         }
1153
1154         trace_firmware("upload of %s : %i / %i ",
1155                        fw_files[fwidx],fw_done,fw_len);
1156
1157         kfree(fw_ptr);
1158         release_firmware(fw_entry);
1159
1160         if (ret) {
1161                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1162                            "firmware2 upload transfer failure");
1163                 return ret;
1164         }
1165
1166         /* Finish upload */
1167
1168         ret |= pvr2_write_register(hdw, 0x9054, 0xffffffff); /*reset hw blocks*/
1169         ret |= pvr2_write_register(hdw, 0x9058, 0xffffffe8); /*VPU ctrl*/
1170         ret |= pvr2_write_u16(hdw, 0x0600, 0);
1171
1172         if (ret) {
1173                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1174                            "firmware2 upload post-proc failure");
1175         } else {
1176                 hdw->subsys_enabled_mask |= (1<<PVR2_SUBSYS_B_ENC_FIRMWARE);
1177         }
1178         return ret;
1179 }
1180
1181
1182 #define FIRMWARE_RECOVERY_BITS \
1183         ((1<<PVR2_SUBSYS_B_ENC_CFG) | \
1184          (1<<PVR2_SUBSYS_B_ENC_RUN) | \
1185          (1<<PVR2_SUBSYS_B_ENC_FIRMWARE) | \
1186          (1<<PVR2_SUBSYS_B_USBSTREAM_RUN))
1187
1188 /*
1189
1190   This single function is key to pretty much everything.  The pvrusb2
1191   device can logically be viewed as a series of subsystems which can be
1192   stopped / started or unconfigured / configured.  To get things streaming,
1193   one must configure everything and start everything, but there may be
1194   various reasons over time to deconfigure something or stop something.
1195   This function handles all of this activity.  Everything EVERYWHERE that
1196   must affect a subsystem eventually comes here to do the work.
1197
1198   The current state of all subsystems is represented by a single bit mask,
1199   known as subsys_enabled_mask.  The bit positions are defined by the
1200   PVR2_SUBSYS_xxxx macros, with one subsystem per bit position.  At any
1201   time the set of configured or active subsystems can be queried just by
1202   looking at that mask.  To change bits in that mask, this function here
1203   must be called.  The "msk" argument indicates which bit positions to
1204   change, and the "val" argument defines the new values for the positions
1205   defined by "msk".
1206
1207   There is a priority ordering of starting / stopping things, and for
1208   multiple requested changes, this function implements that ordering.
1209   (Thus we will act on a request to load encoder firmware before we
1210   configure the encoder.)  In addition to priority ordering, there is a
1211   recovery strategy implemented here.  If a particular step fails and we
1212   detect that failure, this function will clear the affected subsystem bits
1213   and restart.  Thus we have a means for recovering from a dead encoder:
1214   Clear all bits that correspond to subsystems that we need to restart /
1215   reconfigure and start over.
1216
1217 */
1218 static void pvr2_hdw_subsys_bit_chg_no_lock(struct pvr2_hdw *hdw,
1219                                             unsigned long msk,
1220                                             unsigned long val)
1221 {
1222         unsigned long nmsk;
1223         unsigned long vmsk;
1224         int ret;
1225         unsigned int tryCount = 0;
1226
1227         if (!hdw->flag_ok) return;
1228
1229         msk &= PVR2_SUBSYS_ALL;
1230         nmsk = (hdw->subsys_enabled_mask & ~msk) | (val & msk);
1231         nmsk &= PVR2_SUBSYS_ALL;
1232
1233         for (;;) {
1234                 tryCount++;
1235                 if (!((nmsk ^ hdw->subsys_enabled_mask) &
1236                       PVR2_SUBSYS_ALL)) break;
1237                 if (tryCount > 4) {
1238                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1239                                    "Too many retries when configuring device;"
1240                                    " giving up");
1241                         pvr2_hdw_render_useless(hdw);
1242                         break;
1243                 }
1244                 if (tryCount > 1) {
1245                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1246                                    "Retrying device reconfiguration");
1247                 }
1248                 pvr2_trace(PVR2_TRACE_INIT,
1249                            "subsys mask changing 0x%lx:0x%lx"
1250                            " from 0x%lx to 0x%lx",
1251                            msk,val,hdw->subsys_enabled_mask,nmsk);
1252
1253                 vmsk = (nmsk ^ hdw->subsys_enabled_mask) &
1254                         hdw->subsys_enabled_mask;
1255                 if (vmsk) {
1256                         if (vmsk & (1<<PVR2_SUBSYS_B_ENC_RUN)) {
1257                                 pvr2_trace(PVR2_TRACE_CTL,
1258                                            "/*---TRACE_CTL----*/"
1259                                            " pvr2_encoder_stop");
1260                                 ret = pvr2_encoder_stop(hdw);
1261                                 if (ret) {
1262                                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1263                                                    "Error recovery initiated");
1264                                         hdw->subsys_enabled_mask &=
1265                                                 ~FIRMWARE_RECOVERY_BITS;
1266                                         continue;
1267                                 }
1268                         }
1269                         if (vmsk & (1<<PVR2_SUBSYS_B_USBSTREAM_RUN)) {
1270                                 pvr2_trace(PVR2_TRACE_CTL,
1271                                            "/*---TRACE_CTL----*/"
1272                                            " pvr2_hdw_cmd_usbstream(0)");
1273                                 pvr2_hdw_cmd_usbstream(hdw,0);
1274                         }
1275                         if (vmsk & (1<<PVR2_SUBSYS_B_DIGITIZER_RUN)) {
1276                                 pvr2_trace(PVR2_TRACE_CTL,
1277                                            "/*---TRACE_CTL----*/"
1278                                            " decoder disable");
1279                                 if (hdw->decoder_ctrl) {
1280                                         hdw->decoder_ctrl->enable(
1281                                                 hdw->decoder_ctrl->ctxt,0);
1282                                 } else {
1283                                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1284                                                    "WARNING:"
1285                                                    " No decoder present");
1286                                 }
1287                                 hdw->subsys_enabled_mask &=
1288                                         ~(1<<PVR2_SUBSYS_B_DIGITIZER_RUN);
1289                         }
1290                         if (vmsk & PVR2_SUBSYS_CFG_ALL) {
1291                                 hdw->subsys_enabled_mask &=
1292                                         ~(vmsk & PVR2_SUBSYS_CFG_ALL);
1293                         }
1294                 }
1295                 vmsk = (nmsk ^ hdw->subsys_enabled_mask) & nmsk;
1296                 if (vmsk) {
1297                         if (vmsk & (1<<PVR2_SUBSYS_B_ENC_FIRMWARE)) {
1298                                 pvr2_trace(PVR2_TRACE_CTL,
1299                                            "/*---TRACE_CTL----*/"
1300                                            " pvr2_upload_firmware2");
1301                                 ret = pvr2_upload_firmware2(hdw);
1302                                 if (ret) {
1303                                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1304                                                    "Failure uploading encoder"
1305                                                    " firmware");
1306                                         pvr2_hdw_render_useless(hdw);
1307                                         break;
1308                                 }
1309                         }
1310                         if (vmsk & (1<<PVR2_SUBSYS_B_ENC_CFG)) {
1311                                 pvr2_trace(PVR2_TRACE_CTL,
1312                                            "/*---TRACE_CTL----*/"
1313                                            " pvr2_encoder_configure");
1314                                 ret = pvr2_encoder_configure(hdw);
1315                                 if (ret) {
1316                                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1317                                                    "Error recovery initiated");
1318                                         hdw->subsys_enabled_mask &=
1319                                                 ~FIRMWARE_RECOVERY_BITS;
1320                                         continue;
1321                                 }
1322                         }
1323                         if (vmsk & (1<<PVR2_SUBSYS_B_DIGITIZER_RUN)) {
1324                                 pvr2_trace(PVR2_TRACE_CTL,
1325                                            "/*---TRACE_CTL----*/"
1326                                            " decoder enable");
1327                                 if (hdw->decoder_ctrl) {
1328                                         hdw->decoder_ctrl->enable(
1329                                                 hdw->decoder_ctrl->ctxt,!0);
1330                                 } else {
1331                                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1332                                                    "WARNING:"
1333                                                    " No decoder present");
1334                                 }
1335                                 hdw->subsys_enabled_mask |=
1336                                         (1<<PVR2_SUBSYS_B_DIGITIZER_RUN);
1337                         }
1338                         if (vmsk & (1<<PVR2_SUBSYS_B_USBSTREAM_RUN)) {
1339                                 pvr2_trace(PVR2_TRACE_CTL,
1340                                            "/*---TRACE_CTL----*/"
1341                                            " pvr2_hdw_cmd_usbstream(1)");
1342                                 pvr2_hdw_cmd_usbstream(hdw,!0);
1343                         }
1344                         if (vmsk & (1<<PVR2_SUBSYS_B_ENC_RUN)) {
1345                                 pvr2_trace(PVR2_TRACE_CTL,
1346                                            "/*---TRACE_CTL----*/"
1347                                            " pvr2_encoder_start");
1348                                 ret = pvr2_encoder_start(hdw);
1349                                 if (ret) {
1350                                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1351                                                    "Error recovery initiated");
1352                                         hdw->subsys_enabled_mask &=
1353                                                 ~FIRMWARE_RECOVERY_BITS;
1354                                         continue;
1355                                 }
1356                         }
1357                 }
1358         }
1359 }
1360
1361
1362 void pvr2_hdw_subsys_bit_chg(struct pvr2_hdw *hdw,
1363                              unsigned long msk,unsigned long val)
1364 {
1365         LOCK_TAKE(hdw->big_lock); do {
1366                 pvr2_hdw_subsys_bit_chg_no_lock(hdw,msk,val);
1367         } while (0); LOCK_GIVE(hdw->big_lock);
1368 }
1369
1370
1371 unsigned long pvr2_hdw_subsys_get(struct pvr2_hdw *hdw)
1372 {
1373         return hdw->subsys_enabled_mask;
1374 }
1375
1376
1377 unsigned long pvr2_hdw_subsys_stream_get(struct pvr2_hdw *hdw)
1378 {
1379         return hdw->subsys_stream_mask;
1380 }
1381
1382
1383 static void pvr2_hdw_subsys_stream_bit_chg_no_lock(struct pvr2_hdw *hdw,
1384                                                    unsigned long msk,
1385                                                    unsigned long val)
1386 {
1387         unsigned long val2;
1388         msk &= PVR2_SUBSYS_ALL;
1389         val2 = ((hdw->subsys_stream_mask & ~msk) | (val & msk));
1390         pvr2_trace(PVR2_TRACE_INIT,
1391                    "stream mask changing 0x%lx:0x%lx from 0x%lx to 0x%lx",
1392                    msk,val,hdw->subsys_stream_mask,val2);
1393         hdw->subsys_stream_mask = val2;
1394 }
1395
1396
1397 void pvr2_hdw_subsys_stream_bit_chg(struct pvr2_hdw *hdw,
1398                                     unsigned long msk,
1399                                     unsigned long val)
1400 {
1401         LOCK_TAKE(hdw->big_lock); do {
1402                 pvr2_hdw_subsys_stream_bit_chg_no_lock(hdw,msk,val);
1403         } while (0); LOCK_GIVE(hdw->big_lock);
1404 }
1405
1406
1407 static int pvr2_hdw_set_streaming_no_lock(struct pvr2_hdw *hdw,int enableFl)
1408 {
1409         if ((!enableFl) == !(hdw->flag_streaming_enabled)) return 0;
1410         if (enableFl) {
1411                 pvr2_trace(PVR2_TRACE_START_STOP,
1412                            "/*--TRACE_STREAM--*/ enable");
1413                 pvr2_hdw_subsys_bit_chg_no_lock(hdw,~0,~0);
1414         } else {
1415                 pvr2_trace(PVR2_TRACE_START_STOP,
1416                            "/*--TRACE_STREAM--*/ disable");
1417                 pvr2_hdw_subsys_bit_chg_no_lock(hdw,hdw->subsys_stream_mask,0);
1418         }
1419         if (!hdw->flag_ok) return -EIO;
1420         hdw->flag_streaming_enabled = enableFl != 0;
1421         return 0;
1422 }
1423
1424
1425 int pvr2_hdw_get_streaming(struct pvr2_hdw *hdw)
1426 {
1427         return hdw->flag_streaming_enabled != 0;
1428 }
1429
1430
1431 int pvr2_hdw_set_streaming(struct pvr2_hdw *hdw,int enable_flag)
1432 {
1433         int ret;
1434         LOCK_TAKE(hdw->big_lock); do {
1435                 ret = pvr2_hdw_set_streaming_no_lock(hdw,enable_flag);
1436         } while (0); LOCK_GIVE(hdw->big_lock);
1437         return ret;
1438 }
1439
1440
1441 static int pvr2_hdw_set_stream_type_no_lock(struct pvr2_hdw *hdw,
1442                                             enum pvr2_config config)
1443 {
1444         unsigned long sm = hdw->subsys_enabled_mask;
1445         if (!hdw->flag_ok) return -EIO;
1446         pvr2_hdw_subsys_bit_chg_no_lock(hdw,hdw->subsys_stream_mask,0);
1447         hdw->config = config;
1448         pvr2_hdw_subsys_bit_chg_no_lock(hdw,~0,sm);
1449         return 0;
1450 }
1451
1452
1453 int pvr2_hdw_set_stream_type(struct pvr2_hdw *hdw,enum pvr2_config config)
1454 {
1455         int ret;
1456         if (!hdw->flag_ok) return -EIO;
1457         LOCK_TAKE(hdw->big_lock);
1458         ret = pvr2_hdw_set_stream_type_no_lock(hdw,config);
1459         LOCK_GIVE(hdw->big_lock);
1460         return ret;
1461 }
1462
1463
1464 static int get_default_tuner_type(struct pvr2_hdw *hdw)
1465 {
1466         int unit_number = hdw->unit_number;
1467         int tp = -1;
1468         if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1469                 tp = tuner[unit_number];
1470         }
1471         if (tp < 0) return -EINVAL;
1472         hdw->tuner_type = tp;
1473         return 0;
1474 }
1475
1476
1477 static v4l2_std_id get_default_standard(struct pvr2_hdw *hdw)
1478 {
1479         int unit_number = hdw->unit_number;
1480         int tp = 0;
1481         if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1482                 tp = video_std[unit_number];
1483         }
1484         return tp;
1485 }
1486
1487
1488 static unsigned int get_default_error_tolerance(struct pvr2_hdw *hdw)
1489 {
1490         int unit_number = hdw->unit_number;
1491         int tp = 0;
1492         if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1493                 tp = tolerance[unit_number];
1494         }
1495         return tp;
1496 }
1497
1498
1499 static int pvr2_hdw_check_firmware(struct pvr2_hdw *hdw)
1500 {
1501         /* Try a harmless request to fetch the eeprom's address over
1502            endpoint 1.  See what happens.  Only the full FX2 image can
1503            respond to this.  If this probe fails then likely the FX2
1504            firmware needs be loaded. */
1505         int result;
1506         LOCK_TAKE(hdw->ctl_lock); do {
1507                 hdw->cmd_buffer[0] = 0xeb;
1508                 result = pvr2_send_request_ex(hdw,HZ*1,!0,
1509                                            hdw->cmd_buffer,1,
1510                                            hdw->cmd_buffer,1);
1511                 if (result < 0) break;
1512         } while(0); LOCK_GIVE(hdw->ctl_lock);
1513         if (result) {
1514                 pvr2_trace(PVR2_TRACE_INIT,
1515                            "Probe of device endpoint 1 result status %d",
1516                            result);
1517         } else {
1518                 pvr2_trace(PVR2_TRACE_INIT,
1519                            "Probe of device endpoint 1 succeeded");
1520         }
1521         return result == 0;
1522 }
1523
1524 static void pvr2_hdw_setup_std(struct pvr2_hdw *hdw)
1525 {
1526         char buf[40];
1527         unsigned int bcnt;
1528         v4l2_std_id std1,std2;
1529
1530         std1 = get_default_standard(hdw);
1531
1532         bcnt = pvr2_std_id_to_str(buf,sizeof(buf),hdw->std_mask_eeprom);
1533         pvr2_trace(PVR2_TRACE_INIT,
1534                    "Supported video standard(s) reported by eeprom: %.*s",
1535                    bcnt,buf);
1536
1537         hdw->std_mask_avail = hdw->std_mask_eeprom;
1538
1539         std2 = std1 & ~hdw->std_mask_avail;
1540         if (std2) {
1541                 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std2);
1542                 pvr2_trace(PVR2_TRACE_INIT,
1543                            "Expanding supported video standards"
1544                            " to include: %.*s",
1545                            bcnt,buf);
1546                 hdw->std_mask_avail |= std2;
1547         }
1548
1549         pvr2_hdw_internal_set_std_avail(hdw);
1550
1551         if (std1) {
1552                 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std1);
1553                 pvr2_trace(PVR2_TRACE_INIT,
1554                            "Initial video standard forced to %.*s",
1555                            bcnt,buf);
1556                 hdw->std_mask_cur = std1;
1557                 hdw->std_dirty = !0;
1558                 pvr2_hdw_internal_find_stdenum(hdw);
1559                 return;
1560         }
1561
1562         if (hdw->std_enum_cnt > 1) {
1563                 // Autoselect the first listed standard
1564                 hdw->std_enum_cur = 1;
1565                 hdw->std_mask_cur = hdw->std_defs[hdw->std_enum_cur-1].id;
1566                 hdw->std_dirty = !0;
1567                 pvr2_trace(PVR2_TRACE_INIT,
1568                            "Initial video standard auto-selected to %s",
1569                            hdw->std_defs[hdw->std_enum_cur-1].name);
1570                 return;
1571         }
1572
1573         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1574                    "Unable to select a viable initial video standard");
1575 }
1576
1577
1578 static void pvr2_hdw_setup_low(struct pvr2_hdw *hdw)
1579 {
1580         int ret;
1581         unsigned int idx;
1582         struct pvr2_ctrl *cptr;
1583         int reloadFl = 0;
1584         if (!reloadFl) {
1585                 reloadFl = (hdw->usb_intf->cur_altsetting->desc.bNumEndpoints
1586                             == 0);
1587                 if (reloadFl) {
1588                         pvr2_trace(PVR2_TRACE_INIT,
1589                                    "USB endpoint config looks strange"
1590                                    "; possibly firmware needs to be loaded");
1591                 }
1592         }
1593         if (!reloadFl) {
1594                 reloadFl = !pvr2_hdw_check_firmware(hdw);
1595                 if (reloadFl) {
1596                         pvr2_trace(PVR2_TRACE_INIT,
1597                                    "Check for FX2 firmware failed"
1598                                    "; possibly firmware needs to be loaded");
1599                 }
1600         }
1601         if (reloadFl) {
1602                 if (pvr2_upload_firmware1(hdw) != 0) {
1603                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1604                                    "Failure uploading firmware1");
1605                 }
1606                 return;
1607         }
1608         hdw->fw1_state = FW1_STATE_OK;
1609
1610         if (initusbreset) {
1611                 pvr2_hdw_device_reset(hdw);
1612         }
1613         if (!pvr2_hdw_dev_ok(hdw)) return;
1614
1615         for (idx = 0; idx < pvr2_client_lists[hdw->hdw_type].cnt; idx++) {
1616                 request_module(pvr2_client_lists[hdw->hdw_type].lst[idx]);
1617         }
1618
1619         pvr2_hdw_cmd_powerup(hdw);
1620         if (!pvr2_hdw_dev_ok(hdw)) return;
1621
1622         if (pvr2_upload_firmware2(hdw)){
1623                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,"device unstable!!");
1624                 pvr2_hdw_render_useless(hdw);
1625                 return;
1626         }
1627
1628         // This step MUST happen after the earlier powerup step.
1629         pvr2_i2c_core_init(hdw);
1630         if (!pvr2_hdw_dev_ok(hdw)) return;
1631
1632         for (idx = 0; idx < CTRLDEF_COUNT; idx++) {
1633                 cptr = hdw->controls + idx;
1634                 if (cptr->info->skip_init) continue;
1635                 if (!cptr->info->set_value) continue;
1636                 cptr->info->set_value(cptr,~0,cptr->info->default_value);
1637         }
1638
1639         // Do not use pvr2_reset_ctl_endpoints() here.  It is not
1640         // thread-safe against the normal pvr2_send_request() mechanism.
1641         // (We should make it thread safe).
1642
1643         ret = pvr2_hdw_get_eeprom_addr(hdw);
1644         if (!pvr2_hdw_dev_ok(hdw)) return;
1645         if (ret < 0) {
1646                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1647                            "Unable to determine location of eeprom, skipping");
1648         } else {
1649                 hdw->eeprom_addr = ret;
1650                 pvr2_eeprom_analyze(hdw);
1651                 if (!pvr2_hdw_dev_ok(hdw)) return;
1652         }
1653
1654         pvr2_hdw_setup_std(hdw);
1655
1656         if (!get_default_tuner_type(hdw)) {
1657                 pvr2_trace(PVR2_TRACE_INIT,
1658                            "pvr2_hdw_setup: Tuner type overridden to %d",
1659                            hdw->tuner_type);
1660         }
1661
1662         hdw->tuner_updated = !0;
1663         pvr2_i2c_core_check_stale(hdw);
1664         hdw->tuner_updated = 0;
1665
1666         if (!pvr2_hdw_dev_ok(hdw)) return;
1667
1668         pvr2_hdw_commit_ctl_internal(hdw);
1669         if (!pvr2_hdw_dev_ok(hdw)) return;
1670
1671         hdw->vid_stream = pvr2_stream_create();
1672         if (!pvr2_hdw_dev_ok(hdw)) return;
1673         pvr2_trace(PVR2_TRACE_INIT,
1674                    "pvr2_hdw_setup: video stream is %p",hdw->vid_stream);
1675         if (hdw->vid_stream) {
1676                 idx = get_default_error_tolerance(hdw);
1677                 if (idx) {
1678                         pvr2_trace(PVR2_TRACE_INIT,
1679                                    "pvr2_hdw_setup: video stream %p"
1680                                    " setting tolerance %u",
1681                                    hdw->vid_stream,idx);
1682                 }
1683                 pvr2_stream_setup(hdw->vid_stream,hdw->usb_dev,
1684                                   PVR2_VID_ENDPOINT,idx);
1685         }
1686
1687         if (!pvr2_hdw_dev_ok(hdw)) return;
1688
1689         /* Make sure everything is up to date */
1690         pvr2_i2c_core_sync(hdw);
1691
1692         if (!pvr2_hdw_dev_ok(hdw)) return;
1693
1694         hdw->flag_init_ok = !0;
1695 }
1696
1697
1698 int pvr2_hdw_setup(struct pvr2_hdw *hdw)
1699 {
1700         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_setup(hdw=%p) begin",hdw);
1701         LOCK_TAKE(hdw->big_lock); do {
1702                 pvr2_hdw_setup_low(hdw);
1703                 pvr2_trace(PVR2_TRACE_INIT,
1704                            "pvr2_hdw_setup(hdw=%p) done, ok=%d init_ok=%d",
1705                            hdw,hdw->flag_ok,hdw->flag_init_ok);
1706                 if (pvr2_hdw_dev_ok(hdw)) {
1707                         if (pvr2_hdw_init_ok(hdw)) {
1708                                 pvr2_trace(
1709                                         PVR2_TRACE_INFO,
1710                                         "Device initialization"
1711                                         " completed successfully.");
1712                                 break;
1713                         }
1714                         if (hdw->fw1_state == FW1_STATE_RELOAD) {
1715                                 pvr2_trace(
1716                                         PVR2_TRACE_INFO,
1717                                         "Device microcontroller firmware"
1718                                         " (re)loaded; it should now reset"
1719                                         " and reconnect.");
1720                                 break;
1721                         }
1722                         pvr2_trace(
1723                                 PVR2_TRACE_ERROR_LEGS,
1724                                 "Device initialization was not successful.");
1725                         if (hdw->fw1_state == FW1_STATE_MISSING) {
1726                                 pvr2_trace(
1727                                         PVR2_TRACE_ERROR_LEGS,
1728                                         "Giving up since device"
1729                                         " microcontroller firmware"
1730                                         " appears to be missing.");
1731                                 break;
1732                         }
1733                 }
1734                 if (procreload) {
1735                         pvr2_trace(
1736                                 PVR2_TRACE_ERROR_LEGS,
1737                                 "Attempting pvrusb2 recovery by reloading"
1738                                 " primary firmware.");
1739                         pvr2_trace(
1740                                 PVR2_TRACE_ERROR_LEGS,
1741                                 "If this works, device should disconnect"
1742                                 " and reconnect in a sane state.");
1743                         hdw->fw1_state = FW1_STATE_UNKNOWN;
1744                         pvr2_upload_firmware1(hdw);
1745                 } else {
1746                         pvr2_trace(
1747                                 PVR2_TRACE_ERROR_LEGS,
1748                                 "***WARNING*** pvrusb2 device hardware"
1749                                 " appears to be jammed"
1750                                 " and I can't clear it.");
1751                         pvr2_trace(
1752                                 PVR2_TRACE_ERROR_LEGS,
1753                                 "You might need to power cycle"
1754                                 " the pvrusb2 device"
1755                                 " in order to recover.");
1756                 }
1757         } while (0); LOCK_GIVE(hdw->big_lock);
1758         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_setup(hdw=%p) end",hdw);
1759         return hdw->flag_init_ok;
1760 }
1761
1762
1763 /* Create and return a structure for interacting with the underlying
1764    hardware */
1765 struct pvr2_hdw *pvr2_hdw_create(struct usb_interface *intf,
1766                                  const struct usb_device_id *devid)
1767 {
1768         unsigned int idx,cnt1,cnt2;
1769         struct pvr2_hdw *hdw;
1770         unsigned int hdw_type;
1771         int valid_std_mask;
1772         struct pvr2_ctrl *cptr;
1773         __u8 ifnum;
1774         struct v4l2_queryctrl qctrl;
1775         struct pvr2_ctl_info *ciptr;
1776
1777         hdw_type = devid - pvr2_device_table;
1778         if (hdw_type >=
1779             sizeof(pvr2_device_names)/sizeof(pvr2_device_names[0])) {
1780                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1781                            "Bogus device type of %u reported",hdw_type);
1782                 return NULL;
1783         }
1784
1785         hdw = kmalloc(sizeof(*hdw),GFP_KERNEL);
1786         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_create: hdw=%p, type \"%s\"",
1787                    hdw,pvr2_device_names[hdw_type]);
1788         if (!hdw) goto fail;
1789         memset(hdw,0,sizeof(*hdw));
1790         cx2341x_fill_defaults(&hdw->enc_ctl_state);
1791
1792         hdw->control_cnt = CTRLDEF_COUNT;
1793         hdw->control_cnt += MPEGDEF_COUNT;
1794         hdw->controls = kmalloc(sizeof(struct pvr2_ctrl) * hdw->control_cnt,
1795                                 GFP_KERNEL);
1796         if (!hdw->controls) goto fail;
1797         memset(hdw->controls,0,sizeof(struct pvr2_ctrl) * hdw->control_cnt);
1798         hdw->hdw_type = hdw_type;
1799         for (idx = 0; idx < hdw->control_cnt; idx++) {
1800                 cptr = hdw->controls + idx;
1801                 cptr->hdw = hdw;
1802         }
1803         for (idx = 0; idx < 32; idx++) {
1804                 hdw->std_mask_ptrs[idx] = hdw->std_mask_names[idx];
1805         }
1806         for (idx = 0; idx < CTRLDEF_COUNT; idx++) {
1807                 cptr = hdw->controls + idx;
1808                 cptr->info = control_defs+idx;
1809         }
1810         /* Define and configure additional controls from cx2341x module. */
1811         hdw->mpeg_ctrl_info = kmalloc(
1812                 sizeof(*(hdw->mpeg_ctrl_info)) * MPEGDEF_COUNT, GFP_KERNEL);
1813         if (!hdw->mpeg_ctrl_info) goto fail;
1814         memset(hdw->mpeg_ctrl_info,0,
1815                sizeof(*(hdw->mpeg_ctrl_info)) * MPEGDEF_COUNT);
1816         for (idx = 0; idx < MPEGDEF_COUNT; idx++) {
1817                 cptr = hdw->controls + idx + CTRLDEF_COUNT;
1818                 ciptr = &(hdw->mpeg_ctrl_info[idx].info);
1819                 ciptr->desc = hdw->mpeg_ctrl_info[idx].desc;
1820                 ciptr->name = mpeg_ids[idx].strid;
1821                 ciptr->v4l_id = mpeg_ids[idx].id;
1822                 ciptr->skip_init = !0;
1823                 ciptr->get_value = ctrl_cx2341x_get;
1824                 ciptr->get_v4lflags = ctrl_cx2341x_getv4lflags;
1825                 ciptr->is_dirty = ctrl_cx2341x_is_dirty;
1826                 if (!idx) ciptr->clear_dirty = ctrl_cx2341x_clear_dirty;
1827                 qctrl.id = ciptr->v4l_id;
1828                 cx2341x_ctrl_query(&hdw->enc_ctl_state,&qctrl);
1829                 if (!(qctrl.flags & V4L2_CTRL_FLAG_READ_ONLY)) {
1830                         ciptr->set_value = ctrl_cx2341x_set;
1831                 }
1832                 strncpy(hdw->mpeg_ctrl_info[idx].desc,qctrl.name,
1833                         PVR2_CTLD_INFO_DESC_SIZE);
1834                 hdw->mpeg_ctrl_info[idx].desc[PVR2_CTLD_INFO_DESC_SIZE-1] = 0;
1835                 ciptr->default_value = qctrl.default_value;
1836                 switch (qctrl.type) {
1837                 default:
1838                 case V4L2_CTRL_TYPE_INTEGER:
1839                         ciptr->type = pvr2_ctl_int;
1840                         ciptr->def.type_int.min_value = qctrl.minimum;
1841                         ciptr->def.type_int.max_value = qctrl.maximum;
1842                         break;
1843                 case V4L2_CTRL_TYPE_BOOLEAN:
1844                         ciptr->type = pvr2_ctl_bool;
1845                         break;
1846                 case V4L2_CTRL_TYPE_MENU:
1847                         ciptr->type = pvr2_ctl_enum;
1848                         ciptr->def.type_enum.value_names =
1849                                 cx2341x_ctrl_get_menu(ciptr->v4l_id);
1850                         for (cnt1 = 0;
1851                              ciptr->def.type_enum.value_names[cnt1] != NULL;
1852                              cnt1++) { }
1853                         ciptr->def.type_enum.count = cnt1;
1854                         break;
1855                 }
1856                 cptr->info = ciptr;
1857         }
1858
1859         // Initialize video standard enum dynamic control
1860         cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDENUM);
1861         if (cptr) {
1862                 memcpy(&hdw->std_info_enum,cptr->info,
1863                        sizeof(hdw->std_info_enum));
1864                 cptr->info = &hdw->std_info_enum;
1865
1866         }
1867         // Initialize control data regarding video standard masks
1868         valid_std_mask = pvr2_std_get_usable();
1869         for (idx = 0; idx < 32; idx++) {
1870                 if (!(valid_std_mask & (1 << idx))) continue;
1871                 cnt1 = pvr2_std_id_to_str(
1872                         hdw->std_mask_names[idx],
1873                         sizeof(hdw->std_mask_names[idx])-1,
1874                         1 << idx);
1875                 hdw->std_mask_names[idx][cnt1] = 0;
1876         }
1877         cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDAVAIL);
1878         if (cptr) {
1879                 memcpy(&hdw->std_info_avail,cptr->info,
1880                        sizeof(hdw->std_info_avail));
1881                 cptr->info = &hdw->std_info_avail;
1882                 hdw->std_info_avail.def.type_bitmask.bit_names =
1883                         hdw->std_mask_ptrs;
1884                 hdw->std_info_avail.def.type_bitmask.valid_bits =
1885                         valid_std_mask;
1886         }
1887         cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDCUR);
1888         if (cptr) {
1889                 memcpy(&hdw->std_info_cur,cptr->info,
1890                        sizeof(hdw->std_info_cur));
1891                 cptr->info = &hdw->std_info_cur;
1892                 hdw->std_info_cur.def.type_bitmask.bit_names =
1893                         hdw->std_mask_ptrs;
1894                 hdw->std_info_avail.def.type_bitmask.valid_bits =
1895                         valid_std_mask;
1896         }
1897
1898         hdw->eeprom_addr = -1;
1899         hdw->unit_number = -1;
1900         hdw->v4l_minor_number = -1;
1901         hdw->ctl_write_buffer = kmalloc(PVR2_CTL_BUFFSIZE,GFP_KERNEL);
1902         if (!hdw->ctl_write_buffer) goto fail;
1903         hdw->ctl_read_buffer = kmalloc(PVR2_CTL_BUFFSIZE,GFP_KERNEL);
1904         if (!hdw->ctl_read_buffer) goto fail;
1905         hdw->ctl_write_urb = usb_alloc_urb(0,GFP_KERNEL);
1906         if (!hdw->ctl_write_urb) goto fail;
1907         hdw->ctl_read_urb = usb_alloc_urb(0,GFP_KERNEL);
1908         if (!hdw->ctl_read_urb) goto fail;
1909
1910         down(&pvr2_unit_sem); do {
1911                 for (idx = 0; idx < PVR_NUM; idx++) {
1912                         if (unit_pointers[idx]) continue;
1913                         hdw->unit_number = idx;
1914                         unit_pointers[idx] = hdw;
1915                         break;
1916                 }
1917         } while (0); up(&pvr2_unit_sem);
1918
1919         cnt1 = 0;
1920         cnt2 = scnprintf(hdw->name+cnt1,sizeof(hdw->name)-cnt1,"pvrusb2");
1921         cnt1 += cnt2;
1922         if (hdw->unit_number >= 0) {
1923                 cnt2 = scnprintf(hdw->name+cnt1,sizeof(hdw->name)-cnt1,"_%c",
1924                                  ('a' + hdw->unit_number));
1925                 cnt1 += cnt2;
1926         }
1927         if (cnt1 >= sizeof(hdw->name)) cnt1 = sizeof(hdw->name)-1;
1928         hdw->name[cnt1] = 0;
1929
1930         pvr2_trace(PVR2_TRACE_INIT,"Driver unit number is %d, name is %s",
1931                    hdw->unit_number,hdw->name);
1932
1933         hdw->tuner_type = -1;
1934         hdw->flag_ok = !0;
1935         /* Initialize the mask of subsystems that we will shut down when we
1936            stop streaming. */
1937         hdw->subsys_stream_mask = PVR2_SUBSYS_RUN_ALL;
1938         hdw->subsys_stream_mask |= (1<<PVR2_SUBSYS_B_ENC_CFG);
1939
1940         pvr2_trace(PVR2_TRACE_INIT,"subsys_stream_mask: 0x%lx",
1941                    hdw->subsys_stream_mask);
1942
1943         hdw->usb_intf = intf;
1944         hdw->usb_dev = interface_to_usbdev(intf);
1945
1946         ifnum = hdw->usb_intf->cur_altsetting->desc.bInterfaceNumber;
1947         usb_set_interface(hdw->usb_dev,ifnum,0);
1948
1949         mutex_init(&hdw->ctl_lock_mutex);
1950         mutex_init(&hdw->big_lock_mutex);
1951
1952         return hdw;
1953  fail:
1954         if (hdw) {
1955                 if (hdw->ctl_read_urb) usb_free_urb(hdw->ctl_read_urb);
1956                 if (hdw->ctl_write_urb) usb_free_urb(hdw->ctl_write_urb);
1957                 if (hdw->ctl_read_buffer) kfree(hdw->ctl_read_buffer);
1958                 if (hdw->ctl_write_buffer) kfree(hdw->ctl_write_buffer);
1959                 if (hdw->controls) kfree(hdw->controls);
1960                 if (hdw->mpeg_ctrl_info) kfree(hdw->mpeg_ctrl_info);
1961                 kfree(hdw);
1962         }
1963         return NULL;
1964 }
1965
1966
1967 /* Remove _all_ associations between this driver and the underlying USB
1968    layer. */
1969 static void pvr2_hdw_remove_usb_stuff(struct pvr2_hdw *hdw)
1970 {
1971         if (hdw->flag_disconnected) return;
1972         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_remove_usb_stuff: hdw=%p",hdw);
1973         if (hdw->ctl_read_urb) {
1974                 usb_kill_urb(hdw->ctl_read_urb);
1975                 usb_free_urb(hdw->ctl_read_urb);
1976                 hdw->ctl_read_urb = NULL;
1977         }
1978         if (hdw->ctl_write_urb) {
1979                 usb_kill_urb(hdw->ctl_write_urb);
1980                 usb_free_urb(hdw->ctl_write_urb);
1981                 hdw->ctl_write_urb = NULL;
1982         }
1983         if (hdw->ctl_read_buffer) {
1984                 kfree(hdw->ctl_read_buffer);
1985                 hdw->ctl_read_buffer = NULL;
1986         }
1987         if (hdw->ctl_write_buffer) {
1988                 kfree(hdw->ctl_write_buffer);
1989                 hdw->ctl_write_buffer = NULL;
1990         }
1991         pvr2_hdw_render_useless_unlocked(hdw);
1992         hdw->flag_disconnected = !0;
1993         hdw->usb_dev = NULL;
1994         hdw->usb_intf = NULL;
1995 }
1996
1997
1998 /* Destroy hardware interaction structure */
1999 void pvr2_hdw_destroy(struct pvr2_hdw *hdw)
2000 {
2001         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_destroy: hdw=%p",hdw);
2002         if (hdw->fw_buffer) {
2003                 kfree(hdw->fw_buffer);
2004                 hdw->fw_buffer = NULL;
2005         }
2006         if (hdw->vid_stream) {
2007                 pvr2_stream_destroy(hdw->vid_stream);
2008                 hdw->vid_stream = NULL;
2009         }
2010         if (hdw->audio_stat) {
2011                 hdw->audio_stat->detach(hdw->audio_stat->ctxt);
2012         }
2013         if (hdw->decoder_ctrl) {
2014                 hdw->decoder_ctrl->detach(hdw->decoder_ctrl->ctxt);
2015         }
2016         pvr2_i2c_core_done(hdw);
2017         pvr2_hdw_remove_usb_stuff(hdw);
2018         down(&pvr2_unit_sem); do {
2019                 if ((hdw->unit_number >= 0) &&
2020                     (hdw->unit_number < PVR_NUM) &&
2021                     (unit_pointers[hdw->unit_number] == hdw)) {
2022                         unit_pointers[hdw->unit_number] = NULL;
2023                 }
2024         } while (0); up(&pvr2_unit_sem);
2025         if (hdw->controls) kfree(hdw->controls);
2026         if (hdw->mpeg_ctrl_info) kfree(hdw->mpeg_ctrl_info);
2027         if (hdw->std_defs) kfree(hdw->std_defs);
2028         if (hdw->std_enum_names) kfree(hdw->std_enum_names);
2029         kfree(hdw);
2030 }
2031
2032
2033 int pvr2_hdw_init_ok(struct pvr2_hdw *hdw)
2034 {
2035         return hdw->flag_init_ok;
2036 }
2037
2038
2039 int pvr2_hdw_dev_ok(struct pvr2_hdw *hdw)
2040 {
2041         return (hdw && hdw->flag_ok);
2042 }
2043
2044
2045 /* Called when hardware has been unplugged */
2046 void pvr2_hdw_disconnect(struct pvr2_hdw *hdw)
2047 {
2048         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_disconnect(hdw=%p)",hdw);
2049         LOCK_TAKE(hdw->big_lock);
2050         LOCK_TAKE(hdw->ctl_lock);
2051         pvr2_hdw_remove_usb_stuff(hdw);
2052         LOCK_GIVE(hdw->ctl_lock);
2053         LOCK_GIVE(hdw->big_lock);
2054 }
2055
2056
2057 // Attempt to autoselect an appropriate value for std_enum_cur given
2058 // whatever is currently in std_mask_cur
2059 static void pvr2_hdw_internal_find_stdenum(struct pvr2_hdw *hdw)
2060 {
2061         unsigned int idx;
2062         for (idx = 1; idx < hdw->std_enum_cnt; idx++) {
2063                 if (hdw->std_defs[idx-1].id == hdw->std_mask_cur) {
2064                         hdw->std_enum_cur = idx;
2065                         return;
2066                 }
2067         }
2068         hdw->std_enum_cur = 0;
2069 }
2070
2071
2072 // Calculate correct set of enumerated standards based on currently known
2073 // set of available standards bits.
2074 static void pvr2_hdw_internal_set_std_avail(struct pvr2_hdw *hdw)
2075 {
2076         struct v4l2_standard *newstd;
2077         unsigned int std_cnt;
2078         unsigned int idx;
2079
2080         newstd = pvr2_std_create_enum(&std_cnt,hdw->std_mask_avail);
2081
2082         if (hdw->std_defs) {
2083                 kfree(hdw->std_defs);
2084                 hdw->std_defs = NULL;
2085         }
2086         hdw->std_enum_cnt = 0;
2087         if (hdw->std_enum_names) {
2088                 kfree(hdw->std_enum_names);
2089                 hdw->std_enum_names = NULL;
2090         }
2091
2092         if (!std_cnt) {
2093                 pvr2_trace(
2094                         PVR2_TRACE_ERROR_LEGS,
2095                         "WARNING: Failed to identify any viable standards");
2096         }
2097         hdw->std_enum_names = kmalloc(sizeof(char *)*(std_cnt+1),GFP_KERNEL);
2098         hdw->std_enum_names[0] = "none";
2099         for (idx = 0; idx < std_cnt; idx++) {
2100                 hdw->std_enum_names[idx+1] =
2101                         newstd[idx].name;
2102         }
2103         // Set up the dynamic control for this standard
2104         hdw->std_info_enum.def.type_enum.value_names = hdw->std_enum_names;
2105         hdw->std_info_enum.def.type_enum.count = std_cnt+1;
2106         hdw->std_defs = newstd;
2107         hdw->std_enum_cnt = std_cnt+1;
2108         hdw->std_enum_cur = 0;
2109         hdw->std_info_cur.def.type_bitmask.valid_bits = hdw->std_mask_avail;
2110 }
2111
2112
2113 int pvr2_hdw_get_stdenum_value(struct pvr2_hdw *hdw,
2114                                struct v4l2_standard *std,
2115                                unsigned int idx)
2116 {
2117         int ret = -EINVAL;
2118         if (!idx) return ret;
2119         LOCK_TAKE(hdw->big_lock); do {
2120                 if (idx >= hdw->std_enum_cnt) break;
2121                 idx--;
2122                 memcpy(std,hdw->std_defs+idx,sizeof(*std));
2123                 ret = 0;
2124         } while (0); LOCK_GIVE(hdw->big_lock);
2125         return ret;
2126 }
2127
2128
2129 /* Get the number of defined controls */
2130 unsigned int pvr2_hdw_get_ctrl_count(struct pvr2_hdw *hdw)
2131 {
2132         return hdw->control_cnt;
2133 }
2134
2135
2136 /* Retrieve a control handle given its index (0..count-1) */
2137 struct pvr2_ctrl *pvr2_hdw_get_ctrl_by_index(struct pvr2_hdw *hdw,
2138                                              unsigned int idx)
2139 {
2140         if (idx >= hdw->control_cnt) return NULL;
2141         return hdw->controls + idx;
2142 }
2143
2144
2145 /* Retrieve a control handle given its index (0..count-1) */
2146 struct pvr2_ctrl *pvr2_hdw_get_ctrl_by_id(struct pvr2_hdw *hdw,
2147                                           unsigned int ctl_id)
2148 {
2149         struct pvr2_ctrl *cptr;
2150         unsigned int idx;
2151         int i;
2152
2153         /* This could be made a lot more efficient, but for now... */
2154         for (idx = 0; idx < hdw->control_cnt; idx++) {
2155                 cptr = hdw->controls + idx;
2156                 i = cptr->info->internal_id;
2157                 if (i && (i == ctl_id)) return cptr;
2158         }
2159         return NULL;
2160 }
2161
2162
2163 /* Given a V4L ID, retrieve the control structure associated with it. */
2164 struct pvr2_ctrl *pvr2_hdw_get_ctrl_v4l(struct pvr2_hdw *hdw,unsigned int ctl_id)
2165 {
2166         struct pvr2_ctrl *cptr;
2167         unsigned int idx;
2168         int i;
2169
2170         /* This could be made a lot more efficient, but for now... */
2171         for (idx = 0; idx < hdw->control_cnt; idx++) {
2172                 cptr = hdw->controls + idx;
2173                 i = cptr->info->v4l_id;
2174                 if (i && (i == ctl_id)) return cptr;
2175         }
2176         return NULL;
2177 }
2178
2179
2180 /* Given a V4L ID for its immediate predecessor, retrieve the control
2181    structure associated with it. */
2182 struct pvr2_ctrl *pvr2_hdw_get_ctrl_nextv4l(struct pvr2_hdw *hdw,
2183                                             unsigned int ctl_id)
2184 {
2185         struct pvr2_ctrl *cptr,*cp2;
2186         unsigned int idx;
2187         int i;
2188
2189         /* This could be made a lot more efficient, but for now... */
2190         cp2 = NULL;
2191         for (idx = 0; idx < hdw->control_cnt; idx++) {
2192                 cptr = hdw->controls + idx;
2193                 i = cptr->info->v4l_id;
2194                 if (!i) continue;
2195                 if (i <= ctl_id) continue;
2196                 if (cp2 && (cp2->info->v4l_id < i)) continue;
2197                 cp2 = cptr;
2198         }
2199         return cp2;
2200         return NULL;
2201 }
2202
2203
2204 static const char *get_ctrl_typename(enum pvr2_ctl_type tp)
2205 {
2206         switch (tp) {
2207         case pvr2_ctl_int: return "integer";
2208         case pvr2_ctl_enum: return "enum";
2209         case pvr2_ctl_bool: return "boolean";
2210         case pvr2_ctl_bitmask: return "bitmask";
2211         }
2212         return "";
2213 }
2214
2215
2216 /* Commit all control changes made up to this point.  Subsystems can be
2217    indirectly affected by these changes.  For a given set of things being
2218    committed, we'll clear the affected subsystem bits and then once we're
2219    done committing everything we'll make a request to restore the subsystem
2220    state(s) back to their previous value before this function was called.
2221    Thus we can automatically reconfigure affected pieces of the driver as
2222    controls are changed. */
2223 static int pvr2_hdw_commit_ctl_internal(struct pvr2_hdw *hdw)
2224 {
2225         unsigned long saved_subsys_mask = hdw->subsys_enabled_mask;
2226         unsigned long stale_subsys_mask = 0;
2227         unsigned int idx;
2228         struct pvr2_ctrl *cptr;
2229         int value;
2230         int commit_flag = 0;
2231         char buf[100];
2232         unsigned int bcnt,ccnt;
2233
2234         for (idx = 0; idx < hdw->control_cnt; idx++) {
2235                 cptr = hdw->controls + idx;
2236                 if (cptr->info->is_dirty == 0) continue;
2237                 if (!cptr->info->is_dirty(cptr)) continue;
2238                 if (!commit_flag) {
2239                         commit_flag = !0;
2240                 }
2241
2242                 bcnt = scnprintf(buf,sizeof(buf),"\"%s\" <-- ",
2243                                  cptr->info->name);
2244                 value = 0;
2245                 cptr->info->get_value(cptr,&value);
2246                 pvr2_ctrl_value_to_sym_internal(cptr,~0,value,
2247                                                 buf+bcnt,
2248                                                 sizeof(buf)-bcnt,&ccnt);
2249                 bcnt += ccnt;
2250                 bcnt += scnprintf(buf+bcnt,sizeof(buf)-bcnt," <%s>",
2251                                   get_ctrl_typename(cptr->info->type));
2252                 pvr2_trace(PVR2_TRACE_CTL,
2253                            "/*--TRACE_COMMIT--*/ %.*s",
2254                            bcnt,buf);
2255         }
2256
2257         if (!commit_flag) {
2258                 /* Nothing has changed */
2259                 return 0;
2260         }
2261
2262         /* When video standard changes, reset the hres and vres values -
2263            but if the user has pending changes there, then let the changes
2264            take priority. */
2265         if (hdw->std_dirty) {
2266                 /* Rewrite the vertical resolution to be appropriate to the
2267                    video standard that has been selected. */
2268                 int nvres;
2269                 if (hdw->std_mask_cur & V4L2_STD_525_60) {
2270                         nvres = 480;
2271                 } else {
2272                         nvres = 576;
2273                 }
2274                 if (nvres != hdw->res_ver_val) {
2275                         hdw->res_ver_val = nvres;
2276                         hdw->res_ver_dirty = !0;
2277                 }
2278         }
2279
2280         if (hdw->std_dirty ||
2281             hdw->enc_stale ||
2282             hdw->srate_dirty ||
2283             hdw->res_ver_dirty ||
2284             hdw->res_hor_dirty ||
2285             0) {
2286                 /* If any of this changes, then the encoder needs to be
2287                    reconfigured, and we need to reset the stream. */
2288                 stale_subsys_mask |= (1<<PVR2_SUBSYS_B_ENC_CFG);
2289         }
2290
2291         if (hdw->srate_dirty) {
2292                 /* Write new sample rate into control structure since
2293                  * the master copy is stale.  We must track srate
2294                  * separate from the mpeg control structure because
2295                  * other logic also uses this value. */
2296                 struct v4l2_ext_controls cs;
2297                 struct v4l2_ext_control c1;
2298                 memset(&cs,0,sizeof(cs));
2299                 memset(&c1,0,sizeof(c1));
2300                 cs.controls = &c1;
2301                 cs.count = 1;
2302                 c1.id = V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ;
2303                 c1.value = hdw->srate_val;
2304                 cx2341x_ext_ctrls(&hdw->enc_ctl_state,&cs,VIDIOC_S_EXT_CTRLS);
2305         }
2306
2307         /* Scan i2c core at this point - before we clear all the dirty
2308            bits.  Various parts of the i2c core will notice dirty bits as
2309            appropriate and arrange to broadcast or directly send updates to
2310            the client drivers in order to keep everything in sync */
2311         pvr2_i2c_core_check_stale(hdw);
2312
2313         for (idx = 0; idx < hdw->control_cnt; idx++) {
2314                 cptr = hdw->controls + idx;
2315                 if (!cptr->info->clear_dirty) continue;
2316                 cptr->info->clear_dirty(cptr);
2317         }
2318
2319         /* Now execute i2c core update */
2320         pvr2_i2c_core_sync(hdw);
2321
2322         pvr2_hdw_subsys_bit_chg_no_lock(hdw,stale_subsys_mask,0);
2323         pvr2_hdw_subsys_bit_chg_no_lock(hdw,~0,saved_subsys_mask);
2324
2325         return 0;
2326 }
2327
2328
2329 int pvr2_hdw_commit_ctl(struct pvr2_hdw *hdw)
2330 {
2331         LOCK_TAKE(hdw->big_lock); do {
2332                 pvr2_hdw_commit_ctl_internal(hdw);
2333         } while (0); LOCK_GIVE(hdw->big_lock);
2334         return 0;
2335 }
2336
2337
2338 void pvr2_hdw_poll(struct pvr2_hdw *hdw)
2339 {
2340         LOCK_TAKE(hdw->big_lock); do {
2341                 pvr2_i2c_core_sync(hdw);
2342         } while (0); LOCK_GIVE(hdw->big_lock);
2343 }
2344
2345
2346 void pvr2_hdw_setup_poll_trigger(struct pvr2_hdw *hdw,
2347                                  void (*func)(void *),
2348                                  void *data)
2349 {
2350         LOCK_TAKE(hdw->big_lock); do {
2351                 hdw->poll_trigger_func = func;
2352                 hdw->poll_trigger_data = data;
2353         } while (0); LOCK_GIVE(hdw->big_lock);
2354 }
2355
2356
2357 void pvr2_hdw_poll_trigger_unlocked(struct pvr2_hdw *hdw)
2358 {
2359         if (hdw->poll_trigger_func) {
2360                 hdw->poll_trigger_func(hdw->poll_trigger_data);
2361         }
2362 }
2363
2364 /* Return name for this driver instance */
2365 const char *pvr2_hdw_get_driver_name(struct pvr2_hdw *hdw)
2366 {
2367         return hdw->name;
2368 }
2369
2370
2371 /* Return bit mask indicating signal status */
2372 static unsigned int pvr2_hdw_get_signal_status_internal(struct pvr2_hdw *hdw)
2373 {
2374         unsigned int msk = 0;
2375         switch (hdw->input_val) {
2376         case PVR2_CVAL_INPUT_TV:
2377         case PVR2_CVAL_INPUT_RADIO:
2378                 if (hdw->decoder_ctrl &&
2379                     hdw->decoder_ctrl->tuned(hdw->decoder_ctrl->ctxt)) {
2380                         msk |= PVR2_SIGNAL_OK;
2381                         if (hdw->audio_stat &&
2382                             hdw->audio_stat->status(hdw->audio_stat->ctxt)) {
2383                                 if (hdw->flag_stereo) {
2384                                         msk |= PVR2_SIGNAL_STEREO;
2385                                 }
2386                                 if (hdw->flag_bilingual) {
2387                                         msk |= PVR2_SIGNAL_SAP;
2388                                 }
2389                         }
2390                 }
2391                 break;
2392         default:
2393                 msk |= PVR2_SIGNAL_OK | PVR2_SIGNAL_STEREO;
2394         }
2395         return msk;
2396 }
2397
2398
2399 int pvr2_hdw_is_hsm(struct pvr2_hdw *hdw)
2400 {
2401         int result;
2402         LOCK_TAKE(hdw->ctl_lock); do {
2403                 hdw->cmd_buffer[0] = 0x0b;
2404                 result = pvr2_send_request(hdw,
2405                                            hdw->cmd_buffer,1,
2406                                            hdw->cmd_buffer,1);
2407                 if (result < 0) break;
2408                 result = (hdw->cmd_buffer[0] != 0);
2409         } while(0); LOCK_GIVE(hdw->ctl_lock);
2410         return result;
2411 }
2412
2413
2414 /* Return bit mask indicating signal status */
2415 unsigned int pvr2_hdw_get_signal_status(struct pvr2_hdw *hdw)
2416 {
2417         unsigned int msk = 0;
2418         LOCK_TAKE(hdw->big_lock); do {
2419                 msk = pvr2_hdw_get_signal_status_internal(hdw);
2420         } while (0); LOCK_GIVE(hdw->big_lock);
2421         return msk;
2422 }
2423
2424
2425 /* Get handle to video output stream */
2426 struct pvr2_stream *pvr2_hdw_get_video_stream(struct pvr2_hdw *hp)
2427 {
2428         return hp->vid_stream;
2429 }
2430
2431
2432 void pvr2_hdw_trigger_module_log(struct pvr2_hdw *hdw)
2433 {
2434         int nr = pvr2_hdw_get_unit_number(hdw);
2435         LOCK_TAKE(hdw->big_lock); do {
2436                 hdw->log_requested = !0;
2437                 printk(KERN_INFO "pvrusb2: =================  START STATUS CARD #%d  =================\n", nr);
2438                 pvr2_i2c_core_check_stale(hdw);
2439                 hdw->log_requested = 0;
2440                 pvr2_i2c_core_sync(hdw);
2441                 pvr2_trace(PVR2_TRACE_INFO,"cx2341x config:");
2442                 cx2341x_log_status(&hdw->enc_ctl_state, "pvrusb2");
2443                 printk(KERN_INFO "pvrusb2: ==================  END STATUS CARD #%d  ==================\n", nr);
2444         } while (0); LOCK_GIVE(hdw->big_lock);
2445 }
2446
2447 void pvr2_hdw_cpufw_set_enabled(struct pvr2_hdw *hdw, int enable_flag)
2448 {
2449         int ret;
2450         u16 address;
2451         unsigned int pipe;
2452         LOCK_TAKE(hdw->big_lock); do {
2453                 if ((hdw->fw_buffer == 0) == !enable_flag) break;
2454
2455                 if (!enable_flag) {
2456                         pvr2_trace(PVR2_TRACE_FIRMWARE,
2457                                    "Cleaning up after CPU firmware fetch");
2458                         kfree(hdw->fw_buffer);
2459                         hdw->fw_buffer = NULL;
2460                         hdw->fw_size = 0;
2461                         /* Now release the CPU.  It will disconnect and
2462                            reconnect later. */
2463                         pvr2_hdw_cpureset_assert(hdw,0);
2464                         break;
2465                 }
2466
2467                 pvr2_trace(PVR2_TRACE_FIRMWARE,
2468                            "Preparing to suck out CPU firmware");
2469                 hdw->fw_size = 0x2000;
2470                 hdw->fw_buffer = kmalloc(hdw->fw_size,GFP_KERNEL);
2471                 if (!hdw->fw_buffer) {
2472                         hdw->fw_size = 0;
2473                         break;
2474                 }
2475
2476                 memset(hdw->fw_buffer,0,hdw->fw_size);
2477
2478                 /* We have to hold the CPU during firmware upload. */
2479                 pvr2_hdw_cpureset_assert(hdw,1);
2480
2481                 /* download the firmware from address 0000-1fff in 2048
2482                    (=0x800) bytes chunk. */
2483
2484                 pvr2_trace(PVR2_TRACE_FIRMWARE,"Grabbing CPU firmware");
2485                 pipe = usb_rcvctrlpipe(hdw->usb_dev, 0);
2486                 for(address = 0; address < hdw->fw_size; address += 0x800) {
2487                         ret = usb_control_msg(hdw->usb_dev,pipe,0xa0,0xc0,
2488                                               address,0,
2489                                               hdw->fw_buffer+address,0x800,HZ);
2490                         if (ret < 0) break;
2491                 }
2492
2493                 pvr2_trace(PVR2_TRACE_FIRMWARE,"Done grabbing CPU firmware");
2494
2495         } while (0); LOCK_GIVE(hdw->big_lock);
2496 }
2497
2498
2499 /* Return true if we're in a mode for retrieval CPU firmware */
2500 int pvr2_hdw_cpufw_get_enabled(struct pvr2_hdw *hdw)
2501 {
2502         return hdw->fw_buffer != 0;
2503 }
2504
2505
2506 int pvr2_hdw_cpufw_get(struct pvr2_hdw *hdw,unsigned int offs,
2507                        char *buf,unsigned int cnt)
2508 {
2509         int ret = -EINVAL;
2510         LOCK_TAKE(hdw->big_lock); do {
2511                 if (!buf) break;
2512                 if (!cnt) break;
2513
2514                 if (!hdw->fw_buffer) {
2515                         ret = -EIO;
2516                         break;
2517                 }
2518
2519                 if (offs >= hdw->fw_size) {
2520                         pvr2_trace(PVR2_TRACE_FIRMWARE,
2521                                    "Read firmware data offs=%d EOF",
2522                                    offs);
2523                         ret = 0;
2524                         break;
2525                 }
2526
2527                 if (offs + cnt > hdw->fw_size) cnt = hdw->fw_size - offs;
2528
2529                 memcpy(buf,hdw->fw_buffer+offs,cnt);
2530
2531                 pvr2_trace(PVR2_TRACE_FIRMWARE,
2532                            "Read firmware data offs=%d cnt=%d",
2533                            offs,cnt);
2534                 ret = cnt;
2535         } while (0); LOCK_GIVE(hdw->big_lock);
2536
2537         return ret;
2538 }
2539
2540
2541 int pvr2_hdw_v4l_get_minor_number(struct pvr2_hdw *hdw)
2542 {
2543         return hdw->v4l_minor_number;
2544 }
2545
2546
2547 /* Store the v4l minor device number */
2548 void pvr2_hdw_v4l_store_minor_number(struct pvr2_hdw *hdw,int v)
2549 {
2550         hdw->v4l_minor_number = v;
2551 }
2552
2553
2554 static void pvr2_ctl_write_complete(struct urb *urb, struct pt_regs *regs)
2555 {
2556         struct pvr2_hdw *hdw = urb->context;
2557         hdw->ctl_write_pend_flag = 0;
2558         if (hdw->ctl_read_pend_flag) return;
2559         complete(&hdw->ctl_done);
2560 }
2561
2562
2563 static void pvr2_ctl_read_complete(struct urb *urb, struct pt_regs *regs)
2564 {
2565         struct pvr2_hdw *hdw = urb->context;
2566         hdw->ctl_read_pend_flag = 0;
2567         if (hdw->ctl_write_pend_flag) return;
2568         complete(&hdw->ctl_done);
2569 }
2570
2571
2572 static void pvr2_ctl_timeout(unsigned long data)
2573 {
2574         struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
2575         if (hdw->ctl_write_pend_flag || hdw->ctl_read_pend_flag) {
2576                 hdw->ctl_timeout_flag = !0;
2577                 if (hdw->ctl_write_pend_flag && hdw->ctl_write_urb) {
2578                         usb_unlink_urb(hdw->ctl_write_urb);
2579                 }
2580                 if (hdw->ctl_read_pend_flag && hdw->ctl_read_urb) {
2581                         usb_unlink_urb(hdw->ctl_read_urb);
2582                 }
2583         }
2584 }
2585
2586
2587 /* Issue a command and get a response from the device.  This extended
2588    version includes a probe flag (which if set means that device errors
2589    should not be logged or treated as fatal) and a timeout in jiffies.
2590    This can be used to non-lethally probe the health of endpoint 1. */
2591 static int pvr2_send_request_ex(struct pvr2_hdw *hdw,
2592                                 unsigned int timeout,int probe_fl,
2593                                 void *write_data,unsigned int write_len,
2594                                 void *read_data,unsigned int read_len)
2595 {
2596         unsigned int idx;
2597         int status = 0;
2598         struct timer_list timer;
2599         if (!hdw->ctl_lock_held) {
2600                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2601                            "Attempted to execute control transfer"
2602                            " without lock!!");
2603                 return -EDEADLK;
2604         }
2605         if ((!hdw->flag_ok) && !probe_fl) {
2606                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2607                            "Attempted to execute control transfer"
2608                            " when device not ok");
2609                 return -EIO;
2610         }
2611         if (!(hdw->ctl_read_urb && hdw->ctl_write_urb)) {
2612                 if (!probe_fl) {
2613                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2614                                    "Attempted to execute control transfer"
2615                                    " when USB is disconnected");
2616                 }
2617                 return -ENOTTY;
2618         }
2619
2620         /* Ensure that we have sane parameters */
2621         if (!write_data) write_len = 0;
2622         if (!read_data) read_len = 0;
2623         if (write_len > PVR2_CTL_BUFFSIZE) {
2624                 pvr2_trace(
2625                         PVR2_TRACE_ERROR_LEGS,
2626                         "Attempted to execute %d byte"
2627                         " control-write transfer (limit=%d)",
2628                         write_len,PVR2_CTL_BUFFSIZE);
2629                 return -EINVAL;
2630         }
2631         if (read_len > PVR2_CTL_BUFFSIZE) {
2632                 pvr2_trace(
2633                         PVR2_TRACE_ERROR_LEGS,
2634                         "Attempted to execute %d byte"
2635                         " control-read transfer (limit=%d)",
2636                         write_len,PVR2_CTL_BUFFSIZE);
2637                 return -EINVAL;
2638         }
2639         if ((!write_len) && (!read_len)) {
2640                 pvr2_trace(
2641                         PVR2_TRACE_ERROR_LEGS,
2642                         "Attempted to execute null control transfer?");
2643                 return -EINVAL;
2644         }
2645
2646
2647         hdw->cmd_debug_state = 1;
2648         if (write_len) {
2649                 hdw->cmd_debug_code = ((unsigned char *)write_data)[0];
2650         } else {
2651                 hdw->cmd_debug_code = 0;
2652         }
2653         hdw->cmd_debug_write_len = write_len;
2654         hdw->cmd_debug_read_len = read_len;
2655
2656         /* Initialize common stuff */
2657         init_completion(&hdw->ctl_done);
2658         hdw->ctl_timeout_flag = 0;
2659         hdw->ctl_write_pend_flag = 0;
2660         hdw->ctl_read_pend_flag = 0;
2661         init_timer(&timer);
2662         timer.expires = jiffies + timeout;
2663         timer.data = (unsigned long)hdw;
2664         timer.function = pvr2_ctl_timeout;
2665
2666         if (write_len) {
2667                 hdw->cmd_debug_state = 2;
2668                 /* Transfer write data to internal buffer */
2669                 for (idx = 0; idx < write_len; idx++) {
2670                         hdw->ctl_write_buffer[idx] =
2671                                 ((unsigned char *)write_data)[idx];
2672                 }
2673                 /* Initiate a write request */
2674                 usb_fill_bulk_urb(hdw->ctl_write_urb,
2675                                   hdw->usb_dev,
2676                                   usb_sndbulkpipe(hdw->usb_dev,
2677                                                   PVR2_CTL_WRITE_ENDPOINT),
2678                                   hdw->ctl_write_buffer,
2679                                   write_len,
2680                                   pvr2_ctl_write_complete,
2681                                   hdw);
2682                 hdw->ctl_write_urb->actual_length = 0;
2683                 hdw->ctl_write_pend_flag = !0;
2684                 status = usb_submit_urb(hdw->ctl_write_urb,GFP_KERNEL);
2685                 if (status < 0) {
2686                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2687                                    "Failed to submit write-control"
2688                                    " URB status=%d",status);
2689                         hdw->ctl_write_pend_flag = 0;
2690                         goto done;
2691                 }
2692         }
2693
2694         if (read_len) {
2695                 hdw->cmd_debug_state = 3;
2696                 memset(hdw->ctl_read_buffer,0x43,read_len);
2697                 /* Initiate a read request */
2698                 usb_fill_bulk_urb(hdw->ctl_read_urb,
2699                                   hdw->usb_dev,
2700                                   usb_rcvbulkpipe(hdw->usb_dev,
2701                                                   PVR2_CTL_READ_ENDPOINT),
2702                                   hdw->ctl_read_buffer,
2703                                   read_len,
2704                                   pvr2_ctl_read_complete,
2705                                   hdw);
2706                 hdw->ctl_read_urb->actual_length = 0;
2707                 hdw->ctl_read_pend_flag = !0;
2708                 status = usb_submit_urb(hdw->ctl_read_urb,GFP_KERNEL);
2709                 if (status < 0) {
2710                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2711                                    "Failed to submit read-control"
2712                                    " URB status=%d",status);
2713                         hdw->ctl_read_pend_flag = 0;
2714                         goto done;
2715                 }
2716         }
2717
2718         /* Start timer */
2719         add_timer(&timer);
2720
2721         /* Now wait for all I/O to complete */
2722         hdw->cmd_debug_state = 4;
2723         while (hdw->ctl_write_pend_flag || hdw->ctl_read_pend_flag) {
2724                 wait_for_completion(&hdw->ctl_done);
2725         }
2726         hdw->cmd_debug_state = 5;
2727
2728         /* Stop timer */
2729         del_timer_sync(&timer);
2730
2731         hdw->cmd_debug_state = 6;
2732         status = 0;
2733
2734         if (hdw->ctl_timeout_flag) {
2735                 status = -ETIMEDOUT;
2736                 if (!probe_fl) {
2737                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2738                                    "Timed out control-write");
2739                 }
2740                 goto done;
2741         }
2742
2743         if (write_len) {
2744                 /* Validate results of write request */
2745                 if ((hdw->ctl_write_urb->status != 0) &&
2746                     (hdw->ctl_write_urb->status != -ENOENT) &&
2747                     (hdw->ctl_write_urb->status != -ESHUTDOWN) &&
2748                     (hdw->ctl_write_urb->status != -ECONNRESET)) {
2749                         /* USB subsystem is reporting some kind of failure
2750                            on the write */
2751                         status = hdw->ctl_write_urb->status;
2752                         if (!probe_fl) {
2753                                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2754                                            "control-write URB failure,"
2755                                            " status=%d",
2756                                            status);
2757                         }
2758                         goto done;
2759                 }
2760                 if (hdw->ctl_write_urb->actual_length < write_len) {
2761                         /* Failed to write enough data */
2762                         status = -EIO;
2763                         if (!probe_fl) {
2764                                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2765                                            "control-write URB short,"
2766                                            " expected=%d got=%d",
2767                                            write_len,
2768                                            hdw->ctl_write_urb->actual_length);
2769                         }
2770                         goto done;
2771                 }
2772         }
2773         if (read_len) {
2774                 /* Validate results of read request */
2775                 if ((hdw->ctl_read_urb->status != 0) &&
2776                     (hdw->ctl_read_urb->status != -ENOENT) &&
2777                     (hdw->ctl_read_urb->status != -ESHUTDOWN) &&
2778                     (hdw->ctl_read_urb->status != -ECONNRESET)) {
2779                         /* USB subsystem is reporting some kind of failure
2780                            on the read */
2781                         status = hdw->ctl_read_urb->status;
2782                         if (!probe_fl) {
2783                                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2784                                            "control-read URB failure,"
2785                                            " status=%d",
2786                                            status);
2787                         }
2788                         goto done;
2789                 }
2790                 if (hdw->ctl_read_urb->actual_length < read_len) {
2791                         /* Failed to read enough data */
2792                         status = -EIO;
2793                         if (!probe_fl) {
2794                                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2795                                            "control-read URB short,"
2796                                            " expected=%d got=%d",
2797                                            read_len,
2798                                            hdw->ctl_read_urb->actual_length);
2799                         }
2800                         goto done;
2801                 }
2802                 /* Transfer retrieved data out from internal buffer */
2803                 for (idx = 0; idx < read_len; idx++) {
2804                         ((unsigned char *)read_data)[idx] =
2805                                 hdw->ctl_read_buffer[idx];
2806                 }
2807         }
2808
2809  done:
2810
2811         hdw->cmd_debug_state = 0;
2812         if ((status < 0) && (!probe_fl)) {
2813                 pvr2_hdw_render_useless_unlocked(hdw);
2814         }
2815         return status;
2816 }
2817
2818
2819 int pvr2_send_request(struct pvr2_hdw *hdw,
2820                       void *write_data,unsigned int write_len,
2821                       void *read_data,unsigned int read_len)
2822 {
2823         return pvr2_send_request_ex(hdw,HZ*4,0,
2824                                     write_data,write_len,
2825                                     read_data,read_len);
2826 }
2827
2828 int pvr2_write_register(struct pvr2_hdw *hdw, u16 reg, u32 data)
2829 {
2830         int ret;
2831
2832         LOCK_TAKE(hdw->ctl_lock);
2833
2834         hdw->cmd_buffer[0] = 0x04;  /* write register prefix */
2835         PVR2_DECOMPOSE_LE(hdw->cmd_buffer,1,data);
2836         hdw->cmd_buffer[5] = 0;
2837         hdw->cmd_buffer[6] = (reg >> 8) & 0xff;
2838         hdw->cmd_buffer[7] = reg & 0xff;
2839
2840
2841         ret = pvr2_send_request(hdw, hdw->cmd_buffer, 8, hdw->cmd_buffer, 0);
2842
2843         LOCK_GIVE(hdw->ctl_lock);
2844
2845         return ret;
2846 }
2847
2848
2849 static int pvr2_read_register(struct pvr2_hdw *hdw, u16 reg, u32 *data)
2850 {
2851         int ret = 0;
2852
2853         LOCK_TAKE(hdw->ctl_lock);
2854
2855         hdw->cmd_buffer[0] = 0x05;  /* read register prefix */
2856         hdw->cmd_buffer[1] = 0;
2857         hdw->cmd_buffer[2] = 0;
2858         hdw->cmd_buffer[3] = 0;
2859         hdw->cmd_buffer[4] = 0;
2860         hdw->cmd_buffer[5] = 0;
2861         hdw->cmd_buffer[6] = (reg >> 8) & 0xff;
2862         hdw->cmd_buffer[7] = reg & 0xff;
2863
2864         ret |= pvr2_send_request(hdw, hdw->cmd_buffer, 8, hdw->cmd_buffer, 4);
2865         *data = PVR2_COMPOSE_LE(hdw->cmd_buffer,0);
2866
2867         LOCK_GIVE(hdw->ctl_lock);
2868
2869         return ret;
2870 }
2871
2872
2873 static int pvr2_write_u16(struct pvr2_hdw *hdw, u16 data, int res)
2874 {
2875         int ret;
2876
2877         LOCK_TAKE(hdw->ctl_lock);
2878
2879         hdw->cmd_buffer[0] = (data >> 8) & 0xff;
2880         hdw->cmd_buffer[1] = data & 0xff;
2881
2882         ret = pvr2_send_request(hdw, hdw->cmd_buffer, 2, hdw->cmd_buffer, res);
2883
2884         LOCK_GIVE(hdw->ctl_lock);
2885
2886         return ret;
2887 }
2888
2889
2890 static int pvr2_write_u8(struct pvr2_hdw *hdw, u8 data, int res)
2891 {
2892         int ret;
2893
2894         LOCK_TAKE(hdw->ctl_lock);
2895
2896         hdw->cmd_buffer[0] = data;
2897
2898         ret = pvr2_send_request(hdw, hdw->cmd_buffer, 1, hdw->cmd_buffer, res);
2899
2900         LOCK_GIVE(hdw->ctl_lock);
2901
2902         return ret;
2903 }
2904
2905
2906 static void pvr2_hdw_render_useless_unlocked(struct pvr2_hdw *hdw)
2907 {
2908         if (!hdw->flag_ok) return;
2909         pvr2_trace(PVR2_TRACE_INIT,"render_useless");
2910         hdw->flag_ok = 0;
2911         if (hdw->vid_stream) {
2912                 pvr2_stream_setup(hdw->vid_stream,NULL,0,0);
2913         }
2914         hdw->flag_streaming_enabled = 0;
2915         hdw->subsys_enabled_mask = 0;
2916 }
2917
2918
2919 void pvr2_hdw_render_useless(struct pvr2_hdw *hdw)
2920 {
2921         LOCK_TAKE(hdw->ctl_lock);
2922         pvr2_hdw_render_useless_unlocked(hdw);
2923         LOCK_GIVE(hdw->ctl_lock);
2924 }
2925
2926
2927 void pvr2_hdw_device_reset(struct pvr2_hdw *hdw)
2928 {
2929         int ret;
2930         pvr2_trace(PVR2_TRACE_INIT,"Performing a device reset...");
2931         ret = usb_lock_device_for_reset(hdw->usb_dev,NULL);
2932         if (ret == 1) {
2933                 ret = usb_reset_device(hdw->usb_dev);
2934                 usb_unlock_device(hdw->usb_dev);
2935         } else {
2936                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2937                            "Failed to lock USB device ret=%d",ret);
2938         }
2939         if (init_pause_msec) {
2940                 pvr2_trace(PVR2_TRACE_INFO,
2941                            "Waiting %u msec for hardware to settle",
2942                            init_pause_msec);
2943                 msleep(init_pause_msec);
2944         }
2945
2946 }
2947
2948
2949 void pvr2_hdw_cpureset_assert(struct pvr2_hdw *hdw,int val)
2950 {
2951         char da[1];
2952         unsigned int pipe;
2953         int ret;
2954
2955         if (!hdw->usb_dev) return;
2956
2957         pvr2_trace(PVR2_TRACE_INIT,"cpureset_assert(%d)",val);
2958
2959         da[0] = val ? 0x01 : 0x00;
2960
2961         /* Write the CPUCS register on the 8051.  The lsb of the register
2962            is the reset bit; a 1 asserts reset while a 0 clears it. */
2963         pipe = usb_sndctrlpipe(hdw->usb_dev, 0);
2964         ret = usb_control_msg(hdw->usb_dev,pipe,0xa0,0x40,0xe600,0,da,1,HZ);
2965         if (ret < 0) {
2966                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2967                            "cpureset_assert(%d) error=%d",val,ret);
2968                 pvr2_hdw_render_useless(hdw);
2969         }
2970 }
2971
2972
2973 int pvr2_hdw_cmd_deep_reset(struct pvr2_hdw *hdw)
2974 {
2975         int status;
2976         LOCK_TAKE(hdw->ctl_lock); do {
2977                 pvr2_trace(PVR2_TRACE_INIT,"Requesting uproc hard reset");
2978                 hdw->flag_ok = !0;
2979                 hdw->cmd_buffer[0] = 0xdd;
2980                 status = pvr2_send_request(hdw,hdw->cmd_buffer,1,NULL,0);
2981         } while (0); LOCK_GIVE(hdw->ctl_lock);
2982         return status;
2983 }
2984
2985
2986 int pvr2_hdw_cmd_powerup(struct pvr2_hdw *hdw)
2987 {
2988         int status;
2989         LOCK_TAKE(hdw->ctl_lock); do {
2990                 pvr2_trace(PVR2_TRACE_INIT,"Requesting powerup");
2991                 hdw->cmd_buffer[0] = 0xde;
2992                 status = pvr2_send_request(hdw,hdw->cmd_buffer,1,NULL,0);
2993         } while (0); LOCK_GIVE(hdw->ctl_lock);
2994         return status;
2995 }
2996
2997
2998 int pvr2_hdw_cmd_decoder_reset(struct pvr2_hdw *hdw)
2999 {
3000         if (!hdw->decoder_ctrl) {
3001                 pvr2_trace(PVR2_TRACE_INIT,
3002                            "Unable to reset decoder: nothing attached");
3003                 return -ENOTTY;
3004         }
3005
3006         if (!hdw->decoder_ctrl->force_reset) {
3007                 pvr2_trace(PVR2_TRACE_INIT,
3008                            "Unable to reset decoder: not implemented");
3009                 return -ENOTTY;
3010         }
3011
3012         pvr2_trace(PVR2_TRACE_INIT,
3013                    "Requesting decoder reset");
3014         hdw->decoder_ctrl->force_reset(hdw->decoder_ctrl->ctxt);
3015         return 0;
3016 }
3017
3018
3019 /* Stop / start video stream transport */
3020 static int pvr2_hdw_cmd_usbstream(struct pvr2_hdw *hdw,int runFl)
3021 {
3022         int status;
3023         LOCK_TAKE(hdw->ctl_lock); do {
3024                 hdw->cmd_buffer[0] = (runFl ? 0x36 : 0x37);
3025                 status = pvr2_send_request(hdw,hdw->cmd_buffer,1,NULL,0);
3026         } while (0); LOCK_GIVE(hdw->ctl_lock);
3027         if (!status) {
3028                 hdw->subsys_enabled_mask =
3029                         ((hdw->subsys_enabled_mask &
3030                           ~(1<<PVR2_SUBSYS_B_USBSTREAM_RUN)) |
3031                          (runFl ? (1<<PVR2_SUBSYS_B_USBSTREAM_RUN) : 0));
3032         }
3033         return status;
3034 }
3035
3036
3037 void pvr2_hdw_get_debug_info(const struct pvr2_hdw *hdw,
3038                              struct pvr2_hdw_debug_info *ptr)
3039 {
3040         ptr->big_lock_held = hdw->big_lock_held;
3041         ptr->ctl_lock_held = hdw->ctl_lock_held;
3042         ptr->flag_ok = hdw->flag_ok;
3043         ptr->flag_disconnected = hdw->flag_disconnected;
3044         ptr->flag_init_ok = hdw->flag_init_ok;
3045         ptr->flag_streaming_enabled = hdw->flag_streaming_enabled;
3046         ptr->subsys_flags = hdw->subsys_enabled_mask;
3047         ptr->cmd_debug_state = hdw->cmd_debug_state;
3048         ptr->cmd_code = hdw->cmd_debug_code;
3049         ptr->cmd_debug_write_len = hdw->cmd_debug_write_len;
3050         ptr->cmd_debug_read_len = hdw->cmd_debug_read_len;
3051         ptr->cmd_debug_timeout = hdw->ctl_timeout_flag;
3052         ptr->cmd_debug_write_pend = hdw->ctl_write_pend_flag;
3053         ptr->cmd_debug_read_pend = hdw->ctl_read_pend_flag;
3054         ptr->cmd_debug_rstatus = hdw->ctl_read_urb->status;
3055         ptr->cmd_debug_wstatus = hdw->ctl_read_urb->status;
3056 }
3057
3058
3059 int pvr2_hdw_gpio_get_dir(struct pvr2_hdw *hdw,u32 *dp)
3060 {
3061         return pvr2_read_register(hdw,PVR2_GPIO_DIR,dp);
3062 }
3063
3064
3065 int pvr2_hdw_gpio_get_out(struct pvr2_hdw *hdw,u32 *dp)
3066 {
3067         return pvr2_read_register(hdw,PVR2_GPIO_OUT,dp);
3068 }
3069
3070
3071 int pvr2_hdw_gpio_get_in(struct pvr2_hdw *hdw,u32 *dp)
3072 {
3073         return pvr2_read_register(hdw,PVR2_GPIO_IN,dp);
3074 }
3075
3076
3077 int pvr2_hdw_gpio_chg_dir(struct pvr2_hdw *hdw,u32 msk,u32 val)
3078 {
3079         u32 cval,nval;
3080         int ret;
3081         if (~msk) {
3082                 ret = pvr2_read_register(hdw,PVR2_GPIO_DIR,&cval);
3083                 if (ret) return ret;
3084                 nval = (cval & ~msk) | (val & msk);
3085                 pvr2_trace(PVR2_TRACE_GPIO,
3086                            "GPIO direction changing 0x%x:0x%x"
3087                            " from 0x%x to 0x%x",
3088                            msk,val,cval,nval);
3089         } else {
3090                 nval = val;
3091                 pvr2_trace(PVR2_TRACE_GPIO,
3092                            "GPIO direction changing to 0x%x",nval);
3093         }
3094         return pvr2_write_register(hdw,PVR2_GPIO_DIR,nval);
3095 }
3096
3097
3098 int pvr2_hdw_gpio_chg_out(struct pvr2_hdw *hdw,u32 msk,u32 val)
3099 {
3100         u32 cval,nval;
3101         int ret;
3102         if (~msk) {
3103                 ret = pvr2_read_register(hdw,PVR2_GPIO_OUT,&cval);
3104                 if (ret) return ret;
3105                 nval = (cval & ~msk) | (val & msk);
3106                 pvr2_trace(PVR2_TRACE_GPIO,
3107                            "GPIO output changing 0x%x:0x%x from 0x%x to 0x%x",
3108                            msk,val,cval,nval);
3109         } else {
3110                 nval = val;
3111                 pvr2_trace(PVR2_TRACE_GPIO,
3112                            "GPIO output changing to 0x%x",nval);
3113         }
3114         return pvr2_write_register(hdw,PVR2_GPIO_OUT,nval);
3115 }
3116
3117
3118 /* Find I2C address of eeprom */
3119 static int pvr2_hdw_get_eeprom_addr(struct pvr2_hdw *hdw)
3120 {
3121         int result;
3122         LOCK_TAKE(hdw->ctl_lock); do {
3123                 hdw->cmd_buffer[0] = 0xeb;
3124                 result = pvr2_send_request(hdw,
3125                                            hdw->cmd_buffer,1,
3126                                            hdw->cmd_buffer,1);
3127                 if (result < 0) break;
3128                 result = hdw->cmd_buffer[0];
3129         } while(0); LOCK_GIVE(hdw->ctl_lock);
3130         return result;
3131 }
3132
3133
3134 /*
3135   Stuff for Emacs to see, in order to encourage consistent editing style:
3136   *** Local Variables: ***
3137   *** mode: c ***
3138   *** fill-column: 75 ***
3139   *** tab-width: 8 ***
3140   *** c-basic-offset: 8 ***
3141   *** End: ***
3142   */