5 * Copyright (C) 2005 Mike Isely <isely@pobox.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 #include <linux/errno.h>
23 #include <linux/string.h>
24 #include <linux/slab.h>
25 #include <linux/firmware.h>
26 #include <linux/videodev2.h>
27 #include <media/v4l2-common.h>
28 #include <asm/semaphore.h>
30 #include "pvrusb2-std.h"
31 #include "pvrusb2-util.h"
32 #include "pvrusb2-hdw.h"
33 #include "pvrusb2-i2c-core.h"
34 #include "pvrusb2-tuner.h"
35 #include "pvrusb2-eeprom.h"
36 #include "pvrusb2-hdw-internal.h"
37 #include "pvrusb2-encoder.h"
38 #include "pvrusb2-debug.h"
40 #define TV_MIN_FREQ 55250000L
41 #define TV_MAX_FREQ 850000000L
43 #define RADIO_MIN_FREQ 1392000L //87MHz
44 #define RADIO_MAX_FREQ 1728000L //108MHz
46 struct usb_device_id pvr2_device_table[] = {
47 [PVR2_HDW_TYPE_29XXX] = { USB_DEVICE(0x2040, 0x2900) },
48 [PVR2_HDW_TYPE_24XXX] = { USB_DEVICE(0x2040, 0x2400) },
52 MODULE_DEVICE_TABLE(usb, pvr2_device_table);
54 static const char *pvr2_device_names[] = {
55 [PVR2_HDW_TYPE_29XXX] = "WinTV PVR USB2 Model Category 29xxxx",
56 [PVR2_HDW_TYPE_24XXX] = "WinTV PVR USB2 Model Category 24xxxx",
59 struct pvr2_string_table {
64 // Names of other client modules to request for 24xxx model hardware
65 static const char *pvr2_client_24xxx[] = {
71 // Names of other client modules to request for 29xxx model hardware
72 static const char *pvr2_client_29xxx[] = {
78 static struct pvr2_string_table pvr2_client_lists[] = {
79 [PVR2_HDW_TYPE_29XXX] = {
81 sizeof(pvr2_client_29xxx)/sizeof(pvr2_client_29xxx[0]),
83 [PVR2_HDW_TYPE_24XXX] = {
85 sizeof(pvr2_client_24xxx)/sizeof(pvr2_client_24xxx[0]),
89 static struct pvr2_hdw *unit_pointers[PVR_NUM] = {[ 0 ... PVR_NUM-1 ] = NULL};
90 static DECLARE_MUTEX(pvr2_unit_sem);
92 static int ctlchg = 0;
93 static int initusbreset = 1;
94 static int procreload = 0;
95 static int tuner[PVR_NUM] = { [0 ... PVR_NUM-1] = -1 };
96 static int tolerance[PVR_NUM] = { [0 ... PVR_NUM-1] = 0 };
97 static int video_std[PVR_NUM] = { [0 ... PVR_NUM-1] = 0 };
98 static int init_pause_msec = 0;
100 module_param(ctlchg, int, S_IRUGO|S_IWUSR);
101 MODULE_PARM_DESC(ctlchg, "0=optimize ctl change 1=always accept new ctl value");
102 module_param(init_pause_msec, int, S_IRUGO|S_IWUSR);
103 MODULE_PARM_DESC(init_pause_msec, "hardware initialization settling delay");
104 module_param(initusbreset, int, S_IRUGO|S_IWUSR);
105 MODULE_PARM_DESC(initusbreset, "Do USB reset device on probe");
106 module_param(procreload, int, S_IRUGO|S_IWUSR);
107 MODULE_PARM_DESC(procreload,
108 "Attempt init failure recovery with firmware reload");
109 module_param_array(tuner, int, NULL, 0444);
110 MODULE_PARM_DESC(tuner,"specify installed tuner type");
111 module_param_array(video_std, int, NULL, 0444);
112 MODULE_PARM_DESC(video_std,"specify initial video standard");
113 module_param_array(tolerance, int, NULL, 0444);
114 MODULE_PARM_DESC(tolerance,"specify stream error tolerance");
116 #define PVR2_CTL_WRITE_ENDPOINT 0x01
117 #define PVR2_CTL_READ_ENDPOINT 0x81
119 #define PVR2_GPIO_IN 0x9008
120 #define PVR2_GPIO_OUT 0x900c
121 #define PVR2_GPIO_DIR 0x9020
123 #define trace_firmware(...) pvr2_trace(PVR2_TRACE_FIRMWARE,__VA_ARGS__)
125 #define PVR2_FIRMWARE_ENDPOINT 0x02
127 /* size of a firmware chunk */
128 #define FIRMWARE_CHUNK_SIZE 0x2000
130 /* Define the list of additional controls we'll dynamically construct based
131 on query of the cx2341x module. */
132 struct pvr2_mpeg_ids {
136 static const struct pvr2_mpeg_ids mpeg_ids[] = {
138 .strid = "audio_layer",
139 .id = V4L2_CID_MPEG_AUDIO_ENCODING,
141 .strid = "audio_bitrate",
142 .id = V4L2_CID_MPEG_AUDIO_L2_BITRATE,
144 /* Already using audio_mode elsewhere :-( */
145 .strid = "mpeg_audio_mode",
146 .id = V4L2_CID_MPEG_AUDIO_MODE,
148 .strid = "mpeg_audio_mode_extension",
149 .id = V4L2_CID_MPEG_AUDIO_MODE_EXTENSION,
151 .strid = "audio_emphasis",
152 .id = V4L2_CID_MPEG_AUDIO_EMPHASIS,
154 .strid = "audio_crc",
155 .id = V4L2_CID_MPEG_AUDIO_CRC,
157 .strid = "video_aspect",
158 .id = V4L2_CID_MPEG_VIDEO_ASPECT,
160 .strid = "video_b_frames",
161 .id = V4L2_CID_MPEG_VIDEO_B_FRAMES,
163 .strid = "video_gop_size",
164 .id = V4L2_CID_MPEG_VIDEO_GOP_SIZE,
166 .strid = "video_gop_closure",
167 .id = V4L2_CID_MPEG_VIDEO_GOP_CLOSURE,
169 .strid = "video_bitrate_mode",
170 .id = V4L2_CID_MPEG_VIDEO_BITRATE_MODE,
172 .strid = "video_bitrate",
173 .id = V4L2_CID_MPEG_VIDEO_BITRATE,
175 .strid = "video_bitrate_peak",
176 .id = V4L2_CID_MPEG_VIDEO_BITRATE_PEAK,
178 .strid = "video_temporal_decimation",
179 .id = V4L2_CID_MPEG_VIDEO_TEMPORAL_DECIMATION,
181 .strid = "stream_type",
182 .id = V4L2_CID_MPEG_STREAM_TYPE,
184 .strid = "video_spatial_filter_mode",
185 .id = V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER_MODE,
187 .strid = "video_spatial_filter",
188 .id = V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER,
190 .strid = "video_luma_spatial_filter_type",
191 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_SPATIAL_FILTER_TYPE,
193 .strid = "video_chroma_spatial_filter_type",
194 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_SPATIAL_FILTER_TYPE,
196 .strid = "video_temporal_filter_mode",
197 .id = V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER_MODE,
199 .strid = "video_temporal_filter",
200 .id = V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER,
202 .strid = "video_median_filter_type",
203 .id = V4L2_CID_MPEG_CX2341X_VIDEO_MEDIAN_FILTER_TYPE,
205 .strid = "video_luma_median_filter_top",
206 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_TOP,
208 .strid = "video_luma_median_filter_bottom",
209 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_BOTTOM,
211 .strid = "video_chroma_median_filter_top",
212 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_TOP,
214 .strid = "video_chroma_median_filter_bottom",
215 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_BOTTOM,
218 #define MPEGDEF_COUNT (sizeof(mpeg_ids)/sizeof(mpeg_ids[0]))
221 static const char *control_values_srate[] = {
222 [V4L2_MPEG_AUDIO_SAMPLING_FREQ_44100] = "44.1 kHz",
223 [V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000] = "48 kHz",
224 [V4L2_MPEG_AUDIO_SAMPLING_FREQ_32000] = "32 kHz",
229 static const char *control_values_input[] = {
230 [PVR2_CVAL_INPUT_TV] = "television", /*xawtv needs this name*/
231 [PVR2_CVAL_INPUT_RADIO] = "radio",
232 [PVR2_CVAL_INPUT_SVIDEO] = "s-video",
233 [PVR2_CVAL_INPUT_COMPOSITE] = "composite",
237 static const char *control_values_audiomode[] = {
238 [V4L2_TUNER_MODE_MONO] = "Mono",
239 [V4L2_TUNER_MODE_STEREO] = "Stereo",
240 [V4L2_TUNER_MODE_LANG1] = "Lang1",
241 [V4L2_TUNER_MODE_LANG2] = "Lang2",
242 [V4L2_TUNER_MODE_LANG1_LANG2] = "Lang1+Lang2",
246 static const char *control_values_hsm[] = {
247 [PVR2_CVAL_HSM_FAIL] = "Fail",
248 [PVR2_CVAL_HSM_HIGH] = "High",
249 [PVR2_CVAL_HSM_FULL] = "Full",
253 static const char *control_values_subsystem[] = {
254 [PVR2_SUBSYS_B_ENC_FIRMWARE] = "enc_firmware",
255 [PVR2_SUBSYS_B_ENC_CFG] = "enc_config",
256 [PVR2_SUBSYS_B_DIGITIZER_RUN] = "digitizer_run",
257 [PVR2_SUBSYS_B_USBSTREAM_RUN] = "usbstream_run",
258 [PVR2_SUBSYS_B_ENC_RUN] = "enc_run",
261 static int pvr2_hdw_cmd_usbstream(struct pvr2_hdw *hdw,int runFl);
262 static int pvr2_hdw_commit_ctl_internal(struct pvr2_hdw *hdw);
263 static int pvr2_hdw_get_eeprom_addr(struct pvr2_hdw *hdw);
264 static unsigned int pvr2_hdw_get_signal_status_internal(struct pvr2_hdw *hdw);
265 static void pvr2_hdw_internal_find_stdenum(struct pvr2_hdw *hdw);
266 static void pvr2_hdw_internal_set_std_avail(struct pvr2_hdw *hdw);
267 static void pvr2_hdw_render_useless_unlocked(struct pvr2_hdw *hdw);
268 static void pvr2_hdw_subsys_bit_chg_no_lock(struct pvr2_hdw *hdw,
271 static void pvr2_hdw_subsys_stream_bit_chg_no_lock(struct pvr2_hdw *hdw,
274 static int pvr2_send_request_ex(struct pvr2_hdw *hdw,
275 unsigned int timeout,int probe_fl,
276 void *write_data,unsigned int write_len,
277 void *read_data,unsigned int read_len);
278 static int pvr2_write_u16(struct pvr2_hdw *hdw, u16 data, int res);
279 static int pvr2_write_u8(struct pvr2_hdw *hdw, u8 data, int res);
281 static int ctrl_channelfreq_get(struct pvr2_ctrl *cptr,int *vp)
283 struct pvr2_hdw *hdw = cptr->hdw;
284 if ((hdw->freqProgSlot > 0) && (hdw->freqProgSlot <= FREQTABLE_SIZE)) {
285 *vp = hdw->freqTable[hdw->freqProgSlot-1];
292 static int ctrl_channelfreq_set(struct pvr2_ctrl *cptr,int m,int v)
294 struct pvr2_hdw *hdw = cptr->hdw;
295 if ((hdw->freqProgSlot > 0) && (hdw->freqProgSlot <= FREQTABLE_SIZE)) {
296 hdw->freqTable[hdw->freqProgSlot-1] = v;
301 static int ctrl_channelprog_get(struct pvr2_ctrl *cptr,int *vp)
303 *vp = cptr->hdw->freqProgSlot;
307 static int ctrl_channelprog_set(struct pvr2_ctrl *cptr,int m,int v)
309 struct pvr2_hdw *hdw = cptr->hdw;
310 if ((v >= 0) && (v <= FREQTABLE_SIZE)) {
311 hdw->freqProgSlot = v;
316 static int ctrl_channel_get(struct pvr2_ctrl *cptr,int *vp)
318 *vp = cptr->hdw->freqSlot;
322 static int ctrl_channel_set(struct pvr2_ctrl *cptr,int m,int v)
325 struct pvr2_hdw *hdw = cptr->hdw;
327 if ((hdw->freqSlot > 0) && (hdw->freqSlot <= FREQTABLE_SIZE)) {
328 freq = hdw->freqTable[hdw->freqSlot-1];
330 if (freq && (freq != hdw->freqVal)) {
337 static int ctrl_freq_get(struct pvr2_ctrl *cptr,int *vp)
339 *vp = cptr->hdw->freqVal;
343 static int ctrl_freq_is_dirty(struct pvr2_ctrl *cptr)
345 return cptr->hdw->freqDirty != 0;
348 static void ctrl_freq_clear_dirty(struct pvr2_ctrl *cptr)
350 cptr->hdw->freqDirty = 0;
353 static int ctrl_freq_set(struct pvr2_ctrl *cptr,int m,int v)
355 struct pvr2_hdw *hdw = cptr->hdw;
362 static int ctrl_vres_max_get(struct pvr2_ctrl *cptr,int *vp)
364 /* Actual maximum depends on the video standard in effect. */
365 if (cptr->hdw->std_mask_cur & V4L2_STD_525_60) {
373 static int ctrl_vres_min_get(struct pvr2_ctrl *cptr,int *vp)
375 /* Actual minimum depends on device type. */
376 if (cptr->hdw->hdw_type == PVR2_HDW_TYPE_24XXX) {
384 static int ctrl_freq_max_get(struct pvr2_ctrl *cptr, int *vp)
386 /* Actual maximum depends on radio/tv mode */
387 if (cptr->hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
388 *vp = RADIO_MAX_FREQ;
395 static int ctrl_freq_min_get(struct pvr2_ctrl *cptr, int *vp)
397 /* Actual minimum depends on radio/tv mode */
398 if (cptr->hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
399 *vp = RADIO_MIN_FREQ;
406 static int ctrl_cx2341x_is_dirty(struct pvr2_ctrl *cptr)
408 return cptr->hdw->enc_stale != 0;
411 static void ctrl_cx2341x_clear_dirty(struct pvr2_ctrl *cptr)
413 cptr->hdw->enc_stale = 0;
416 static int ctrl_cx2341x_get(struct pvr2_ctrl *cptr,int *vp)
419 struct v4l2_ext_controls cs;
420 struct v4l2_ext_control c1;
421 memset(&cs,0,sizeof(cs));
422 memset(&c1,0,sizeof(c1));
425 c1.id = cptr->info->v4l_id;
426 ret = cx2341x_ext_ctrls(&cptr->hdw->enc_ctl_state,&cs,
433 static int ctrl_cx2341x_set(struct pvr2_ctrl *cptr,int m,int v)
436 struct v4l2_ext_controls cs;
437 struct v4l2_ext_control c1;
438 memset(&cs,0,sizeof(cs));
439 memset(&c1,0,sizeof(c1));
442 c1.id = cptr->info->v4l_id;
444 ret = cx2341x_ext_ctrls(&cptr->hdw->enc_ctl_state,&cs,
447 cptr->hdw->enc_stale = !0;
451 static unsigned int ctrl_cx2341x_getv4lflags(struct pvr2_ctrl *cptr)
453 struct v4l2_queryctrl qctrl;
454 struct pvr2_ctl_info *info;
455 qctrl.id = cptr->info->v4l_id;
456 cx2341x_ctrl_query(&cptr->hdw->enc_ctl_state,&qctrl);
457 /* Strip out the const so we can adjust a function pointer. It's
458 OK to do this here because we know this is a dynamically created
459 control, so the underlying storage for the info pointer is (a)
460 private to us, and (b) not in read-only storage. Either we do
461 this or we significantly complicate the underlying control
463 info = (struct pvr2_ctl_info *)(cptr->info);
464 if (qctrl.flags & V4L2_CTRL_FLAG_READ_ONLY) {
465 if (info->set_value) {
466 info->set_value = NULL;
469 if (!(info->set_value)) {
470 info->set_value = ctrl_cx2341x_set;
476 static int ctrl_streamingenabled_get(struct pvr2_ctrl *cptr,int *vp)
478 *vp = cptr->hdw->flag_streaming_enabled;
482 static int ctrl_hsm_get(struct pvr2_ctrl *cptr,int *vp)
484 int result = pvr2_hdw_is_hsm(cptr->hdw);
485 *vp = PVR2_CVAL_HSM_FULL;
486 if (result < 0) *vp = PVR2_CVAL_HSM_FAIL;
487 if (result) *vp = PVR2_CVAL_HSM_HIGH;
491 static int ctrl_stdavail_get(struct pvr2_ctrl *cptr,int *vp)
493 *vp = cptr->hdw->std_mask_avail;
497 static int ctrl_stdavail_set(struct pvr2_ctrl *cptr,int m,int v)
499 struct pvr2_hdw *hdw = cptr->hdw;
501 ns = hdw->std_mask_avail;
502 ns = (ns & ~m) | (v & m);
503 if (ns == hdw->std_mask_avail) return 0;
504 hdw->std_mask_avail = ns;
505 pvr2_hdw_internal_set_std_avail(hdw);
506 pvr2_hdw_internal_find_stdenum(hdw);
510 static int ctrl_std_val_to_sym(struct pvr2_ctrl *cptr,int msk,int val,
511 char *bufPtr,unsigned int bufSize,
514 *len = pvr2_std_id_to_str(bufPtr,bufSize,msk & val);
518 static int ctrl_std_sym_to_val(struct pvr2_ctrl *cptr,
519 const char *bufPtr,unsigned int bufSize,
524 ret = pvr2_std_str_to_id(&id,bufPtr,bufSize);
525 if (ret < 0) return ret;
526 if (mskp) *mskp = id;
527 if (valp) *valp = id;
531 static int ctrl_stdcur_get(struct pvr2_ctrl *cptr,int *vp)
533 *vp = cptr->hdw->std_mask_cur;
537 static int ctrl_stdcur_set(struct pvr2_ctrl *cptr,int m,int v)
539 struct pvr2_hdw *hdw = cptr->hdw;
541 ns = hdw->std_mask_cur;
542 ns = (ns & ~m) | (v & m);
543 if (ns == hdw->std_mask_cur) return 0;
544 hdw->std_mask_cur = ns;
546 pvr2_hdw_internal_find_stdenum(hdw);
550 static int ctrl_stdcur_is_dirty(struct pvr2_ctrl *cptr)
552 return cptr->hdw->std_dirty != 0;
555 static void ctrl_stdcur_clear_dirty(struct pvr2_ctrl *cptr)
557 cptr->hdw->std_dirty = 0;
560 static int ctrl_signal_get(struct pvr2_ctrl *cptr,int *vp)
562 *vp = ((pvr2_hdw_get_signal_status_internal(cptr->hdw) &
563 PVR2_SIGNAL_OK) ? 1 : 0);
567 static int ctrl_subsys_get(struct pvr2_ctrl *cptr,int *vp)
569 *vp = cptr->hdw->subsys_enabled_mask;
573 static int ctrl_subsys_set(struct pvr2_ctrl *cptr,int m,int v)
575 pvr2_hdw_subsys_bit_chg_no_lock(cptr->hdw,m,v);
579 static int ctrl_subsys_stream_get(struct pvr2_ctrl *cptr,int *vp)
581 *vp = cptr->hdw->subsys_stream_mask;
585 static int ctrl_subsys_stream_set(struct pvr2_ctrl *cptr,int m,int v)
587 pvr2_hdw_subsys_stream_bit_chg_no_lock(cptr->hdw,m,v);
591 static int ctrl_stdenumcur_set(struct pvr2_ctrl *cptr,int m,int v)
593 struct pvr2_hdw *hdw = cptr->hdw;
594 if (v < 0) return -EINVAL;
595 if (v > hdw->std_enum_cnt) return -EINVAL;
596 hdw->std_enum_cur = v;
599 if (hdw->std_mask_cur == hdw->std_defs[v].id) return 0;
600 hdw->std_mask_cur = hdw->std_defs[v].id;
606 static int ctrl_stdenumcur_get(struct pvr2_ctrl *cptr,int *vp)
608 *vp = cptr->hdw->std_enum_cur;
613 static int ctrl_stdenumcur_is_dirty(struct pvr2_ctrl *cptr)
615 return cptr->hdw->std_dirty != 0;
619 static void ctrl_stdenumcur_clear_dirty(struct pvr2_ctrl *cptr)
621 cptr->hdw->std_dirty = 0;
625 #define DEFINT(vmin,vmax) \
626 .type = pvr2_ctl_int, \
627 .def.type_int.min_value = vmin, \
628 .def.type_int.max_value = vmax
630 #define DEFENUM(tab) \
631 .type = pvr2_ctl_enum, \
632 .def.type_enum.count = (sizeof(tab)/sizeof((tab)[0])), \
633 .def.type_enum.value_names = tab
636 .type = pvr2_ctl_bool
638 #define DEFMASK(msk,tab) \
639 .type = pvr2_ctl_bitmask, \
640 .def.type_bitmask.valid_bits = msk, \
641 .def.type_bitmask.bit_names = tab
643 #define DEFREF(vname) \
644 .set_value = ctrl_set_##vname, \
645 .get_value = ctrl_get_##vname, \
646 .is_dirty = ctrl_isdirty_##vname, \
647 .clear_dirty = ctrl_cleardirty_##vname
650 #define VCREATE_FUNCS(vname) \
651 static int ctrl_get_##vname(struct pvr2_ctrl *cptr,int *vp) \
652 {*vp = cptr->hdw->vname##_val; return 0;} \
653 static int ctrl_set_##vname(struct pvr2_ctrl *cptr,int m,int v) \
654 {cptr->hdw->vname##_val = v; cptr->hdw->vname##_dirty = !0; return 0;} \
655 static int ctrl_isdirty_##vname(struct pvr2_ctrl *cptr) \
656 {return cptr->hdw->vname##_dirty != 0;} \
657 static void ctrl_cleardirty_##vname(struct pvr2_ctrl *cptr) \
658 {cptr->hdw->vname##_dirty = 0;}
660 VCREATE_FUNCS(brightness)
661 VCREATE_FUNCS(contrast)
662 VCREATE_FUNCS(saturation)
664 VCREATE_FUNCS(volume)
665 VCREATE_FUNCS(balance)
667 VCREATE_FUNCS(treble)
670 VCREATE_FUNCS(audiomode)
671 VCREATE_FUNCS(res_hor)
672 VCREATE_FUNCS(res_ver)
675 /* Table definition of all controls which can be manipulated */
676 static const struct pvr2_ctl_info control_defs[] = {
678 .v4l_id = V4L2_CID_BRIGHTNESS,
679 .desc = "Brightness",
680 .name = "brightness",
681 .default_value = 128,
685 .v4l_id = V4L2_CID_CONTRAST,
692 .v4l_id = V4L2_CID_SATURATION,
693 .desc = "Saturation",
694 .name = "saturation",
699 .v4l_id = V4L2_CID_HUE,
706 .v4l_id = V4L2_CID_AUDIO_VOLUME,
709 .default_value = 65535,
713 .v4l_id = V4L2_CID_AUDIO_BALANCE,
718 DEFINT(-32768,32767),
720 .v4l_id = V4L2_CID_AUDIO_BASS,
725 DEFINT(-32768,32767),
727 .v4l_id = V4L2_CID_AUDIO_TREBLE,
732 DEFINT(-32768,32767),
734 .v4l_id = V4L2_CID_AUDIO_MUTE,
741 .desc = "Video Source",
743 .internal_id = PVR2_CID_INPUT,
744 .default_value = PVR2_CVAL_INPUT_TV,
746 DEFENUM(control_values_input),
748 .desc = "Audio Mode",
749 .name = "audio_mode",
750 .internal_id = PVR2_CID_AUDIOMODE,
751 .default_value = V4L2_TUNER_MODE_STEREO,
753 DEFENUM(control_values_audiomode),
755 .desc = "Horizontal capture resolution",
756 .name = "resolution_hor",
757 .internal_id = PVR2_CID_HRES,
758 .default_value = 720,
762 .desc = "Vertical capture resolution",
763 .name = "resolution_ver",
764 .internal_id = PVR2_CID_VRES,
765 .default_value = 480,
768 /* Hook in check for video standard and adjust maximum
769 depending on the standard. */
770 .get_max_value = ctrl_vres_max_get,
771 .get_min_value = ctrl_vres_min_get,
773 .v4l_id = V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ,
774 .default_value = V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000,
775 .desc = "Audio Sampling Frequency",
778 DEFENUM(control_values_srate),
780 .desc = "Tuner Frequency (Hz)",
782 .internal_id = PVR2_CID_FREQUENCY,
783 .default_value = 175250000L,
784 .set_value = ctrl_freq_set,
785 .get_value = ctrl_freq_get,
786 .is_dirty = ctrl_freq_is_dirty,
787 .clear_dirty = ctrl_freq_clear_dirty,
788 DEFINT(TV_MIN_FREQ,TV_MAX_FREQ),
789 /* Hook in check for input value (tv/radio) and adjust
790 max/min values accordingly */
791 .get_max_value = ctrl_freq_max_get,
792 .get_min_value = ctrl_freq_min_get,
796 .set_value = ctrl_channel_set,
797 .get_value = ctrl_channel_get,
798 DEFINT(0,FREQTABLE_SIZE),
800 .desc = "Channel Program Frequency",
801 .name = "freq_table_value",
802 .set_value = ctrl_channelfreq_set,
803 .get_value = ctrl_channelfreq_get,
804 DEFINT(TV_MIN_FREQ,TV_MAX_FREQ),
806 .desc = "Channel Program ID",
807 .name = "freq_table_channel",
808 .set_value = ctrl_channelprog_set,
809 .get_value = ctrl_channelprog_get,
810 DEFINT(0,FREQTABLE_SIZE),
812 .desc = "Streaming Enabled",
813 .name = "streaming_enabled",
814 .get_value = ctrl_streamingenabled_get,
819 .get_value = ctrl_hsm_get,
820 DEFENUM(control_values_hsm),
822 .desc = "Signal Present",
823 .name = "signal_present",
824 .get_value = ctrl_signal_get,
827 .desc = "Video Standards Available Mask",
828 .name = "video_standard_mask_available",
829 .internal_id = PVR2_CID_STDAVAIL,
831 .get_value = ctrl_stdavail_get,
832 .set_value = ctrl_stdavail_set,
833 .val_to_sym = ctrl_std_val_to_sym,
834 .sym_to_val = ctrl_std_sym_to_val,
835 .type = pvr2_ctl_bitmask,
837 .desc = "Video Standards In Use Mask",
838 .name = "video_standard_mask_active",
839 .internal_id = PVR2_CID_STDCUR,
841 .get_value = ctrl_stdcur_get,
842 .set_value = ctrl_stdcur_set,
843 .is_dirty = ctrl_stdcur_is_dirty,
844 .clear_dirty = ctrl_stdcur_clear_dirty,
845 .val_to_sym = ctrl_std_val_to_sym,
846 .sym_to_val = ctrl_std_sym_to_val,
847 .type = pvr2_ctl_bitmask,
849 .desc = "Subsystem enabled mask",
850 .name = "debug_subsys_mask",
852 .get_value = ctrl_subsys_get,
853 .set_value = ctrl_subsys_set,
854 DEFMASK(PVR2_SUBSYS_ALL,control_values_subsystem),
856 .desc = "Subsystem stream mask",
857 .name = "debug_subsys_stream_mask",
859 .get_value = ctrl_subsys_stream_get,
860 .set_value = ctrl_subsys_stream_set,
861 DEFMASK(PVR2_SUBSYS_ALL,control_values_subsystem),
863 .desc = "Video Standard Name",
864 .name = "video_standard",
865 .internal_id = PVR2_CID_STDENUM,
867 .get_value = ctrl_stdenumcur_get,
868 .set_value = ctrl_stdenumcur_set,
869 .is_dirty = ctrl_stdenumcur_is_dirty,
870 .clear_dirty = ctrl_stdenumcur_clear_dirty,
871 .type = pvr2_ctl_enum,
875 #define CTRLDEF_COUNT (sizeof(control_defs)/sizeof(control_defs[0]))
878 const char *pvr2_config_get_name(enum pvr2_config cfg)
881 case pvr2_config_empty: return "empty";
882 case pvr2_config_mpeg: return "mpeg";
883 case pvr2_config_vbi: return "vbi";
884 case pvr2_config_radio: return "radio";
890 struct usb_device *pvr2_hdw_get_dev(struct pvr2_hdw *hdw)
896 unsigned long pvr2_hdw_get_sn(struct pvr2_hdw *hdw)
898 return hdw->serial_number;
901 int pvr2_hdw_get_unit_number(struct pvr2_hdw *hdw)
903 return hdw->unit_number;
907 /* Attempt to locate one of the given set of files. Messages are logged
908 appropriate to what has been found. The return value will be 0 or
909 greater on success (it will be the index of the file name found) and
910 fw_entry will be filled in. Otherwise a negative error is returned on
911 failure. If the return value is -ENOENT then no viable firmware file
913 static int pvr2_locate_firmware(struct pvr2_hdw *hdw,
914 const struct firmware **fw_entry,
915 const char *fwtypename,
916 unsigned int fwcount,
917 const char *fwnames[])
921 for (idx = 0; idx < fwcount; idx++) {
922 ret = request_firmware(fw_entry,
926 trace_firmware("Located %s firmware: %s;"
932 if (ret == -ENOENT) continue;
933 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
934 "request_firmware fatal error with code=%d",ret);
937 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
939 " Device %s firmware"
940 " seems to be missing.",
942 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
943 "Did you install the pvrusb2 firmware files"
944 " in their proper location?");
946 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
947 "request_firmware unable to locate %s file %s",
948 fwtypename,fwnames[0]);
950 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
951 "request_firmware unable to locate"
952 " one of the following %s files:",
954 for (idx = 0; idx < fwcount; idx++) {
955 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
956 "request_firmware: Failed to find %s",
965 * pvr2_upload_firmware1().
967 * Send the 8051 firmware to the device. After the upload, arrange for
968 * device to re-enumerate.
970 * NOTE : the pointer to the firmware data given by request_firmware()
971 * is not suitable for an usb transaction.
974 static int pvr2_upload_firmware1(struct pvr2_hdw *hdw)
976 const struct firmware *fw_entry = NULL;
981 static const char *fw_files_29xxx[] = {
982 "v4l-pvrusb2-29xxx-01.fw",
984 static const char *fw_files_24xxx[] = {
985 "v4l-pvrusb2-24xxx-01.fw",
987 static const struct pvr2_string_table fw_file_defs[] = {
988 [PVR2_HDW_TYPE_29XXX] = {
990 sizeof(fw_files_29xxx)/sizeof(fw_files_29xxx[0]),
992 [PVR2_HDW_TYPE_24XXX] = {
994 sizeof(fw_files_24xxx)/sizeof(fw_files_24xxx[0]),
997 hdw->fw1_state = FW1_STATE_FAILED; // default result
999 trace_firmware("pvr2_upload_firmware1");
1001 ret = pvr2_locate_firmware(hdw,&fw_entry,"fx2 controller",
1002 fw_file_defs[hdw->hdw_type].cnt,
1003 fw_file_defs[hdw->hdw_type].lst);
1005 if (ret == -ENOENT) hdw->fw1_state = FW1_STATE_MISSING;
1009 usb_settoggle(hdw->usb_dev, 0 & 0xf, !(0 & USB_DIR_IN), 0);
1010 usb_clear_halt(hdw->usb_dev, usb_sndbulkpipe(hdw->usb_dev, 0 & 0x7f));
1012 pipe = usb_sndctrlpipe(hdw->usb_dev, 0);
1014 if (fw_entry->size != 0x2000){
1015 pvr2_trace(PVR2_TRACE_ERROR_LEGS,"wrong fx2 firmware size");
1016 release_firmware(fw_entry);
1020 fw_ptr = kmalloc(0x800, GFP_KERNEL);
1021 if (fw_ptr == NULL){
1022 release_firmware(fw_entry);
1026 /* We have to hold the CPU during firmware upload. */
1027 pvr2_hdw_cpureset_assert(hdw,1);
1029 /* upload the firmware to address 0000-1fff in 2048 (=0x800) bytes
1033 for(address = 0; address < fw_entry->size; address += 0x800) {
1034 memcpy(fw_ptr, fw_entry->data + address, 0x800);
1035 ret += usb_control_msg(hdw->usb_dev, pipe, 0xa0, 0x40, address,
1036 0, fw_ptr, 0x800, HZ);
1039 trace_firmware("Upload done, releasing device's CPU");
1041 /* Now release the CPU. It will disconnect and reconnect later. */
1042 pvr2_hdw_cpureset_assert(hdw,0);
1045 release_firmware(fw_entry);
1047 trace_firmware("Upload done (%d bytes sent)",ret);
1049 /* We should have written 8192 bytes */
1051 hdw->fw1_state = FW1_STATE_RELOAD;
1060 * pvr2_upload_firmware2()
1062 * This uploads encoder firmware on endpoint 2.
1066 int pvr2_upload_firmware2(struct pvr2_hdw *hdw)
1068 const struct firmware *fw_entry = NULL;
1070 unsigned int pipe, fw_len, fw_done;
1074 static const char *fw_files[] = {
1075 CX2341X_FIRM_ENC_FILENAME,
1078 trace_firmware("pvr2_upload_firmware2");
1080 ret = pvr2_locate_firmware(hdw,&fw_entry,"encoder",
1081 sizeof(fw_files)/sizeof(fw_files[0]),
1083 if (ret < 0) return ret;
1086 /* Since we're about to completely reinitialize the encoder,
1087 invalidate our cached copy of its configuration state. Next
1088 time we configure the encoder, then we'll fully configure it. */
1089 hdw->enc_cur_valid = 0;
1091 /* First prepare firmware loading */
1092 ret |= pvr2_write_register(hdw, 0x0048, 0xffffffff); /*interrupt mask*/
1093 ret |= pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000088); /*gpio dir*/
1094 ret |= pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000008); /*gpio output state*/
1095 ret |= pvr2_hdw_cmd_deep_reset(hdw);
1096 ret |= pvr2_write_register(hdw, 0xa064, 0x00000000); /*APU command*/
1097 ret |= pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000408); /*gpio dir*/
1098 ret |= pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000008); /*gpio output state*/
1099 ret |= pvr2_write_register(hdw, 0x9058, 0xffffffed); /*VPU ctrl*/
1100 ret |= pvr2_write_register(hdw, 0x9054, 0xfffffffd); /*reset hw blocks*/
1101 ret |= pvr2_write_register(hdw, 0x07f8, 0x80000800); /*encoder SDRAM refresh*/
1102 ret |= pvr2_write_register(hdw, 0x07fc, 0x0000001a); /*encoder SDRAM pre-charge*/
1103 ret |= pvr2_write_register(hdw, 0x0700, 0x00000000); /*I2C clock*/
1104 ret |= pvr2_write_register(hdw, 0xaa00, 0x00000000); /*unknown*/
1105 ret |= pvr2_write_register(hdw, 0xaa04, 0x00057810); /*unknown*/
1106 ret |= pvr2_write_register(hdw, 0xaa10, 0x00148500); /*unknown*/
1107 ret |= pvr2_write_register(hdw, 0xaa18, 0x00840000); /*unknown*/
1108 ret |= pvr2_write_u8(hdw, 0x52, 0);
1109 ret |= pvr2_write_u16(hdw, 0x0600, 0);
1112 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1113 "firmware2 upload prep failed, ret=%d",ret);
1114 release_firmware(fw_entry);
1118 /* Now send firmware */
1120 fw_len = fw_entry->size;
1122 if (fw_len % FIRMWARE_CHUNK_SIZE) {
1123 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1124 "size of %s firmware"
1125 " must be a multiple of 8192B",
1127 release_firmware(fw_entry);
1131 fw_ptr = kmalloc(FIRMWARE_CHUNK_SIZE, GFP_KERNEL);
1132 if (fw_ptr == NULL){
1133 release_firmware(fw_entry);
1134 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1135 "failed to allocate memory for firmware2 upload");
1139 pipe = usb_sndbulkpipe(hdw->usb_dev, PVR2_FIRMWARE_ENDPOINT);
1141 for (fw_done = 0 ; (fw_done < fw_len) && !ret ;
1142 fw_done += FIRMWARE_CHUNK_SIZE ) {
1144 memcpy(fw_ptr, fw_entry->data + fw_done, FIRMWARE_CHUNK_SIZE);
1145 /* Usbsnoop log shows that we must swap bytes... */
1146 for (i = 0; i < FIRMWARE_CHUNK_SIZE/4 ; i++)
1147 ((u32 *)fw_ptr)[i] = ___swab32(((u32 *)fw_ptr)[i]);
1149 ret |= usb_bulk_msg(hdw->usb_dev, pipe, fw_ptr,
1150 FIRMWARE_CHUNK_SIZE,
1151 &actual_length, HZ);
1152 ret |= (actual_length != FIRMWARE_CHUNK_SIZE);
1155 trace_firmware("upload of %s : %i / %i ",
1156 fw_files[fwidx],fw_done,fw_len);
1159 release_firmware(fw_entry);
1162 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1163 "firmware2 upload transfer failure");
1169 ret |= pvr2_write_register(hdw, 0x9054, 0xffffffff); /*reset hw blocks*/
1170 ret |= pvr2_write_register(hdw, 0x9058, 0xffffffe8); /*VPU ctrl*/
1171 ret |= pvr2_write_u16(hdw, 0x0600, 0);
1174 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1175 "firmware2 upload post-proc failure");
1177 hdw->subsys_enabled_mask |= (1<<PVR2_SUBSYS_B_ENC_FIRMWARE);
1183 #define FIRMWARE_RECOVERY_BITS \
1184 ((1<<PVR2_SUBSYS_B_ENC_CFG) | \
1185 (1<<PVR2_SUBSYS_B_ENC_RUN) | \
1186 (1<<PVR2_SUBSYS_B_ENC_FIRMWARE) | \
1187 (1<<PVR2_SUBSYS_B_USBSTREAM_RUN))
1191 This single function is key to pretty much everything. The pvrusb2
1192 device can logically be viewed as a series of subsystems which can be
1193 stopped / started or unconfigured / configured. To get things streaming,
1194 one must configure everything and start everything, but there may be
1195 various reasons over time to deconfigure something or stop something.
1196 This function handles all of this activity. Everything EVERYWHERE that
1197 must affect a subsystem eventually comes here to do the work.
1199 The current state of all subsystems is represented by a single bit mask,
1200 known as subsys_enabled_mask. The bit positions are defined by the
1201 PVR2_SUBSYS_xxxx macros, with one subsystem per bit position. At any
1202 time the set of configured or active subsystems can be queried just by
1203 looking at that mask. To change bits in that mask, this function here
1204 must be called. The "msk" argument indicates which bit positions to
1205 change, and the "val" argument defines the new values for the positions
1208 There is a priority ordering of starting / stopping things, and for
1209 multiple requested changes, this function implements that ordering.
1210 (Thus we will act on a request to load encoder firmware before we
1211 configure the encoder.) In addition to priority ordering, there is a
1212 recovery strategy implemented here. If a particular step fails and we
1213 detect that failure, this function will clear the affected subsystem bits
1214 and restart. Thus we have a means for recovering from a dead encoder:
1215 Clear all bits that correspond to subsystems that we need to restart /
1216 reconfigure and start over.
1219 static void pvr2_hdw_subsys_bit_chg_no_lock(struct pvr2_hdw *hdw,
1226 unsigned int tryCount = 0;
1228 if (!hdw->flag_ok) return;
1230 msk &= PVR2_SUBSYS_ALL;
1231 nmsk = (hdw->subsys_enabled_mask & ~msk) | (val & msk);
1232 nmsk &= PVR2_SUBSYS_ALL;
1236 if (!((nmsk ^ hdw->subsys_enabled_mask) &
1237 PVR2_SUBSYS_ALL)) break;
1239 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1240 "Too many retries when configuring device;"
1242 pvr2_hdw_render_useless(hdw);
1246 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1247 "Retrying device reconfiguration");
1249 pvr2_trace(PVR2_TRACE_INIT,
1250 "subsys mask changing 0x%lx:0x%lx"
1251 " from 0x%lx to 0x%lx",
1252 msk,val,hdw->subsys_enabled_mask,nmsk);
1254 vmsk = (nmsk ^ hdw->subsys_enabled_mask) &
1255 hdw->subsys_enabled_mask;
1257 if (vmsk & (1<<PVR2_SUBSYS_B_ENC_RUN)) {
1258 pvr2_trace(PVR2_TRACE_CTL,
1259 "/*---TRACE_CTL----*/"
1260 " pvr2_encoder_stop");
1261 ret = pvr2_encoder_stop(hdw);
1263 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1264 "Error recovery initiated");
1265 hdw->subsys_enabled_mask &=
1266 ~FIRMWARE_RECOVERY_BITS;
1270 if (vmsk & (1<<PVR2_SUBSYS_B_USBSTREAM_RUN)) {
1271 pvr2_trace(PVR2_TRACE_CTL,
1272 "/*---TRACE_CTL----*/"
1273 " pvr2_hdw_cmd_usbstream(0)");
1274 pvr2_hdw_cmd_usbstream(hdw,0);
1276 if (vmsk & (1<<PVR2_SUBSYS_B_DIGITIZER_RUN)) {
1277 pvr2_trace(PVR2_TRACE_CTL,
1278 "/*---TRACE_CTL----*/"
1279 " decoder disable");
1280 if (hdw->decoder_ctrl) {
1281 hdw->decoder_ctrl->enable(
1282 hdw->decoder_ctrl->ctxt,0);
1284 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1286 " No decoder present");
1288 hdw->subsys_enabled_mask &=
1289 ~(1<<PVR2_SUBSYS_B_DIGITIZER_RUN);
1291 if (vmsk & PVR2_SUBSYS_CFG_ALL) {
1292 hdw->subsys_enabled_mask &=
1293 ~(vmsk & PVR2_SUBSYS_CFG_ALL);
1296 vmsk = (nmsk ^ hdw->subsys_enabled_mask) & nmsk;
1298 if (vmsk & (1<<PVR2_SUBSYS_B_ENC_FIRMWARE)) {
1299 pvr2_trace(PVR2_TRACE_CTL,
1300 "/*---TRACE_CTL----*/"
1301 " pvr2_upload_firmware2");
1302 ret = pvr2_upload_firmware2(hdw);
1304 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1305 "Failure uploading encoder"
1307 pvr2_hdw_render_useless(hdw);
1311 if (vmsk & (1<<PVR2_SUBSYS_B_ENC_CFG)) {
1312 pvr2_trace(PVR2_TRACE_CTL,
1313 "/*---TRACE_CTL----*/"
1314 " pvr2_encoder_configure");
1315 ret = pvr2_encoder_configure(hdw);
1317 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1318 "Error recovery initiated");
1319 hdw->subsys_enabled_mask &=
1320 ~FIRMWARE_RECOVERY_BITS;
1324 if (vmsk & (1<<PVR2_SUBSYS_B_DIGITIZER_RUN)) {
1325 pvr2_trace(PVR2_TRACE_CTL,
1326 "/*---TRACE_CTL----*/"
1328 if (hdw->decoder_ctrl) {
1329 hdw->decoder_ctrl->enable(
1330 hdw->decoder_ctrl->ctxt,!0);
1332 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1334 " No decoder present");
1336 hdw->subsys_enabled_mask |=
1337 (1<<PVR2_SUBSYS_B_DIGITIZER_RUN);
1339 if (vmsk & (1<<PVR2_SUBSYS_B_USBSTREAM_RUN)) {
1340 pvr2_trace(PVR2_TRACE_CTL,
1341 "/*---TRACE_CTL----*/"
1342 " pvr2_hdw_cmd_usbstream(1)");
1343 pvr2_hdw_cmd_usbstream(hdw,!0);
1345 if (vmsk & (1<<PVR2_SUBSYS_B_ENC_RUN)) {
1346 pvr2_trace(PVR2_TRACE_CTL,
1347 "/*---TRACE_CTL----*/"
1348 " pvr2_encoder_start");
1349 ret = pvr2_encoder_start(hdw);
1351 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1352 "Error recovery initiated");
1353 hdw->subsys_enabled_mask &=
1354 ~FIRMWARE_RECOVERY_BITS;
1363 void pvr2_hdw_subsys_bit_chg(struct pvr2_hdw *hdw,
1364 unsigned long msk,unsigned long val)
1366 LOCK_TAKE(hdw->big_lock); do {
1367 pvr2_hdw_subsys_bit_chg_no_lock(hdw,msk,val);
1368 } while (0); LOCK_GIVE(hdw->big_lock);
1372 unsigned long pvr2_hdw_subsys_get(struct pvr2_hdw *hdw)
1374 return hdw->subsys_enabled_mask;
1378 unsigned long pvr2_hdw_subsys_stream_get(struct pvr2_hdw *hdw)
1380 return hdw->subsys_stream_mask;
1384 static void pvr2_hdw_subsys_stream_bit_chg_no_lock(struct pvr2_hdw *hdw,
1389 msk &= PVR2_SUBSYS_ALL;
1390 val2 = ((hdw->subsys_stream_mask & ~msk) | (val & msk));
1391 pvr2_trace(PVR2_TRACE_INIT,
1392 "stream mask changing 0x%lx:0x%lx from 0x%lx to 0x%lx",
1393 msk,val,hdw->subsys_stream_mask,val2);
1394 hdw->subsys_stream_mask = val2;
1398 void pvr2_hdw_subsys_stream_bit_chg(struct pvr2_hdw *hdw,
1402 LOCK_TAKE(hdw->big_lock); do {
1403 pvr2_hdw_subsys_stream_bit_chg_no_lock(hdw,msk,val);
1404 } while (0); LOCK_GIVE(hdw->big_lock);
1408 static int pvr2_hdw_set_streaming_no_lock(struct pvr2_hdw *hdw,int enableFl)
1410 if ((!enableFl) == !(hdw->flag_streaming_enabled)) return 0;
1412 pvr2_trace(PVR2_TRACE_START_STOP,
1413 "/*--TRACE_STREAM--*/ enable");
1414 pvr2_hdw_subsys_bit_chg_no_lock(hdw,~0,~0);
1416 pvr2_trace(PVR2_TRACE_START_STOP,
1417 "/*--TRACE_STREAM--*/ disable");
1418 pvr2_hdw_subsys_bit_chg_no_lock(hdw,hdw->subsys_stream_mask,0);
1420 if (!hdw->flag_ok) return -EIO;
1421 hdw->flag_streaming_enabled = enableFl != 0;
1426 int pvr2_hdw_get_streaming(struct pvr2_hdw *hdw)
1428 return hdw->flag_streaming_enabled != 0;
1432 int pvr2_hdw_set_streaming(struct pvr2_hdw *hdw,int enable_flag)
1435 LOCK_TAKE(hdw->big_lock); do {
1436 ret = pvr2_hdw_set_streaming_no_lock(hdw,enable_flag);
1437 } while (0); LOCK_GIVE(hdw->big_lock);
1442 static int pvr2_hdw_set_stream_type_no_lock(struct pvr2_hdw *hdw,
1443 enum pvr2_config config)
1445 unsigned long sm = hdw->subsys_enabled_mask;
1446 if (!hdw->flag_ok) return -EIO;
1447 pvr2_hdw_subsys_bit_chg_no_lock(hdw,hdw->subsys_stream_mask,0);
1448 hdw->config = config;
1449 pvr2_hdw_subsys_bit_chg_no_lock(hdw,~0,sm);
1454 int pvr2_hdw_set_stream_type(struct pvr2_hdw *hdw,enum pvr2_config config)
1457 if (!hdw->flag_ok) return -EIO;
1458 LOCK_TAKE(hdw->big_lock);
1459 ret = pvr2_hdw_set_stream_type_no_lock(hdw,config);
1460 LOCK_GIVE(hdw->big_lock);
1465 static int get_default_tuner_type(struct pvr2_hdw *hdw)
1467 int unit_number = hdw->unit_number;
1469 if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1470 tp = tuner[unit_number];
1472 if (tp < 0) return -EINVAL;
1473 hdw->tuner_type = tp;
1478 static v4l2_std_id get_default_standard(struct pvr2_hdw *hdw)
1480 int unit_number = hdw->unit_number;
1482 if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1483 tp = video_std[unit_number];
1489 static unsigned int get_default_error_tolerance(struct pvr2_hdw *hdw)
1491 int unit_number = hdw->unit_number;
1493 if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1494 tp = tolerance[unit_number];
1500 static int pvr2_hdw_check_firmware(struct pvr2_hdw *hdw)
1502 /* Try a harmless request to fetch the eeprom's address over
1503 endpoint 1. See what happens. Only the full FX2 image can
1504 respond to this. If this probe fails then likely the FX2
1505 firmware needs be loaded. */
1507 LOCK_TAKE(hdw->ctl_lock); do {
1508 hdw->cmd_buffer[0] = 0xeb;
1509 result = pvr2_send_request_ex(hdw,HZ*1,!0,
1512 if (result < 0) break;
1513 } while(0); LOCK_GIVE(hdw->ctl_lock);
1515 pvr2_trace(PVR2_TRACE_INIT,
1516 "Probe of device endpoint 1 result status %d",
1519 pvr2_trace(PVR2_TRACE_INIT,
1520 "Probe of device endpoint 1 succeeded");
1525 static void pvr2_hdw_setup_std(struct pvr2_hdw *hdw)
1529 v4l2_std_id std1,std2;
1531 std1 = get_default_standard(hdw);
1533 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),hdw->std_mask_eeprom);
1534 pvr2_trace(PVR2_TRACE_INIT,
1535 "Supported video standard(s) reported by eeprom: %.*s",
1538 hdw->std_mask_avail = hdw->std_mask_eeprom;
1540 std2 = std1 & ~hdw->std_mask_avail;
1542 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std2);
1543 pvr2_trace(PVR2_TRACE_INIT,
1544 "Expanding supported video standards"
1545 " to include: %.*s",
1547 hdw->std_mask_avail |= std2;
1550 pvr2_hdw_internal_set_std_avail(hdw);
1553 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std1);
1554 pvr2_trace(PVR2_TRACE_INIT,
1555 "Initial video standard forced to %.*s",
1557 hdw->std_mask_cur = std1;
1558 hdw->std_dirty = !0;
1559 pvr2_hdw_internal_find_stdenum(hdw);
1563 if (hdw->std_enum_cnt > 1) {
1564 // Autoselect the first listed standard
1565 hdw->std_enum_cur = 1;
1566 hdw->std_mask_cur = hdw->std_defs[hdw->std_enum_cur-1].id;
1567 hdw->std_dirty = !0;
1568 pvr2_trace(PVR2_TRACE_INIT,
1569 "Initial video standard auto-selected to %s",
1570 hdw->std_defs[hdw->std_enum_cur-1].name);
1574 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1575 "Unable to select a viable initial video standard");
1579 static void pvr2_hdw_setup_low(struct pvr2_hdw *hdw)
1583 struct pvr2_ctrl *cptr;
1586 reloadFl = (hdw->usb_intf->cur_altsetting->desc.bNumEndpoints
1589 pvr2_trace(PVR2_TRACE_INIT,
1590 "USB endpoint config looks strange"
1591 "; possibly firmware needs to be loaded");
1595 reloadFl = !pvr2_hdw_check_firmware(hdw);
1597 pvr2_trace(PVR2_TRACE_INIT,
1598 "Check for FX2 firmware failed"
1599 "; possibly firmware needs to be loaded");
1603 if (pvr2_upload_firmware1(hdw) != 0) {
1604 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1605 "Failure uploading firmware1");
1609 hdw->fw1_state = FW1_STATE_OK;
1612 pvr2_hdw_device_reset(hdw);
1614 if (!pvr2_hdw_dev_ok(hdw)) return;
1616 for (idx = 0; idx < pvr2_client_lists[hdw->hdw_type].cnt; idx++) {
1617 request_module(pvr2_client_lists[hdw->hdw_type].lst[idx]);
1620 pvr2_hdw_cmd_powerup(hdw);
1621 if (!pvr2_hdw_dev_ok(hdw)) return;
1623 if (pvr2_upload_firmware2(hdw)){
1624 pvr2_trace(PVR2_TRACE_ERROR_LEGS,"device unstable!!");
1625 pvr2_hdw_render_useless(hdw);
1629 // This step MUST happen after the earlier powerup step.
1630 pvr2_i2c_core_init(hdw);
1631 if (!pvr2_hdw_dev_ok(hdw)) return;
1633 for (idx = 0; idx < CTRLDEF_COUNT; idx++) {
1634 cptr = hdw->controls + idx;
1635 if (cptr->info->skip_init) continue;
1636 if (!cptr->info->set_value) continue;
1637 cptr->info->set_value(cptr,~0,cptr->info->default_value);
1640 // Do not use pvr2_reset_ctl_endpoints() here. It is not
1641 // thread-safe against the normal pvr2_send_request() mechanism.
1642 // (We should make it thread safe).
1644 ret = pvr2_hdw_get_eeprom_addr(hdw);
1645 if (!pvr2_hdw_dev_ok(hdw)) return;
1647 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1648 "Unable to determine location of eeprom, skipping");
1650 hdw->eeprom_addr = ret;
1651 pvr2_eeprom_analyze(hdw);
1652 if (!pvr2_hdw_dev_ok(hdw)) return;
1655 pvr2_hdw_setup_std(hdw);
1657 if (!get_default_tuner_type(hdw)) {
1658 pvr2_trace(PVR2_TRACE_INIT,
1659 "pvr2_hdw_setup: Tuner type overridden to %d",
1663 hdw->tuner_updated = !0;
1664 pvr2_i2c_core_check_stale(hdw);
1665 hdw->tuner_updated = 0;
1667 if (!pvr2_hdw_dev_ok(hdw)) return;
1669 pvr2_hdw_commit_ctl_internal(hdw);
1670 if (!pvr2_hdw_dev_ok(hdw)) return;
1672 hdw->vid_stream = pvr2_stream_create();
1673 if (!pvr2_hdw_dev_ok(hdw)) return;
1674 pvr2_trace(PVR2_TRACE_INIT,
1675 "pvr2_hdw_setup: video stream is %p",hdw->vid_stream);
1676 if (hdw->vid_stream) {
1677 idx = get_default_error_tolerance(hdw);
1679 pvr2_trace(PVR2_TRACE_INIT,
1680 "pvr2_hdw_setup: video stream %p"
1681 " setting tolerance %u",
1682 hdw->vid_stream,idx);
1684 pvr2_stream_setup(hdw->vid_stream,hdw->usb_dev,
1685 PVR2_VID_ENDPOINT,idx);
1688 if (!pvr2_hdw_dev_ok(hdw)) return;
1690 /* Make sure everything is up to date */
1691 pvr2_i2c_core_sync(hdw);
1693 if (!pvr2_hdw_dev_ok(hdw)) return;
1695 hdw->flag_init_ok = !0;
1699 int pvr2_hdw_setup(struct pvr2_hdw *hdw)
1701 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_setup(hdw=%p) begin",hdw);
1702 LOCK_TAKE(hdw->big_lock); do {
1703 pvr2_hdw_setup_low(hdw);
1704 pvr2_trace(PVR2_TRACE_INIT,
1705 "pvr2_hdw_setup(hdw=%p) done, ok=%d init_ok=%d",
1706 hdw,hdw->flag_ok,hdw->flag_init_ok);
1707 if (pvr2_hdw_dev_ok(hdw)) {
1708 if (pvr2_hdw_init_ok(hdw)) {
1711 "Device initialization"
1712 " completed successfully.");
1715 if (hdw->fw1_state == FW1_STATE_RELOAD) {
1718 "Device microcontroller firmware"
1719 " (re)loaded; it should now reset"
1724 PVR2_TRACE_ERROR_LEGS,
1725 "Device initialization was not successful.");
1726 if (hdw->fw1_state == FW1_STATE_MISSING) {
1728 PVR2_TRACE_ERROR_LEGS,
1729 "Giving up since device"
1730 " microcontroller firmware"
1731 " appears to be missing.");
1737 PVR2_TRACE_ERROR_LEGS,
1738 "Attempting pvrusb2 recovery by reloading"
1739 " primary firmware.");
1741 PVR2_TRACE_ERROR_LEGS,
1742 "If this works, device should disconnect"
1743 " and reconnect in a sane state.");
1744 hdw->fw1_state = FW1_STATE_UNKNOWN;
1745 pvr2_upload_firmware1(hdw);
1748 PVR2_TRACE_ERROR_LEGS,
1749 "***WARNING*** pvrusb2 device hardware"
1750 " appears to be jammed"
1751 " and I can't clear it.");
1753 PVR2_TRACE_ERROR_LEGS,
1754 "You might need to power cycle"
1755 " the pvrusb2 device"
1756 " in order to recover.");
1758 } while (0); LOCK_GIVE(hdw->big_lock);
1759 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_setup(hdw=%p) end",hdw);
1760 return hdw->flag_init_ok;
1764 /* Create and return a structure for interacting with the underlying
1766 struct pvr2_hdw *pvr2_hdw_create(struct usb_interface *intf,
1767 const struct usb_device_id *devid)
1769 unsigned int idx,cnt1,cnt2;
1770 struct pvr2_hdw *hdw;
1771 unsigned int hdw_type;
1773 struct pvr2_ctrl *cptr;
1775 struct v4l2_queryctrl qctrl;
1776 struct pvr2_ctl_info *ciptr;
1778 hdw_type = devid - pvr2_device_table;
1780 sizeof(pvr2_device_names)/sizeof(pvr2_device_names[0])) {
1781 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1782 "Bogus device type of %u reported",hdw_type);
1786 hdw = kmalloc(sizeof(*hdw),GFP_KERNEL);
1787 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_create: hdw=%p, type \"%s\"",
1788 hdw,pvr2_device_names[hdw_type]);
1789 if (!hdw) goto fail;
1790 memset(hdw,0,sizeof(*hdw));
1791 cx2341x_fill_defaults(&hdw->enc_ctl_state);
1793 hdw->control_cnt = CTRLDEF_COUNT;
1794 hdw->control_cnt += MPEGDEF_COUNT;
1795 hdw->controls = kmalloc(sizeof(struct pvr2_ctrl) * hdw->control_cnt,
1797 if (!hdw->controls) goto fail;
1798 memset(hdw->controls,0,sizeof(struct pvr2_ctrl) * hdw->control_cnt);
1799 hdw->hdw_type = hdw_type;
1800 for (idx = 0; idx < hdw->control_cnt; idx++) {
1801 cptr = hdw->controls + idx;
1804 for (idx = 0; idx < 32; idx++) {
1805 hdw->std_mask_ptrs[idx] = hdw->std_mask_names[idx];
1807 for (idx = 0; idx < CTRLDEF_COUNT; idx++) {
1808 cptr = hdw->controls + idx;
1809 cptr->info = control_defs+idx;
1811 /* Define and configure additional controls from cx2341x module. */
1812 hdw->mpeg_ctrl_info = kmalloc(
1813 sizeof(*(hdw->mpeg_ctrl_info)) * MPEGDEF_COUNT, GFP_KERNEL);
1814 if (!hdw->mpeg_ctrl_info) goto fail;
1815 memset(hdw->mpeg_ctrl_info,0,
1816 sizeof(*(hdw->mpeg_ctrl_info)) * MPEGDEF_COUNT);
1817 for (idx = 0; idx < MPEGDEF_COUNT; idx++) {
1818 cptr = hdw->controls + idx + CTRLDEF_COUNT;
1819 ciptr = &(hdw->mpeg_ctrl_info[idx].info);
1820 ciptr->desc = hdw->mpeg_ctrl_info[idx].desc;
1821 ciptr->name = mpeg_ids[idx].strid;
1822 ciptr->v4l_id = mpeg_ids[idx].id;
1823 ciptr->skip_init = !0;
1824 ciptr->get_value = ctrl_cx2341x_get;
1825 ciptr->get_v4lflags = ctrl_cx2341x_getv4lflags;
1826 ciptr->is_dirty = ctrl_cx2341x_is_dirty;
1827 if (!idx) ciptr->clear_dirty = ctrl_cx2341x_clear_dirty;
1828 qctrl.id = ciptr->v4l_id;
1829 cx2341x_ctrl_query(&hdw->enc_ctl_state,&qctrl);
1830 if (!(qctrl.flags & V4L2_CTRL_FLAG_READ_ONLY)) {
1831 ciptr->set_value = ctrl_cx2341x_set;
1833 strncpy(hdw->mpeg_ctrl_info[idx].desc,qctrl.name,
1834 PVR2_CTLD_INFO_DESC_SIZE);
1835 hdw->mpeg_ctrl_info[idx].desc[PVR2_CTLD_INFO_DESC_SIZE-1] = 0;
1836 ciptr->default_value = qctrl.default_value;
1837 switch (qctrl.type) {
1839 case V4L2_CTRL_TYPE_INTEGER:
1840 ciptr->type = pvr2_ctl_int;
1841 ciptr->def.type_int.min_value = qctrl.minimum;
1842 ciptr->def.type_int.max_value = qctrl.maximum;
1844 case V4L2_CTRL_TYPE_BOOLEAN:
1845 ciptr->type = pvr2_ctl_bool;
1847 case V4L2_CTRL_TYPE_MENU:
1848 ciptr->type = pvr2_ctl_enum;
1849 ciptr->def.type_enum.value_names =
1850 cx2341x_ctrl_get_menu(ciptr->v4l_id);
1852 ciptr->def.type_enum.value_names[cnt1] != NULL;
1854 ciptr->def.type_enum.count = cnt1;
1860 // Initialize video standard enum dynamic control
1861 cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDENUM);
1863 memcpy(&hdw->std_info_enum,cptr->info,
1864 sizeof(hdw->std_info_enum));
1865 cptr->info = &hdw->std_info_enum;
1868 // Initialize control data regarding video standard masks
1869 valid_std_mask = pvr2_std_get_usable();
1870 for (idx = 0; idx < 32; idx++) {
1871 if (!(valid_std_mask & (1 << idx))) continue;
1872 cnt1 = pvr2_std_id_to_str(
1873 hdw->std_mask_names[idx],
1874 sizeof(hdw->std_mask_names[idx])-1,
1876 hdw->std_mask_names[idx][cnt1] = 0;
1878 cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDAVAIL);
1880 memcpy(&hdw->std_info_avail,cptr->info,
1881 sizeof(hdw->std_info_avail));
1882 cptr->info = &hdw->std_info_avail;
1883 hdw->std_info_avail.def.type_bitmask.bit_names =
1885 hdw->std_info_avail.def.type_bitmask.valid_bits =
1888 cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDCUR);
1890 memcpy(&hdw->std_info_cur,cptr->info,
1891 sizeof(hdw->std_info_cur));
1892 cptr->info = &hdw->std_info_cur;
1893 hdw->std_info_cur.def.type_bitmask.bit_names =
1895 hdw->std_info_avail.def.type_bitmask.valid_bits =
1899 hdw->eeprom_addr = -1;
1900 hdw->unit_number = -1;
1901 hdw->v4l_minor_number_mpeg = -1;
1902 hdw->v4l_minor_number_radio = -1;
1903 hdw->ctl_write_buffer = kmalloc(PVR2_CTL_BUFFSIZE,GFP_KERNEL);
1904 if (!hdw->ctl_write_buffer) goto fail;
1905 hdw->ctl_read_buffer = kmalloc(PVR2_CTL_BUFFSIZE,GFP_KERNEL);
1906 if (!hdw->ctl_read_buffer) goto fail;
1907 hdw->ctl_write_urb = usb_alloc_urb(0,GFP_KERNEL);
1908 if (!hdw->ctl_write_urb) goto fail;
1909 hdw->ctl_read_urb = usb_alloc_urb(0,GFP_KERNEL);
1910 if (!hdw->ctl_read_urb) goto fail;
1912 down(&pvr2_unit_sem); do {
1913 for (idx = 0; idx < PVR_NUM; idx++) {
1914 if (unit_pointers[idx]) continue;
1915 hdw->unit_number = idx;
1916 unit_pointers[idx] = hdw;
1919 } while (0); up(&pvr2_unit_sem);
1922 cnt2 = scnprintf(hdw->name+cnt1,sizeof(hdw->name)-cnt1,"pvrusb2");
1924 if (hdw->unit_number >= 0) {
1925 cnt2 = scnprintf(hdw->name+cnt1,sizeof(hdw->name)-cnt1,"_%c",
1926 ('a' + hdw->unit_number));
1929 if (cnt1 >= sizeof(hdw->name)) cnt1 = sizeof(hdw->name)-1;
1930 hdw->name[cnt1] = 0;
1932 pvr2_trace(PVR2_TRACE_INIT,"Driver unit number is %d, name is %s",
1933 hdw->unit_number,hdw->name);
1935 hdw->tuner_type = -1;
1937 /* Initialize the mask of subsystems that we will shut down when we
1939 hdw->subsys_stream_mask = PVR2_SUBSYS_RUN_ALL;
1940 hdw->subsys_stream_mask |= (1<<PVR2_SUBSYS_B_ENC_CFG);
1942 pvr2_trace(PVR2_TRACE_INIT,"subsys_stream_mask: 0x%lx",
1943 hdw->subsys_stream_mask);
1945 hdw->usb_intf = intf;
1946 hdw->usb_dev = interface_to_usbdev(intf);
1948 ifnum = hdw->usb_intf->cur_altsetting->desc.bInterfaceNumber;
1949 usb_set_interface(hdw->usb_dev,ifnum,0);
1951 mutex_init(&hdw->ctl_lock_mutex);
1952 mutex_init(&hdw->big_lock_mutex);
1957 usb_free_urb(hdw->ctl_read_urb);
1958 usb_free_urb(hdw->ctl_write_urb);
1959 kfree(hdw->ctl_read_buffer);
1960 kfree(hdw->ctl_write_buffer);
1961 kfree(hdw->controls);
1962 kfree(hdw->mpeg_ctrl_info);
1969 /* Remove _all_ associations between this driver and the underlying USB
1971 static void pvr2_hdw_remove_usb_stuff(struct pvr2_hdw *hdw)
1973 if (hdw->flag_disconnected) return;
1974 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_remove_usb_stuff: hdw=%p",hdw);
1975 if (hdw->ctl_read_urb) {
1976 usb_kill_urb(hdw->ctl_read_urb);
1977 usb_free_urb(hdw->ctl_read_urb);
1978 hdw->ctl_read_urb = NULL;
1980 if (hdw->ctl_write_urb) {
1981 usb_kill_urb(hdw->ctl_write_urb);
1982 usb_free_urb(hdw->ctl_write_urb);
1983 hdw->ctl_write_urb = NULL;
1985 if (hdw->ctl_read_buffer) {
1986 kfree(hdw->ctl_read_buffer);
1987 hdw->ctl_read_buffer = NULL;
1989 if (hdw->ctl_write_buffer) {
1990 kfree(hdw->ctl_write_buffer);
1991 hdw->ctl_write_buffer = NULL;
1993 pvr2_hdw_render_useless_unlocked(hdw);
1994 hdw->flag_disconnected = !0;
1995 hdw->usb_dev = NULL;
1996 hdw->usb_intf = NULL;
2000 /* Destroy hardware interaction structure */
2001 void pvr2_hdw_destroy(struct pvr2_hdw *hdw)
2003 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_destroy: hdw=%p",hdw);
2004 if (hdw->fw_buffer) {
2005 kfree(hdw->fw_buffer);
2006 hdw->fw_buffer = NULL;
2008 if (hdw->vid_stream) {
2009 pvr2_stream_destroy(hdw->vid_stream);
2010 hdw->vid_stream = NULL;
2012 if (hdw->audio_stat) {
2013 hdw->audio_stat->detach(hdw->audio_stat->ctxt);
2015 if (hdw->decoder_ctrl) {
2016 hdw->decoder_ctrl->detach(hdw->decoder_ctrl->ctxt);
2018 pvr2_i2c_core_done(hdw);
2019 pvr2_hdw_remove_usb_stuff(hdw);
2020 down(&pvr2_unit_sem); do {
2021 if ((hdw->unit_number >= 0) &&
2022 (hdw->unit_number < PVR_NUM) &&
2023 (unit_pointers[hdw->unit_number] == hdw)) {
2024 unit_pointers[hdw->unit_number] = NULL;
2026 } while (0); up(&pvr2_unit_sem);
2027 kfree(hdw->controls);
2028 kfree(hdw->mpeg_ctrl_info);
2029 kfree(hdw->std_defs);
2030 kfree(hdw->std_enum_names);
2035 int pvr2_hdw_init_ok(struct pvr2_hdw *hdw)
2037 return hdw->flag_init_ok;
2041 int pvr2_hdw_dev_ok(struct pvr2_hdw *hdw)
2043 return (hdw && hdw->flag_ok);
2047 /* Called when hardware has been unplugged */
2048 void pvr2_hdw_disconnect(struct pvr2_hdw *hdw)
2050 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_disconnect(hdw=%p)",hdw);
2051 LOCK_TAKE(hdw->big_lock);
2052 LOCK_TAKE(hdw->ctl_lock);
2053 pvr2_hdw_remove_usb_stuff(hdw);
2054 LOCK_GIVE(hdw->ctl_lock);
2055 LOCK_GIVE(hdw->big_lock);
2059 // Attempt to autoselect an appropriate value for std_enum_cur given
2060 // whatever is currently in std_mask_cur
2061 static void pvr2_hdw_internal_find_stdenum(struct pvr2_hdw *hdw)
2064 for (idx = 1; idx < hdw->std_enum_cnt; idx++) {
2065 if (hdw->std_defs[idx-1].id == hdw->std_mask_cur) {
2066 hdw->std_enum_cur = idx;
2070 hdw->std_enum_cur = 0;
2074 // Calculate correct set of enumerated standards based on currently known
2075 // set of available standards bits.
2076 static void pvr2_hdw_internal_set_std_avail(struct pvr2_hdw *hdw)
2078 struct v4l2_standard *newstd;
2079 unsigned int std_cnt;
2082 newstd = pvr2_std_create_enum(&std_cnt,hdw->std_mask_avail);
2084 if (hdw->std_defs) {
2085 kfree(hdw->std_defs);
2086 hdw->std_defs = NULL;
2088 hdw->std_enum_cnt = 0;
2089 if (hdw->std_enum_names) {
2090 kfree(hdw->std_enum_names);
2091 hdw->std_enum_names = NULL;
2096 PVR2_TRACE_ERROR_LEGS,
2097 "WARNING: Failed to identify any viable standards");
2099 hdw->std_enum_names = kmalloc(sizeof(char *)*(std_cnt+1),GFP_KERNEL);
2100 hdw->std_enum_names[0] = "none";
2101 for (idx = 0; idx < std_cnt; idx++) {
2102 hdw->std_enum_names[idx+1] =
2105 // Set up the dynamic control for this standard
2106 hdw->std_info_enum.def.type_enum.value_names = hdw->std_enum_names;
2107 hdw->std_info_enum.def.type_enum.count = std_cnt+1;
2108 hdw->std_defs = newstd;
2109 hdw->std_enum_cnt = std_cnt+1;
2110 hdw->std_enum_cur = 0;
2111 hdw->std_info_cur.def.type_bitmask.valid_bits = hdw->std_mask_avail;
2115 int pvr2_hdw_get_stdenum_value(struct pvr2_hdw *hdw,
2116 struct v4l2_standard *std,
2120 if (!idx) return ret;
2121 LOCK_TAKE(hdw->big_lock); do {
2122 if (idx >= hdw->std_enum_cnt) break;
2124 memcpy(std,hdw->std_defs+idx,sizeof(*std));
2126 } while (0); LOCK_GIVE(hdw->big_lock);
2131 /* Get the number of defined controls */
2132 unsigned int pvr2_hdw_get_ctrl_count(struct pvr2_hdw *hdw)
2134 return hdw->control_cnt;
2138 /* Retrieve a control handle given its index (0..count-1) */
2139 struct pvr2_ctrl *pvr2_hdw_get_ctrl_by_index(struct pvr2_hdw *hdw,
2142 if (idx >= hdw->control_cnt) return NULL;
2143 return hdw->controls + idx;
2147 /* Retrieve a control handle given its index (0..count-1) */
2148 struct pvr2_ctrl *pvr2_hdw_get_ctrl_by_id(struct pvr2_hdw *hdw,
2149 unsigned int ctl_id)
2151 struct pvr2_ctrl *cptr;
2155 /* This could be made a lot more efficient, but for now... */
2156 for (idx = 0; idx < hdw->control_cnt; idx++) {
2157 cptr = hdw->controls + idx;
2158 i = cptr->info->internal_id;
2159 if (i && (i == ctl_id)) return cptr;
2165 /* Given a V4L ID, retrieve the control structure associated with it. */
2166 struct pvr2_ctrl *pvr2_hdw_get_ctrl_v4l(struct pvr2_hdw *hdw,unsigned int ctl_id)
2168 struct pvr2_ctrl *cptr;
2172 /* This could be made a lot more efficient, but for now... */
2173 for (idx = 0; idx < hdw->control_cnt; idx++) {
2174 cptr = hdw->controls + idx;
2175 i = cptr->info->v4l_id;
2176 if (i && (i == ctl_id)) return cptr;
2182 /* Given a V4L ID for its immediate predecessor, retrieve the control
2183 structure associated with it. */
2184 struct pvr2_ctrl *pvr2_hdw_get_ctrl_nextv4l(struct pvr2_hdw *hdw,
2185 unsigned int ctl_id)
2187 struct pvr2_ctrl *cptr,*cp2;
2191 /* This could be made a lot more efficient, but for now... */
2193 for (idx = 0; idx < hdw->control_cnt; idx++) {
2194 cptr = hdw->controls + idx;
2195 i = cptr->info->v4l_id;
2197 if (i <= ctl_id) continue;
2198 if (cp2 && (cp2->info->v4l_id < i)) continue;
2206 static const char *get_ctrl_typename(enum pvr2_ctl_type tp)
2209 case pvr2_ctl_int: return "integer";
2210 case pvr2_ctl_enum: return "enum";
2211 case pvr2_ctl_bool: return "boolean";
2212 case pvr2_ctl_bitmask: return "bitmask";
2218 /* Commit all control changes made up to this point. Subsystems can be
2219 indirectly affected by these changes. For a given set of things being
2220 committed, we'll clear the affected subsystem bits and then once we're
2221 done committing everything we'll make a request to restore the subsystem
2222 state(s) back to their previous value before this function was called.
2223 Thus we can automatically reconfigure affected pieces of the driver as
2224 controls are changed. */
2225 static int pvr2_hdw_commit_ctl_internal(struct pvr2_hdw *hdw)
2227 unsigned long saved_subsys_mask = hdw->subsys_enabled_mask;
2228 unsigned long stale_subsys_mask = 0;
2230 struct pvr2_ctrl *cptr;
2232 int commit_flag = 0;
2234 unsigned int bcnt,ccnt;
2236 for (idx = 0; idx < hdw->control_cnt; idx++) {
2237 cptr = hdw->controls + idx;
2238 if (cptr->info->is_dirty == 0) continue;
2239 if (!cptr->info->is_dirty(cptr)) continue;
2244 bcnt = scnprintf(buf,sizeof(buf),"\"%s\" <-- ",
2247 cptr->info->get_value(cptr,&value);
2248 pvr2_ctrl_value_to_sym_internal(cptr,~0,value,
2250 sizeof(buf)-bcnt,&ccnt);
2252 bcnt += scnprintf(buf+bcnt,sizeof(buf)-bcnt," <%s>",
2253 get_ctrl_typename(cptr->info->type));
2254 pvr2_trace(PVR2_TRACE_CTL,
2255 "/*--TRACE_COMMIT--*/ %.*s",
2260 /* Nothing has changed */
2264 /* When video standard changes, reset the hres and vres values -
2265 but if the user has pending changes there, then let the changes
2267 if (hdw->std_dirty) {
2268 /* Rewrite the vertical resolution to be appropriate to the
2269 video standard that has been selected. */
2271 if (hdw->std_mask_cur & V4L2_STD_525_60) {
2276 if (nvres != hdw->res_ver_val) {
2277 hdw->res_ver_val = nvres;
2278 hdw->res_ver_dirty = !0;
2282 if (hdw->std_dirty ||
2285 hdw->res_ver_dirty ||
2286 hdw->res_hor_dirty ||
2288 /* If any of this changes, then the encoder needs to be
2289 reconfigured, and we need to reset the stream. */
2290 stale_subsys_mask |= (1<<PVR2_SUBSYS_B_ENC_CFG);
2293 if (hdw->input_dirty) {
2294 /* pk: If input changes to or from radio, then the encoder
2295 needs to be restarted (for ENC_MUTE_VIDEO to work) */
2296 stale_subsys_mask |= (1<<PVR2_SUBSYS_B_ENC_RUN);
2300 if (hdw->srate_dirty) {
2301 /* Write new sample rate into control structure since
2302 * the master copy is stale. We must track srate
2303 * separate from the mpeg control structure because
2304 * other logic also uses this value. */
2305 struct v4l2_ext_controls cs;
2306 struct v4l2_ext_control c1;
2307 memset(&cs,0,sizeof(cs));
2308 memset(&c1,0,sizeof(c1));
2311 c1.id = V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ;
2312 c1.value = hdw->srate_val;
2313 cx2341x_ext_ctrls(&hdw->enc_ctl_state,&cs,VIDIOC_S_EXT_CTRLS);
2316 /* Scan i2c core at this point - before we clear all the dirty
2317 bits. Various parts of the i2c core will notice dirty bits as
2318 appropriate and arrange to broadcast or directly send updates to
2319 the client drivers in order to keep everything in sync */
2320 pvr2_i2c_core_check_stale(hdw);
2322 for (idx = 0; idx < hdw->control_cnt; idx++) {
2323 cptr = hdw->controls + idx;
2324 if (!cptr->info->clear_dirty) continue;
2325 cptr->info->clear_dirty(cptr);
2328 /* Now execute i2c core update */
2329 pvr2_i2c_core_sync(hdw);
2331 pvr2_hdw_subsys_bit_chg_no_lock(hdw,stale_subsys_mask,0);
2332 pvr2_hdw_subsys_bit_chg_no_lock(hdw,~0,saved_subsys_mask);
2338 int pvr2_hdw_commit_ctl(struct pvr2_hdw *hdw)
2340 LOCK_TAKE(hdw->big_lock); do {
2341 pvr2_hdw_commit_ctl_internal(hdw);
2342 } while (0); LOCK_GIVE(hdw->big_lock);
2347 void pvr2_hdw_poll(struct pvr2_hdw *hdw)
2349 LOCK_TAKE(hdw->big_lock); do {
2350 pvr2_i2c_core_sync(hdw);
2351 } while (0); LOCK_GIVE(hdw->big_lock);
2355 void pvr2_hdw_setup_poll_trigger(struct pvr2_hdw *hdw,
2356 void (*func)(void *),
2359 LOCK_TAKE(hdw->big_lock); do {
2360 hdw->poll_trigger_func = func;
2361 hdw->poll_trigger_data = data;
2362 } while (0); LOCK_GIVE(hdw->big_lock);
2366 void pvr2_hdw_poll_trigger_unlocked(struct pvr2_hdw *hdw)
2368 if (hdw->poll_trigger_func) {
2369 hdw->poll_trigger_func(hdw->poll_trigger_data);
2373 /* Return name for this driver instance */
2374 const char *pvr2_hdw_get_driver_name(struct pvr2_hdw *hdw)
2380 /* Return bit mask indicating signal status */
2381 static unsigned int pvr2_hdw_get_signal_status_internal(struct pvr2_hdw *hdw)
2383 unsigned int msk = 0;
2384 switch (hdw->input_val) {
2385 case PVR2_CVAL_INPUT_TV:
2386 case PVR2_CVAL_INPUT_RADIO:
2387 if (hdw->decoder_ctrl &&
2388 hdw->decoder_ctrl->tuned(hdw->decoder_ctrl->ctxt)) {
2389 msk |= PVR2_SIGNAL_OK;
2390 if (hdw->audio_stat &&
2391 hdw->audio_stat->status(hdw->audio_stat->ctxt)) {
2392 if (hdw->flag_stereo) {
2393 msk |= PVR2_SIGNAL_STEREO;
2395 if (hdw->flag_bilingual) {
2396 msk |= PVR2_SIGNAL_SAP;
2402 msk |= PVR2_SIGNAL_OK | PVR2_SIGNAL_STEREO;
2408 int pvr2_hdw_is_hsm(struct pvr2_hdw *hdw)
2411 LOCK_TAKE(hdw->ctl_lock); do {
2412 hdw->cmd_buffer[0] = 0x0b;
2413 result = pvr2_send_request(hdw,
2416 if (result < 0) break;
2417 result = (hdw->cmd_buffer[0] != 0);
2418 } while(0); LOCK_GIVE(hdw->ctl_lock);
2423 /* Return bit mask indicating signal status */
2424 unsigned int pvr2_hdw_get_signal_status(struct pvr2_hdw *hdw)
2426 unsigned int msk = 0;
2427 LOCK_TAKE(hdw->big_lock); do {
2428 msk = pvr2_hdw_get_signal_status_internal(hdw);
2429 } while (0); LOCK_GIVE(hdw->big_lock);
2434 /* Get handle to video output stream */
2435 struct pvr2_stream *pvr2_hdw_get_video_stream(struct pvr2_hdw *hp)
2437 return hp->vid_stream;
2441 void pvr2_hdw_trigger_module_log(struct pvr2_hdw *hdw)
2443 int nr = pvr2_hdw_get_unit_number(hdw);
2444 LOCK_TAKE(hdw->big_lock); do {
2445 hdw->log_requested = !0;
2446 printk(KERN_INFO "pvrusb2: ================= START STATUS CARD #%d =================\n", nr);
2447 pvr2_i2c_core_check_stale(hdw);
2448 hdw->log_requested = 0;
2449 pvr2_i2c_core_sync(hdw);
2450 pvr2_trace(PVR2_TRACE_INFO,"cx2341x config:");
2451 cx2341x_log_status(&hdw->enc_ctl_state, "pvrusb2");
2452 printk(KERN_INFO "pvrusb2: ================== END STATUS CARD #%d ==================\n", nr);
2453 } while (0); LOCK_GIVE(hdw->big_lock);
2456 void pvr2_hdw_cpufw_set_enabled(struct pvr2_hdw *hdw, int enable_flag)
2461 LOCK_TAKE(hdw->big_lock); do {
2462 if ((hdw->fw_buffer == 0) == !enable_flag) break;
2465 pvr2_trace(PVR2_TRACE_FIRMWARE,
2466 "Cleaning up after CPU firmware fetch");
2467 kfree(hdw->fw_buffer);
2468 hdw->fw_buffer = NULL;
2470 /* Now release the CPU. It will disconnect and
2472 pvr2_hdw_cpureset_assert(hdw,0);
2476 pvr2_trace(PVR2_TRACE_FIRMWARE,
2477 "Preparing to suck out CPU firmware");
2478 hdw->fw_size = 0x2000;
2479 hdw->fw_buffer = kmalloc(hdw->fw_size,GFP_KERNEL);
2480 if (!hdw->fw_buffer) {
2485 memset(hdw->fw_buffer,0,hdw->fw_size);
2487 /* We have to hold the CPU during firmware upload. */
2488 pvr2_hdw_cpureset_assert(hdw,1);
2490 /* download the firmware from address 0000-1fff in 2048
2491 (=0x800) bytes chunk. */
2493 pvr2_trace(PVR2_TRACE_FIRMWARE,"Grabbing CPU firmware");
2494 pipe = usb_rcvctrlpipe(hdw->usb_dev, 0);
2495 for(address = 0; address < hdw->fw_size; address += 0x800) {
2496 ret = usb_control_msg(hdw->usb_dev,pipe,0xa0,0xc0,
2498 hdw->fw_buffer+address,0x800,HZ);
2502 pvr2_trace(PVR2_TRACE_FIRMWARE,"Done grabbing CPU firmware");
2504 } while (0); LOCK_GIVE(hdw->big_lock);
2508 /* Return true if we're in a mode for retrieval CPU firmware */
2509 int pvr2_hdw_cpufw_get_enabled(struct pvr2_hdw *hdw)
2511 return hdw->fw_buffer != 0;
2515 int pvr2_hdw_cpufw_get(struct pvr2_hdw *hdw,unsigned int offs,
2516 char *buf,unsigned int cnt)
2519 LOCK_TAKE(hdw->big_lock); do {
2523 if (!hdw->fw_buffer) {
2528 if (offs >= hdw->fw_size) {
2529 pvr2_trace(PVR2_TRACE_FIRMWARE,
2530 "Read firmware data offs=%d EOF",
2536 if (offs + cnt > hdw->fw_size) cnt = hdw->fw_size - offs;
2538 memcpy(buf,hdw->fw_buffer+offs,cnt);
2540 pvr2_trace(PVR2_TRACE_FIRMWARE,
2541 "Read firmware data offs=%d cnt=%d",
2544 } while (0); LOCK_GIVE(hdw->big_lock);
2550 int pvr2_hdw_v4l_get_minor_number(struct pvr2_hdw *hdw,
2551 enum pvr2_config index)
2554 case pvr2_config_mpeg: return hdw->v4l_minor_number_mpeg;
2555 case pvr2_config_radio: return hdw->v4l_minor_number_radio;
2561 /* Store a v4l minor device number */
2562 void pvr2_hdw_v4l_store_minor_number(struct pvr2_hdw *hdw,
2563 enum pvr2_config index,int v)
2566 case pvr2_config_mpeg: hdw->v4l_minor_number_mpeg = v;
2567 case pvr2_config_radio: hdw->v4l_minor_number_radio = v;
2573 static void pvr2_ctl_write_complete(struct urb *urb)
2575 struct pvr2_hdw *hdw = urb->context;
2576 hdw->ctl_write_pend_flag = 0;
2577 if (hdw->ctl_read_pend_flag) return;
2578 complete(&hdw->ctl_done);
2582 static void pvr2_ctl_read_complete(struct urb *urb)
2584 struct pvr2_hdw *hdw = urb->context;
2585 hdw->ctl_read_pend_flag = 0;
2586 if (hdw->ctl_write_pend_flag) return;
2587 complete(&hdw->ctl_done);
2591 static void pvr2_ctl_timeout(unsigned long data)
2593 struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
2594 if (hdw->ctl_write_pend_flag || hdw->ctl_read_pend_flag) {
2595 hdw->ctl_timeout_flag = !0;
2596 if (hdw->ctl_write_pend_flag)
2597 usb_unlink_urb(hdw->ctl_write_urb);
2598 if (hdw->ctl_read_pend_flag)
2599 usb_unlink_urb(hdw->ctl_read_urb);
2604 /* Issue a command and get a response from the device. This extended
2605 version includes a probe flag (which if set means that device errors
2606 should not be logged or treated as fatal) and a timeout in jiffies.
2607 This can be used to non-lethally probe the health of endpoint 1. */
2608 static int pvr2_send_request_ex(struct pvr2_hdw *hdw,
2609 unsigned int timeout,int probe_fl,
2610 void *write_data,unsigned int write_len,
2611 void *read_data,unsigned int read_len)
2615 struct timer_list timer;
2616 if (!hdw->ctl_lock_held) {
2617 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2618 "Attempted to execute control transfer"
2622 if ((!hdw->flag_ok) && !probe_fl) {
2623 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2624 "Attempted to execute control transfer"
2625 " when device not ok");
2628 if (!(hdw->ctl_read_urb && hdw->ctl_write_urb)) {
2630 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2631 "Attempted to execute control transfer"
2632 " when USB is disconnected");
2637 /* Ensure that we have sane parameters */
2638 if (!write_data) write_len = 0;
2639 if (!read_data) read_len = 0;
2640 if (write_len > PVR2_CTL_BUFFSIZE) {
2642 PVR2_TRACE_ERROR_LEGS,
2643 "Attempted to execute %d byte"
2644 " control-write transfer (limit=%d)",
2645 write_len,PVR2_CTL_BUFFSIZE);
2648 if (read_len > PVR2_CTL_BUFFSIZE) {
2650 PVR2_TRACE_ERROR_LEGS,
2651 "Attempted to execute %d byte"
2652 " control-read transfer (limit=%d)",
2653 write_len,PVR2_CTL_BUFFSIZE);
2656 if ((!write_len) && (!read_len)) {
2658 PVR2_TRACE_ERROR_LEGS,
2659 "Attempted to execute null control transfer?");
2664 hdw->cmd_debug_state = 1;
2666 hdw->cmd_debug_code = ((unsigned char *)write_data)[0];
2668 hdw->cmd_debug_code = 0;
2670 hdw->cmd_debug_write_len = write_len;
2671 hdw->cmd_debug_read_len = read_len;
2673 /* Initialize common stuff */
2674 init_completion(&hdw->ctl_done);
2675 hdw->ctl_timeout_flag = 0;
2676 hdw->ctl_write_pend_flag = 0;
2677 hdw->ctl_read_pend_flag = 0;
2679 timer.expires = jiffies + timeout;
2680 timer.data = (unsigned long)hdw;
2681 timer.function = pvr2_ctl_timeout;
2684 hdw->cmd_debug_state = 2;
2685 /* Transfer write data to internal buffer */
2686 for (idx = 0; idx < write_len; idx++) {
2687 hdw->ctl_write_buffer[idx] =
2688 ((unsigned char *)write_data)[idx];
2690 /* Initiate a write request */
2691 usb_fill_bulk_urb(hdw->ctl_write_urb,
2693 usb_sndbulkpipe(hdw->usb_dev,
2694 PVR2_CTL_WRITE_ENDPOINT),
2695 hdw->ctl_write_buffer,
2697 pvr2_ctl_write_complete,
2699 hdw->ctl_write_urb->actual_length = 0;
2700 hdw->ctl_write_pend_flag = !0;
2701 status = usb_submit_urb(hdw->ctl_write_urb,GFP_KERNEL);
2703 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2704 "Failed to submit write-control"
2705 " URB status=%d",status);
2706 hdw->ctl_write_pend_flag = 0;
2712 hdw->cmd_debug_state = 3;
2713 memset(hdw->ctl_read_buffer,0x43,read_len);
2714 /* Initiate a read request */
2715 usb_fill_bulk_urb(hdw->ctl_read_urb,
2717 usb_rcvbulkpipe(hdw->usb_dev,
2718 PVR2_CTL_READ_ENDPOINT),
2719 hdw->ctl_read_buffer,
2721 pvr2_ctl_read_complete,
2723 hdw->ctl_read_urb->actual_length = 0;
2724 hdw->ctl_read_pend_flag = !0;
2725 status = usb_submit_urb(hdw->ctl_read_urb,GFP_KERNEL);
2727 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2728 "Failed to submit read-control"
2729 " URB status=%d",status);
2730 hdw->ctl_read_pend_flag = 0;
2738 /* Now wait for all I/O to complete */
2739 hdw->cmd_debug_state = 4;
2740 while (hdw->ctl_write_pend_flag || hdw->ctl_read_pend_flag) {
2741 wait_for_completion(&hdw->ctl_done);
2743 hdw->cmd_debug_state = 5;
2746 del_timer_sync(&timer);
2748 hdw->cmd_debug_state = 6;
2751 if (hdw->ctl_timeout_flag) {
2752 status = -ETIMEDOUT;
2754 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2755 "Timed out control-write");
2761 /* Validate results of write request */
2762 if ((hdw->ctl_write_urb->status != 0) &&
2763 (hdw->ctl_write_urb->status != -ENOENT) &&
2764 (hdw->ctl_write_urb->status != -ESHUTDOWN) &&
2765 (hdw->ctl_write_urb->status != -ECONNRESET)) {
2766 /* USB subsystem is reporting some kind of failure
2768 status = hdw->ctl_write_urb->status;
2770 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2771 "control-write URB failure,"
2777 if (hdw->ctl_write_urb->actual_length < write_len) {
2778 /* Failed to write enough data */
2781 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2782 "control-write URB short,"
2783 " expected=%d got=%d",
2785 hdw->ctl_write_urb->actual_length);
2791 /* Validate results of read request */
2792 if ((hdw->ctl_read_urb->status != 0) &&
2793 (hdw->ctl_read_urb->status != -ENOENT) &&
2794 (hdw->ctl_read_urb->status != -ESHUTDOWN) &&
2795 (hdw->ctl_read_urb->status != -ECONNRESET)) {
2796 /* USB subsystem is reporting some kind of failure
2798 status = hdw->ctl_read_urb->status;
2800 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2801 "control-read URB failure,"
2807 if (hdw->ctl_read_urb->actual_length < read_len) {
2808 /* Failed to read enough data */
2811 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2812 "control-read URB short,"
2813 " expected=%d got=%d",
2815 hdw->ctl_read_urb->actual_length);
2819 /* Transfer retrieved data out from internal buffer */
2820 for (idx = 0; idx < read_len; idx++) {
2821 ((unsigned char *)read_data)[idx] =
2822 hdw->ctl_read_buffer[idx];
2828 hdw->cmd_debug_state = 0;
2829 if ((status < 0) && (!probe_fl)) {
2830 pvr2_hdw_render_useless_unlocked(hdw);
2836 int pvr2_send_request(struct pvr2_hdw *hdw,
2837 void *write_data,unsigned int write_len,
2838 void *read_data,unsigned int read_len)
2840 return pvr2_send_request_ex(hdw,HZ*4,0,
2841 write_data,write_len,
2842 read_data,read_len);
2845 int pvr2_write_register(struct pvr2_hdw *hdw, u16 reg, u32 data)
2849 LOCK_TAKE(hdw->ctl_lock);
2851 hdw->cmd_buffer[0] = 0x04; /* write register prefix */
2852 PVR2_DECOMPOSE_LE(hdw->cmd_buffer,1,data);
2853 hdw->cmd_buffer[5] = 0;
2854 hdw->cmd_buffer[6] = (reg >> 8) & 0xff;
2855 hdw->cmd_buffer[7] = reg & 0xff;
2858 ret = pvr2_send_request(hdw, hdw->cmd_buffer, 8, hdw->cmd_buffer, 0);
2860 LOCK_GIVE(hdw->ctl_lock);
2866 static int pvr2_read_register(struct pvr2_hdw *hdw, u16 reg, u32 *data)
2870 LOCK_TAKE(hdw->ctl_lock);
2872 hdw->cmd_buffer[0] = 0x05; /* read register prefix */
2873 hdw->cmd_buffer[1] = 0;
2874 hdw->cmd_buffer[2] = 0;
2875 hdw->cmd_buffer[3] = 0;
2876 hdw->cmd_buffer[4] = 0;
2877 hdw->cmd_buffer[5] = 0;
2878 hdw->cmd_buffer[6] = (reg >> 8) & 0xff;
2879 hdw->cmd_buffer[7] = reg & 0xff;
2881 ret |= pvr2_send_request(hdw, hdw->cmd_buffer, 8, hdw->cmd_buffer, 4);
2882 *data = PVR2_COMPOSE_LE(hdw->cmd_buffer,0);
2884 LOCK_GIVE(hdw->ctl_lock);
2890 static int pvr2_write_u16(struct pvr2_hdw *hdw, u16 data, int res)
2894 LOCK_TAKE(hdw->ctl_lock);
2896 hdw->cmd_buffer[0] = (data >> 8) & 0xff;
2897 hdw->cmd_buffer[1] = data & 0xff;
2899 ret = pvr2_send_request(hdw, hdw->cmd_buffer, 2, hdw->cmd_buffer, res);
2901 LOCK_GIVE(hdw->ctl_lock);
2907 static int pvr2_write_u8(struct pvr2_hdw *hdw, u8 data, int res)
2911 LOCK_TAKE(hdw->ctl_lock);
2913 hdw->cmd_buffer[0] = data;
2915 ret = pvr2_send_request(hdw, hdw->cmd_buffer, 1, hdw->cmd_buffer, res);
2917 LOCK_GIVE(hdw->ctl_lock);
2923 static void pvr2_hdw_render_useless_unlocked(struct pvr2_hdw *hdw)
2925 if (!hdw->flag_ok) return;
2926 pvr2_trace(PVR2_TRACE_INIT,"render_useless");
2928 if (hdw->vid_stream) {
2929 pvr2_stream_setup(hdw->vid_stream,NULL,0,0);
2931 hdw->flag_streaming_enabled = 0;
2932 hdw->subsys_enabled_mask = 0;
2936 void pvr2_hdw_render_useless(struct pvr2_hdw *hdw)
2938 LOCK_TAKE(hdw->ctl_lock);
2939 pvr2_hdw_render_useless_unlocked(hdw);
2940 LOCK_GIVE(hdw->ctl_lock);
2944 void pvr2_hdw_device_reset(struct pvr2_hdw *hdw)
2947 pvr2_trace(PVR2_TRACE_INIT,"Performing a device reset...");
2948 ret = usb_lock_device_for_reset(hdw->usb_dev,NULL);
2950 ret = usb_reset_device(hdw->usb_dev);
2951 usb_unlock_device(hdw->usb_dev);
2953 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2954 "Failed to lock USB device ret=%d",ret);
2956 if (init_pause_msec) {
2957 pvr2_trace(PVR2_TRACE_INFO,
2958 "Waiting %u msec for hardware to settle",
2960 msleep(init_pause_msec);
2966 void pvr2_hdw_cpureset_assert(struct pvr2_hdw *hdw,int val)
2972 if (!hdw->usb_dev) return;
2974 pvr2_trace(PVR2_TRACE_INIT,"cpureset_assert(%d)",val);
2976 da[0] = val ? 0x01 : 0x00;
2978 /* Write the CPUCS register on the 8051. The lsb of the register
2979 is the reset bit; a 1 asserts reset while a 0 clears it. */
2980 pipe = usb_sndctrlpipe(hdw->usb_dev, 0);
2981 ret = usb_control_msg(hdw->usb_dev,pipe,0xa0,0x40,0xe600,0,da,1,HZ);
2983 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2984 "cpureset_assert(%d) error=%d",val,ret);
2985 pvr2_hdw_render_useless(hdw);
2990 int pvr2_hdw_cmd_deep_reset(struct pvr2_hdw *hdw)
2993 LOCK_TAKE(hdw->ctl_lock); do {
2994 pvr2_trace(PVR2_TRACE_INIT,"Requesting uproc hard reset");
2996 hdw->cmd_buffer[0] = 0xdd;
2997 status = pvr2_send_request(hdw,hdw->cmd_buffer,1,NULL,0);
2998 } while (0); LOCK_GIVE(hdw->ctl_lock);
3003 int pvr2_hdw_cmd_powerup(struct pvr2_hdw *hdw)
3006 LOCK_TAKE(hdw->ctl_lock); do {
3007 pvr2_trace(PVR2_TRACE_INIT,"Requesting powerup");
3008 hdw->cmd_buffer[0] = 0xde;
3009 status = pvr2_send_request(hdw,hdw->cmd_buffer,1,NULL,0);
3010 } while (0); LOCK_GIVE(hdw->ctl_lock);
3015 int pvr2_hdw_cmd_decoder_reset(struct pvr2_hdw *hdw)
3017 if (!hdw->decoder_ctrl) {
3018 pvr2_trace(PVR2_TRACE_INIT,
3019 "Unable to reset decoder: nothing attached");
3023 if (!hdw->decoder_ctrl->force_reset) {
3024 pvr2_trace(PVR2_TRACE_INIT,
3025 "Unable to reset decoder: not implemented");
3029 pvr2_trace(PVR2_TRACE_INIT,
3030 "Requesting decoder reset");
3031 hdw->decoder_ctrl->force_reset(hdw->decoder_ctrl->ctxt);
3036 /* Stop / start video stream transport */
3037 static int pvr2_hdw_cmd_usbstream(struct pvr2_hdw *hdw,int runFl)
3040 LOCK_TAKE(hdw->ctl_lock); do {
3041 hdw->cmd_buffer[0] = (runFl ? 0x36 : 0x37);
3042 status = pvr2_send_request(hdw,hdw->cmd_buffer,1,NULL,0);
3043 } while (0); LOCK_GIVE(hdw->ctl_lock);
3045 hdw->subsys_enabled_mask =
3046 ((hdw->subsys_enabled_mask &
3047 ~(1<<PVR2_SUBSYS_B_USBSTREAM_RUN)) |
3048 (runFl ? (1<<PVR2_SUBSYS_B_USBSTREAM_RUN) : 0));
3054 void pvr2_hdw_get_debug_info(const struct pvr2_hdw *hdw,
3055 struct pvr2_hdw_debug_info *ptr)
3057 ptr->big_lock_held = hdw->big_lock_held;
3058 ptr->ctl_lock_held = hdw->ctl_lock_held;
3059 ptr->flag_ok = hdw->flag_ok;
3060 ptr->flag_disconnected = hdw->flag_disconnected;
3061 ptr->flag_init_ok = hdw->flag_init_ok;
3062 ptr->flag_streaming_enabled = hdw->flag_streaming_enabled;
3063 ptr->subsys_flags = hdw->subsys_enabled_mask;
3064 ptr->cmd_debug_state = hdw->cmd_debug_state;
3065 ptr->cmd_code = hdw->cmd_debug_code;
3066 ptr->cmd_debug_write_len = hdw->cmd_debug_write_len;
3067 ptr->cmd_debug_read_len = hdw->cmd_debug_read_len;
3068 ptr->cmd_debug_timeout = hdw->ctl_timeout_flag;
3069 ptr->cmd_debug_write_pend = hdw->ctl_write_pend_flag;
3070 ptr->cmd_debug_read_pend = hdw->ctl_read_pend_flag;
3071 ptr->cmd_debug_rstatus = hdw->ctl_read_urb->status;
3072 ptr->cmd_debug_wstatus = hdw->ctl_read_urb->status;
3076 int pvr2_hdw_gpio_get_dir(struct pvr2_hdw *hdw,u32 *dp)
3078 return pvr2_read_register(hdw,PVR2_GPIO_DIR,dp);
3082 int pvr2_hdw_gpio_get_out(struct pvr2_hdw *hdw,u32 *dp)
3084 return pvr2_read_register(hdw,PVR2_GPIO_OUT,dp);
3088 int pvr2_hdw_gpio_get_in(struct pvr2_hdw *hdw,u32 *dp)
3090 return pvr2_read_register(hdw,PVR2_GPIO_IN,dp);
3094 int pvr2_hdw_gpio_chg_dir(struct pvr2_hdw *hdw,u32 msk,u32 val)
3099 ret = pvr2_read_register(hdw,PVR2_GPIO_DIR,&cval);
3100 if (ret) return ret;
3101 nval = (cval & ~msk) | (val & msk);
3102 pvr2_trace(PVR2_TRACE_GPIO,
3103 "GPIO direction changing 0x%x:0x%x"
3104 " from 0x%x to 0x%x",
3108 pvr2_trace(PVR2_TRACE_GPIO,
3109 "GPIO direction changing to 0x%x",nval);
3111 return pvr2_write_register(hdw,PVR2_GPIO_DIR,nval);
3115 int pvr2_hdw_gpio_chg_out(struct pvr2_hdw *hdw,u32 msk,u32 val)
3120 ret = pvr2_read_register(hdw,PVR2_GPIO_OUT,&cval);
3121 if (ret) return ret;
3122 nval = (cval & ~msk) | (val & msk);
3123 pvr2_trace(PVR2_TRACE_GPIO,
3124 "GPIO output changing 0x%x:0x%x from 0x%x to 0x%x",
3128 pvr2_trace(PVR2_TRACE_GPIO,
3129 "GPIO output changing to 0x%x",nval);
3131 return pvr2_write_register(hdw,PVR2_GPIO_OUT,nval);
3135 /* Find I2C address of eeprom */
3136 static int pvr2_hdw_get_eeprom_addr(struct pvr2_hdw *hdw)
3139 LOCK_TAKE(hdw->ctl_lock); do {
3140 hdw->cmd_buffer[0] = 0xeb;
3141 result = pvr2_send_request(hdw,
3144 if (result < 0) break;
3145 result = hdw->cmd_buffer[0];
3146 } while(0); LOCK_GIVE(hdw->ctl_lock);
3151 int pvr2_hdw_register_access(struct pvr2_hdw *hdw,
3152 u32 chip_id,unsigned long reg_id,
3153 int setFl,u32 *val_ptr)
3155 #ifdef CONFIG_VIDEO_ADV_DEBUG
3156 struct list_head *item;
3157 struct pvr2_i2c_client *cp;
3158 struct v4l2_register req;
3162 req.i2c_id = chip_id;
3164 if (setFl) req.val = *val_ptr;
3165 mutex_lock(&hdw->i2c_list_lock); do {
3166 list_for_each(item,&hdw->i2c_clients) {
3167 cp = list_entry(item,struct pvr2_i2c_client,list);
3168 if (cp->client->driver->id != chip_id) continue;
3169 stat = pvr2_i2c_client_cmd(
3170 cp,(setFl ? VIDIOC_INT_S_REGISTER :
3171 VIDIOC_INT_G_REGISTER),&req);
3172 if (!setFl) *val_ptr = req.val;
3176 } while (0); mutex_unlock(&hdw->i2c_list_lock);
3188 Stuff for Emacs to see, in order to encourage consistent editing style:
3189 *** Local Variables: ***
3191 *** fill-column: 75 ***
3192 *** tab-width: 8 ***
3193 *** c-basic-offset: 8 ***