2 * linux/drivers/mmc/host/omap.c
4 * Copyright (C) 2004 Nokia Corporation
5 * Written by Tuukka Tikkanen and Juha Yrjölä<juha.yrjola@nokia.com>
6 * Misc hacks here and there by Tony Lindgren <tony@atomide.com>
7 * Other hacks (DMA, SD, etc) by David Brownell
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 #include <linux/module.h>
15 #include <linux/moduleparam.h>
16 #include <linux/init.h>
17 #include <linux/ioport.h>
18 #include <linux/platform_device.h>
19 #include <linux/interrupt.h>
20 #include <linux/dma-mapping.h>
21 #include <linux/delay.h>
22 #include <linux/spinlock.h>
23 #include <linux/timer.h>
24 #include <linux/mmc/mmc.h>
25 #include <linux/mmc/host.h>
26 #include <linux/mmc/card.h>
27 #include <linux/clk.h>
28 #include <linux/scatterlist.h>
32 #include <asm/mach-types.h>
34 #include <asm/arch/board.h>
35 #include <asm/arch/mmc.h>
36 #include <asm/arch/gpio.h>
37 #include <asm/arch/dma.h>
38 #include <asm/arch/mux.h>
39 #include <asm/arch/fpga.h>
40 #include <asm/arch/tps65010.h>
41 #include <asm/arch/board-sx1.h>
43 #define OMAP_MMC_REG_CMD 0x00
44 #define OMAP_MMC_REG_ARGL 0x04
45 #define OMAP_MMC_REG_ARGH 0x08
46 #define OMAP_MMC_REG_CON 0x0c
47 #define OMAP_MMC_REG_STAT 0x10
48 #define OMAP_MMC_REG_IE 0x14
49 #define OMAP_MMC_REG_CTO 0x18
50 #define OMAP_MMC_REG_DTO 0x1c
51 #define OMAP_MMC_REG_DATA 0x20
52 #define OMAP_MMC_REG_BLEN 0x24
53 #define OMAP_MMC_REG_NBLK 0x28
54 #define OMAP_MMC_REG_BUF 0x2c
55 #define OMAP_MMC_REG_SDIO 0x34
56 #define OMAP_MMC_REG_REV 0x3c
57 #define OMAP_MMC_REG_RSP0 0x40
58 #define OMAP_MMC_REG_RSP1 0x44
59 #define OMAP_MMC_REG_RSP2 0x48
60 #define OMAP_MMC_REG_RSP3 0x4c
61 #define OMAP_MMC_REG_RSP4 0x50
62 #define OMAP_MMC_REG_RSP5 0x54
63 #define OMAP_MMC_REG_RSP6 0x58
64 #define OMAP_MMC_REG_RSP7 0x5c
65 #define OMAP_MMC_REG_IOSR 0x60
66 #define OMAP_MMC_REG_SYSC 0x64
67 #define OMAP_MMC_REG_SYSS 0x68
69 #define OMAP_MMC_STAT_CARD_ERR (1 << 14)
70 #define OMAP_MMC_STAT_CARD_IRQ (1 << 13)
71 #define OMAP_MMC_STAT_OCR_BUSY (1 << 12)
72 #define OMAP_MMC_STAT_A_EMPTY (1 << 11)
73 #define OMAP_MMC_STAT_A_FULL (1 << 10)
74 #define OMAP_MMC_STAT_CMD_CRC (1 << 8)
75 #define OMAP_MMC_STAT_CMD_TOUT (1 << 7)
76 #define OMAP_MMC_STAT_DATA_CRC (1 << 6)
77 #define OMAP_MMC_STAT_DATA_TOUT (1 << 5)
78 #define OMAP_MMC_STAT_END_BUSY (1 << 4)
79 #define OMAP_MMC_STAT_END_OF_DATA (1 << 3)
80 #define OMAP_MMC_STAT_CARD_BUSY (1 << 2)
81 #define OMAP_MMC_STAT_END_OF_CMD (1 << 0)
83 #define OMAP_MMC_READ(host, reg) __raw_readw((host)->virt_base + OMAP_MMC_REG_##reg)
84 #define OMAP_MMC_WRITE(host, reg, val) __raw_writew((val), (host)->virt_base + OMAP_MMC_REG_##reg)
89 #define OMAP_MMC_CMDTYPE_BC 0
90 #define OMAP_MMC_CMDTYPE_BCR 1
91 #define OMAP_MMC_CMDTYPE_AC 2
92 #define OMAP_MMC_CMDTYPE_ADTC 3
95 #define DRIVER_NAME "mmci-omap"
97 /* Specifies how often in millisecs to poll for card status changes
98 * when the cover switch is open */
99 #define OMAP_MMC_SWITCH_POLL_DELAY 500
101 struct mmc_omap_host;
103 struct mmc_omap_slot {
108 unsigned int fclk_freq;
111 struct work_struct switch_work;
112 struct timer_list switch_timer;
115 struct mmc_request *mrq;
116 struct mmc_omap_host *host;
117 struct mmc_host *mmc;
118 struct omap_mmc_slot_data *pdata;
121 struct mmc_omap_host {
124 struct mmc_request * mrq;
125 struct mmc_command * cmd;
126 struct mmc_data * data;
127 struct mmc_host * mmc;
129 unsigned char id; /* 16xx chips have 2 MMC blocks */
132 struct resource *mem_res;
133 void __iomem *virt_base;
134 unsigned int phys_base;
136 unsigned char bus_mode;
137 unsigned char hw_bus_mode;
139 struct work_struct cmd_abort;
140 struct timer_list cmd_timer;
145 u32 buffer_bytes_left;
146 u32 total_bytes_left;
149 unsigned brs_received:1, dma_done:1;
150 unsigned dma_is_read:1;
151 unsigned dma_in_use:1;
154 struct timer_list dma_timer;
159 struct mmc_omap_slot *slots[OMAP_MMC_MAX_SLOTS];
160 struct mmc_omap_slot *current_slot;
161 spinlock_t slot_lock;
162 wait_queue_head_t slot_wq;
165 struct omap_mmc_platform_data *pdata;
168 static void mmc_omap_select_slot(struct mmc_omap_slot *slot, int claimed)
170 struct mmc_omap_host *host = slot->host;
175 spin_lock_irqsave(&host->slot_lock, flags);
176 while (host->mmc != NULL) {
177 spin_unlock_irqrestore(&host->slot_lock, flags);
178 wait_event(host->slot_wq, host->mmc == NULL);
179 spin_lock_irqsave(&host->slot_lock, flags);
181 host->mmc = slot->mmc;
182 spin_unlock_irqrestore(&host->slot_lock, flags);
184 clk_enable(host->fclk);
185 if (host->current_slot != slot) {
186 if (host->pdata->switch_slot != NULL)
187 host->pdata->switch_slot(mmc_dev(slot->mmc), slot->id);
188 host->current_slot = slot;
191 /* Doing the dummy read here seems to work around some bug
192 * at least in OMAP24xx silicon where the command would not
193 * start after writing the CMD register. Sigh. */
194 OMAP_MMC_READ(host, CON);
196 OMAP_MMC_WRITE(host, CON, slot->saved_con);
199 static void mmc_omap_start_request(struct mmc_omap_host *host,
200 struct mmc_request *req);
202 static void mmc_omap_release_slot(struct mmc_omap_slot *slot)
204 struct mmc_omap_host *host = slot->host;
208 BUG_ON(slot == NULL || host->mmc == NULL);
209 clk_disable(host->fclk);
211 spin_lock_irqsave(&host->slot_lock, flags);
212 /* Check for any pending requests */
213 for (i = 0; i < host->nr_slots; i++) {
214 struct mmc_omap_slot *new_slot;
215 struct mmc_request *rq;
217 if (host->slots[i] == NULL || host->slots[i]->mrq == NULL)
220 new_slot = host->slots[i];
221 /* The current slot should not have a request in queue */
222 BUG_ON(new_slot == host->current_slot);
224 host->mmc = new_slot->mmc;
225 spin_unlock_irqrestore(&host->slot_lock, flags);
226 mmc_omap_select_slot(new_slot, 1);
228 new_slot->mrq = NULL;
229 mmc_omap_start_request(host, rq);
234 wake_up(&host->slot_wq);
235 spin_unlock_irqrestore(&host->slot_lock, flags);
239 int mmc_omap_cover_is_open(struct mmc_omap_slot *slot)
241 if (slot->pdata->get_cover_state)
242 return slot->pdata->get_cover_state(mmc_dev(slot->mmc), slot->id);
247 mmc_omap_show_cover_switch(struct device *dev, struct device_attribute *attr,
250 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
251 struct mmc_omap_slot *slot = mmc_priv(mmc);
253 return sprintf(buf, "%s\n", mmc_omap_cover_is_open(slot) ? "open" :
257 static DEVICE_ATTR(cover_switch, S_IRUGO, mmc_omap_show_cover_switch, NULL);
259 /* Access to the R/O switch is required for production testing
262 mmc_omap_show_ro(struct device *dev, struct device_attribute *attr, char *buf)
264 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
265 struct mmc_omap_slot *slot = mmc_priv(mmc);
267 return sprintf(buf, "%d\n", slot->pdata->get_ro(mmc_dev(mmc),
271 static DEVICE_ATTR(ro, S_IRUGO, mmc_omap_show_ro, NULL);
274 mmc_omap_show_slot_name(struct device *dev, struct device_attribute *attr,
277 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
278 struct mmc_omap_slot *slot = mmc_priv(mmc);
280 return sprintf(buf, "%s\n", slot->pdata->name);
283 static DEVICE_ATTR(slot_name, S_IRUGO, mmc_omap_show_slot_name, NULL);
286 mmc_omap_start_command(struct mmc_omap_host *host, struct mmc_command *cmd)
297 /* Our hardware needs to know exact type */
298 switch (mmc_resp_type(cmd)) {
303 /* resp 1, 1b, 6, 7 */
313 dev_err(mmc_dev(host->mmc), "Invalid response type: %04x\n", mmc_resp_type(cmd));
317 if (mmc_cmd_type(cmd) == MMC_CMD_ADTC) {
318 cmdtype = OMAP_MMC_CMDTYPE_ADTC;
319 } else if (mmc_cmd_type(cmd) == MMC_CMD_BC) {
320 cmdtype = OMAP_MMC_CMDTYPE_BC;
321 } else if (mmc_cmd_type(cmd) == MMC_CMD_BCR) {
322 cmdtype = OMAP_MMC_CMDTYPE_BCR;
324 cmdtype = OMAP_MMC_CMDTYPE_AC;
327 cmdreg = cmd->opcode | (resptype << 8) | (cmdtype << 12);
329 if (host->current_slot->bus_mode == MMC_BUSMODE_OPENDRAIN)
332 if (cmd->flags & MMC_RSP_BUSY)
335 if (host->data && !(host->data->flags & MMC_DATA_WRITE))
338 mod_timer(&host->cmd_timer, jiffies + HZ/2);
340 OMAP_MMC_WRITE(host, CTO, 200);
341 OMAP_MMC_WRITE(host, ARGL, cmd->arg & 0xffff);
342 OMAP_MMC_WRITE(host, ARGH, cmd->arg >> 16);
343 OMAP_MMC_WRITE(host, IE,
344 OMAP_MMC_STAT_A_EMPTY | OMAP_MMC_STAT_A_FULL |
345 OMAP_MMC_STAT_CMD_CRC | OMAP_MMC_STAT_CMD_TOUT |
346 OMAP_MMC_STAT_DATA_CRC | OMAP_MMC_STAT_DATA_TOUT |
347 OMAP_MMC_STAT_END_OF_CMD | OMAP_MMC_STAT_CARD_ERR |
348 OMAP_MMC_STAT_END_OF_DATA);
349 OMAP_MMC_WRITE(host, CMD, cmdreg);
353 mmc_omap_release_dma(struct mmc_omap_host *host, struct mmc_data *data,
356 enum dma_data_direction dma_data_dir;
358 BUG_ON(host->dma_ch < 0);
360 omap_stop_dma(host->dma_ch);
361 /* Release DMA channel lazily */
362 mod_timer(&host->dma_timer, jiffies + HZ);
363 if (data->flags & MMC_DATA_WRITE)
364 dma_data_dir = DMA_TO_DEVICE;
366 dma_data_dir = DMA_FROM_DEVICE;
367 dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->sg_len,
372 mmc_omap_xfer_done(struct mmc_omap_host *host, struct mmc_data *data)
374 if (host->dma_in_use)
375 mmc_omap_release_dma(host, data, data->error);
380 /* NOTE: MMC layer will sometimes poll-wait CMD13 next, issuing
381 * dozens of requests until the card finishes writing data.
382 * It'd be cheaper to just wait till an EOFB interrupt arrives...
386 struct mmc_host *mmc;
390 mmc_omap_release_slot(host->current_slot);
391 mmc_request_done(mmc, data->mrq);
395 mmc_omap_start_command(host, data->stop);
399 mmc_omap_send_abort(struct mmc_omap_host *host)
401 struct mmc_omap_slot *slot = host->current_slot;
402 unsigned int restarts, passes, timeout;
405 /* Sending abort takes 80 clocks. Have some extra and round up */
406 timeout = (120*1000000 + slot->fclk_freq - 1)/slot->fclk_freq;
408 while (restarts < 10000) {
409 OMAP_MMC_WRITE(host, STAT, 0xFFFF);
410 OMAP_MMC_WRITE(host, CMD, (3 << 12) | (1 << 7));
413 while (passes < timeout) {
414 stat = OMAP_MMC_READ(host, STAT);
415 if (stat & OMAP_MMC_STAT_END_OF_CMD)
424 OMAP_MMC_WRITE(host, STAT, stat);
428 mmc_omap_abort_xfer(struct mmc_omap_host *host, struct mmc_data *data)
432 if (host->dma_in_use)
433 mmc_omap_release_dma(host, data, 1);
438 ie = OMAP_MMC_READ(host, IE);
439 OMAP_MMC_WRITE(host, IE, 0);
440 OMAP_MMC_WRITE(host, IE, ie);
441 mmc_omap_send_abort(host);
445 mmc_omap_end_of_data(struct mmc_omap_host *host, struct mmc_data *data)
450 if (!host->dma_in_use) {
451 mmc_omap_xfer_done(host, data);
455 spin_lock_irqsave(&host->dma_lock, flags);
459 host->brs_received = 1;
460 spin_unlock_irqrestore(&host->dma_lock, flags);
462 mmc_omap_xfer_done(host, data);
466 mmc_omap_dma_timer(unsigned long data)
468 struct mmc_omap_host *host = (struct mmc_omap_host *) data;
470 BUG_ON(host->dma_ch < 0);
471 omap_free_dma(host->dma_ch);
476 mmc_omap_dma_done(struct mmc_omap_host *host, struct mmc_data *data)
482 spin_lock_irqsave(&host->dma_lock, flags);
483 if (host->brs_received)
487 spin_unlock_irqrestore(&host->dma_lock, flags);
489 mmc_omap_xfer_done(host, data);
493 mmc_omap_cmd_done(struct mmc_omap_host *host, struct mmc_command *cmd)
497 del_timer(&host->cmd_timer);
499 if (cmd->flags & MMC_RSP_PRESENT) {
500 if (cmd->flags & MMC_RSP_136) {
501 /* response type 2 */
503 OMAP_MMC_READ(host, RSP0) |
504 (OMAP_MMC_READ(host, RSP1) << 16);
506 OMAP_MMC_READ(host, RSP2) |
507 (OMAP_MMC_READ(host, RSP3) << 16);
509 OMAP_MMC_READ(host, RSP4) |
510 (OMAP_MMC_READ(host, RSP5) << 16);
512 OMAP_MMC_READ(host, RSP6) |
513 (OMAP_MMC_READ(host, RSP7) << 16);
515 /* response types 1, 1b, 3, 4, 5, 6 */
517 OMAP_MMC_READ(host, RSP6) |
518 (OMAP_MMC_READ(host, RSP7) << 16);
522 if (host->data == NULL || cmd->error) {
523 struct mmc_host *mmc;
525 if (host->data != NULL)
526 mmc_omap_abort_xfer(host, host->data);
529 mmc_omap_release_slot(host->current_slot);
530 mmc_request_done(mmc, cmd->mrq);
535 * Abort stuck command. Can occur when card is removed while it is being
538 static void mmc_omap_abort_command(struct work_struct *work)
540 struct mmc_omap_host *host = container_of(work, struct mmc_omap_host,
544 ie = OMAP_MMC_READ(host, IE);
545 OMAP_MMC_WRITE(host, IE, 0);
548 OMAP_MMC_WRITE(host, IE, ie);
552 dev_dbg(mmc_dev(host->mmc), "Aborting stuck command CMD%d\n",
555 if (host->data && host->dma_in_use)
556 mmc_omap_release_dma(host, host->data, 1);
561 mmc_omap_send_abort(host);
562 host->cmd->error = -ETIMEDOUT;
563 mmc_omap_cmd_done(host, host->cmd);
564 OMAP_MMC_WRITE(host, IE, ie);
568 mmc_omap_cmd_timer(unsigned long data)
570 struct mmc_omap_host *host = (struct mmc_omap_host *) data;
572 schedule_work(&host->cmd_abort);
577 mmc_omap_sg_to_buf(struct mmc_omap_host *host)
579 struct scatterlist *sg;
581 sg = host->data->sg + host->sg_idx;
582 host->buffer_bytes_left = sg->length;
583 host->buffer = sg_virt(sg);
584 if (host->buffer_bytes_left > host->total_bytes_left)
585 host->buffer_bytes_left = host->total_bytes_left;
590 mmc_omap_xfer_data(struct mmc_omap_host *host, int write)
594 if (host->buffer_bytes_left == 0) {
596 BUG_ON(host->sg_idx == host->sg_len);
597 mmc_omap_sg_to_buf(host);
600 if (n > host->buffer_bytes_left)
601 n = host->buffer_bytes_left;
602 host->buffer_bytes_left -= n;
603 host->total_bytes_left -= n;
604 host->data->bytes_xfered += n;
607 __raw_writesw(host->virt_base + OMAP_MMC_REG_DATA, host->buffer, n);
609 __raw_readsw(host->virt_base + OMAP_MMC_REG_DATA, host->buffer, n);
613 static inline void mmc_omap_report_irq(u16 status)
615 static const char *mmc_omap_status_bits[] = {
616 "EOC", "CD", "CB", "BRS", "EOFB", "DTO", "DCRC", "CTO",
617 "CCRC", "CRW", "AF", "AE", "OCRB", "CIRQ", "CERR"
621 for (i = 0; i < ARRAY_SIZE(mmc_omap_status_bits); i++)
622 if (status & (1 << i)) {
625 printk("%s", mmc_omap_status_bits[i]);
630 static irqreturn_t mmc_omap_irq(int irq, void *dev_id)
632 struct mmc_omap_host * host = (struct mmc_omap_host *)dev_id;
636 int transfer_error, cmd_error;
638 if (host->cmd == NULL && host->data == NULL) {
639 status = OMAP_MMC_READ(host, STAT);
640 dev_info(mmc_dev(host->slots[0]->mmc),
641 "Spurious IRQ 0x%04x\n", status);
643 OMAP_MMC_WRITE(host, STAT, status);
644 OMAP_MMC_WRITE(host, IE, 0);
654 while ((status = OMAP_MMC_READ(host, STAT)) != 0) {
657 OMAP_MMC_WRITE(host, STAT, status);
658 if (host->cmd != NULL)
659 cmd = host->cmd->opcode;
662 #ifdef CONFIG_MMC_DEBUG
663 dev_dbg(mmc_dev(host->mmc), "MMC IRQ %04x (CMD %d): ",
665 mmc_omap_report_irq(status);
668 if (host->total_bytes_left) {
669 if ((status & OMAP_MMC_STAT_A_FULL) ||
670 (status & OMAP_MMC_STAT_END_OF_DATA))
671 mmc_omap_xfer_data(host, 0);
672 if (status & OMAP_MMC_STAT_A_EMPTY)
673 mmc_omap_xfer_data(host, 1);
676 if (status & OMAP_MMC_STAT_END_OF_DATA)
679 if (status & OMAP_MMC_STAT_DATA_TOUT) {
680 dev_dbg(mmc_dev(host->mmc), "data timeout (CMD%d)\n",
683 host->data->error = -ETIMEDOUT;
688 if (status & OMAP_MMC_STAT_DATA_CRC) {
690 host->data->error = -EILSEQ;
691 dev_dbg(mmc_dev(host->mmc),
692 "data CRC error, bytes left %d\n",
693 host->total_bytes_left);
696 dev_dbg(mmc_dev(host->mmc), "data CRC error\n");
700 if (status & OMAP_MMC_STAT_CMD_TOUT) {
701 /* Timeouts are routine with some commands */
703 struct mmc_omap_slot *slot =
705 if (host->cmd->opcode != MMC_ALL_SEND_CID &&
706 host->cmd->opcode != MMC_SEND_OP_COND &&
707 host->cmd->opcode != MMC_APP_CMD &&
709 !mmc_omap_cover_is_open(slot)))
710 dev_err(mmc_dev(host->mmc),
711 "command timeout (CMD%d)\n",
713 host->cmd->error = -ETIMEDOUT;
719 if (status & OMAP_MMC_STAT_CMD_CRC) {
721 dev_err(mmc_dev(host->mmc),
722 "command CRC error (CMD%d, arg 0x%08x)\n",
723 cmd, host->cmd->arg);
724 host->cmd->error = -EILSEQ;
728 dev_err(mmc_dev(host->mmc),
729 "command CRC error without cmd?\n");
732 if (status & OMAP_MMC_STAT_CARD_ERR) {
733 dev_dbg(mmc_dev(host->mmc),
734 "ignoring card status error (CMD%d)\n",
740 * NOTE: On 1610 the END_OF_CMD may come too early when
743 if ((status & OMAP_MMC_STAT_END_OF_CMD) &&
744 (!(status & OMAP_MMC_STAT_A_EMPTY))) {
750 mmc_omap_cmd_done(host, host->cmd);
751 if (host->data != NULL) {
753 mmc_omap_xfer_done(host, host->data);
754 else if (end_transfer)
755 mmc_omap_end_of_data(host, host->data);
761 void omap_mmc_notify_cover_event(struct device *dev, int slot, int is_closed)
763 struct mmc_omap_host *host = dev_get_drvdata(dev);
765 BUG_ON(slot >= host->nr_slots);
767 /* Other subsystems can call in here before we're initialised. */
768 if (host->nr_slots == 0 || !host->slots[slot])
771 schedule_work(&host->slots[slot]->switch_work);
774 static void mmc_omap_switch_timer(unsigned long arg)
776 struct mmc_omap_slot *slot = (struct mmc_omap_slot *) arg;
778 schedule_work(&slot->switch_work);
781 static void mmc_omap_cover_handler(struct work_struct *work)
783 struct mmc_omap_slot *slot = container_of(work, struct mmc_omap_slot,
787 cover_open = mmc_omap_cover_is_open(slot);
788 if (cover_open != slot->cover_open) {
789 sysfs_notify(&slot->mmc->class_dev.kobj, NULL, "cover_switch");
790 slot->cover_open = cover_open;
791 dev_info(mmc_dev(slot->mmc), "cover is now %s\n",
792 cover_open ? "open" : "closed");
794 mmc_detect_change(slot->mmc, slot->id);
797 /* Prepare to transfer the next segment of a scatterlist */
799 mmc_omap_prepare_dma(struct mmc_omap_host *host, struct mmc_data *data)
801 int dma_ch = host->dma_ch;
802 unsigned long data_addr;
805 struct scatterlist *sg = &data->sg[host->sg_idx];
810 data_addr = host->phys_base + OMAP_MMC_REG_DATA;
812 count = sg_dma_len(sg);
814 if ((data->blocks == 1) && (count > data->blksz))
817 host->dma_len = count;
819 /* FIFO is 16x2 bytes on 15xx, and 32x2 bytes on 16xx and 24xx.
820 * Use 16 or 32 word frames when the blocksize is at least that large.
821 * Blocksize is usually 512 bytes; but not for some SD reads.
823 if (cpu_is_omap15xx() && frame > 32)
830 if (!(data->flags & MMC_DATA_WRITE)) {
831 buf = 0x800f | ((frame - 1) << 8);
833 if (cpu_class_is_omap1()) {
834 src_port = OMAP_DMA_PORT_TIPB;
835 dst_port = OMAP_DMA_PORT_EMIFF;
837 if (cpu_is_omap24xx())
838 sync_dev = OMAP24XX_DMA_MMC1_RX;
840 omap_set_dma_src_params(dma_ch, src_port,
841 OMAP_DMA_AMODE_CONSTANT,
843 omap_set_dma_dest_params(dma_ch, dst_port,
844 OMAP_DMA_AMODE_POST_INC,
845 sg_dma_address(sg), 0, 0);
846 omap_set_dma_dest_data_pack(dma_ch, 1);
847 omap_set_dma_dest_burst_mode(dma_ch, OMAP_DMA_DATA_BURST_4);
849 buf = 0x0f80 | ((frame - 1) << 0);
851 if (cpu_class_is_omap1()) {
852 src_port = OMAP_DMA_PORT_EMIFF;
853 dst_port = OMAP_DMA_PORT_TIPB;
855 if (cpu_is_omap24xx())
856 sync_dev = OMAP24XX_DMA_MMC1_TX;
858 omap_set_dma_dest_params(dma_ch, dst_port,
859 OMAP_DMA_AMODE_CONSTANT,
861 omap_set_dma_src_params(dma_ch, src_port,
862 OMAP_DMA_AMODE_POST_INC,
863 sg_dma_address(sg), 0, 0);
864 omap_set_dma_src_data_pack(dma_ch, 1);
865 omap_set_dma_src_burst_mode(dma_ch, OMAP_DMA_DATA_BURST_4);
868 /* Max limit for DMA frame count is 0xffff */
869 BUG_ON(count > 0xffff);
871 OMAP_MMC_WRITE(host, BUF, buf);
872 omap_set_dma_transfer_params(dma_ch, OMAP_DMA_DATA_TYPE_S16,
873 frame, count, OMAP_DMA_SYNC_FRAME,
877 /* A scatterlist segment completed */
878 static void mmc_omap_dma_cb(int lch, u16 ch_status, void *data)
880 struct mmc_omap_host *host = (struct mmc_omap_host *) data;
881 struct mmc_data *mmcdat = host->data;
883 if (unlikely(host->dma_ch < 0)) {
884 dev_err(mmc_dev(host->mmc),
885 "DMA callback while DMA not enabled\n");
888 /* FIXME: We really should do something to _handle_ the errors */
889 if (ch_status & OMAP1_DMA_TOUT_IRQ) {
890 dev_err(mmc_dev(host->mmc),"DMA timeout\n");
893 if (ch_status & OMAP_DMA_DROP_IRQ) {
894 dev_err(mmc_dev(host->mmc), "DMA sync error\n");
897 if (!(ch_status & OMAP_DMA_BLOCK_IRQ)) {
900 mmcdat->bytes_xfered += host->dma_len;
902 if (host->sg_idx < host->sg_len) {
903 mmc_omap_prepare_dma(host, host->data);
904 omap_start_dma(host->dma_ch);
906 mmc_omap_dma_done(host, host->data);
909 static int mmc_omap_get_dma_channel(struct mmc_omap_host *host, struct mmc_data *data)
911 const char *dev_name;
912 int sync_dev, dma_ch, is_read, r;
914 is_read = !(data->flags & MMC_DATA_WRITE);
915 del_timer_sync(&host->dma_timer);
916 if (host->dma_ch >= 0) {
917 if (is_read == host->dma_is_read)
919 omap_free_dma(host->dma_ch);
925 sync_dev = OMAP_DMA_MMC_RX;
926 dev_name = "MMC1 read";
928 sync_dev = OMAP_DMA_MMC2_RX;
929 dev_name = "MMC2 read";
933 sync_dev = OMAP_DMA_MMC_TX;
934 dev_name = "MMC1 write";
936 sync_dev = OMAP_DMA_MMC2_TX;
937 dev_name = "MMC2 write";
940 r = omap_request_dma(sync_dev, dev_name, mmc_omap_dma_cb,
943 dev_dbg(mmc_dev(host->mmc), "omap_request_dma() failed with %d\n", r);
946 host->dma_ch = dma_ch;
947 host->dma_is_read = is_read;
952 static inline void set_cmd_timeout(struct mmc_omap_host *host, struct mmc_request *req)
956 reg = OMAP_MMC_READ(host, SDIO);
958 OMAP_MMC_WRITE(host, SDIO, reg);
959 /* Set maximum timeout */
960 OMAP_MMC_WRITE(host, CTO, 0xff);
963 static inline void set_data_timeout(struct mmc_omap_host *host, struct mmc_request *req)
965 unsigned int timeout, cycle_ns;
968 cycle_ns = 1000000000 / host->current_slot->fclk_freq;
969 timeout = req->data->timeout_ns / cycle_ns;
970 timeout += req->data->timeout_clks;
972 /* Check if we need to use timeout multiplier register */
973 reg = OMAP_MMC_READ(host, SDIO);
974 if (timeout > 0xffff) {
979 OMAP_MMC_WRITE(host, SDIO, reg);
980 OMAP_MMC_WRITE(host, DTO, timeout);
984 mmc_omap_prepare_data(struct mmc_omap_host *host, struct mmc_request *req)
986 struct mmc_data *data = req->data;
987 int i, use_dma, block_size;
992 OMAP_MMC_WRITE(host, BLEN, 0);
993 OMAP_MMC_WRITE(host, NBLK, 0);
994 OMAP_MMC_WRITE(host, BUF, 0);
995 host->dma_in_use = 0;
996 set_cmd_timeout(host, req);
1000 block_size = data->blksz;
1002 OMAP_MMC_WRITE(host, NBLK, data->blocks - 1);
1003 OMAP_MMC_WRITE(host, BLEN, block_size - 1);
1004 set_data_timeout(host, req);
1006 /* cope with calling layer confusion; it issues "single
1007 * block" writes using multi-block scatterlists.
1009 sg_len = (data->blocks == 1) ? 1 : data->sg_len;
1011 /* Only do DMA for entire blocks */
1012 use_dma = host->use_dma;
1014 for (i = 0; i < sg_len; i++) {
1015 if ((data->sg[i].length % block_size) != 0) {
1024 if (mmc_omap_get_dma_channel(host, data) == 0) {
1025 enum dma_data_direction dma_data_dir;
1027 if (data->flags & MMC_DATA_WRITE)
1028 dma_data_dir = DMA_TO_DEVICE;
1030 dma_data_dir = DMA_FROM_DEVICE;
1032 host->sg_len = dma_map_sg(mmc_dev(host->mmc), data->sg,
1033 sg_len, dma_data_dir);
1034 host->total_bytes_left = 0;
1035 mmc_omap_prepare_dma(host, req->data);
1036 host->brs_received = 0;
1038 host->dma_in_use = 1;
1043 /* Revert to PIO? */
1045 OMAP_MMC_WRITE(host, BUF, 0x1f1f);
1046 host->total_bytes_left = data->blocks * block_size;
1047 host->sg_len = sg_len;
1048 mmc_omap_sg_to_buf(host);
1049 host->dma_in_use = 0;
1053 static void mmc_omap_start_request(struct mmc_omap_host *host,
1054 struct mmc_request *req)
1056 BUG_ON(host->mrq != NULL);
1060 /* only touch fifo AFTER the controller readies it */
1061 mmc_omap_prepare_data(host, req);
1062 mmc_omap_start_command(host, req->cmd);
1063 if (host->dma_in_use)
1064 omap_start_dma(host->dma_ch);
1065 BUG_ON(irqs_disabled());
1068 static void mmc_omap_request(struct mmc_host *mmc, struct mmc_request *req)
1070 struct mmc_omap_slot *slot = mmc_priv(mmc);
1071 struct mmc_omap_host *host = slot->host;
1072 unsigned long flags;
1074 spin_lock_irqsave(&host->slot_lock, flags);
1075 if (host->mmc != NULL) {
1076 BUG_ON(slot->mrq != NULL);
1078 spin_unlock_irqrestore(&host->slot_lock, flags);
1082 spin_unlock_irqrestore(&host->slot_lock, flags);
1083 mmc_omap_select_slot(slot, 1);
1084 mmc_omap_start_request(host, req);
1087 static void mmc_omap_set_power(struct mmc_omap_slot *slot, int power_on,
1090 struct mmc_omap_host *host;
1094 if (slot->pdata->set_power != NULL)
1095 slot->pdata->set_power(mmc_dev(slot->mmc), slot->id, power_on,
1098 if (cpu_is_omap24xx()) {
1102 w = OMAP_MMC_READ(host, CON);
1103 OMAP_MMC_WRITE(host, CON, w | (1 << 11));
1105 w = OMAP_MMC_READ(host, CON);
1106 OMAP_MMC_WRITE(host, CON, w & ~(1 << 11));
1111 static int mmc_omap_calc_divisor(struct mmc_host *mmc, struct mmc_ios *ios)
1113 struct mmc_omap_slot *slot = mmc_priv(mmc);
1114 struct mmc_omap_host *host = slot->host;
1115 int func_clk_rate = clk_get_rate(host->fclk);
1118 if (ios->clock == 0)
1121 dsor = func_clk_rate / ios->clock;
1125 if (func_clk_rate / dsor > ios->clock)
1131 slot->fclk_freq = func_clk_rate / dsor;
1133 if (ios->bus_width == MMC_BUS_WIDTH_4)
1139 static void mmc_omap_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1141 struct mmc_omap_slot *slot = mmc_priv(mmc);
1142 struct mmc_omap_host *host = slot->host;
1145 dsor = mmc_omap_calc_divisor(mmc, ios);
1147 mmc_omap_select_slot(slot, 0);
1149 if (ios->vdd != slot->vdd)
1150 slot->vdd = ios->vdd;
1152 switch (ios->power_mode) {
1154 mmc_omap_set_power(slot, 0, ios->vdd);
1157 /* Cannot touch dsor yet, just power up MMC */
1158 mmc_omap_set_power(slot, 1, ios->vdd);
1165 if (slot->bus_mode != ios->bus_mode) {
1166 if (slot->pdata->set_bus_mode != NULL)
1167 slot->pdata->set_bus_mode(mmc_dev(mmc), slot->id,
1169 slot->bus_mode = ios->bus_mode;
1172 /* On insanely high arm_per frequencies something sometimes
1173 * goes somehow out of sync, and the POW bit is not being set,
1174 * which results in the while loop below getting stuck.
1175 * Writing to the CON register twice seems to do the trick. */
1176 for (i = 0; i < 2; i++)
1177 OMAP_MMC_WRITE(host, CON, dsor);
1178 slot->saved_con = dsor;
1179 if (ios->power_mode == MMC_POWER_ON) {
1180 /* Send clock cycles, poll completion */
1181 OMAP_MMC_WRITE(host, IE, 0);
1182 OMAP_MMC_WRITE(host, STAT, 0xffff);
1183 OMAP_MMC_WRITE(host, CMD, 1 << 7);
1184 while ((OMAP_MMC_READ(host, STAT) & 1) == 0);
1185 OMAP_MMC_WRITE(host, STAT, 1);
1189 mmc_omap_release_slot(slot);
1192 static int mmc_omap_get_ro(struct mmc_host *mmc)
1194 struct mmc_omap_slot *slot = mmc_priv(mmc);
1196 if (slot->pdata->get_ro != NULL)
1197 return slot->pdata->get_ro(mmc_dev(mmc), slot->id);
1201 static const struct mmc_host_ops mmc_omap_ops = {
1202 .request = mmc_omap_request,
1203 .set_ios = mmc_omap_set_ios,
1204 .get_ro = mmc_omap_get_ro,
1207 static int __init mmc_omap_new_slot(struct mmc_omap_host *host, int id)
1209 struct mmc_omap_slot *slot = NULL;
1210 struct mmc_host *mmc;
1213 mmc = mmc_alloc_host(sizeof(struct mmc_omap_slot), host->dev);
1217 slot = mmc_priv(mmc);
1221 slot->pdata = &host->pdata->slots[id];
1223 host->slots[id] = slot;
1225 mmc->caps = MMC_CAP_MULTIWRITE | MMC_CAP_MMC_HIGHSPEED |
1226 MMC_CAP_SD_HIGHSPEED;
1227 if (host->pdata->conf.wire4)
1228 mmc->caps |= MMC_CAP_4_BIT_DATA;
1230 mmc->ops = &mmc_omap_ops;
1231 mmc->f_min = 400000;
1233 if (cpu_class_is_omap2())
1234 mmc->f_max = 48000000;
1236 mmc->f_max = 24000000;
1237 if (host->pdata->max_freq)
1238 mmc->f_max = min(host->pdata->max_freq, mmc->f_max);
1239 mmc->ocr_avail = slot->pdata->ocr_mask;
1241 /* Use scatterlist DMA to reduce per-transfer costs.
1242 * NOTE max_seg_size assumption that small blocks aren't
1243 * normally used (except e.g. for reading SD registers).
1245 mmc->max_phys_segs = 32;
1246 mmc->max_hw_segs = 32;
1247 mmc->max_blk_size = 2048; /* BLEN is 11 bits (+1) */
1248 mmc->max_blk_count = 2048; /* NBLK is 11 bits (+1) */
1249 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1250 mmc->max_seg_size = mmc->max_req_size;
1252 r = mmc_add_host(mmc);
1256 if (slot->pdata->name != NULL) {
1257 r = device_create_file(&mmc->class_dev,
1258 &dev_attr_slot_name);
1260 goto err_remove_host;
1263 if (slot->pdata->get_cover_state != NULL) {
1264 r = device_create_file(&mmc->class_dev,
1265 &dev_attr_cover_switch);
1267 goto err_remove_slot_name;
1269 INIT_WORK(&slot->switch_work, mmc_omap_cover_handler);
1270 setup_timer(&slot->switch_timer, mmc_omap_switch_timer,
1271 (unsigned long) slot);
1272 schedule_work(&slot->switch_work);
1275 if (slot->pdata->get_ro != NULL) {
1276 r = device_create_file(&mmc->class_dev,
1279 goto err_remove_cover_attr;
1284 err_remove_cover_attr:
1285 if (slot->pdata->get_cover_state != NULL)
1286 device_remove_file(&mmc->class_dev, &dev_attr_cover_switch);
1287 err_remove_slot_name:
1288 if (slot->pdata->name != NULL)
1289 device_remove_file(&mmc->class_dev, &dev_attr_ro);
1291 mmc_remove_host(mmc);
1295 static void mmc_omap_remove_slot(struct mmc_omap_slot *slot)
1297 struct mmc_host *mmc = slot->mmc;
1299 if (slot->pdata->name != NULL)
1300 device_remove_file(&mmc->class_dev, &dev_attr_slot_name);
1301 if (slot->pdata->get_cover_state != NULL)
1302 device_remove_file(&mmc->class_dev, &dev_attr_cover_switch);
1303 if (slot->pdata->get_ro != NULL)
1304 device_remove_file(&mmc->class_dev, &dev_attr_ro);
1306 del_timer_sync(&slot->switch_timer);
1307 flush_scheduled_work();
1309 mmc_remove_host(mmc);
1313 static int __init mmc_omap_probe(struct platform_device *pdev)
1315 struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;
1316 struct mmc_omap_host *host = NULL;
1317 struct resource *res;
1321 if (pdata == NULL) {
1322 dev_err(&pdev->dev, "platform data missing\n");
1325 if (pdata->nr_slots == 0) {
1326 dev_err(&pdev->dev, "no slots\n");
1330 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1331 irq = platform_get_irq(pdev, 0);
1332 if (res == NULL || irq < 0)
1335 res = request_mem_region(res->start, res->end - res->start + 1,
1340 host = kzalloc(sizeof(struct mmc_omap_host), GFP_KERNEL);
1343 goto err_free_mem_region;
1346 INIT_WORK(&host->cmd_abort, mmc_omap_abort_command);
1347 setup_timer(&host->cmd_timer, mmc_omap_cmd_timer, (unsigned long) host);
1349 spin_lock_init(&host->dma_lock);
1350 setup_timer(&host->dma_timer, mmc_omap_dma_timer, (unsigned long) host);
1351 spin_lock_init(&host->slot_lock);
1352 init_waitqueue_head(&host->slot_wq);
1354 host->pdata = pdata;
1355 host->dev = &pdev->dev;
1356 platform_set_drvdata(pdev, host);
1358 host->id = pdev->id;
1359 host->mem_res = res;
1366 host->phys_base = host->mem_res->start;
1367 host->virt_base = (void __iomem *) IO_ADDRESS(host->phys_base);
1369 if (cpu_is_omap24xx()) {
1370 host->iclk = clk_get(&pdev->dev, "mmc_ick");
1371 if (IS_ERR(host->iclk))
1372 goto err_free_mmc_host;
1373 clk_enable(host->iclk);
1376 if (!cpu_is_omap24xx())
1377 host->fclk = clk_get(&pdev->dev, "mmc_ck");
1379 host->fclk = clk_get(&pdev->dev, "mmc_fck");
1381 if (IS_ERR(host->fclk)) {
1382 ret = PTR_ERR(host->fclk);
1386 ret = request_irq(host->irq, mmc_omap_irq, 0, DRIVER_NAME, host);
1390 if (pdata->init != NULL) {
1391 ret = pdata->init(&pdev->dev);
1396 host->nr_slots = pdata->nr_slots;
1397 for (i = 0; i < pdata->nr_slots; i++) {
1398 ret = mmc_omap_new_slot(host, i);
1401 mmc_omap_remove_slot(host->slots[i]);
1403 goto err_plat_cleanup;
1411 pdata->cleanup(&pdev->dev);
1413 free_irq(host->irq, host);
1415 clk_put(host->fclk);
1417 if (host->iclk != NULL) {
1418 clk_disable(host->iclk);
1419 clk_put(host->iclk);
1423 err_free_mem_region:
1424 release_mem_region(res->start, res->end - res->start + 1);
1428 static int mmc_omap_remove(struct platform_device *pdev)
1430 struct mmc_omap_host *host = platform_get_drvdata(pdev);
1433 platform_set_drvdata(pdev, NULL);
1435 BUG_ON(host == NULL);
1437 for (i = 0; i < host->nr_slots; i++)
1438 mmc_omap_remove_slot(host->slots[i]);
1440 if (host->pdata->cleanup)
1441 host->pdata->cleanup(&pdev->dev);
1443 if (host->iclk && !IS_ERR(host->iclk))
1444 clk_put(host->iclk);
1445 if (host->fclk && !IS_ERR(host->fclk))
1446 clk_put(host->fclk);
1448 release_mem_region(pdev->resource[0].start,
1449 pdev->resource[0].end - pdev->resource[0].start + 1);
1457 static int mmc_omap_suspend(struct platform_device *pdev, pm_message_t mesg)
1460 struct mmc_omap_host *host = platform_get_drvdata(pdev);
1462 if (host == NULL || host->suspended)
1465 for (i = 0; i < host->nr_slots; i++) {
1466 struct mmc_omap_slot *slot;
1468 slot = host->slots[i];
1469 ret = mmc_suspend_host(slot->mmc, mesg);
1472 slot = host->slots[i];
1473 mmc_resume_host(slot->mmc);
1478 host->suspended = 1;
1482 static int mmc_omap_resume(struct platform_device *pdev)
1485 struct mmc_omap_host *host = platform_get_drvdata(pdev);
1487 if (host == NULL || !host->suspended)
1490 for (i = 0; i < host->nr_slots; i++) {
1491 struct mmc_omap_slot *slot;
1492 slot = host->slots[i];
1493 ret = mmc_resume_host(slot->mmc);
1497 host->suspended = 0;
1502 #define mmc_omap_suspend NULL
1503 #define mmc_omap_resume NULL
1506 static struct platform_driver mmc_omap_driver = {
1507 .probe = mmc_omap_probe,
1508 .remove = mmc_omap_remove,
1509 .suspend = mmc_omap_suspend,
1510 .resume = mmc_omap_resume,
1512 .name = DRIVER_NAME,
1516 static int __init mmc_omap_init(void)
1518 return platform_driver_register(&mmc_omap_driver);
1521 static void __exit mmc_omap_exit(void)
1523 platform_driver_unregister(&mmc_omap_driver);
1526 module_init(mmc_omap_init);
1527 module_exit(mmc_omap_exit);
1529 MODULE_DESCRIPTION("OMAP Multimedia Card driver");
1530 MODULE_LICENSE("GPL");
1531 MODULE_ALIAS(DRIVER_NAME);
1532 MODULE_AUTHOR("Juha Yrjölä");