2 * Common Flash Interface support:
3 * AMD & Fujitsu Standard Vendor Command Set (ID 0x0002)
5 * Copyright (C) 2000 Crossnet Co. <info@crossnet.co.jp>
6 * Copyright (C) 2004 Arcom Control Systems Ltd <linux@arcom.com>
7 * Copyright (C) 2005 MontaVista Software Inc. <source@mvista.com>
9 * 2_by_8 routines added by Simon Munton
11 * 4_by_16 work by Carolyn J. Smith
13 * XIP support hooks by Vitaly Wool (based on code for Intel flash
16 * Occasionally maintained by Thayne Harbaugh tharbaugh at lnxi dot com
20 * $Id: cfi_cmdset_0002.c,v 1.122 2005/11/07 11:14:22 gleixner Exp $
24 #include <linux/module.h>
25 #include <linux/types.h>
26 #include <linux/kernel.h>
27 #include <linux/sched.h>
28 #include <linux/init.h>
30 #include <asm/byteorder.h>
32 #include <linux/errno.h>
33 #include <linux/slab.h>
34 #include <linux/delay.h>
35 #include <linux/interrupt.h>
36 #include <linux/mtd/compatmac.h>
37 #include <linux/mtd/map.h>
38 #include <linux/mtd/mtd.h>
39 #include <linux/mtd/cfi.h>
40 #include <linux/mtd/xip.h>
42 #define AMD_BOOTLOC_BUG
43 #define FORCE_WORD_WRITE 0
45 #define MAX_WORD_RETRIES 3
47 #define MANUFACTURER_AMD 0x0001
48 #define MANUFACTURER_ATMEL 0x001F
49 #define MANUFACTURER_SST 0x00BF
50 #define SST49LF004B 0x0060
51 #define SST49LF040B 0x0050
52 #define SST49LF008A 0x005a
53 #define AT49BV6416 0x00d6
55 static int cfi_amdstd_read (struct mtd_info *, loff_t, size_t, size_t *, u_char *);
56 static int cfi_amdstd_write_words(struct mtd_info *, loff_t, size_t, size_t *, const u_char *);
57 static int cfi_amdstd_write_buffers(struct mtd_info *, loff_t, size_t, size_t *, const u_char *);
58 static int cfi_amdstd_erase_chip(struct mtd_info *, struct erase_info *);
59 static int cfi_amdstd_erase_varsize(struct mtd_info *, struct erase_info *);
60 static void cfi_amdstd_sync (struct mtd_info *);
61 static int cfi_amdstd_suspend (struct mtd_info *);
62 static void cfi_amdstd_resume (struct mtd_info *);
63 static int cfi_amdstd_secsi_read (struct mtd_info *, loff_t, size_t, size_t *, u_char *);
65 static void cfi_amdstd_destroy(struct mtd_info *);
67 struct mtd_info *cfi_cmdset_0002(struct map_info *, int);
68 static struct mtd_info *cfi_amdstd_setup (struct mtd_info *);
70 static int get_chip(struct map_info *map, struct flchip *chip, unsigned long adr, int mode);
71 static void put_chip(struct map_info *map, struct flchip *chip, unsigned long adr);
74 static int cfi_atmel_lock(struct mtd_info *mtd, loff_t ofs, size_t len);
75 static int cfi_atmel_unlock(struct mtd_info *mtd, loff_t ofs, size_t len);
77 static struct mtd_chip_driver cfi_amdstd_chipdrv = {
78 .probe = NULL, /* Not usable directly */
79 .destroy = cfi_amdstd_destroy,
80 .name = "cfi_cmdset_0002",
85 /* #define DEBUG_CFI_FEATURES */
88 #ifdef DEBUG_CFI_FEATURES
89 static void cfi_tell_features(struct cfi_pri_amdstd *extp)
91 const char* erase_suspend[3] = {
92 "Not supported", "Read only", "Read/write"
94 const char* top_bottom[6] = {
95 "No WP", "8x8KiB sectors at top & bottom, no WP",
96 "Bottom boot", "Top boot",
97 "Uniform, Bottom WP", "Uniform, Top WP"
100 printk(" Silicon revision: %d\n", extp->SiliconRevision >> 1);
101 printk(" Address sensitive unlock: %s\n",
102 (extp->SiliconRevision & 1) ? "Not required" : "Required");
104 if (extp->EraseSuspend < ARRAY_SIZE(erase_suspend))
105 printk(" Erase Suspend: %s\n", erase_suspend[extp->EraseSuspend]);
107 printk(" Erase Suspend: Unknown value %d\n", extp->EraseSuspend);
109 if (extp->BlkProt == 0)
110 printk(" Block protection: Not supported\n");
112 printk(" Block protection: %d sectors per group\n", extp->BlkProt);
115 printk(" Temporary block unprotect: %s\n",
116 extp->TmpBlkUnprotect ? "Supported" : "Not supported");
117 printk(" Block protect/unprotect scheme: %d\n", extp->BlkProtUnprot);
118 printk(" Number of simultaneous operations: %d\n", extp->SimultaneousOps);
119 printk(" Burst mode: %s\n",
120 extp->BurstMode ? "Supported" : "Not supported");
121 if (extp->PageMode == 0)
122 printk(" Page mode: Not supported\n");
124 printk(" Page mode: %d word page\n", extp->PageMode << 2);
126 printk(" Vpp Supply Minimum Program/Erase Voltage: %d.%d V\n",
127 extp->VppMin >> 4, extp->VppMin & 0xf);
128 printk(" Vpp Supply Maximum Program/Erase Voltage: %d.%d V\n",
129 extp->VppMax >> 4, extp->VppMax & 0xf);
131 if (extp->TopBottom < ARRAY_SIZE(top_bottom))
132 printk(" Top/Bottom Boot Block: %s\n", top_bottom[extp->TopBottom]);
134 printk(" Top/Bottom Boot Block: Unknown value %d\n", extp->TopBottom);
138 #ifdef AMD_BOOTLOC_BUG
139 /* Wheee. Bring me the head of someone at AMD. */
140 static void fixup_amd_bootblock(struct mtd_info *mtd, void* param)
142 struct map_info *map = mtd->priv;
143 struct cfi_private *cfi = map->fldrv_priv;
144 struct cfi_pri_amdstd *extp = cfi->cmdset_priv;
145 __u8 major = extp->MajorVersion;
146 __u8 minor = extp->MinorVersion;
148 if (((major << 8) | minor) < 0x3131) {
149 /* CFI version 1.0 => don't trust bootloc */
150 if (cfi->id & 0x80) {
151 printk(KERN_WARNING "%s: JEDEC Device ID is 0x%02X. Assuming broken CFI table.\n", map->name, cfi->id);
152 extp->TopBottom = 3; /* top boot */
154 extp->TopBottom = 2; /* bottom boot */
160 static void fixup_use_write_buffers(struct mtd_info *mtd, void *param)
162 struct map_info *map = mtd->priv;
163 struct cfi_private *cfi = map->fldrv_priv;
164 if (cfi->cfiq->BufWriteTimeoutTyp) {
165 DEBUG(MTD_DEBUG_LEVEL1, "Using buffer write method\n" );
166 mtd->write = cfi_amdstd_write_buffers;
170 /* Atmel chips don't use the same PRI format as AMD chips */
171 static void fixup_convert_atmel_pri(struct mtd_info *mtd, void *param)
173 struct map_info *map = mtd->priv;
174 struct cfi_private *cfi = map->fldrv_priv;
175 struct cfi_pri_amdstd *extp = cfi->cmdset_priv;
176 struct cfi_pri_atmel atmel_pri;
178 memcpy(&atmel_pri, extp, sizeof(atmel_pri));
179 memset((char *)extp + 5, 0, sizeof(*extp) - 5);
181 if (atmel_pri.Features & 0x02)
182 extp->EraseSuspend = 2;
184 if (atmel_pri.BottomBoot)
189 /* burst write mode not supported */
190 cfi->cfiq->BufWriteTimeoutTyp = 0;
191 cfi->cfiq->BufWriteTimeoutMax = 0;
194 static void fixup_use_secsi(struct mtd_info *mtd, void *param)
196 /* Setup for chips with a secsi area */
197 mtd->read_user_prot_reg = cfi_amdstd_secsi_read;
198 mtd->read_fact_prot_reg = cfi_amdstd_secsi_read;
201 static void fixup_use_erase_chip(struct mtd_info *mtd, void *param)
203 struct map_info *map = mtd->priv;
204 struct cfi_private *cfi = map->fldrv_priv;
205 if ((cfi->cfiq->NumEraseRegions == 1) &&
206 ((cfi->cfiq->EraseRegionInfo[0] & 0xffff) == 0)) {
207 mtd->erase = cfi_amdstd_erase_chip;
213 * Some Atmel chips (e.g. the AT49BV6416) power-up with all sectors
216 static void fixup_use_atmel_lock(struct mtd_info *mtd, void *param)
218 mtd->lock = cfi_atmel_lock;
219 mtd->unlock = cfi_atmel_unlock;
220 mtd->flags |= MTD_STUPID_LOCK;
223 static struct cfi_fixup cfi_fixup_table[] = {
224 { CFI_MFR_ATMEL, CFI_ID_ANY, fixup_convert_atmel_pri, NULL },
225 #ifdef AMD_BOOTLOC_BUG
226 { CFI_MFR_AMD, CFI_ID_ANY, fixup_amd_bootblock, NULL },
228 { CFI_MFR_AMD, 0x0050, fixup_use_secsi, NULL, },
229 { CFI_MFR_AMD, 0x0053, fixup_use_secsi, NULL, },
230 { CFI_MFR_AMD, 0x0055, fixup_use_secsi, NULL, },
231 { CFI_MFR_AMD, 0x0056, fixup_use_secsi, NULL, },
232 { CFI_MFR_AMD, 0x005C, fixup_use_secsi, NULL, },
233 { CFI_MFR_AMD, 0x005F, fixup_use_secsi, NULL, },
234 #if !FORCE_WORD_WRITE
235 { CFI_MFR_ANY, CFI_ID_ANY, fixup_use_write_buffers, NULL, },
239 static struct cfi_fixup jedec_fixup_table[] = {
240 { MANUFACTURER_SST, SST49LF004B, fixup_use_fwh_lock, NULL, },
241 { MANUFACTURER_SST, SST49LF040B, fixup_use_fwh_lock, NULL, },
242 { MANUFACTURER_SST, SST49LF008A, fixup_use_fwh_lock, NULL, },
246 static struct cfi_fixup fixup_table[] = {
247 /* The CFI vendor ids and the JEDEC vendor IDs appear
248 * to be common. It is like the devices id's are as
249 * well. This table is to pick all cases where
250 * we know that is the case.
252 { CFI_MFR_ANY, CFI_ID_ANY, fixup_use_erase_chip, NULL },
253 { CFI_MFR_ATMEL, AT49BV6416, fixup_use_atmel_lock, NULL },
258 struct mtd_info *cfi_cmdset_0002(struct map_info *map, int primary)
260 struct cfi_private *cfi = map->fldrv_priv;
261 struct mtd_info *mtd;
264 mtd = kzalloc(sizeof(*mtd), GFP_KERNEL);
266 printk(KERN_WARNING "Failed to allocate memory for MTD device\n");
270 mtd->type = MTD_NORFLASH;
272 /* Fill in the default mtd operations */
273 mtd->erase = cfi_amdstd_erase_varsize;
274 mtd->write = cfi_amdstd_write_words;
275 mtd->read = cfi_amdstd_read;
276 mtd->sync = cfi_amdstd_sync;
277 mtd->suspend = cfi_amdstd_suspend;
278 mtd->resume = cfi_amdstd_resume;
279 mtd->flags = MTD_CAP_NORFLASH;
280 mtd->name = map->name;
283 if (cfi->cfi_mode==CFI_MODE_CFI){
284 unsigned char bootloc;
286 * It's a real CFI chip, not one for which the probe
287 * routine faked a CFI structure. So we read the feature
290 __u16 adr = primary?cfi->cfiq->P_ADR:cfi->cfiq->A_ADR;
291 struct cfi_pri_amdstd *extp;
293 extp = (struct cfi_pri_amdstd*)cfi_read_pri(map, adr, sizeof(*extp), "Amd/Fujitsu");
299 if (extp->MajorVersion != '1' ||
300 (extp->MinorVersion < '0' || extp->MinorVersion > '4')) {
301 printk(KERN_ERR " Unknown Amd/Fujitsu Extended Query "
302 "version %c.%c.\n", extp->MajorVersion,
309 /* Install our own private info structure */
310 cfi->cmdset_priv = extp;
312 /* Apply cfi device specific fixups */
313 cfi_fixup(mtd, cfi_fixup_table);
315 #ifdef DEBUG_CFI_FEATURES
316 /* Tell the user about it in lots of lovely detail */
317 cfi_tell_features(extp);
320 bootloc = extp->TopBottom;
321 if ((bootloc != 2) && (bootloc != 3)) {
322 printk(KERN_WARNING "%s: CFI does not contain boot "
323 "bank location. Assuming top.\n", map->name);
327 if (bootloc == 3 && cfi->cfiq->NumEraseRegions > 1) {
328 printk(KERN_WARNING "%s: Swapping erase regions for broken CFI table.\n", map->name);
330 for (i=0; i<cfi->cfiq->NumEraseRegions / 2; i++) {
331 int j = (cfi->cfiq->NumEraseRegions-1)-i;
334 swap = cfi->cfiq->EraseRegionInfo[i];
335 cfi->cfiq->EraseRegionInfo[i] = cfi->cfiq->EraseRegionInfo[j];
336 cfi->cfiq->EraseRegionInfo[j] = swap;
339 /* Set the default CFI lock/unlock addresses */
340 cfi->addr_unlock1 = 0x555;
341 cfi->addr_unlock2 = 0x2aa;
342 /* Modify the unlock address if we are in compatibility mode */
343 if ( /* x16 in x8 mode */
344 ((cfi->device_type == CFI_DEVICETYPE_X8) &&
345 (cfi->cfiq->InterfaceDesc == 2)) ||
346 /* x32 in x16 mode */
347 ((cfi->device_type == CFI_DEVICETYPE_X16) &&
348 (cfi->cfiq->InterfaceDesc == 4)))
350 cfi->addr_unlock1 = 0xaaa;
351 cfi->addr_unlock2 = 0x555;
355 else if (cfi->cfi_mode == CFI_MODE_JEDEC) {
356 /* Apply jedec specific fixups */
357 cfi_fixup(mtd, jedec_fixup_table);
359 /* Apply generic fixups */
360 cfi_fixup(mtd, fixup_table);
362 for (i=0; i< cfi->numchips; i++) {
363 cfi->chips[i].word_write_time = 1<<cfi->cfiq->WordWriteTimeoutTyp;
364 cfi->chips[i].buffer_write_time = 1<<cfi->cfiq->BufWriteTimeoutTyp;
365 cfi->chips[i].erase_time = 1<<cfi->cfiq->BlockEraseTimeoutTyp;
366 cfi->chips[i].ref_point_counter = 0;
367 init_waitqueue_head(&(cfi->chips[i].wq));
370 map->fldrv = &cfi_amdstd_chipdrv;
372 return cfi_amdstd_setup(mtd);
374 EXPORT_SYMBOL_GPL(cfi_cmdset_0002);
376 static struct mtd_info *cfi_amdstd_setup(struct mtd_info *mtd)
378 struct map_info *map = mtd->priv;
379 struct cfi_private *cfi = map->fldrv_priv;
380 unsigned long devsize = (1<<cfi->cfiq->DevSize) * cfi->interleave;
381 unsigned long offset = 0;
384 printk(KERN_NOTICE "number of %s chips: %d\n",
385 (cfi->cfi_mode == CFI_MODE_CFI)?"CFI":"JEDEC",cfi->numchips);
386 /* Select the correct geometry setup */
387 mtd->size = devsize * cfi->numchips;
389 mtd->numeraseregions = cfi->cfiq->NumEraseRegions * cfi->numchips;
390 mtd->eraseregions = kmalloc(sizeof(struct mtd_erase_region_info)
391 * mtd->numeraseregions, GFP_KERNEL);
392 if (!mtd->eraseregions) {
393 printk(KERN_WARNING "Failed to allocate memory for MTD erase region info\n");
397 for (i=0; i<cfi->cfiq->NumEraseRegions; i++) {
398 unsigned long ernum, ersize;
399 ersize = ((cfi->cfiq->EraseRegionInfo[i] >> 8) & ~0xff) * cfi->interleave;
400 ernum = (cfi->cfiq->EraseRegionInfo[i] & 0xffff) + 1;
402 if (mtd->erasesize < ersize) {
403 mtd->erasesize = ersize;
405 for (j=0; j<cfi->numchips; j++) {
406 mtd->eraseregions[(j*cfi->cfiq->NumEraseRegions)+i].offset = (j*devsize)+offset;
407 mtd->eraseregions[(j*cfi->cfiq->NumEraseRegions)+i].erasesize = ersize;
408 mtd->eraseregions[(j*cfi->cfiq->NumEraseRegions)+i].numblocks = ernum;
410 offset += (ersize * ernum);
412 if (offset != devsize) {
414 printk(KERN_WARNING "Sum of regions (%lx) != total size of set of interleaved chips (%lx)\n", offset, devsize);
419 for (i=0; i<mtd->numeraseregions;i++){
420 printk("%d: offset=0x%x,size=0x%x,blocks=%d\n",
421 i,mtd->eraseregions[i].offset,
422 mtd->eraseregions[i].erasesize,
423 mtd->eraseregions[i].numblocks);
427 /* FIXME: erase-suspend-program is broken. See
428 http://lists.infradead.org/pipermail/linux-mtd/2003-December/009001.html */
429 printk(KERN_NOTICE "cfi_cmdset_0002: Disabling erase-suspend-program due to code brokenness.\n");
431 __module_get(THIS_MODULE);
436 kfree(mtd->eraseregions);
439 kfree(cfi->cmdset_priv);
445 * Return true if the chip is ready.
447 * Ready is one of: read mode, query mode, erase-suspend-read mode (in any
448 * non-suspended sector) and is indicated by no toggle bits toggling.
450 * Note that anything more complicated than checking if no bits are toggling
451 * (including checking DQ5 for an error status) is tricky to get working
452 * correctly and is therefore not done (particulary with interleaved chips
453 * as each chip must be checked independantly of the others).
455 static int __xipram chip_ready(struct map_info *map, unsigned long addr)
459 d = map_read(map, addr);
460 t = map_read(map, addr);
462 return map_word_equal(map, d, t);
466 * Return true if the chip is ready and has the correct value.
468 * Ready is one of: read mode, query mode, erase-suspend-read mode (in any
469 * non-suspended sector) and it is indicated by no bits toggling.
471 * Error are indicated by toggling bits or bits held with the wrong value,
472 * or with bits toggling.
474 * Note that anything more complicated than checking if no bits are toggling
475 * (including checking DQ5 for an error status) is tricky to get working
476 * correctly and is therefore not done (particulary with interleaved chips
477 * as each chip must be checked independantly of the others).
480 static int __xipram chip_good(struct map_info *map, unsigned long addr, map_word expected)
484 oldd = map_read(map, addr);
485 curd = map_read(map, addr);
487 return map_word_equal(map, oldd, curd) &&
488 map_word_equal(map, curd, expected);
491 static int get_chip(struct map_info *map, struct flchip *chip, unsigned long adr, int mode)
493 DECLARE_WAITQUEUE(wait, current);
494 struct cfi_private *cfi = map->fldrv_priv;
496 struct cfi_pri_amdstd *cfip = (struct cfi_pri_amdstd *)cfi->cmdset_priv;
499 timeo = jiffies + HZ;
501 switch (chip->state) {
505 if (chip_ready(map, adr))
508 if (time_after(jiffies, timeo)) {
509 printk(KERN_ERR "Waiting for chip to be ready timed out.\n");
510 spin_unlock(chip->mutex);
513 spin_unlock(chip->mutex);
515 spin_lock(chip->mutex);
516 /* Someone else might have been playing with it. */
526 if (mode == FL_WRITING) /* FIXME: Erase-suspend-program appears broken. */
529 if (!( mode == FL_READY
532 || (mode == FL_WRITING && (cfip->EraseSuspend & 0x2))
533 || (mode == FL_WRITING && (cfip->EraseSuspend & 0x1)
537 /* We could check to see if we're trying to access the sector
538 * that is currently being erased. However, no user will try
539 * anything like that so we just wait for the timeout. */
542 /* It's harmless to issue the Erase-Suspend and Erase-Resume
543 * commands when the erase algorithm isn't in progress. */
544 map_write(map, CMD(0xB0), chip->in_progress_block_addr);
545 chip->oldstate = FL_ERASING;
546 chip->state = FL_ERASE_SUSPENDING;
547 chip->erase_suspended = 1;
549 if (chip_ready(map, adr))
552 if (time_after(jiffies, timeo)) {
553 /* Should have suspended the erase by now.
554 * Send an Erase-Resume command as either
555 * there was an error (so leave the erase
556 * routine to recover from it) or we trying to
557 * use the erase-in-progress sector. */
558 map_write(map, CMD(0x30), chip->in_progress_block_addr);
559 chip->state = FL_ERASING;
560 chip->oldstate = FL_READY;
561 printk(KERN_ERR "MTD %s(): chip not ready after erase suspend\n", __func__);
565 spin_unlock(chip->mutex);
567 spin_lock(chip->mutex);
568 /* Nobody will touch it while it's in state FL_ERASE_SUSPENDING.
569 So we can just loop here. */
571 chip->state = FL_READY;
574 case FL_XIP_WHILE_ERASING:
575 if (mode != FL_READY && mode != FL_POINT &&
576 (!cfip || !(cfip->EraseSuspend&2)))
578 chip->oldstate = chip->state;
579 chip->state = FL_READY;
583 /* Only if there's no operation suspended... */
584 if (mode == FL_READY && chip->oldstate == FL_READY)
589 set_current_state(TASK_UNINTERRUPTIBLE);
590 add_wait_queue(&chip->wq, &wait);
591 spin_unlock(chip->mutex);
593 remove_wait_queue(&chip->wq, &wait);
594 spin_lock(chip->mutex);
600 static void put_chip(struct map_info *map, struct flchip *chip, unsigned long adr)
602 struct cfi_private *cfi = map->fldrv_priv;
604 switch(chip->oldstate) {
606 chip->state = chip->oldstate;
607 map_write(map, CMD(0x30), chip->in_progress_block_addr);
608 chip->oldstate = FL_READY;
609 chip->state = FL_ERASING;
612 case FL_XIP_WHILE_ERASING:
613 chip->state = chip->oldstate;
614 chip->oldstate = FL_READY;
619 /* We should really make set_vpp() count, rather than doing this */
623 printk(KERN_ERR "MTD: put_chip() called with oldstate %d!!\n", chip->oldstate);
628 #ifdef CONFIG_MTD_XIP
631 * No interrupt what so ever can be serviced while the flash isn't in array
632 * mode. This is ensured by the xip_disable() and xip_enable() functions
633 * enclosing any code path where the flash is known not to be in array mode.
634 * And within a XIP disabled code path, only functions marked with __xipram
635 * may be called and nothing else (it's a good thing to inspect generated
636 * assembly to make sure inline functions were actually inlined and that gcc
637 * didn't emit calls to its own support functions). Also configuring MTD CFI
638 * support to a single buswidth and a single interleave is also recommended.
641 static void xip_disable(struct map_info *map, struct flchip *chip,
644 /* TODO: chips with no XIP use should ignore and return */
645 (void) map_read(map, adr); /* ensure mmu mapping is up to date */
649 static void __xipram xip_enable(struct map_info *map, struct flchip *chip,
652 struct cfi_private *cfi = map->fldrv_priv;
654 if (chip->state != FL_POINT && chip->state != FL_READY) {
655 map_write(map, CMD(0xf0), adr);
656 chip->state = FL_READY;
658 (void) map_read(map, adr);
664 * When a delay is required for the flash operation to complete, the
665 * xip_udelay() function is polling for both the given timeout and pending
666 * (but still masked) hardware interrupts. Whenever there is an interrupt
667 * pending then the flash erase operation is suspended, array mode restored
668 * and interrupts unmasked. Task scheduling might also happen at that
669 * point. The CPU eventually returns from the interrupt or the call to
670 * schedule() and the suspended flash operation is resumed for the remaining
671 * of the delay period.
673 * Warning: this function _will_ fool interrupt latency tracing tools.
676 static void __xipram xip_udelay(struct map_info *map, struct flchip *chip,
677 unsigned long adr, int usec)
679 struct cfi_private *cfi = map->fldrv_priv;
680 struct cfi_pri_amdstd *extp = cfi->cmdset_priv;
681 map_word status, OK = CMD(0x80);
682 unsigned long suspended, start = xip_currtime();
687 if (xip_irqpending() && extp &&
688 ((chip->state == FL_ERASING && (extp->EraseSuspend & 2))) &&
689 (cfi_interleave_is_1(cfi) || chip->oldstate == FL_READY)) {
691 * Let's suspend the erase operation when supported.
692 * Note that we currently don't try to suspend
693 * interleaved chips if there is already another
694 * operation suspended (imagine what happens
695 * when one chip was already done with the current
696 * operation while another chip suspended it, then
697 * we resume the whole thing at once). Yes, it
700 map_write(map, CMD(0xb0), adr);
701 usec -= xip_elapsed_since(start);
702 suspended = xip_currtime();
704 if (xip_elapsed_since(suspended) > 100000) {
706 * The chip doesn't want to suspend
707 * after waiting for 100 msecs.
708 * This is a critical error but there
709 * is not much we can do here.
713 status = map_read(map, adr);
714 } while (!map_word_andequal(map, status, OK, OK));
716 /* Suspend succeeded */
717 oldstate = chip->state;
718 if (!map_word_bitsset(map, status, CMD(0x40)))
720 chip->state = FL_XIP_WHILE_ERASING;
721 chip->erase_suspended = 1;
722 map_write(map, CMD(0xf0), adr);
723 (void) map_read(map, adr);
724 asm volatile (".rep 8; nop; .endr");
726 spin_unlock(chip->mutex);
727 asm volatile (".rep 8; nop; .endr");
731 * We're back. However someone else might have
732 * decided to go write to the chip if we are in
733 * a suspended erase state. If so let's wait
736 spin_lock(chip->mutex);
737 while (chip->state != FL_XIP_WHILE_ERASING) {
738 DECLARE_WAITQUEUE(wait, current);
739 set_current_state(TASK_UNINTERRUPTIBLE);
740 add_wait_queue(&chip->wq, &wait);
741 spin_unlock(chip->mutex);
743 remove_wait_queue(&chip->wq, &wait);
744 spin_lock(chip->mutex);
746 /* Disallow XIP again */
749 /* Resume the write or erase operation */
750 map_write(map, CMD(0x30), adr);
751 chip->state = oldstate;
752 start = xip_currtime();
753 } else if (usec >= 1000000/HZ) {
755 * Try to save on CPU power when waiting delay
756 * is at least a system timer tick period.
757 * No need to be extremely accurate here.
761 status = map_read(map, adr);
762 } while (!map_word_andequal(map, status, OK, OK)
763 && xip_elapsed_since(start) < usec);
766 #define UDELAY(map, chip, adr, usec) xip_udelay(map, chip, adr, usec)
769 * The INVALIDATE_CACHED_RANGE() macro is normally used in parallel while
770 * the flash is actively programming or erasing since we have to poll for
771 * the operation to complete anyway. We can't do that in a generic way with
772 * a XIP setup so do it before the actual flash operation in this case
773 * and stub it out from INVALIDATE_CACHE_UDELAY.
775 #define XIP_INVAL_CACHED_RANGE(map, from, size) \
776 INVALIDATE_CACHED_RANGE(map, from, size)
778 #define INVALIDATE_CACHE_UDELAY(map, chip, adr, len, usec) \
779 UDELAY(map, chip, adr, usec)
784 * Activating this XIP support changes the way the code works a bit. For
785 * example the code to suspend the current process when concurrent access
786 * happens is never executed because xip_udelay() will always return with the
787 * same chip state as it was entered with. This is why there is no care for
788 * the presence of add_wait_queue() or schedule() calls from within a couple
789 * xip_disable()'d areas of code, like in do_erase_oneblock for example.
790 * The queueing and scheduling are always happening within xip_udelay().
792 * Similarly, get_chip() and put_chip() just happen to always be executed
793 * with chip->state set to FL_READY (or FL_XIP_WHILE_*) where flash state
794 * is in array mode, therefore never executing many cases therein and not
795 * causing any problem with XIP.
800 #define xip_disable(map, chip, adr)
801 #define xip_enable(map, chip, adr)
802 #define XIP_INVAL_CACHED_RANGE(x...)
804 #define UDELAY(map, chip, adr, usec) \
806 spin_unlock(chip->mutex); \
808 spin_lock(chip->mutex); \
811 #define INVALIDATE_CACHE_UDELAY(map, chip, adr, len, usec) \
813 spin_unlock(chip->mutex); \
814 INVALIDATE_CACHED_RANGE(map, adr, len); \
816 spin_lock(chip->mutex); \
821 static inline int do_read_onechip(struct map_info *map, struct flchip *chip, loff_t adr, size_t len, u_char *buf)
823 unsigned long cmd_addr;
824 struct cfi_private *cfi = map->fldrv_priv;
829 /* Ensure cmd read/writes are aligned. */
830 cmd_addr = adr & ~(map_bankwidth(map)-1);
832 spin_lock(chip->mutex);
833 ret = get_chip(map, chip, cmd_addr, FL_READY);
835 spin_unlock(chip->mutex);
839 if (chip->state != FL_POINT && chip->state != FL_READY) {
840 map_write(map, CMD(0xf0), cmd_addr);
841 chip->state = FL_READY;
844 map_copy_from(map, buf, adr, len);
846 put_chip(map, chip, cmd_addr);
848 spin_unlock(chip->mutex);
853 static int cfi_amdstd_read (struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf)
855 struct map_info *map = mtd->priv;
856 struct cfi_private *cfi = map->fldrv_priv;
861 /* ofs: offset within the first chip that the first read should start */
863 chipnum = (from >> cfi->chipshift);
864 ofs = from - (chipnum << cfi->chipshift);
870 unsigned long thislen;
872 if (chipnum >= cfi->numchips)
875 if ((len + ofs -1) >> cfi->chipshift)
876 thislen = (1<<cfi->chipshift) - ofs;
880 ret = do_read_onechip(map, &cfi->chips[chipnum], ofs, thislen, buf);
895 static inline int do_read_secsi_onechip(struct map_info *map, struct flchip *chip, loff_t adr, size_t len, u_char *buf)
897 DECLARE_WAITQUEUE(wait, current);
898 unsigned long timeo = jiffies + HZ;
899 struct cfi_private *cfi = map->fldrv_priv;
902 spin_lock(chip->mutex);
904 if (chip->state != FL_READY){
906 printk(KERN_DEBUG "Waiting for chip to read, status = %d\n", chip->state);
908 set_current_state(TASK_UNINTERRUPTIBLE);
909 add_wait_queue(&chip->wq, &wait);
911 spin_unlock(chip->mutex);
914 remove_wait_queue(&chip->wq, &wait);
916 if(signal_pending(current))
919 timeo = jiffies + HZ;
926 chip->state = FL_READY;
928 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
929 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
930 cfi_send_gen_cmd(0x88, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
932 map_copy_from(map, buf, adr, len);
934 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
935 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
936 cfi_send_gen_cmd(0x90, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
937 cfi_send_gen_cmd(0x00, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
940 spin_unlock(chip->mutex);
945 static int cfi_amdstd_secsi_read (struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf)
947 struct map_info *map = mtd->priv;
948 struct cfi_private *cfi = map->fldrv_priv;
954 /* ofs: offset within the first chip that the first read should start */
956 /* 8 secsi bytes per chip */
964 unsigned long thislen;
966 if (chipnum >= cfi->numchips)
969 if ((len + ofs -1) >> 3)
970 thislen = (1<<3) - ofs;
974 ret = do_read_secsi_onechip(map, &cfi->chips[chipnum], ofs, thislen, buf);
989 static int __xipram do_write_oneword(struct map_info *map, struct flchip *chip, unsigned long adr, map_word datum)
991 struct cfi_private *cfi = map->fldrv_priv;
992 unsigned long timeo = jiffies + HZ;
994 * We use a 1ms + 1 jiffies generic timeout for writes (most devices
995 * have a max write time of a few hundreds usec). However, we should
996 * use the maximum timeout value given by the chip at probe time
997 * instead. Unfortunately, struct flchip does have a field for
998 * maximum timeout, only for typical which can be far too short
999 * depending of the conditions. The ' + 1' is to avoid having a
1000 * timeout of 0 jiffies if HZ is smaller than 1000.
1002 unsigned long uWriteTimeout = ( HZ / 1000 ) + 1;
1009 spin_lock(chip->mutex);
1010 ret = get_chip(map, chip, adr, FL_WRITING);
1012 spin_unlock(chip->mutex);
1016 DEBUG( MTD_DEBUG_LEVEL3, "MTD %s(): WRITE 0x%.8lx(0x%.8lx)\n",
1017 __func__, adr, datum.x[0] );
1020 * Check for a NOP for the case when the datum to write is already
1021 * present - it saves time and works around buggy chips that corrupt
1022 * data at other locations when 0xff is written to a location that
1023 * already contains 0xff.
1025 oldd = map_read(map, adr);
1026 if (map_word_equal(map, oldd, datum)) {
1027 DEBUG( MTD_DEBUG_LEVEL3, "MTD %s(): NOP\n",
1032 XIP_INVAL_CACHED_RANGE(map, adr, map_bankwidth(map));
1034 xip_disable(map, chip, adr);
1036 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
1037 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
1038 cfi_send_gen_cmd(0xA0, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
1039 map_write(map, datum, adr);
1040 chip->state = FL_WRITING;
1042 INVALIDATE_CACHE_UDELAY(map, chip,
1043 adr, map_bankwidth(map),
1044 chip->word_write_time);
1046 /* See comment above for timeout value. */
1047 timeo = jiffies + uWriteTimeout;
1049 if (chip->state != FL_WRITING) {
1050 /* Someone's suspended the write. Sleep */
1051 DECLARE_WAITQUEUE(wait, current);
1053 set_current_state(TASK_UNINTERRUPTIBLE);
1054 add_wait_queue(&chip->wq, &wait);
1055 spin_unlock(chip->mutex);
1057 remove_wait_queue(&chip->wq, &wait);
1058 timeo = jiffies + (HZ / 2); /* FIXME */
1059 spin_lock(chip->mutex);
1063 if (time_after(jiffies, timeo) && !chip_ready(map, adr)){
1064 xip_enable(map, chip, adr);
1065 printk(KERN_WARNING "MTD %s(): software timeout\n", __func__);
1066 xip_disable(map, chip, adr);
1070 if (chip_ready(map, adr))
1073 /* Latency issues. Drop the lock, wait a while and retry */
1074 UDELAY(map, chip, adr, 1);
1076 /* Did we succeed? */
1077 if (!chip_good(map, adr, datum)) {
1078 /* reset on all failures. */
1079 map_write( map, CMD(0xF0), chip->start );
1080 /* FIXME - should have reset delay before continuing */
1082 if (++retry_cnt <= MAX_WORD_RETRIES)
1087 xip_enable(map, chip, adr);
1089 chip->state = FL_READY;
1090 put_chip(map, chip, adr);
1091 spin_unlock(chip->mutex);
1097 static int cfi_amdstd_write_words(struct mtd_info *mtd, loff_t to, size_t len,
1098 size_t *retlen, const u_char *buf)
1100 struct map_info *map = mtd->priv;
1101 struct cfi_private *cfi = map->fldrv_priv;
1104 unsigned long ofs, chipstart;
1105 DECLARE_WAITQUEUE(wait, current);
1111 chipnum = to >> cfi->chipshift;
1112 ofs = to - (chipnum << cfi->chipshift);
1113 chipstart = cfi->chips[chipnum].start;
1115 /* If it's not bus-aligned, do the first byte write */
1116 if (ofs & (map_bankwidth(map)-1)) {
1117 unsigned long bus_ofs = ofs & ~(map_bankwidth(map)-1);
1118 int i = ofs - bus_ofs;
1123 spin_lock(cfi->chips[chipnum].mutex);
1125 if (cfi->chips[chipnum].state != FL_READY) {
1127 printk(KERN_DEBUG "Waiting for chip to write, status = %d\n", cfi->chips[chipnum].state);
1129 set_current_state(TASK_UNINTERRUPTIBLE);
1130 add_wait_queue(&cfi->chips[chipnum].wq, &wait);
1132 spin_unlock(cfi->chips[chipnum].mutex);
1135 remove_wait_queue(&cfi->chips[chipnum].wq, &wait);
1137 if(signal_pending(current))
1143 /* Load 'tmp_buf' with old contents of flash */
1144 tmp_buf = map_read(map, bus_ofs+chipstart);
1146 spin_unlock(cfi->chips[chipnum].mutex);
1148 /* Number of bytes to copy from buffer */
1149 n = min_t(int, len, map_bankwidth(map)-i);
1151 tmp_buf = map_word_load_partial(map, tmp_buf, buf, i, n);
1153 ret = do_write_oneword(map, &cfi->chips[chipnum],
1163 if (ofs >> cfi->chipshift) {
1166 if (chipnum == cfi->numchips)
1171 /* We are now aligned, write as much as possible */
1172 while(len >= map_bankwidth(map)) {
1175 datum = map_word_load(map, buf);
1177 ret = do_write_oneword(map, &cfi->chips[chipnum],
1182 ofs += map_bankwidth(map);
1183 buf += map_bankwidth(map);
1184 (*retlen) += map_bankwidth(map);
1185 len -= map_bankwidth(map);
1187 if (ofs >> cfi->chipshift) {
1190 if (chipnum == cfi->numchips)
1192 chipstart = cfi->chips[chipnum].start;
1196 /* Write the trailing bytes if any */
1197 if (len & (map_bankwidth(map)-1)) {
1201 spin_lock(cfi->chips[chipnum].mutex);
1203 if (cfi->chips[chipnum].state != FL_READY) {
1205 printk(KERN_DEBUG "Waiting for chip to write, status = %d\n", cfi->chips[chipnum].state);
1207 set_current_state(TASK_UNINTERRUPTIBLE);
1208 add_wait_queue(&cfi->chips[chipnum].wq, &wait);
1210 spin_unlock(cfi->chips[chipnum].mutex);
1213 remove_wait_queue(&cfi->chips[chipnum].wq, &wait);
1215 if(signal_pending(current))
1221 tmp_buf = map_read(map, ofs + chipstart);
1223 spin_unlock(cfi->chips[chipnum].mutex);
1225 tmp_buf = map_word_load_partial(map, tmp_buf, buf, 0, len);
1227 ret = do_write_oneword(map, &cfi->chips[chipnum],
1240 * FIXME: interleaved mode not tested, and probably not supported!
1242 static int __xipram do_write_buffer(struct map_info *map, struct flchip *chip,
1243 unsigned long adr, const u_char *buf,
1246 struct cfi_private *cfi = map->fldrv_priv;
1247 unsigned long timeo = jiffies + HZ;
1248 /* see comments in do_write_oneword() regarding uWriteTimeo. */
1249 unsigned long uWriteTimeout = ( HZ / 1000 ) + 1;
1251 unsigned long cmd_adr;
1258 spin_lock(chip->mutex);
1259 ret = get_chip(map, chip, adr, FL_WRITING);
1261 spin_unlock(chip->mutex);
1265 datum = map_word_load(map, buf);
1267 DEBUG( MTD_DEBUG_LEVEL3, "MTD %s(): WRITE 0x%.8lx(0x%.8lx)\n",
1268 __func__, adr, datum.x[0] );
1270 XIP_INVAL_CACHED_RANGE(map, adr, len);
1272 xip_disable(map, chip, cmd_adr);
1274 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
1275 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
1276 //cfi_send_gen_cmd(0xA0, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
1278 /* Write Buffer Load */
1279 map_write(map, CMD(0x25), cmd_adr);
1281 chip->state = FL_WRITING_TO_BUFFER;
1283 /* Write length of data to come */
1284 words = len / map_bankwidth(map);
1285 map_write(map, CMD(words - 1), cmd_adr);
1288 while(z < words * map_bankwidth(map)) {
1289 datum = map_word_load(map, buf);
1290 map_write(map, datum, adr + z);
1292 z += map_bankwidth(map);
1293 buf += map_bankwidth(map);
1295 z -= map_bankwidth(map);
1299 /* Write Buffer Program Confirm: GO GO GO */
1300 map_write(map, CMD(0x29), cmd_adr);
1301 chip->state = FL_WRITING;
1303 INVALIDATE_CACHE_UDELAY(map, chip,
1304 adr, map_bankwidth(map),
1305 chip->word_write_time);
1307 timeo = jiffies + uWriteTimeout;
1310 if (chip->state != FL_WRITING) {
1311 /* Someone's suspended the write. Sleep */
1312 DECLARE_WAITQUEUE(wait, current);
1314 set_current_state(TASK_UNINTERRUPTIBLE);
1315 add_wait_queue(&chip->wq, &wait);
1316 spin_unlock(chip->mutex);
1318 remove_wait_queue(&chip->wq, &wait);
1319 timeo = jiffies + (HZ / 2); /* FIXME */
1320 spin_lock(chip->mutex);
1324 if (time_after(jiffies, timeo) && !chip_ready(map, adr))
1327 if (chip_ready(map, adr)) {
1328 xip_enable(map, chip, adr);
1332 /* Latency issues. Drop the lock, wait a while and retry */
1333 UDELAY(map, chip, adr, 1);
1336 /* reset on all failures. */
1337 map_write( map, CMD(0xF0), chip->start );
1338 xip_enable(map, chip, adr);
1339 /* FIXME - should have reset delay before continuing */
1341 printk(KERN_WARNING "MTD %s(): software timeout\n",
1346 chip->state = FL_READY;
1347 put_chip(map, chip, adr);
1348 spin_unlock(chip->mutex);
1354 static int cfi_amdstd_write_buffers(struct mtd_info *mtd, loff_t to, size_t len,
1355 size_t *retlen, const u_char *buf)
1357 struct map_info *map = mtd->priv;
1358 struct cfi_private *cfi = map->fldrv_priv;
1359 int wbufsize = cfi_interleave(cfi) << cfi->cfiq->MaxBufWriteSize;
1368 chipnum = to >> cfi->chipshift;
1369 ofs = to - (chipnum << cfi->chipshift);
1371 /* If it's not bus-aligned, do the first word write */
1372 if (ofs & (map_bankwidth(map)-1)) {
1373 size_t local_len = (-ofs)&(map_bankwidth(map)-1);
1374 if (local_len > len)
1376 ret = cfi_amdstd_write_words(mtd, ofs + (chipnum<<cfi->chipshift),
1377 local_len, retlen, buf);
1384 if (ofs >> cfi->chipshift) {
1387 if (chipnum == cfi->numchips)
1392 /* Write buffer is worth it only if more than one word to write... */
1393 while (len >= map_bankwidth(map) * 2) {
1394 /* We must not cross write block boundaries */
1395 int size = wbufsize - (ofs & (wbufsize-1));
1399 if (size % map_bankwidth(map))
1400 size -= size % map_bankwidth(map);
1402 ret = do_write_buffer(map, &cfi->chips[chipnum],
1412 if (ofs >> cfi->chipshift) {
1415 if (chipnum == cfi->numchips)
1421 size_t retlen_dregs = 0;
1423 ret = cfi_amdstd_write_words(mtd, ofs + (chipnum<<cfi->chipshift),
1424 len, &retlen_dregs, buf);
1426 *retlen += retlen_dregs;
1435 * Handle devices with one erase region, that only implement
1436 * the chip erase command.
1438 static int __xipram do_erase_chip(struct map_info *map, struct flchip *chip)
1440 struct cfi_private *cfi = map->fldrv_priv;
1441 unsigned long timeo = jiffies + HZ;
1442 unsigned long int adr;
1443 DECLARE_WAITQUEUE(wait, current);
1446 adr = cfi->addr_unlock1;
1448 spin_lock(chip->mutex);
1449 ret = get_chip(map, chip, adr, FL_WRITING);
1451 spin_unlock(chip->mutex);
1455 DEBUG( MTD_DEBUG_LEVEL3, "MTD %s(): ERASE 0x%.8lx\n",
1456 __func__, chip->start );
1458 XIP_INVAL_CACHED_RANGE(map, adr, map->size);
1460 xip_disable(map, chip, adr);
1462 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
1463 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
1464 cfi_send_gen_cmd(0x80, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
1465 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
1466 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
1467 cfi_send_gen_cmd(0x10, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
1469 chip->state = FL_ERASING;
1470 chip->erase_suspended = 0;
1471 chip->in_progress_block_addr = adr;
1473 INVALIDATE_CACHE_UDELAY(map, chip,
1475 chip->erase_time*500);
1477 timeo = jiffies + (HZ*20);
1480 if (chip->state != FL_ERASING) {
1481 /* Someone's suspended the erase. Sleep */
1482 set_current_state(TASK_UNINTERRUPTIBLE);
1483 add_wait_queue(&chip->wq, &wait);
1484 spin_unlock(chip->mutex);
1486 remove_wait_queue(&chip->wq, &wait);
1487 spin_lock(chip->mutex);
1490 if (chip->erase_suspended) {
1491 /* This erase was suspended and resumed.
1492 Adjust the timeout */
1493 timeo = jiffies + (HZ*20); /* FIXME */
1494 chip->erase_suspended = 0;
1497 if (chip_ready(map, adr))
1500 if (time_after(jiffies, timeo)) {
1501 printk(KERN_WARNING "MTD %s(): software timeout\n",
1506 /* Latency issues. Drop the lock, wait a while and retry */
1507 UDELAY(map, chip, adr, 1000000/HZ);
1509 /* Did we succeed? */
1510 if (!chip_good(map, adr, map_word_ff(map))) {
1511 /* reset on all failures. */
1512 map_write( map, CMD(0xF0), chip->start );
1513 /* FIXME - should have reset delay before continuing */
1518 chip->state = FL_READY;
1519 xip_enable(map, chip, adr);
1520 put_chip(map, chip, adr);
1521 spin_unlock(chip->mutex);
1527 static int __xipram do_erase_oneblock(struct map_info *map, struct flchip *chip, unsigned long adr, int len, void *thunk)
1529 struct cfi_private *cfi = map->fldrv_priv;
1530 unsigned long timeo = jiffies + HZ;
1531 DECLARE_WAITQUEUE(wait, current);
1536 spin_lock(chip->mutex);
1537 ret = get_chip(map, chip, adr, FL_ERASING);
1539 spin_unlock(chip->mutex);
1543 DEBUG( MTD_DEBUG_LEVEL3, "MTD %s(): ERASE 0x%.8lx\n",
1546 XIP_INVAL_CACHED_RANGE(map, adr, len);
1548 xip_disable(map, chip, adr);
1550 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
1551 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
1552 cfi_send_gen_cmd(0x80, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
1553 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
1554 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
1555 map_write(map, CMD(0x30), adr);
1557 chip->state = FL_ERASING;
1558 chip->erase_suspended = 0;
1559 chip->in_progress_block_addr = adr;
1561 INVALIDATE_CACHE_UDELAY(map, chip,
1563 chip->erase_time*500);
1565 timeo = jiffies + (HZ*20);
1568 if (chip->state != FL_ERASING) {
1569 /* Someone's suspended the erase. Sleep */
1570 set_current_state(TASK_UNINTERRUPTIBLE);
1571 add_wait_queue(&chip->wq, &wait);
1572 spin_unlock(chip->mutex);
1574 remove_wait_queue(&chip->wq, &wait);
1575 spin_lock(chip->mutex);
1578 if (chip->erase_suspended) {
1579 /* This erase was suspended and resumed.
1580 Adjust the timeout */
1581 timeo = jiffies + (HZ*20); /* FIXME */
1582 chip->erase_suspended = 0;
1585 if (chip_ready(map, adr)) {
1586 xip_enable(map, chip, adr);
1590 if (time_after(jiffies, timeo)) {
1591 xip_enable(map, chip, adr);
1592 printk(KERN_WARNING "MTD %s(): software timeout\n",
1597 /* Latency issues. Drop the lock, wait a while and retry */
1598 UDELAY(map, chip, adr, 1000000/HZ);
1600 /* Did we succeed? */
1601 if (!chip_good(map, adr, map_word_ff(map))) {
1602 /* reset on all failures. */
1603 map_write( map, CMD(0xF0), chip->start );
1604 /* FIXME - should have reset delay before continuing */
1609 chip->state = FL_READY;
1610 put_chip(map, chip, adr);
1611 spin_unlock(chip->mutex);
1616 static int cfi_amdstd_erase_varsize(struct mtd_info *mtd, struct erase_info *instr)
1618 unsigned long ofs, len;
1624 ret = cfi_varsize_frob(mtd, do_erase_oneblock, ofs, len, NULL);
1628 instr->state = MTD_ERASE_DONE;
1629 mtd_erase_callback(instr);
1635 static int cfi_amdstd_erase_chip(struct mtd_info *mtd, struct erase_info *instr)
1637 struct map_info *map = mtd->priv;
1638 struct cfi_private *cfi = map->fldrv_priv;
1641 if (instr->addr != 0)
1644 if (instr->len != mtd->size)
1647 ret = do_erase_chip(map, &cfi->chips[0]);
1651 instr->state = MTD_ERASE_DONE;
1652 mtd_erase_callback(instr);
1657 static int do_atmel_lock(struct map_info *map, struct flchip *chip,
1658 unsigned long adr, int len, void *thunk)
1660 struct cfi_private *cfi = map->fldrv_priv;
1663 spin_lock(chip->mutex);
1664 ret = get_chip(map, chip, adr + chip->start, FL_LOCKING);
1667 chip->state = FL_LOCKING;
1669 DEBUG(MTD_DEBUG_LEVEL3, "MTD %s(): LOCK 0x%08lx len %d\n",
1670 __func__, adr, len);
1672 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi,
1673 cfi->device_type, NULL);
1674 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi,
1675 cfi->device_type, NULL);
1676 cfi_send_gen_cmd(0x80, cfi->addr_unlock1, chip->start, map, cfi,
1677 cfi->device_type, NULL);
1678 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi,
1679 cfi->device_type, NULL);
1680 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi,
1681 cfi->device_type, NULL);
1682 map_write(map, CMD(0x40), chip->start + adr);
1684 chip->state = FL_READY;
1685 put_chip(map, chip, adr + chip->start);
1689 spin_unlock(chip->mutex);
1693 static int do_atmel_unlock(struct map_info *map, struct flchip *chip,
1694 unsigned long adr, int len, void *thunk)
1696 struct cfi_private *cfi = map->fldrv_priv;
1699 spin_lock(chip->mutex);
1700 ret = get_chip(map, chip, adr + chip->start, FL_UNLOCKING);
1703 chip->state = FL_UNLOCKING;
1705 DEBUG(MTD_DEBUG_LEVEL3, "MTD %s(): LOCK 0x%08lx len %d\n",
1706 __func__, adr, len);
1708 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi,
1709 cfi->device_type, NULL);
1710 map_write(map, CMD(0x70), adr);
1712 chip->state = FL_READY;
1713 put_chip(map, chip, adr + chip->start);
1717 spin_unlock(chip->mutex);
1721 static int cfi_atmel_lock(struct mtd_info *mtd, loff_t ofs, size_t len)
1723 return cfi_varsize_frob(mtd, do_atmel_lock, ofs, len, NULL);
1726 static int cfi_atmel_unlock(struct mtd_info *mtd, loff_t ofs, size_t len)
1728 return cfi_varsize_frob(mtd, do_atmel_unlock, ofs, len, NULL);
1732 static void cfi_amdstd_sync (struct mtd_info *mtd)
1734 struct map_info *map = mtd->priv;
1735 struct cfi_private *cfi = map->fldrv_priv;
1737 struct flchip *chip;
1739 DECLARE_WAITQUEUE(wait, current);
1741 for (i=0; !ret && i<cfi->numchips; i++) {
1742 chip = &cfi->chips[i];
1745 spin_lock(chip->mutex);
1747 switch(chip->state) {
1751 case FL_JEDEC_QUERY:
1752 chip->oldstate = chip->state;
1753 chip->state = FL_SYNCING;
1754 /* No need to wake_up() on this state change -
1755 * as the whole point is that nobody can do anything
1756 * with the chip now anyway.
1759 spin_unlock(chip->mutex);
1763 /* Not an idle state */
1764 add_wait_queue(&chip->wq, &wait);
1766 spin_unlock(chip->mutex);
1770 remove_wait_queue(&chip->wq, &wait);
1776 /* Unlock the chips again */
1778 for (i--; i >=0; i--) {
1779 chip = &cfi->chips[i];
1781 spin_lock(chip->mutex);
1783 if (chip->state == FL_SYNCING) {
1784 chip->state = chip->oldstate;
1787 spin_unlock(chip->mutex);
1792 static int cfi_amdstd_suspend(struct mtd_info *mtd)
1794 struct map_info *map = mtd->priv;
1795 struct cfi_private *cfi = map->fldrv_priv;
1797 struct flchip *chip;
1800 for (i=0; !ret && i<cfi->numchips; i++) {
1801 chip = &cfi->chips[i];
1803 spin_lock(chip->mutex);
1805 switch(chip->state) {
1809 case FL_JEDEC_QUERY:
1810 chip->oldstate = chip->state;
1811 chip->state = FL_PM_SUSPENDED;
1812 /* No need to wake_up() on this state change -
1813 * as the whole point is that nobody can do anything
1814 * with the chip now anyway.
1816 case FL_PM_SUSPENDED:
1823 spin_unlock(chip->mutex);
1826 /* Unlock the chips again */
1829 for (i--; i >=0; i--) {
1830 chip = &cfi->chips[i];
1832 spin_lock(chip->mutex);
1834 if (chip->state == FL_PM_SUSPENDED) {
1835 chip->state = chip->oldstate;
1838 spin_unlock(chip->mutex);
1846 static void cfi_amdstd_resume(struct mtd_info *mtd)
1848 struct map_info *map = mtd->priv;
1849 struct cfi_private *cfi = map->fldrv_priv;
1851 struct flchip *chip;
1853 for (i=0; i<cfi->numchips; i++) {
1855 chip = &cfi->chips[i];
1857 spin_lock(chip->mutex);
1859 if (chip->state == FL_PM_SUSPENDED) {
1860 chip->state = FL_READY;
1861 map_write(map, CMD(0xF0), chip->start);
1865 printk(KERN_ERR "Argh. Chip not in PM_SUSPENDED state upon resume()\n");
1867 spin_unlock(chip->mutex);
1871 static void cfi_amdstd_destroy(struct mtd_info *mtd)
1873 struct map_info *map = mtd->priv;
1874 struct cfi_private *cfi = map->fldrv_priv;
1876 kfree(cfi->cmdset_priv);
1879 kfree(mtd->eraseregions);
1882 MODULE_LICENSE("GPL");
1883 MODULE_AUTHOR("Crossnet Co. <info@crossnet.co.jp> et al.");
1884 MODULE_DESCRIPTION("MTD chip driver for AMD/Fujitsu flash chips");