drivers/mtd/nand/cafe.c

   1 /*
   2  * cafe_nand.c
   3  *
   4  * Copyright © 2006 Red Hat, Inc.
   5  * Copyright © 2006 David Woodhouse <dwmw2@infradead.org>
   6  */
   7
   8 #define DEBUG
   9
  10 #include <linux/device.h>
  11 #undef DEBUG
  12 #include <linux/mtd/mtd.h>
  13 #include <linux/mtd/nand.h>
  14 #include <linux/pci.h>
  15 #include <linux/delay.h>
  16 #include <linux/interrupt.h>
  17 #include <asm/io.h>
  18
  19 #define CAFE_NAND_CTRL1         0x00
  20 #define CAFE_NAND_CTRL2         0x04
  21 #define CAFE_NAND_CTRL3         0x08
  22 #define CAFE_NAND_STATUS        0x0c
  23 #define CAFE_NAND_IRQ           0x10
  24 #define CAFE_NAND_IRQ_MASK      0x14
  25 #define CAFE_NAND_DATA_LEN      0x18
  26 #define CAFE_NAND_ADDR1         0x1c
  27 #define CAFE_NAND_ADDR2         0x20
  28 #define CAFE_NAND_TIMING1       0x24
  29 #define CAFE_NAND_TIMING2       0x28
  30 #define CAFE_NAND_TIMING3       0x2c
  31 #define CAFE_NAND_NONMEM        0x30
  32 #define CAFE_NAND_ECC_RESULT    0x3C
  33 #define CAFE_NAND_ECC_SYN01     0x50
  34 #define CAFE_NAND_ECC_SYN23     0x54
  35 #define CAFE_NAND_ECC_SYN45     0x58
  36 #define CAFE_NAND_ECC_SYN67     0x5c
  37 #define CAFE_NAND_DMA_CTRL      0x40
  38 #define CAFE_NAND_DMA_ADDR0     0x44
  39 #define CAFE_NAND_DMA_ADDR1     0x48
  40 #define CAFE_NAND_READ_DATA     0x1000
  41 #define CAFE_NAND_WRITE_DATA    0x2000
  42
  43 int cafe_correct_ecc(unsigned char *buf,
  44                      unsigned short *chk_syndrome_list);
  45
  46 struct cafe_priv {
  47         struct nand_chip nand;
  48         struct pci_dev *pdev;
  49         void __iomem *mmio;
  50         uint32_t ctl1;
  51         uint32_t ctl2;
  52         int datalen;
  53         int nr_data;
  54         int data_pos;
  55         int page_addr;
  56         dma_addr_t dmaaddr;
  57         unsigned char *dmabuf;
  58
  59 };
  60
  61 static int usedma = 0;
  62 module_param(usedma, int, 0644);
  63
  64 static int skipbbt = 0;
  65 module_param(skipbbt, int, 0644);
  66
  67 static int debug = 0;
  68 module_param(debug, int, 0644);
  69
  70 /* Hrm. Why isn't this already conditional on something in the struct device? */
  71 #define cafe_dev_dbg(dev, args...) do { if (debug) dev_dbg(dev, ##args); } while(0)
  72
  73
  74 static int cafe_device_ready(struct mtd_info *mtd)
  75 {
  76         struct cafe_priv *cafe = mtd->priv;
  77         int result = !!(readl(cafe->mmio + CAFE_NAND_STATUS) | 0x40000000);
  78
  79         uint32_t irqs = readl(cafe->mmio + CAFE_NAND_IRQ);
  80         writel(irqs, cafe->mmio+CAFE_NAND_IRQ);
  81         cafe_dev_dbg(&cafe->pdev->dev, "NAND device is%s ready, IRQ %x (%x) (%x,%x)\n",
  82                 result?"":" not", irqs, readl(cafe->mmio + CAFE_NAND_IRQ),
  83                 readl(cafe->mmio + 0x3008), readl(cafe->mmio + 0x300c));
  84         return result;
  85 }
  86
  87
  88 static void cafe_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
  89 {
  90         struct cafe_priv *cafe = mtd->priv;
  91
  92         if (usedma)
  93                 memcpy(cafe->dmabuf + cafe->datalen, buf, len);
  94         else
  95                 memcpy_toio(cafe->mmio + CAFE_NAND_WRITE_DATA + cafe->datalen, buf, len);
  96         cafe->datalen += len;
  97
  98         cafe_dev_dbg(&cafe->pdev->dev, "Copy 0x%x bytes to write buffer. datalen 0x%x\n",
  99                 len, cafe->datalen);
 100 }
 101
 102 static void cafe_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
 103 {
 104         struct cafe_priv *cafe = mtd->priv;
 105
 106         if (usedma)
 107                 memcpy(buf, cafe->dmabuf + cafe->datalen, len);
 108         else
 109                 memcpy_fromio(buf, cafe->mmio + CAFE_NAND_READ_DATA + cafe->datalen, len);
 110
 111         cafe_dev_dbg(&cafe->pdev->dev, "Copy 0x%x bytes from position 0x%x in read buffer.\n",
 112                   len, cafe->datalen);
 113         cafe->datalen += len;
 114 }
 115
 116 static uint8_t cafe_read_byte(struct mtd_info *mtd)
 117 {
 118         struct cafe_priv *cafe = mtd->priv;
 119         uint8_t d;
 120
 121         cafe_read_buf(mtd, &d, 1);
 122         cafe_dev_dbg(&cafe->pdev->dev, "Read %02x\n", d);
 123
 124         return d;
 125 }
 126
 127 static void cafe_nand_cmdfunc(struct mtd_info *mtd, unsigned command,
 128                               int column, int page_addr)
 129 {
 130         struct cafe_priv *cafe = mtd->priv;
 131         int adrbytes = 0;
 132         uint32_t ctl1;
 133         uint32_t doneint = 0x80000000;
 134         int i;
 135
 136         cafe_dev_dbg(&cafe->pdev->dev, "cmdfunc %02x, 0x%x, 0x%x\n",
 137                 command, column, page_addr);
 138
 139         if (command == NAND_CMD_ERASE2 || command == NAND_CMD_PAGEPROG) {
 140                 /* Second half of a command we already calculated */
 141                 writel(cafe->ctl2 | 0x100 | command, cafe->mmio + 0x04);
 142                 ctl1 = cafe->ctl1;
 143                 cafe_dev_dbg(&cafe->pdev->dev, "Continue command, ctl1 %08x, #data %d\n",
 144                           cafe->ctl1, cafe->nr_data);
 145                 goto do_command;
 146         }
 147         /* Reset ECC engine */
 148         writel(0, cafe->mmio + CAFE_NAND_CTRL2);
 149
 150         /* Emulate NAND_CMD_READOOB on large-page chips */
 151         if (mtd->writesize > 512 &&
 152             command == NAND_CMD_READOOB) {
 153                 column += mtd->writesize;
 154                 command = NAND_CMD_READ0;
 155         }
 156
 157         /* FIXME: Do we need to send read command before sending data
 158            for small-page chips, to position the buffer correctly? */
 159
 160         if (column != -1) {
 161                 writel(column, cafe->mmio + 0x1c);
 162                 adrbytes = 2;
 163                 if (page_addr != -1)
 164                         goto write_adr2;
 165         } else if (page_addr != -1) {
 166                 writel(page_addr & 0xffff, cafe->mmio + 0x1c);
 167                 page_addr >>= 16;
 168         write_adr2:
 169                 writel(page_addr, cafe->mmio+0x20);
 170                 adrbytes += 2;
 171                 if (mtd->size > mtd->writesize << 16)
 172                         adrbytes++;
 173         }
 174
 175         cafe->data_pos = cafe->datalen = 0;
 176
 177         /* Set command valid bit */
 178         ctl1 = 0x80000000 | command;
 179
 180         /* Set RD or WR bits as appropriate */
 181         if (command == NAND_CMD_READID || command == NAND_CMD_STATUS) {
 182                 ctl1 |= (1<<26); /* rd */
 183                 /* Always 5 bytes, for now */
 184                 cafe->datalen = 4;
 185                 /* And one address cycle -- even for STATUS, since the controller doesn't work without */
 186                 adrbytes = 1;
 187         } else if (command == NAND_CMD_READ0 || command == NAND_CMD_READ1 ||
 188                    command == NAND_CMD_READOOB || command == NAND_CMD_RNDOUT) {
 189                 ctl1 |= 1<<26; /* rd */
 190                 /* For now, assume just read to end of page */
 191                 cafe->datalen = mtd->writesize + mtd->oobsize - column;
 192         } else if (command == NAND_CMD_SEQIN)
 193                 ctl1 |= 1<<25; /* wr */
 194
 195         /* Set number of address bytes */
 196         if (adrbytes)
 197                 ctl1 |= ((adrbytes-1)|8) << 27;
 198
 199         if (command == NAND_CMD_SEQIN || command == NAND_CMD_ERASE1) {
 200                 /* Ignore the first command of a pair; the hardware
 201                    deals with them both at once, later */
 202                 cafe->ctl1 = ctl1;
 203                 cafe->ctl2 = 0;
 204                 cafe_dev_dbg(&cafe->pdev->dev, "Setup for delayed command, ctl1 %08x, dlen %x\n",
 205                           cafe->ctl1, cafe->datalen);
 206                 return;
 207         }
 208         /* RNDOUT and READ0 commands need a following byte */
 209         if (command == NAND_CMD_RNDOUT)
 210                 writel(cafe->ctl2 | 0x100 | NAND_CMD_RNDOUTSTART, cafe->mmio + CAFE_NAND_CTRL2);
 211         else if (command == NAND_CMD_READ0 && mtd->writesize > 512)
 212                 writel(cafe->ctl2 | 0x100 | NAND_CMD_READSTART, cafe->mmio + CAFE_NAND_CTRL2);
 213
 214  do_command:
 215 #if 0
 216         // ECC on read only works if we ...
 217         if (cafe->datalen == 2112)
 218                 cafe->datalen = 2062;
 219 #endif
 220         cafe_dev_dbg(&cafe->pdev->dev, "dlen %x, ctl1 %x, ctl2 %x\n",
 221                 cafe->datalen, ctl1, readl(cafe->mmio+CAFE_NAND_CTRL2));
 222         /* NB: The datasheet lies -- we really should be subtracting 1 here */
 223         writel(cafe->datalen, cafe->mmio + CAFE_NAND_DATA_LEN);
 224         writel(0x90000000, cafe->mmio + CAFE_NAND_IRQ);
 225         if (usedma && (ctl1 & (3<<25))) {
 226                 uint32_t dmactl = 0xc0000000 + cafe->datalen;
 227                 /* If WR or RD bits set, set up DMA */
 228                 if (ctl1 & (1<<26)) {
 229                         /* It's a read */
 230                         dmactl |= (1<<29);
 231                         /* ... so it's done when the DMA is done, not just
 232                            the command. */
 233                         doneint = 0x10000000;
 234                 }
 235                 writel(dmactl, cafe->mmio + 0x40);
 236         }
 237 #if 0
 238         printk("DMA setup is %x, status %x, ctl1 %x\n", readl(cafe->mmio + 0x40), readl(cafe->mmio + 0x0c), readl(cafe->mmio));
 239         printk("DMA setup is %x, status %x, ctl1 %x\n", readl(cafe->mmio + 0x40), readl(cafe->mmio + 0x0c), readl(cafe->mmio));
 240 #endif
 241         cafe->datalen = 0;
 242
 243 #if 0
 244         printk("About to write command %08x\n", ctl1);
 245         for (i=0; i< 0x5c; i+=4)
 246                 printk("Register %x: %08x\n", i, readl(cafe->mmio + i));
 247 #endif
 248         writel(ctl1, cafe->mmio + CAFE_NAND_CTRL1);
 249         /* Apply this short delay always to ensure that we do wait tWB in
 250          * any case on any machine. */
 251         ndelay(100);
 252
 253         if (1) {
 254                 int c = 500000;
 255                 uint32_t irqs;
 256
 257                 while (c--) {
 258                         irqs = readl(cafe->mmio + CAFE_NAND_IRQ);
 259                         if (irqs & doneint)
 260                                 break;
 261                         udelay(1);
 262                         if (!(c % 100000))
 263                                 cafe_dev_dbg(&cafe->pdev->dev, "Wait for ready, IRQ %x\n", irqs);
 264                         cpu_relax();
 265                 }
 266                 writel(doneint, cafe->mmio + CAFE_NAND_IRQ);
 267                 cafe_dev_dbg(&cafe->pdev->dev, "Command %x completed after %d usec, irqs %x (%x)\n", command, 50000-c, irqs, readl(cafe->mmio + CAFE_NAND_IRQ));
 268         }
 269
 270
 271         cafe->ctl2 &= ~(1<<8);
 272         cafe->ctl2 &= ~(1<<30);
 273
 274         switch (command) {
 275
 276         case NAND_CMD_CACHEDPROG:
 277         case NAND_CMD_PAGEPROG:
 278         case NAND_CMD_ERASE1:
 279         case NAND_CMD_ERASE2:
 280         case NAND_CMD_SEQIN:
 281         case NAND_CMD_RNDIN:
 282         case NAND_CMD_STATUS:
 283         case NAND_CMD_DEPLETE1:
 284         case NAND_CMD_RNDOUT:
 285         case NAND_CMD_STATUS_ERROR:
 286         case NAND_CMD_STATUS_ERROR0:
 287         case NAND_CMD_STATUS_ERROR1:
 288         case NAND_CMD_STATUS_ERROR2:
 289         case NAND_CMD_STATUS_ERROR3:
 290                 writel(cafe->ctl2, cafe->mmio + CAFE_NAND_CTRL2);
 291                 return;
 292         }
 293         nand_wait_ready(mtd);
 294         writel(cafe->ctl2, cafe->mmio + CAFE_NAND_CTRL2);
 295 }
 296
 297 static void cafe_select_chip(struct mtd_info *mtd, int chipnr)
 298 {
 299         //struct cafe_priv *cafe = mtd->priv;
 300         //      cafe_dev_dbg(&cafe->pdev->dev, "select_chip %d\n", chipnr);
 301 }
 302 static int cafe_nand_interrupt(int irq, void *id, struct pt_regs *regs)
 303 {
 304         struct mtd_info *mtd = id;
 305         struct cafe_priv *cafe = mtd->priv;
 306         uint32_t irqs = readl(cafe->mmio + CAFE_NAND_IRQ);
 307         writel(irqs & ~0x90000000, cafe->mmio + CAFE_NAND_IRQ);
 308         if (!irqs)
 309                 return IRQ_NONE;
 310
 311         cafe_dev_dbg(&cafe->pdev->dev, "irq, bits %x (%x)\n", irqs, readl(cafe->mmio + CAFE_NAND_IRQ));
 312         return IRQ_HANDLED;
 313 }
 314
 315 static void cafe_nand_bug(struct mtd_info *mtd)
 316 {
 317         BUG();
 318 }
 319
 320 static int cafe_nand_write_oob(struct mtd_info *mtd,
 321                                struct nand_chip *chip, int page)
 322 {
 323         int status = 0;
 324
 325         chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
 326         chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
 327         chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
 328         status = chip->waitfunc(mtd, chip);
 329
 330         return status & NAND_STATUS_FAIL ? -EIO : 0;
 331 }
 332
 333 /* Don't use -- use nand_read_oob_std for now */
 334 static int cafe_nand_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
 335                               int page, int sndcmd)
 336 {
 337         chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
 338         chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
 339         return 1;
 340 }
 341 /**
 342  * cafe_nand_read_page_syndrome - {REPLACABLE] hardware ecc syndrom based page read
 343  * @mtd:        mtd info structure
 344  * @chip:       nand chip info structure
 345  * @buf:        buffer to store read data
 346  *
 347  * The hw generator calculates the error syndrome automatically. Therefor
 348  * we need a special oob layout and handling.
 349  */
 350 static int cafe_nand_read_page(struct mtd_info *mtd, struct nand_chip *chip,
 351                                uint8_t *buf)
 352 {
 353         struct cafe_priv *cafe = mtd->priv;
 354
 355         dev_dbg(&cafe->pdev->dev, "ECC result %08x SYN1,2 %08x\n",
 356                 readl(cafe->mmio + CAFE_NAND_ECC_RESULT),
 357                 readl(cafe->mmio + CAFE_NAND_ECC_SYN01));
 358
 359         chip->read_buf(mtd, buf, mtd->writesize);
 360         chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
 361
 362         if (readl(cafe->mmio + CAFE_NAND_ECC_RESULT) & (1<<18)) {
 363                 unsigned short syn[8];
 364                 int i;
 365
 366                 for (i=0; i<8; i+=2) {
 367                         uint32_t tmp = readl(cafe->mmio + CAFE_NAND_ECC_SYN01 + (i*2));
 368                         syn[i] = tmp & 0xfff;
 369                         syn[i+1] = (tmp >> 16) & 0xfff;
 370                 }
 371
 372                 if ((i = cafe_correct_ecc(buf, syn)) < 0) {
 373                         dev_dbg(&cafe->pdev->dev, "Failed to correct ECC\n");
 374                         mtd->ecc_stats.failed++;
 375                 } else {
 376                         dev_dbg(&cafe->pdev->dev, "Corrected %d symbol errors\n", i);
 377                         mtd->ecc_stats.corrected += i;
 378                 }
 379         }
 380
 381
 382         return 0;
 383 }
 384
 385 static struct nand_ecclayout cafe_oobinfo_2048 = {
 386         .eccbytes = 14,
 387         .eccpos = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13},
 388         .oobfree = {{14, 50}}
 389 };
 390
 391 /* Ick. The BBT code really ought to be able to work this bit out
 392    for itself from the above */
 393 static uint8_t cafe_bbt_pattern[] = {'B', 'b', 't', '0' };
 394 static uint8_t cafe_mirror_pattern[] = {'1', 't', 'b', 'B' };
 395
 396 static struct nand_bbt_descr cafe_bbt_main_descr_2048 = {
 397         .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
 398                 | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
 399         .offs = 14,
 400         .len = 4,
 401         .veroffs = 18,
 402         .maxblocks = 4,
 403         .pattern = cafe_bbt_pattern
 404 };
 405
 406 static struct nand_bbt_descr cafe_bbt_mirror_descr_2048 = {
 407         .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
 408                 | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
 409         .offs = 14,
 410         .len = 4,
 411         .veroffs = 18,
 412         .maxblocks = 4,
 413         .pattern = cafe_mirror_pattern
 414 };
 415
 416 static struct nand_ecclayout cafe_oobinfo_512 = {
 417         .eccbytes = 14,
 418         .eccpos = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13},
 419         .oobfree = {{14, 2}}
 420 };
 421
 422 static void cafe_nand_write_page_lowlevel(struct mtd_info *mtd,
 423                                           struct nand_chip *chip, const uint8_t *buf)
 424 {
 425         struct cafe_priv *cafe = mtd->priv;
 426
 427         chip->write_buf(mtd, buf, mtd->writesize);
 428         chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
 429
 430         /* Set up ECC autogeneration */
 431         cafe->ctl2 |= (1<<27) | (1<<30);
 432         if (mtd->writesize == 2048)
 433                 cafe->ctl2 |= (1<<29);
 434 }
 435
 436 static int cafe_nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
 437                                 const uint8_t *buf, int page, int cached, int raw)
 438 {
 439         int status;
 440
 441         chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
 442
 443         if (unlikely(raw))
 444                 chip->ecc.write_page_raw(mtd, chip, buf);
 445         else
 446                 chip->ecc.write_page(mtd, chip, buf);
 447
 448         /*
 449          * Cached progamming disabled for now, Not sure if its worth the
 450          * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s)
 451          */
 452         cached = 0;
 453
 454         if (!cached || !(chip->options & NAND_CACHEPRG)) {
 455
 456                 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
 457                 status = chip->waitfunc(mtd, chip);
 458                 /*
 459                  * See if operation failed and additional status checks are
 460                  * available
 461                  */
 462                 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
 463                         status = chip->errstat(mtd, chip, FL_WRITING, status,
 464                                                page);
 465
 466                 if (status & NAND_STATUS_FAIL)
 467                         return -EIO;
 468         } else {
 469                 chip->cmdfunc(mtd, NAND_CMD_CACHEDPROG, -1, -1);
 470                 status = chip->waitfunc(mtd, chip);
 471         }
 472
 473 #ifdef CONFIG_MTD_NAND_VERIFY_WRITE
 474         /* Send command to read back the data */
 475         chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
 476
 477         if (chip->verify_buf(mtd, buf, mtd->writesize))
 478                 return -EIO;
 479 #endif
 480         return 0;
 481 }
 482
 483 static int cafe_nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
 484 {
 485         return 0;
 486 }
 487
 488 static int __devinit cafe_nand_probe(struct pci_dev *pdev,
 489                                      const struct pci_device_id *ent)
 490 {
 491         struct mtd_info *mtd;
 492         struct cafe_priv *cafe;
 493         uint32_t ctrl;
 494         int err = 0;
 495
 496         err = pci_enable_device(pdev);
 497         if (err)
 498                 return err;
 499
 500         pci_set_master(pdev);
 501
 502         mtd = kzalloc(sizeof(*mtd) + sizeof(struct cafe_priv), GFP_KERNEL);
 503         if (!mtd) {
 504                 dev_warn(&pdev->dev, "failed to alloc mtd_info\n");
 505                 return  -ENOMEM;
 506         }
 507         cafe = (void *)(&mtd[1]);
 508
 509         mtd->priv = cafe;
 510         mtd->owner = THIS_MODULE;
 511
 512         cafe->pdev = pdev;
 513         cafe->mmio = pci_iomap(pdev, 0, 0);
 514         if (!cafe->mmio) {
 515                 dev_warn(&pdev->dev, "failed to iomap\n");
 516                 err = -ENOMEM;
 517                 goto out_free_mtd;
 518         }
 519         cafe->dmabuf = dma_alloc_coherent(&cafe->pdev->dev, 2112 + sizeof(struct nand_buffers),
 520                                           &cafe->dmaaddr, GFP_KERNEL);
 521         if (!cafe->dmabuf) {
 522                 err = -ENOMEM;
 523                 goto out_ior;
 524         }
 525         cafe->nand.buffers = (void *)cafe->dmabuf + 2112;
 526
 527         cafe->nand.cmdfunc = cafe_nand_cmdfunc;
 528         cafe->nand.dev_ready = cafe_device_ready;
 529         cafe->nand.read_byte = cafe_read_byte;
 530         cafe->nand.read_buf = cafe_read_buf;
 531         cafe->nand.write_buf = cafe_write_buf;
 532         cafe->nand.select_chip = cafe_select_chip;
 533
 534         cafe->nand.chip_delay = 0;
 535
 536         /* Enable the following for a flash based bad block table */
 537         cafe->nand.options = NAND_USE_FLASH_BBT | NAND_NO_AUTOINCR | NAND_OWN_BUFFERS;
 538
 539         if (skipbbt) {
 540                 cafe->nand.options |= NAND_SKIP_BBTSCAN;
 541                 cafe->nand.block_bad = cafe_nand_block_bad;
 542         }
 543
 544         /* Timings from Marvell's test code (not verified or calculated by us) */
 545         writel(0xffffffff, cafe->mmio + CAFE_NAND_IRQ_MASK);
 546 #if 1
 547         writel(0x01010a0a, cafe->mmio + CAFE_NAND_TIMING1);
 548         writel(0x24121212, cafe->mmio + CAFE_NAND_TIMING2);
 549         writel(0x11000000, cafe->mmio + CAFE_NAND_TIMING3);
 550 #else
 551         writel(0xffffffff, cafe->mmio + CAFE_NAND_TIMING1);
 552         writel(0xffffffff, cafe->mmio + CAFE_NAND_TIMING2);
 553         writel(0xffffffff, cafe->mmio + CAFE_NAND_TIMING3);
 554 #endif
 555         writel(0xffffffff, cafe->mmio + CAFE_NAND_IRQ_MASK);
 556         err = request_irq(pdev->irq, &cafe_nand_interrupt, SA_SHIRQ, "CAFE NAND", mtd);
 557         if (err) {
 558                 dev_warn(&pdev->dev, "Could not register IRQ %d\n", pdev->irq);
 559
 560                 goto out_free_dma;
 561         }
 562 #if 1
 563         /* Disable master reset, enable NAND clock */
 564         ctrl = readl(cafe->mmio + 0x3004);
 565         ctrl &= 0xffffeff0;
 566         ctrl |= 0x00007000;
 567         writel(ctrl | 0x05, cafe->mmio + 0x3004);
 568         writel(ctrl | 0x0a, cafe->mmio + 0x3004);
 569         writel(0, cafe->mmio + 0x40);
 570
 571         writel(0x7006, cafe->mmio + 0x3004);
 572         writel(0x700a, cafe->mmio + 0x3004);
 573
 574         /* Set up DMA address */
 575         writel(cafe->dmaaddr & 0xffffffff, cafe->mmio + 0x44);
 576         if (sizeof(cafe->dmaaddr) > 4)
 577                 writel((cafe->dmaaddr >> 16) >> 16, cafe->mmio + 0x48);
 578         else
 579                 writel(0, cafe->mmio + 0x48);
 580         cafe_dev_dbg(&cafe->pdev->dev, "Set DMA address to %x (virt %p)\n",
 581                 readl(cafe->mmio+0x44), cafe->dmabuf);
 582
 583         /* Enable NAND IRQ in global IRQ mask register */
 584         writel(0x80000007, cafe->mmio + 0x300c);
 585         cafe_dev_dbg(&cafe->pdev->dev, "Control %x, IRQ mask %x\n",
 586                 readl(cafe->mmio + 0x3004), readl(cafe->mmio + 0x300c));
 587 #endif
 588 #if 1
 589         mtd->writesize=2048;
 590         mtd->oobsize = 0x40;
 591         memset(cafe->dmabuf, 0x5a, 2112);
 592         cafe->nand.cmdfunc(mtd, NAND_CMD_READID, 0, -1);
 593         cafe->nand.read_byte(mtd);
 594         cafe->nand.read_byte(mtd);
 595         cafe->nand.read_byte(mtd);
 596         cafe->nand.read_byte(mtd);
 597         cafe->nand.read_byte(mtd);
 598 #endif
 599 #if 0
 600         cafe->nand.cmdfunc(mtd, NAND_CMD_READ0, 0, 0);
 601         //      nand_wait_ready(mtd);
 602         cafe->nand.read_byte(mtd);
 603         cafe->nand.read_byte(mtd);
 604         cafe->nand.read_byte(mtd);
 605         cafe->nand.read_byte(mtd);
 606 #endif
 607 #if 0
 608         writel(0x84600070, cafe->mmio);
 609         udelay(10);
 610         cafe_dev_dbg(&cafe->pdev->dev, "Status %x\n", readl(cafe->mmio + 0x30));
 611 #endif
 612         /* Scan to find existance of the device */
 613         if (nand_scan_ident(mtd, 1)) {
 614                 err = -ENXIO;
 615                 goto out_irq;
 616         }
 617
 618         cafe->ctl2 = 1<<27; /* Reed-Solomon ECC */
 619         if (mtd->writesize == 2048)
 620                 cafe->ctl2 |= 1<<29; /* 2KiB page size */
 621
 622         /* Set up ECC according to the type of chip we found */
 623         if (mtd->writesize == 512 || mtd->writesize == 2048) {
 624                 cafe->nand.ecc.mode = NAND_ECC_HW_SYNDROME;
 625                 cafe->nand.ecc.size = mtd->writesize;
 626                 cafe->nand.ecc.bytes = 14;
 627                 cafe->nand.ecc.layout = &cafe_oobinfo_2048;
 628                 cafe->nand.bbt_td = &cafe_bbt_main_descr_2048;
 629                 cafe->nand.bbt_md = &cafe_bbt_mirror_descr_2048;
 630                 cafe->nand.ecc.hwctl  = (void *)cafe_nand_bug;
 631                 cafe->nand.ecc.calculate = (void *)cafe_nand_bug;
 632                 cafe->nand.ecc.correct  = (void *)cafe_nand_bug;
 633                 cafe->nand.write_page = cafe_nand_write_page;
 634                 cafe->nand.ecc.write_page = cafe_nand_write_page_lowlevel;
 635                 cafe->nand.ecc.write_oob = cafe_nand_write_oob;
 636                 cafe->nand.ecc.read_page = cafe_nand_read_page;
 637                 cafe->nand.ecc.read_oob = cafe_nand_read_oob;
 638
 639         } else {
 640                 printk(KERN_WARNING "Unexpected NAND flash writesize %d. Using software ECC\n",
 641                        mtd->writesize);
 642                 cafe->nand.ecc.mode = NAND_ECC_NONE;
 643         }
 644
 645         err = nand_scan_tail(mtd);
 646         if (err)
 647                 goto out_irq;
 648
 649         pci_set_drvdata(pdev, mtd);
 650         add_mtd_device(mtd);
 651         goto out;
 652
 653  out_irq:
 654         /* Disable NAND IRQ in global IRQ mask register */
 655         writel(~1 & readl(cafe->mmio + 0x300c), cafe->mmio + 0x300c);
 656         free_irq(pdev->irq, mtd);
 657  out_free_dma:
 658         dma_free_coherent(&cafe->pdev->dev, 2112, cafe->dmabuf, cafe->dmaaddr);
 659  out_ior:
 660         pci_iounmap(pdev, cafe->mmio);
 661  out_free_mtd:
 662         kfree(mtd);
 663  out:
 664         return err;
 665 }
 666
 667 static void __devexit cafe_nand_remove(struct pci_dev *pdev)
 668 {
 669         struct mtd_info *mtd = pci_get_drvdata(pdev);
 670         struct cafe_priv *cafe = mtd->priv;
 671
 672         del_mtd_device(mtd);
 673         /* Disable NAND IRQ in global IRQ mask register */
 674         writel(~1 & readl(cafe->mmio + 0x300c), cafe->mmio + 0x300c);
 675         free_irq(pdev->irq, mtd);
 676         nand_release(mtd);
 677         pci_iounmap(pdev, cafe->mmio);
 678         dma_free_coherent(&cafe->pdev->dev, 2112, cafe->dmabuf, cafe->dmaaddr);
 679         kfree(mtd);
 680 }
 681
 682 static struct pci_device_id cafe_nand_tbl[] = {
 683         { 0x11ab, 0x4100, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_MEMORY_FLASH << 8, 0xFFFF0 }
 684 };
 685
 686 MODULE_DEVICE_TABLE(pci, cafe_nand_tbl);
 687
 688 static struct pci_driver cafe_nand_pci_driver = {
 689         .name = "CAFÉ NAND",
 690         .id_table = cafe_nand_tbl,
 691         .probe = cafe_nand_probe,
 692         .remove = __devexit_p(cafe_nand_remove),
 693 #ifdef CONFIG_PMx
 694         .suspend = cafe_nand_suspend,
 695         .resume = cafe_nand_resume,
 696 #endif
 697 };
 698
 699 static int cafe_nand_init(void)
 700 {
 701         return pci_register_driver(&cafe_nand_pci_driver);
 702 }
 703
 704 static void cafe_nand_exit(void)
 705 {
 706         pci_unregister_driver(&cafe_nand_pci_driver);
 707 }
 708 module_init(cafe_nand_init);
 709 module_exit(cafe_nand_exit);
 710
 711 MODULE_LICENSE("GPL");
 712 MODULE_AUTHOR("David Woodhouse <dwmw2@infradead.org>");
 713 MODULE_DESCRIPTION("NAND flash driver for OLPC CAFE chip");
 714
 715 /* Correct ECC for 2048 bytes of 0xff:
 716    41 a0 71 65 54 27 f3 93 ec a9 be ed 0b a1 */
 717
 718 /* dwmw2's B-test board, in case of completely screwing it:
 719 Bad eraseblock 2394 at 0x12b40000
 720 Bad eraseblock 2627 at 0x14860000
 721 Bad eraseblock 3349 at 0x1a2a0000
 722 */