5 * This is the generic MTD driver for NAND flash devices. It should be
6 * capable of working with almost all NAND chips currently available.
7 * Basic support for AG-AND chips is provided.
9 * Additional technical information is available on
10 * http://www.linux-mtd.infradead.org/tech/nand.html
12 * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
13 * 2002-2006 Thomas Gleixner (tglx@linutronix.de)
16 * David Woodhouse for adding multichip support
18 * Aleph One Ltd. and Toby Churchill Ltd. for supporting the
19 * rework for 2K page size chips
22 * Enable cached programming for 2k page size chips
23 * Check, if mtd->ecctype should be set to MTD_ECC_HW
24 * if we have HW ecc support.
25 * The AG-AND chips have nice features for speed improvement,
26 * which are not supported yet. Read / program 4 pages in one go.
28 * This program is free software; you can redistribute it and/or modify
29 * it under the terms of the GNU General Public License version 2 as
30 * published by the Free Software Foundation.
34 #include <linux/module.h>
35 #include <linux/delay.h>
36 #include <linux/errno.h>
37 #include <linux/err.h>
38 #include <linux/sched.h>
39 #include <linux/slab.h>
40 #include <linux/types.h>
41 #include <linux/mtd/mtd.h>
42 #include <linux/mtd/nand.h>
43 #include <linux/mtd/nand_ecc.h>
44 #include <linux/mtd/compatmac.h>
45 #include <linux/interrupt.h>
46 #include <linux/bitops.h>
47 #include <linux/leds.h>
50 #ifdef CONFIG_MTD_PARTITIONS
51 #include <linux/mtd/partitions.h>
54 /* Define default oob placement schemes for large and small page devices */
55 static struct nand_oobinfo nand_oob_8 = {
56 .useecc = MTD_NANDECC_AUTOPLACE,
59 .oobfree = {{3, 2}, {6, 2}}
62 static struct nand_oobinfo nand_oob_16 = {
63 .useecc = MTD_NANDECC_AUTOPLACE,
65 .eccpos = {0, 1, 2, 3, 6, 7},
69 static struct nand_oobinfo nand_oob_64 = {
70 .useecc = MTD_NANDECC_AUTOPLACE,
73 40, 41, 42, 43, 44, 45, 46, 47,
74 48, 49, 50, 51, 52, 53, 54, 55,
75 56, 57, 58, 59, 60, 61, 62, 63},
79 /* This is used for padding purposes in nand_write_oob */
80 static uint8_t ffchars[] = {
81 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
82 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
83 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
84 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
85 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
86 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
87 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
88 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
92 * NAND low-level MTD interface functions
94 static void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len);
95 static void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len);
96 static int nand_verify_buf(struct mtd_info *mtd, const uint8_t *buf, int len);
98 static int nand_read(struct mtd_info *mtd, loff_t from, size_t len,
99 size_t *retlen, uint8_t *buf);
100 static int nand_read_oob(struct mtd_info *mtd, loff_t from, size_t len,
101 size_t *retlen, uint8_t *buf);
102 static int nand_write(struct mtd_info *mtd, loff_t to, size_t len,
103 size_t *retlen, const uint8_t *buf);
104 static int nand_write_oob(struct mtd_info *mtd, loff_t to, size_t len,
105 size_t *retlen, const uint8_t *buf);
106 static int nand_erase(struct mtd_info *mtd, struct erase_info *instr);
107 static void nand_sync(struct mtd_info *mtd);
109 /* Some internal functions */
110 static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
111 int page, uint8_t * oob_buf,
112 struct nand_oobinfo *oobsel, int mode);
113 #ifdef CONFIG_MTD_NAND_VERIFY_WRITE
114 static int nand_verify_pages(struct mtd_info *mtd, struct nand_chip *chip,
115 int page, int numpages, uint8_t *oob_buf,
116 struct nand_oobinfo *oobsel, int chipnr,
119 #define nand_verify_pages(...) (0)
122 static int nand_get_device(struct nand_chip *chip, struct mtd_info *mtd,
126 * For devices which display every fart in the system on a seperate LED. Is
127 * compiled away when LED support is disabled.
129 DEFINE_LED_TRIGGER(nand_led_trigger);
132 * nand_release_device - [GENERIC] release chip
133 * @mtd: MTD device structure
135 * Deselect, release chip lock and wake up anyone waiting on the device
137 static void nand_release_device(struct mtd_info *mtd)
139 struct nand_chip *chip = mtd->priv;
141 /* De-select the NAND device */
142 chip->select_chip(mtd, -1);
144 /* Release the controller and the chip */
145 spin_lock(&chip->controller->lock);
146 chip->controller->active = NULL;
147 chip->state = FL_READY;
148 wake_up(&chip->controller->wq);
149 spin_unlock(&chip->controller->lock);
153 * nand_read_byte - [DEFAULT] read one byte from the chip
154 * @mtd: MTD device structure
156 * Default read function for 8bit buswith
158 static uint8_t nand_read_byte(struct mtd_info *mtd)
160 struct nand_chip *chip = mtd->priv;
161 return readb(chip->IO_ADDR_R);
165 * nand_read_byte16 - [DEFAULT] read one byte endianess aware from the chip
166 * @mtd: MTD device structure
168 * Default read function for 16bit buswith with
169 * endianess conversion
171 static uint8_t nand_read_byte16(struct mtd_info *mtd)
173 struct nand_chip *chip = mtd->priv;
174 return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R));
178 * nand_read_word - [DEFAULT] read one word from the chip
179 * @mtd: MTD device structure
181 * Default read function for 16bit buswith without
182 * endianess conversion
184 static u16 nand_read_word(struct mtd_info *mtd)
186 struct nand_chip *chip = mtd->priv;
187 return readw(chip->IO_ADDR_R);
191 * nand_select_chip - [DEFAULT] control CE line
192 * @mtd: MTD device structure
193 * @chip: chipnumber to select, -1 for deselect
195 * Default select function for 1 chip devices.
197 static void nand_select_chip(struct mtd_info *mtd, int chipnr)
199 struct nand_chip *chip = mtd->priv;
203 chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
206 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
207 NAND_NCE | NAND_CTRL_CHANGE);
216 * nand_write_buf - [DEFAULT] write buffer to chip
217 * @mtd: MTD device structure
219 * @len: number of bytes to write
221 * Default write function for 8bit buswith
223 static void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
226 struct nand_chip *chip = mtd->priv;
228 for (i = 0; i < len; i++)
229 writeb(buf[i], chip->IO_ADDR_W);
233 * nand_read_buf - [DEFAULT] read chip data into buffer
234 * @mtd: MTD device structure
235 * @buf: buffer to store date
236 * @len: number of bytes to read
238 * Default read function for 8bit buswith
240 static void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
243 struct nand_chip *chip = mtd->priv;
245 for (i = 0; i < len; i++)
246 buf[i] = readb(chip->IO_ADDR_R);
250 * nand_verify_buf - [DEFAULT] Verify chip data against buffer
251 * @mtd: MTD device structure
252 * @buf: buffer containing the data to compare
253 * @len: number of bytes to compare
255 * Default verify function for 8bit buswith
257 static int nand_verify_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
260 struct nand_chip *chip = mtd->priv;
262 for (i = 0; i < len; i++)
263 if (buf[i] != readb(chip->IO_ADDR_R))
270 * nand_write_buf16 - [DEFAULT] write buffer to chip
271 * @mtd: MTD device structure
273 * @len: number of bytes to write
275 * Default write function for 16bit buswith
277 static void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
280 struct nand_chip *chip = mtd->priv;
281 u16 *p = (u16 *) buf;
284 for (i = 0; i < len; i++)
285 writew(p[i], chip->IO_ADDR_W);
290 * nand_read_buf16 - [DEFAULT] read chip data into buffer
291 * @mtd: MTD device structure
292 * @buf: buffer to store date
293 * @len: number of bytes to read
295 * Default read function for 16bit buswith
297 static void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
300 struct nand_chip *chip = mtd->priv;
301 u16 *p = (u16 *) buf;
304 for (i = 0; i < len; i++)
305 p[i] = readw(chip->IO_ADDR_R);
309 * nand_verify_buf16 - [DEFAULT] Verify chip data against buffer
310 * @mtd: MTD device structure
311 * @buf: buffer containing the data to compare
312 * @len: number of bytes to compare
314 * Default verify function for 16bit buswith
316 static int nand_verify_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
319 struct nand_chip *chip = mtd->priv;
320 u16 *p = (u16 *) buf;
323 for (i = 0; i < len; i++)
324 if (p[i] != readw(chip->IO_ADDR_R))
331 * nand_block_bad - [DEFAULT] Read bad block marker from the chip
332 * @mtd: MTD device structure
333 * @ofs: offset from device start
334 * @getchip: 0, if the chip is already selected
336 * Check, if the block is bad.
338 static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
340 int page, chipnr, res = 0;
341 struct nand_chip *chip = mtd->priv;
345 page = (int)(ofs >> chip->page_shift);
346 chipnr = (int)(ofs >> chip->chip_shift);
348 nand_get_device(chip, mtd, FL_READING);
350 /* Select the NAND device */
351 chip->select_chip(mtd, chipnr);
355 if (chip->options & NAND_BUSWIDTH_16) {
356 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos & 0xFE,
357 page & chip->pagemask);
358 bad = cpu_to_le16(chip->read_word(mtd));
359 if (chip->badblockpos & 0x1)
361 if ((bad & 0xFF) != 0xff)
364 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos,
365 page & chip->pagemask);
366 if (chip->read_byte(mtd) != 0xff)
371 nand_release_device(mtd);
377 * nand_default_block_markbad - [DEFAULT] mark a block bad
378 * @mtd: MTD device structure
379 * @ofs: offset from device start
381 * This is the default implementation, which can be overridden by
382 * a hardware specific driver.
384 static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs)
386 struct nand_chip *chip = mtd->priv;
387 uint8_t buf[2] = { 0, 0 };
391 /* Get block number */
392 block = ((int)ofs) >> chip->bbt_erase_shift;
394 chip->bbt[block >> 2] |= 0x01 << ((block & 0x03) << 1);
396 /* Do we have a flash based bad block table ? */
397 if (chip->options & NAND_USE_FLASH_BBT)
398 return nand_update_bbt(mtd, ofs);
400 /* We write two bytes, so we dont have to mess with 16 bit access */
401 ofs += mtd->oobsize + (chip->badblockpos & ~0x01);
402 return nand_write_oob(mtd, ofs, 2, &retlen, buf);
406 * nand_check_wp - [GENERIC] check if the chip is write protected
407 * @mtd: MTD device structure
408 * Check, if the device is write protected
410 * The function expects, that the device is already selected
412 static int nand_check_wp(struct mtd_info *mtd)
414 struct nand_chip *chip = mtd->priv;
415 /* Check the WP bit */
416 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
417 return (chip->read_byte(mtd) & NAND_STATUS_WP) ? 0 : 1;
421 * nand_block_checkbad - [GENERIC] Check if a block is marked bad
422 * @mtd: MTD device structure
423 * @ofs: offset from device start
424 * @getchip: 0, if the chip is already selected
425 * @allowbbt: 1, if its allowed to access the bbt area
427 * Check, if the block is bad. Either by reading the bad block table or
428 * calling of the scan function.
430 static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int getchip,
433 struct nand_chip *chip = mtd->priv;
436 return chip->block_bad(mtd, ofs, getchip);
438 /* Return info from the table */
439 return nand_isbad_bbt(mtd, ofs, allowbbt);
443 * Wait for the ready pin, after a command
444 * The timeout is catched later.
446 static void nand_wait_ready(struct mtd_info *mtd)
448 struct nand_chip *chip = mtd->priv;
449 unsigned long timeo = jiffies + 2;
451 led_trigger_event(nand_led_trigger, LED_FULL);
452 /* wait until command is processed or timeout occures */
454 if (chip->dev_ready(mtd))
456 touch_softlockup_watchdog();
457 } while (time_before(jiffies, timeo));
458 led_trigger_event(nand_led_trigger, LED_OFF);
462 * nand_command - [DEFAULT] Send command to NAND device
463 * @mtd: MTD device structure
464 * @command: the command to be sent
465 * @column: the column address for this command, -1 if none
466 * @page_addr: the page address for this command, -1 if none
468 * Send command to NAND device. This function is used for small page
469 * devices (256/512 Bytes per page)
471 static void nand_command(struct mtd_info *mtd, unsigned int command,
472 int column, int page_addr)
474 register struct nand_chip *chip = mtd->priv;
475 int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE;
478 * Write out the command to the device.
480 if (command == NAND_CMD_SEQIN) {
483 if (column >= mtd->writesize) {
485 column -= mtd->writesize;
486 readcmd = NAND_CMD_READOOB;
487 } else if (column < 256) {
488 /* First 256 bytes --> READ0 */
489 readcmd = NAND_CMD_READ0;
492 readcmd = NAND_CMD_READ1;
494 chip->cmd_ctrl(mtd, readcmd, ctrl);
495 ctrl &= ~NAND_CTRL_CHANGE;
497 chip->cmd_ctrl(mtd, command, ctrl);
500 * Address cycle, when necessary
502 ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE;
503 /* Serially input address */
505 /* Adjust columns for 16 bit buswidth */
506 if (chip->options & NAND_BUSWIDTH_16)
508 chip->cmd_ctrl(mtd, column, ctrl);
509 ctrl &= ~NAND_CTRL_CHANGE;
511 if (page_addr != -1) {
512 chip->cmd_ctrl(mtd, page_addr, ctrl);
513 ctrl &= ~NAND_CTRL_CHANGE;
514 chip->cmd_ctrl(mtd, page_addr >> 8, ctrl);
515 /* One more address cycle for devices > 32MiB */
516 if (chip->chipsize > (32 << 20))
517 chip->cmd_ctrl(mtd, page_addr >> 16, ctrl);
519 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
522 * program and erase have their own busy handlers
523 * status and sequential in needs no delay
527 case NAND_CMD_PAGEPROG:
528 case NAND_CMD_ERASE1:
529 case NAND_CMD_ERASE2:
531 case NAND_CMD_STATUS:
532 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE);
538 udelay(chip->chip_delay);
539 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
540 NAND_CTRL_CLE | NAND_CTRL_CHANGE);
541 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE);
542 while (!(chip->read_byte(mtd) & NAND_STATUS_READY)) ;
545 /* This applies to read commands */
548 * If we don't have access to the busy pin, we apply the given
551 if (!chip->dev_ready) {
552 udelay(chip->chip_delay);
556 /* Apply this short delay always to ensure that we do wait tWB in
557 * any case on any machine. */
560 nand_wait_ready(mtd);
564 * nand_command_lp - [DEFAULT] Send command to NAND large page device
565 * @mtd: MTD device structure
566 * @command: the command to be sent
567 * @column: the column address for this command, -1 if none
568 * @page_addr: the page address for this command, -1 if none
570 * Send command to NAND device. This is the version for the new large page
571 * devices We dont have the separate regions as we have in the small page
572 * devices. We must emulate NAND_CMD_READOOB to keep the code compatible.
575 static void nand_command_lp(struct mtd_info *mtd, unsigned int command,
576 int column, int page_addr)
578 register struct nand_chip *chip = mtd->priv;
580 /* Emulate NAND_CMD_READOOB */
581 if (command == NAND_CMD_READOOB) {
582 column += mtd->writesize;
583 command = NAND_CMD_READ0;
586 /* Command latch cycle */
587 chip->cmd_ctrl(mtd, command & 0xff,
588 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
590 if (column != -1 || page_addr != -1) {
591 int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE;
593 /* Serially input address */
595 /* Adjust columns for 16 bit buswidth */
596 if (chip->options & NAND_BUSWIDTH_16)
598 chip->cmd_ctrl(mtd, column, ctrl);
599 ctrl &= ~NAND_CTRL_CHANGE;
600 chip->cmd_ctrl(mtd, column >> 8, ctrl);
602 if (page_addr != -1) {
603 chip->cmd_ctrl(mtd, page_addr, ctrl);
604 chip->cmd_ctrl(mtd, page_addr >> 8,
605 NAND_NCE | NAND_ALE);
606 /* One more address cycle for devices > 128MiB */
607 if (chip->chipsize > (128 << 20))
608 chip->cmd_ctrl(mtd, page_addr >> 16,
609 NAND_NCE | NAND_ALE);
612 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
615 * program and erase have their own busy handlers
616 * status, sequential in, and deplete1 need no delay
620 case NAND_CMD_CACHEDPROG:
621 case NAND_CMD_PAGEPROG:
622 case NAND_CMD_ERASE1:
623 case NAND_CMD_ERASE2:
625 case NAND_CMD_STATUS:
626 case NAND_CMD_DEPLETE1:
630 * read error status commands require only a short delay
632 case NAND_CMD_STATUS_ERROR:
633 case NAND_CMD_STATUS_ERROR0:
634 case NAND_CMD_STATUS_ERROR1:
635 case NAND_CMD_STATUS_ERROR2:
636 case NAND_CMD_STATUS_ERROR3:
637 udelay(chip->chip_delay);
643 udelay(chip->chip_delay);
644 chip->cmd_ctrl(mtd, NAND_CMD_STATUS, NAND_NCE | NAND_CLE);
645 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE);
646 while (!(chip->read_byte(mtd) & NAND_STATUS_READY)) ;
650 chip->cmd_ctrl(mtd, NAND_CMD_READSTART, NAND_NCE | NAND_CLE);
651 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE);
653 /* This applies to read commands */
656 * If we don't have access to the busy pin, we apply the given
659 if (!chip->dev_ready) {
660 udelay(chip->chip_delay);
665 /* Apply this short delay always to ensure that we do wait tWB in
666 * any case on any machine. */
669 nand_wait_ready(mtd);
673 * nand_get_device - [GENERIC] Get chip for selected access
674 * @this: the nand chip descriptor
675 * @mtd: MTD device structure
676 * @new_state: the state which is requested
678 * Get the device and lock it for exclusive access
681 nand_get_device(struct nand_chip *chip, struct mtd_info *mtd, int new_state)
683 spinlock_t *lock = &chip->controller->lock;
684 wait_queue_head_t *wq = &chip->controller->wq;
685 DECLARE_WAITQUEUE(wait, current);
689 /* Hardware controller shared among independend devices */
690 /* Hardware controller shared among independend devices */
691 if (!chip->controller->active)
692 chip->controller->active = chip;
694 if (chip->controller->active == chip && chip->state == FL_READY) {
695 chip->state = new_state;
699 if (new_state == FL_PM_SUSPENDED) {
701 return (chip->state == FL_PM_SUSPENDED) ? 0 : -EAGAIN;
703 set_current_state(TASK_UNINTERRUPTIBLE);
704 add_wait_queue(wq, &wait);
707 remove_wait_queue(wq, &wait);
712 * nand_wait - [DEFAULT] wait until the command is done
713 * @mtd: MTD device structure
714 * @this: NAND chip structure
715 * @state: state to select the max. timeout value
717 * Wait for command done. This applies to erase and program only
718 * Erase can take up to 400ms and program up to 20ms according to
719 * general NAND and SmartMedia specs
722 static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip, int state)
725 unsigned long timeo = jiffies;
728 if (state == FL_ERASING)
729 timeo += (HZ * 400) / 1000;
731 timeo += (HZ * 20) / 1000;
733 led_trigger_event(nand_led_trigger, LED_FULL);
735 /* Apply this short delay always to ensure that we do wait tWB in
736 * any case on any machine. */
739 if ((state == FL_ERASING) && (chip->options & NAND_IS_AND))
740 chip->cmdfunc(mtd, NAND_CMD_STATUS_MULTI, -1, -1);
742 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
744 while (time_before(jiffies, timeo)) {
745 /* Check, if we were interrupted */
746 if (chip->state != state)
749 if (chip->dev_ready) {
750 if (chip->dev_ready(mtd))
753 if (chip->read_byte(mtd) & NAND_STATUS_READY)
758 led_trigger_event(nand_led_trigger, LED_OFF);
760 status = (int)chip->read_byte(mtd);
765 * nand_write_page - [GENERIC] write one page
766 * @mtd: MTD device structure
767 * @this: NAND chip structure
768 * @page: startpage inside the chip, must be called with (page & chip->pagemask)
769 * @oob_buf: out of band data buffer
770 * @oobsel: out of band selecttion structre
771 * @cached: 1 = enable cached programming if supported by chip
773 * Nand_page_program function is used for write and writev !
774 * This function will always program a full page of data
775 * If you call it with a non page aligned buffer, you're lost :)
777 * Cached programming is not supported yet.
779 static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip, int page,
780 uint8_t *oob_buf, struct nand_oobinfo *oobsel, int cached)
783 uint8_t ecc_code[32];
784 int eccmode = oobsel->useecc ? chip->ecc.mode : NAND_ECC_NONE;
785 int *oob_config = oobsel->eccpos;
786 int datidx = 0, eccidx = 0, eccsteps = chip->ecc.steps;
789 /* FIXME: Enable cached programming */
792 /* Send command to begin auto page programming */
793 chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
795 /* Write out complete page of data, take care of eccmode */
797 /* No ecc, write all */
799 printk(KERN_WARNING "Writing data without ECC to NAND-FLASH is not recommended\n");
800 chip->write_buf(mtd, chip->data_poi, mtd->writesize);
803 /* Software ecc 3/256, write all */
805 for (; eccsteps; eccsteps--) {
806 chip->ecc.calculate(mtd, &chip->data_poi[datidx], ecc_code);
807 for (i = 0; i < 3; i++, eccidx++)
808 oob_buf[oob_config[eccidx]] = ecc_code[i];
809 datidx += chip->ecc.size;
811 chip->write_buf(mtd, chip->data_poi, mtd->writesize);
814 eccbytes = chip->ecc.bytes;
815 for (; eccsteps; eccsteps--) {
816 /* enable hardware ecc logic for write */
817 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
818 chip->write_buf(mtd, &chip->data_poi[datidx], chip->ecc.size);
819 chip->ecc.calculate(mtd, &chip->data_poi[datidx], ecc_code);
820 for (i = 0; i < eccbytes; i++, eccidx++)
821 oob_buf[oob_config[eccidx]] = ecc_code[i];
822 /* If the hardware ecc provides syndromes then
823 * the ecc code must be written immidiately after
824 * the data bytes (words) */
825 if (chip->options & NAND_HWECC_SYNDROME)
826 chip->write_buf(mtd, ecc_code, eccbytes);
827 datidx += chip->ecc.size;
832 /* Write out OOB data */
833 if (chip->options & NAND_HWECC_SYNDROME)
834 chip->write_buf(mtd, &oob_buf[oobsel->eccbytes], mtd->oobsize - oobsel->eccbytes);
836 chip->write_buf(mtd, oob_buf, mtd->oobsize);
838 /* Send command to actually program the data */
839 chip->cmdfunc(mtd, cached ? NAND_CMD_CACHEDPROG : NAND_CMD_PAGEPROG, -1, -1);
842 /* call wait ready function */
843 status = chip->waitfunc(mtd, chip, FL_WRITING);
845 /* See if operation failed and additional status checks are available */
846 if ((status & NAND_STATUS_FAIL) && (chip->errstat)) {
847 status = chip->errstat(mtd, chip, FL_WRITING, status, page);
850 /* See if device thinks it succeeded */
851 if (status & NAND_STATUS_FAIL) {
852 DEBUG(MTD_DEBUG_LEVEL0, "%s: " "Failed write, page 0x%08x, ", __FUNCTION__, page);
856 /* FIXME: Implement cached programming ! */
857 /* wait until cache is ready */
858 // status = chip->waitfunc (mtd, this, FL_CACHEDRPG);
863 #ifdef CONFIG_MTD_NAND_VERIFY_WRITE
865 * nand_verify_pages - [GENERIC] verify the chip contents after a write
866 * @mtd: MTD device structure
867 * @this: NAND chip structure
868 * @page: startpage inside the chip, must be called with (page & chip->pagemask)
869 * @numpages: number of pages to verify
870 * @oob_buf: out of band data buffer
871 * @oobsel: out of band selecttion structre
872 * @chipnr: number of the current chip
873 * @oobmode: 1 = full buffer verify, 0 = ecc only
875 * The NAND device assumes that it is always writing to a cleanly erased page.
876 * Hence, it performs its internal write verification only on bits that
877 * transitioned from 1 to 0. The device does NOT verify the whole page on a
878 * byte by byte basis. It is possible that the page was not completely erased
879 * or the page is becoming unusable due to wear. The read with ECC would catch
880 * the error later when the ECC page check fails, but we would rather catch
881 * it early in the page write stage. Better to write no data than invalid data.
883 static int nand_verify_pages(struct mtd_info *mtd, struct nand_chip *chip, int page, int numpages,
884 uint8_t *oob_buf, struct nand_oobinfo *oobsel, int chipnr, int oobmode)
886 int i, j, datidx = 0, oobofs = 0, res = -EIO;
887 int eccsteps = chip->eccsteps;
891 hweccbytes = (chip->options & NAND_HWECC_SYNDROME) ? (oobsel->eccbytes / eccsteps) : 0;
893 /* Send command to read back the first page */
894 chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
897 for (j = 0; j < eccsteps; j++) {
898 /* Loop through and verify the data */
899 if (chip->verify_buf(mtd, &chip->data_poi[datidx], mtd->eccsize)) {
900 DEBUG(MTD_DEBUG_LEVEL0, "%s: " "Failed write verify, page 0x%08x ", __FUNCTION__, page);
903 datidx += mtd->eccsize;
904 /* Have we a hw generator layout ? */
907 if (chip->verify_buf(mtd, &chip->oob_buf[oobofs], hweccbytes)) {
908 DEBUG(MTD_DEBUG_LEVEL0, "%s: " "Failed write verify, page 0x%08x ", __FUNCTION__, page);
911 oobofs += hweccbytes;
914 /* check, if we must compare all data or if we just have to
915 * compare the ecc bytes
918 if (chip->verify_buf(mtd, &oob_buf[oobofs], mtd->oobsize - hweccbytes * eccsteps)) {
919 DEBUG(MTD_DEBUG_LEVEL0, "%s: " "Failed write verify, page 0x%08x ", __FUNCTION__, page);
923 /* Read always, else autoincrement fails */
924 chip->read_buf(mtd, oobdata, mtd->oobsize - hweccbytes * eccsteps);
926 if (oobsel->useecc != MTD_NANDECC_OFF && !hweccbytes) {
927 int ecccnt = oobsel->eccbytes;
929 for (i = 0; i < ecccnt; i++) {
930 int idx = oobsel->eccpos[i];
931 if (oobdata[idx] != oob_buf[oobofs + idx]) {
932 DEBUG(MTD_DEBUG_LEVEL0, "%s: Failed ECC write verify, page 0x%08x, %6i bytes were succesful\n",
933 __FUNCTION__, page, i);
939 oobofs += mtd->oobsize - hweccbytes * eccsteps;
943 /* Apply delay or wait for ready/busy pin
944 * Do this before the AUTOINCR check, so no problems
945 * arise if a chip which does auto increment
946 * is marked as NOAUTOINCR by the board driver.
947 * Do this also before returning, so the chip is
948 * ready for the next command.
950 if (!chip->dev_ready)
951 udelay(chip->chip_delay);
953 nand_wait_ready(mtd);
955 /* All done, return happy */
959 /* Check, if the chip supports auto page increment */
960 if (!NAND_CANAUTOINCR(this))
961 chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
964 * Terminate the read command. We come here in case of an error
965 * So we must issue a reset command.
968 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
974 * nand_read - [MTD Interface] MTD compability function for nand_do_read_ecc
975 * @mtd: MTD device structure
976 * @from: offset to read from
977 * @len: number of bytes to read
978 * @retlen: pointer to variable to store the number of read bytes
979 * @buf: the databuffer to put data
981 * This function simply calls nand_do_read_ecc with oob buffer and oobsel = NULL
984 static int nand_read(struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, uint8_t *buf)
986 return nand_do_read_ecc(mtd, from, len, retlen, buf, NULL, &mtd->oobinfo, 0xff);
990 * nand_do_read_ecc - [MTD Interface] Read data with ECC
991 * @mtd: MTD device structure
992 * @from: offset to read from
993 * @len: number of bytes to read
994 * @retlen: pointer to variable to store the number of read bytes
995 * @buf: the databuffer to put data
996 * @oob_buf: filesystem supplied oob data buffer (can be NULL)
997 * @oobsel: oob selection structure
998 * @flags: flag to indicate if nand_get_device/nand_release_device should be preformed
999 * and how many corrected error bits are acceptable:
1000 * bits 0..7 - number of tolerable errors
1001 * bit 8 - 0 == do not get/release chip, 1 == get/release chip
1003 * NAND read with ECC
1005 int nand_do_read_ecc(struct mtd_info *mtd, loff_t from, size_t len,
1006 size_t *retlen, uint8_t *buf, uint8_t *oob_buf, struct nand_oobinfo *oobsel, int flags)
1009 int i, j, col, realpage, page, end, ecc, chipnr, sndcmd = 1;
1010 int read = 0, oob = 0, ecc_status = 0, ecc_failed = 0;
1011 struct nand_chip *chip = mtd->priv;
1012 uint8_t *data_poi, *oob_data = oob_buf;
1013 uint8_t ecc_calc[32];
1014 uint8_t ecc_code[32];
1015 int eccmode, eccsteps;
1016 int *oob_config, datidx;
1017 int blockcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
1022 DEBUG(MTD_DEBUG_LEVEL3, "nand_read_ecc: from = 0x%08x, len = %i\n", (unsigned int)from, (int)len);
1024 /* Do not allow reads past end of device */
1025 if ((from + len) > mtd->size) {
1026 DEBUG(MTD_DEBUG_LEVEL0, "nand_read_ecc: Attempt read beyond end of device\n");
1031 /* Grab the lock and see if the device is available */
1032 if (flags & NAND_GET_DEVICE)
1033 nand_get_device(chip, mtd, FL_READING);
1035 /* Autoplace of oob data ? Use the default placement scheme */
1036 if (oobsel->useecc == MTD_NANDECC_AUTOPLACE)
1037 oobsel = chip->autooob;
1039 eccmode = oobsel->useecc ? chip->ecc.mode : NAND_ECC_NONE;
1040 oob_config = oobsel->eccpos;
1042 /* Select the NAND device */
1043 chipnr = (int)(from >> chip->chip_shift);
1044 chip->select_chip(mtd, chipnr);
1046 /* First we calculate the starting page */
1047 realpage = (int)(from >> chip->page_shift);
1048 page = realpage & chip->pagemask;
1050 /* Get raw starting column */
1051 col = from & (mtd->writesize - 1);
1053 end = mtd->writesize;
1054 ecc = chip->ecc.size;
1055 eccbytes = chip->ecc.bytes;
1057 if ((eccmode == NAND_ECC_NONE) || (chip->options & NAND_HWECC_SYNDROME))
1060 oobreadlen = mtd->oobsize;
1061 if (chip->options & NAND_HWECC_SYNDROME)
1062 oobreadlen -= oobsel->eccbytes;
1064 /* Loop until all data read */
1065 while (read < len) {
1067 int aligned = (!col && (len - read) >= end);
1069 * If the read is not page aligned, we have to read into data buffer
1070 * due to ecc, else we read into return buffer direct
1073 data_poi = &buf[read];
1075 data_poi = chip->data_buf;
1077 /* Check, if we have this page in the buffer
1079 * FIXME: Make it work when we must provide oob data too,
1080 * check the usage of data_buf oob field
1082 if (realpage == chip->pagebuf && !oob_buf) {
1083 /* aligned read ? */
1085 memcpy(data_poi, chip->data_buf, end);
1089 /* Check, if we must send the read command */
1091 chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
1095 /* get oob area, if we have no oob buffer from fs-driver */
1096 if (!oob_buf || oobsel->useecc == MTD_NANDECC_AUTOPLACE ||
1097 oobsel->useecc == MTD_NANDECC_AUTOPL_USR)
1098 oob_data = &chip->data_buf[end];
1100 eccsteps = chip->ecc.steps;
1103 case NAND_ECC_NONE:{
1104 /* No ECC, Read in a page */
1105 static unsigned long lastwhinge = 0;
1106 if ((lastwhinge / HZ) != (jiffies / HZ)) {
1108 "Reading data from NAND FLASH without ECC is not recommended\n");
1109 lastwhinge = jiffies;
1111 chip->read_buf(mtd, data_poi, end);
1115 case NAND_ECC_SOFT: /* Software ECC 3/256: Read in a page + oob data */
1116 chip->read_buf(mtd, data_poi, end);
1117 for (i = 0, datidx = 0; eccsteps; eccsteps--, i += 3, datidx += ecc)
1118 chip->ecc.calculate(mtd, &data_poi[datidx], &ecc_calc[i]);
1122 for (i = 0, datidx = 0; eccsteps; eccsteps--, i += eccbytes, datidx += ecc) {
1123 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1124 chip->read_buf(mtd, &data_poi[datidx], ecc);
1126 /* HW ecc with syndrome calculation must read the
1127 * syndrome from flash immidiately after the data */
1129 /* Some hw ecc generators need to know when the
1130 * syndrome is read from flash */
1131 chip->ecc.hwctl(mtd, NAND_ECC_READSYN);
1132 chip->read_buf(mtd, &oob_data[i], eccbytes);
1133 /* We calc error correction directly, it checks the hw
1134 * generator for an error, reads back the syndrome and
1135 * does the error correction on the fly */
1136 ecc_status = chip->ecc.correct(mtd, &data_poi[datidx], &oob_data[i], &ecc_code[i]);
1137 if ((ecc_status == -1) || (ecc_status > (flags && 0xff))) {
1138 DEBUG(MTD_DEBUG_LEVEL0, "nand_read_ecc: "
1139 "Failed ECC read, page 0x%08x on chip %d\n", page, chipnr);
1143 chip->ecc.calculate(mtd, &data_poi[datidx], &ecc_calc[i]);
1150 chip->read_buf(mtd, &oob_data[mtd->oobsize - oobreadlen], oobreadlen);
1152 /* Skip ECC check, if not requested (ECC_NONE or HW_ECC with syndromes) */
1156 /* Pick the ECC bytes out of the oob data */
1157 for (j = 0; j < oobsel->eccbytes; j++)
1158 ecc_code[j] = oob_data[oob_config[j]];
1160 /* correct data, if necessary */
1161 for (i = 0, j = 0, datidx = 0; i < chip->ecc.steps; i++, datidx += ecc) {
1162 ecc_status = chip->ecc.correct(mtd, &data_poi[datidx], &ecc_code[j], &ecc_calc[j]);
1164 /* Get next chunk of ecc bytes */
1167 /* Check, if we have a fs supplied oob-buffer,
1168 * This is the legacy mode. Used by YAFFS1
1169 * Should go away some day
1171 if (oob_buf && oobsel->useecc == MTD_NANDECC_PLACE) {
1172 int *p = (int *)(&oob_data[mtd->oobsize]);
1176 if ((ecc_status == -1) || (ecc_status > (flags && 0xff))) {
1177 DEBUG(MTD_DEBUG_LEVEL0, "nand_read_ecc: " "Failed ECC read, page 0x%08x\n", page);
1183 /* check, if we have a fs supplied oob-buffer */
1185 /* without autoplace. Legacy mode used by YAFFS1 */
1186 switch (oobsel->useecc) {
1187 case MTD_NANDECC_AUTOPLACE:
1188 case MTD_NANDECC_AUTOPL_USR:
1189 /* Walk through the autoplace chunks */
1190 for (i = 0; oobsel->oobfree[i][1]; i++) {
1191 int from = oobsel->oobfree[i][0];
1192 int num = oobsel->oobfree[i][1];
1193 memcpy(&oob_buf[oob], &oob_data[from], num);
1197 case MTD_NANDECC_PLACE:
1198 /* YAFFS1 legacy mode */
1199 oob_data += chip->ecc.steps * sizeof(int);
1201 oob_data += mtd->oobsize;
1205 /* Partial page read, transfer data into fs buffer */
1207 for (j = col; j < end && read < len; j++)
1208 buf[read++] = data_poi[j];
1209 chip->pagebuf = realpage;
1211 read += mtd->writesize;
1213 /* Apply delay or wait for ready/busy pin
1214 * Do this before the AUTOINCR check, so no problems
1215 * arise if a chip which does auto increment
1216 * is marked as NOAUTOINCR by the board driver.
1218 if (!chip->dev_ready)
1219 udelay(chip->chip_delay);
1221 nand_wait_ready(mtd);
1226 /* For subsequent reads align to page boundary. */
1228 /* Increment page address */
1231 page = realpage & chip->pagemask;
1232 /* Check, if we cross a chip boundary */
1235 chip->select_chip(mtd, -1);
1236 chip->select_chip(mtd, chipnr);
1238 /* Check, if the chip supports auto page increment
1239 * or if we have hit a block boundary.
1241 if (!NAND_CANAUTOINCR(chip) || !(page & blockcheck))
1245 /* Deselect and wake up anyone waiting on the device */
1246 if (flags & NAND_GET_DEVICE)
1247 nand_release_device(mtd);
1250 * Return success, if no ECC failures, else -EBADMSG
1251 * fs driver will take care of that, because
1252 * retlen == desired len and result == -EBADMSG
1255 return ecc_failed ? -EBADMSG : 0;
1259 * nand_read_oob - [MTD Interface] NAND read out-of-band
1260 * @mtd: MTD device structure
1261 * @from: offset to read from
1262 * @len: number of bytes to read
1263 * @retlen: pointer to variable to store the number of read bytes
1264 * @buf: the databuffer to put data
1266 * NAND read out-of-band data from the spare area
1268 static int nand_read_oob(struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, uint8_t *buf)
1270 int i, col, page, chipnr;
1271 struct nand_chip *chip = mtd->priv;
1272 int blockcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
1274 DEBUG(MTD_DEBUG_LEVEL3, "nand_read_oob: from = 0x%08x, len = %i\n", (unsigned int)from, (int)len);
1276 /* Shift to get page */
1277 page = (int)(from >> chip->page_shift);
1278 chipnr = (int)(from >> chip->chip_shift);
1280 /* Mask to get column */
1281 col = from & (mtd->oobsize - 1);
1283 /* Initialize return length value */
1286 /* Do not allow reads past end of device */
1287 if ((from + len) > mtd->size) {
1288 DEBUG(MTD_DEBUG_LEVEL0, "nand_read_oob: Attempt read beyond end of device\n");
1293 /* Grab the lock and see if the device is available */
1294 nand_get_device(chip, mtd, FL_READING);
1296 /* Select the NAND device */
1297 chip->select_chip(mtd, chipnr);
1299 /* Send the read command */
1300 chip->cmdfunc(mtd, NAND_CMD_READOOB, col, page & chip->pagemask);
1302 * Read the data, if we read more than one page
1303 * oob data, let the device transfer the data !
1307 int thislen = mtd->oobsize - col;
1308 thislen = min_t(int, thislen, len);
1309 chip->read_buf(mtd, &buf[i], thislen);
1317 /* Check, if we cross a chip boundary */
1318 if (!(page & chip->pagemask)) {
1320 chip->select_chip(mtd, -1);
1321 chip->select_chip(mtd, chipnr);
1324 /* Apply delay or wait for ready/busy pin
1325 * Do this before the AUTOINCR check, so no problems
1326 * arise if a chip which does auto increment
1327 * is marked as NOAUTOINCR by the board driver.
1329 if (!chip->dev_ready)
1330 udelay(chip->chip_delay);
1332 nand_wait_ready(mtd);
1334 /* Check, if the chip supports auto page increment
1335 * or if we have hit a block boundary.
1337 if (!NAND_CANAUTOINCR(chip) || !(page & blockcheck)) {
1338 /* For subsequent page reads set offset to 0 */
1339 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0x0, page & chip->pagemask);
1344 /* Deselect and wake up anyone waiting on the device */
1345 nand_release_device(mtd);
1353 * nand_read_raw - [GENERIC] Read raw data including oob into buffer
1354 * @mtd: MTD device structure
1355 * @buf: temporary buffer
1356 * @from: offset to read from
1357 * @len: number of bytes to read
1358 * @ooblen: number of oob data bytes to read
1360 * Read raw data including oob into buffer
1362 int nand_read_raw(struct mtd_info *mtd, uint8_t *buf, loff_t from, size_t len,
1365 struct nand_chip *chip = mtd->priv;
1366 int page = (int)(from >> chip->page_shift);
1367 int chipnr = (int)(from >> chip->chip_shift);
1370 int pagesize = mtd->writesize + mtd->oobsize;
1373 /* Do not allow reads past end of device */
1374 if ((from + len) > mtd->size) {
1375 DEBUG(MTD_DEBUG_LEVEL0, "nand_read_raw: "
1376 "Attempt read beyond end of device\n");
1380 /* Grab the lock and see if the device is available */
1381 nand_get_device(chip, mtd, FL_READING);
1383 chip->select_chip(mtd, chipnr);
1385 /* Add requested oob length */
1387 blockcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
1391 chip->cmdfunc(mtd, NAND_CMD_READ0, 0,
1392 page & chip->pagemask);
1395 chip->read_buf(mtd, &buf[cnt], pagesize);
1401 if (!chip->dev_ready)
1402 udelay(chip->chip_delay);
1404 nand_wait_ready(mtd);
1407 * Check, if the chip supports auto page increment or if we
1408 * cross a block boundary.
1410 if (!NAND_CANAUTOINCR(chip) || !(page & blockcheck))
1414 /* Deselect and wake up anyone waiting on the device */
1415 nand_release_device(mtd);
1420 * nand_write_raw - [GENERIC] Write raw data including oob
1421 * @mtd: MTD device structure
1422 * @buf: source buffer
1423 * @to: offset to write to
1424 * @len: number of bytes to write
1425 * @buf: source buffer
1428 * Write raw data including oob
1430 int nand_write_raw(struct mtd_info *mtd, loff_t to, size_t len, size_t *retlen,
1431 uint8_t *buf, uint8_t *oob)
1433 struct nand_chip *chip = mtd->priv;
1434 int page = (int)(to >> chip->page_shift);
1435 int chipnr = (int)(to >> chip->chip_shift);
1440 /* Do not allow writes past end of device */
1441 if ((to + len) > mtd->size) {
1442 DEBUG(MTD_DEBUG_LEVEL0, "nand_read_raw: Attempt write "
1443 "beyond end of device\n");
1447 /* Grab the lock and see if the device is available */
1448 nand_get_device(chip, mtd, FL_WRITING);
1450 chip->select_chip(mtd, chipnr);
1451 chip->data_poi = buf;
1453 while (len != *retlen) {
1454 ret = nand_write_page(mtd, chip, page, oob, &mtd->oobinfo, 0);
1458 *retlen += mtd->writesize;
1459 chip->data_poi += mtd->writesize;
1460 oob += mtd->oobsize;
1463 /* Deselect and wake up anyone waiting on the device */
1464 nand_release_device(mtd);
1467 EXPORT_SYMBOL_GPL(nand_write_raw);
1470 * nand_prepare_oobbuf - [GENERIC] Prepare the out of band buffer
1471 * @mtd: MTD device structure
1472 * @fsbuf: buffer given by fs driver
1473 * @oobsel: out of band selection structre
1474 * @autoplace: 1 = place given buffer into the oob bytes
1475 * @numpages: number of pages to prepare
1478 * 1. Filesystem buffer available and autoplacement is off,
1479 * return filesystem buffer
1480 * 2. No filesystem buffer or autoplace is off, return internal
1482 * 3. Filesystem buffer is given and autoplace selected
1483 * put data from fs buffer into internal buffer and
1484 * retrun internal buffer
1486 * Note: The internal buffer is filled with 0xff. This must
1487 * be done only once, when no autoplacement happens
1488 * Autoplacement sets the buffer dirty flag, which
1489 * forces the 0xff fill before using the buffer again.
1492 static uint8_t *nand_prepare_oobbuf(struct mtd_info *mtd, uint8_t *fsbuf, struct nand_oobinfo *oobsel,
1493 int autoplace, int numpages)
1495 struct nand_chip *chip = mtd->priv;
1498 /* Zero copy fs supplied buffer */
1499 if (fsbuf && !autoplace)
1502 /* Check, if the buffer must be filled with ff again */
1503 if (chip->oobdirty) {
1504 memset(chip->oob_buf, 0xff, mtd->oobsize << (chip->phys_erase_shift - chip->page_shift));
1508 /* If we have no autoplacement or no fs buffer use the internal one */
1509 if (!autoplace || !fsbuf)
1510 return chip->oob_buf;
1512 /* Walk through the pages and place the data */
1515 while (numpages--) {
1516 for (i = 0, len = 0; len < mtd->oobavail; i++) {
1517 int to = ofs + oobsel->oobfree[i][0];
1518 int num = oobsel->oobfree[i][1];
1519 memcpy(&chip->oob_buf[to], fsbuf, num);
1523 ofs += mtd->oobavail;
1525 return chip->oob_buf;
1528 #define NOTALIGNED(x) (x & (mtd->writesize-1)) != 0
1531 * nand_write - [MTD Interface] NAND write with ECC
1532 * @mtd: MTD device structure
1533 * @to: offset to write to
1534 * @len: number of bytes to write
1535 * @retlen: pointer to variable to store the number of written bytes
1536 * @buf: the data to write
1538 * NAND write with ECC
1540 static int nand_write(struct mtd_info *mtd, loff_t to, size_t len,
1541 size_t *retlen, const uint8_t *buf)
1543 int startpage, page, ret = -EIO, oob = 0, written = 0, chipnr;
1544 int autoplace = 0, numpages, totalpages;
1545 struct nand_chip *chip = mtd->priv;
1546 uint8_t *oobbuf, *bufstart, *eccbuf = NULL;
1547 int ppblock = (1 << (chip->phys_erase_shift - chip->page_shift));
1548 struct nand_oobinfo *oobsel = &mtd->oobinfo;
1550 DEBUG(MTD_DEBUG_LEVEL3, "nand_write: to = 0x%08x, len = %i\n", (unsigned int)to, (int)len);
1552 /* Initialize retlen, in case of early exit */
1555 /* Do not allow write past end of device */
1556 if ((to + len) > mtd->size) {
1557 DEBUG(MTD_DEBUG_LEVEL0, "nand_write: Attempt to write past end of page\n");
1561 /* reject writes, which are not page aligned */
1562 if (NOTALIGNED(to) || NOTALIGNED(len)) {
1563 printk(KERN_NOTICE "nand_write: Attempt to write not page aligned data\n");
1567 /* Grab the lock and see if the device is available */
1568 nand_get_device(chip, mtd, FL_WRITING);
1570 /* Calculate chipnr */
1571 chipnr = (int)(to >> chip->chip_shift);
1572 /* Select the NAND device */
1573 chip->select_chip(mtd, chipnr);
1575 /* Check, if it is write protected */
1576 if (nand_check_wp(mtd))
1579 /* Autoplace of oob data ? Use the default placement scheme */
1580 if (oobsel->useecc == MTD_NANDECC_AUTOPLACE) {
1581 oobsel = chip->autooob;
1584 if (oobsel->useecc == MTD_NANDECC_AUTOPL_USR)
1587 /* Setup variables and oob buffer */
1588 totalpages = len >> chip->page_shift;
1589 page = (int)(to >> chip->page_shift);
1590 /* Invalidate the page cache, if we write to the cached page */
1591 if (page <= chip->pagebuf && chip->pagebuf < (page + totalpages))
1594 /* Set it relative to chip */
1595 page &= chip->pagemask;
1597 /* Calc number of pages we can write in one go */
1598 numpages = min(ppblock - (startpage & (ppblock - 1)), totalpages);
1599 oobbuf = nand_prepare_oobbuf(mtd, eccbuf, oobsel, autoplace, numpages);
1600 bufstart = (uint8_t *) buf;
1602 /* Loop until all data is written */
1603 while (written < len) {
1605 chip->data_poi = (uint8_t *) &buf[written];
1606 /* Write one page. If this is the last page to write
1607 * or the last page in this block, then use the
1608 * real pageprogram command, else select cached programming
1609 * if supported by the chip.
1611 ret = nand_write_page(mtd, chip, page, &oobbuf[oob], oobsel, (--numpages > 0));
1613 DEBUG(MTD_DEBUG_LEVEL0, "nand_write: write_page failed %d\n", ret);
1617 oob += mtd->oobsize;
1618 /* Update written bytes count */
1619 written += mtd->writesize;
1623 /* Increment page address */
1626 /* Have we hit a block boundary ? Then we have to verify and
1627 * if verify is ok, we have to setup the oob buffer for
1630 if (!(page & (ppblock - 1))) {
1632 chip->data_poi = bufstart;
1633 ret = nand_verify_pages(mtd, this, startpage, page - startpage,
1634 oobbuf, oobsel, chipnr, (eccbuf != NULL));
1636 DEBUG(MTD_DEBUG_LEVEL0, "nand_write: verify_pages failed %d\n", ret);
1641 ofs = autoplace ? mtd->oobavail : mtd->oobsize;
1643 eccbuf += (page - startpage) * ofs;
1644 totalpages -= page - startpage;
1645 numpages = min(totalpages, ppblock);
1646 page &= chip->pagemask;
1648 oobbuf = nand_prepare_oobbuf(mtd, eccbuf, oobsel, autoplace, numpages);
1650 /* Check, if we cross a chip boundary */
1653 chip->select_chip(mtd, -1);
1654 chip->select_chip(mtd, chipnr);
1658 /* Verify the remaining pages */
1660 chip->data_poi = bufstart;
1661 ret = nand_verify_pages(mtd, this, startpage, totalpages, oobbuf, oobsel, chipnr, (eccbuf != NULL));
1665 DEBUG(MTD_DEBUG_LEVEL0, "nand_write: verify_pages failed %d\n", ret);
1668 /* Deselect and wake up anyone waiting on the device */
1669 nand_release_device(mtd);
1675 * nand_write_oob - [MTD Interface] NAND write out-of-band
1676 * @mtd: MTD device structure
1677 * @to: offset to write to
1678 * @len: number of bytes to write
1679 * @retlen: pointer to variable to store the number of written bytes
1680 * @buf: the data to write
1682 * NAND write out-of-band
1684 static int nand_write_oob(struct mtd_info *mtd, loff_t to, size_t len, size_t *retlen, const uint8_t *buf)
1686 int column, page, status, ret = -EIO, chipnr;
1687 struct nand_chip *chip = mtd->priv;
1689 DEBUG(MTD_DEBUG_LEVEL3, "nand_write_oob: to = 0x%08x, len = %i\n", (unsigned int)to, (int)len);
1691 /* Shift to get page */
1692 page = (int)(to >> chip->page_shift);
1693 chipnr = (int)(to >> chip->chip_shift);
1695 /* Mask to get column */
1696 column = to & (mtd->oobsize - 1);
1698 /* Initialize return length value */
1701 /* Do not allow write past end of page */
1702 if ((column + len) > mtd->oobsize) {
1703 DEBUG(MTD_DEBUG_LEVEL0, "nand_write_oob: Attempt to write past end of page\n");
1707 /* Grab the lock and see if the device is available */
1708 nand_get_device(chip, mtd, FL_WRITING);
1710 /* Select the NAND device */
1711 chip->select_chip(mtd, chipnr);
1713 /* Reset the chip. Some chips (like the Toshiba TC5832DC found
1714 in one of my DiskOnChip 2000 test units) will clear the whole
1715 data page too if we don't do this. I have no clue why, but
1716 I seem to have 'fixed' it in the doc2000 driver in
1717 August 1999. dwmw2. */
1718 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
1720 /* Check, if it is write protected */
1721 if (nand_check_wp(mtd))
1724 /* Invalidate the page cache, if we write to the cached page */
1725 if (page == chip->pagebuf)
1728 if (NAND_MUST_PAD(chip)) {
1729 /* Write out desired data */
1730 chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page & chip->pagemask);
1731 /* prepad 0xff for partial programming */
1732 chip->write_buf(mtd, ffchars, column);
1734 chip->write_buf(mtd, buf, len);
1735 /* postpad 0xff for partial programming */
1736 chip->write_buf(mtd, ffchars, mtd->oobsize - (len + column));
1738 /* Write out desired data */
1739 chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize + column, page & chip->pagemask);
1741 chip->write_buf(mtd, buf, len);
1743 /* Send command to program the OOB data */
1744 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1746 status = chip->waitfunc(mtd, chip, FL_WRITING);
1748 /* See if device thinks it succeeded */
1749 if (status & NAND_STATUS_FAIL) {
1750 DEBUG(MTD_DEBUG_LEVEL0, "nand_write_oob: " "Failed write, page 0x%08x\n", page);
1757 #ifdef CONFIG_MTD_NAND_VERIFY_WRITE
1758 /* Send command to read back the data */
1759 chip->cmdfunc(mtd, NAND_CMD_READOOB, column, page & chip->pagemask);
1761 if (chip->verify_buf(mtd, buf, len)) {
1762 DEBUG(MTD_DEBUG_LEVEL0, "nand_write_oob: " "Failed write verify, page 0x%08x\n", page);
1769 /* Deselect and wake up anyone waiting on the device */
1770 nand_release_device(mtd);
1776 * single_erease_cmd - [GENERIC] NAND standard block erase command function
1777 * @mtd: MTD device structure
1778 * @page: the page address of the block which will be erased
1780 * Standard erase command for NAND chips
1782 static void single_erase_cmd(struct mtd_info *mtd, int page)
1784 struct nand_chip *chip = mtd->priv;
1785 /* Send commands to erase a block */
1786 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
1787 chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
1791 * multi_erease_cmd - [GENERIC] AND specific block erase command function
1792 * @mtd: MTD device structure
1793 * @page: the page address of the block which will be erased
1795 * AND multi block erase command function
1796 * Erase 4 consecutive blocks
1798 static void multi_erase_cmd(struct mtd_info *mtd, int page)
1800 struct nand_chip *chip = mtd->priv;
1801 /* Send commands to erase a block */
1802 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
1803 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
1804 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
1805 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
1806 chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
1810 * nand_erase - [MTD Interface] erase block(s)
1811 * @mtd: MTD device structure
1812 * @instr: erase instruction
1814 * Erase one ore more blocks
1816 static int nand_erase(struct mtd_info *mtd, struct erase_info *instr)
1818 return nand_erase_nand(mtd, instr, 0);
1821 #define BBT_PAGE_MASK 0xffffff3f
1823 * nand_erase_nand - [Internal] erase block(s)
1824 * @mtd: MTD device structure
1825 * @instr: erase instruction
1826 * @allowbbt: allow erasing the bbt area
1828 * Erase one ore more blocks
1830 int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
1833 int page, len, status, pages_per_block, ret, chipnr;
1834 struct nand_chip *chip = mtd->priv;
1835 int rewrite_bbt[NAND_MAX_CHIPS]={0};
1836 unsigned int bbt_masked_page = 0xffffffff;
1838 DEBUG(MTD_DEBUG_LEVEL3, "nand_erase: start = 0x%08x, len = %i\n",
1839 (unsigned int)instr->addr, (unsigned int)instr->len);
1841 /* Start address must align on block boundary */
1842 if (instr->addr & ((1 << chip->phys_erase_shift) - 1)) {
1843 DEBUG(MTD_DEBUG_LEVEL0, "nand_erase: Unaligned address\n");
1847 /* Length must align on block boundary */
1848 if (instr->len & ((1 << chip->phys_erase_shift) - 1)) {
1849 DEBUG(MTD_DEBUG_LEVEL0, "nand_erase: "
1850 "Length not block aligned\n");
1854 /* Do not allow erase past end of device */
1855 if ((instr->len + instr->addr) > mtd->size) {
1856 DEBUG(MTD_DEBUG_LEVEL0, "nand_erase: "
1857 "Erase past end of device\n");
1861 instr->fail_addr = 0xffffffff;
1863 /* Grab the lock and see if the device is available */
1864 nand_get_device(chip, mtd, FL_ERASING);
1866 /* Shift to get first page */
1867 page = (int)(instr->addr >> chip->page_shift);
1868 chipnr = (int)(instr->addr >> chip->chip_shift);
1870 /* Calculate pages in each block */
1871 pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift);
1873 /* Select the NAND device */
1874 chip->select_chip(mtd, chipnr);
1876 /* Check, if it is write protected */
1877 if (nand_check_wp(mtd)) {
1878 DEBUG(MTD_DEBUG_LEVEL0, "nand_erase: "
1879 "Device is write protected!!!\n");
1880 instr->state = MTD_ERASE_FAILED;
1885 * If BBT requires refresh, set the BBT page mask to see if the BBT
1886 * should be rewritten. Otherwise the mask is set to 0xffffffff which
1887 * can not be matched. This is also done when the bbt is actually
1888 * erased to avoid recusrsive updates
1890 if (chip->options & BBT_AUTO_REFRESH && !allowbbt)
1891 bbt_masked_page = chip->bbt_td->pages[chipnr] & BBT_PAGE_MASK;
1893 /* Loop through the pages */
1896 instr->state = MTD_ERASING;
1900 * heck if we have a bad block, we do not erase bad blocks !
1902 if (nand_block_checkbad(mtd, ((loff_t) page) <<
1903 chip->page_shift, 0, allowbbt)) {
1904 printk(KERN_WARNING "nand_erase: attempt to erase a "
1905 "bad block at page 0x%08x\n", page);
1906 instr->state = MTD_ERASE_FAILED;
1911 * Invalidate the page cache, if we erase the block which
1912 * contains the current cached page
1914 if (page <= chip->pagebuf && chip->pagebuf <
1915 (page + pages_per_block))
1918 chip->erase_cmd(mtd, page & chip->pagemask);
1920 status = chip->waitfunc(mtd, chip, FL_ERASING);
1923 * See if operation failed and additional status checks are
1926 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
1927 status = chip->errstat(mtd, chip, FL_ERASING,
1930 /* See if block erase succeeded */
1931 if (status & NAND_STATUS_FAIL) {
1932 DEBUG(MTD_DEBUG_LEVEL0, "nand_erase: "
1933 "Failed erase, page 0x%08x\n", page);
1934 instr->state = MTD_ERASE_FAILED;
1935 instr->fail_addr = (page << chip->page_shift);
1940 * If BBT requires refresh, set the BBT rewrite flag to the
1943 if (bbt_masked_page != 0xffffffff &&
1944 (page & BBT_PAGE_MASK) == bbt_masked_page)
1945 rewrite_bbt[chipnr] = (page << chip->page_shift);
1947 /* Increment page address and decrement length */
1948 len -= (1 << chip->phys_erase_shift);
1949 page += pages_per_block;
1951 /* Check, if we cross a chip boundary */
1952 if (len && !(page & chip->pagemask)) {
1954 chip->select_chip(mtd, -1);
1955 chip->select_chip(mtd, chipnr);
1958 * If BBT requires refresh and BBT-PERCHIP, set the BBT
1959 * page mask to see if this BBT should be rewritten
1961 if (bbt_masked_page != 0xffffffff &&
1962 (chip->bbt_td->options & NAND_BBT_PERCHIP))
1963 bbt_masked_page = chip->bbt_td->pages[chipnr] &
1967 instr->state = MTD_ERASE_DONE;
1971 ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO;
1972 /* Do call back function */
1974 mtd_erase_callback(instr);
1976 /* Deselect and wake up anyone waiting on the device */
1977 nand_release_device(mtd);
1980 * If BBT requires refresh and erase was successful, rewrite any
1981 * selected bad block tables
1983 if (bbt_masked_page == 0xffffffff || ret)
1986 for (chipnr = 0; chipnr < chip->numchips; chipnr++) {
1987 if (!rewrite_bbt[chipnr])
1989 /* update the BBT for chip */
1990 DEBUG(MTD_DEBUG_LEVEL0, "nand_erase_nand: nand_update_bbt "
1991 "(%d:0x%0x 0x%0x)\n", chipnr, rewrite_bbt[chipnr],
1992 chip->bbt_td->pages[chipnr]);
1993 nand_update_bbt(mtd, rewrite_bbt[chipnr]);
1996 /* Return more or less happy */
2001 * nand_sync - [MTD Interface] sync
2002 * @mtd: MTD device structure
2004 * Sync is actually a wait for chip ready function
2006 static void nand_sync(struct mtd_info *mtd)
2008 struct nand_chip *chip = mtd->priv;
2010 DEBUG(MTD_DEBUG_LEVEL3, "nand_sync: called\n");
2012 /* Grab the lock and see if the device is available */
2013 nand_get_device(chip, mtd, FL_SYNCING);
2014 /* Release it and go back */
2015 nand_release_device(mtd);
2019 * nand_block_isbad - [MTD Interface] Check if block at offset is bad
2020 * @mtd: MTD device structure
2021 * @ofs: offset relative to mtd start
2023 static int nand_block_isbad(struct mtd_info *mtd, loff_t offs)
2025 /* Check for invalid offset */
2026 if (offs > mtd->size)
2029 return nand_block_checkbad(mtd, offs, 1, 0);
2033 * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad
2034 * @mtd: MTD device structure
2035 * @ofs: offset relative to mtd start
2037 static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs)
2039 struct nand_chip *chip = mtd->priv;
2042 if ((ret = nand_block_isbad(mtd, ofs))) {
2043 /* If it was bad already, return success and do nothing. */
2049 return chip->block_markbad(mtd, ofs);
2053 * nand_suspend - [MTD Interface] Suspend the NAND flash
2054 * @mtd: MTD device structure
2056 static int nand_suspend(struct mtd_info *mtd)
2058 struct nand_chip *chip = mtd->priv;
2060 return nand_get_device(chip, mtd, FL_PM_SUSPENDED);
2064 * nand_resume - [MTD Interface] Resume the NAND flash
2065 * @mtd: MTD device structure
2067 static void nand_resume(struct mtd_info *mtd)
2069 struct nand_chip *chip = mtd->priv;
2071 if (chip->state == FL_PM_SUSPENDED)
2072 nand_release_device(mtd);
2074 printk(KERN_ERR "nand_resume() called for a chip which is not "
2075 "in suspended state\n");
2079 * Free allocated data structures
2081 static void nand_free_kmem(struct nand_chip *chip)
2083 /* Buffer allocated by nand_scan ? */
2084 if (chip->options & NAND_OOBBUF_ALLOC)
2085 kfree(chip->oob_buf);
2086 /* Buffer allocated by nand_scan ? */
2087 if (chip->options & NAND_DATABUF_ALLOC)
2088 kfree(chip->data_buf);
2089 /* Controller allocated by nand_scan ? */
2090 if (chip->options & NAND_CONTROLLER_ALLOC)
2091 kfree(chip->controller);
2095 * Allocate buffers and data structures
2097 static int nand_allocate_kmem(struct mtd_info *mtd, struct nand_chip *chip)
2101 if (!chip->oob_buf) {
2102 len = mtd->oobsize <<
2103 (chip->phys_erase_shift - chip->page_shift);
2104 chip->oob_buf = kmalloc(len, GFP_KERNEL);
2107 chip->options |= NAND_OOBBUF_ALLOC;
2110 if (!chip->data_buf) {
2111 len = mtd->writesize + mtd->oobsize;
2112 chip->data_buf = kmalloc(len, GFP_KERNEL);
2113 if (!chip->data_buf)
2115 chip->options |= NAND_DATABUF_ALLOC;
2118 if (!chip->controller) {
2119 chip->controller = kzalloc(sizeof(struct nand_hw_control),
2121 if (!chip->controller)
2123 chip->options |= NAND_CONTROLLER_ALLOC;
2128 printk(KERN_ERR "nand_scan(): Cannot allocate buffers\n");
2129 nand_free_kmem(chip);
2134 * Set default functions
2136 static void nand_set_defaults(struct nand_chip *chip, int busw)
2138 /* check for proper chip_delay setup, set 20us if not */
2139 if (!chip->chip_delay)
2140 chip->chip_delay = 20;
2142 /* check, if a user supplied command function given */
2143 if (chip->cmdfunc == NULL)
2144 chip->cmdfunc = nand_command;
2146 /* check, if a user supplied wait function given */
2147 if (chip->waitfunc == NULL)
2148 chip->waitfunc = nand_wait;
2150 if (!chip->select_chip)
2151 chip->select_chip = nand_select_chip;
2152 if (!chip->read_byte)
2153 chip->read_byte = busw ? nand_read_byte16 : nand_read_byte;
2154 if (!chip->read_word)
2155 chip->read_word = nand_read_word;
2156 if (!chip->block_bad)
2157 chip->block_bad = nand_block_bad;
2158 if (!chip->block_markbad)
2159 chip->block_markbad = nand_default_block_markbad;
2160 if (!chip->write_buf)
2161 chip->write_buf = busw ? nand_write_buf16 : nand_write_buf;
2162 if (!chip->read_buf)
2163 chip->read_buf = busw ? nand_read_buf16 : nand_read_buf;
2164 if (!chip->verify_buf)
2165 chip->verify_buf = busw ? nand_verify_buf16 : nand_verify_buf;
2166 if (!chip->scan_bbt)
2167 chip->scan_bbt = nand_default_bbt;
2171 * Get the flash and manufacturer id and lookup if the type is supported
2173 static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
2174 struct nand_chip *chip,
2175 int busw, int *maf_id)
2177 struct nand_flash_dev *type = NULL;
2178 int i, dev_id, maf_idx;
2180 /* Select the device */
2181 chip->select_chip(mtd, 0);
2183 /* Send the command for reading device ID */
2184 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2186 /* Read manufacturer and device IDs */
2187 *maf_id = chip->read_byte(mtd);
2188 dev_id = chip->read_byte(mtd);
2190 /* Lookup the flash id */
2191 for (i = 0; nand_flash_ids[i].name != NULL; i++) {
2192 if (dev_id == nand_flash_ids[i].id) {
2193 type = &nand_flash_ids[i];
2199 return ERR_PTR(-ENODEV);
2201 chip->chipsize = nand_flash_ids[i].chipsize << 20;
2203 /* Newer devices have all the information in additional id bytes */
2204 if (!nand_flash_ids[i].pagesize) {
2206 /* The 3rd id byte contains non relevant data ATM */
2207 extid = chip->read_byte(mtd);
2208 /* The 4th id byte is the important one */
2209 extid = chip->read_byte(mtd);
2211 mtd->writesize = 1024 << (extid & 0x3);
2214 mtd->oobsize = (8 << (extid & 0x01)) * (mtd->writesize >> 9);
2216 /* Calc blocksize. Blocksize is multiples of 64KiB */
2217 mtd->erasesize = (64 * 1024) << (extid & 0x03);
2219 /* Get buswidth information */
2220 busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0;
2224 * Old devices have chip data hardcoded in the device id table
2226 mtd->erasesize = nand_flash_ids[i].erasesize;
2227 mtd->writesize = nand_flash_ids[i].pagesize;
2228 mtd->oobsize = mtd->writesize / 32;
2229 busw = nand_flash_ids[i].options & NAND_BUSWIDTH_16;
2232 /* Try to identify manufacturer */
2233 for (maf_idx = 0; nand_manuf_ids[maf_idx].id != 0x0; maf_id++) {
2234 if (nand_manuf_ids[maf_idx].id == *maf_id)
2239 * Check, if buswidth is correct. Hardware drivers should set
2242 if (busw != (chip->options & NAND_BUSWIDTH_16)) {
2243 printk(KERN_INFO "NAND device: Manufacturer ID:"
2244 " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id,
2245 dev_id, nand_manuf_ids[maf_idx].name, mtd->name);
2246 printk(KERN_WARNING "NAND bus width %d instead %d bit\n",
2247 (chip->options & NAND_BUSWIDTH_16) ? 16 : 8,
2249 return ERR_PTR(-EINVAL);
2252 /* Calculate the address shift from the page size */
2253 chip->page_shift = ffs(mtd->writesize) - 1;
2254 /* Convert chipsize to number of pages per chip -1. */
2255 chip->pagemask = (chip->chipsize >> chip->page_shift) - 1;
2257 chip->bbt_erase_shift = chip->phys_erase_shift =
2258 ffs(mtd->erasesize) - 1;
2259 chip->chip_shift = ffs(chip->chipsize) - 1;
2261 /* Set the bad block position */
2262 chip->badblockpos = mtd->writesize > 512 ?
2263 NAND_LARGE_BADBLOCK_POS : NAND_SMALL_BADBLOCK_POS;
2265 /* Get chip options, preserve non chip based options */
2266 chip->options &= ~NAND_CHIPOPTIONS_MSK;
2267 chip->options |= nand_flash_ids[i].options & NAND_CHIPOPTIONS_MSK;
2270 * Set chip as a default. Board drivers can override it, if necessary
2272 chip->options |= NAND_NO_AUTOINCR;
2274 /* Check if chip is a not a samsung device. Do not clear the
2275 * options for chips which are not having an extended id.
2277 if (*maf_id != NAND_MFR_SAMSUNG && !nand_flash_ids[i].pagesize)
2278 chip->options &= ~NAND_SAMSUNG_LP_OPTIONS;
2280 /* Check for AND chips with 4 page planes */
2281 if (chip->options & NAND_4PAGE_ARRAY)
2282 chip->erase_cmd = multi_erase_cmd;
2284 chip->erase_cmd = single_erase_cmd;
2286 /* Do not replace user supplied command function ! */
2287 if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
2288 chip->cmdfunc = nand_command_lp;
2290 printk(KERN_INFO "NAND device: Manufacturer ID:"
2291 " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id, dev_id,
2292 nand_manuf_ids[maf_idx].name, type->name);
2297 /* module_text_address() isn't exported, and it's mostly a pointless
2298 test if this is a module _anyway_ -- they'd have to try _really_ hard
2299 to call us from in-kernel code if the core NAND support is modular. */
2301 #define caller_is_module() (1)
2303 #define caller_is_module() \
2304 module_text_address((unsigned long)__builtin_return_address(0))
2308 * nand_scan - [NAND Interface] Scan for the NAND device
2309 * @mtd: MTD device structure
2310 * @maxchips: Number of chips to scan for
2312 * This fills out all the uninitialized function pointers
2313 * with the defaults.
2314 * The flash ID is read and the mtd/chip structures are
2315 * filled with the appropriate values. Buffers are allocated if
2316 * they are not provided by the board driver
2317 * The mtd->owner field must be set to the module of the caller
2320 int nand_scan(struct mtd_info *mtd, int maxchips)
2322 int i, busw, nand_maf_id;
2323 struct nand_chip *chip = mtd->priv;
2324 struct nand_flash_dev *type;
2326 /* Many callers got this wrong, so check for it for a while... */
2327 if (!mtd->owner && caller_is_module()) {
2328 printk(KERN_CRIT "nand_scan() called with NULL mtd->owner!\n");
2332 /* Get buswidth to select the correct functions */
2333 busw = chip->options & NAND_BUSWIDTH_16;
2334 /* Set the default functions */
2335 nand_set_defaults(chip, busw);
2337 /* Read the flash type */
2338 type = nand_get_flash_type(mtd, chip, busw, &nand_maf_id);
2341 printk(KERN_WARNING "No NAND device found!!!\n");
2342 chip->select_chip(mtd, -1);
2343 return PTR_ERR(type);
2346 /* Check for a chip array */
2347 for (i = 1; i < maxchips; i++) {
2348 chip->select_chip(mtd, i);
2349 /* Send the command for reading device ID */
2350 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2351 /* Read manufacturer and device IDs */
2352 if (nand_maf_id != chip->read_byte(mtd) ||
2353 type->id != chip->read_byte(mtd))
2357 printk(KERN_INFO "%d NAND chips detected\n", i);
2359 /* Store the number of chips and calc total size for mtd */
2361 mtd->size = i * chip->chipsize;
2363 /* Allocate buffers and data structures */
2364 if (nand_allocate_kmem(mtd, chip))
2367 /* Preset the internal oob buffer */
2368 memset(chip->oob_buf, 0xff,
2369 mtd->oobsize << (chip->phys_erase_shift - chip->page_shift));
2372 * If no default placement scheme is given, select an appropriate one
2374 if (!chip->autooob) {
2375 switch (mtd->oobsize) {
2377 chip->autooob = &nand_oob_8;
2380 chip->autooob = &nand_oob_16;
2383 chip->autooob = &nand_oob_64;
2386 printk(KERN_WARNING "No oob scheme defined for "
2387 "oobsize %d\n", mtd->oobsize);
2393 * The number of bytes available for the filesystem to place fs
2394 * dependend oob data
2397 for (i = 0; chip->autooob->oobfree[i][1]; i++)
2398 mtd->oobavail += chip->autooob->oobfree[i][1];
2401 * check ECC mode, default to software if 3byte/512byte hardware ECC is
2402 * selected and we have 256 byte pagesize fallback to software ECC
2404 switch (chip->ecc.mode) {
2406 case NAND_ECC_HW_SYNDROME:
2407 if (!chip->ecc.calculate || !chip->ecc.correct ||
2409 printk(KERN_WARNING "No ECC functions supplied, "
2410 "Hardware ECC not possible\n");
2413 if (mtd->writesize >= chip->ecc.size)
2415 printk(KERN_WARNING "%d byte HW ECC not possible on "
2416 "%d byte page size, fallback to SW ECC\n",
2417 chip->ecc.size, mtd->writesize);
2418 chip->ecc.mode = NAND_ECC_SOFT;
2421 chip->ecc.calculate = nand_calculate_ecc;
2422 chip->ecc.correct = nand_correct_data;
2423 chip->ecc.size = 256;
2424 chip->ecc.bytes = 3;
2428 printk(KERN_WARNING "NAND_ECC_NONE selected by board driver. "
2429 "This is not recommended !!\n");
2430 chip->ecc.size = mtd->writesize;
2431 chip->ecc.bytes = 0;
2434 printk(KERN_WARNING "Invalid NAND_ECC_MODE %d\n",
2440 * Set the number of read / write steps for one page depending on ECC
2443 chip->ecc.steps = mtd->writesize / chip->ecc.size;
2444 if(chip->ecc.steps * chip->ecc.size != mtd->writesize) {
2445 printk(KERN_WARNING "Invalid ecc parameters\n");
2449 /* Initialize state, waitqueue and spinlock */
2450 chip->state = FL_READY;
2451 init_waitqueue_head(&chip->controller->wq);
2452 spin_lock_init(&chip->controller->lock);
2454 /* De-select the device */
2455 chip->select_chip(mtd, -1);
2457 /* Invalidate the pagebuffer reference */
2460 /* Fill in remaining MTD driver data */
2461 mtd->type = MTD_NANDFLASH;
2462 mtd->flags = MTD_CAP_NANDFLASH;
2463 mtd->ecctype = MTD_ECC_SW;
2464 mtd->erase = nand_erase;
2466 mtd->unpoint = NULL;
2467 mtd->read = nand_read;
2468 mtd->write = nand_write;
2469 mtd->read_oob = nand_read_oob;
2470 mtd->write_oob = nand_write_oob;
2471 mtd->sync = nand_sync;
2474 mtd->suspend = nand_suspend;
2475 mtd->resume = nand_resume;
2476 mtd->block_isbad = nand_block_isbad;
2477 mtd->block_markbad = nand_block_markbad;
2479 /* and make the autooob the default one */
2480 memcpy(&mtd->oobinfo, chip->autooob, sizeof(mtd->oobinfo));
2482 /* Check, if we should skip the bad block table scan */
2483 if (chip->options & NAND_SKIP_BBTSCAN)
2486 /* Build bad block table */
2487 return chip->scan_bbt(mtd);
2491 * nand_release - [NAND Interface] Free resources held by the NAND device
2492 * @mtd: MTD device structure
2494 void nand_release(struct mtd_info *mtd)
2496 struct nand_chip *chip = mtd->priv;
2498 #ifdef CONFIG_MTD_PARTITIONS
2499 /* Deregister partitions */
2500 del_mtd_partitions(mtd);
2502 /* Deregister the device */
2503 del_mtd_device(mtd);
2505 /* Free bad block table memory */
2508 nand_free_kmem(chip);
2511 EXPORT_SYMBOL_GPL(nand_scan);
2512 EXPORT_SYMBOL_GPL(nand_release);
2514 static int __init nand_base_init(void)
2516 led_trigger_register_simple("nand-disk", &nand_led_trigger);
2520 static void __exit nand_base_exit(void)
2522 led_trigger_unregister_simple(nand_led_trigger);
2525 module_init(nand_base_init);
2526 module_exit(nand_base_exit);
2528 MODULE_LICENSE("GPL");
2529 MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>, Thomas Gleixner <tglx@linutronix.de>");
2530 MODULE_DESCRIPTION("Generic NAND flash driver code");