2 * drivers/mtd/nand/omap-hw.c
4 * This is the MTD driver for OMAP 1710 internal HW nand controller.
6 * Copyright (C) 2004 Nokia Corporation
8 * Author: Jarkko Lavinen <jarkko.lavinen@nokia.com>
10 * Dma patches by Juha Yrjölä <juha.yrjola@nokia.com>
12 * $Id: omap-hw.c,v 1.1 2004/12/08 00:00:01 jlavi Exp $
14 * This program is free software; you can redistribute it and/or modify it
15 * under the terms of the GNU General Public License version 2 as published by
16 * the Free Software Foundation.
18 * This program is distributed in the hope that it will be useful, but WITHOUT
19 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
20 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
23 * You should have received a copy of the GNU General Public License along with
24 * this program; see the file COPYING. If not, write to the Free Software
25 * Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
29 #include <linux/slab.h>
30 #include <linux/init.h>
31 #include <linux/module.h>
32 #include <linux/delay.h>
33 #include <linux/delay.h>
34 #include <linux/errno.h>
35 #include <linux/sched.h>
36 #include <linux/types.h>
37 #include <linux/wait.h>
38 #include <linux/spinlock.h>
39 #include <linux/interrupt.h>
40 #include <linux/mtd/mtd.h>
41 #include <linux/mtd/nand.h>
42 #include <linux/mtd/partitions.h>
43 #include <linux/mtd/nand_ecc.h>
44 #include <linux/dma-mapping.h>
45 #include <linux/clk.h>
49 #include <asm/arch/board.h>
50 #include <asm/arch/dma.h>
52 #define NAND_BASE 0xfffbcc00
53 #define NND_REVISION 0x00
54 #define NND_ACCESS 0x04
55 #define NND_ADDR_SRC 0x08
58 #define NND_STATUS 0x18
59 #define NND_READY 0x1c
60 #define NND_COMMAND 0x20
61 #define NND_COMMAND_SEC 0x24
62 #define NND_ECC_SELECT 0x28
63 #define NND_ECC_START 0x2c
64 #define NND_ECC_9 0x4c
65 #define NND_RESET 0x50
67 #define NND_FIFOCTRL 0x58
68 #define NND_PSC_CLK 0x5c
69 #define NND_SYSTEST 0x60
70 #define NND_SYSCFG 0x64
71 #define NND_SYSSTATUS 0x68
72 #define NND_FIFOTEST1 0x6c
73 #define NND_FIFOTEST2 0x70
74 #define NND_FIFOTEST3 0x74
75 #define NND_FIFOTEST4 0x78
76 #define NND_PSC1_CLK 0x8c
77 #define NND_PSC2_CLK 0x90
80 #define NND_CMD_READ1_LOWER 0x00
81 #define NND_CMD_WRITE1_LOWER 0x00
82 #define NND_CMD_READ1_UPPER 0x01
83 #define NND_CMD_WRITE1_UPPER 0x01
84 #define NND_CMD_PROGRAM_END 0x10
85 #define NND_CMD_READ2_SPARE 0x50
86 #define NND_CMD_WRITE2_SPARE 0x50
87 #define NND_CMD_ERASE 0x60
88 #define NND_CMD_STATUS 0x70
89 #define NND_CMD_PROGRAM 0x80
90 #define NND_CMD_READ_ID 0x90
91 #define NND_CMD_ERASE_END 0xD0
92 #define NND_CMD_RESET 0xFF
95 #define NAND_Ecc_P1e (1 << 0)
96 #define NAND_Ecc_P2e (1 << 1)
97 #define NAND_Ecc_P4e (1 << 2)
98 #define NAND_Ecc_P8e (1 << 3)
99 #define NAND_Ecc_P16e (1 << 4)
100 #define NAND_Ecc_P32e (1 << 5)
101 #define NAND_Ecc_P64e (1 << 6)
102 #define NAND_Ecc_P128e (1 << 7)
103 #define NAND_Ecc_P256e (1 << 8)
104 #define NAND_Ecc_P512e (1 << 9)
105 #define NAND_Ecc_P1024e (1 << 10)
106 #define NAND_Ecc_P2048e (1 << 11)
108 #define NAND_Ecc_P1o (1 << 16)
109 #define NAND_Ecc_P2o (1 << 17)
110 #define NAND_Ecc_P4o (1 << 18)
111 #define NAND_Ecc_P8o (1 << 19)
112 #define NAND_Ecc_P16o (1 << 20)
113 #define NAND_Ecc_P32o (1 << 21)
114 #define NAND_Ecc_P64o (1 << 22)
115 #define NAND_Ecc_P128o (1 << 23)
116 #define NAND_Ecc_P256o (1 << 24)
117 #define NAND_Ecc_P512o (1 << 25)
118 #define NAND_Ecc_P1024o (1 << 26)
119 #define NAND_Ecc_P2048o (1 << 27)
121 #define TF(value) (value ? 1 : 0)
123 #define P2048e(a) (TF(a & NAND_Ecc_P2048e) << 0 )
124 #define P2048o(a) (TF(a & NAND_Ecc_P2048o) << 1 )
125 #define P1e(a) (TF(a & NAND_Ecc_P1e) << 2 )
126 #define P1o(a) (TF(a & NAND_Ecc_P1o) << 3 )
127 #define P2e(a) (TF(a & NAND_Ecc_P2e) << 4 )
128 #define P2o(a) (TF(a & NAND_Ecc_P2o) << 5 )
129 #define P4e(a) (TF(a & NAND_Ecc_P4e) << 6 )
130 #define P4o(a) (TF(a & NAND_Ecc_P4o) << 7 )
132 #define P8e(a) (TF(a & NAND_Ecc_P8e) << 0 )
133 #define P8o(a) (TF(a & NAND_Ecc_P8o) << 1 )
134 #define P16e(a) (TF(a & NAND_Ecc_P16e) << 2 )
135 #define P16o(a) (TF(a & NAND_Ecc_P16o) << 3 )
136 #define P32e(a) (TF(a & NAND_Ecc_P32e) << 4 )
137 #define P32o(a) (TF(a & NAND_Ecc_P32o) << 5 )
138 #define P64e(a) (TF(a & NAND_Ecc_P64e) << 6 )
139 #define P64o(a) (TF(a & NAND_Ecc_P64o) << 7 )
141 #define P128e(a) (TF(a & NAND_Ecc_P128e) << 0 )
142 #define P128o(a) (TF(a & NAND_Ecc_P128o) << 1 )
143 #define P256e(a) (TF(a & NAND_Ecc_P256e) << 2 )
144 #define P256o(a) (TF(a & NAND_Ecc_P256o) << 3 )
145 #define P512e(a) (TF(a & NAND_Ecc_P512e) << 4 )
146 #define P512o(a) (TF(a & NAND_Ecc_P512o) << 5 )
147 #define P1024e(a) (TF(a & NAND_Ecc_P1024e) << 6 )
148 #define P1024o(a) (TF(a & NAND_Ecc_P1024o) << 7 )
150 #define P8e_s(a) (TF(a & NAND_Ecc_P8e) << 0 )
151 #define P8o_s(a) (TF(a & NAND_Ecc_P8o) << 1 )
152 #define P16e_s(a) (TF(a & NAND_Ecc_P16e) << 2 )
153 #define P16o_s(a) (TF(a & NAND_Ecc_P16o) << 3 )
154 #define P1e_s(a) (TF(a & NAND_Ecc_P1e) << 4 )
155 #define P1o_s(a) (TF(a & NAND_Ecc_P1o) << 5 )
156 #define P2e_s(a) (TF(a & NAND_Ecc_P2e) << 6 )
157 #define P2o_s(a) (TF(a & NAND_Ecc_P2o) << 7 )
159 #define P4e_s(a) (TF(a & NAND_Ecc_P4e) << 0 )
160 #define P4o_s(a) (TF(a & NAND_Ecc_P4o) << 1 )
162 extern struct nand_oobinfo jffs2_oobinfo;
165 * MTD structure for OMAP board
167 static struct mtd_info *omap_mtd;
168 static struct clk *omap_nand_clk;
169 static unsigned long omap_nand_base = io_p2v(NAND_BASE);
172 static inline u32 nand_read_reg(int idx)
174 return __raw_readl(omap_nand_base + idx);
177 static inline void nand_write_reg(int idx, u32 val)
179 __raw_writel(val, omap_nand_base + idx);
182 static inline u8 nand_read_reg8(int idx)
184 return __raw_readb(omap_nand_base + idx);
187 static inline void nand_write_reg8(int idx, u8 val)
189 __raw_writeb(val, omap_nand_base + idx);
192 static void omap_nand_select_chip(struct mtd_info *mtd, int chip)
198 l = nand_read_reg(NND_CTRL);
199 l |= (1 << 8) | (1 << 10) | (1 << 12) | (1 << 14);
200 nand_write_reg(NND_CTRL, l);
203 /* Also CS1, CS2, CS4 would be available */
204 l = nand_read_reg(NND_CTRL);
206 nand_write_reg(NND_CTRL, l);
213 static void nand_dma_cb(int lch, u16 ch_status, void *data)
215 complete((struct completion *) data);
218 static inline int omap_nand_dma_transfer(struct mtd_info *mtd, void *addr,
219 unsigned int u32_count, int is_write)
221 const int block_size = 16;
222 unsigned int block_count, len;
224 struct completion comp;
225 unsigned long fifo_reg;
227 r = omap_request_dma(OMAP_DMA_NAND, "NAND", nand_dma_cb, &comp, &dma_ch);
230 block_count = u32_count * 4 / block_size;
231 nand_write_reg(NND_FIFOCTRL, (block_size << 24) | block_count);
232 fifo_reg = NAND_BASE + NND_FIFO;
234 omap_set_dma_dest_params(dma_ch, OMAP_DMA_PORT_TIPB,
235 OMAP_DMA_AMODE_CONSTANT, fifo_reg,
237 omap_set_dma_src_params(dma_ch, OMAP_DMA_PORT_EMIFF,
238 OMAP_DMA_AMODE_POST_INC,
241 // omap_set_dma_src_burst_mode(dma_ch, OMAP_DMA_DATA_BURST_4);
242 /* Set POSTWRITE bit */
243 nand_write_reg(NND_CTRL, nand_read_reg(NND_CTRL) | (1 << 16));
245 omap_set_dma_src_params(dma_ch, OMAP_DMA_PORT_TIPB,
246 OMAP_DMA_AMODE_CONSTANT, fifo_reg,
248 omap_set_dma_dest_params(dma_ch, OMAP_DMA_PORT_EMIFF,
249 OMAP_DMA_AMODE_POST_INC,
252 // omap_set_dma_dest_burst_mode(dma_ch, OMAP_DMA_DATA_BURST_8);
253 /* Set PREFETCH bit */
254 nand_write_reg(NND_CTRL, nand_read_reg(NND_CTRL) | (1 << 17));
256 omap_set_dma_transfer_params(dma_ch, OMAP_DMA_DATA_TYPE_S32, block_size / 4,
257 block_count, OMAP_DMA_SYNC_FRAME,
259 init_completion(&comp);
261 len = u32_count << 2;
262 consistent_sync(addr, len, DMA_TO_DEVICE);
263 omap_start_dma(dma_ch);
264 wait_for_completion(&comp);
265 omap_free_dma(dma_ch);
267 consistent_sync(addr, len, DMA_FROM_DEVICE);
269 nand_write_reg(NND_CTRL, nand_read_reg(NND_CTRL) & ~((1 << 16) | (1 << 17)));
273 static void fifo_read(u32 *out, unsigned int len)
275 const int block_size = 16;
276 unsigned long status_reg, fifo_reg;
279 status_reg = omap_nand_base + NND_STATUS;
280 fifo_reg = omap_nand_base + NND_FIFO;
281 len = len * 4 / block_size;
282 nand_write_reg(NND_FIFOCTRL, (block_size << 24) | len);
283 nand_write_reg(NND_STATUS, 0x0f);
284 nand_write_reg(NND_CTRL, nand_read_reg(NND_CTRL) | (1 << 17));
289 while ((__raw_readl(status_reg) & (1 << 2)) == 0);
290 __raw_writel(0x0f, status_reg);
291 for (i = 0; i < c; i++) {
292 u32 l = __raw_readl(fifo_reg);
296 nand_write_reg(NND_CTRL, nand_read_reg(NND_CTRL) & ~(1 << 17));
297 nand_write_reg(NND_STATUS, 0x0f);
300 static void omap_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
302 unsigned long access_reg;
304 if (likely(((unsigned long) buf & 3) == 0 && (len & 3) == 0)) {
305 int u32_count = len >> 2;
306 u32 *dest = (u32 *) buf;
307 /* If the transfer is big enough and the length divisible by
308 * 16, we try to use DMA transfer, or FIFO copy in case of
309 * DMA failure (e.g. all channels busy) */
310 if (u32_count > 64 && (u32_count & 3) == 0) {
312 if (omap_nand_dma_transfer(mtd, buf, u32_count, 0) == 0)
315 /* In case of an error, fallback to FIFO copy */
316 fifo_read((u32 *) buf, u32_count);
319 access_reg = omap_nand_base + NND_ACCESS;
320 /* Small buffers we just read directly */
322 *dest++ = __raw_readl(access_reg);
324 /* If we're not word-aligned, we use byte copy */
325 access_reg = omap_nand_base + NND_ACCESS;
327 *buf++ = __raw_readb(access_reg);
331 static void omap_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
333 if (likely(((unsigned long) buf & 3) == 0 && (len & 3) == 0)) {
334 const u32 *src = (const u32 *) buf;
338 /* If the transfer is big enough and length divisible by 16,
339 * we try to use DMA transfer. */
340 if (len > 256 / 4 && (len & 3) == 0) {
341 if (omap_nand_dma_transfer(mtd, (void *) buf, len, 1) == 0)
343 /* In case of an error, fallback to CPU copy */
347 nand_write_reg(NND_ACCESS, *src++);
350 nand_write_reg8(NND_ACCESS, *buf++);
354 static int omap_nand_verify_buf(struct mtd_info *mtd, const u_char *buf, int len)
356 if (likely(((unsigned long) buf & 3) == 0 && (len & 3) == 0)) {
357 const u32 *dest = (const u32 *) buf;
360 if (*dest++ != nand_read_reg(NND_ACCESS))
364 if (*buf++ != nand_read_reg8(NND_ACCESS))
370 static u_char omap_nand_read_byte(struct mtd_info *mtd)
372 return nand_read_reg8(NND_ACCESS);
375 static void omap_nand_write_byte(struct mtd_info *mtd, u_char byte)
377 nand_write_reg8(NND_ACCESS, byte);
380 static int omap_nand_dev_ready(struct mtd_info *mtd)
384 l = nand_read_reg(NND_READY);
388 static int nand_write_command(u8 cmd, u32 addr, int addr_valid)
391 nand_write_reg(NND_ADDR_SRC, addr);
392 nand_write_reg8(NND_COMMAND, cmd);
394 nand_write_reg(NND_ADDR_SRC, 0);
395 nand_write_reg8(NND_COMMAND_SEC, cmd);
397 while (!omap_nand_dev_ready(NULL));
402 * Send command to NAND device
404 static void omap_nand_command(struct mtd_info *mtd, unsigned command, int column, int page_addr)
406 struct nand_chip *this = mtd->priv;
409 * Write out the command to the device.
411 if (command == NAND_CMD_SEQIN) {
414 if (column >= mtd->oobblock) {
416 column -= mtd->oobblock;
417 readcmd = NAND_CMD_READOOB;
418 } else if (column < 256) {
419 /* First 256 bytes --> READ0 */
420 readcmd = NAND_CMD_READ0;
423 readcmd = NAND_CMD_READ1;
425 nand_write_command(readcmd, 0, 0);
430 case NAND_CMD_PAGEPROG:
431 case NAND_CMD_STATUS:
432 case NAND_CMD_ERASE2:
433 nand_write_command(command, 0, 0);
436 case NAND_CMD_ERASE1:
437 nand_write_command(command, ((page_addr & 0xFFFFFF00) << 1) | (page_addr & 0XFF), 1);
441 nand_write_command(command, (page_addr << this->page_shift) | column, 1);
445 static void omap_nand_command_lp(struct mtd_info *mtd, unsigned command, int column, int page_addr)
447 struct nand_chip *this = mtd->priv;
449 if (command == NAND_CMD_READOOB) {
450 column += mtd->oobblock;
451 command = NAND_CMD_READ0;
455 case NAND_CMD_PAGEPROG:
456 case NAND_CMD_STATUS:
457 case NAND_CMD_ERASE2:
458 nand_write_command(command, 0, 0);
460 case NAND_CMD_ERASE1:
461 nand_write_command(command, page_addr << this->page_shift >> 11, 1);
464 nand_write_command(command, (page_addr << 16) | column, 1);
466 if (command == NAND_CMD_READ0)
467 nand_write_command(NAND_CMD_READSTART, 0, 0);
471 * Generate non-inverted ECC bytes.
473 * Using noninverted ECC can be considered ugly since writing a blank
474 * page ie. padding will clear the ECC bytes. This is no problem as long
475 * nobody is trying to write data on the seemingly unused page.
477 * Reading an erased page will produce an ECC mismatch between
478 * generated and read ECC bytes that has to be dealt with separately.
480 static int omap_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code)
485 struct nand_chip *this = mtd->priv;
487 if (this->eccmode == NAND_ECC_HW12_2048)
493 l = nand_read_reg(reg);
494 *ecc_code++ = l; // P128e, ..., P1e
495 *ecc_code++ = l >> 16; // P128o, ..., P1o
496 // P2048o, P1024o, P512o, P256o, P2048e, P1024e, P512e, P256e
497 *ecc_code++ = ((l >> 8) & 0x0f) | ((l >> 20) & 0xf0);
504 * This function will generate true ECC value, which can be used
505 * when correcting data read from NAND flash memory core
507 static void gen_true_ecc(u8 *ecc_buf)
509 u32 tmp = ecc_buf[0] | (ecc_buf[1] << 16) | ((ecc_buf[2] & 0xF0) << 20) | ((ecc_buf[2] & 0x0F) << 8);
511 ecc_buf[0] = ~(P64o(tmp) | P64e(tmp) | P32o(tmp) | P32e(tmp) | P16o(tmp) | P16e(tmp) | P8o(tmp) | P8e(tmp) );
512 ecc_buf[1] = ~(P1024o(tmp) | P1024e(tmp) | P512o(tmp) | P512e(tmp) | P256o(tmp) | P256e(tmp) | P128o(tmp) | P128e(tmp));
513 ecc_buf[2] = ~( P4o(tmp) | P4e(tmp) | P2o(tmp) | P2e(tmp) | P1o(tmp) | P1e(tmp) | P2048o(tmp) | P2048e(tmp));
517 * This function compares two ECC's and indicates if there is an error.
518 * If the error can be corrected it will be corrected to the buffer
520 static int omap_nand_compare_ecc(u8 *ecc_data1, /* read from NAND memory */
521 u8 *ecc_data2, /* read from register */
525 u8 tmp0_bit[8], tmp1_bit[8], tmp2_bit[8];
526 u8 comp0_bit[8], comp1_bit[8], comp2_bit[8];
533 isEccFF = ((*(u32 *)ecc_data1 & 0xFFFFFF) == 0xFFFFFF);
535 gen_true_ecc(ecc_data1);
536 gen_true_ecc(ecc_data2);
538 for (i = 0; i <= 2; i++) {
539 *(ecc_data1 + i) = ~(*(ecc_data1 + i));
540 *(ecc_data2 + i) = ~(*(ecc_data2 + i));
543 for (i = 0; i < 8; i++) {
544 tmp0_bit[i] = *ecc_data1 % 2;
545 *ecc_data1 = *ecc_data1 / 2;
548 for (i = 0; i < 8; i++) {
549 tmp1_bit[i] = *(ecc_data1 + 1) % 2;
550 *(ecc_data1 + 1) = *(ecc_data1 + 1) / 2;
553 for (i = 0; i < 8; i++) {
554 tmp2_bit[i] = *(ecc_data1 + 2) % 2;
555 *(ecc_data1 + 2) = *(ecc_data1 + 2) / 2;
558 for (i = 0; i < 8; i++) {
559 comp0_bit[i] = *ecc_data2 % 2;
560 *ecc_data2 = *ecc_data2 / 2;
563 for (i = 0; i < 8; i++) {
564 comp1_bit[i] = *(ecc_data2 + 1) % 2;
565 *(ecc_data2 + 1) = *(ecc_data2 + 1) / 2;
568 for (i = 0; i < 8; i++) {
569 comp2_bit[i] = *(ecc_data2 + 2) % 2;
570 *(ecc_data2 + 2) = *(ecc_data2 + 2) / 2;
573 for (i = 0; i< 6; i++ )
574 ecc_bit[i] = tmp2_bit[i + 2] ^ comp2_bit[i + 2];
576 for (i = 0; i < 8; i++)
577 ecc_bit[i + 6] = tmp0_bit[i] ^ comp0_bit[i];
579 for (i = 0; i < 8; i++)
580 ecc_bit[i + 14] = tmp1_bit[i] ^ comp1_bit[i];
582 ecc_bit[22] = tmp2_bit[0] ^ comp2_bit[0];
583 ecc_bit[23] = tmp2_bit[1] ^ comp2_bit[1];
585 for (i = 0; i < 24; i++)
586 ecc_sum += ecc_bit[i];
590 /* Not reached because this function is not called if
591 ECC values are equal */
595 /* Uncorrectable error */
596 DEBUG (MTD_DEBUG_LEVEL0, "ECC UNCORRECTED_ERROR 1\n");
600 /* Correctable error */
601 find_byte = (ecc_bit[23] << 8) +
611 find_bit = (ecc_bit[5] << 2) + (ecc_bit[3] << 1) + ecc_bit[1];
613 DEBUG (MTD_DEBUG_LEVEL0, "Correcting single bit ECC error at offset: %d, bit: %d\n", find_byte, find_bit);
615 page_data[find_byte] ^= (1 << find_bit);
620 if (ecc_data2[0] == 0 && ecc_data2[1] == 0 && ecc_data2[2] == 0)
623 DEBUG (MTD_DEBUG_LEVEL0, "UNCORRECTED_ERROR default\n");
628 static int omap_nand_correct_data(struct mtd_info *mtd, u_char *dat, u_char *read_ecc, u_char *calc_ecc)
630 struct nand_chip *this;
631 int block_count = 0, i, r;
634 if (this->eccmode == NAND_ECC_HW12_2048)
638 for (i = 0; i < block_count; i++) {
639 if (memcmp(read_ecc, calc_ecc, 3) != 0) {
640 r = omap_nand_compare_ecc(read_ecc, calc_ecc, dat);
651 static void omap_nand_enable_hwecc(struct mtd_info *mtd, int mode)
653 nand_write_reg(NND_RESET, 0x01);
656 static int omap_nand_scan_bbt(struct mtd_info *mtd)
661 #ifdef CONFIG_MTD_CMDLINE_PARTS
663 extern int mtdpart_setup(char *);
665 static int __init add_dynamic_parts(struct mtd_info *mtd)
667 static const char *part_parsers[] = { "cmdlinepart", NULL };
668 struct mtd_partition *parts;
669 const struct omap_flash_part_config *cfg;
670 char *part_str = NULL;
674 cfg = omap_get_var_config(OMAP_TAG_FLASH_PART, &part_str_len);
676 part_str = kmalloc(part_str_len + 1, GFP_KERNEL);
677 if (part_str == NULL)
679 memcpy(part_str, cfg->part_table, part_str_len);
680 part_str[part_str_len] = '\0';
681 mtdpart_setup(part_str);
683 c = parse_mtd_partitions(omap_mtd, part_parsers, &parts, 0);
684 if (part_str != NULL) {
691 add_mtd_partitions(mtd, parts, c);
698 static inline int add_dynamic_parts(struct mtd_info *mtd)
705 static inline int calc_psc(int ns, int cycle_ps)
707 return (ns * 1000 + (cycle_ps - 1)) / cycle_ps;
710 static void set_psc_regs(int psc_ns, int psc1_ns, int psc2_ns)
713 unsigned long rate, ps;
715 rate = clk_get_rate(omap_nand_clk);
716 ps = 1000000000 / (rate / 1000);
717 psc[0] = calc_psc(psc_ns, ps);
718 psc[1] = calc_psc(psc1_ns, ps);
719 psc[2] = calc_psc(psc2_ns, ps);
720 for (i = 0; i < 3; i++) {
723 else if (psc[i] > 256)
726 nand_write_reg(NND_PSC_CLK, psc[0] - 1);
727 nand_write_reg(NND_PSC1_CLK, psc[1] - 1);
728 nand_write_reg(NND_PSC2_CLK, psc[2] - 1);
729 printk(KERN_INFO "omap-hw-nand: using PSC values %d, %d, %d\n", psc[0], psc[1], psc[2]);
733 * Main initialization routine
735 static int __init omap_nand_init(void)
737 struct nand_chip *this;
741 omap_nand_clk = clk_get(NULL, "armper_ck");
742 BUG_ON(omap_nand_clk == NULL);
743 clk_enable(omap_nand_clk);
745 l = nand_read_reg(NND_REVISION);
746 printk(KERN_INFO "omap-hw-nand: OMAP NAND Controller rev. %d.%d\n", l>>4, l & 0xf);
748 /* Reset the NAND Controller */
749 nand_write_reg(NND_SYSCFG, 0x02);
750 while ((nand_read_reg(NND_SYSSTATUS) & 0x01) == 0);
752 /* No Prefetch, no postwrite, write prot & enable pairs disabled,
753 addres counter set to send 4 byte addresses to flash,
754 A8 is set not to be sent to flash (erase addre needs formatting),
755 choose little endian, enable 512 byte ECC logic,
757 nand_write_reg(NND_CTRL, 0xFF01);
759 /* Allocate memory for MTD device structure and private data */
760 omap_mtd = kmalloc(sizeof(struct mtd_info) + sizeof(struct nand_chip), GFP_KERNEL);
762 printk(KERN_WARNING "omap-hw-nand: Unable to allocate OMAP NAND MTD device structure.\n");
767 /* Get pointer to private data */
768 this = (struct nand_chip *) (&omap_mtd[1]);
770 /* Initialize structures */
771 memset((char *) omap_mtd, 0, sizeof(struct mtd_info));
772 memset((char *) this, 0, sizeof(struct nand_chip));
774 /* Link the private data with the MTD structure */
775 omap_mtd->priv = this;
776 omap_mtd->name = "omap-nand";
778 /* Used from chip select and nand_command() */
779 this->read_byte = omap_nand_read_byte;
780 this->write_byte = omap_nand_write_byte;
782 this->select_chip = omap_nand_select_chip;
783 this->dev_ready = omap_nand_dev_ready;
784 this->chip_delay = 0;
785 this->eccmode = NAND_ECC_HW3_512;
786 this->cmdfunc = omap_nand_command;
787 this->write_buf = omap_nand_write_buf;
788 this->read_buf = omap_nand_read_buf;
789 this->verify_buf = omap_nand_verify_buf;
790 this->calculate_ecc = omap_nand_calculate_ecc;
791 this->correct_data = omap_nand_correct_data;
792 this->enable_hwecc = omap_nand_enable_hwecc;
793 this->scan_bbt = omap_nand_scan_bbt;
795 nand_write_reg(NND_PSC_CLK, 10);
796 /* Scan to find existance of the device */
797 if (nand_scan(omap_mtd, 1)) {
802 set_psc_regs(25, 15, 35);
803 if (this->page_shift == 11) {
804 this->cmdfunc = omap_nand_command_lp;
805 l = nand_read_reg(NND_CTRL);
806 l |= 1 << 4; /* Set the A8 bit in CTRL reg */
807 nand_write_reg(NND_CTRL, l);
808 this->eccmode = NAND_ECC_HW12_2048;
810 this->eccsize = 2048;
812 omap_mtd->eccsize = 2048;
813 nand_write_reg(NND_ECC_SELECT, 6);
816 this->options |= NAND_NO_AUTOINCR;
818 err = add_dynamic_parts(omap_mtd);
820 printk(KERN_ERR "omap-hw-nand: no partitions defined\n");
822 nand_release(omap_mtd);
830 clk_put(omap_nand_clk);
834 module_init(omap_nand_init);
839 static void __exit omap_nand_cleanup (void)
841 clk_disable(omap_nand_clk);
842 clk_put(omap_nand_clk);
843 nand_release(omap_mtd);
847 module_exit(omap_nand_cleanup);