drivers/mtd/nand/s3c2410.c

   1 /* linux/drivers/mtd/nand/s3c2410.c
   2  *
   3  * Copyright (c) 2004,2005 Simtec Electronics
   4  *      http://www.simtec.co.uk/products/SWLINUX/
   5  *      Ben Dooks <ben@simtec.co.uk>
   6  *
   7  * Samsung S3C2410/S3C240 NAND driver
   8  *
   9  * Changelog:
  10  *      21-Sep-2004  BJD  Initial version
  11  *      23-Sep-2004  BJD  Mulitple device support
  12  *      28-Sep-2004  BJD  Fixed ECC placement for Hardware mode
  13  *      12-Oct-2004  BJD  Fixed errors in use of platform data
  14  *      18-Feb-2005  BJD  Fix sparse errors
  15  *      14-Mar-2005  BJD  Applied tglx's code reduction patch
  16  *      02-May-2005  BJD  Fixed s3c2440 support
  17  *      02-May-2005  BJD  Reduced hwcontrol decode
  18  *      20-Jun-2005  BJD  Updated s3c2440 support, fixed timing bug
  19  *      08-Jul-2005  BJD  Fix OOPS when no platform data supplied
  20  *      20-Oct-2005  BJD  Fix timing calculation bug
  21  *
  22  * $Id: s3c2410.c,v 1.20 2005/11/07 11:14:31 gleixner Exp $
  23  *
  24  * This program is free software; you can redistribute it and/or modify
  25  * it under the terms of the GNU General Public License as published by
  26  * the Free Software Foundation; either version 2 of the License, or
  27  * (at your option) any later version.
  28  *
  29  * This program is distributed in the hope that it will be useful,
  30  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  31  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  32  * GNU General Public License for more details.
  33  *
  34  * You should have received a copy of the GNU General Public License
  35  * along with this program; if not, write to the Free Software
  36  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  37 */
  38
  39 #include <config/mtd/nand/s3c2410/hwecc.h>
  40 #include <config/mtd/nand/s3c2410/debug.h>
  41
  42 #ifdef CONFIG_MTD_NAND_S3C2410_DEBUG
  43 #define DEBUG
  44 #endif
  45
  46 #include <linux/module.h>
  47 #include <linux/types.h>
  48 #include <linux/init.h>
  49 #include <linux/kernel.h>
  50 #include <linux/string.h>
  51 #include <linux/ioport.h>
  52 #include <linux/platform_device.h>
  53 #include <linux/delay.h>
  54 #include <linux/err.h>
  55 #include <linux/slab.h>
  56 #include <linux/clk.h>
  57
  58 #include <linux/mtd/mtd.h>
  59 #include <linux/mtd/nand.h>
  60 #include <linux/mtd/nand_ecc.h>
  61 #include <linux/mtd/partitions.h>
  62
  63 #include <asm/io.h>
  64
  65 #include <asm/arch/regs-nand.h>
  66 #include <asm/arch/nand.h>
  67
  68 #define PFX "s3c2410-nand: "
  69
  70 #ifdef CONFIG_MTD_NAND_S3C2410_HWECC
  71 static int hardware_ecc = 1;
  72 #else
  73 static int hardware_ecc = 0;
  74 #endif
  75
  76 /* new oob placement block for use with hardware ecc generation
  77  */
  78
  79 static struct nand_oobinfo nand_hw_eccoob = {
  80         .useecc = MTD_NANDECC_AUTOPLACE,
  81         .eccbytes = 3,
  82         .eccpos = {0, 1, 2},
  83         .oobfree = {{8, 8}}
  84 };
  85
  86 /* controller and mtd information */
  87
  88 struct s3c2410_nand_info;
  89
  90 struct s3c2410_nand_mtd {
  91         struct mtd_info                 mtd;
  92         struct nand_chip                chip;
  93         struct s3c2410_nand_set         *set;
  94         struct s3c2410_nand_info        *info;
  95         int                             scan_res;
  96 };
  97
  98 /* overview of the s3c2410 nand state */
  99
 100 struct s3c2410_nand_info {
 101         /* mtd info */
 102         struct nand_hw_control          controller;
 103         struct s3c2410_nand_mtd         *mtds;
 104         struct s3c2410_platform_nand    *platform;
 105
 106         /* device info */
 107         struct device                   *device;
 108         struct resource                 *area;
 109         struct clk                      *clk;
 110         void __iomem                    *regs;
 111         int                             mtd_count;
 112
 113         unsigned char                   is_s3c2440;
 114 };
 115
 116 /* conversion functions */
 117
 118 static struct s3c2410_nand_mtd *s3c2410_nand_mtd_toours(struct mtd_info *mtd)
 119 {
 120         return container_of(mtd, struct s3c2410_nand_mtd, mtd);
 121 }
 122
 123 static struct s3c2410_nand_info *s3c2410_nand_mtd_toinfo(struct mtd_info *mtd)
 124 {
 125         return s3c2410_nand_mtd_toours(mtd)->info;
 126 }
 127
 128 static struct s3c2410_nand_info *to_nand_info(struct platform_device *dev)
 129 {
 130         return platform_get_drvdata(dev);
 131 }
 132
 133 static struct s3c2410_platform_nand *to_nand_plat(struct platform_device *dev)
 134 {
 135         return dev->dev.platform_data;
 136 }
 137
 138 /* timing calculations */
 139
 140 #define NS_IN_KHZ 1000000
 141
 142 static int s3c2410_nand_calc_rate(int wanted, unsigned long clk, int max)
 143 {
 144         int result;
 145
 146         result = (wanted * clk) / NS_IN_KHZ;
 147         result++;
 148
 149         pr_debug("result %d from %ld, %d\n", result, clk, wanted);
 150
 151         if (result > max) {
 152                 printk("%d ns is too big for current clock rate %ld\n", wanted, clk);
 153                 return -1;
 154         }
 155
 156         if (result < 1)
 157                 result = 1;
 158
 159         return result;
 160 }
 161
 162 #define to_ns(ticks,clk) (((ticks) * NS_IN_KHZ) / (unsigned int)(clk))
 163
 164 /* controller setup */
 165
 166 static int s3c2410_nand_inithw(struct s3c2410_nand_info *info, struct platform_device *pdev)
 167 {
 168         struct s3c2410_platform_nand *plat = to_nand_plat(pdev);
 169         unsigned long clkrate = clk_get_rate(info->clk);
 170         int tacls, twrph0, twrph1;
 171         unsigned long cfg;
 172
 173         /* calculate the timing information for the controller */
 174
 175         clkrate /= 1000;        /* turn clock into kHz for ease of use */
 176
 177         if (plat != NULL) {
 178                 tacls = s3c2410_nand_calc_rate(plat->tacls, clkrate, 4);
 179                 twrph0 = s3c2410_nand_calc_rate(plat->twrph0, clkrate, 8);
 180                 twrph1 = s3c2410_nand_calc_rate(plat->twrph1, clkrate, 8);
 181         } else {
 182                 /* default timings */
 183                 tacls = 4;
 184                 twrph0 = 8;
 185                 twrph1 = 8;
 186         }
 187
 188         if (tacls < 0 || twrph0 < 0 || twrph1 < 0) {
 189                 printk(KERN_ERR PFX "cannot get timings suitable for board\n");
 190                 return -EINVAL;
 191         }
 192
 193         printk(KERN_INFO PFX "Tacls=%d, %dns Twrph0=%d %dns, Twrph1=%d %dns\n",
 194                tacls, to_ns(tacls, clkrate), twrph0, to_ns(twrph0, clkrate), twrph1, to_ns(twrph1, clkrate));
 195
 196         if (!info->is_s3c2440) {
 197                 cfg = S3C2410_NFCONF_EN;
 198                 cfg |= S3C2410_NFCONF_TACLS(tacls - 1);
 199                 cfg |= S3C2410_NFCONF_TWRPH0(twrph0 - 1);
 200                 cfg |= S3C2410_NFCONF_TWRPH1(twrph1 - 1);
 201         } else {
 202                 cfg = S3C2440_NFCONF_TACLS(tacls - 1);
 203                 cfg |= S3C2440_NFCONF_TWRPH0(twrph0 - 1);
 204                 cfg |= S3C2440_NFCONF_TWRPH1(twrph1 - 1);
 205         }
 206
 207         pr_debug(PFX "NF_CONF is 0x%lx\n", cfg);
 208
 209         writel(cfg, info->regs + S3C2410_NFCONF);
 210         return 0;
 211 }
 212
 213 /* select chip */
 214
 215 static void s3c2410_nand_select_chip(struct mtd_info *mtd, int chip)
 216 {
 217         struct s3c2410_nand_info *info;
 218         struct s3c2410_nand_mtd *nmtd;
 219         struct nand_chip *this = mtd->priv;
 220         void __iomem *reg;
 221         unsigned long cur;
 222         unsigned long bit;
 223
 224         nmtd = this->priv;
 225         info = nmtd->info;
 226
 227         bit = (info->is_s3c2440) ? S3C2440_NFCONT_nFCE : S3C2410_NFCONF_nFCE;
 228         reg = info->regs + ((info->is_s3c2440) ? S3C2440_NFCONT : S3C2410_NFCONF);
 229
 230         cur = readl(reg);
 231
 232         if (chip == -1) {
 233                 cur |= bit;
 234         } else {
 235                 if (nmtd->set != NULL && chip > nmtd->set->nr_chips) {
 236                         printk(KERN_ERR PFX "chip %d out of range\n", chip);
 237                         return;
 238                 }
 239
 240                 if (info->platform != NULL) {
 241                         if (info->platform->select_chip != NULL)
 242                                 (info->platform->select_chip) (nmtd->set, chip);
 243                 }
 244
 245                 cur &= ~bit;
 246         }
 247
 248         writel(cur, reg);
 249 }
 250
 251 /* command and control functions
 252  *
 253  * Note, these all use tglx's method of changing the IO_ADDR_W field
 254  * to make the code simpler, and use the nand layer's code to issue the
 255  * command and address sequences via the proper IO ports.
 256  *
 257 */
 258
 259 static void s3c2410_nand_hwcontrol(struct mtd_info *mtd, int cmd)
 260 {
 261         struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
 262         struct nand_chip *chip = mtd->priv;
 263
 264         switch (cmd) {
 265         case NAND_CTL_SETNCE:
 266         case NAND_CTL_CLRNCE:
 267                 printk(KERN_ERR "%s: called for NCE\n", __FUNCTION__);
 268                 break;
 269
 270         case NAND_CTL_SETCLE:
 271                 chip->IO_ADDR_W = info->regs + S3C2410_NFCMD;
 272                 break;
 273
 274         case NAND_CTL_SETALE:
 275                 chip->IO_ADDR_W = info->regs + S3C2410_NFADDR;
 276                 break;
 277
 278                 /* NAND_CTL_CLRCLE: */
 279                 /* NAND_CTL_CLRALE: */
 280         default:
 281                 chip->IO_ADDR_W = info->regs + S3C2410_NFDATA;
 282                 break;
 283         }
 284 }
 285
 286 /* command and control functions */
 287
 288 static void s3c2440_nand_hwcontrol(struct mtd_info *mtd, int cmd)
 289 {
 290         struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
 291         struct nand_chip *chip = mtd->priv;
 292
 293         switch (cmd) {
 294         case NAND_CTL_SETNCE:
 295         case NAND_CTL_CLRNCE:
 296                 printk(KERN_ERR "%s: called for NCE\n", __FUNCTION__);
 297                 break;
 298
 299         case NAND_CTL_SETCLE:
 300                 chip->IO_ADDR_W = info->regs + S3C2440_NFCMD;
 301                 break;
 302
 303         case NAND_CTL_SETALE:
 304                 chip->IO_ADDR_W = info->regs + S3C2440_NFADDR;
 305                 break;
 306
 307                 /* NAND_CTL_CLRCLE: */
 308                 /* NAND_CTL_CLRALE: */
 309         default:
 310                 chip->IO_ADDR_W = info->regs + S3C2440_NFDATA;
 311                 break;
 312         }
 313 }
 314
 315 /* s3c2410_nand_devready()
 316  *
 317  * returns 0 if the nand is busy, 1 if it is ready
 318 */
 319
 320 static int s3c2410_nand_devready(struct mtd_info *mtd)
 321 {
 322         struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
 323
 324         if (info->is_s3c2440)
 325                 return readb(info->regs + S3C2440_NFSTAT) & S3C2440_NFSTAT_READY;
 326         return readb(info->regs + S3C2410_NFSTAT) & S3C2410_NFSTAT_BUSY;
 327 }
 328
 329 /* ECC handling functions */
 330
 331 static int s3c2410_nand_correct_data(struct mtd_info *mtd, u_char *dat, u_char *read_ecc, u_char *calc_ecc)
 332 {
 333         pr_debug("s3c2410_nand_correct_data(%p,%p,%p,%p)\n", mtd, dat, read_ecc, calc_ecc);
 334
 335         pr_debug("eccs: read %02x,%02x,%02x vs calc %02x,%02x,%02x\n",
 336                  read_ecc[0], read_ecc[1], read_ecc[2], calc_ecc[0], calc_ecc[1], calc_ecc[2]);
 337
 338         if (read_ecc[0] == calc_ecc[0] && read_ecc[1] == calc_ecc[1] && read_ecc[2] == calc_ecc[2])
 339                 return 0;
 340
 341         /* we curently have no method for correcting the error */
 342
 343         return -1;
 344 }
 345
 346 /* ECC functions
 347  *
 348  * These allow the s3c2410 and s3c2440 to use the controller's ECC
 349  * generator block to ECC the data as it passes through]
 350 */
 351
 352 static void s3c2410_nand_enable_hwecc(struct mtd_info *mtd, int mode)
 353 {
 354         struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
 355         unsigned long ctrl;
 356
 357         ctrl = readl(info->regs + S3C2410_NFCONF);
 358         ctrl |= S3C2410_NFCONF_INITECC;
 359         writel(ctrl, info->regs + S3C2410_NFCONF);
 360 }
 361
 362 static void s3c2440_nand_enable_hwecc(struct mtd_info *mtd, int mode)
 363 {
 364         struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
 365         unsigned long ctrl;
 366
 367         ctrl = readl(info->regs + S3C2440_NFCONT);
 368         writel(ctrl | S3C2440_NFCONT_INITECC, info->regs + S3C2440_NFCONT);
 369 }
 370
 371 static int s3c2410_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code)
 372 {
 373         struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
 374
 375         ecc_code[0] = readb(info->regs + S3C2410_NFECC + 0);
 376         ecc_code[1] = readb(info->regs + S3C2410_NFECC + 1);
 377         ecc_code[2] = readb(info->regs + S3C2410_NFECC + 2);
 378
 379         pr_debug("calculate_ecc: returning ecc %02x,%02x,%02x\n", ecc_code[0], ecc_code[1], ecc_code[2]);
 380
 381         return 0;
 382 }
 383
 384 static int s3c2440_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code)
 385 {
 386         struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
 387         unsigned long ecc = readl(info->regs + S3C2440_NFMECC0);
 388
 389         ecc_code[0] = ecc;
 390         ecc_code[1] = ecc >> 8;
 391         ecc_code[2] = ecc >> 16;
 392
 393         pr_debug("calculate_ecc: returning ecc %02x,%02x,%02x\n", ecc_code[0], ecc_code[1], ecc_code[2]);
 394
 395         return 0;
 396 }
 397
 398 /* over-ride the standard functions for a little more speed. We can
 399  * use read/write block to move the data buffers to/from the controller
 400 */
 401
 402 static void s3c2410_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
 403 {
 404         struct nand_chip *this = mtd->priv;
 405         readsb(this->IO_ADDR_R, buf, len);
 406 }
 407
 408 static void s3c2410_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
 409 {
 410         struct nand_chip *this = mtd->priv;
 411         writesb(this->IO_ADDR_W, buf, len);
 412 }
 413
 414 /* device management functions */
 415
 416 static int s3c2410_nand_remove(struct platform_device *pdev)
 417 {
 418         struct s3c2410_nand_info *info = to_nand_info(pdev);
 419
 420         platform_set_drvdata(pdev, NULL);
 421
 422         if (info == NULL)
 423                 return 0;
 424
 425         /* first thing we need to do is release all our mtds
 426          * and their partitions, then go through freeing the
 427          * resources used
 428          */
 429
 430         if (info->mtds != NULL) {
 431                 struct s3c2410_nand_mtd *ptr = info->mtds;
 432                 int mtdno;
 433
 434                 for (mtdno = 0; mtdno < info->mtd_count; mtdno++, ptr++) {
 435                         pr_debug("releasing mtd %d (%p)\n", mtdno, ptr);
 436                         nand_release(&ptr->mtd);
 437                 }
 438
 439                 kfree(info->mtds);
 440         }
 441
 442         /* free the common resources */
 443
 444         if (info->clk != NULL && !IS_ERR(info->clk)) {
 445                 clk_disable(info->clk);
 446                 clk_put(info->clk);
 447         }
 448
 449         if (info->regs != NULL) {
 450                 iounmap(info->regs);
 451                 info->regs = NULL;
 452         }
 453
 454         if (info->area != NULL) {
 455                 release_resource(info->area);
 456                 kfree(info->area);
 457                 info->area = NULL;
 458         }
 459
 460         kfree(info);
 461
 462         return 0;
 463 }
 464
 465 #ifdef CONFIG_MTD_PARTITIONS
 466 static int s3c2410_nand_add_partition(struct s3c2410_nand_info *info,
 467                                       struct s3c2410_nand_mtd *mtd,
 468                                       struct s3c2410_nand_set *set)
 469 {
 470         if (set == NULL)
 471                 return add_mtd_device(&mtd->mtd);
 472
 473         if (set->nr_partitions > 0 && set->partitions != NULL) {
 474                 return add_mtd_partitions(&mtd->mtd, set->partitions, set->nr_partitions);
 475         }
 476
 477         return add_mtd_device(&mtd->mtd);
 478 }
 479 #else
 480 static int s3c2410_nand_add_partition(struct s3c2410_nand_info *info,
 481                                       struct s3c2410_nand_mtd *mtd,
 482                                       struct s3c2410_nand_set *set)
 483 {
 484         return add_mtd_device(&mtd->mtd);
 485 }
 486 #endif
 487
 488 /* s3c2410_nand_init_chip
 489  *
 490  * init a single instance of an chip
 491 */
 492
 493 static void s3c2410_nand_init_chip(struct s3c2410_nand_info *info,
 494                                    struct s3c2410_nand_mtd *nmtd,
 495                                    struct s3c2410_nand_set *set)
 496 {
 497         struct nand_chip *chip = &nmtd->chip;
 498
 499         chip->IO_ADDR_R    = info->regs + S3C2410_NFDATA;
 500         chip->IO_ADDR_W    = info->regs + S3C2410_NFDATA;
 501         chip->hwcontrol    = s3c2410_nand_hwcontrol;
 502         chip->dev_ready    = s3c2410_nand_devready;
 503         chip->write_buf    = s3c2410_nand_write_buf;
 504         chip->read_buf     = s3c2410_nand_read_buf;
 505         chip->select_chip  = s3c2410_nand_select_chip;
 506         chip->chip_delay   = 50;
 507         chip->priv         = nmtd;
 508         chip->options      = 0;
 509         chip->controller   = &info->controller;
 510
 511         if (info->is_s3c2440) {
 512                 chip->IO_ADDR_R  = info->regs + S3C2440_NFDATA;
 513                 chip->IO_ADDR_W  = info->regs + S3C2440_NFDATA;
 514                 chip->hwcontrol  = s3c2440_nand_hwcontrol;
 515         }
 516
 517         nmtd->info         = info;
 518         nmtd->mtd.priv     = chip;
 519         nmtd->mtd.owner    = THIS_MODULE;
 520         nmtd->set          = set;
 521
 522         if (hardware_ecc) {
 523                 chip->correct_data  = s3c2410_nand_correct_data;
 524                 chip->enable_hwecc  = s3c2410_nand_enable_hwecc;
 525                 chip->calculate_ecc = s3c2410_nand_calculate_ecc;
 526                 chip->eccmode       = NAND_ECC_HW3_512;
 527                 chip->autooob       = &nand_hw_eccoob;
 528
 529                 if (info->is_s3c2440) {
 530                         chip->enable_hwecc  = s3c2440_nand_enable_hwecc;
 531                         chip->calculate_ecc = s3c2440_nand_calculate_ecc;
 532                 }
 533         } else {
 534                 chip->eccmode       = NAND_ECC_SOFT;
 535         }
 536 }
 537
 538 /* s3c2410_nand_probe
 539  *
 540  * called by device layer when it finds a device matching
 541  * one our driver can handled. This code checks to see if
 542  * it can allocate all necessary resources then calls the
 543  * nand layer to look for devices
 544 */
 545
 546 static int s3c24xx_nand_probe(struct platform_device *pdev, int is_s3c2440)
 547 {
 548         struct s3c2410_platform_nand *plat = to_nand_plat(pdev);
 549         struct s3c2410_nand_info *info;
 550         struct s3c2410_nand_mtd *nmtd;
 551         struct s3c2410_nand_set *sets;
 552         struct resource *res;
 553         int err = 0;
 554         int size;
 555         int nr_sets;
 556         int setno;
 557
 558         pr_debug("s3c2410_nand_probe(%p)\n", pdev);
 559
 560         info = kmalloc(sizeof(*info), GFP_KERNEL);
 561         if (info == NULL) {
 562                 dev_err(&pdev->dev, "no memory for flash info\n");
 563                 err = -ENOMEM;
 564                 goto exit_error;
 565         }
 566
 567         memzero(info, sizeof(*info));
 568         platform_set_drvdata(pdev, info);
 569
 570         spin_lock_init(&info->controller.lock);
 571         init_waitqueue_head(&info->controller.wq);
 572
 573         /* get the clock source and enable it */
 574
 575         info->clk = clk_get(&pdev->dev, "nand");
 576         if (IS_ERR(info->clk)) {
 577                 dev_err(&pdev->dev, "failed to get clock");
 578                 err = -ENOENT;
 579                 goto exit_error;
 580         }
 581
 582         clk_enable(info->clk);
 583
 584         /* allocate and map the resource */
 585
 586         /* currently we assume we have the one resource */
 587         res  = pdev->resource;
 588         size = res->end - res->start + 1;
 589
 590         info->area = request_mem_region(res->start, size, pdev->name);
 591
 592         if (info->area == NULL) {
 593                 dev_err(&pdev->dev, "cannot reserve register region\n");
 594                 err = -ENOENT;
 595                 goto exit_error;
 596         }
 597
 598         info->device     = &pdev->dev;
 599         info->platform   = plat;
 600         info->regs       = ioremap(res->start, size);
 601         info->is_s3c2440 = is_s3c2440;
 602
 603         if (info->regs == NULL) {
 604                 dev_err(&pdev->dev, "cannot reserve register region\n");
 605                 err = -EIO;
 606                 goto exit_error;
 607         }
 608
 609         dev_dbg(&pdev->dev, "mapped registers at %p\n", info->regs);
 610
 611         /* initialise the hardware */
 612
 613         err = s3c2410_nand_inithw(info, pdev);
 614         if (err != 0)
 615                 goto exit_error;
 616
 617         sets = (plat != NULL) ? plat->sets : NULL;
 618         nr_sets = (plat != NULL) ? plat->nr_sets : 1;
 619
 620         info->mtd_count = nr_sets;
 621
 622         /* allocate our information */
 623
 624         size = nr_sets * sizeof(*info->mtds);
 625         info->mtds = kmalloc(size, GFP_KERNEL);
 626         if (info->mtds == NULL) {
 627                 dev_err(&pdev->dev, "failed to allocate mtd storage\n");
 628                 err = -ENOMEM;
 629                 goto exit_error;
 630         }
 631
 632         memzero(info->mtds, size);
 633
 634         /* initialise all possible chips */
 635
 636         nmtd = info->mtds;
 637
 638         for (setno = 0; setno < nr_sets; setno++, nmtd++) {
 639                 pr_debug("initialising set %d (%p, info %p)\n", setno, nmtd, info);
 640
 641                 s3c2410_nand_init_chip(info, nmtd, sets);
 642
 643                 nmtd->scan_res = nand_scan(&nmtd->mtd, (sets) ? sets->nr_chips : 1);
 644
 645                 if (nmtd->scan_res == 0) {
 646                         s3c2410_nand_add_partition(info, nmtd, sets);
 647                 }
 648
 649                 if (sets != NULL)
 650                         sets++;
 651         }
 652
 653         pr_debug("initialised ok\n");
 654         return 0;
 655
 656  exit_error:
 657         s3c2410_nand_remove(pdev);
 658
 659         if (err == 0)
 660                 err = -EINVAL;
 661         return err;
 662 }
 663
 664 /* driver device registration */
 665
 666 static int s3c2410_nand_probe(struct platform_device *dev)
 667 {
 668         return s3c24xx_nand_probe(dev, 0);
 669 }
 670
 671 static int s3c2440_nand_probe(struct platform_device *dev)
 672 {
 673         return s3c24xx_nand_probe(dev, 1);
 674 }
 675
 676 static struct platform_driver s3c2410_nand_driver = {
 677         .probe          = s3c2410_nand_probe,
 678         .remove         = s3c2410_nand_remove,
 679         .driver         = {
 680                 .name   = "s3c2410-nand",
 681                 .owner  = THIS_MODULE,
 682         },
 683 };
 684
 685 static struct platform_driver s3c2440_nand_driver = {
 686         .probe          = s3c2440_nand_probe,
 687         .remove         = s3c2410_nand_remove,
 688         .driver         = {
 689                 .name   = "s3c2440-nand",
 690                 .owner  = THIS_MODULE,
 691         },
 692 };
 693
 694 static int __init s3c2410_nand_init(void)
 695 {
 696         printk("S3C24XX NAND Driver, (c) 2004 Simtec Electronics\n");
 697
 698         platform_driver_register(&s3c2440_nand_driver);
 699         return platform_driver_register(&s3c2410_nand_driver);
 700 }
 701
 702 static void __exit s3c2410_nand_exit(void)
 703 {
 704         platform_driver_unregister(&s3c2440_nand_driver);
 705         platform_driver_unregister(&s3c2410_nand_driver);
 706 }
 707
 708 module_init(s3c2410_nand_init);
 709 module_exit(s3c2410_nand_exit);
 710
 711 MODULE_LICENSE("GPL");
 712 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
 713 MODULE_DESCRIPTION("S3C24XX MTD NAND driver");