drivers/net/bnx2.c

   1 /* bnx2.c: Broadcom NX2 network driver.
   2  *
   3  * Copyright (c) 2004, 2005 Broadcom Corporation
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation.
   8  *
   9  * Written by: Michael Chan  (mchan@broadcom.com)
  10  */
  11
  12 #include "bnx2.h"
  13 #include "bnx2_fw.h"
  14
  15 #define DRV_MODULE_NAME         "bnx2"
  16 #define PFX DRV_MODULE_NAME     ": "
  17 #define DRV_MODULE_VERSION      "1.4.30"
  18 #define DRV_MODULE_RELDATE      "October 11, 2005"
  19
  20 #define RUN_AT(x) (jiffies + (x))
  21
  22 /* Time in jiffies before concluding the transmitter is hung. */
  23 #define TX_TIMEOUT  (5*HZ)
  24
  25 static char version[] __devinitdata =
  26         "Broadcom NetXtreme II Gigabit Ethernet Driver " DRV_MODULE_NAME " v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
  27
  28 MODULE_AUTHOR("Michael Chan <mchan@broadcom.com>");
  29 MODULE_DESCRIPTION("Broadcom NetXtreme II BCM5706/5708 Driver");
  30 MODULE_LICENSE("GPL");
  31 MODULE_VERSION(DRV_MODULE_VERSION);
  32
  33 static int disable_msi = 0;
  34
  35 module_param(disable_msi, int, 0);
  36 MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
  37
  38 typedef enum {
  39         BCM5706 = 0,
  40         NC370T,
  41         NC370I,
  42         BCM5706S,
  43         NC370F,
  44         BCM5708,
  45         BCM5708S,
  46 } board_t;
  47
  48 /* indexed by board_t, above */
  49 static struct {
  50         char *name;
  51 } board_info[] __devinitdata = {
  52         { "Broadcom NetXtreme II BCM5706 1000Base-T" },
  53         { "HP NC370T Multifunction Gigabit Server Adapter" },
  54         { "HP NC370i Multifunction Gigabit Server Adapter" },
  55         { "Broadcom NetXtreme II BCM5706 1000Base-SX" },
  56         { "HP NC370F Multifunction Gigabit Server Adapter" },
  57         { "Broadcom NetXtreme II BCM5708 1000Base-T" },
  58         { "Broadcom NetXtreme II BCM5708 1000Base-SX" },
  59         };
  60
  61 static struct pci_device_id bnx2_pci_tbl[] = {
  62         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
  63           PCI_VENDOR_ID_HP, 0x3101, 0, 0, NC370T },
  64         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
  65           PCI_VENDOR_ID_HP, 0x3106, 0, 0, NC370I },
  66         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
  67           PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706 },
  68         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708,
  69           PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708 },
  70         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
  71           PCI_VENDOR_ID_HP, 0x3102, 0, 0, NC370F },
  72         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
  73           PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706S },
  74         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708S,
  75           PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708S },
  76         { 0, }
  77 };
  78
  79 static struct flash_spec flash_table[] =
  80 {
  81         /* Slow EEPROM */
  82         {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400,
  83          1, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
  84          SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
  85          "EEPROM - slow"},
  86         /* Expansion entry 0001 */
  87         {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406,
  88          0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
  89          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
  90          "Entry 0001"},
  91         /* Saifun SA25F010 (non-buffered flash) */
  92         /* strap, cfg1, & write1 need updates */
  93         {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406,
  94          0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
  95          SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2,
  96          "Non-buffered flash (128kB)"},
  97         /* Saifun SA25F020 (non-buffered flash) */
  98         /* strap, cfg1, & write1 need updates */
  99         {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406,
 100          0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 101          SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4,
 102          "Non-buffered flash (256kB)"},
 103         /* Expansion entry 0100 */
 104         {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406,
 105          0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 106          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 107          "Entry 0100"},
 108         /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */
 109         {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406,
 110          0, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
 111          ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2,
 112          "Entry 0101: ST M45PE10 (128kB non-bufferred)"},
 113         /* Entry 0110: ST M45PE20 (non-buffered flash)*/
 114         {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406,
 115          0, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
 116          ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4,
 117          "Entry 0110: ST M45PE20 (256kB non-bufferred)"},
 118         /* Saifun SA25F005 (non-buffered flash) */
 119         /* strap, cfg1, & write1 need updates */
 120         {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406,
 121          0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 122          SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE,
 123          "Non-buffered flash (64kB)"},
 124         /* Fast EEPROM */
 125         {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400,
 126          1, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
 127          SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
 128          "EEPROM - fast"},
 129         /* Expansion entry 1001 */
 130         {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406,
 131          0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 132          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 133          "Entry 1001"},
 134         /* Expansion entry 1010 */
 135         {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406,
 136          0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 137          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 138          "Entry 1010"},
 139         /* ATMEL AT45DB011B (buffered flash) */
 140         {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400,
 141          1, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
 142          BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE,
 143          "Buffered flash (128kB)"},
 144         /* Expansion entry 1100 */
 145         {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406,
 146          0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 147          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 148          "Entry 1100"},
 149         /* Expansion entry 1101 */
 150         {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406,
 151          0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 152          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 153          "Entry 1101"},
 154         /* Ateml Expansion entry 1110 */
 155         {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400,
 156          1, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
 157          BUFFERED_FLASH_BYTE_ADDR_MASK, 0,
 158          "Entry 1110 (Atmel)"},
 159         /* ATMEL AT45DB021B (buffered flash) */
 160         {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400,
 161          1, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
 162          BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2,
 163          "Buffered flash (256kB)"},
 164 };
 165
 166 MODULE_DEVICE_TABLE(pci, bnx2_pci_tbl);
 167
 168 static inline u32 bnx2_tx_avail(struct bnx2 *bp)
 169 {
 170         u32 diff = TX_RING_IDX(bp->tx_prod) - TX_RING_IDX(bp->tx_cons);
 171
 172         if (diff > MAX_TX_DESC_CNT)
 173                 diff = (diff & MAX_TX_DESC_CNT) - 1;
 174         return (bp->tx_ring_size - diff);
 175 }
 176
 177 static u32
 178 bnx2_reg_rd_ind(struct bnx2 *bp, u32 offset)
 179 {
 180         REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
 181         return (REG_RD(bp, BNX2_PCICFG_REG_WINDOW));
 182 }
 183
 184 static void
 185 bnx2_reg_wr_ind(struct bnx2 *bp, u32 offset, u32 val)
 186 {
 187         REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
 188         REG_WR(bp, BNX2_PCICFG_REG_WINDOW, val);
 189 }
 190
 191 static void
 192 bnx2_ctx_wr(struct bnx2 *bp, u32 cid_addr, u32 offset, u32 val)
 193 {
 194         offset += cid_addr;
 195         REG_WR(bp, BNX2_CTX_DATA_ADR, offset);
 196         REG_WR(bp, BNX2_CTX_DATA, val);
 197 }
 198
 199 static int
 200 bnx2_read_phy(struct bnx2 *bp, u32 reg, u32 *val)
 201 {
 202         u32 val1;
 203         int i, ret;
 204
 205         if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
 206                 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
 207                 val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
 208
 209                 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
 210                 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
 211
 212                 udelay(40);
 213         }
 214
 215         val1 = (bp->phy_addr << 21) | (reg << 16) |
 216                 BNX2_EMAC_MDIO_COMM_COMMAND_READ | BNX2_EMAC_MDIO_COMM_DISEXT |
 217                 BNX2_EMAC_MDIO_COMM_START_BUSY;
 218         REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
 219
 220         for (i = 0; i < 50; i++) {
 221                 udelay(10);
 222
 223                 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
 224                 if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
 225                         udelay(5);
 226
 227                         val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
 228                         val1 &= BNX2_EMAC_MDIO_COMM_DATA;
 229
 230                         break;
 231                 }
 232         }
 233
 234         if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY) {
 235                 *val = 0x0;
 236                 ret = -EBUSY;
 237         }
 238         else {
 239                 *val = val1;
 240                 ret = 0;
 241         }
 242
 243         if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
 244                 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
 245                 val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
 246
 247                 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
 248                 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
 249
 250                 udelay(40);
 251         }
 252
 253         return ret;
 254 }
 255
 256 static int
 257 bnx2_write_phy(struct bnx2 *bp, u32 reg, u32 val)
 258 {
 259         u32 val1;
 260         int i, ret;
 261
 262         if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
 263                 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
 264                 val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
 265
 266                 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
 267                 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
 268
 269                 udelay(40);
 270         }
 271
 272         val1 = (bp->phy_addr << 21) | (reg << 16) | val |
 273                 BNX2_EMAC_MDIO_COMM_COMMAND_WRITE |
 274                 BNX2_EMAC_MDIO_COMM_START_BUSY | BNX2_EMAC_MDIO_COMM_DISEXT;
 275         REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
 276
 277         for (i = 0; i < 50; i++) {
 278                 udelay(10);
 279
 280                 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
 281                 if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
 282                         udelay(5);
 283                         break;
 284                 }
 285         }
 286
 287         if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)
 288                 ret = -EBUSY;
 289         else
 290                 ret = 0;
 291
 292         if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
 293                 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
 294                 val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
 295
 296                 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
 297                 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
 298
 299                 udelay(40);
 300         }
 301
 302         return ret;
 303 }
 304
 305 static void
 306 bnx2_disable_int(struct bnx2 *bp)
 307 {
 308         REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
 309                BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
 310         REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD);
 311 }
 312
 313 static void
 314 bnx2_enable_int(struct bnx2 *bp)
 315 {
 316         u32 val;
 317
 318         REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
 319                BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
 320                BNX2_PCICFG_INT_ACK_CMD_MASK_INT | bp->last_status_idx);
 321
 322         REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
 323                BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | bp->last_status_idx);
 324
 325         val = REG_RD(bp, BNX2_HC_COMMAND);
 326         REG_WR(bp, BNX2_HC_COMMAND, val | BNX2_HC_COMMAND_COAL_NOW);
 327 }
 328
 329 static void
 330 bnx2_disable_int_sync(struct bnx2 *bp)
 331 {
 332         atomic_inc(&bp->intr_sem);
 333         bnx2_disable_int(bp);
 334         synchronize_irq(bp->pdev->irq);
 335 }
 336
 337 static void
 338 bnx2_netif_stop(struct bnx2 *bp)
 339 {
 340         bnx2_disable_int_sync(bp);
 341         if (netif_running(bp->dev)) {
 342                 netif_poll_disable(bp->dev);
 343                 netif_tx_disable(bp->dev);
 344                 bp->dev->trans_start = jiffies; /* prevent tx timeout */
 345         }
 346 }
 347
 348 static void
 349 bnx2_netif_start(struct bnx2 *bp)
 350 {
 351         if (atomic_dec_and_test(&bp->intr_sem)) {
 352                 if (netif_running(bp->dev)) {
 353                         netif_wake_queue(bp->dev);
 354                         netif_poll_enable(bp->dev);
 355                         bnx2_enable_int(bp);
 356                 }
 357         }
 358 }
 359
 360 static void
 361 bnx2_free_mem(struct bnx2 *bp)
 362 {
 363         if (bp->stats_blk) {
 364                 pci_free_consistent(bp->pdev, sizeof(struct statistics_block),
 365                                     bp->stats_blk, bp->stats_blk_mapping);
 366                 bp->stats_blk = NULL;
 367         }
 368         if (bp->status_blk) {
 369                 pci_free_consistent(bp->pdev, sizeof(struct status_block),
 370                                     bp->status_blk, bp->status_blk_mapping);
 371                 bp->status_blk = NULL;
 372         }
 373         if (bp->tx_desc_ring) {
 374                 pci_free_consistent(bp->pdev,
 375                                     sizeof(struct tx_bd) * TX_DESC_CNT,
 376                                     bp->tx_desc_ring, bp->tx_desc_mapping);
 377                 bp->tx_desc_ring = NULL;
 378         }
 379         kfree(bp->tx_buf_ring);
 380         bp->tx_buf_ring = NULL;
 381         if (bp->rx_desc_ring) {
 382                 pci_free_consistent(bp->pdev,
 383                                     sizeof(struct rx_bd) * RX_DESC_CNT,
 384                                     bp->rx_desc_ring, bp->rx_desc_mapping);
 385                 bp->rx_desc_ring = NULL;
 386         }
 387         kfree(bp->rx_buf_ring);
 388         bp->rx_buf_ring = NULL;
 389 }
 390
 391 static int
 392 bnx2_alloc_mem(struct bnx2 *bp)
 393 {
 394         bp->tx_buf_ring = kmalloc(sizeof(struct sw_bd) * TX_DESC_CNT,
 395                                      GFP_KERNEL);
 396         if (bp->tx_buf_ring == NULL)
 397                 return -ENOMEM;
 398
 399         memset(bp->tx_buf_ring, 0, sizeof(struct sw_bd) * TX_DESC_CNT);
 400         bp->tx_desc_ring = pci_alloc_consistent(bp->pdev,
 401                                                 sizeof(struct tx_bd) *
 402                                                 TX_DESC_CNT,
 403                                                 &bp->tx_desc_mapping);
 404         if (bp->tx_desc_ring == NULL)
 405                 goto alloc_mem_err;
 406
 407         bp->rx_buf_ring = kmalloc(sizeof(struct sw_bd) * RX_DESC_CNT,
 408                                      GFP_KERNEL);
 409         if (bp->rx_buf_ring == NULL)
 410                 goto alloc_mem_err;
 411
 412         memset(bp->rx_buf_ring, 0, sizeof(struct sw_bd) * RX_DESC_CNT);
 413         bp->rx_desc_ring = pci_alloc_consistent(bp->pdev,
 414                                                 sizeof(struct rx_bd) *
 415                                                 RX_DESC_CNT,
 416                                                 &bp->rx_desc_mapping);
 417         if (bp->rx_desc_ring == NULL)
 418                 goto alloc_mem_err;
 419
 420         bp->status_blk = pci_alloc_consistent(bp->pdev,
 421                                               sizeof(struct status_block),
 422                                               &bp->status_blk_mapping);
 423         if (bp->status_blk == NULL)
 424                 goto alloc_mem_err;
 425
 426         memset(bp->status_blk, 0, sizeof(struct status_block));
 427
 428         bp->stats_blk = pci_alloc_consistent(bp->pdev,
 429                                              sizeof(struct statistics_block),
 430                                              &bp->stats_blk_mapping);
 431         if (bp->stats_blk == NULL)
 432                 goto alloc_mem_err;
 433
 434         memset(bp->stats_blk, 0, sizeof(struct statistics_block));
 435
 436         return 0;
 437
 438 alloc_mem_err:
 439         bnx2_free_mem(bp);
 440         return -ENOMEM;
 441 }
 442
 443 static void
 444 bnx2_report_fw_link(struct bnx2 *bp)
 445 {
 446         u32 fw_link_status = 0;
 447
 448         if (bp->link_up) {
 449                 u32 bmsr;
 450
 451                 switch (bp->line_speed) {
 452                 case SPEED_10:
 453                         if (bp->duplex == DUPLEX_HALF)
 454                                 fw_link_status = BNX2_LINK_STATUS_10HALF;
 455                         else
 456                                 fw_link_status = BNX2_LINK_STATUS_10FULL;
 457                         break;
 458                 case SPEED_100:
 459                         if (bp->duplex == DUPLEX_HALF)
 460                                 fw_link_status = BNX2_LINK_STATUS_100HALF;
 461                         else
 462                                 fw_link_status = BNX2_LINK_STATUS_100FULL;
 463                         break;
 464                 case SPEED_1000:
 465                         if (bp->duplex == DUPLEX_HALF)
 466                                 fw_link_status = BNX2_LINK_STATUS_1000HALF;
 467                         else
 468                                 fw_link_status = BNX2_LINK_STATUS_1000FULL;
 469                         break;
 470                 case SPEED_2500:
 471                         if (bp->duplex == DUPLEX_HALF)
 472                                 fw_link_status = BNX2_LINK_STATUS_2500HALF;
 473                         else
 474                                 fw_link_status = BNX2_LINK_STATUS_2500FULL;
 475                         break;
 476                 }
 477
 478                 fw_link_status |= BNX2_LINK_STATUS_LINK_UP;
 479
 480                 if (bp->autoneg) {
 481                         fw_link_status |= BNX2_LINK_STATUS_AN_ENABLED;
 482
 483                         bnx2_read_phy(bp, MII_BMSR, &bmsr);
 484                         bnx2_read_phy(bp, MII_BMSR, &bmsr);
 485
 486                         if (!(bmsr & BMSR_ANEGCOMPLETE) ||
 487                             bp->phy_flags & PHY_PARALLEL_DETECT_FLAG)
 488                                 fw_link_status |= BNX2_LINK_STATUS_PARALLEL_DET;
 489                         else
 490                                 fw_link_status |= BNX2_LINK_STATUS_AN_COMPLETE;
 491                 }
 492         }
 493         else
 494                 fw_link_status = BNX2_LINK_STATUS_LINK_DOWN;
 495
 496         REG_WR_IND(bp, bp->shmem_base + BNX2_LINK_STATUS, fw_link_status);
 497 }
 498
 499 static void
 500 bnx2_report_link(struct bnx2 *bp)
 501 {
 502         if (bp->link_up) {
 503                 netif_carrier_on(bp->dev);
 504                 printk(KERN_INFO PFX "%s NIC Link is Up, ", bp->dev->name);
 505
 506                 printk("%d Mbps ", bp->line_speed);
 507
 508                 if (bp->duplex == DUPLEX_FULL)
 509                         printk("full duplex");
 510                 else
 511                         printk("half duplex");
 512
 513                 if (bp->flow_ctrl) {
 514                         if (bp->flow_ctrl & FLOW_CTRL_RX) {
 515                                 printk(", receive ");
 516                                 if (bp->flow_ctrl & FLOW_CTRL_TX)
 517                                         printk("& transmit ");
 518                         }
 519                         else {
 520                                 printk(", transmit ");
 521                         }
 522                         printk("flow control ON");
 523                 }
 524                 printk("\n");
 525         }
 526         else {
 527                 netif_carrier_off(bp->dev);
 528                 printk(KERN_ERR PFX "%s NIC Link is Down\n", bp->dev->name);
 529         }
 530
 531         bnx2_report_fw_link(bp);
 532 }
 533
 534 static void
 535 bnx2_resolve_flow_ctrl(struct bnx2 *bp)
 536 {
 537         u32 local_adv, remote_adv;
 538
 539         bp->flow_ctrl = 0;
 540         if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) !=
 541                 (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) {
 542
 543                 if (bp->duplex == DUPLEX_FULL) {
 544                         bp->flow_ctrl = bp->req_flow_ctrl;
 545                 }
 546                 return;
 547         }
 548
 549         if (bp->duplex != DUPLEX_FULL) {
 550                 return;
 551         }
 552
 553         if ((bp->phy_flags & PHY_SERDES_FLAG) &&
 554             (CHIP_NUM(bp) == CHIP_NUM_5708)) {
 555                 u32 val;
 556
 557                 bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
 558                 if (val & BCM5708S_1000X_STAT1_TX_PAUSE)
 559                         bp->flow_ctrl |= FLOW_CTRL_TX;
 560                 if (val & BCM5708S_1000X_STAT1_RX_PAUSE)
 561                         bp->flow_ctrl |= FLOW_CTRL_RX;
 562                 return;
 563         }
 564
 565         bnx2_read_phy(bp, MII_ADVERTISE, &local_adv);
 566         bnx2_read_phy(bp, MII_LPA, &remote_adv);
 567
 568         if (bp->phy_flags & PHY_SERDES_FLAG) {
 569                 u32 new_local_adv = 0;
 570                 u32 new_remote_adv = 0;
 571
 572                 if (local_adv & ADVERTISE_1000XPAUSE)
 573                         new_local_adv |= ADVERTISE_PAUSE_CAP;
 574                 if (local_adv & ADVERTISE_1000XPSE_ASYM)
 575                         new_local_adv |= ADVERTISE_PAUSE_ASYM;
 576                 if (remote_adv & ADVERTISE_1000XPAUSE)
 577                         new_remote_adv |= ADVERTISE_PAUSE_CAP;
 578                 if (remote_adv & ADVERTISE_1000XPSE_ASYM)
 579                         new_remote_adv |= ADVERTISE_PAUSE_ASYM;
 580
 581                 local_adv = new_local_adv;
 582                 remote_adv = new_remote_adv;
 583         }
 584
 585         /* See Table 28B-3 of 802.3ab-1999 spec. */
 586         if (local_adv & ADVERTISE_PAUSE_CAP) {
 587                 if(local_adv & ADVERTISE_PAUSE_ASYM) {
 588                         if (remote_adv & ADVERTISE_PAUSE_CAP) {
 589                                 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
 590                         }
 591                         else if (remote_adv & ADVERTISE_PAUSE_ASYM) {
 592                                 bp->flow_ctrl = FLOW_CTRL_RX;
 593                         }
 594                 }
 595                 else {
 596                         if (remote_adv & ADVERTISE_PAUSE_CAP) {
 597                                 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
 598                         }
 599                 }
 600         }
 601         else if (local_adv & ADVERTISE_PAUSE_ASYM) {
 602                 if ((remote_adv & ADVERTISE_PAUSE_CAP) &&
 603                         (remote_adv & ADVERTISE_PAUSE_ASYM)) {
 604
 605                         bp->flow_ctrl = FLOW_CTRL_TX;
 606                 }
 607         }
 608 }
 609
 610 static int
 611 bnx2_5708s_linkup(struct bnx2 *bp)
 612 {
 613         u32 val;
 614
 615         bp->link_up = 1;
 616         bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
 617         switch (val & BCM5708S_1000X_STAT1_SPEED_MASK) {
 618                 case BCM5708S_1000X_STAT1_SPEED_10:
 619                         bp->line_speed = SPEED_10;
 620                         break;
 621                 case BCM5708S_1000X_STAT1_SPEED_100:
 622                         bp->line_speed = SPEED_100;
 623                         break;
 624                 case BCM5708S_1000X_STAT1_SPEED_1G:
 625                         bp->line_speed = SPEED_1000;
 626                         break;
 627                 case BCM5708S_1000X_STAT1_SPEED_2G5:
 628                         bp->line_speed = SPEED_2500;
 629                         break;
 630         }
 631         if (val & BCM5708S_1000X_STAT1_FD)
 632                 bp->duplex = DUPLEX_FULL;
 633         else
 634                 bp->duplex = DUPLEX_HALF;
 635
 636         return 0;
 637 }
 638
 639 static int
 640 bnx2_5706s_linkup(struct bnx2 *bp)
 641 {
 642         u32 bmcr, local_adv, remote_adv, common;
 643
 644         bp->link_up = 1;
 645         bp->line_speed = SPEED_1000;
 646
 647         bnx2_read_phy(bp, MII_BMCR, &bmcr);
 648         if (bmcr & BMCR_FULLDPLX) {
 649                 bp->duplex = DUPLEX_FULL;
 650         }
 651         else {
 652                 bp->duplex = DUPLEX_HALF;
 653         }
 654
 655         if (!(bmcr & BMCR_ANENABLE)) {
 656                 return 0;
 657         }
 658
 659         bnx2_read_phy(bp, MII_ADVERTISE, &local_adv);
 660         bnx2_read_phy(bp, MII_LPA, &remote_adv);
 661
 662         common = local_adv & remote_adv;
 663         if (common & (ADVERTISE_1000XHALF | ADVERTISE_1000XFULL)) {
 664
 665                 if (common & ADVERTISE_1000XFULL) {
 666                         bp->duplex = DUPLEX_FULL;
 667                 }
 668                 else {
 669                         bp->duplex = DUPLEX_HALF;
 670                 }
 671         }
 672
 673         return 0;
 674 }
 675
 676 static int
 677 bnx2_copper_linkup(struct bnx2 *bp)
 678 {
 679         u32 bmcr;
 680
 681         bnx2_read_phy(bp, MII_BMCR, &bmcr);
 682         if (bmcr & BMCR_ANENABLE) {
 683                 u32 local_adv, remote_adv, common;
 684
 685                 bnx2_read_phy(bp, MII_CTRL1000, &local_adv);
 686                 bnx2_read_phy(bp, MII_STAT1000, &remote_adv);
 687
 688                 common = local_adv & (remote_adv >> 2);
 689                 if (common & ADVERTISE_1000FULL) {
 690                         bp->line_speed = SPEED_1000;
 691                         bp->duplex = DUPLEX_FULL;
 692                 }
 693                 else if (common & ADVERTISE_1000HALF) {
 694                         bp->line_speed = SPEED_1000;
 695                         bp->duplex = DUPLEX_HALF;
 696                 }
 697                 else {
 698                         bnx2_read_phy(bp, MII_ADVERTISE, &local_adv);
 699                         bnx2_read_phy(bp, MII_LPA, &remote_adv);
 700
 701                         common = local_adv & remote_adv;
 702                         if (common & ADVERTISE_100FULL) {
 703                                 bp->line_speed = SPEED_100;
 704                                 bp->duplex = DUPLEX_FULL;
 705                         }
 706                         else if (common & ADVERTISE_100HALF) {
 707                                 bp->line_speed = SPEED_100;
 708                                 bp->duplex = DUPLEX_HALF;
 709                         }
 710                         else if (common & ADVERTISE_10FULL) {
 711                                 bp->line_speed = SPEED_10;
 712                                 bp->duplex = DUPLEX_FULL;
 713                         }
 714                         else if (common & ADVERTISE_10HALF) {
 715                                 bp->line_speed = SPEED_10;
 716                                 bp->duplex = DUPLEX_HALF;
 717                         }
 718                         else {
 719                                 bp->line_speed = 0;
 720                                 bp->link_up = 0;
 721                         }
 722                 }
 723         }
 724         else {
 725                 if (bmcr & BMCR_SPEED100) {
 726                         bp->line_speed = SPEED_100;
 727                 }
 728                 else {
 729                         bp->line_speed = SPEED_10;
 730                 }
 731                 if (bmcr & BMCR_FULLDPLX) {
 732                         bp->duplex = DUPLEX_FULL;
 733                 }
 734                 else {
 735                         bp->duplex = DUPLEX_HALF;
 736                 }
 737         }
 738
 739         return 0;
 740 }
 741
 742 static int
 743 bnx2_set_mac_link(struct bnx2 *bp)
 744 {
 745         u32 val;
 746
 747         REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x2620);
 748         if (bp->link_up && (bp->line_speed == SPEED_1000) &&
 749                 (bp->duplex == DUPLEX_HALF)) {
 750                 REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x26ff);
 751         }
 752
 753         /* Configure the EMAC mode register. */
 754         val = REG_RD(bp, BNX2_EMAC_MODE);
 755
 756         val &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
 757                 BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK |
 758                 BNX2_EMAC_MODE_25G);
 759
 760         if (bp->link_up) {
 761                 switch (bp->line_speed) {
 762                         case SPEED_10:
 763                                 if (CHIP_NUM(bp) == CHIP_NUM_5708) {
 764                                         val |= BNX2_EMAC_MODE_PORT_MII_10;
 765                                         break;
 766                                 }
 767                                 /* fall through */
 768                         case SPEED_100:
 769                                 val |= BNX2_EMAC_MODE_PORT_MII;
 770                                 break;
 771                         case SPEED_2500:
 772                                 val |= BNX2_EMAC_MODE_25G;
 773                                 /* fall through */
 774                         case SPEED_1000:
 775                                 val |= BNX2_EMAC_MODE_PORT_GMII;
 776                                 break;
 777                 }
 778         }
 779         else {
 780                 val |= BNX2_EMAC_MODE_PORT_GMII;
 781         }
 782
 783         /* Set the MAC to operate in the appropriate duplex mode. */
 784         if (bp->duplex == DUPLEX_HALF)
 785                 val |= BNX2_EMAC_MODE_HALF_DUPLEX;
 786         REG_WR(bp, BNX2_EMAC_MODE, val);
 787
 788         /* Enable/disable rx PAUSE. */
 789         bp->rx_mode &= ~BNX2_EMAC_RX_MODE_FLOW_EN;
 790
 791         if (bp->flow_ctrl & FLOW_CTRL_RX)
 792                 bp->rx_mode |= BNX2_EMAC_RX_MODE_FLOW_EN;
 793         REG_WR(bp, BNX2_EMAC_RX_MODE, bp->rx_mode);
 794
 795         /* Enable/disable tx PAUSE. */
 796         val = REG_RD(bp, BNX2_EMAC_TX_MODE);
 797         val &= ~BNX2_EMAC_TX_MODE_FLOW_EN;
 798
 799         if (bp->flow_ctrl & FLOW_CTRL_TX)
 800                 val |= BNX2_EMAC_TX_MODE_FLOW_EN;
 801         REG_WR(bp, BNX2_EMAC_TX_MODE, val);
 802
 803         /* Acknowledge the interrupt. */
 804         REG_WR(bp, BNX2_EMAC_STATUS, BNX2_EMAC_STATUS_LINK_CHANGE);
 805
 806         return 0;
 807 }
 808
 809 static int
 810 bnx2_set_link(struct bnx2 *bp)
 811 {
 812         u32 bmsr;
 813         u8 link_up;
 814
 815         if (bp->loopback == MAC_LOOPBACK) {
 816                 bp->link_up = 1;
 817                 return 0;
 818         }
 819
 820         link_up = bp->link_up;
 821
 822         bnx2_read_phy(bp, MII_BMSR, &bmsr);
 823         bnx2_read_phy(bp, MII_BMSR, &bmsr);
 824
 825         if ((bp->phy_flags & PHY_SERDES_FLAG) &&
 826             (CHIP_NUM(bp) == CHIP_NUM_5706)) {
 827                 u32 val;
 828
 829                 val = REG_RD(bp, BNX2_EMAC_STATUS);
 830                 if (val & BNX2_EMAC_STATUS_LINK)
 831                         bmsr |= BMSR_LSTATUS;
 832                 else
 833                         bmsr &= ~BMSR_LSTATUS;
 834         }
 835
 836         if (bmsr & BMSR_LSTATUS) {
 837                 bp->link_up = 1;
 838
 839                 if (bp->phy_flags & PHY_SERDES_FLAG) {
 840                         if (CHIP_NUM(bp) == CHIP_NUM_5706)
 841                                 bnx2_5706s_linkup(bp);
 842                         else if (CHIP_NUM(bp) == CHIP_NUM_5708)
 843                                 bnx2_5708s_linkup(bp);
 844                 }
 845                 else {
 846                         bnx2_copper_linkup(bp);
 847                 }
 848                 bnx2_resolve_flow_ctrl(bp);
 849         }
 850         else {
 851                 if ((bp->phy_flags & PHY_SERDES_FLAG) &&
 852                         (bp->autoneg & AUTONEG_SPEED)) {
 853
 854                         u32 bmcr;
 855
 856                         bnx2_read_phy(bp, MII_BMCR, &bmcr);
 857                         if (!(bmcr & BMCR_ANENABLE)) {
 858                                 bnx2_write_phy(bp, MII_BMCR, bmcr |
 859                                         BMCR_ANENABLE);
 860                         }
 861                 }
 862                 bp->phy_flags &= ~PHY_PARALLEL_DETECT_FLAG;
 863                 bp->link_up = 0;
 864         }
 865
 866         if (bp->link_up != link_up) {
 867                 bnx2_report_link(bp);
 868         }
 869
 870         bnx2_set_mac_link(bp);
 871
 872         return 0;
 873 }
 874
 875 static int
 876 bnx2_reset_phy(struct bnx2 *bp)
 877 {
 878         int i;
 879         u32 reg;
 880
 881         bnx2_write_phy(bp, MII_BMCR, BMCR_RESET);
 882
 883 #define PHY_RESET_MAX_WAIT 100
 884         for (i = 0; i < PHY_RESET_MAX_WAIT; i++) {
 885                 udelay(10);
 886
 887                 bnx2_read_phy(bp, MII_BMCR, &reg);
 888                 if (!(reg & BMCR_RESET)) {
 889                         udelay(20);
 890                         break;
 891                 }
 892         }
 893         if (i == PHY_RESET_MAX_WAIT) {
 894                 return -EBUSY;
 895         }
 896         return 0;
 897 }
 898
 899 static u32
 900 bnx2_phy_get_pause_adv(struct bnx2 *bp)
 901 {
 902         u32 adv = 0;
 903
 904         if ((bp->req_flow_ctrl & (FLOW_CTRL_RX | FLOW_CTRL_TX)) ==
 905                 (FLOW_CTRL_RX | FLOW_CTRL_TX)) {
 906
 907                 if (bp->phy_flags & PHY_SERDES_FLAG) {
 908                         adv = ADVERTISE_1000XPAUSE;
 909                 }
 910                 else {
 911                         adv = ADVERTISE_PAUSE_CAP;
 912                 }
 913         }
 914         else if (bp->req_flow_ctrl & FLOW_CTRL_TX) {
 915                 if (bp->phy_flags & PHY_SERDES_FLAG) {
 916                         adv = ADVERTISE_1000XPSE_ASYM;
 917                 }
 918                 else {
 919                         adv = ADVERTISE_PAUSE_ASYM;
 920                 }
 921         }
 922         else if (bp->req_flow_ctrl & FLOW_CTRL_RX) {
 923                 if (bp->phy_flags & PHY_SERDES_FLAG) {
 924                         adv = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
 925                 }
 926                 else {
 927                         adv = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
 928                 }
 929         }
 930         return adv;
 931 }
 932
 933 static int
 934 bnx2_setup_serdes_phy(struct bnx2 *bp)
 935 {
 936         u32 adv, bmcr, up1;
 937         u32 new_adv = 0;
 938
 939         if (!(bp->autoneg & AUTONEG_SPEED)) {
 940                 u32 new_bmcr;
 941                 int force_link_down = 0;
 942
 943                 if (CHIP_NUM(bp) == CHIP_NUM_5708) {
 944                         bnx2_read_phy(bp, BCM5708S_UP1, &up1);
 945                         if (up1 & BCM5708S_UP1_2G5) {
 946                                 up1 &= ~BCM5708S_UP1_2G5;
 947                                 bnx2_write_phy(bp, BCM5708S_UP1, up1);
 948                                 force_link_down = 1;
 949                         }
 950                 }
 951
 952                 bnx2_read_phy(bp, MII_ADVERTISE, &adv);
 953                 adv &= ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF);
 954
 955                 bnx2_read_phy(bp, MII_BMCR, &bmcr);
 956                 new_bmcr = bmcr & ~BMCR_ANENABLE;
 957                 new_bmcr |= BMCR_SPEED1000;
 958                 if (bp->req_duplex == DUPLEX_FULL) {
 959                         adv |= ADVERTISE_1000XFULL;
 960                         new_bmcr |= BMCR_FULLDPLX;
 961                 }
 962                 else {
 963                         adv |= ADVERTISE_1000XHALF;
 964                         new_bmcr &= ~BMCR_FULLDPLX;
 965                 }
 966                 if ((new_bmcr != bmcr) || (force_link_down)) {
 967                         /* Force a link down visible on the other side */
 968                         if (bp->link_up) {
 969                                 bnx2_write_phy(bp, MII_ADVERTISE, adv &
 970                                                ~(ADVERTISE_1000XFULL |
 971                                                  ADVERTISE_1000XHALF));
 972                                 bnx2_write_phy(bp, MII_BMCR, bmcr |
 973                                         BMCR_ANRESTART | BMCR_ANENABLE);
 974
 975                                 bp->link_up = 0;
 976                                 netif_carrier_off(bp->dev);
 977                                 bnx2_write_phy(bp, MII_BMCR, new_bmcr);
 978                         }
 979                         bnx2_write_phy(bp, MII_ADVERTISE, adv);
 980                         bnx2_write_phy(bp, MII_BMCR, new_bmcr);
 981                 }
 982                 return 0;
 983         }
 984
 985         if (bp->phy_flags & PHY_2_5G_CAPABLE_FLAG) {
 986                 bnx2_read_phy(bp, BCM5708S_UP1, &up1);
 987                 up1 |= BCM5708S_UP1_2G5;
 988                 bnx2_write_phy(bp, BCM5708S_UP1, up1);
 989         }
 990
 991         if (bp->advertising & ADVERTISED_1000baseT_Full)
 992                 new_adv |= ADVERTISE_1000XFULL;
 993
 994         new_adv |= bnx2_phy_get_pause_adv(bp);
 995
 996         bnx2_read_phy(bp, MII_ADVERTISE, &adv);
 997         bnx2_read_phy(bp, MII_BMCR, &bmcr);
 998
 999         bp->serdes_an_pending = 0;
1000         if ((adv != new_adv) || ((bmcr & BMCR_ANENABLE) == 0)) {
1001                 /* Force a link down visible on the other side */
1002                 if (bp->link_up) {
1003                         int i;
1004
1005                         bnx2_write_phy(bp, MII_BMCR, BMCR_LOOPBACK);
1006                         for (i = 0; i < 110; i++) {
1007                                 udelay(100);
1008                         }
1009                 }
1010
1011                 bnx2_write_phy(bp, MII_ADVERTISE, new_adv);
1012                 bnx2_write_phy(bp, MII_BMCR, bmcr | BMCR_ANRESTART |
1013                         BMCR_ANENABLE);
1014                 if (CHIP_NUM(bp) == CHIP_NUM_5706) {
1015                         /* Speed up link-up time when the link partner
1016                          * does not autonegotiate which is very common
1017                          * in blade servers. Some blade servers use
1018                          * IPMI for kerboard input and it's important
1019                          * to minimize link disruptions. Autoneg. involves
1020                          * exchanging base pages plus 3 next pages and
1021                          * normally completes in about 120 msec.
1022                          */
1023                         bp->current_interval = SERDES_AN_TIMEOUT;
1024                         bp->serdes_an_pending = 1;
1025                         mod_timer(&bp->timer, jiffies + bp->current_interval);
1026                 }
1027         }
1028
1029         return 0;
1030 }
1031
1032 #define ETHTOOL_ALL_FIBRE_SPEED                                         \
1033         (ADVERTISED_1000baseT_Full)
1034
1035 #define ETHTOOL_ALL_COPPER_SPEED                                        \
1036         (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |            \
1037         ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |           \
1038         ADVERTISED_1000baseT_Full)
1039
1040 #define PHY_ALL_10_100_SPEED (ADVERTISE_10HALF | ADVERTISE_10FULL | \
1041         ADVERTISE_100HALF | ADVERTISE_100FULL | ADVERTISE_CSMA)
1042
1043 #define PHY_ALL_1000_SPEED (ADVERTISE_1000HALF | ADVERTISE_1000FULL)
1044
1045 static int
1046 bnx2_setup_copper_phy(struct bnx2 *bp)
1047 {
1048         u32 bmcr;
1049         u32 new_bmcr;
1050
1051         bnx2_read_phy(bp, MII_BMCR, &bmcr);
1052
1053         if (bp->autoneg & AUTONEG_SPEED) {
1054                 u32 adv_reg, adv1000_reg;
1055                 u32 new_adv_reg = 0;
1056                 u32 new_adv1000_reg = 0;
1057
1058                 bnx2_read_phy(bp, MII_ADVERTISE, &adv_reg);
1059                 adv_reg &= (PHY_ALL_10_100_SPEED | ADVERTISE_PAUSE_CAP |
1060                         ADVERTISE_PAUSE_ASYM);
1061
1062                 bnx2_read_phy(bp, MII_CTRL1000, &adv1000_reg);
1063                 adv1000_reg &= PHY_ALL_1000_SPEED;
1064
1065                 if (bp->advertising & ADVERTISED_10baseT_Half)
1066                         new_adv_reg |= ADVERTISE_10HALF;
1067                 if (bp->advertising & ADVERTISED_10baseT_Full)
1068                         new_adv_reg |= ADVERTISE_10FULL;
1069                 if (bp->advertising & ADVERTISED_100baseT_Half)
1070                         new_adv_reg |= ADVERTISE_100HALF;
1071                 if (bp->advertising & ADVERTISED_100baseT_Full)
1072                         new_adv_reg |= ADVERTISE_100FULL;
1073                 if (bp->advertising & ADVERTISED_1000baseT_Full)
1074                         new_adv1000_reg |= ADVERTISE_1000FULL;
1075
1076                 new_adv_reg |= ADVERTISE_CSMA;
1077
1078                 new_adv_reg |= bnx2_phy_get_pause_adv(bp);
1079
1080                 if ((adv1000_reg != new_adv1000_reg) ||
1081                         (adv_reg != new_adv_reg) ||
1082                         ((bmcr & BMCR_ANENABLE) == 0)) {
1083
1084                         bnx2_write_phy(bp, MII_ADVERTISE, new_adv_reg);
1085                         bnx2_write_phy(bp, MII_CTRL1000, new_adv1000_reg);
1086                         bnx2_write_phy(bp, MII_BMCR, BMCR_ANRESTART |
1087                                 BMCR_ANENABLE);
1088                 }
1089                 else if (bp->link_up) {
1090                         /* Flow ctrl may have changed from auto to forced */
1091                         /* or vice-versa. */
1092
1093                         bnx2_resolve_flow_ctrl(bp);
1094                         bnx2_set_mac_link(bp);
1095                 }
1096                 return 0;
1097         }
1098
1099         new_bmcr = 0;
1100         if (bp->req_line_speed == SPEED_100) {
1101                 new_bmcr |= BMCR_SPEED100;
1102         }
1103         if (bp->req_duplex == DUPLEX_FULL) {
1104                 new_bmcr |= BMCR_FULLDPLX;
1105         }
1106         if (new_bmcr != bmcr) {
1107                 u32 bmsr;
1108                 int i = 0;
1109
1110                 bnx2_read_phy(bp, MII_BMSR, &bmsr);
1111                 bnx2_read_phy(bp, MII_BMSR, &bmsr);
1112
1113                 if (bmsr & BMSR_LSTATUS) {
1114                         /* Force link down */
1115                         bnx2_write_phy(bp, MII_BMCR, BMCR_LOOPBACK);
1116                         do {
1117                                 udelay(100);
1118                                 bnx2_read_phy(bp, MII_BMSR, &bmsr);
1119                                 bnx2_read_phy(bp, MII_BMSR, &bmsr);
1120                                 i++;
1121                         } while ((bmsr & BMSR_LSTATUS) && (i < 620));
1122                 }
1123
1124                 bnx2_write_phy(bp, MII_BMCR, new_bmcr);
1125
1126                 /* Normally, the new speed is setup after the link has
1127                  * gone down and up again. In some cases, link will not go
1128                  * down so we need to set up the new speed here.
1129                  */
1130                 if (bmsr & BMSR_LSTATUS) {
1131                         bp->line_speed = bp->req_line_speed;
1132                         bp->duplex = bp->req_duplex;
1133                         bnx2_resolve_flow_ctrl(bp);
1134                         bnx2_set_mac_link(bp);
1135                 }
1136         }
1137         return 0;
1138 }
1139
1140 static int
1141 bnx2_setup_phy(struct bnx2 *bp)
1142 {
1143         if (bp->loopback == MAC_LOOPBACK)
1144                 return 0;
1145
1146         if (bp->phy_flags & PHY_SERDES_FLAG) {
1147                 return (bnx2_setup_serdes_phy(bp));
1148         }
1149         else {
1150                 return (bnx2_setup_copper_phy(bp));
1151         }
1152 }
1153
1154 static int
1155 bnx2_init_5708s_phy(struct bnx2 *bp)
1156 {
1157         u32 val;
1158
1159         bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG3);
1160         bnx2_write_phy(bp, BCM5708S_DIG_3_0, BCM5708S_DIG_3_0_USE_IEEE);
1161         bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
1162
1163         bnx2_read_phy(bp, BCM5708S_1000X_CTL1, &val);
1164         val |= BCM5708S_1000X_CTL1_FIBER_MODE | BCM5708S_1000X_CTL1_AUTODET_EN;
1165         bnx2_write_phy(bp, BCM5708S_1000X_CTL1, val);
1166
1167         bnx2_read_phy(bp, BCM5708S_1000X_CTL2, &val);
1168         val |= BCM5708S_1000X_CTL2_PLLEL_DET_EN;
1169         bnx2_write_phy(bp, BCM5708S_1000X_CTL2, val);
1170
1171         if (bp->phy_flags & PHY_2_5G_CAPABLE_FLAG) {
1172                 bnx2_read_phy(bp, BCM5708S_UP1, &val);
1173                 val |= BCM5708S_UP1_2G5;
1174                 bnx2_write_phy(bp, BCM5708S_UP1, val);
1175         }
1176
1177         if ((CHIP_ID(bp) == CHIP_ID_5708_A0) ||
1178             (CHIP_ID(bp) == CHIP_ID_5708_B0) ||
1179             (CHIP_ID(bp) == CHIP_ID_5708_B1)) {
1180                 /* increase tx signal amplitude */
1181                 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
1182                                BCM5708S_BLK_ADDR_TX_MISC);
1183                 bnx2_read_phy(bp, BCM5708S_TX_ACTL1, &val);
1184                 val &= ~BCM5708S_TX_ACTL1_DRIVER_VCM;
1185                 bnx2_write_phy(bp, BCM5708S_TX_ACTL1, val);
1186                 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
1187         }
1188
1189         val = REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_HW_CFG_CONFIG) &
1190               BNX2_PORT_HW_CFG_CFG_TXCTL3_MASK;
1191
1192         if (val) {
1193                 u32 is_backplane;
1194
1195                 is_backplane = REG_RD_IND(bp, bp->shmem_base +
1196                                           BNX2_SHARED_HW_CFG_CONFIG);
1197                 if (is_backplane & BNX2_SHARED_HW_CFG_PHY_BACKPLANE) {
1198                         bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
1199                                        BCM5708S_BLK_ADDR_TX_MISC);
1200                         bnx2_write_phy(bp, BCM5708S_TX_ACTL3, val);
1201                         bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
1202                                        BCM5708S_BLK_ADDR_DIG);
1203                 }
1204         }
1205         return 0;
1206 }
1207
1208 static int
1209 bnx2_init_5706s_phy(struct bnx2 *bp)
1210 {
1211         bp->phy_flags &= ~PHY_PARALLEL_DETECT_FLAG;
1212
1213         if (CHIP_NUM(bp) == CHIP_NUM_5706) {
1214                 REG_WR(bp, BNX2_MISC_UNUSED0, 0x300);
1215         }
1216
1217         if (bp->dev->mtu > 1500) {
1218                 u32 val;
1219
1220                 /* Set extended packet length bit */
1221                 bnx2_write_phy(bp, 0x18, 0x7);
1222                 bnx2_read_phy(bp, 0x18, &val);
1223                 bnx2_write_phy(bp, 0x18, (val & 0xfff8) | 0x4000);
1224
1225                 bnx2_write_phy(bp, 0x1c, 0x6c00);
1226                 bnx2_read_phy(bp, 0x1c, &val);
1227                 bnx2_write_phy(bp, 0x1c, (val & 0x3ff) | 0xec02);
1228         }
1229         else {
1230                 u32 val;
1231
1232                 bnx2_write_phy(bp, 0x18, 0x7);
1233                 bnx2_read_phy(bp, 0x18, &val);
1234                 bnx2_write_phy(bp, 0x18, val & ~0x4007);
1235
1236                 bnx2_write_phy(bp, 0x1c, 0x6c00);
1237                 bnx2_read_phy(bp, 0x1c, &val);
1238                 bnx2_write_phy(bp, 0x1c, (val & 0x3fd) | 0xec00);
1239         }
1240
1241         return 0;
1242 }
1243
1244 static int
1245 bnx2_init_copper_phy(struct bnx2 *bp)
1246 {
1247         u32 val;
1248
1249         bp->phy_flags |= PHY_CRC_FIX_FLAG;
1250
1251         if (bp->phy_flags & PHY_CRC_FIX_FLAG) {
1252                 bnx2_write_phy(bp, 0x18, 0x0c00);
1253                 bnx2_write_phy(bp, 0x17, 0x000a);
1254                 bnx2_write_phy(bp, 0x15, 0x310b);
1255                 bnx2_write_phy(bp, 0x17, 0x201f);
1256                 bnx2_write_phy(bp, 0x15, 0x9506);
1257                 bnx2_write_phy(bp, 0x17, 0x401f);
1258                 bnx2_write_phy(bp, 0x15, 0x14e2);
1259                 bnx2_write_phy(bp, 0x18, 0x0400);
1260         }
1261
1262         if (bp->dev->mtu > 1500) {
1263                 /* Set extended packet length bit */
1264                 bnx2_write_phy(bp, 0x18, 0x7);
1265                 bnx2_read_phy(bp, 0x18, &val);
1266                 bnx2_write_phy(bp, 0x18, val | 0x4000);
1267
1268                 bnx2_read_phy(bp, 0x10, &val);
1269                 bnx2_write_phy(bp, 0x10, val | 0x1);
1270         }
1271         else {
1272                 bnx2_write_phy(bp, 0x18, 0x7);
1273                 bnx2_read_phy(bp, 0x18, &val);
1274                 bnx2_write_phy(bp, 0x18, val & ~0x4007);
1275
1276                 bnx2_read_phy(bp, 0x10, &val);
1277                 bnx2_write_phy(bp, 0x10, val & ~0x1);
1278         }
1279
1280         /* ethernet@wirespeed */
1281         bnx2_write_phy(bp, 0x18, 0x7007);
1282         bnx2_read_phy(bp, 0x18, &val);
1283         bnx2_write_phy(bp, 0x18, val | (1 << 15) | (1 << 4));
1284         return 0;
1285 }
1286
1287
1288 static int
1289 bnx2_init_phy(struct bnx2 *bp)
1290 {
1291         u32 val;
1292         int rc = 0;
1293
1294         bp->phy_flags &= ~PHY_INT_MODE_MASK_FLAG;
1295         bp->phy_flags |= PHY_INT_MODE_LINK_READY_FLAG;
1296
1297         REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
1298
1299         bnx2_reset_phy(bp);
1300
1301         bnx2_read_phy(bp, MII_PHYSID1, &val);
1302         bp->phy_id = val << 16;
1303         bnx2_read_phy(bp, MII_PHYSID2, &val);
1304         bp->phy_id |= val & 0xffff;
1305
1306         if (bp->phy_flags & PHY_SERDES_FLAG) {
1307                 if (CHIP_NUM(bp) == CHIP_NUM_5706)
1308                         rc = bnx2_init_5706s_phy(bp);
1309                 else if (CHIP_NUM(bp) == CHIP_NUM_5708)
1310                         rc = bnx2_init_5708s_phy(bp);
1311         }
1312         else {
1313                 rc = bnx2_init_copper_phy(bp);
1314         }
1315
1316         bnx2_setup_phy(bp);
1317
1318         return rc;
1319 }
1320
1321 static int
1322 bnx2_set_mac_loopback(struct bnx2 *bp)
1323 {
1324         u32 mac_mode;
1325
1326         mac_mode = REG_RD(bp, BNX2_EMAC_MODE);
1327         mac_mode &= ~BNX2_EMAC_MODE_PORT;
1328         mac_mode |= BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK;
1329         REG_WR(bp, BNX2_EMAC_MODE, mac_mode);
1330         bp->link_up = 1;
1331         return 0;
1332 }
1333
1334 static int
1335 bnx2_fw_sync(struct bnx2 *bp, u32 msg_data, int silent)
1336 {
1337         int i;
1338         u32 val;
1339
1340         bp->fw_wr_seq++;
1341         msg_data |= bp->fw_wr_seq;
1342
1343         REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_MB, msg_data);
1344
1345         /* wait for an acknowledgement. */
1346         for (i = 0; i < (FW_ACK_TIME_OUT_MS / 10); i++) {
1347                 msleep(10);
1348
1349                 val = REG_RD_IND(bp, bp->shmem_base + BNX2_FW_MB);
1350
1351                 if ((val & BNX2_FW_MSG_ACK) == (msg_data & BNX2_DRV_MSG_SEQ))
1352                         break;
1353         }
1354         if ((msg_data & BNX2_DRV_MSG_DATA) == BNX2_DRV_MSG_DATA_WAIT0)
1355                 return 0;
1356
1357         /* If we timed out, inform the firmware that this is the case. */
1358         if ((val & BNX2_FW_MSG_ACK) != (msg_data & BNX2_DRV_MSG_SEQ)) {
1359                 if (!silent)
1360                         printk(KERN_ERR PFX "fw sync timeout, reset code = "
1361                                             "%x\n", msg_data);
1362
1363                 msg_data &= ~BNX2_DRV_MSG_CODE;
1364                 msg_data |= BNX2_DRV_MSG_CODE_FW_TIMEOUT;
1365
1366                 REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_MB, msg_data);
1367
1368                 return -EBUSY;
1369         }
1370
1371         if ((val & BNX2_FW_MSG_STATUS_MASK) != BNX2_FW_MSG_STATUS_OK)
1372                 return -EIO;
1373
1374         return 0;
1375 }
1376
1377 static void
1378 bnx2_init_context(struct bnx2 *bp)
1379 {
1380         u32 vcid;
1381
1382         vcid = 96;
1383         while (vcid) {
1384                 u32 vcid_addr, pcid_addr, offset;
1385
1386                 vcid--;
1387
1388                 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
1389                         u32 new_vcid;
1390
1391                         vcid_addr = GET_PCID_ADDR(vcid);
1392                         if (vcid & 0x8) {
1393                                 new_vcid = 0x60 + (vcid & 0xf0) + (vcid & 0x7);
1394                         }
1395                         else {
1396                                 new_vcid = vcid;
1397                         }
1398                         pcid_addr = GET_PCID_ADDR(new_vcid);
1399                 }
1400                 else {
1401                         vcid_addr = GET_CID_ADDR(vcid);
1402                         pcid_addr = vcid_addr;
1403                 }
1404
1405                 REG_WR(bp, BNX2_CTX_VIRT_ADDR, 0x00);
1406                 REG_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr);
1407
1408                 /* Zero out the context. */
1409                 for (offset = 0; offset < PHY_CTX_SIZE; offset += 4) {
1410                         CTX_WR(bp, 0x00, offset, 0);
1411                 }
1412
1413                 REG_WR(bp, BNX2_CTX_VIRT_ADDR, vcid_addr);
1414                 REG_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr);
1415         }
1416 }
1417
1418 static int
1419 bnx2_alloc_bad_rbuf(struct bnx2 *bp)
1420 {
1421         u16 *good_mbuf;
1422         u32 good_mbuf_cnt;
1423         u32 val;
1424
1425         good_mbuf = kmalloc(512 * sizeof(u16), GFP_KERNEL);
1426         if (good_mbuf == NULL) {
1427                 printk(KERN_ERR PFX "Failed to allocate memory in "
1428                                     "bnx2_alloc_bad_rbuf\n");
1429                 return -ENOMEM;
1430         }
1431
1432         REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
1433                 BNX2_MISC_ENABLE_SET_BITS_RX_MBUF_ENABLE);
1434
1435         good_mbuf_cnt = 0;
1436
1437         /* Allocate a bunch of mbufs and save the good ones in an array. */
1438         val = REG_RD_IND(bp, BNX2_RBUF_STATUS1);
1439         while (val & BNX2_RBUF_STATUS1_FREE_COUNT) {
1440                 REG_WR_IND(bp, BNX2_RBUF_COMMAND, BNX2_RBUF_COMMAND_ALLOC_REQ);
1441
1442                 val = REG_RD_IND(bp, BNX2_RBUF_FW_BUF_ALLOC);
1443
1444                 val &= BNX2_RBUF_FW_BUF_ALLOC_VALUE;
1445
1446                 /* The addresses with Bit 9 set are bad memory blocks. */
1447                 if (!(val & (1 << 9))) {
1448                         good_mbuf[good_mbuf_cnt] = (u16) val;
1449                         good_mbuf_cnt++;
1450                 }
1451
1452                 val = REG_RD_IND(bp, BNX2_RBUF_STATUS1);
1453         }
1454
1455         /* Free the good ones back to the mbuf pool thus discarding
1456          * all the bad ones. */
1457         while (good_mbuf_cnt) {
1458                 good_mbuf_cnt--;
1459
1460                 val = good_mbuf[good_mbuf_cnt];
1461                 val = (val << 9) | val | 1;
1462
1463                 REG_WR_IND(bp, BNX2_RBUF_FW_BUF_FREE, val);
1464         }
1465         kfree(good_mbuf);
1466         return 0;
1467 }
1468
1469 static void
1470 bnx2_set_mac_addr(struct bnx2 *bp)
1471 {
1472         u32 val;
1473         u8 *mac_addr = bp->dev->dev_addr;
1474
1475         val = (mac_addr[0] << 8) | mac_addr[1];
1476
1477         REG_WR(bp, BNX2_EMAC_MAC_MATCH0, val);
1478
1479         val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
1480                 (mac_addr[4] << 8) | mac_addr[5];
1481
1482         REG_WR(bp, BNX2_EMAC_MAC_MATCH1, val);
1483 }
1484
1485 static inline int
1486 bnx2_alloc_rx_skb(struct bnx2 *bp, u16 index)
1487 {
1488         struct sk_buff *skb;
1489         struct sw_bd *rx_buf = &bp->rx_buf_ring[index];
1490         dma_addr_t mapping;
1491         struct rx_bd *rxbd = &bp->rx_desc_ring[index];
1492         unsigned long align;
1493
1494         skb = dev_alloc_skb(bp->rx_buf_size);
1495         if (skb == NULL) {
1496                 return -ENOMEM;
1497         }
1498
1499         if (unlikely((align = (unsigned long) skb->data & 0x7))) {
1500                 skb_reserve(skb, 8 - align);
1501         }
1502
1503         skb->dev = bp->dev;
1504         mapping = pci_map_single(bp->pdev, skb->data, bp->rx_buf_use_size,
1505                 PCI_DMA_FROMDEVICE);
1506
1507         rx_buf->skb = skb;
1508         pci_unmap_addr_set(rx_buf, mapping, mapping);
1509
1510         rxbd->rx_bd_haddr_hi = (u64) mapping >> 32;
1511         rxbd->rx_bd_haddr_lo = (u64) mapping & 0xffffffff;
1512
1513         bp->rx_prod_bseq += bp->rx_buf_use_size;
1514
1515         return 0;
1516 }
1517
1518 static void
1519 bnx2_phy_int(struct bnx2 *bp)
1520 {
1521         u32 new_link_state, old_link_state;
1522
1523         new_link_state = bp->status_blk->status_attn_bits &
1524                 STATUS_ATTN_BITS_LINK_STATE;
1525         old_link_state = bp->status_blk->status_attn_bits_ack &
1526                 STATUS_ATTN_BITS_LINK_STATE;
1527         if (new_link_state != old_link_state) {
1528                 if (new_link_state) {
1529                         REG_WR(bp, BNX2_PCICFG_STATUS_BIT_SET_CMD,
1530                                 STATUS_ATTN_BITS_LINK_STATE);
1531                 }
1532                 else {
1533                         REG_WR(bp, BNX2_PCICFG_STATUS_BIT_CLEAR_CMD,
1534                                 STATUS_ATTN_BITS_LINK_STATE);
1535                 }
1536                 bnx2_set_link(bp);
1537         }
1538 }
1539
1540 static void
1541 bnx2_tx_int(struct bnx2 *bp)
1542 {
1543         struct status_block *sblk = bp->status_blk;
1544         u16 hw_cons, sw_cons, sw_ring_cons;
1545         int tx_free_bd = 0;
1546
1547         hw_cons = bp->hw_tx_cons = sblk->status_tx_quick_consumer_index0;
1548         if ((hw_cons & MAX_TX_DESC_CNT) == MAX_TX_DESC_CNT) {
1549                 hw_cons++;
1550         }
1551         sw_cons = bp->tx_cons;
1552
1553         while (sw_cons != hw_cons) {
1554                 struct sw_bd *tx_buf;
1555                 struct sk_buff *skb;
1556                 int i, last;
1557
1558                 sw_ring_cons = TX_RING_IDX(sw_cons);
1559
1560                 tx_buf = &bp->tx_buf_ring[sw_ring_cons];
1561                 skb = tx_buf->skb;
1562 #ifdef BCM_TSO
1563                 /* partial BD completions possible with TSO packets */
1564                 if (skb_shinfo(skb)->tso_size) {
1565                         u16 last_idx, last_ring_idx;
1566
1567                         last_idx = sw_cons +
1568                                 skb_shinfo(skb)->nr_frags + 1;
1569                         last_ring_idx = sw_ring_cons +
1570                                 skb_shinfo(skb)->nr_frags + 1;
1571                         if (unlikely(last_ring_idx >= MAX_TX_DESC_CNT)) {
1572                                 last_idx++;
1573                         }
1574                         if (((s16) ((s16) last_idx - (s16) hw_cons)) > 0) {
1575                                 break;
1576                         }
1577                 }
1578 #endif
1579                 pci_unmap_single(bp->pdev, pci_unmap_addr(tx_buf, mapping),
1580                         skb_headlen(skb), PCI_DMA_TODEVICE);
1581
1582                 tx_buf->skb = NULL;
1583                 last = skb_shinfo(skb)->nr_frags;
1584
1585                 for (i = 0; i < last; i++) {
1586                         sw_cons = NEXT_TX_BD(sw_cons);
1587
1588                         pci_unmap_page(bp->pdev,
1589                                 pci_unmap_addr(
1590                                         &bp->tx_buf_ring[TX_RING_IDX(sw_cons)],
1591                                         mapping),
1592                                 skb_shinfo(skb)->frags[i].size,
1593                                 PCI_DMA_TODEVICE);
1594                 }
1595
1596                 sw_cons = NEXT_TX_BD(sw_cons);
1597
1598                 tx_free_bd += last + 1;
1599
1600                 dev_kfree_skb_irq(skb);
1601
1602                 hw_cons = bp->hw_tx_cons =
1603                         sblk->status_tx_quick_consumer_index0;
1604
1605                 if ((hw_cons & MAX_TX_DESC_CNT) == MAX_TX_DESC_CNT) {
1606                         hw_cons++;
1607                 }
1608         }
1609
1610         bp->tx_cons = sw_cons;
1611
1612         if (unlikely(netif_queue_stopped(bp->dev))) {
1613                 spin_lock(&bp->tx_lock);
1614                 if ((netif_queue_stopped(bp->dev)) &&
1615                     (bnx2_tx_avail(bp) > MAX_SKB_FRAGS)) {
1616
1617                         netif_wake_queue(bp->dev);
1618                 }
1619                 spin_unlock(&bp->tx_lock);
1620         }
1621 }
1622
1623 static inline void
1624 bnx2_reuse_rx_skb(struct bnx2 *bp, struct sk_buff *skb,
1625         u16 cons, u16 prod)
1626 {
1627         struct sw_bd *cons_rx_buf = &bp->rx_buf_ring[cons];
1628         struct sw_bd *prod_rx_buf = &bp->rx_buf_ring[prod];
1629         struct rx_bd *cons_bd = &bp->rx_desc_ring[cons];
1630         struct rx_bd *prod_bd = &bp->rx_desc_ring[prod];
1631
1632         pci_dma_sync_single_for_device(bp->pdev,
1633                 pci_unmap_addr(cons_rx_buf, mapping),
1634                 bp->rx_offset + RX_COPY_THRESH, PCI_DMA_FROMDEVICE);
1635
1636         prod_rx_buf->skb = cons_rx_buf->skb;
1637         pci_unmap_addr_set(prod_rx_buf, mapping,
1638                         pci_unmap_addr(cons_rx_buf, mapping));
1639
1640         memcpy(prod_bd, cons_bd, 8);
1641
1642         bp->rx_prod_bseq += bp->rx_buf_use_size;
1643
1644 }
1645
1646 static int
1647 bnx2_rx_int(struct bnx2 *bp, int budget)
1648 {
1649         struct status_block *sblk = bp->status_blk;
1650         u16 hw_cons, sw_cons, sw_ring_cons, sw_prod, sw_ring_prod;
1651         struct l2_fhdr *rx_hdr;
1652         int rx_pkt = 0;
1653
1654         hw_cons = bp->hw_rx_cons = sblk->status_rx_quick_consumer_index0;
1655         if ((hw_cons & MAX_RX_DESC_CNT) == MAX_RX_DESC_CNT) {
1656                 hw_cons++;
1657         }
1658         sw_cons = bp->rx_cons;
1659         sw_prod = bp->rx_prod;
1660
1661         /* Memory barrier necessary as speculative reads of the rx
1662          * buffer can be ahead of the index in the status block
1663          */
1664         rmb();
1665         while (sw_cons != hw_cons) {
1666                 unsigned int len;
1667                 u32 status;
1668                 struct sw_bd *rx_buf;
1669                 struct sk_buff *skb;
1670
1671                 sw_ring_cons = RX_RING_IDX(sw_cons);
1672                 sw_ring_prod = RX_RING_IDX(sw_prod);
1673
1674                 rx_buf = &bp->rx_buf_ring[sw_ring_cons];
1675                 skb = rx_buf->skb;
1676                 pci_dma_sync_single_for_cpu(bp->pdev,
1677                         pci_unmap_addr(rx_buf, mapping),
1678                         bp->rx_offset + RX_COPY_THRESH, PCI_DMA_FROMDEVICE);
1679
1680                 rx_hdr = (struct l2_fhdr *) skb->data;
1681                 len = rx_hdr->l2_fhdr_pkt_len - 4;
1682
1683                 if ((status = rx_hdr->l2_fhdr_status) &
1684                         (L2_FHDR_ERRORS_BAD_CRC |
1685                         L2_FHDR_ERRORS_PHY_DECODE |
1686                         L2_FHDR_ERRORS_ALIGNMENT |
1687                         L2_FHDR_ERRORS_TOO_SHORT |
1688                         L2_FHDR_ERRORS_GIANT_FRAME)) {
1689
1690                         goto reuse_rx;
1691                 }
1692
1693                 /* Since we don't have a jumbo ring, copy small packets
1694                  * if mtu > 1500
1695                  */
1696                 if ((bp->dev->mtu > 1500) && (len <= RX_COPY_THRESH)) {
1697                         struct sk_buff *new_skb;
1698
1699                         new_skb = dev_alloc_skb(len + 2);
1700                         if (new_skb == NULL)
1701                                 goto reuse_rx;
1702
1703                         /* aligned copy */
1704                         memcpy(new_skb->data,
1705                                 skb->data + bp->rx_offset - 2,
1706                                 len + 2);
1707
1708                         skb_reserve(new_skb, 2);
1709                         skb_put(new_skb, len);
1710                         new_skb->dev = bp->dev;
1711
1712                         bnx2_reuse_rx_skb(bp, skb,
1713                                 sw_ring_cons, sw_ring_prod);
1714
1715                         skb = new_skb;
1716                 }
1717                 else if (bnx2_alloc_rx_skb(bp, sw_ring_prod) == 0) {
1718                         pci_unmap_single(bp->pdev,
1719                                 pci_unmap_addr(rx_buf, mapping),
1720                                 bp->rx_buf_use_size, PCI_DMA_FROMDEVICE);
1721
1722                         skb_reserve(skb, bp->rx_offset);
1723                         skb_put(skb, len);
1724                 }
1725                 else {
1726 reuse_rx:
1727                         bnx2_reuse_rx_skb(bp, skb,
1728                                 sw_ring_cons, sw_ring_prod);
1729                         goto next_rx;
1730                 }
1731
1732                 skb->protocol = eth_type_trans(skb, bp->dev);
1733
1734                 if ((len > (bp->dev->mtu + ETH_HLEN)) &&
1735                         (htons(skb->protocol) != 0x8100)) {
1736
1737                         dev_kfree_skb_irq(skb);
1738                         goto next_rx;
1739
1740                 }
1741
1742                 skb->ip_summed = CHECKSUM_NONE;
1743                 if (bp->rx_csum &&
1744                         (status & (L2_FHDR_STATUS_TCP_SEGMENT |
1745                         L2_FHDR_STATUS_UDP_DATAGRAM))) {
1746
1747                         if (likely((status & (L2_FHDR_ERRORS_TCP_XSUM |
1748                                               L2_FHDR_ERRORS_UDP_XSUM)) == 0))
1749                                 skb->ip_summed = CHECKSUM_UNNECESSARY;
1750                 }
1751
1752 #ifdef BCM_VLAN
1753                 if ((status & L2_FHDR_STATUS_L2_VLAN_TAG) && (bp->vlgrp != 0)) {
1754                         vlan_hwaccel_receive_skb(skb, bp->vlgrp,
1755                                 rx_hdr->l2_fhdr_vlan_tag);
1756                 }
1757                 else
1758 #endif
1759                         netif_receive_skb(skb);
1760
1761                 bp->dev->last_rx = jiffies;
1762                 rx_pkt++;
1763
1764 next_rx:
1765                 rx_buf->skb = NULL;
1766
1767                 sw_cons = NEXT_RX_BD(sw_cons);
1768                 sw_prod = NEXT_RX_BD(sw_prod);
1769
1770                 if ((rx_pkt == budget))
1771                         break;
1772
1773                 /* Refresh hw_cons to see if there is new work */
1774                 if (sw_cons == hw_cons) {
1775                         hw_cons = bp->hw_rx_cons =
1776                                 sblk->status_rx_quick_consumer_index0;
1777                         if ((hw_cons & MAX_RX_DESC_CNT) == MAX_RX_DESC_CNT)
1778                                 hw_cons++;
1779                         rmb();
1780                 }
1781         }
1782         bp->rx_cons = sw_cons;
1783         bp->rx_prod = sw_prod;
1784
1785         REG_WR16(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BDIDX, sw_prod);
1786
1787         REG_WR(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BSEQ, bp->rx_prod_bseq);
1788
1789         mmiowb();
1790
1791         return rx_pkt;
1792
1793 }
1794
1795 /* MSI ISR - The only difference between this and the INTx ISR
1796  * is that the MSI interrupt is always serviced.
1797  */
1798 static irqreturn_t
1799 bnx2_msi(int irq, void *dev_instance, struct pt_regs *regs)
1800 {
1801         struct net_device *dev = dev_instance;
1802         struct bnx2 *bp = dev->priv;
1803
1804         prefetch(bp->status_blk);
1805         REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
1806                 BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
1807                 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
1808
1809         /* Return here if interrupt is disabled. */
1810         if (unlikely(atomic_read(&bp->intr_sem) != 0))
1811                 return IRQ_HANDLED;
1812
1813         netif_rx_schedule(dev);
1814
1815         return IRQ_HANDLED;
1816 }
1817
1818 static irqreturn_t
1819 bnx2_interrupt(int irq, void *dev_instance, struct pt_regs *regs)
1820 {
1821         struct net_device *dev = dev_instance;
1822         struct bnx2 *bp = dev->priv;
1823
1824         /* When using INTx, it is possible for the interrupt to arrive
1825          * at the CPU before the status block posted prior to the
1826          * interrupt. Reading a register will flush the status block.
1827          * When using MSI, the MSI message will always complete after
1828          * the status block write.
1829          */
1830         if ((bp->status_blk->status_idx == bp->last_status_idx) &&
1831             (REG_RD(bp, BNX2_PCICFG_MISC_STATUS) &
1832              BNX2_PCICFG_MISC_STATUS_INTA_VALUE))
1833                 return IRQ_NONE;
1834
1835         REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
1836                 BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
1837                 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
1838
1839         /* Return here if interrupt is shared and is disabled. */
1840         if (unlikely(atomic_read(&bp->intr_sem) != 0))
1841                 return IRQ_HANDLED;
1842
1843         netif_rx_schedule(dev);
1844
1845         return IRQ_HANDLED;
1846 }
1847
1848 static inline int
1849 bnx2_has_work(struct bnx2 *bp)
1850 {
1851         struct status_block *sblk = bp->status_blk;
1852
1853         if ((sblk->status_rx_quick_consumer_index0 != bp->hw_rx_cons) ||
1854             (sblk->status_tx_quick_consumer_index0 != bp->hw_tx_cons))
1855                 return 1;
1856
1857         if (((sblk->status_attn_bits & STATUS_ATTN_BITS_LINK_STATE) != 0) !=
1858             bp->link_up)
1859                 return 1;
1860
1861         return 0;
1862 }
1863
1864 static int
1865 bnx2_poll(struct net_device *dev, int *budget)
1866 {
1867         struct bnx2 *bp = dev->priv;
1868
1869         if ((bp->status_blk->status_attn_bits &
1870                 STATUS_ATTN_BITS_LINK_STATE) !=
1871                 (bp->status_blk->status_attn_bits_ack &
1872                 STATUS_ATTN_BITS_LINK_STATE)) {
1873
1874                 spin_lock(&bp->phy_lock);
1875                 bnx2_phy_int(bp);
1876                 spin_unlock(&bp->phy_lock);
1877         }
1878
1879         if (bp->status_blk->status_tx_quick_consumer_index0 != bp->hw_tx_cons)
1880                 bnx2_tx_int(bp);
1881
1882         if (bp->status_blk->status_rx_quick_consumer_index0 != bp->hw_rx_cons) {
1883                 int orig_budget = *budget;
1884                 int work_done;
1885
1886                 if (orig_budget > dev->quota)
1887                         orig_budget = dev->quota;
1888
1889                 work_done = bnx2_rx_int(bp, orig_budget);
1890                 *budget -= work_done;
1891                 dev->quota -= work_done;
1892         }
1893
1894         bp->last_status_idx = bp->status_blk->status_idx;
1895         rmb();
1896
1897         if (!bnx2_has_work(bp)) {
1898                 netif_rx_complete(dev);
1899                 if (likely(bp->flags & USING_MSI_FLAG)) {
1900                         REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
1901                                BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
1902                                bp->last_status_idx);
1903                         return 0;
1904                 }
1905                 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
1906                        BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
1907                        BNX2_PCICFG_INT_ACK_CMD_MASK_INT |
1908                        bp->last_status_idx);
1909
1910                 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
1911                        BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
1912                        bp->last_status_idx);
1913                 return 0;
1914         }
1915
1916         return 1;
1917 }
1918
1919 /* Called with rtnl_lock from vlan functions and also dev->xmit_lock
1920  * from set_multicast.
1921  */
1922 static void
1923 bnx2_set_rx_mode(struct net_device *dev)
1924 {
1925         struct bnx2 *bp = dev->priv;
1926         u32 rx_mode, sort_mode;
1927         int i;
1928
1929         spin_lock_bh(&bp->phy_lock);
1930
1931         rx_mode = bp->rx_mode & ~(BNX2_EMAC_RX_MODE_PROMISCUOUS |
1932                                   BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG);
1933         sort_mode = 1 | BNX2_RPM_SORT_USER0_BC_EN;
1934 #ifdef BCM_VLAN
1935         if (!bp->vlgrp && !(bp->flags & ASF_ENABLE_FLAG))
1936                 rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
1937 #else
1938         if (!(bp->flags & ASF_ENABLE_FLAG))
1939                 rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
1940 #endif
1941         if (dev->flags & IFF_PROMISC) {
1942                 /* Promiscuous mode. */
1943                 rx_mode |= BNX2_EMAC_RX_MODE_PROMISCUOUS;
1944                 sort_mode |= BNX2_RPM_SORT_USER0_PROM_EN;
1945         }
1946         else if (dev->flags & IFF_ALLMULTI) {
1947                 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
1948                         REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
1949                                0xffffffff);
1950                 }
1951                 sort_mode |= BNX2_RPM_SORT_USER0_MC_EN;
1952         }
1953         else {
1954                 /* Accept one or more multicast(s). */
1955                 struct dev_mc_list *mclist;
1956                 u32 mc_filter[NUM_MC_HASH_REGISTERS];
1957                 u32 regidx;
1958                 u32 bit;
1959                 u32 crc;
1960
1961                 memset(mc_filter, 0, 4 * NUM_MC_HASH_REGISTERS);
1962
1963                 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
1964                      i++, mclist = mclist->next) {
1965
1966                         crc = ether_crc_le(ETH_ALEN, mclist->dmi_addr);
1967                         bit = crc & 0xff;
1968                         regidx = (bit & 0xe0) >> 5;
1969                         bit &= 0x1f;
1970                         mc_filter[regidx] |= (1 << bit);
1971                 }
1972
1973                 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
1974                         REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
1975                                mc_filter[i]);
1976                 }
1977
1978                 sort_mode |= BNX2_RPM_SORT_USER0_MC_HSH_EN;
1979         }
1980
1981         if (rx_mode != bp->rx_mode) {
1982                 bp->rx_mode = rx_mode;
1983                 REG_WR(bp, BNX2_EMAC_RX_MODE, rx_mode);
1984         }
1985
1986         REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
1987         REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode);
1988         REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode | BNX2_RPM_SORT_USER0_ENA);
1989
1990         spin_unlock_bh(&bp->phy_lock);
1991 }
1992
1993 static void
1994 load_rv2p_fw(struct bnx2 *bp, u32 *rv2p_code, u32 rv2p_code_len,
1995         u32 rv2p_proc)
1996 {
1997         int i;
1998         u32 val;
1999
2000
2001         for (i = 0; i < rv2p_code_len; i += 8) {
2002                 REG_WR(bp, BNX2_RV2P_INSTR_HIGH, *rv2p_code);
2003                 rv2p_code++;
2004                 REG_WR(bp, BNX2_RV2P_INSTR_LOW, *rv2p_code);
2005                 rv2p_code++;
2006
2007                 if (rv2p_proc == RV2P_PROC1) {
2008                         val = (i / 8) | BNX2_RV2P_PROC1_ADDR_CMD_RDWR;
2009                         REG_WR(bp, BNX2_RV2P_PROC1_ADDR_CMD, val);
2010                 }
2011                 else {
2012                         val = (i / 8) | BNX2_RV2P_PROC2_ADDR_CMD_RDWR;
2013                         REG_WR(bp, BNX2_RV2P_PROC2_ADDR_CMD, val);
2014                 }
2015         }
2016
2017         /* Reset the processor, un-stall is done later. */
2018         if (rv2p_proc == RV2P_PROC1) {
2019                 REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC1_RESET);
2020         }
2021         else {
2022                 REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC2_RESET);
2023         }
2024 }
2025
2026 static void
2027 load_cpu_fw(struct bnx2 *bp, struct cpu_reg *cpu_reg, struct fw_info *fw)
2028 {
2029         u32 offset;
2030         u32 val;
2031
2032         /* Halt the CPU. */
2033         val = REG_RD_IND(bp, cpu_reg->mode);
2034         val |= cpu_reg->mode_value_halt;
2035         REG_WR_IND(bp, cpu_reg->mode, val);
2036         REG_WR_IND(bp, cpu_reg->state, cpu_reg->state_value_clear);
2037
2038         /* Load the Text area. */
2039         offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base);
2040         if (fw->text) {
2041                 int j;
2042
2043                 for (j = 0; j < (fw->text_len / 4); j++, offset += 4) {
2044                         REG_WR_IND(bp, offset, fw->text[j]);
2045                 }
2046         }
2047
2048         /* Load the Data area. */
2049         offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base);
2050         if (fw->data) {
2051                 int j;
2052
2053                 for (j = 0; j < (fw->data_len / 4); j++, offset += 4) {
2054                         REG_WR_IND(bp, offset, fw->data[j]);
2055                 }
2056         }
2057
2058         /* Load the SBSS area. */
2059         offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base);
2060         if (fw->sbss) {
2061                 int j;
2062
2063                 for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4) {
2064                         REG_WR_IND(bp, offset, fw->sbss[j]);
2065                 }
2066         }
2067
2068         /* Load the BSS area. */
2069         offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base);
2070         if (fw->bss) {
2071                 int j;
2072
2073                 for (j = 0; j < (fw->bss_len/4); j++, offset += 4) {
2074                         REG_WR_IND(bp, offset, fw->bss[j]);
2075                 }
2076         }
2077
2078         /* Load the Read-Only area. */
2079         offset = cpu_reg->spad_base +
2080                 (fw->rodata_addr - cpu_reg->mips_view_base);
2081         if (fw->rodata) {
2082                 int j;
2083
2084                 for (j = 0; j < (fw->rodata_len / 4); j++, offset += 4) {
2085                         REG_WR_IND(bp, offset, fw->rodata[j]);
2086                 }
2087         }
2088
2089         /* Clear the pre-fetch instruction. */
2090         REG_WR_IND(bp, cpu_reg->inst, 0);
2091         REG_WR_IND(bp, cpu_reg->pc, fw->start_addr);
2092
2093         /* Start the CPU. */
2094         val = REG_RD_IND(bp, cpu_reg->mode);
2095         val &= ~cpu_reg->mode_value_halt;
2096         REG_WR_IND(bp, cpu_reg->state, cpu_reg->state_value_clear);
2097         REG_WR_IND(bp, cpu_reg->mode, val);
2098 }
2099
2100 static void
2101 bnx2_init_cpus(struct bnx2 *bp)
2102 {
2103         struct cpu_reg cpu_reg;
2104         struct fw_info fw;
2105
2106         /* Initialize the RV2P processor. */
2107         load_rv2p_fw(bp, bnx2_rv2p_proc1, sizeof(bnx2_rv2p_proc1), RV2P_PROC1);
2108         load_rv2p_fw(bp, bnx2_rv2p_proc2, sizeof(bnx2_rv2p_proc2), RV2P_PROC2);
2109
2110         /* Initialize the RX Processor. */
2111         cpu_reg.mode = BNX2_RXP_CPU_MODE;
2112         cpu_reg.mode_value_halt = BNX2_RXP_CPU_MODE_SOFT_HALT;
2113         cpu_reg.mode_value_sstep = BNX2_RXP_CPU_MODE_STEP_ENA;
2114         cpu_reg.state = BNX2_RXP_CPU_STATE;
2115         cpu_reg.state_value_clear = 0xffffff;
2116         cpu_reg.gpr0 = BNX2_RXP_CPU_REG_FILE;
2117         cpu_reg.evmask = BNX2_RXP_CPU_EVENT_MASK;
2118         cpu_reg.pc = BNX2_RXP_CPU_PROGRAM_COUNTER;
2119         cpu_reg.inst = BNX2_RXP_CPU_INSTRUCTION;
2120         cpu_reg.bp = BNX2_RXP_CPU_HW_BREAKPOINT;
2121         cpu_reg.spad_base = BNX2_RXP_SCRATCH;
2122         cpu_reg.mips_view_base = 0x8000000;
2123
2124         fw.ver_major = bnx2_RXP_b06FwReleaseMajor;
2125         fw.ver_minor = bnx2_RXP_b06FwReleaseMinor;
2126         fw.ver_fix = bnx2_RXP_b06FwReleaseFix;
2127         fw.start_addr = bnx2_RXP_b06FwStartAddr;
2128
2129         fw.text_addr = bnx2_RXP_b06FwTextAddr;
2130         fw.text_len = bnx2_RXP_b06FwTextLen;
2131         fw.text_index = 0;
2132         fw.text = bnx2_RXP_b06FwText;
2133
2134         fw.data_addr = bnx2_RXP_b06FwDataAddr;
2135         fw.data_len = bnx2_RXP_b06FwDataLen;
2136         fw.data_index = 0;
2137         fw.data = bnx2_RXP_b06FwData;
2138
2139         fw.sbss_addr = bnx2_RXP_b06FwSbssAddr;
2140         fw.sbss_len = bnx2_RXP_b06FwSbssLen;
2141         fw.sbss_index = 0;
2142         fw.sbss = bnx2_RXP_b06FwSbss;
2143
2144         fw.bss_addr = bnx2_RXP_b06FwBssAddr;
2145         fw.bss_len = bnx2_RXP_b06FwBssLen;
2146         fw.bss_index = 0;
2147         fw.bss = bnx2_RXP_b06FwBss;
2148
2149         fw.rodata_addr = bnx2_RXP_b06FwRodataAddr;
2150         fw.rodata_len = bnx2_RXP_b06FwRodataLen;
2151         fw.rodata_index = 0;
2152         fw.rodata = bnx2_RXP_b06FwRodata;
2153
2154         load_cpu_fw(bp, &cpu_reg, &fw);
2155
2156         /* Initialize the TX Processor. */
2157         cpu_reg.mode = BNX2_TXP_CPU_MODE;
2158         cpu_reg.mode_value_halt = BNX2_TXP_CPU_MODE_SOFT_HALT;
2159         cpu_reg.mode_value_sstep = BNX2_TXP_CPU_MODE_STEP_ENA;
2160         cpu_reg.state = BNX2_TXP_CPU_STATE;
2161         cpu_reg.state_value_clear = 0xffffff;
2162         cpu_reg.gpr0 = BNX2_TXP_CPU_REG_FILE;
2163         cpu_reg.evmask = BNX2_TXP_CPU_EVENT_MASK;
2164         cpu_reg.pc = BNX2_TXP_CPU_PROGRAM_COUNTER;
2165         cpu_reg.inst = BNX2_TXP_CPU_INSTRUCTION;
2166         cpu_reg.bp = BNX2_TXP_CPU_HW_BREAKPOINT;
2167         cpu_reg.spad_base = BNX2_TXP_SCRATCH;
2168         cpu_reg.mips_view_base = 0x8000000;
2169
2170         fw.ver_major = bnx2_TXP_b06FwReleaseMajor;
2171         fw.ver_minor = bnx2_TXP_b06FwReleaseMinor;
2172         fw.ver_fix = bnx2_TXP_b06FwReleaseFix;
2173         fw.start_addr = bnx2_TXP_b06FwStartAddr;
2174
2175         fw.text_addr = bnx2_TXP_b06FwTextAddr;
2176         fw.text_len = bnx2_TXP_b06FwTextLen;
2177         fw.text_index = 0;
2178         fw.text = bnx2_TXP_b06FwText;
2179
2180         fw.data_addr = bnx2_TXP_b06FwDataAddr;
2181         fw.data_len = bnx2_TXP_b06FwDataLen;
2182         fw.data_index = 0;
2183         fw.data = bnx2_TXP_b06FwData;
2184
2185         fw.sbss_addr = bnx2_TXP_b06FwSbssAddr;
2186         fw.sbss_len = bnx2_TXP_b06FwSbssLen;
2187         fw.sbss_index = 0;
2188         fw.sbss = bnx2_TXP_b06FwSbss;
2189
2190         fw.bss_addr = bnx2_TXP_b06FwBssAddr;
2191         fw.bss_len = bnx2_TXP_b06FwBssLen;
2192         fw.bss_index = 0;
2193         fw.bss = bnx2_TXP_b06FwBss;
2194
2195         fw.rodata_addr = bnx2_TXP_b06FwRodataAddr;
2196         fw.rodata_len = bnx2_TXP_b06FwRodataLen;
2197         fw.rodata_index = 0;
2198         fw.rodata = bnx2_TXP_b06FwRodata;
2199
2200         load_cpu_fw(bp, &cpu_reg, &fw);
2201
2202         /* Initialize the TX Patch-up Processor. */
2203         cpu_reg.mode = BNX2_TPAT_CPU_MODE;
2204         cpu_reg.mode_value_halt = BNX2_TPAT_CPU_MODE_SOFT_HALT;
2205         cpu_reg.mode_value_sstep = BNX2_TPAT_CPU_MODE_STEP_ENA;
2206         cpu_reg.state = BNX2_TPAT_CPU_STATE;
2207         cpu_reg.state_value_clear = 0xffffff;
2208         cpu_reg.gpr0 = BNX2_TPAT_CPU_REG_FILE;
2209         cpu_reg.evmask = BNX2_TPAT_CPU_EVENT_MASK;
2210         cpu_reg.pc = BNX2_TPAT_CPU_PROGRAM_COUNTER;
2211         cpu_reg.inst = BNX2_TPAT_CPU_INSTRUCTION;
2212         cpu_reg.bp = BNX2_TPAT_CPU_HW_BREAKPOINT;
2213         cpu_reg.spad_base = BNX2_TPAT_SCRATCH;
2214         cpu_reg.mips_view_base = 0x8000000;
2215
2216         fw.ver_major = bnx2_TPAT_b06FwReleaseMajor;
2217         fw.ver_minor = bnx2_TPAT_b06FwReleaseMinor;
2218         fw.ver_fix = bnx2_TPAT_b06FwReleaseFix;
2219         fw.start_addr = bnx2_TPAT_b06FwStartAddr;
2220
2221         fw.text_addr = bnx2_TPAT_b06FwTextAddr;
2222         fw.text_len = bnx2_TPAT_b06FwTextLen;
2223         fw.text_index = 0;
2224         fw.text = bnx2_TPAT_b06FwText;
2225
2226         fw.data_addr = bnx2_TPAT_b06FwDataAddr;
2227         fw.data_len = bnx2_TPAT_b06FwDataLen;
2228         fw.data_index = 0;
2229         fw.data = bnx2_TPAT_b06FwData;
2230
2231         fw.sbss_addr = bnx2_TPAT_b06FwSbssAddr;
2232         fw.sbss_len = bnx2_TPAT_b06FwSbssLen;
2233         fw.sbss_index = 0;
2234         fw.sbss = bnx2_TPAT_b06FwSbss;
2235
2236         fw.bss_addr = bnx2_TPAT_b06FwBssAddr;
2237         fw.bss_len = bnx2_TPAT_b06FwBssLen;
2238         fw.bss_index = 0;
2239         fw.bss = bnx2_TPAT_b06FwBss;
2240
2241         fw.rodata_addr = bnx2_TPAT_b06FwRodataAddr;
2242         fw.rodata_len = bnx2_TPAT_b06FwRodataLen;
2243         fw.rodata_index = 0;
2244         fw.rodata = bnx2_TPAT_b06FwRodata;
2245
2246         load_cpu_fw(bp, &cpu_reg, &fw);
2247
2248         /* Initialize the Completion Processor. */
2249         cpu_reg.mode = BNX2_COM_CPU_MODE;
2250         cpu_reg.mode_value_halt = BNX2_COM_CPU_MODE_SOFT_HALT;
2251         cpu_reg.mode_value_sstep = BNX2_COM_CPU_MODE_STEP_ENA;
2252         cpu_reg.state = BNX2_COM_CPU_STATE;
2253         cpu_reg.state_value_clear = 0xffffff;
2254         cpu_reg.gpr0 = BNX2_COM_CPU_REG_FILE;
2255         cpu_reg.evmask = BNX2_COM_CPU_EVENT_MASK;
2256         cpu_reg.pc = BNX2_COM_CPU_PROGRAM_COUNTER;
2257         cpu_reg.inst = BNX2_COM_CPU_INSTRUCTION;
2258         cpu_reg.bp = BNX2_COM_CPU_HW_BREAKPOINT;
2259         cpu_reg.spad_base = BNX2_COM_SCRATCH;
2260         cpu_reg.mips_view_base = 0x8000000;
2261
2262         fw.ver_major = bnx2_COM_b06FwReleaseMajor;
2263         fw.ver_minor = bnx2_COM_b06FwReleaseMinor;
2264         fw.ver_fix = bnx2_COM_b06FwReleaseFix;
2265         fw.start_addr = bnx2_COM_b06FwStartAddr;
2266
2267         fw.text_addr = bnx2_COM_b06FwTextAddr;
2268         fw.text_len = bnx2_COM_b06FwTextLen;
2269         fw.text_index = 0;
2270         fw.text = bnx2_COM_b06FwText;
2271
2272         fw.data_addr = bnx2_COM_b06FwDataAddr;
2273         fw.data_len = bnx2_COM_b06FwDataLen;
2274         fw.data_index = 0;
2275         fw.data = bnx2_COM_b06FwData;
2276
2277         fw.sbss_addr = bnx2_COM_b06FwSbssAddr;
2278         fw.sbss_len = bnx2_COM_b06FwSbssLen;
2279         fw.sbss_index = 0;
2280         fw.sbss = bnx2_COM_b06FwSbss;
2281
2282         fw.bss_addr = bnx2_COM_b06FwBssAddr;
2283         fw.bss_len = bnx2_COM_b06FwBssLen;
2284         fw.bss_index = 0;
2285         fw.bss = bnx2_COM_b06FwBss;
2286
2287         fw.rodata_addr = bnx2_COM_b06FwRodataAddr;
2288         fw.rodata_len = bnx2_COM_b06FwRodataLen;
2289         fw.rodata_index = 0;
2290         fw.rodata = bnx2_COM_b06FwRodata;
2291
2292         load_cpu_fw(bp, &cpu_reg, &fw);
2293
2294 }
2295
2296 static int
2297 bnx2_set_power_state(struct bnx2 *bp, pci_power_t state)
2298 {
2299         u16 pmcsr;
2300
2301         pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &pmcsr);
2302
2303         switch (state) {
2304         case PCI_D0: {
2305                 u32 val;
2306
2307                 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
2308                         (pmcsr & ~PCI_PM_CTRL_STATE_MASK) |
2309                         PCI_PM_CTRL_PME_STATUS);
2310
2311                 if (pmcsr & PCI_PM_CTRL_STATE_MASK)
2312                         /* delay required during transition out of D3hot */
2313                         msleep(20);
2314
2315                 val = REG_RD(bp, BNX2_EMAC_MODE);
2316                 val |= BNX2_EMAC_MODE_MPKT_RCVD | BNX2_EMAC_MODE_ACPI_RCVD;
2317                 val &= ~BNX2_EMAC_MODE_MPKT;
2318                 REG_WR(bp, BNX2_EMAC_MODE, val);
2319
2320                 val = REG_RD(bp, BNX2_RPM_CONFIG);
2321                 val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
2322                 REG_WR(bp, BNX2_RPM_CONFIG, val);
2323                 break;
2324         }
2325         case PCI_D3hot: {
2326                 int i;
2327                 u32 val, wol_msg;
2328
2329                 if (bp->wol) {
2330                         u32 advertising;
2331                         u8 autoneg;
2332
2333                         autoneg = bp->autoneg;
2334                         advertising = bp->advertising;
2335
2336                         bp->autoneg = AUTONEG_SPEED;
2337                         bp->advertising = ADVERTISED_10baseT_Half |
2338                                 ADVERTISED_10baseT_Full |
2339                                 ADVERTISED_100baseT_Half |
2340                                 ADVERTISED_100baseT_Full |
2341                                 ADVERTISED_Autoneg;
2342
2343                         bnx2_setup_copper_phy(bp);
2344
2345                         bp->autoneg = autoneg;
2346                         bp->advertising = advertising;
2347
2348                         bnx2_set_mac_addr(bp);
2349
2350                         val = REG_RD(bp, BNX2_EMAC_MODE);
2351
2352                         /* Enable port mode. */
2353                         val &= ~BNX2_EMAC_MODE_PORT;
2354                         val |= BNX2_EMAC_MODE_PORT_MII |
2355                                BNX2_EMAC_MODE_MPKT_RCVD |
2356                                BNX2_EMAC_MODE_ACPI_RCVD |
2357                                BNX2_EMAC_MODE_MPKT;
2358
2359                         REG_WR(bp, BNX2_EMAC_MODE, val);
2360
2361                         /* receive all multicast */
2362                         for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
2363                                 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
2364                                        0xffffffff);
2365                         }
2366                         REG_WR(bp, BNX2_EMAC_RX_MODE,
2367                                BNX2_EMAC_RX_MODE_SORT_MODE);
2368
2369                         val = 1 | BNX2_RPM_SORT_USER0_BC_EN |
2370                               BNX2_RPM_SORT_USER0_MC_EN;
2371                         REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
2372                         REG_WR(bp, BNX2_RPM_SORT_USER0, val);
2373                         REG_WR(bp, BNX2_RPM_SORT_USER0, val |
2374                                BNX2_RPM_SORT_USER0_ENA);
2375
2376                         /* Need to enable EMAC and RPM for WOL. */
2377                         REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
2378                                BNX2_MISC_ENABLE_SET_BITS_RX_PARSER_MAC_ENABLE |
2379                                BNX2_MISC_ENABLE_SET_BITS_TX_HEADER_Q_ENABLE |
2380                                BNX2_MISC_ENABLE_SET_BITS_EMAC_ENABLE);
2381
2382                         val = REG_RD(bp, BNX2_RPM_CONFIG);
2383                         val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
2384                         REG_WR(bp, BNX2_RPM_CONFIG, val);
2385
2386                         wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
2387                 }
2388                 else {
2389                         wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
2390                 }
2391
2392                 if (!(bp->flags & NO_WOL_FLAG))
2393                         bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT3 | wol_msg, 0);
2394
2395                 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
2396                 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
2397                     (CHIP_ID(bp) == CHIP_ID_5706_A1)) {
2398
2399                         if (bp->wol)
2400                                 pmcsr |= 3;
2401                 }
2402                 else {
2403                         pmcsr |= 3;
2404                 }
2405                 if (bp->wol) {
2406                         pmcsr |= PCI_PM_CTRL_PME_ENABLE;
2407                 }
2408                 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
2409                                       pmcsr);
2410
2411                 /* No more memory access after this point until
2412                  * device is brought back to D0.
2413                  */
2414                 udelay(50);
2415                 break;
2416         }
2417         default:
2418                 return -EINVAL;
2419         }
2420         return 0;
2421 }
2422
2423 static int
2424 bnx2_acquire_nvram_lock(struct bnx2 *bp)
2425 {
2426         u32 val;
2427         int j;
2428
2429         /* Request access to the flash interface. */
2430         REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_SET2);
2431         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2432                 val = REG_RD(bp, BNX2_NVM_SW_ARB);
2433                 if (val & BNX2_NVM_SW_ARB_ARB_ARB2)
2434                         break;
2435
2436                 udelay(5);
2437         }
2438
2439         if (j >= NVRAM_TIMEOUT_COUNT)
2440                 return -EBUSY;
2441
2442         return 0;
2443 }
2444
2445 static int
2446 bnx2_release_nvram_lock(struct bnx2 *bp)
2447 {
2448         int j;
2449         u32 val;
2450
2451         /* Relinquish nvram interface. */
2452         REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_CLR2);
2453
2454         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2455                 val = REG_RD(bp, BNX2_NVM_SW_ARB);
2456                 if (!(val & BNX2_NVM_SW_ARB_ARB_ARB2))
2457                         break;
2458
2459                 udelay(5);
2460         }
2461
2462         if (j >= NVRAM_TIMEOUT_COUNT)
2463                 return -EBUSY;
2464
2465         return 0;
2466 }
2467
2468
2469 static int
2470 bnx2_enable_nvram_write(struct bnx2 *bp)
2471 {
2472         u32 val;
2473
2474         val = REG_RD(bp, BNX2_MISC_CFG);
2475         REG_WR(bp, BNX2_MISC_CFG, val | BNX2_MISC_CFG_NVM_WR_EN_PCI);
2476
2477         if (!bp->flash_info->buffered) {
2478                 int j;
2479
2480                 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
2481                 REG_WR(bp, BNX2_NVM_COMMAND,
2482                        BNX2_NVM_COMMAND_WREN | BNX2_NVM_COMMAND_DOIT);
2483
2484                 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2485                         udelay(5);
2486
2487                         val = REG_RD(bp, BNX2_NVM_COMMAND);
2488                         if (val & BNX2_NVM_COMMAND_DONE)
2489                                 break;
2490                 }
2491
2492                 if (j >= NVRAM_TIMEOUT_COUNT)
2493                         return -EBUSY;
2494         }
2495         return 0;
2496 }
2497
2498 static void
2499 bnx2_disable_nvram_write(struct bnx2 *bp)
2500 {
2501         u32 val;
2502
2503         val = REG_RD(bp, BNX2_MISC_CFG);
2504         REG_WR(bp, BNX2_MISC_CFG, val & ~BNX2_MISC_CFG_NVM_WR_EN);
2505 }
2506
2507
2508 static void
2509 bnx2_enable_nvram_access(struct bnx2 *bp)
2510 {
2511         u32 val;
2512
2513         val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
2514         /* Enable both bits, even on read. */
2515         REG_WR(bp, BNX2_NVM_ACCESS_ENABLE,
2516                val | BNX2_NVM_ACCESS_ENABLE_EN | BNX2_NVM_ACCESS_ENABLE_WR_EN);
2517 }
2518
2519 static void
2520 bnx2_disable_nvram_access(struct bnx2 *bp)
2521 {
2522         u32 val;
2523
2524         val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
2525         /* Disable both bits, even after read. */
2526         REG_WR(bp, BNX2_NVM_ACCESS_ENABLE,
2527                 val & ~(BNX2_NVM_ACCESS_ENABLE_EN |
2528                         BNX2_NVM_ACCESS_ENABLE_WR_EN));
2529 }
2530
2531 static int
2532 bnx2_nvram_erase_page(struct bnx2 *bp, u32 offset)
2533 {
2534         u32 cmd;
2535         int j;
2536
2537         if (bp->flash_info->buffered)
2538                 /* Buffered flash, no erase needed */
2539                 return 0;
2540
2541         /* Build an erase command */
2542         cmd = BNX2_NVM_COMMAND_ERASE | BNX2_NVM_COMMAND_WR |
2543               BNX2_NVM_COMMAND_DOIT;
2544
2545         /* Need to clear DONE bit separately. */
2546         REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
2547
2548         /* Address of the NVRAM to read from. */
2549         REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
2550
2551         /* Issue an erase command. */
2552         REG_WR(bp, BNX2_NVM_COMMAND, cmd);
2553
2554         /* Wait for completion. */
2555         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2556                 u32 val;
2557
2558                 udelay(5);
2559
2560                 val = REG_RD(bp, BNX2_NVM_COMMAND);
2561                 if (val & BNX2_NVM_COMMAND_DONE)
2562                         break;
2563         }
2564
2565         if (j >= NVRAM_TIMEOUT_COUNT)
2566                 return -EBUSY;
2567
2568         return 0;
2569 }
2570
2571 static int
2572 bnx2_nvram_read_dword(struct bnx2 *bp, u32 offset, u8 *ret_val, u32 cmd_flags)
2573 {
2574         u32 cmd;
2575         int j;
2576
2577         /* Build the command word. */
2578         cmd = BNX2_NVM_COMMAND_DOIT | cmd_flags;
2579
2580         /* Calculate an offset of a buffered flash. */
2581         if (bp->flash_info->buffered) {
2582                 offset = ((offset / bp->flash_info->page_size) <<
2583                            bp->flash_info->page_bits) +
2584                           (offset % bp->flash_info->page_size);
2585         }
2586
2587         /* Need to clear DONE bit separately. */
2588         REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
2589
2590         /* Address of the NVRAM to read from. */
2591         REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
2592
2593         /* Issue a read command. */
2594         REG_WR(bp, BNX2_NVM_COMMAND, cmd);
2595
2596         /* Wait for completion. */
2597         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2598                 u32 val;
2599
2600                 udelay(5);
2601
2602                 val = REG_RD(bp, BNX2_NVM_COMMAND);
2603                 if (val & BNX2_NVM_COMMAND_DONE) {
2604                         val = REG_RD(bp, BNX2_NVM_READ);
2605
2606                         val = be32_to_cpu(val);
2607                         memcpy(ret_val, &val, 4);
2608                         break;
2609                 }
2610         }
2611         if (j >= NVRAM_TIMEOUT_COUNT)
2612                 return -EBUSY;
2613
2614         return 0;
2615 }
2616
2617
2618 static int
2619 bnx2_nvram_write_dword(struct bnx2 *bp, u32 offset, u8 *val, u32 cmd_flags)
2620 {
2621         u32 cmd, val32;
2622         int j;
2623
2624         /* Build the command word. */
2625         cmd = BNX2_NVM_COMMAND_DOIT | BNX2_NVM_COMMAND_WR | cmd_flags;
2626
2627         /* Calculate an offset of a buffered flash. */
2628         if (bp->flash_info->buffered) {
2629                 offset = ((offset / bp->flash_info->page_size) <<
2630                           bp->flash_info->page_bits) +
2631                          (offset % bp->flash_info->page_size);
2632         }
2633
2634         /* Need to clear DONE bit separately. */
2635         REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
2636
2637         memcpy(&val32, val, 4);
2638         val32 = cpu_to_be32(val32);
2639
2640         /* Write the data. */
2641         REG_WR(bp, BNX2_NVM_WRITE, val32);
2642
2643         /* Address of the NVRAM to write to. */
2644         REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
2645
2646         /* Issue the write command. */
2647         REG_WR(bp, BNX2_NVM_COMMAND, cmd);
2648
2649         /* Wait for completion. */
2650         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2651                 udelay(5);
2652
2653                 if (REG_RD(bp, BNX2_NVM_COMMAND) & BNX2_NVM_COMMAND_DONE)
2654                         break;
2655         }
2656         if (j >= NVRAM_TIMEOUT_COUNT)
2657                 return -EBUSY;
2658
2659         return 0;
2660 }
2661
2662 static int
2663 bnx2_init_nvram(struct bnx2 *bp)
2664 {
2665         u32 val;
2666         int j, entry_count, rc;
2667         struct flash_spec *flash;
2668
2669         /* Determine the selected interface. */
2670         val = REG_RD(bp, BNX2_NVM_CFG1);
2671
2672         entry_count = sizeof(flash_table) / sizeof(struct flash_spec);
2673
2674         rc = 0;
2675         if (val & 0x40000000) {
2676
2677                 /* Flash interface has been reconfigured */
2678                 for (j = 0, flash = &flash_table[0]; j < entry_count;
2679                      j++, flash++) {
2680                         if ((val & FLASH_BACKUP_STRAP_MASK) ==
2681                             (flash->config1 & FLASH_BACKUP_STRAP_MASK)) {
2682                                 bp->flash_info = flash;
2683                                 break;
2684                         }
2685                 }
2686         }
2687         else {
2688                 u32 mask;
2689                 /* Not yet been reconfigured */
2690
2691                 if (val & (1 << 23))
2692                         mask = FLASH_BACKUP_STRAP_MASK;
2693                 else
2694                         mask = FLASH_STRAP_MASK;
2695
2696                 for (j = 0, flash = &flash_table[0]; j < entry_count;
2697                         j++, flash++) {
2698
2699                         if ((val & mask) == (flash->strapping & mask)) {
2700                                 bp->flash_info = flash;
2701
2702                                 /* Request access to the flash interface. */
2703                                 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
2704                                         return rc;
2705
2706                                 /* Enable access to flash interface */
2707                                 bnx2_enable_nvram_access(bp);
2708
2709                                 /* Reconfigure the flash interface */
2710                                 REG_WR(bp, BNX2_NVM_CFG1, flash->config1);
2711                                 REG_WR(bp, BNX2_NVM_CFG2, flash->config2);
2712                                 REG_WR(bp, BNX2_NVM_CFG3, flash->config3);
2713                                 REG_WR(bp, BNX2_NVM_WRITE1, flash->write1);
2714
2715                                 /* Disable access to flash interface */
2716                                 bnx2_disable_nvram_access(bp);
2717                                 bnx2_release_nvram_lock(bp);
2718
2719                                 break;
2720                         }
2721                 }
2722         } /* if (val & 0x40000000) */
2723
2724         if (j == entry_count) {
2725                 bp->flash_info = NULL;
2726                 printk(KERN_ALERT PFX "Unknown flash/EEPROM type.\n");
2727                 rc = -ENODEV;
2728         }
2729
2730         return rc;
2731 }
2732
2733 static int
2734 bnx2_nvram_read(struct bnx2 *bp, u32 offset, u8 *ret_buf,
2735                 int buf_size)
2736 {
2737         int rc = 0;
2738         u32 cmd_flags, offset32, len32, extra;
2739
2740         if (buf_size == 0)
2741                 return 0;
2742
2743         /* Request access to the flash interface. */
2744         if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
2745                 return rc;
2746
2747         /* Enable access to flash interface */
2748         bnx2_enable_nvram_access(bp);
2749
2750         len32 = buf_size;
2751         offset32 = offset;
2752         extra = 0;
2753
2754         cmd_flags = 0;
2755
2756         if (offset32 & 3) {
2757                 u8 buf[4];
2758                 u32 pre_len;
2759
2760                 offset32 &= ~3;
2761                 pre_len = 4 - (offset & 3);
2762
2763                 if (pre_len >= len32) {
2764                         pre_len = len32;
2765                         cmd_flags = BNX2_NVM_COMMAND_FIRST |
2766                                     BNX2_NVM_COMMAND_LAST;
2767                 }
2768                 else {
2769                         cmd_flags = BNX2_NVM_COMMAND_FIRST;
2770                 }
2771
2772                 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
2773
2774                 if (rc)
2775                         return rc;
2776
2777                 memcpy(ret_buf, buf + (offset & 3), pre_len);
2778
2779                 offset32 += 4;
2780                 ret_buf += pre_len;
2781                 len32 -= pre_len;
2782         }
2783         if (len32 & 3) {
2784                 extra = 4 - (len32 & 3);
2785                 len32 = (len32 + 4) & ~3;
2786         }
2787
2788         if (len32 == 4) {
2789                 u8 buf[4];
2790
2791                 if (cmd_flags)
2792                         cmd_flags = BNX2_NVM_COMMAND_LAST;
2793                 else
2794                         cmd_flags = BNX2_NVM_COMMAND_FIRST |
2795                                     BNX2_NVM_COMMAND_LAST;
2796
2797                 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
2798
2799                 memcpy(ret_buf, buf, 4 - extra);
2800         }
2801         else if (len32 > 0) {
2802                 u8 buf[4];
2803
2804                 /* Read the first word. */
2805                 if (cmd_flags)
2806                         cmd_flags = 0;
2807                 else
2808                         cmd_flags = BNX2_NVM_COMMAND_FIRST;
2809
2810                 rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, cmd_flags);
2811
2812                 /* Advance to the next dword. */
2813                 offset32 += 4;
2814                 ret_buf += 4;
2815                 len32 -= 4;
2816
2817                 while (len32 > 4 && rc == 0) {
2818                         rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, 0);
2819
2820                         /* Advance to the next dword. */
2821                         offset32 += 4;
2822                         ret_buf += 4;
2823                         len32 -= 4;
2824                 }
2825
2826                 if (rc)
2827                         return rc;
2828
2829                 cmd_flags = BNX2_NVM_COMMAND_LAST;
2830                 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
2831
2832                 memcpy(ret_buf, buf, 4 - extra);
2833         }
2834
2835         /* Disable access to flash interface */
2836         bnx2_disable_nvram_access(bp);
2837
2838         bnx2_release_nvram_lock(bp);
2839
2840         return rc;
2841 }
2842
2843 static int
2844 bnx2_nvram_write(struct bnx2 *bp, u32 offset, u8 *data_buf,
2845                 int buf_size)
2846 {
2847         u32 written, offset32, len32;
2848         u8 *buf, start[4], end[4];
2849         int rc = 0;
2850         int align_start, align_end;
2851
2852         buf = data_buf;
2853         offset32 = offset;
2854         len32 = buf_size;
2855         align_start = align_end = 0;
2856
2857         if ((align_start = (offset32 & 3))) {
2858                 offset32 &= ~3;
2859                 len32 += align_start;
2860                 if ((rc = bnx2_nvram_read(bp, offset32, start, 4)))
2861                         return rc;
2862         }
2863
2864         if (len32 & 3) {
2865                 if ((len32 > 4) || !align_start) {
2866                         align_end = 4 - (len32 & 3);
2867                         len32 += align_end;
2868                         if ((rc = bnx2_nvram_read(bp, offset32 + len32 - 4,
2869                                 end, 4))) {
2870                                 return rc;
2871                         }
2872                 }
2873         }
2874
2875         if (align_start || align_end) {
2876                 buf = kmalloc(len32, GFP_KERNEL);
2877                 if (buf == 0)
2878                         return -ENOMEM;
2879                 if (align_start) {
2880                         memcpy(buf, start, 4);
2881                 }
2882                 if (align_end) {
2883                         memcpy(buf + len32 - 4, end, 4);
2884                 }
2885                 memcpy(buf + align_start, data_buf, buf_size);
2886         }
2887
2888         written = 0;
2889         while ((written < len32) && (rc == 0)) {
2890                 u32 page_start, page_end, data_start, data_end;
2891                 u32 addr, cmd_flags;
2892                 int i;
2893                 u8 flash_buffer[264];
2894
2895                 /* Find the page_start addr */
2896                 page_start = offset32 + written;
2897                 page_start -= (page_start % bp->flash_info->page_size);
2898                 /* Find the page_end addr */
2899                 page_end = page_start + bp->flash_info->page_size;
2900                 /* Find the data_start addr */
2901                 data_start = (written == 0) ? offset32 : page_start;
2902                 /* Find the data_end addr */
2903                 data_end = (page_end > offset32 + len32) ?
2904                         (offset32 + len32) : page_end;
2905
2906                 /* Request access to the flash interface. */
2907                 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
2908                         goto nvram_write_end;
2909
2910                 /* Enable access to flash interface */
2911                 bnx2_enable_nvram_access(bp);
2912
2913                 cmd_flags = BNX2_NVM_COMMAND_FIRST;
2914                 if (bp->flash_info->buffered == 0) {
2915                         int j;
2916
2917                         /* Read the whole page into the buffer
2918                          * (non-buffer flash only) */
2919                         for (j = 0; j < bp->flash_info->page_size; j += 4) {
2920                                 if (j == (bp->flash_info->page_size - 4)) {
2921                                         cmd_flags |= BNX2_NVM_COMMAND_LAST;
2922                                 }
2923                                 rc = bnx2_nvram_read_dword(bp,
2924                                         page_start + j,
2925                                         &flash_buffer[j],
2926                                         cmd_flags);
2927
2928                                 if (rc)
2929                                         goto nvram_write_end;
2930
2931                                 cmd_flags = 0;
2932                         }
2933                 }
2934
2935                 /* Enable writes to flash interface (unlock write-protect) */
2936                 if ((rc = bnx2_enable_nvram_write(bp)) != 0)
2937                         goto nvram_write_end;
2938
2939                 /* Erase the page */
2940                 if ((rc = bnx2_nvram_erase_page(bp, page_start)) != 0)
2941                         goto nvram_write_end;
2942
2943                 /* Re-enable the write again for the actual write */
2944                 bnx2_enable_nvram_write(bp);
2945
2946                 /* Loop to write back the buffer data from page_start to
2947                  * data_start */
2948                 i = 0;
2949                 if (bp->flash_info->buffered == 0) {
2950                         for (addr = page_start; addr < data_start;
2951                                 addr += 4, i += 4) {
2952
2953                                 rc = bnx2_nvram_write_dword(bp, addr,
2954                                         &flash_buffer[i], cmd_flags);
2955
2956                                 if (rc != 0)
2957                                         goto nvram_write_end;
2958
2959                                 cmd_flags = 0;
2960                         }
2961                 }
2962
2963                 /* Loop to write the new data from data_start to data_end */
2964                 for (addr = data_start; addr < data_end; addr += 4, i++) {
2965                         if ((addr == page_end - 4) ||
2966                                 ((bp->flash_info->buffered) &&
2967                                  (addr == data_end - 4))) {
2968
2969                                 cmd_flags |= BNX2_NVM_COMMAND_LAST;
2970                         }
2971                         rc = bnx2_nvram_write_dword(bp, addr, buf,
2972                                 cmd_flags);
2973
2974                         if (rc != 0)
2975                                 goto nvram_write_end;
2976
2977                         cmd_flags = 0;
2978                         buf += 4;
2979                 }
2980
2981                 /* Loop to write back the buffer data from data_end
2982                  * to page_end */
2983                 if (bp->flash_info->buffered == 0) {
2984                         for (addr = data_end; addr < page_end;
2985                                 addr += 4, i += 4) {
2986
2987                                 if (addr == page_end-4) {
2988                                         cmd_flags = BNX2_NVM_COMMAND_LAST;
2989                                 }
2990                                 rc = bnx2_nvram_write_dword(bp, addr,
2991                                         &flash_buffer[i], cmd_flags);
2992
2993                                 if (rc != 0)
2994                                         goto nvram_write_end;
2995
2996                                 cmd_flags = 0;
2997                         }
2998                 }
2999
3000                 /* Disable writes to flash interface (lock write-protect) */
3001                 bnx2_disable_nvram_write(bp);
3002
3003                 /* Disable access to flash interface */
3004                 bnx2_disable_nvram_access(bp);
3005                 bnx2_release_nvram_lock(bp);
3006
3007                 /* Increment written */
3008                 written += data_end - data_start;
3009         }
3010
3011 nvram_write_end:
3012         if (align_start || align_end)
3013                 kfree(buf);
3014         return rc;
3015 }
3016
3017 static int
3018 bnx2_reset_chip(struct bnx2 *bp, u32 reset_code)
3019 {
3020         u32 val;
3021         int i, rc = 0;
3022
3023         /* Wait for the current PCI transaction to complete before
3024          * issuing a reset. */
3025         REG_WR(bp, BNX2_MISC_ENABLE_CLR_BITS,
3026                BNX2_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE |
3027                BNX2_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE |
3028                BNX2_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE |
3029                BNX2_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE);
3030         val = REG_RD(bp, BNX2_MISC_ENABLE_CLR_BITS);
3031         udelay(5);
3032
3033         /* Wait for the firmware to tell us it is ok to issue a reset. */
3034         bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT0 | reset_code, 1);
3035
3036         /* Deposit a driver reset signature so the firmware knows that
3037          * this is a soft reset. */
3038         REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_RESET_SIGNATURE,
3039                    BNX2_DRV_RESET_SIGNATURE_MAGIC);
3040
3041         /* Do a dummy read to force the chip to complete all current transaction
3042          * before we issue a reset. */
3043         val = REG_RD(bp, BNX2_MISC_ID);
3044
3045         val = BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
3046               BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
3047               BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
3048
3049         /* Chip reset. */
3050         REG_WR(bp, BNX2_PCICFG_MISC_CONFIG, val);
3051
3052         if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
3053             (CHIP_ID(bp) == CHIP_ID_5706_A1))
3054                 msleep(15);
3055
3056         /* Reset takes approximate 30 usec */
3057         for (i = 0; i < 10; i++) {
3058                 val = REG_RD(bp, BNX2_PCICFG_MISC_CONFIG);
3059                 if ((val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
3060                             BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0) {
3061                         break;
3062                 }
3063                 udelay(10);
3064         }
3065
3066         if (val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
3067                    BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) {
3068                 printk(KERN_ERR PFX "Chip reset did not complete\n");
3069                 return -EBUSY;
3070         }
3071
3072         /* Make sure byte swapping is properly configured. */
3073         val = REG_RD(bp, BNX2_PCI_SWAP_DIAG0);
3074         if (val != 0x01020304) {
3075                 printk(KERN_ERR PFX "Chip not in correct endian mode\n");
3076                 return -ENODEV;
3077         }
3078
3079         /* Wait for the firmware to finish its initialization. */
3080         rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT1 | reset_code, 0);
3081         if (rc)
3082                 return rc;
3083
3084         if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
3085                 /* Adjust the voltage regular to two steps lower.  The default
3086                  * of this register is 0x0000000e. */
3087                 REG_WR(bp, BNX2_MISC_VREG_CONTROL, 0x000000fa);
3088
3089                 /* Remove bad rbuf memory from the free pool. */
3090                 rc = bnx2_alloc_bad_rbuf(bp);
3091         }
3092
3093         return rc;
3094 }
3095
3096 static int
3097 bnx2_init_chip(struct bnx2 *bp)
3098 {
3099         u32 val;
3100         int rc;
3101
3102         /* Make sure the interrupt is not active. */
3103         REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
3104
3105         val = BNX2_DMA_CONFIG_DATA_BYTE_SWAP |
3106               BNX2_DMA_CONFIG_DATA_WORD_SWAP |
3107 #ifdef __BIG_ENDIAN
3108               BNX2_DMA_CONFIG_CNTL_BYTE_SWAP |
3109 #endif
3110               BNX2_DMA_CONFIG_CNTL_WORD_SWAP |
3111               DMA_READ_CHANS << 12 |
3112               DMA_WRITE_CHANS << 16;
3113
3114         val |= (0x2 << 20) | (1 << 11);
3115
3116         if ((bp->flags & PCIX_FLAG) && (bp->bus_speed_mhz == 133))
3117                 val |= (1 << 23);
3118
3119         if ((CHIP_NUM(bp) == CHIP_NUM_5706) &&
3120             (CHIP_ID(bp) != CHIP_ID_5706_A0) && !(bp->flags & PCIX_FLAG))
3121                 val |= BNX2_DMA_CONFIG_CNTL_PING_PONG_DMA;
3122
3123         REG_WR(bp, BNX2_DMA_CONFIG, val);
3124
3125         if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
3126                 val = REG_RD(bp, BNX2_TDMA_CONFIG);
3127                 val |= BNX2_TDMA_CONFIG_ONE_DMA;
3128                 REG_WR(bp, BNX2_TDMA_CONFIG, val);
3129         }
3130
3131         if (bp->flags & PCIX_FLAG) {
3132                 u16 val16;
3133
3134                 pci_read_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
3135                                      &val16);
3136                 pci_write_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
3137                                       val16 & ~PCI_X_CMD_ERO);
3138         }
3139
3140         REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
3141                BNX2_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE |
3142                BNX2_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE |
3143                BNX2_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE);
3144
3145         /* Initialize context mapping and zero out the quick contexts.  The
3146          * context block must have already been enabled. */
3147         bnx2_init_context(bp);
3148
3149         bnx2_init_cpus(bp);
3150         bnx2_init_nvram(bp);
3151
3152         bnx2_set_mac_addr(bp);
3153
3154         val = REG_RD(bp, BNX2_MQ_CONFIG);
3155         val &= ~BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE;
3156         val |= BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_256;
3157         REG_WR(bp, BNX2_MQ_CONFIG, val);
3158
3159         val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE);
3160         REG_WR(bp, BNX2_MQ_KNL_BYP_WIND_START, val);
3161         REG_WR(bp, BNX2_MQ_KNL_WIND_END, val);
3162
3163         val = (BCM_PAGE_BITS - 8) << 24;
3164         REG_WR(bp, BNX2_RV2P_CONFIG, val);
3165
3166         /* Configure page size. */
3167         val = REG_RD(bp, BNX2_TBDR_CONFIG);
3168         val &= ~BNX2_TBDR_CONFIG_PAGE_SIZE;
3169         val |= (BCM_PAGE_BITS - 8) << 24 | 0x40;
3170         REG_WR(bp, BNX2_TBDR_CONFIG, val);
3171
3172         val = bp->mac_addr[0] +
3173               (bp->mac_addr[1] << 8) +
3174               (bp->mac_addr[2] << 16) +
3175               bp->mac_addr[3] +
3176               (bp->mac_addr[4] << 8) +
3177               (bp->mac_addr[5] << 16);
3178         REG_WR(bp, BNX2_EMAC_BACKOFF_SEED, val);
3179
3180         /* Program the MTU.  Also include 4 bytes for CRC32. */
3181         val = bp->dev->mtu + ETH_HLEN + 4;
3182         if (val > (MAX_ETHERNET_PACKET_SIZE + 4))
3183                 val |= BNX2_EMAC_RX_MTU_SIZE_JUMBO_ENA;
3184         REG_WR(bp, BNX2_EMAC_RX_MTU_SIZE, val);
3185
3186         bp->last_status_idx = 0;
3187         bp->rx_mode = BNX2_EMAC_RX_MODE_SORT_MODE;
3188
3189         /* Set up how to generate a link change interrupt. */
3190         REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
3191
3192         REG_WR(bp, BNX2_HC_STATUS_ADDR_L,
3193                (u64) bp->status_blk_mapping & 0xffffffff);
3194         REG_WR(bp, BNX2_HC_STATUS_ADDR_H, (u64) bp->status_blk_mapping >> 32);
3195
3196         REG_WR(bp, BNX2_HC_STATISTICS_ADDR_L,
3197                (u64) bp->stats_blk_mapping & 0xffffffff);
3198         REG_WR(bp, BNX2_HC_STATISTICS_ADDR_H,
3199                (u64) bp->stats_blk_mapping >> 32);
3200
3201         REG_WR(bp, BNX2_HC_TX_QUICK_CONS_TRIP,
3202                (bp->tx_quick_cons_trip_int << 16) | bp->tx_quick_cons_trip);
3203
3204         REG_WR(bp, BNX2_HC_RX_QUICK_CONS_TRIP,
3205                (bp->rx_quick_cons_trip_int << 16) | bp->rx_quick_cons_trip);
3206
3207         REG_WR(bp, BNX2_HC_COMP_PROD_TRIP,
3208                (bp->comp_prod_trip_int << 16) | bp->comp_prod_trip);
3209
3210         REG_WR(bp, BNX2_HC_TX_TICKS, (bp->tx_ticks_int << 16) | bp->tx_ticks);
3211
3212         REG_WR(bp, BNX2_HC_RX_TICKS, (bp->rx_ticks_int << 16) | bp->rx_ticks);
3213
3214         REG_WR(bp, BNX2_HC_COM_TICKS,
3215                (bp->com_ticks_int << 16) | bp->com_ticks);
3216
3217         REG_WR(bp, BNX2_HC_CMD_TICKS,
3218                (bp->cmd_ticks_int << 16) | bp->cmd_ticks);
3219
3220         REG_WR(bp, BNX2_HC_STATS_TICKS, bp->stats_ticks & 0xffff00);
3221         REG_WR(bp, BNX2_HC_STAT_COLLECT_TICKS, 0xbb8);  /* 3ms */
3222
3223         if (CHIP_ID(bp) == CHIP_ID_5706_A1)
3224                 REG_WR(bp, BNX2_HC_CONFIG, BNX2_HC_CONFIG_COLLECT_STATS);
3225         else {
3226                 REG_WR(bp, BNX2_HC_CONFIG, BNX2_HC_CONFIG_RX_TMR_MODE |
3227                        BNX2_HC_CONFIG_TX_TMR_MODE |
3228                        BNX2_HC_CONFIG_COLLECT_STATS);
3229         }
3230
3231         /* Clear internal stats counters. */
3232         REG_WR(bp, BNX2_HC_COMMAND, BNX2_HC_COMMAND_CLR_STAT_NOW);
3233
3234         REG_WR(bp, BNX2_HC_ATTN_BITS_ENABLE, STATUS_ATTN_BITS_LINK_STATE);
3235
3236         if (REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_FEATURE) &
3237             BNX2_PORT_FEATURE_ASF_ENABLED)
3238                 bp->flags |= ASF_ENABLE_FLAG;
3239
3240         /* Initialize the receive filter. */
3241         bnx2_set_rx_mode(bp->dev);
3242
3243         rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT2 | BNX2_DRV_MSG_CODE_RESET,
3244                           0);
3245
3246         REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS, 0x5ffffff);
3247         REG_RD(bp, BNX2_MISC_ENABLE_SET_BITS);
3248
3249         udelay(20);
3250
3251         return rc;
3252 }
3253
3254
3255 static void
3256 bnx2_init_tx_ring(struct bnx2 *bp)
3257 {
3258         struct tx_bd *txbd;
3259         u32 val;
3260
3261         txbd = &bp->tx_desc_ring[MAX_TX_DESC_CNT];
3262
3263         txbd->tx_bd_haddr_hi = (u64) bp->tx_desc_mapping >> 32;
3264         txbd->tx_bd_haddr_lo = (u64) bp->tx_desc_mapping & 0xffffffff;
3265
3266         bp->tx_prod = 0;
3267         bp->tx_cons = 0;
3268         bp->hw_tx_cons = 0;
3269         bp->tx_prod_bseq = 0;
3270
3271         val = BNX2_L2CTX_TYPE_TYPE_L2;
3272         val |= BNX2_L2CTX_TYPE_SIZE_L2;
3273         CTX_WR(bp, GET_CID_ADDR(TX_CID), BNX2_L2CTX_TYPE, val);
3274
3275         val = BNX2_L2CTX_CMD_TYPE_TYPE_L2;
3276         val |= 8 << 16;
3277         CTX_WR(bp, GET_CID_ADDR(TX_CID), BNX2_L2CTX_CMD_TYPE, val);
3278
3279         val = (u64) bp->tx_desc_mapping >> 32;
3280         CTX_WR(bp, GET_CID_ADDR(TX_CID), BNX2_L2CTX_TBDR_BHADDR_HI, val);
3281
3282         val = (u64) bp->tx_desc_mapping & 0xffffffff;
3283         CTX_WR(bp, GET_CID_ADDR(TX_CID), BNX2_L2CTX_TBDR_BHADDR_LO, val);
3284 }
3285
3286 static void
3287 bnx2_init_rx_ring(struct bnx2 *bp)
3288 {
3289         struct rx_bd *rxbd;
3290         int i;
3291         u16 prod, ring_prod;
3292         u32 val;
3293
3294         /* 8 for CRC and VLAN */
3295         bp->rx_buf_use_size = bp->dev->mtu + ETH_HLEN + bp->rx_offset + 8;
3296         /* 8 for alignment */
3297         bp->rx_buf_size = bp->rx_buf_use_size + 8;
3298
3299         ring_prod = prod = bp->rx_prod = 0;
3300         bp->rx_cons = 0;
3301         bp->hw_rx_cons = 0;
3302         bp->rx_prod_bseq = 0;
3303
3304         rxbd = &bp->rx_desc_ring[0];
3305         for (i = 0; i < MAX_RX_DESC_CNT; i++, rxbd++) {
3306                 rxbd->rx_bd_len = bp->rx_buf_use_size;
3307                 rxbd->rx_bd_flags = RX_BD_FLAGS_START | RX_BD_FLAGS_END;
3308         }
3309
3310         rxbd->rx_bd_haddr_hi = (u64) bp->rx_desc_mapping >> 32;
3311         rxbd->rx_bd_haddr_lo = (u64) bp->rx_desc_mapping & 0xffffffff;
3312
3313         val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE;
3314         val |= BNX2_L2CTX_CTX_TYPE_SIZE_L2;
3315         val |= 0x02 << 8;
3316         CTX_WR(bp, GET_CID_ADDR(RX_CID), BNX2_L2CTX_CTX_TYPE, val);
3317
3318         val = (u64) bp->rx_desc_mapping >> 32;
3319         CTX_WR(bp, GET_CID_ADDR(RX_CID), BNX2_L2CTX_NX_BDHADDR_HI, val);
3320
3321         val = (u64) bp->rx_desc_mapping & 0xffffffff;
3322         CTX_WR(bp, GET_CID_ADDR(RX_CID), BNX2_L2CTX_NX_BDHADDR_LO, val);
3323
3324         for ( ;ring_prod < bp->rx_ring_size; ) {
3325                 if (bnx2_alloc_rx_skb(bp, ring_prod) < 0) {
3326                         break;
3327                 }
3328                 prod = NEXT_RX_BD(prod);
3329                 ring_prod = RX_RING_IDX(prod);
3330         }
3331         bp->rx_prod = prod;
3332
3333         REG_WR16(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BDIDX, prod);
3334
3335         REG_WR(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BSEQ, bp->rx_prod_bseq);
3336 }
3337
3338 static void
3339 bnx2_free_tx_skbs(struct bnx2 *bp)
3340 {
3341         int i;
3342
3343         if (bp->tx_buf_ring == NULL)
3344                 return;
3345
3346         for (i = 0; i < TX_DESC_CNT; ) {
3347                 struct sw_bd *tx_buf = &bp->tx_buf_ring[i];
3348                 struct sk_buff *skb = tx_buf->skb;
3349                 int j, last;
3350
3351                 if (skb == NULL) {
3352                         i++;
3353                         continue;
3354                 }
3355
3356                 pci_unmap_single(bp->pdev, pci_unmap_addr(tx_buf, mapping),
3357                         skb_headlen(skb), PCI_DMA_TODEVICE);
3358
3359                 tx_buf->skb = NULL;
3360
3361                 last = skb_shinfo(skb)->nr_frags;
3362                 for (j = 0; j < last; j++) {
3363                         tx_buf = &bp->tx_buf_ring[i + j + 1];
3364                         pci_unmap_page(bp->pdev,
3365                                 pci_unmap_addr(tx_buf, mapping),
3366                                 skb_shinfo(skb)->frags[j].size,
3367                                 PCI_DMA_TODEVICE);
3368                 }
3369                 dev_kfree_skb_any(skb);
3370                 i += j + 1;
3371         }
3372
3373 }
3374
3375 static void
3376 bnx2_free_rx_skbs(struct bnx2 *bp)
3377 {
3378         int i;
3379
3380         if (bp->rx_buf_ring == NULL)
3381                 return;
3382
3383         for (i = 0; i < RX_DESC_CNT; i++) {
3384                 struct sw_bd *rx_buf = &bp->rx_buf_ring[i];
3385                 struct sk_buff *skb = rx_buf->skb;
3386
3387                 if (skb == NULL)
3388                         continue;
3389
3390                 pci_unmap_single(bp->pdev, pci_unmap_addr(rx_buf, mapping),
3391                         bp->rx_buf_use_size, PCI_DMA_FROMDEVICE);
3392
3393                 rx_buf->skb = NULL;
3394
3395                 dev_kfree_skb_any(skb);
3396         }
3397 }
3398
3399 static void
3400 bnx2_free_skbs(struct bnx2 *bp)
3401 {
3402         bnx2_free_tx_skbs(bp);
3403         bnx2_free_rx_skbs(bp);
3404 }
3405
3406 static int
3407 bnx2_reset_nic(struct bnx2 *bp, u32 reset_code)
3408 {
3409         int rc;
3410
3411         rc = bnx2_reset_chip(bp, reset_code);
3412         bnx2_free_skbs(bp);
3413         if (rc)
3414                 return rc;
3415
3416         bnx2_init_chip(bp);
3417         bnx2_init_tx_ring(bp);
3418         bnx2_init_rx_ring(bp);
3419         return 0;
3420 }
3421
3422 static int
3423 bnx2_init_nic(struct bnx2 *bp)
3424 {
3425         int rc;
3426
3427         if ((rc = bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET)) != 0)
3428                 return rc;
3429
3430         bnx2_init_phy(bp);
3431         bnx2_set_link(bp);
3432         return 0;
3433 }
3434
3435 static int
3436 bnx2_test_registers(struct bnx2 *bp)
3437 {
3438         int ret;
3439         int i;
3440         static struct {
3441                 u16   offset;
3442                 u16   flags;
3443                 u32   rw_mask;
3444                 u32   ro_mask;
3445         } reg_tbl[] = {
3446                 { 0x006c, 0, 0x00000000, 0x0000003f },
3447                 { 0x0090, 0, 0xffffffff, 0x00000000 },
3448                 { 0x0094, 0, 0x00000000, 0x00000000 },
3449
3450                 { 0x0404, 0, 0x00003f00, 0x00000000 },
3451                 { 0x0418, 0, 0x00000000, 0xffffffff },
3452                 { 0x041c, 0, 0x00000000, 0xffffffff },
3453                 { 0x0420, 0, 0x00000000, 0x80ffffff },
3454                 { 0x0424, 0, 0x00000000, 0x00000000 },
3455                 { 0x0428, 0, 0x00000000, 0x00000001 },
3456                 { 0x0450, 0, 0x00000000, 0x0000ffff },
3457                 { 0x0454, 0, 0x00000000, 0xffffffff },
3458                 { 0x0458, 0, 0x00000000, 0xffffffff },
3459
3460                 { 0x0808, 0, 0x00000000, 0xffffffff },
3461                 { 0x0854, 0, 0x00000000, 0xffffffff },
3462                 { 0x0868, 0, 0x00000000, 0x77777777 },
3463                 { 0x086c, 0, 0x00000000, 0x77777777 },
3464                 { 0x0870, 0, 0x00000000, 0x77777777 },
3465                 { 0x0874, 0, 0x00000000, 0x77777777 },
3466
3467                 { 0x0c00, 0, 0x00000000, 0x00000001 },
3468                 { 0x0c04, 0, 0x00000000, 0x03ff0001 },
3469                 { 0x0c08, 0, 0x0f0ff073, 0x00000000 },
3470                 { 0x0c0c, 0, 0x00ffffff, 0x00000000 },
3471                 { 0x0c30, 0, 0x00000000, 0xffffffff },
3472                 { 0x0c34, 0, 0x00000000, 0xffffffff },
3473                 { 0x0c38, 0, 0x00000000, 0xffffffff },
3474                 { 0x0c3c, 0, 0x00000000, 0xffffffff },
3475                 { 0x0c40, 0, 0x00000000, 0xffffffff },
3476                 { 0x0c44, 0, 0x00000000, 0xffffffff },
3477                 { 0x0c48, 0, 0x00000000, 0x0007ffff },
3478                 { 0x0c4c, 0, 0x00000000, 0xffffffff },
3479                 { 0x0c50, 0, 0x00000000, 0xffffffff },
3480                 { 0x0c54, 0, 0x00000000, 0xffffffff },
3481                 { 0x0c58, 0, 0x00000000, 0xffffffff },
3482                 { 0x0c5c, 0, 0x00000000, 0xffffffff },
3483                 { 0x0c60, 0, 0x00000000, 0xffffffff },
3484                 { 0x0c64, 0, 0x00000000, 0xffffffff },
3485                 { 0x0c68, 0, 0x00000000, 0xffffffff },
3486                 { 0x0c6c, 0, 0x00000000, 0xffffffff },
3487                 { 0x0c70, 0, 0x00000000, 0xffffffff },
3488                 { 0x0c74, 0, 0x00000000, 0xffffffff },
3489                 { 0x0c78, 0, 0x00000000, 0xffffffff },
3490                 { 0x0c7c, 0, 0x00000000, 0xffffffff },
3491                 { 0x0c80, 0, 0x00000000, 0xffffffff },
3492                 { 0x0c84, 0, 0x00000000, 0xffffffff },
3493                 { 0x0c88, 0, 0x00000000, 0xffffffff },
3494                 { 0x0c8c, 0, 0x00000000, 0xffffffff },
3495                 { 0x0c90, 0, 0x00000000, 0xffffffff },
3496                 { 0x0c94, 0, 0x00000000, 0xffffffff },
3497                 { 0x0c98, 0, 0x00000000, 0xffffffff },
3498                 { 0x0c9c, 0, 0x00000000, 0xffffffff },
3499                 { 0x0ca0, 0, 0x00000000, 0xffffffff },
3500                 { 0x0ca4, 0, 0x00000000, 0xffffffff },
3501                 { 0x0ca8, 0, 0x00000000, 0x0007ffff },
3502                 { 0x0cac, 0, 0x00000000, 0xffffffff },
3503                 { 0x0cb0, 0, 0x00000000, 0xffffffff },
3504                 { 0x0cb4, 0, 0x00000000, 0xffffffff },
3505                 { 0x0cb8, 0, 0x00000000, 0xffffffff },
3506                 { 0x0cbc, 0, 0x00000000, 0xffffffff },
3507                 { 0x0cc0, 0, 0x00000000, 0xffffffff },
3508                 { 0x0cc4, 0, 0x00000000, 0xffffffff },
3509                 { 0x0cc8, 0, 0x00000000, 0xffffffff },
3510                 { 0x0ccc, 0, 0x00000000, 0xffffffff },
3511                 { 0x0cd0, 0, 0x00000000, 0xffffffff },
3512                 { 0x0cd4, 0, 0x00000000, 0xffffffff },
3513                 { 0x0cd8, 0, 0x00000000, 0xffffffff },
3514                 { 0x0cdc, 0, 0x00000000, 0xffffffff },
3515                 { 0x0ce0, 0, 0x00000000, 0xffffffff },
3516                 { 0x0ce4, 0, 0x00000000, 0xffffffff },
3517                 { 0x0ce8, 0, 0x00000000, 0xffffffff },
3518                 { 0x0cec, 0, 0x00000000, 0xffffffff },
3519                 { 0x0cf0, 0, 0x00000000, 0xffffffff },
3520                 { 0x0cf4, 0, 0x00000000, 0xffffffff },
3521                 { 0x0cf8, 0, 0x00000000, 0xffffffff },
3522                 { 0x0cfc, 0, 0x00000000, 0xffffffff },
3523                 { 0x0d00, 0, 0x00000000, 0xffffffff },
3524                 { 0x0d04, 0, 0x00000000, 0xffffffff },
3525
3526                 { 0x1000, 0, 0x00000000, 0x00000001 },
3527                 { 0x1004, 0, 0x00000000, 0x000f0001 },
3528                 { 0x1044, 0, 0x00000000, 0xffc003ff },
3529                 { 0x1080, 0, 0x00000000, 0x0001ffff },
3530                 { 0x1084, 0, 0x00000000, 0xffffffff },
3531                 { 0x1088, 0, 0x00000000, 0xffffffff },
3532                 { 0x108c, 0, 0x00000000, 0xffffffff },
3533                 { 0x1090, 0, 0x00000000, 0xffffffff },
3534                 { 0x1094, 0, 0x00000000, 0xffffffff },
3535                 { 0x1098, 0, 0x00000000, 0xffffffff },
3536                 { 0x109c, 0, 0x00000000, 0xffffffff },
3537                 { 0x10a0, 0, 0x00000000, 0xffffffff },
3538
3539                 { 0x1408, 0, 0x01c00800, 0x00000000 },
3540                 { 0x149c, 0, 0x8000ffff, 0x00000000 },
3541                 { 0x14a8, 0, 0x00000000, 0x000001ff },
3542                 { 0x14ac, 0, 0x0fffffff, 0x10000000 },
3543                 { 0x14b0, 0, 0x00000002, 0x00000001 },
3544                 { 0x14b8, 0, 0x00000000, 0x00000000 },
3545                 { 0x14c0, 0, 0x00000000, 0x00000009 },
3546                 { 0x14c4, 0, 0x00003fff, 0x00000000 },
3547                 { 0x14cc, 0, 0x00000000, 0x00000001 },
3548                 { 0x14d0, 0, 0xffffffff, 0x00000000 },
3549                 { 0x1500, 0, 0x00000000, 0xffffffff },
3550                 { 0x1504, 0, 0x00000000, 0xffffffff },
3551                 { 0x1508, 0, 0x00000000, 0xffffffff },
3552                 { 0x150c, 0, 0x00000000, 0xffffffff },
3553                 { 0x1510, 0, 0x00000000, 0xffffffff },
3554                 { 0x1514, 0, 0x00000000, 0xffffffff },
3555                 { 0x1518, 0, 0x00000000, 0xffffffff },
3556                 { 0x151c, 0, 0x00000000, 0xffffffff },
3557                 { 0x1520, 0, 0x00000000, 0xffffffff },
3558                 { 0x1524, 0, 0x00000000, 0xffffffff },
3559                 { 0x1528, 0, 0x00000000, 0xffffffff },
3560                 { 0x152c, 0, 0x00000000, 0xffffffff },
3561                 { 0x1530, 0, 0x00000000, 0xffffffff },
3562                 { 0x1534, 0, 0x00000000, 0xffffffff },
3563                 { 0x1538, 0, 0x00000000, 0xffffffff },
3564                 { 0x153c, 0, 0x00000000, 0xffffffff },
3565                 { 0x1540, 0, 0x00000000, 0xffffffff },
3566                 { 0x1544, 0, 0x00000000, 0xffffffff },
3567                 { 0x1548, 0, 0x00000000, 0xffffffff },
3568                 { 0x154c, 0, 0x00000000, 0xffffffff },
3569                 { 0x1550, 0, 0x00000000, 0xffffffff },
3570                 { 0x1554, 0, 0x00000000, 0xffffffff },
3571                 { 0x1558, 0, 0x00000000, 0xffffffff },
3572                 { 0x1600, 0, 0x00000000, 0xffffffff },
3573                 { 0x1604, 0, 0x00000000, 0xffffffff },
3574                 { 0x1608, 0, 0x00000000, 0xffffffff },
3575                 { 0x160c, 0, 0x00000000, 0xffffffff },
3576                 { 0x1610, 0, 0x00000000, 0xffffffff },
3577                 { 0x1614, 0, 0x00000000, 0xffffffff },
3578                 { 0x1618, 0, 0x00000000, 0xffffffff },
3579                 { 0x161c, 0, 0x00000000, 0xffffffff },
3580                 { 0x1620, 0, 0x00000000, 0xffffffff },
3581                 { 0x1624, 0, 0x00000000, 0xffffffff },
3582                 { 0x1628, 0, 0x00000000, 0xffffffff },
3583                 { 0x162c, 0, 0x00000000, 0xffffffff },
3584                 { 0x1630, 0, 0x00000000, 0xffffffff },
3585                 { 0x1634, 0, 0x00000000, 0xffffffff },
3586                 { 0x1638, 0, 0x00000000, 0xffffffff },
3587                 { 0x163c, 0, 0x00000000, 0xffffffff },
3588                 { 0x1640, 0, 0x00000000, 0xffffffff },
3589                 { 0x1644, 0, 0x00000000, 0xffffffff },
3590                 { 0x1648, 0, 0x00000000, 0xffffffff },
3591                 { 0x164c, 0, 0x00000000, 0xffffffff },
3592                 { 0x1650, 0, 0x00000000, 0xffffffff },
3593                 { 0x1654, 0, 0x00000000, 0xffffffff },
3594
3595                 { 0x1800, 0, 0x00000000, 0x00000001 },
3596                 { 0x1804, 0, 0x00000000, 0x00000003 },
3597                 { 0x1840, 0, 0x00000000, 0xffffffff },
3598                 { 0x1844, 0, 0x00000000, 0xffffffff },
3599                 { 0x1848, 0, 0x00000000, 0xffffffff },
3600                 { 0x184c, 0, 0x00000000, 0xffffffff },
3601                 { 0x1850, 0, 0x00000000, 0xffffffff },
3602                 { 0x1900, 0, 0x7ffbffff, 0x00000000 },
3603                 { 0x1904, 0, 0xffffffff, 0x00000000 },
3604                 { 0x190c, 0, 0xffffffff, 0x00000000 },
3605                 { 0x1914, 0, 0xffffffff, 0x00000000 },
3606                 { 0x191c, 0, 0xffffffff, 0x00000000 },
3607                 { 0x1924, 0, 0xffffffff, 0x00000000 },
3608                 { 0x192c, 0, 0xffffffff, 0x00000000 },
3609                 { 0x1934, 0, 0xffffffff, 0x00000000 },
3610                 { 0x193c, 0, 0xffffffff, 0x00000000 },
3611                 { 0x1944, 0, 0xffffffff, 0x00000000 },
3612                 { 0x194c, 0, 0xffffffff, 0x00000000 },
3613                 { 0x1954, 0, 0xffffffff, 0x00000000 },
3614                 { 0x195c, 0, 0xffffffff, 0x00000000 },
3615                 { 0x1964, 0, 0xffffffff, 0x00000000 },
3616                 { 0x196c, 0, 0xffffffff, 0x00000000 },
3617                 { 0x1974, 0, 0xffffffff, 0x00000000 },
3618                 { 0x197c, 0, 0xffffffff, 0x00000000 },
3619                 { 0x1980, 0, 0x0700ffff, 0x00000000 },
3620
3621                 { 0x1c00, 0, 0x00000000, 0x00000001 },
3622                 { 0x1c04, 0, 0x00000000, 0x00000003 },
3623                 { 0x1c08, 0, 0x0000000f, 0x00000000 },
3624                 { 0x1c40, 0, 0x00000000, 0xffffffff },
3625                 { 0x1c44, 0, 0x00000000, 0xffffffff },
3626                 { 0x1c48, 0, 0x00000000, 0xffffffff },
3627                 { 0x1c4c, 0, 0x00000000, 0xffffffff },
3628                 { 0x1c50, 0, 0x00000000, 0xffffffff },
3629                 { 0x1d00, 0, 0x7ffbffff, 0x00000000 },
3630                 { 0x1d04, 0, 0xffffffff, 0x00000000 },
3631                 { 0x1d0c, 0, 0xffffffff, 0x00000000 },
3632                 { 0x1d14, 0, 0xffffffff, 0x00000000 },
3633                 { 0x1d1c, 0, 0xffffffff, 0x00000000 },
3634                 { 0x1d24, 0, 0xffffffff, 0x00000000 },
3635                 { 0x1d2c, 0, 0xffffffff, 0x00000000 },
3636                 { 0x1d34, 0, 0xffffffff, 0x00000000 },
3637                 { 0x1d3c, 0, 0xffffffff, 0x00000000 },
3638                 { 0x1d44, 0, 0xffffffff, 0x00000000 },
3639                 { 0x1d4c, 0, 0xffffffff, 0x00000000 },
3640                 { 0x1d54, 0, 0xffffffff, 0x00000000 },
3641                 { 0x1d5c, 0, 0xffffffff, 0x00000000 },
3642                 { 0x1d64, 0, 0xffffffff, 0x00000000 },
3643                 { 0x1d6c, 0, 0xffffffff, 0x00000000 },
3644                 { 0x1d74, 0, 0xffffffff, 0x00000000 },
3645                 { 0x1d7c, 0, 0xffffffff, 0x00000000 },
3646                 { 0x1d80, 0, 0x0700ffff, 0x00000000 },
3647
3648                 { 0x2004, 0, 0x00000000, 0x0337000f },
3649                 { 0x2008, 0, 0xffffffff, 0x00000000 },
3650                 { 0x200c, 0, 0xffffffff, 0x00000000 },
3651                 { 0x2010, 0, 0xffffffff, 0x00000000 },
3652                 { 0x2014, 0, 0x801fff80, 0x00000000 },
3653                 { 0x2018, 0, 0x000003ff, 0x00000000 },
3654
3655                 { 0x2800, 0, 0x00000000, 0x00000001 },
3656                 { 0x2804, 0, 0x00000000, 0x00003f01 },
3657                 { 0x2808, 0, 0x0f3f3f03, 0x00000000 },
3658                 { 0x2810, 0, 0xffff0000, 0x00000000 },
3659                 { 0x2814, 0, 0xffff0000, 0x00000000 },
3660                 { 0x2818, 0, 0xffff0000, 0x00000000 },
3661                 { 0x281c, 0, 0xffff0000, 0x00000000 },
3662                 { 0x2834, 0, 0xffffffff, 0x00000000 },
3663                 { 0x2840, 0, 0x00000000, 0xffffffff },
3664                 { 0x2844, 0, 0x00000000, 0xffffffff },
3665                 { 0x2848, 0, 0xffffffff, 0x00000000 },
3666                 { 0x284c, 0, 0xf800f800, 0x07ff07ff },
3667
3668                 { 0x2c00, 0, 0x00000000, 0x00000011 },
3669                 { 0x2c04, 0, 0x00000000, 0x00030007 },
3670
3671                 { 0x3000, 0, 0x00000000, 0x00000001 },
3672                 { 0x3004, 0, 0x00000000, 0x007007ff },
3673                 { 0x3008, 0, 0x00000003, 0x00000000 },
3674                 { 0x300c, 0, 0xffffffff, 0x00000000 },
3675                 { 0x3010, 0, 0xffffffff, 0x00000000 },
3676                 { 0x3014, 0, 0xffffffff, 0x00000000 },
3677                 { 0x3034, 0, 0xffffffff, 0x00000000 },
3678                 { 0x3038, 0, 0xffffffff, 0x00000000 },
3679                 { 0x3050, 0, 0x00000001, 0x00000000 },
3680
3681                 { 0x3c00, 0, 0x00000000, 0x00000001 },
3682                 { 0x3c04, 0, 0x00000000, 0x00070000 },
3683                 { 0x3c08, 0, 0x00007f71, 0x07f00000 },
3684                 { 0x3c0c, 0, 0x1f3ffffc, 0x00000000 },
3685                 { 0x3c10, 0, 0xffffffff, 0x00000000 },
3686                 { 0x3c14, 0, 0x00000000, 0xffffffff },
3687                 { 0x3c18, 0, 0x00000000, 0xffffffff },
3688                 { 0x3c1c, 0, 0xfffff000, 0x00000000 },
3689                 { 0x3c20, 0, 0xffffff00, 0x00000000 },
3690                 { 0x3c24, 0, 0xffffffff, 0x00000000 },
3691                 { 0x3c28, 0, 0xffffffff, 0x00000000 },
3692                 { 0x3c2c, 0, 0xffffffff, 0x00000000 },
3693                 { 0x3c30, 0, 0xffffffff, 0x00000000 },
3694                 { 0x3c34, 0, 0xffffffff, 0x00000000 },
3695                 { 0x3c38, 0, 0xffffffff, 0x00000000 },
3696                 { 0x3c3c, 0, 0xffffffff, 0x00000000 },
3697                 { 0x3c40, 0, 0xffffffff, 0x00000000 },
3698                 { 0x3c44, 0, 0xffffffff, 0x00000000 },
3699                 { 0x3c48, 0, 0xffffffff, 0x00000000 },
3700                 { 0x3c4c, 0, 0xffffffff, 0x00000000 },
3701                 { 0x3c50, 0, 0xffffffff, 0x00000000 },
3702                 { 0x3c54, 0, 0xffffffff, 0x00000000 },
3703                 { 0x3c58, 0, 0xffffffff, 0x00000000 },
3704                 { 0x3c5c, 0, 0xffffffff, 0x00000000 },
3705                 { 0x3c60, 0, 0xffffffff, 0x00000000 },
3706                 { 0x3c64, 0, 0xffffffff, 0x00000000 },
3707                 { 0x3c68, 0, 0xffffffff, 0x00000000 },
3708                 { 0x3c6c, 0, 0xffffffff, 0x00000000 },
3709                 { 0x3c70, 0, 0xffffffff, 0x00000000 },
3710                 { 0x3c74, 0, 0x0000003f, 0x00000000 },
3711                 { 0x3c78, 0, 0x00000000, 0x00000000 },
3712                 { 0x3c7c, 0, 0x00000000, 0x00000000 },
3713                 { 0x3c80, 0, 0x3fffffff, 0x00000000 },
3714                 { 0x3c84, 0, 0x0000003f, 0x00000000 },
3715                 { 0x3c88, 0, 0x00000000, 0xffffffff },
3716                 { 0x3c8c, 0, 0x00000000, 0xffffffff },
3717
3718                 { 0x4000, 0, 0x00000000, 0x00000001 },
3719                 { 0x4004, 0, 0x00000000, 0x00030000 },
3720                 { 0x4008, 0, 0x00000ff0, 0x00000000 },
3721                 { 0x400c, 0, 0xffffffff, 0x00000000 },
3722                 { 0x4088, 0, 0x00000000, 0x00070303 },
3723
3724                 { 0x4400, 0, 0x00000000, 0x00000001 },
3725                 { 0x4404, 0, 0x00000000, 0x00003f01 },
3726                 { 0x4408, 0, 0x7fff00ff, 0x00000000 },
3727                 { 0x440c, 0, 0xffffffff, 0x00000000 },
3728                 { 0x4410, 0, 0xffff,     0x0000 },
3729                 { 0x4414, 0, 0xffff,     0x0000 },
3730                 { 0x4418, 0, 0xffff,     0x0000 },
3731                 { 0x441c, 0, 0xffff,     0x0000 },
3732                 { 0x4428, 0, 0xffffffff, 0x00000000 },
3733                 { 0x442c, 0, 0xffffffff, 0x00000000 },
3734                 { 0x4430, 0, 0xffffffff, 0x00000000 },
3735                 { 0x4434, 0, 0xffffffff, 0x00000000 },
3736                 { 0x4438, 0, 0xffffffff, 0x00000000 },
3737                 { 0x443c, 0, 0xffffffff, 0x00000000 },
3738                 { 0x4440, 0, 0xffffffff, 0x00000000 },
3739                 { 0x4444, 0, 0xffffffff, 0x00000000 },
3740
3741                 { 0x4c00, 0, 0x00000000, 0x00000001 },
3742                 { 0x4c04, 0, 0x00000000, 0x0000003f },
3743                 { 0x4c08, 0, 0xffffffff, 0x00000000 },
3744                 { 0x4c0c, 0, 0x0007fc00, 0x00000000 },
3745                 { 0x4c10, 0, 0x80003fe0, 0x00000000 },
3746                 { 0x4c14, 0, 0xffffffff, 0x00000000 },
3747                 { 0x4c44, 0, 0x00000000, 0x9fff9fff },
3748                 { 0x4c48, 0, 0x00000000, 0xb3009fff },
3749                 { 0x4c4c, 0, 0x00000000, 0x77f33b30 },
3750                 { 0x4c50, 0, 0x00000000, 0xffffffff },
3751
3752                 { 0x5004, 0, 0x00000000, 0x0000007f },
3753                 { 0x5008, 0, 0x0f0007ff, 0x00000000 },
3754                 { 0x500c, 0, 0xf800f800, 0x07ff07ff },
3755
3756                 { 0x5400, 0, 0x00000008, 0x00000001 },
3757                 { 0x5404, 0, 0x00000000, 0x0000003f },
3758                 { 0x5408, 0, 0x0000001f, 0x00000000 },
3759                 { 0x540c, 0, 0xffffffff, 0x00000000 },
3760                 { 0x5410, 0, 0xffffffff, 0x00000000 },
3761                 { 0x5414, 0, 0x0000ffff, 0x00000000 },
3762                 { 0x5418, 0, 0x0000ffff, 0x00000000 },
3763                 { 0x541c, 0, 0x0000ffff, 0x00000000 },
3764                 { 0x5420, 0, 0x0000ffff, 0x00000000 },
3765                 { 0x5428, 0, 0x000000ff, 0x00000000 },
3766                 { 0x542c, 0, 0xff00ffff, 0x00000000 },
3767                 { 0x5430, 0, 0x001fff80, 0x00000000 },
3768                 { 0x5438, 0, 0xffffffff, 0x00000000 },
3769                 { 0x543c, 0, 0xffffffff, 0x00000000 },
3770                 { 0x5440, 0, 0xf800f800, 0x07ff07ff },
3771
3772                 { 0x5c00, 0, 0x00000000, 0x00000001 },
3773                 { 0x5c04, 0, 0x00000000, 0x0003000f },
3774                 { 0x5c08, 0, 0x00000003, 0x00000000 },
3775                 { 0x5c0c, 0, 0x0000fff8, 0x00000000 },
3776                 { 0x5c10, 0, 0x00000000, 0xffffffff },
3777                 { 0x5c80, 0, 0x00000000, 0x0f7113f1 },
3778                 { 0x5c84, 0, 0x00000000, 0x0000f333 },
3779                 { 0x5c88, 0, 0x00000000, 0x00077373 },
3780                 { 0x5c8c, 0, 0x00000000, 0x0007f737 },
3781
3782                 { 0x6808, 0, 0x0000ff7f, 0x00000000 },
3783                 { 0x680c, 0, 0xffffffff, 0x00000000 },
3784                 { 0x6810, 0, 0xffffffff, 0x00000000 },
3785                 { 0x6814, 0, 0xffffffff, 0x00000000 },
3786                 { 0x6818, 0, 0xffffffff, 0x00000000 },
3787                 { 0x681c, 0, 0xffffffff, 0x00000000 },
3788                 { 0x6820, 0, 0x00ff00ff, 0x00000000 },
3789                 { 0x6824, 0, 0x00ff00ff, 0x00000000 },
3790                 { 0x6828, 0, 0x00ff00ff, 0x00000000 },
3791                 { 0x682c, 0, 0x03ff03ff, 0x00000000 },
3792                 { 0x6830, 0, 0x03ff03ff, 0x00000000 },
3793                 { 0x6834, 0, 0x03ff03ff, 0x00000000 },
3794                 { 0x6838, 0, 0x03ff03ff, 0x00000000 },
3795                 { 0x683c, 0, 0x0000ffff, 0x00000000 },
3796                 { 0x6840, 0, 0x00000ff0, 0x00000000 },
3797                 { 0x6844, 0, 0x00ffff00, 0x00000000 },
3798                 { 0x684c, 0, 0xffffffff, 0x00000000 },
3799                 { 0x6850, 0, 0x7f7f7f7f, 0x00000000 },
3800                 { 0x6854, 0, 0x7f7f7f7f, 0x00000000 },
3801                 { 0x6858, 0, 0x7f7f7f7f, 0x00000000 },
3802                 { 0x685c, 0, 0x7f7f7f7f, 0x00000000 },
3803                 { 0x6908, 0, 0x00000000, 0x0001ff0f },
3804                 { 0x690c, 0, 0x00000000, 0x0ffe00f0 },
3805
3806                 { 0xffff, 0, 0x00000000, 0x00000000 },
3807         };
3808
3809         ret = 0;
3810         for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
3811                 u32 offset, rw_mask, ro_mask, save_val, val;
3812
3813                 offset = (u32) reg_tbl[i].offset;
3814                 rw_mask = reg_tbl[i].rw_mask;
3815                 ro_mask = reg_tbl[i].ro_mask;
3816
3817                 save_val = readl(bp->regview + offset);
3818
3819                 writel(0, bp->regview + offset);
3820
3821                 val = readl(bp->regview + offset);
3822                 if ((val & rw_mask) != 0) {
3823                         goto reg_test_err;
3824                 }
3825
3826                 if ((val & ro_mask) != (save_val & ro_mask)) {
3827                         goto reg_test_err;
3828                 }
3829
3830                 writel(0xffffffff, bp->regview + offset);
3831
3832                 val = readl(bp->regview + offset);
3833                 if ((val & rw_mask) != rw_mask) {
3834                         goto reg_test_err;
3835                 }
3836
3837                 if ((val & ro_mask) != (save_val & ro_mask)) {
3838                         goto reg_test_err;
3839                 }
3840
3841                 writel(save_val, bp->regview + offset);
3842                 continue;
3843
3844 reg_test_err:
3845                 writel(save_val, bp->regview + offset);
3846                 ret = -ENODEV;
3847                 break;
3848         }
3849         return ret;
3850 }
3851
3852 static int
3853 bnx2_do_mem_test(struct bnx2 *bp, u32 start, u32 size)
3854 {
3855         static u32 test_pattern[] = { 0x00000000, 0xffffffff, 0x55555555,
3856                 0xaaaaaaaa , 0xaa55aa55, 0x55aa55aa };
3857         int i;
3858
3859         for (i = 0; i < sizeof(test_pattern) / 4; i++) {
3860                 u32 offset;
3861
3862                 for (offset = 0; offset < size; offset += 4) {
3863
3864                         REG_WR_IND(bp, start + offset, test_pattern[i]);
3865
3866                         if (REG_RD_IND(bp, start + offset) !=
3867                                 test_pattern[i]) {
3868                                 return -ENODEV;
3869                         }
3870                 }
3871         }
3872         return 0;
3873 }
3874
3875 static int
3876 bnx2_test_memory(struct bnx2 *bp)
3877 {
3878         int ret = 0;
3879         int i;
3880         static struct {
3881                 u32   offset;
3882                 u32   len;
3883         } mem_tbl[] = {
3884                 { 0x60000,  0x4000 },
3885                 { 0xa0000,  0x3000 },
3886                 { 0xe0000,  0x4000 },
3887                 { 0x120000, 0x4000 },
3888                 { 0x1a0000, 0x4000 },
3889                 { 0x160000, 0x4000 },
3890                 { 0xffffffff, 0    },
3891         };
3892
3893         for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
3894                 if ((ret = bnx2_do_mem_test(bp, mem_tbl[i].offset,
3895                         mem_tbl[i].len)) != 0) {
3896                         return ret;
3897                 }
3898         }
3899
3900         return ret;
3901 }
3902
3903 static int
3904 bnx2_test_loopback(struct bnx2 *bp)
3905 {
3906         unsigned int pkt_size, num_pkts, i;
3907         struct sk_buff *skb, *rx_skb;
3908         unsigned char *packet;
3909         u16 rx_start_idx, rx_idx, send_idx;
3910         u32 send_bseq, val;
3911         dma_addr_t map;
3912         struct tx_bd *txbd;
3913         struct sw_bd *rx_buf;
3914         struct l2_fhdr *rx_hdr;
3915         int ret = -ENODEV;
3916
3917         if (!netif_running(bp->dev))
3918                 return -ENODEV;
3919
3920         bp->loopback = MAC_LOOPBACK;
3921         bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_DIAG);
3922         bnx2_set_mac_loopback(bp);
3923
3924         pkt_size = 1514;
3925         skb = dev_alloc_skb(pkt_size);
3926         if (!skb)
3927                 return -ENOMEM;
3928         packet = skb_put(skb, pkt_size);
3929         memcpy(packet, bp->mac_addr, 6);
3930         memset(packet + 6, 0x0, 8);
3931         for (i = 14; i < pkt_size; i++)
3932                 packet[i] = (unsigned char) (i & 0xff);
3933
3934         map = pci_map_single(bp->pdev, skb->data, pkt_size,
3935                 PCI_DMA_TODEVICE);
3936
3937         val = REG_RD(bp, BNX2_HC_COMMAND);
3938         REG_WR(bp, BNX2_HC_COMMAND, val | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
3939         REG_RD(bp, BNX2_HC_COMMAND);
3940
3941         udelay(5);
3942         rx_start_idx = bp->status_blk->status_rx_quick_consumer_index0;
3943
3944         send_idx = 0;
3945         send_bseq = 0;
3946         num_pkts = 0;
3947
3948         txbd = &bp->tx_desc_ring[send_idx];
3949
3950         txbd->tx_bd_haddr_hi = (u64) map >> 32;
3951         txbd->tx_bd_haddr_lo = (u64) map & 0xffffffff;
3952         txbd->tx_bd_mss_nbytes = pkt_size;
3953         txbd->tx_bd_vlan_tag_flags = TX_BD_FLAGS_START | TX_BD_FLAGS_END;
3954
3955         num_pkts++;
3956         send_idx = NEXT_TX_BD(send_idx);
3957
3958         send_bseq += pkt_size;
3959
3960         REG_WR16(bp, MB_TX_CID_ADDR + BNX2_L2CTX_TX_HOST_BIDX, send_idx);
3961         REG_WR(bp, MB_TX_CID_ADDR + BNX2_L2CTX_TX_HOST_BSEQ, send_bseq);
3962
3963
3964         udelay(100);
3965
3966         val = REG_RD(bp, BNX2_HC_COMMAND);
3967         REG_WR(bp, BNX2_HC_COMMAND, val | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
3968         REG_RD(bp, BNX2_HC_COMMAND);
3969
3970         udelay(5);
3971
3972         pci_unmap_single(bp->pdev, map, pkt_size, PCI_DMA_TODEVICE);
3973         dev_kfree_skb_irq(skb);
3974
3975         if (bp->status_blk->status_tx_quick_consumer_index0 != send_idx) {
3976                 goto loopback_test_done;
3977         }
3978
3979         rx_idx = bp->status_blk->status_rx_quick_consumer_index0;
3980         if (rx_idx != rx_start_idx + num_pkts) {
3981                 goto loopback_test_done;
3982         }
3983
3984         rx_buf = &bp->rx_buf_ring[rx_start_idx];
3985         rx_skb = rx_buf->skb;
3986
3987         rx_hdr = (struct l2_fhdr *) rx_skb->data;
3988         skb_reserve(rx_skb, bp->rx_offset);
3989
3990         pci_dma_sync_single_for_cpu(bp->pdev,
3991                 pci_unmap_addr(rx_buf, mapping),
3992                 bp->rx_buf_size, PCI_DMA_FROMDEVICE);
3993
3994         if (rx_hdr->l2_fhdr_status &
3995                 (L2_FHDR_ERRORS_BAD_CRC |
3996                 L2_FHDR_ERRORS_PHY_DECODE |
3997                 L2_FHDR_ERRORS_ALIGNMENT |
3998                 L2_FHDR_ERRORS_TOO_SHORT |
3999                 L2_FHDR_ERRORS_GIANT_FRAME)) {
4000
4001                 goto loopback_test_done;
4002         }
4003
4004         if ((rx_hdr->l2_fhdr_pkt_len - 4) != pkt_size) {
4005                 goto loopback_test_done;
4006         }
4007
4008         for (i = 14; i < pkt_size; i++) {
4009                 if (*(rx_skb->data + i) != (unsigned char) (i & 0xff)) {
4010                         goto loopback_test_done;
4011                 }
4012         }
4013
4014         ret = 0;
4015
4016 loopback_test_done:
4017         bp->loopback = 0;
4018         return ret;
4019 }
4020
4021 #define NVRAM_SIZE 0x200
4022 #define CRC32_RESIDUAL 0xdebb20e3
4023
4024 static int
4025 bnx2_test_nvram(struct bnx2 *bp)
4026 {
4027         u32 buf[NVRAM_SIZE / 4];
4028         u8 *data = (u8 *) buf;
4029         int rc = 0;
4030         u32 magic, csum;
4031
4032         if ((rc = bnx2_nvram_read(bp, 0, data, 4)) != 0)
4033                 goto test_nvram_done;
4034
4035         magic = be32_to_cpu(buf[0]);
4036         if (magic != 0x669955aa) {
4037                 rc = -ENODEV;
4038                 goto test_nvram_done;
4039         }
4040
4041         if ((rc = bnx2_nvram_read(bp, 0x100, data, NVRAM_SIZE)) != 0)
4042                 goto test_nvram_done;
4043
4044         csum = ether_crc_le(0x100, data);
4045         if (csum != CRC32_RESIDUAL) {
4046                 rc = -ENODEV;
4047                 goto test_nvram_done;
4048         }
4049
4050         csum = ether_crc_le(0x100, data + 0x100);
4051         if (csum != CRC32_RESIDUAL) {
4052                 rc = -ENODEV;
4053         }
4054
4055 test_nvram_done:
4056         return rc;
4057 }
4058
4059 static int
4060 bnx2_test_link(struct bnx2 *bp)
4061 {
4062         u32 bmsr;
4063
4064         spin_lock_bh(&bp->phy_lock);
4065         bnx2_read_phy(bp, MII_BMSR, &bmsr);
4066         bnx2_read_phy(bp, MII_BMSR, &bmsr);
4067         spin_unlock_bh(&bp->phy_lock);
4068
4069         if (bmsr & BMSR_LSTATUS) {
4070                 return 0;
4071         }
4072         return -ENODEV;
4073 }
4074
4075 static int
4076 bnx2_test_intr(struct bnx2 *bp)
4077 {
4078         int i;
4079         u32 val;
4080         u16 status_idx;
4081
4082         if (!netif_running(bp->dev))
4083                 return -ENODEV;
4084
4085         status_idx = REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff;
4086
4087         /* This register is not touched during run-time. */
4088         val = REG_RD(bp, BNX2_HC_COMMAND);
4089         REG_WR(bp, BNX2_HC_COMMAND, val | BNX2_HC_COMMAND_COAL_NOW);
4090         REG_RD(bp, BNX2_HC_COMMAND);
4091
4092         for (i = 0; i < 10; i++) {
4093                 if ((REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff) !=
4094                         status_idx) {
4095
4096                         break;
4097                 }
4098
4099                 msleep_interruptible(10);
4100         }
4101         if (i < 10)
4102                 return 0;
4103
4104         return -ENODEV;
4105 }
4106
4107 static void
4108 bnx2_timer(unsigned long data)
4109 {
4110         struct bnx2 *bp = (struct bnx2 *) data;
4111         u32 msg;
4112
4113         if (!netif_running(bp->dev))
4114                 return;
4115
4116         if (atomic_read(&bp->intr_sem) != 0)
4117                 goto bnx2_restart_timer;
4118
4119         msg = (u32) ++bp->fw_drv_pulse_wr_seq;
4120         REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_PULSE_MB, msg);
4121
4122         if ((bp->phy_flags & PHY_SERDES_FLAG) &&
4123             (CHIP_NUM(bp) == CHIP_NUM_5706)) {
4124
4125                 spin_lock(&bp->phy_lock);
4126                 if (bp->serdes_an_pending) {
4127                         bp->serdes_an_pending--;
4128                 }
4129                 else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) {
4130                         u32 bmcr;
4131
4132                         bp->current_interval = bp->timer_interval;
4133
4134                         bnx2_read_phy(bp, MII_BMCR, &bmcr);
4135
4136                         if (bmcr & BMCR_ANENABLE) {
4137                                 u32 phy1, phy2;
4138
4139                                 bnx2_write_phy(bp, 0x1c, 0x7c00);
4140                                 bnx2_read_phy(bp, 0x1c, &phy1);
4141
4142                                 bnx2_write_phy(bp, 0x17, 0x0f01);
4143                                 bnx2_read_phy(bp, 0x15, &phy2);
4144                                 bnx2_write_phy(bp, 0x17, 0x0f01);
4145                                 bnx2_read_phy(bp, 0x15, &phy2);
4146
4147                                 if ((phy1 & 0x10) &&    /* SIGNAL DETECT */
4148                                         !(phy2 & 0x20)) {       /* no CONFIG */
4149
4150                                         bmcr &= ~BMCR_ANENABLE;
4151                                         bmcr |= BMCR_SPEED1000 |
4152                                                 BMCR_FULLDPLX;
4153                                         bnx2_write_phy(bp, MII_BMCR, bmcr);
4154                                         bp->phy_flags |=
4155                                                 PHY_PARALLEL_DETECT_FLAG;
4156                                 }
4157                         }
4158                 }
4159                 else if ((bp->link_up) && (bp->autoneg & AUTONEG_SPEED) &&
4160                         (bp->phy_flags & PHY_PARALLEL_DETECT_FLAG)) {
4161                         u32 phy2;
4162
4163                         bnx2_write_phy(bp, 0x17, 0x0f01);
4164                         bnx2_read_phy(bp, 0x15, &phy2);
4165                         if (phy2 & 0x20) {
4166                                 u32 bmcr;
4167
4168                                 bnx2_read_phy(bp, MII_BMCR, &bmcr);
4169                                 bmcr |= BMCR_ANENABLE;
4170                                 bnx2_write_phy(bp, MII_BMCR, bmcr);
4171
4172                                 bp->phy_flags &= ~PHY_PARALLEL_DETECT_FLAG;
4173
4174                         }
4175                 }
4176                 else
4177                         bp->current_interval = bp->timer_interval;
4178
4179                 spin_unlock(&bp->phy_lock);
4180         }
4181
4182 bnx2_restart_timer:
4183         mod_timer(&bp->timer, jiffies + bp->current_interval);
4184 }
4185
4186 /* Called with rtnl_lock */
4187 static int
4188 bnx2_open(struct net_device *dev)
4189 {
4190         struct bnx2 *bp = dev->priv;
4191         int rc;
4192
4193         bnx2_set_power_state(bp, PCI_D0);
4194         bnx2_disable_int(bp);
4195
4196         rc = bnx2_alloc_mem(bp);
4197         if (rc)
4198                 return rc;
4199
4200         if ((CHIP_ID(bp) != CHIP_ID_5706_A0) &&
4201                 (CHIP_ID(bp) != CHIP_ID_5706_A1) &&
4202                 !disable_msi) {
4203
4204                 if (pci_enable_msi(bp->pdev) == 0) {
4205                         bp->flags |= USING_MSI_FLAG;
4206                         rc = request_irq(bp->pdev->irq, bnx2_msi, 0, dev->name,
4207                                         dev);
4208                 }
4209                 else {
4210                         rc = request_irq(bp->pdev->irq, bnx2_interrupt,
4211                                         SA_SHIRQ, dev->name, dev);
4212                 }
4213         }
4214         else {
4215                 rc = request_irq(bp->pdev->irq, bnx2_interrupt, SA_SHIRQ,
4216                                 dev->name, dev);
4217         }
4218         if (rc) {
4219                 bnx2_free_mem(bp);
4220                 return rc;
4221         }
4222
4223         rc = bnx2_init_nic(bp);
4224
4225         if (rc) {
4226                 free_irq(bp->pdev->irq, dev);
4227                 if (bp->flags & USING_MSI_FLAG) {
4228                         pci_disable_msi(bp->pdev);
4229                         bp->flags &= ~USING_MSI_FLAG;
4230                 }
4231                 bnx2_free_skbs(bp);
4232                 bnx2_free_mem(bp);
4233                 return rc;
4234         }
4235
4236         mod_timer(&bp->timer, jiffies + bp->current_interval);
4237
4238         atomic_set(&bp->intr_sem, 0);
4239
4240         bnx2_enable_int(bp);
4241
4242         if (bp->flags & USING_MSI_FLAG) {
4243                 /* Test MSI to make sure it is working
4244                  * If MSI test fails, go back to INTx mode
4245                  */
4246                 if (bnx2_test_intr(bp) != 0) {
4247                         printk(KERN_WARNING PFX "%s: No interrupt was generated"
4248                                " using MSI, switching to INTx mode. Please"
4249                                " report this failure to the PCI maintainer"
4250                                " and include system chipset information.\n",
4251                                bp->dev->name);
4252
4253                         bnx2_disable_int(bp);
4254                         free_irq(bp->pdev->irq, dev);
4255                         pci_disable_msi(bp->pdev);
4256                         bp->flags &= ~USING_MSI_FLAG;
4257
4258                         rc = bnx2_init_nic(bp);
4259
4260                         if (!rc) {
4261                                 rc = request_irq(bp->pdev->irq, bnx2_interrupt,
4262                                         SA_SHIRQ, dev->name, dev);
4263                         }
4264                         if (rc) {
4265                                 bnx2_free_skbs(bp);
4266                                 bnx2_free_mem(bp);
4267                                 del_timer_sync(&bp->timer);
4268                                 return rc;
4269                         }
4270                         bnx2_enable_int(bp);
4271                 }
4272         }
4273         if (bp->flags & USING_MSI_FLAG) {
4274                 printk(KERN_INFO PFX "%s: using MSI\n", dev->name);
4275         }
4276
4277         netif_start_queue(dev);
4278
4279         return 0;
4280 }
4281
4282 static void
4283 bnx2_reset_task(void *data)
4284 {
4285         struct bnx2 *bp = data;
4286
4287         if (!netif_running(bp->dev))
4288                 return;
4289
4290         bp->in_reset_task = 1;
4291         bnx2_netif_stop(bp);
4292
4293         bnx2_init_nic(bp);
4294
4295         atomic_set(&bp->intr_sem, 1);
4296         bnx2_netif_start(bp);
4297         bp->in_reset_task = 0;
4298 }
4299
4300 static void
4301 bnx2_tx_timeout(struct net_device *dev)
4302 {
4303         struct bnx2 *bp = dev->priv;
4304
4305         /* This allows the netif to be shutdown gracefully before resetting */
4306         schedule_work(&bp->reset_task);
4307 }
4308
4309 #ifdef BCM_VLAN
4310 /* Called with rtnl_lock */
4311 static void
4312 bnx2_vlan_rx_register(struct net_device *dev, struct vlan_group *vlgrp)
4313 {
4314         struct bnx2 *bp = dev->priv;
4315
4316         bnx2_netif_stop(bp);
4317
4318         bp->vlgrp = vlgrp;
4319         bnx2_set_rx_mode(dev);
4320
4321         bnx2_netif_start(bp);
4322 }
4323
4324 /* Called with rtnl_lock */
4325 static void
4326 bnx2_vlan_rx_kill_vid(struct net_device *dev, uint16_t vid)
4327 {
4328         struct bnx2 *bp = dev->priv;
4329
4330         bnx2_netif_stop(bp);
4331
4332         if (bp->vlgrp)
4333                 bp->vlgrp->vlan_devices[vid] = NULL;
4334         bnx2_set_rx_mode(dev);
4335
4336         bnx2_netif_start(bp);
4337 }
4338 #endif
4339
4340 /* Called with dev->xmit_lock.
4341  * hard_start_xmit is pseudo-lockless - a lock is only required when
4342  * the tx queue is full. This way, we get the benefit of lockless
4343  * operations most of the time without the complexities to handle
4344  * netif_stop_queue/wake_queue race conditions.
4345  */
4346 static int
4347 bnx2_start_xmit(struct sk_buff *skb, struct net_device *dev)
4348 {
4349         struct bnx2 *bp = dev->priv;
4350         dma_addr_t mapping;
4351         struct tx_bd *txbd;
4352         struct sw_bd *tx_buf;
4353         u32 len, vlan_tag_flags, last_frag, mss;
4354         u16 prod, ring_prod;
4355         int i;
4356
4357         if (unlikely(bnx2_tx_avail(bp) < (skb_shinfo(skb)->nr_frags + 1))) {
4358                 netif_stop_queue(dev);
4359                 printk(KERN_ERR PFX "%s: BUG! Tx ring full when queue awake!\n",
4360                         dev->name);
4361
4362                 return NETDEV_TX_BUSY;
4363         }
4364         len = skb_headlen(skb);
4365         prod = bp->tx_prod;
4366         ring_prod = TX_RING_IDX(prod);
4367
4368         vlan_tag_flags = 0;
4369         if (skb->ip_summed == CHECKSUM_HW) {
4370                 vlan_tag_flags |= TX_BD_FLAGS_TCP_UDP_CKSUM;
4371         }
4372
4373         if (bp->vlgrp != 0 && vlan_tx_tag_present(skb)) {
4374                 vlan_tag_flags |=
4375                         (TX_BD_FLAGS_VLAN_TAG | (vlan_tx_tag_get(skb) << 16));
4376         }
4377 #ifdef BCM_TSO
4378         if ((mss = skb_shinfo(skb)->tso_size) &&
4379                 (skb->len > (bp->dev->mtu + ETH_HLEN))) {
4380                 u32 tcp_opt_len, ip_tcp_len;
4381
4382                 if (skb_header_cloned(skb) &&
4383                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
4384                         dev_kfree_skb(skb);
4385                         return NETDEV_TX_OK;
4386                 }
4387
4388                 tcp_opt_len = ((skb->h.th->doff - 5) * 4);
4389                 vlan_tag_flags |= TX_BD_FLAGS_SW_LSO;
4390
4391                 tcp_opt_len = 0;
4392                 if (skb->h.th->doff > 5) {
4393                         tcp_opt_len = (skb->h.th->doff - 5) << 2;
4394                 }
4395                 ip_tcp_len = (skb->nh.iph->ihl << 2) + sizeof(struct tcphdr);
4396
4397                 skb->nh.iph->check = 0;
4398                 skb->nh.iph->tot_len = ntohs(mss + ip_tcp_len + tcp_opt_len);
4399                 skb->h.th->check =
4400                         ~csum_tcpudp_magic(skb->nh.iph->saddr,
4401                                             skb->nh.iph->daddr,
4402                                             0, IPPROTO_TCP, 0);
4403
4404                 if (tcp_opt_len || (skb->nh.iph->ihl > 5)) {
4405                         vlan_tag_flags |= ((skb->nh.iph->ihl - 5) +
4406                                 (tcp_opt_len >> 2)) << 8;
4407                 }
4408         }
4409         else
4410 #endif
4411         {
4412                 mss = 0;
4413         }
4414
4415         mapping = pci_map_single(bp->pdev, skb->data, len, PCI_DMA_TODEVICE);
4416
4417         tx_buf = &bp->tx_buf_ring[ring_prod];
4418         tx_buf->skb = skb;
4419         pci_unmap_addr_set(tx_buf, mapping, mapping);
4420
4421         txbd = &bp->tx_desc_ring[ring_prod];
4422
4423         txbd->tx_bd_haddr_hi = (u64) mapping >> 32;
4424         txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff;
4425         txbd->tx_bd_mss_nbytes = len | (mss << 16);
4426         txbd->tx_bd_vlan_tag_flags = vlan_tag_flags | TX_BD_FLAGS_START;
4427
4428         last_frag = skb_shinfo(skb)->nr_frags;
4429
4430         for (i = 0; i < last_frag; i++) {
4431                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
4432
4433                 prod = NEXT_TX_BD(prod);
4434                 ring_prod = TX_RING_IDX(prod);
4435                 txbd = &bp->tx_desc_ring[ring_prod];
4436
4437                 len = frag->size;
4438                 mapping = pci_map_page(bp->pdev, frag->page, frag->page_offset,
4439                         len, PCI_DMA_TODEVICE);
4440                 pci_unmap_addr_set(&bp->tx_buf_ring[ring_prod],
4441                                 mapping, mapping);
4442
4443                 txbd->tx_bd_haddr_hi = (u64) mapping >> 32;
4444                 txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff;
4445                 txbd->tx_bd_mss_nbytes = len | (mss << 16);
4446                 txbd->tx_bd_vlan_tag_flags = vlan_tag_flags;
4447
4448         }
4449         txbd->tx_bd_vlan_tag_flags |= TX_BD_FLAGS_END;
4450
4451         prod = NEXT_TX_BD(prod);
4452         bp->tx_prod_bseq += skb->len;
4453
4454         REG_WR16(bp, MB_TX_CID_ADDR + BNX2_L2CTX_TX_HOST_BIDX, prod);
4455         REG_WR(bp, MB_TX_CID_ADDR + BNX2_L2CTX_TX_HOST_BSEQ, bp->tx_prod_bseq);
4456
4457         mmiowb();
4458
4459         bp->tx_prod = prod;
4460         dev->trans_start = jiffies;
4461
4462         if (unlikely(bnx2_tx_avail(bp) <= MAX_SKB_FRAGS)) {
4463                 spin_lock(&bp->tx_lock);
4464                 netif_stop_queue(dev);
4465
4466                 if (bnx2_tx_avail(bp) > MAX_SKB_FRAGS)
4467                         netif_wake_queue(dev);
4468                 spin_unlock(&bp->tx_lock);
4469         }
4470
4471         return NETDEV_TX_OK;
4472 }
4473
4474 /* Called with rtnl_lock */
4475 static int
4476 bnx2_close(struct net_device *dev)
4477 {
4478         struct bnx2 *bp = dev->priv;
4479         u32 reset_code;
4480
4481         /* Calling flush_scheduled_work() may deadlock because
4482          * linkwatch_event() may be on the workqueue and it will try to get
4483          * the rtnl_lock which we are holding.
4484          */
4485         while (bp->in_reset_task)
4486                 msleep(1);
4487
4488         bnx2_netif_stop(bp);
4489         del_timer_sync(&bp->timer);
4490         if (bp->flags & NO_WOL_FLAG)
4491                 reset_code = BNX2_DRV_MSG_CODE_UNLOAD;
4492         else if (bp->wol)
4493                 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
4494         else
4495                 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
4496         bnx2_reset_chip(bp, reset_code);
4497         free_irq(bp->pdev->irq, dev);
4498         if (bp->flags & USING_MSI_FLAG) {
4499                 pci_disable_msi(bp->pdev);
4500                 bp->flags &= ~USING_MSI_FLAG;
4501         }
4502         bnx2_free_skbs(bp);
4503         bnx2_free_mem(bp);
4504         bp->link_up = 0;
4505         netif_carrier_off(bp->dev);
4506         bnx2_set_power_state(bp, PCI_D3hot);
4507         return 0;
4508 }
4509
4510 #define GET_NET_STATS64(ctr)                                    \
4511         (unsigned long) ((unsigned long) (ctr##_hi) << 32) +    \
4512         (unsigned long) (ctr##_lo)
4513
4514 #define GET_NET_STATS32(ctr)            \
4515         (ctr##_lo)
4516
4517 #if (BITS_PER_LONG == 64)
4518 #define GET_NET_STATS   GET_NET_STATS64
4519 #else
4520 #define GET_NET_STATS   GET_NET_STATS32
4521 #endif
4522
4523 static struct net_device_stats *
4524 bnx2_get_stats(struct net_device *dev)
4525 {
4526         struct bnx2 *bp = dev->priv;
4527         struct statistics_block *stats_blk = bp->stats_blk;
4528         struct net_device_stats *net_stats = &bp->net_stats;
4529
4530         if (bp->stats_blk == NULL) {
4531                 return net_stats;
4532         }
4533         net_stats->rx_packets =
4534                 GET_NET_STATS(stats_blk->stat_IfHCInUcastPkts) +
4535                 GET_NET_STATS(stats_blk->stat_IfHCInMulticastPkts) +
4536                 GET_NET_STATS(stats_blk->stat_IfHCInBroadcastPkts);
4537
4538         net_stats->tx_packets =
4539                 GET_NET_STATS(stats_blk->stat_IfHCOutUcastPkts) +
4540                 GET_NET_STATS(stats_blk->stat_IfHCOutMulticastPkts) +
4541                 GET_NET_STATS(stats_blk->stat_IfHCOutBroadcastPkts);
4542
4543         net_stats->rx_bytes =
4544                 GET_NET_STATS(stats_blk->stat_IfHCInOctets);
4545
4546         net_stats->tx_bytes =
4547                 GET_NET_STATS(stats_blk->stat_IfHCOutOctets);
4548
4549         net_stats->multicast =
4550                 GET_NET_STATS(stats_blk->stat_IfHCOutMulticastPkts);
4551
4552         net_stats->collisions =
4553                 (unsigned long) stats_blk->stat_EtherStatsCollisions;
4554
4555         net_stats->rx_length_errors =
4556                 (unsigned long) (stats_blk->stat_EtherStatsUndersizePkts +
4557                 stats_blk->stat_EtherStatsOverrsizePkts);
4558
4559         net_stats->rx_over_errors =
4560                 (unsigned long) stats_blk->stat_IfInMBUFDiscards;
4561
4562         net_stats->rx_frame_errors =
4563                 (unsigned long) stats_blk->stat_Dot3StatsAlignmentErrors;
4564
4565         net_stats->rx_crc_errors =
4566                 (unsigned long) stats_blk->stat_Dot3StatsFCSErrors;
4567
4568         net_stats->rx_errors = net_stats->rx_length_errors +
4569                 net_stats->rx_over_errors + net_stats->rx_frame_errors +
4570                 net_stats->rx_crc_errors;
4571
4572         net_stats->tx_aborted_errors =
4573                 (unsigned long) (stats_blk->stat_Dot3StatsExcessiveCollisions +
4574                 stats_blk->stat_Dot3StatsLateCollisions);
4575
4576         if ((CHIP_NUM(bp) == CHIP_NUM_5706) ||
4577             (CHIP_ID(bp) == CHIP_ID_5708_A0))
4578                 net_stats->tx_carrier_errors = 0;
4579         else {
4580                 net_stats->tx_carrier_errors =
4581                         (unsigned long)
4582                         stats_blk->stat_Dot3StatsCarrierSenseErrors;
4583         }
4584
4585         net_stats->tx_errors =
4586                 (unsigned long)
4587                 stats_blk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors
4588                 +
4589                 net_stats->tx_aborted_errors +
4590                 net_stats->tx_carrier_errors;
4591
4592         return net_stats;
4593 }
4594
4595 /* All ethtool functions called with rtnl_lock */
4596
4597 static int
4598 bnx2_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
4599 {
4600         struct bnx2 *bp = dev->priv;
4601
4602         cmd->supported = SUPPORTED_Autoneg;
4603         if (bp->phy_flags & PHY_SERDES_FLAG) {
4604                 cmd->supported |= SUPPORTED_1000baseT_Full |
4605                         SUPPORTED_FIBRE;
4606
4607                 cmd->port = PORT_FIBRE;
4608         }
4609         else {
4610                 cmd->supported |= SUPPORTED_10baseT_Half |
4611                         SUPPORTED_10baseT_Full |
4612                         SUPPORTED_100baseT_Half |
4613                         SUPPORTED_100baseT_Full |
4614                         SUPPORTED_1000baseT_Full |
4615                         SUPPORTED_TP;
4616
4617                 cmd->port = PORT_TP;
4618         }
4619
4620         cmd->advertising = bp->advertising;
4621
4622         if (bp->autoneg & AUTONEG_SPEED) {
4623                 cmd->autoneg = AUTONEG_ENABLE;
4624         }
4625         else {
4626                 cmd->autoneg = AUTONEG_DISABLE;
4627         }
4628
4629         if (netif_carrier_ok(dev)) {
4630                 cmd->speed = bp->line_speed;
4631                 cmd->duplex = bp->duplex;
4632         }
4633         else {
4634                 cmd->speed = -1;
4635                 cmd->duplex = -1;
4636         }
4637
4638         cmd->transceiver = XCVR_INTERNAL;
4639         cmd->phy_address = bp->phy_addr;
4640
4641         return 0;
4642 }
4643
4644 static int
4645 bnx2_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
4646 {
4647         struct bnx2 *bp = dev->priv;
4648         u8 autoneg = bp->autoneg;
4649         u8 req_duplex = bp->req_duplex;
4650         u16 req_line_speed = bp->req_line_speed;
4651         u32 advertising = bp->advertising;
4652
4653         if (cmd->autoneg == AUTONEG_ENABLE) {
4654                 autoneg |= AUTONEG_SPEED;
4655
4656                 cmd->advertising &= ETHTOOL_ALL_COPPER_SPEED;
4657
4658                 /* allow advertising 1 speed */
4659                 if ((cmd->advertising == ADVERTISED_10baseT_Half) ||
4660                         (cmd->advertising == ADVERTISED_10baseT_Full) ||
4661                         (cmd->advertising == ADVERTISED_100baseT_Half) ||
4662                         (cmd->advertising == ADVERTISED_100baseT_Full)) {
4663
4664                         if (bp->phy_flags & PHY_SERDES_FLAG)
4665                                 return -EINVAL;
4666
4667                         advertising = cmd->advertising;
4668
4669                 }
4670                 else if (cmd->advertising == ADVERTISED_1000baseT_Full) {
4671                         advertising = cmd->advertising;
4672                 }
4673                 else if (cmd->advertising == ADVERTISED_1000baseT_Half) {
4674                         return -EINVAL;
4675                 }
4676                 else {
4677                         if (bp->phy_flags & PHY_SERDES_FLAG) {
4678                                 advertising = ETHTOOL_ALL_FIBRE_SPEED;
4679                         }
4680                         else {
4681                                 advertising = ETHTOOL_ALL_COPPER_SPEED;
4682                         }
4683                 }
4684                 advertising |= ADVERTISED_Autoneg;
4685         }
4686         else {
4687                 if (bp->phy_flags & PHY_SERDES_FLAG) {
4688                         if ((cmd->speed != SPEED_1000) ||
4689                                 (cmd->duplex != DUPLEX_FULL)) {
4690                                 return -EINVAL;
4691                         }
4692                 }
4693                 else if (cmd->speed == SPEED_1000) {
4694                         return -EINVAL;
4695                 }
4696                 autoneg &= ~AUTONEG_SPEED;
4697                 req_line_speed = cmd->speed;
4698                 req_duplex = cmd->duplex;
4699                 advertising = 0;
4700         }
4701
4702         bp->autoneg = autoneg;
4703         bp->advertising = advertising;
4704         bp->req_line_speed = req_line_speed;
4705         bp->req_duplex = req_duplex;
4706
4707         spin_lock_bh(&bp->phy_lock);
4708
4709         bnx2_setup_phy(bp);
4710
4711         spin_unlock_bh(&bp->phy_lock);
4712
4713         return 0;
4714 }
4715
4716 static void
4717 bnx2_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
4718 {
4719         struct bnx2 *bp = dev->priv;
4720
4721         strcpy(info->driver, DRV_MODULE_NAME);
4722         strcpy(info->version, DRV_MODULE_VERSION);
4723         strcpy(info->bus_info, pci_name(bp->pdev));
4724         info->fw_version[0] = ((bp->fw_ver & 0xff000000) >> 24) + '0';
4725         info->fw_version[2] = ((bp->fw_ver & 0xff0000) >> 16) + '0';
4726         info->fw_version[4] = ((bp->fw_ver & 0xff00) >> 8) + '0';
4727         info->fw_version[6] = (bp->fw_ver & 0xff) + '0';
4728         info->fw_version[1] = info->fw_version[3] = info->fw_version[5] = '.';
4729         info->fw_version[7] = 0;
4730 }
4731
4732 static void
4733 bnx2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
4734 {
4735         struct bnx2 *bp = dev->priv;
4736
4737         if (bp->flags & NO_WOL_FLAG) {
4738                 wol->supported = 0;
4739                 wol->wolopts = 0;
4740         }
4741         else {
4742                 wol->supported = WAKE_MAGIC;
4743                 if (bp->wol)
4744                         wol->wolopts = WAKE_MAGIC;
4745                 else
4746                         wol->wolopts = 0;
4747         }
4748         memset(&wol->sopass, 0, sizeof(wol->sopass));
4749 }
4750
4751 static int
4752 bnx2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
4753 {
4754         struct bnx2 *bp = dev->priv;
4755
4756         if (wol->wolopts & ~WAKE_MAGIC)
4757                 return -EINVAL;
4758
4759         if (wol->wolopts & WAKE_MAGIC) {
4760                 if (bp->flags & NO_WOL_FLAG)
4761                         return -EINVAL;
4762
4763                 bp->wol = 1;
4764         }
4765         else {
4766                 bp->wol = 0;
4767         }
4768         return 0;
4769 }
4770
4771 static int
4772 bnx2_nway_reset(struct net_device *dev)
4773 {
4774         struct bnx2 *bp = dev->priv;
4775         u32 bmcr;
4776
4777         if (!(bp->autoneg & AUTONEG_SPEED)) {
4778                 return -EINVAL;
4779         }
4780
4781         spin_lock_bh(&bp->phy_lock);
4782
4783         /* Force a link down visible on the other side */
4784         if (bp->phy_flags & PHY_SERDES_FLAG) {
4785                 bnx2_write_phy(bp, MII_BMCR, BMCR_LOOPBACK);
4786                 spin_unlock_bh(&bp->phy_lock);
4787
4788                 msleep(20);
4789
4790                 spin_lock_bh(&bp->phy_lock);
4791                 if (CHIP_NUM(bp) == CHIP_NUM_5706) {
4792                         bp->current_interval = SERDES_AN_TIMEOUT;
4793                         bp->serdes_an_pending = 1;
4794                         mod_timer(&bp->timer, jiffies + bp->current_interval);
4795                 }
4796         }
4797
4798         bnx2_read_phy(bp, MII_BMCR, &bmcr);
4799         bmcr &= ~BMCR_LOOPBACK;
4800         bnx2_write_phy(bp, MII_BMCR, bmcr | BMCR_ANRESTART | BMCR_ANENABLE);
4801
4802         spin_unlock_bh(&bp->phy_lock);
4803
4804         return 0;
4805 }
4806
4807 static int
4808 bnx2_get_eeprom_len(struct net_device *dev)
4809 {
4810         struct bnx2 *bp = dev->priv;
4811
4812         if (bp->flash_info == 0)
4813                 return 0;
4814
4815         return (int) bp->flash_info->total_size;
4816 }
4817
4818 static int
4819 bnx2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
4820                 u8 *eebuf)
4821 {
4822         struct bnx2 *bp = dev->priv;
4823         int rc;
4824
4825         /* parameters already validated in ethtool_get_eeprom */
4826
4827         rc = bnx2_nvram_read(bp, eeprom->offset, eebuf, eeprom->len);
4828
4829         return rc;
4830 }
4831
4832 static int
4833 bnx2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
4834                 u8 *eebuf)
4835 {
4836         struct bnx2 *bp = dev->priv;
4837         int rc;
4838
4839         /* parameters already validated in ethtool_set_eeprom */
4840
4841         rc = bnx2_nvram_write(bp, eeprom->offset, eebuf, eeprom->len);
4842
4843         return rc;
4844 }
4845
4846 static int
4847 bnx2_get_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
4848 {
4849         struct bnx2 *bp = dev->priv;
4850
4851         memset(coal, 0, sizeof(struct ethtool_coalesce));
4852
4853         coal->rx_coalesce_usecs = bp->rx_ticks;
4854         coal->rx_max_coalesced_frames = bp->rx_quick_cons_trip;
4855         coal->rx_coalesce_usecs_irq = bp->rx_ticks_int;
4856         coal->rx_max_coalesced_frames_irq = bp->rx_quick_cons_trip_int;
4857
4858         coal->tx_coalesce_usecs = bp->tx_ticks;
4859         coal->tx_max_coalesced_frames = bp->tx_quick_cons_trip;
4860         coal->tx_coalesce_usecs_irq = bp->tx_ticks_int;
4861         coal->tx_max_coalesced_frames_irq = bp->tx_quick_cons_trip_int;
4862
4863         coal->stats_block_coalesce_usecs = bp->stats_ticks;
4864
4865         return 0;
4866 }
4867
4868 static int
4869 bnx2_set_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
4870 {
4871         struct bnx2 *bp = dev->priv;
4872
4873         bp->rx_ticks = (u16) coal->rx_coalesce_usecs;
4874         if (bp->rx_ticks > 0x3ff) bp->rx_ticks = 0x3ff;
4875
4876         bp->rx_quick_cons_trip = (u16) coal->rx_max_coalesced_frames;
4877         if (bp->rx_quick_cons_trip > 0xff) bp->rx_quick_cons_trip = 0xff;
4878
4879         bp->rx_ticks_int = (u16) coal->rx_coalesce_usecs_irq;
4880         if (bp->rx_ticks_int > 0x3ff) bp->rx_ticks_int = 0x3ff;
4881
4882         bp->rx_quick_cons_trip_int = (u16) coal->rx_max_coalesced_frames_irq;
4883         if (bp->rx_quick_cons_trip_int > 0xff)
4884                 bp->rx_quick_cons_trip_int = 0xff;
4885
4886         bp->tx_ticks = (u16) coal->tx_coalesce_usecs;
4887         if (bp->tx_ticks > 0x3ff) bp->tx_ticks = 0x3ff;
4888
4889         bp->tx_quick_cons_trip = (u16) coal->tx_max_coalesced_frames;
4890         if (bp->tx_quick_cons_trip > 0xff) bp->tx_quick_cons_trip = 0xff;
4891
4892         bp->tx_ticks_int = (u16) coal->tx_coalesce_usecs_irq;
4893         if (bp->tx_ticks_int > 0x3ff) bp->tx_ticks_int = 0x3ff;
4894
4895         bp->tx_quick_cons_trip_int = (u16) coal->tx_max_coalesced_frames_irq;
4896         if (bp->tx_quick_cons_trip_int > 0xff) bp->tx_quick_cons_trip_int =
4897                 0xff;
4898
4899         bp->stats_ticks = coal->stats_block_coalesce_usecs;
4900         if (bp->stats_ticks > 0xffff00) bp->stats_ticks = 0xffff00;
4901         bp->stats_ticks &= 0xffff00;
4902
4903         if (netif_running(bp->dev)) {
4904                 bnx2_netif_stop(bp);
4905                 bnx2_init_nic(bp);
4906                 bnx2_netif_start(bp);
4907         }
4908
4909         return 0;
4910 }
4911
4912 static void
4913 bnx2_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
4914 {
4915         struct bnx2 *bp = dev->priv;
4916
4917         ering->rx_max_pending = MAX_RX_DESC_CNT;
4918         ering->rx_mini_max_pending = 0;
4919         ering->rx_jumbo_max_pending = 0;
4920
4921         ering->rx_pending = bp->rx_ring_size;
4922         ering->rx_mini_pending = 0;
4923         ering->rx_jumbo_pending = 0;
4924
4925         ering->tx_max_pending = MAX_TX_DESC_CNT;
4926         ering->tx_pending = bp->tx_ring_size;
4927 }
4928
4929 static int
4930 bnx2_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
4931 {
4932         struct bnx2 *bp = dev->priv;
4933
4934         if ((ering->rx_pending > MAX_RX_DESC_CNT) ||
4935                 (ering->tx_pending > MAX_TX_DESC_CNT) ||
4936                 (ering->tx_pending <= MAX_SKB_FRAGS)) {
4937
4938                 return -EINVAL;
4939         }
4940         bp->rx_ring_size = ering->rx_pending;
4941         bp->tx_ring_size = ering->tx_pending;
4942
4943         if (netif_running(bp->dev)) {
4944                 bnx2_netif_stop(bp);
4945                 bnx2_init_nic(bp);
4946                 bnx2_netif_start(bp);
4947         }
4948
4949         return 0;
4950 }
4951
4952 static void
4953 bnx2_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
4954 {
4955         struct bnx2 *bp = dev->priv;
4956
4957         epause->autoneg = ((bp->autoneg & AUTONEG_FLOW_CTRL) != 0);
4958         epause->rx_pause = ((bp->flow_ctrl & FLOW_CTRL_RX) != 0);
4959         epause->tx_pause = ((bp->flow_ctrl & FLOW_CTRL_TX) != 0);
4960 }
4961
4962 static int
4963 bnx2_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
4964 {
4965         struct bnx2 *bp = dev->priv;
4966
4967         bp->req_flow_ctrl = 0;
4968         if (epause->rx_pause)
4969                 bp->req_flow_ctrl |= FLOW_CTRL_RX;
4970         if (epause->tx_pause)
4971                 bp->req_flow_ctrl |= FLOW_CTRL_TX;
4972
4973         if (epause->autoneg) {
4974                 bp->autoneg |= AUTONEG_FLOW_CTRL;
4975         }
4976         else {
4977                 bp->autoneg &= ~AUTONEG_FLOW_CTRL;
4978         }
4979
4980         spin_lock_bh(&bp->phy_lock);
4981
4982         bnx2_setup_phy(bp);
4983
4984         spin_unlock_bh(&bp->phy_lock);
4985
4986         return 0;
4987 }
4988
4989 static u32
4990 bnx2_get_rx_csum(struct net_device *dev)
4991 {
4992         struct bnx2 *bp = dev->priv;
4993
4994         return bp->rx_csum;
4995 }
4996
4997 static int
4998 bnx2_set_rx_csum(struct net_device *dev, u32 data)
4999 {
5000         struct bnx2 *bp = dev->priv;
5001
5002         bp->rx_csum = data;
5003         return 0;
5004 }
5005
5006 #define BNX2_NUM_STATS 45
5007
5008 static struct {
5009         char string[ETH_GSTRING_LEN];
5010 } bnx2_stats_str_arr[BNX2_NUM_STATS] = {
5011         { "rx_bytes" },
5012         { "rx_error_bytes" },
5013         { "tx_bytes" },
5014         { "tx_error_bytes" },
5015         { "rx_ucast_packets" },
5016         { "rx_mcast_packets" },
5017         { "rx_bcast_packets" },
5018         { "tx_ucast_packets" },
5019         { "tx_mcast_packets" },
5020         { "tx_bcast_packets" },
5021         { "tx_mac_errors" },
5022         { "tx_carrier_errors" },
5023         { "rx_crc_errors" },
5024         { "rx_align_errors" },
5025         { "tx_single_collisions" },
5026         { "tx_multi_collisions" },
5027         { "tx_deferred" },
5028         { "tx_excess_collisions" },
5029         { "tx_late_collisions" },
5030         { "tx_total_collisions" },
5031         { "rx_fragments" },
5032         { "rx_jabbers" },
5033         { "rx_undersize_packets" },
5034         { "rx_oversize_packets" },
5035         { "rx_64_byte_packets" },
5036         { "rx_65_to_127_byte_packets" },
5037         { "rx_128_to_255_byte_packets" },
5038         { "rx_256_to_511_byte_packets" },
5039         { "rx_512_to_1023_byte_packets" },
5040         { "rx_1024_to_1522_byte_packets" },
5041         { "rx_1523_to_9022_byte_packets" },
5042         { "tx_64_byte_packets" },
5043         { "tx_65_to_127_byte_packets" },
5044         { "tx_128_to_255_byte_packets" },
5045         { "tx_256_to_511_byte_packets" },
5046         { "tx_512_to_1023_byte_packets" },
5047         { "tx_1024_to_1522_byte_packets" },
5048         { "tx_1523_to_9022_byte_packets" },
5049         { "rx_xon_frames" },
5050         { "rx_xoff_frames" },
5051         { "tx_xon_frames" },
5052         { "tx_xoff_frames" },
5053         { "rx_mac_ctrl_frames" },
5054         { "rx_filtered_packets" },
5055         { "rx_discards" },
5056 };
5057
5058 #define STATS_OFFSET32(offset_name) (offsetof(struct statistics_block, offset_name) / 4)
5059
5060 static unsigned long bnx2_stats_offset_arr[BNX2_NUM_STATS] = {
5061     STATS_OFFSET32(stat_IfHCInOctets_hi),
5062     STATS_OFFSET32(stat_IfHCInBadOctets_hi),
5063     STATS_OFFSET32(stat_IfHCOutOctets_hi),
5064     STATS_OFFSET32(stat_IfHCOutBadOctets_hi),
5065     STATS_OFFSET32(stat_IfHCInUcastPkts_hi),
5066     STATS_OFFSET32(stat_IfHCInMulticastPkts_hi),
5067     STATS_OFFSET32(stat_IfHCInBroadcastPkts_hi),
5068     STATS_OFFSET32(stat_IfHCOutUcastPkts_hi),
5069     STATS_OFFSET32(stat_IfHCOutMulticastPkts_hi),
5070     STATS_OFFSET32(stat_IfHCOutBroadcastPkts_hi),
5071     STATS_OFFSET32(stat_emac_tx_stat_dot3statsinternalmactransmiterrors),
5072     STATS_OFFSET32(stat_Dot3StatsCarrierSenseErrors),
5073     STATS_OFFSET32(stat_Dot3StatsFCSErrors),
5074     STATS_OFFSET32(stat_Dot3StatsAlignmentErrors),
5075     STATS_OFFSET32(stat_Dot3StatsSingleCollisionFrames),
5076     STATS_OFFSET32(stat_Dot3StatsMultipleCollisionFrames),
5077     STATS_OFFSET32(stat_Dot3StatsDeferredTransmissions),
5078     STATS_OFFSET32(stat_Dot3StatsExcessiveCollisions),
5079     STATS_OFFSET32(stat_Dot3StatsLateCollisions),
5080     STATS_OFFSET32(stat_EtherStatsCollisions),
5081     STATS_OFFSET32(stat_EtherStatsFragments),
5082     STATS_OFFSET32(stat_EtherStatsJabbers),
5083     STATS_OFFSET32(stat_EtherStatsUndersizePkts),
5084     STATS_OFFSET32(stat_EtherStatsOverrsizePkts),
5085     STATS_OFFSET32(stat_EtherStatsPktsRx64Octets),
5086     STATS_OFFSET32(stat_EtherStatsPktsRx65Octetsto127Octets),
5087     STATS_OFFSET32(stat_EtherStatsPktsRx128Octetsto255Octets),
5088     STATS_OFFSET32(stat_EtherStatsPktsRx256Octetsto511Octets),
5089     STATS_OFFSET32(stat_EtherStatsPktsRx512Octetsto1023Octets),
5090     STATS_OFFSET32(stat_EtherStatsPktsRx1024Octetsto1522Octets),
5091     STATS_OFFSET32(stat_EtherStatsPktsRx1523Octetsto9022Octets),
5092     STATS_OFFSET32(stat_EtherStatsPktsTx64Octets),
5093     STATS_OFFSET32(stat_EtherStatsPktsTx65Octetsto127Octets),
5094     STATS_OFFSET32(stat_EtherStatsPktsTx128Octetsto255Octets),
5095     STATS_OFFSET32(stat_EtherStatsPktsTx256Octetsto511Octets),
5096     STATS_OFFSET32(stat_EtherStatsPktsTx512Octetsto1023Octets),
5097     STATS_OFFSET32(stat_EtherStatsPktsTx1024Octetsto1522Octets),
5098     STATS_OFFSET32(stat_EtherStatsPktsTx1523Octetsto9022Octets),
5099     STATS_OFFSET32(stat_XonPauseFramesReceived),
5100     STATS_OFFSET32(stat_XoffPauseFramesReceived),
5101     STATS_OFFSET32(stat_OutXonSent),
5102     STATS_OFFSET32(stat_OutXoffSent),
5103     STATS_OFFSET32(stat_MacControlFramesReceived),
5104     STATS_OFFSET32(stat_IfInFramesL2FilterDiscards),
5105     STATS_OFFSET32(stat_IfInMBUFDiscards),
5106 };
5107
5108 /* stat_IfHCInBadOctets and stat_Dot3StatsCarrierSenseErrors are
5109  * skipped because of errata.
5110  */
5111 static u8 bnx2_5706_stats_len_arr[BNX2_NUM_STATS] = {
5112         8,0,8,8,8,8,8,8,8,8,
5113         4,0,4,4,4,4,4,4,4,4,
5114         4,4,4,4,4,4,4,4,4,4,
5115         4,4,4,4,4,4,4,4,4,4,
5116         4,4,4,4,4,
5117 };
5118
5119 static u8 bnx2_5708_stats_len_arr[BNX2_NUM_STATS] = {
5120         8,0,8,8,8,8,8,8,8,8,
5121         4,4,4,4,4,4,4,4,4,4,
5122         4,4,4,4,4,4,4,4,4,4,
5123         4,4,4,4,4,4,4,4,4,4,
5124         4,4,4,4,4,
5125 };
5126
5127 #define BNX2_NUM_TESTS 6
5128
5129 static struct {
5130         char string[ETH_GSTRING_LEN];
5131 } bnx2_tests_str_arr[BNX2_NUM_TESTS] = {
5132         { "register_test (offline)" },
5133         { "memory_test (offline)" },
5134         { "loopback_test (offline)" },
5135         { "nvram_test (online)" },
5136         { "interrupt_test (online)" },
5137         { "link_test (online)" },
5138 };
5139
5140 static int
5141 bnx2_self_test_count(struct net_device *dev)
5142 {
5143         return BNX2_NUM_TESTS;
5144 }
5145
5146 static void
5147 bnx2_self_test(struct net_device *dev, struct ethtool_test *etest, u64 *buf)
5148 {
5149         struct bnx2 *bp = dev->priv;
5150
5151         memset(buf, 0, sizeof(u64) * BNX2_NUM_TESTS);
5152         if (etest->flags & ETH_TEST_FL_OFFLINE) {
5153                 bnx2_netif_stop(bp);
5154                 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_DIAG);
5155                 bnx2_free_skbs(bp);
5156
5157                 if (bnx2_test_registers(bp) != 0) {
5158                         buf[0] = 1;
5159                         etest->flags |= ETH_TEST_FL_FAILED;
5160                 }
5161                 if (bnx2_test_memory(bp) != 0) {
5162                         buf[1] = 1;
5163                         etest->flags |= ETH_TEST_FL_FAILED;
5164                 }
5165                 if (bnx2_test_loopback(bp) != 0) {
5166                         buf[2] = 1;
5167                         etest->flags |= ETH_TEST_FL_FAILED;
5168                 }
5169
5170                 if (!netif_running(bp->dev)) {
5171                         bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_RESET);
5172                 }
5173                 else {
5174                         bnx2_init_nic(bp);
5175                         bnx2_netif_start(bp);
5176                 }
5177
5178                 /* wait for link up */
5179                 msleep_interruptible(3000);
5180                 if ((!bp->link_up) && !(bp->phy_flags & PHY_SERDES_FLAG))
5181                         msleep_interruptible(4000);
5182         }
5183
5184         if (bnx2_test_nvram(bp) != 0) {
5185                 buf[3] = 1;
5186                 etest->flags |= ETH_TEST_FL_FAILED;
5187         }
5188         if (bnx2_test_intr(bp) != 0) {
5189                 buf[4] = 1;
5190                 etest->flags |= ETH_TEST_FL_FAILED;
5191         }
5192
5193         if (bnx2_test_link(bp) != 0) {
5194                 buf[5] = 1;
5195                 etest->flags |= ETH_TEST_FL_FAILED;
5196
5197         }
5198 }
5199
5200 static void
5201 bnx2_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
5202 {
5203         switch (stringset) {
5204         case ETH_SS_STATS:
5205                 memcpy(buf, bnx2_stats_str_arr,
5206                         sizeof(bnx2_stats_str_arr));
5207                 break;
5208         case ETH_SS_TEST:
5209                 memcpy(buf, bnx2_tests_str_arr,
5210                         sizeof(bnx2_tests_str_arr));
5211                 break;
5212         }
5213 }
5214
5215 static int
5216 bnx2_get_stats_count(struct net_device *dev)
5217 {
5218         return BNX2_NUM_STATS;
5219 }
5220
5221 static void
5222 bnx2_get_ethtool_stats(struct net_device *dev,
5223                 struct ethtool_stats *stats, u64 *buf)
5224 {
5225         struct bnx2 *bp = dev->priv;
5226         int i;
5227         u32 *hw_stats = (u32 *) bp->stats_blk;
5228         u8 *stats_len_arr = NULL;
5229
5230         if (hw_stats == NULL) {
5231                 memset(buf, 0, sizeof(u64) * BNX2_NUM_STATS);
5232                 return;
5233         }
5234
5235         if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
5236             (CHIP_ID(bp) == CHIP_ID_5706_A1) ||
5237             (CHIP_ID(bp) == CHIP_ID_5706_A2) ||
5238             (CHIP_ID(bp) == CHIP_ID_5708_A0))
5239                 stats_len_arr = bnx2_5706_stats_len_arr;
5240         else
5241                 stats_len_arr = bnx2_5708_stats_len_arr;
5242
5243         for (i = 0; i < BNX2_NUM_STATS; i++) {
5244                 if (stats_len_arr[i] == 0) {
5245                         /* skip this counter */
5246                         buf[i] = 0;
5247                         continue;
5248                 }
5249                 if (stats_len_arr[i] == 4) {
5250                         /* 4-byte counter */
5251                         buf[i] = (u64)
5252                                 *(hw_stats + bnx2_stats_offset_arr[i]);
5253                         continue;
5254                 }
5255                 /* 8-byte counter */
5256                 buf[i] = (((u64) *(hw_stats +
5257                                         bnx2_stats_offset_arr[i])) << 32) +
5258                                 *(hw_stats + bnx2_stats_offset_arr[i] + 1);
5259         }
5260 }
5261
5262 static int
5263 bnx2_phys_id(struct net_device *dev, u32 data)
5264 {
5265         struct bnx2 *bp = dev->priv;
5266         int i;
5267         u32 save;
5268
5269         if (data == 0)
5270                 data = 2;
5271
5272         save = REG_RD(bp, BNX2_MISC_CFG);
5273         REG_WR(bp, BNX2_MISC_CFG, BNX2_MISC_CFG_LEDMODE_MAC);
5274
5275         for (i = 0; i < (data * 2); i++) {
5276                 if ((i % 2) == 0) {
5277                         REG_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE);
5278                 }
5279                 else {
5280                         REG_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE |
5281                                 BNX2_EMAC_LED_1000MB_OVERRIDE |
5282                                 BNX2_EMAC_LED_100MB_OVERRIDE |
5283                                 BNX2_EMAC_LED_10MB_OVERRIDE |
5284                                 BNX2_EMAC_LED_TRAFFIC_OVERRIDE |
5285                                 BNX2_EMAC_LED_TRAFFIC);
5286                 }
5287                 msleep_interruptible(500);
5288                 if (signal_pending(current))
5289                         break;
5290         }
5291         REG_WR(bp, BNX2_EMAC_LED, 0);
5292         REG_WR(bp, BNX2_MISC_CFG, save);
5293         return 0;
5294 }
5295
5296 static struct ethtool_ops bnx2_ethtool_ops = {
5297         .get_settings           = bnx2_get_settings,
5298         .set_settings           = bnx2_set_settings,
5299         .get_drvinfo            = bnx2_get_drvinfo,
5300         .get_wol                = bnx2_get_wol,
5301         .set_wol                = bnx2_set_wol,
5302         .nway_reset             = bnx2_nway_reset,
5303         .get_link               = ethtool_op_get_link,
5304         .get_eeprom_len         = bnx2_get_eeprom_len,
5305         .get_eeprom             = bnx2_get_eeprom,
5306         .set_eeprom             = bnx2_set_eeprom,
5307         .get_coalesce           = bnx2_get_coalesce,
5308         .set_coalesce           = bnx2_set_coalesce,
5309         .get_ringparam          = bnx2_get_ringparam,
5310         .set_ringparam          = bnx2_set_ringparam,
5311         .get_pauseparam         = bnx2_get_pauseparam,
5312         .set_pauseparam         = bnx2_set_pauseparam,
5313         .get_rx_csum            = bnx2_get_rx_csum,
5314         .set_rx_csum            = bnx2_set_rx_csum,
5315         .get_tx_csum            = ethtool_op_get_tx_csum,
5316         .set_tx_csum            = ethtool_op_set_tx_csum,
5317         .get_sg                 = ethtool_op_get_sg,
5318         .set_sg                 = ethtool_op_set_sg,
5319 #ifdef BCM_TSO
5320         .get_tso                = ethtool_op_get_tso,
5321         .set_tso                = ethtool_op_set_tso,
5322 #endif
5323         .self_test_count        = bnx2_self_test_count,
5324         .self_test              = bnx2_self_test,
5325         .get_strings            = bnx2_get_strings,
5326         .phys_id                = bnx2_phys_id,
5327         .get_stats_count        = bnx2_get_stats_count,
5328         .get_ethtool_stats      = bnx2_get_ethtool_stats,
5329         .get_perm_addr          = ethtool_op_get_perm_addr,
5330 };
5331
5332 /* Called with rtnl_lock */
5333 static int
5334 bnx2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
5335 {
5336         struct mii_ioctl_data *data = if_mii(ifr);
5337         struct bnx2 *bp = dev->priv;
5338         int err;
5339
5340         switch(cmd) {
5341         case SIOCGMIIPHY:
5342                 data->phy_id = bp->phy_addr;
5343
5344                 /* fallthru */
5345         case SIOCGMIIREG: {
5346                 u32 mii_regval;
5347
5348                 spin_lock_bh(&bp->phy_lock);
5349                 err = bnx2_read_phy(bp, data->reg_num & 0x1f, &mii_regval);
5350                 spin_unlock_bh(&bp->phy_lock);
5351
5352                 data->val_out = mii_regval;
5353
5354                 return err;
5355         }
5356
5357         case SIOCSMIIREG:
5358                 if (!capable(CAP_NET_ADMIN))
5359                         return -EPERM;
5360
5361                 spin_lock_bh(&bp->phy_lock);
5362                 err = bnx2_write_phy(bp, data->reg_num & 0x1f, data->val_in);
5363                 spin_unlock_bh(&bp->phy_lock);
5364
5365                 return err;
5366
5367         default:
5368                 /* do nothing */
5369                 break;
5370         }
5371         return -EOPNOTSUPP;
5372 }
5373
5374 /* Called with rtnl_lock */
5375 static int
5376 bnx2_change_mac_addr(struct net_device *dev, void *p)
5377 {
5378         struct sockaddr *addr = p;
5379         struct bnx2 *bp = dev->priv;
5380
5381         if (!is_valid_ether_addr(addr->sa_data))
5382                 return -EINVAL;
5383
5384         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
5385         if (netif_running(dev))
5386                 bnx2_set_mac_addr(bp);
5387
5388         return 0;
5389 }
5390
5391 /* Called with rtnl_lock */
5392 static int
5393 bnx2_change_mtu(struct net_device *dev, int new_mtu)
5394 {
5395         struct bnx2 *bp = dev->priv;
5396
5397         if (((new_mtu + ETH_HLEN) > MAX_ETHERNET_JUMBO_PACKET_SIZE) ||
5398                 ((new_mtu + ETH_HLEN) < MIN_ETHERNET_PACKET_SIZE))
5399                 return -EINVAL;
5400
5401         dev->mtu = new_mtu;
5402         if (netif_running(dev)) {
5403                 bnx2_netif_stop(bp);
5404
5405                 bnx2_init_nic(bp);
5406
5407                 bnx2_netif_start(bp);
5408         }
5409         return 0;
5410 }
5411
5412 #if defined(HAVE_POLL_CONTROLLER) || defined(CONFIG_NET_POLL_CONTROLLER)
5413 static void
5414 poll_bnx2(struct net_device *dev)
5415 {
5416         struct bnx2 *bp = dev->priv;
5417
5418         disable_irq(bp->pdev->irq);
5419         bnx2_interrupt(bp->pdev->irq, dev, NULL);
5420         enable_irq(bp->pdev->irq);
5421 }
5422 #endif
5423
5424 static int __devinit
5425 bnx2_init_board(struct pci_dev *pdev, struct net_device *dev)
5426 {
5427         struct bnx2 *bp;
5428         unsigned long mem_len;
5429         int rc;
5430         u32 reg;
5431
5432         SET_MODULE_OWNER(dev);
5433         SET_NETDEV_DEV(dev, &pdev->dev);
5434         bp = dev->priv;
5435
5436         bp->flags = 0;
5437         bp->phy_flags = 0;
5438
5439         /* enable device (incl. PCI PM wakeup), and bus-mastering */
5440         rc = pci_enable_device(pdev);
5441         if (rc) {
5442                 printk(KERN_ERR PFX "Cannot enable PCI device, aborting.");
5443                 goto err_out;
5444         }
5445
5446         if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
5447                 printk(KERN_ERR PFX "Cannot find PCI device base address, "
5448                        "aborting.\n");
5449                 rc = -ENODEV;
5450                 goto err_out_disable;
5451         }
5452
5453         rc = pci_request_regions(pdev, DRV_MODULE_NAME);
5454         if (rc) {
5455                 printk(KERN_ERR PFX "Cannot obtain PCI resources, aborting.\n");
5456                 goto err_out_disable;
5457         }
5458
5459         pci_set_master(pdev);
5460
5461         bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
5462         if (bp->pm_cap == 0) {
5463                 printk(KERN_ERR PFX "Cannot find power management capability, "
5464                                "aborting.\n");
5465                 rc = -EIO;
5466                 goto err_out_release;
5467         }
5468
5469         bp->pcix_cap = pci_find_capability(pdev, PCI_CAP_ID_PCIX);
5470         if (bp->pcix_cap == 0) {
5471                 printk(KERN_ERR PFX "Cannot find PCIX capability, aborting.\n");
5472                 rc = -EIO;
5473                 goto err_out_release;
5474         }
5475
5476         if (pci_set_dma_mask(pdev, DMA_64BIT_MASK) == 0) {
5477                 bp->flags |= USING_DAC_FLAG;
5478                 if (pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK) != 0) {
5479                         printk(KERN_ERR PFX "pci_set_consistent_dma_mask "
5480                                "failed, aborting.\n");
5481                         rc = -EIO;
5482                         goto err_out_release;
5483                 }
5484         }
5485         else if (pci_set_dma_mask(pdev, DMA_32BIT_MASK) != 0) {
5486                 printk(KERN_ERR PFX "System does not support DMA, aborting.\n");
5487                 rc = -EIO;
5488                 goto err_out_release;
5489         }
5490
5491         bp->dev = dev;
5492         bp->pdev = pdev;
5493
5494         spin_lock_init(&bp->phy_lock);
5495         spin_lock_init(&bp->tx_lock);
5496         INIT_WORK(&bp->reset_task, bnx2_reset_task, bp);
5497
5498         dev->base_addr = dev->mem_start = pci_resource_start(pdev, 0);
5499         mem_len = MB_GET_CID_ADDR(17);
5500         dev->mem_end = dev->mem_start + mem_len;
5501         dev->irq = pdev->irq;
5502
5503         bp->regview = ioremap_nocache(dev->base_addr, mem_len);
5504
5505         if (!bp->regview) {
5506                 printk(KERN_ERR PFX "Cannot map register space, aborting.\n");
5507                 rc = -ENOMEM;
5508                 goto err_out_release;
5509         }
5510
5511         /* Configure byte swap and enable write to the reg_window registers.
5512          * Rely on CPU to do target byte swapping on big endian systems
5513          * The chip's target access swapping will not swap all accesses
5514          */
5515         pci_write_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG,
5516                                BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
5517                                BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP);
5518
5519         bnx2_set_power_state(bp, PCI_D0);
5520
5521         bp->chip_id = REG_RD(bp, BNX2_MISC_ID);
5522
5523         /* Get bus information. */
5524         reg = REG_RD(bp, BNX2_PCICFG_MISC_STATUS);
5525         if (reg & BNX2_PCICFG_MISC_STATUS_PCIX_DET) {
5526                 u32 clkreg;
5527
5528                 bp->flags |= PCIX_FLAG;
5529
5530                 clkreg = REG_RD(bp, BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS);
5531
5532                 clkreg &= BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET;
5533                 switch (clkreg) {
5534                 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ:
5535                         bp->bus_speed_mhz = 133;
5536                         break;
5537
5538                 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ:
5539                         bp->bus_speed_mhz = 100;
5540                         break;
5541
5542                 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ:
5543                 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ:
5544                         bp->bus_speed_mhz = 66;
5545                         break;
5546
5547                 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ:
5548                 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ:
5549                         bp->bus_speed_mhz = 50;
5550                         break;
5551
5552                 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW:
5553                 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ:
5554                 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ:
5555                         bp->bus_speed_mhz = 33;
5556                         break;
5557                 }
5558         }
5559         else {
5560                 if (reg & BNX2_PCICFG_MISC_STATUS_M66EN)
5561                         bp->bus_speed_mhz = 66;
5562                 else
5563                         bp->bus_speed_mhz = 33;
5564         }
5565
5566         if (reg & BNX2_PCICFG_MISC_STATUS_32BIT_DET)
5567                 bp->flags |= PCI_32BIT_FLAG;
5568
5569         /* 5706A0 may falsely detect SERR and PERR. */
5570         if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
5571                 reg = REG_RD(bp, PCI_COMMAND);
5572                 reg &= ~(PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
5573                 REG_WR(bp, PCI_COMMAND, reg);
5574         }
5575         else if ((CHIP_ID(bp) == CHIP_ID_5706_A1) &&
5576                 !(bp->flags & PCIX_FLAG)) {
5577
5578                 printk(KERN_ERR PFX "5706 A1 can only be used in a PCIX bus, "
5579                        "aborting.\n");
5580                 goto err_out_unmap;
5581         }
5582
5583         bnx2_init_nvram(bp);
5584
5585         reg = REG_RD_IND(bp, BNX2_SHM_HDR_SIGNATURE);
5586
5587         if ((reg & BNX2_SHM_HDR_SIGNATURE_SIG_MASK) ==
5588             BNX2_SHM_HDR_SIGNATURE_SIG)
5589                 bp->shmem_base = REG_RD_IND(bp, BNX2_SHM_HDR_ADDR_0);
5590         else
5591                 bp->shmem_base = HOST_VIEW_SHMEM_BASE;
5592
5593         /* Get the permanent MAC address.  First we need to make sure the
5594          * firmware is actually running.
5595          */
5596         reg = REG_RD_IND(bp, bp->shmem_base + BNX2_DEV_INFO_SIGNATURE);
5597
5598         if ((reg & BNX2_DEV_INFO_SIGNATURE_MAGIC_MASK) !=
5599             BNX2_DEV_INFO_SIGNATURE_MAGIC) {
5600                 printk(KERN_ERR PFX "Firmware not running, aborting.\n");
5601                 rc = -ENODEV;
5602                 goto err_out_unmap;
5603         }
5604
5605         bp->fw_ver = REG_RD_IND(bp, bp->shmem_base + BNX2_DEV_INFO_BC_REV);
5606
5607         reg = REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_HW_CFG_MAC_UPPER);
5608         bp->mac_addr[0] = (u8) (reg >> 8);
5609         bp->mac_addr[1] = (u8) reg;
5610
5611         reg = REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_HW_CFG_MAC_LOWER);
5612         bp->mac_addr[2] = (u8) (reg >> 24);
5613         bp->mac_addr[3] = (u8) (reg >> 16);
5614         bp->mac_addr[4] = (u8) (reg >> 8);
5615         bp->mac_addr[5] = (u8) reg;
5616
5617         bp->tx_ring_size = MAX_TX_DESC_CNT;
5618         bp->rx_ring_size = 100;
5619
5620         bp->rx_csum = 1;
5621
5622         bp->rx_offset = sizeof(struct l2_fhdr) + 2;
5623
5624         bp->tx_quick_cons_trip_int = 20;
5625         bp->tx_quick_cons_trip = 20;
5626         bp->tx_ticks_int = 80;
5627         bp->tx_ticks = 80;
5628
5629         bp->rx_quick_cons_trip_int = 6;
5630         bp->rx_quick_cons_trip = 6;
5631         bp->rx_ticks_int = 18;
5632         bp->rx_ticks = 18;
5633
5634         bp->stats_ticks = 1000000 & 0xffff00;
5635
5636         bp->timer_interval =  HZ;
5637         bp->current_interval =  HZ;
5638
5639         bp->phy_addr = 1;
5640
5641         /* Disable WOL support if we are running on a SERDES chip. */
5642         if (CHIP_BOND_ID(bp) & CHIP_BOND_ID_SERDES_BIT) {
5643                 bp->phy_flags |= PHY_SERDES_FLAG;
5644                 bp->flags |= NO_WOL_FLAG;
5645                 if (CHIP_NUM(bp) == CHIP_NUM_5708) {
5646                         bp->phy_addr = 2;
5647                         reg = REG_RD_IND(bp, bp->shmem_base +
5648                                          BNX2_SHARED_HW_CFG_CONFIG);
5649                         if (reg & BNX2_SHARED_HW_CFG_PHY_2_5G)
5650                                 bp->phy_flags |= PHY_2_5G_CAPABLE_FLAG;
5651                 }
5652         }
5653
5654         if (CHIP_NUM(bp) == CHIP_NUM_5708)
5655                 bp->flags |= NO_WOL_FLAG;
5656
5657         if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
5658                 bp->tx_quick_cons_trip_int =
5659                         bp->tx_quick_cons_trip;
5660                 bp->tx_ticks_int = bp->tx_ticks;
5661                 bp->rx_quick_cons_trip_int =
5662                         bp->rx_quick_cons_trip;
5663                 bp->rx_ticks_int = bp->rx_ticks;
5664                 bp->comp_prod_trip_int = bp->comp_prod_trip;
5665                 bp->com_ticks_int = bp->com_ticks;
5666                 bp->cmd_ticks_int = bp->cmd_ticks;
5667         }
5668
5669         bp->autoneg = AUTONEG_SPEED | AUTONEG_FLOW_CTRL;
5670         bp->req_line_speed = 0;
5671         if (bp->phy_flags & PHY_SERDES_FLAG) {
5672                 bp->advertising = ETHTOOL_ALL_FIBRE_SPEED | ADVERTISED_Autoneg;
5673
5674                 reg = REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_HW_CFG_CONFIG);
5675                 reg &= BNX2_PORT_HW_CFG_CFG_DFLT_LINK_MASK;
5676                 if (reg == BNX2_PORT_HW_CFG_CFG_DFLT_LINK_1G) {
5677                         bp->autoneg = 0;
5678                         bp->req_line_speed = bp->line_speed = SPEED_1000;
5679                         bp->req_duplex = DUPLEX_FULL;
5680                 }
5681         }
5682         else {
5683                 bp->advertising = ETHTOOL_ALL_COPPER_SPEED | ADVERTISED_Autoneg;
5684         }
5685
5686         bp->req_flow_ctrl = FLOW_CTRL_RX | FLOW_CTRL_TX;
5687
5688         init_timer(&bp->timer);
5689         bp->timer.expires = RUN_AT(bp->timer_interval);
5690         bp->timer.data = (unsigned long) bp;
5691         bp->timer.function = bnx2_timer;
5692
5693         return 0;
5694
5695 err_out_unmap:
5696         if (bp->regview) {
5697                 iounmap(bp->regview);
5698                 bp->regview = NULL;
5699         }
5700
5701 err_out_release:
5702         pci_release_regions(pdev);
5703
5704 err_out_disable:
5705         pci_disable_device(pdev);
5706         pci_set_drvdata(pdev, NULL);
5707
5708 err_out:
5709         return rc;
5710 }
5711
5712 static int __devinit
5713 bnx2_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
5714 {
5715         static int version_printed = 0;
5716         struct net_device *dev = NULL;
5717         struct bnx2 *bp;
5718         int rc, i;
5719
5720         if (version_printed++ == 0)
5721                 printk(KERN_INFO "%s", version);
5722
5723         /* dev zeroed in init_etherdev */
5724         dev = alloc_etherdev(sizeof(*bp));
5725
5726         if (!dev)
5727                 return -ENOMEM;
5728
5729         rc = bnx2_init_board(pdev, dev);
5730         if (rc < 0) {
5731                 free_netdev(dev);
5732                 return rc;
5733         }
5734
5735         dev->open = bnx2_open;
5736         dev->hard_start_xmit = bnx2_start_xmit;
5737         dev->stop = bnx2_close;
5738         dev->get_stats = bnx2_get_stats;
5739         dev->set_multicast_list = bnx2_set_rx_mode;
5740         dev->do_ioctl = bnx2_ioctl;
5741         dev->set_mac_address = bnx2_change_mac_addr;
5742         dev->change_mtu = bnx2_change_mtu;
5743         dev->tx_timeout = bnx2_tx_timeout;
5744         dev->watchdog_timeo = TX_TIMEOUT;
5745 #ifdef BCM_VLAN
5746         dev->vlan_rx_register = bnx2_vlan_rx_register;
5747         dev->vlan_rx_kill_vid = bnx2_vlan_rx_kill_vid;
5748 #endif
5749         dev->poll = bnx2_poll;
5750         dev->ethtool_ops = &bnx2_ethtool_ops;
5751         dev->weight = 64;
5752
5753         bp = dev->priv;
5754
5755 #if defined(HAVE_POLL_CONTROLLER) || defined(CONFIG_NET_POLL_CONTROLLER)
5756         dev->poll_controller = poll_bnx2;
5757 #endif
5758
5759         if ((rc = register_netdev(dev))) {
5760                 printk(KERN_ERR PFX "Cannot register net device\n");
5761                 if (bp->regview)
5762                         iounmap(bp->regview);
5763                 pci_release_regions(pdev);
5764                 pci_disable_device(pdev);
5765                 pci_set_drvdata(pdev, NULL);
5766                 free_netdev(dev);
5767                 return rc;
5768         }
5769
5770         pci_set_drvdata(pdev, dev);
5771
5772         memcpy(dev->dev_addr, bp->mac_addr, 6);
5773         memcpy(dev->perm_addr, bp->mac_addr, 6);
5774         bp->name = board_info[ent->driver_data].name,
5775         printk(KERN_INFO "%s: %s (%c%d) PCI%s %s %dMHz found at mem %lx, "
5776                 "IRQ %d, ",
5777                 dev->name,
5778                 bp->name,
5779                 ((CHIP_ID(bp) & 0xf000) >> 12) + 'A',
5780                 ((CHIP_ID(bp) & 0x0ff0) >> 4),
5781                 ((bp->flags & PCIX_FLAG) ? "-X" : ""),
5782                 ((bp->flags & PCI_32BIT_FLAG) ? "32-bit" : "64-bit"),
5783                 bp->bus_speed_mhz,
5784                 dev->base_addr,
5785                 bp->pdev->irq);
5786
5787         printk("node addr ");
5788         for (i = 0; i < 6; i++)
5789                 printk("%2.2x", dev->dev_addr[i]);
5790         printk("\n");
5791
5792         dev->features |= NETIF_F_SG;
5793         if (bp->flags & USING_DAC_FLAG)
5794                 dev->features |= NETIF_F_HIGHDMA;
5795         dev->features |= NETIF_F_IP_CSUM;
5796 #ifdef BCM_VLAN
5797         dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
5798 #endif
5799 #ifdef BCM_TSO
5800         dev->features |= NETIF_F_TSO;
5801 #endif
5802
5803         netif_carrier_off(bp->dev);
5804
5805         return 0;
5806 }
5807
5808 static void __devexit
5809 bnx2_remove_one(struct pci_dev *pdev)
5810 {
5811         struct net_device *dev = pci_get_drvdata(pdev);
5812         struct bnx2 *bp = dev->priv;
5813
5814         flush_scheduled_work();
5815
5816         unregister_netdev(dev);
5817
5818         if (bp->regview)
5819                 iounmap(bp->regview);
5820
5821         free_netdev(dev);
5822         pci_release_regions(pdev);
5823         pci_disable_device(pdev);
5824         pci_set_drvdata(pdev, NULL);
5825 }
5826
5827 static int
5828 bnx2_suspend(struct pci_dev *pdev, pm_message_t state)
5829 {
5830         struct net_device *dev = pci_get_drvdata(pdev);
5831         struct bnx2 *bp = dev->priv;
5832         u32 reset_code;
5833
5834         if (!netif_running(dev))
5835                 return 0;
5836
5837         bnx2_netif_stop(bp);
5838         netif_device_detach(dev);
5839         del_timer_sync(&bp->timer);
5840         if (bp->flags & NO_WOL_FLAG)
5841                 reset_code = BNX2_DRV_MSG_CODE_UNLOAD;
5842         else if (bp->wol)
5843                 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
5844         else
5845                 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
5846         bnx2_reset_chip(bp, reset_code);
5847         bnx2_free_skbs(bp);
5848         bnx2_set_power_state(bp, pci_choose_state(pdev, state));
5849         return 0;
5850 }
5851
5852 static int
5853 bnx2_resume(struct pci_dev *pdev)
5854 {
5855         struct net_device *dev = pci_get_drvdata(pdev);
5856         struct bnx2 *bp = dev->priv;
5857
5858         if (!netif_running(dev))
5859                 return 0;
5860
5861         bnx2_set_power_state(bp, PCI_D0);
5862         netif_device_attach(dev);
5863         bnx2_init_nic(bp);
5864         bnx2_netif_start(bp);
5865         return 0;
5866 }
5867
5868 static struct pci_driver bnx2_pci_driver = {
5869         .name           = DRV_MODULE_NAME,
5870         .id_table       = bnx2_pci_tbl,
5871         .probe          = bnx2_init_one,
5872         .remove         = __devexit_p(bnx2_remove_one),
5873         .suspend        = bnx2_suspend,
5874         .resume         = bnx2_resume,
5875 };
5876
5877 static int __init bnx2_init(void)
5878 {
5879         return pci_module_init(&bnx2_pci_driver);
5880 }
5881
5882 static void __exit bnx2_cleanup(void)
5883 {
5884         pci_unregister_driver(&bnx2_pci_driver);
5885 }
5886
5887 module_init(bnx2_init);
5888 module_exit(bnx2_cleanup);
5889
5890
5891