1 /* bnx2.c: Broadcom NX2 network driver.
3 * Copyright (c) 2004-2007 Broadcom Corporation
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
9 * Written by: Michael Chan (mchan@broadcom.com)
13 #include <linux/module.h>
14 #include <linux/moduleparam.h>
16 #include <linux/kernel.h>
17 #include <linux/timer.h>
18 #include <linux/errno.h>
19 #include <linux/ioport.h>
20 #include <linux/slab.h>
21 #include <linux/vmalloc.h>
22 #include <linux/interrupt.h>
23 #include <linux/pci.h>
24 #include <linux/init.h>
25 #include <linux/netdevice.h>
26 #include <linux/etherdevice.h>
27 #include <linux/skbuff.h>
28 #include <linux/dma-mapping.h>
29 #include <linux/bitops.h>
32 #include <linux/delay.h>
33 #include <asm/byteorder.h>
35 #include <linux/time.h>
36 #include <linux/ethtool.h>
37 #include <linux/mii.h>
38 #ifdef NETIF_F_HW_VLAN_TX
39 #include <linux/if_vlan.h>
44 #include <net/checksum.h>
45 #include <linux/workqueue.h>
46 #include <linux/crc32.h>
47 #include <linux/prefetch.h>
48 #include <linux/cache.h>
49 #include <linux/zlib.h>
55 #define FW_BUF_SIZE 0x8000
57 #define DRV_MODULE_NAME "bnx2"
58 #define PFX DRV_MODULE_NAME ": "
59 #define DRV_MODULE_VERSION "1.6.9"
60 #define DRV_MODULE_RELDATE "December 8, 2007"
62 #define RUN_AT(x) (jiffies + (x))
64 /* Time in jiffies before concluding the transmitter is hung. */
65 #define TX_TIMEOUT (5*HZ)
67 static const char version[] __devinitdata =
68 "Broadcom NetXtreme II Gigabit Ethernet Driver " DRV_MODULE_NAME " v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
70 MODULE_AUTHOR("Michael Chan <mchan@broadcom.com>");
71 MODULE_DESCRIPTION("Broadcom NetXtreme II BCM5706/5708 Driver");
72 MODULE_LICENSE("GPL");
73 MODULE_VERSION(DRV_MODULE_VERSION);
75 static int disable_msi = 0;
77 module_param(disable_msi, int, 0);
78 MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
92 /* indexed by board_t, above */
95 } board_info[] __devinitdata = {
96 { "Broadcom NetXtreme II BCM5706 1000Base-T" },
97 { "HP NC370T Multifunction Gigabit Server Adapter" },
98 { "HP NC370i Multifunction Gigabit Server Adapter" },
99 { "Broadcom NetXtreme II BCM5706 1000Base-SX" },
100 { "HP NC370F Multifunction Gigabit Server Adapter" },
101 { "Broadcom NetXtreme II BCM5708 1000Base-T" },
102 { "Broadcom NetXtreme II BCM5708 1000Base-SX" },
103 { "Broadcom NetXtreme II BCM5709 1000Base-T" },
104 { "Broadcom NetXtreme II BCM5709 1000Base-SX" },
107 static struct pci_device_id bnx2_pci_tbl[] = {
108 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
109 PCI_VENDOR_ID_HP, 0x3101, 0, 0, NC370T },
110 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
111 PCI_VENDOR_ID_HP, 0x3106, 0, 0, NC370I },
112 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
113 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706 },
114 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708,
115 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708 },
116 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
117 PCI_VENDOR_ID_HP, 0x3102, 0, 0, NC370F },
118 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
119 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706S },
120 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708S,
121 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708S },
122 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5709,
123 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5709 },
124 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5709S,
125 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5709S },
129 static struct flash_spec flash_table[] =
131 #define BUFFERED_FLAGS (BNX2_NV_BUFFERED | BNX2_NV_TRANSLATE)
132 #define NONBUFFERED_FLAGS (BNX2_NV_WREN)
134 {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400,
135 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
136 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
138 /* Expansion entry 0001 */
139 {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406,
140 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
141 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
143 /* Saifun SA25F010 (non-buffered flash) */
144 /* strap, cfg1, & write1 need updates */
145 {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406,
146 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
147 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2,
148 "Non-buffered flash (128kB)"},
149 /* Saifun SA25F020 (non-buffered flash) */
150 /* strap, cfg1, & write1 need updates */
151 {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406,
152 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
153 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4,
154 "Non-buffered flash (256kB)"},
155 /* Expansion entry 0100 */
156 {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406,
157 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
158 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
160 /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */
161 {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406,
162 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
163 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2,
164 "Entry 0101: ST M45PE10 (128kB non-bufferred)"},
165 /* Entry 0110: ST M45PE20 (non-buffered flash)*/
166 {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406,
167 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
168 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4,
169 "Entry 0110: ST M45PE20 (256kB non-bufferred)"},
170 /* Saifun SA25F005 (non-buffered flash) */
171 /* strap, cfg1, & write1 need updates */
172 {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406,
173 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
174 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE,
175 "Non-buffered flash (64kB)"},
177 {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400,
178 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
179 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
181 /* Expansion entry 1001 */
182 {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406,
183 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
184 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
186 /* Expansion entry 1010 */
187 {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406,
188 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
189 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
191 /* ATMEL AT45DB011B (buffered flash) */
192 {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400,
193 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
194 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE,
195 "Buffered flash (128kB)"},
196 /* Expansion entry 1100 */
197 {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406,
198 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
199 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
201 /* Expansion entry 1101 */
202 {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406,
203 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
204 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
206 /* Ateml Expansion entry 1110 */
207 {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400,
208 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
209 BUFFERED_FLASH_BYTE_ADDR_MASK, 0,
210 "Entry 1110 (Atmel)"},
211 /* ATMEL AT45DB021B (buffered flash) */
212 {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400,
213 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
214 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2,
215 "Buffered flash (256kB)"},
218 static struct flash_spec flash_5709 = {
219 .flags = BNX2_NV_BUFFERED,
220 .page_bits = BCM5709_FLASH_PAGE_BITS,
221 .page_size = BCM5709_FLASH_PAGE_SIZE,
222 .addr_mask = BCM5709_FLASH_BYTE_ADDR_MASK,
223 .total_size = BUFFERED_FLASH_TOTAL_SIZE*2,
224 .name = "5709 Buffered flash (256kB)",
227 MODULE_DEVICE_TABLE(pci, bnx2_pci_tbl);
229 static inline u32 bnx2_tx_avail(struct bnx2 *bp)
235 /* The ring uses 256 indices for 255 entries, one of them
236 * needs to be skipped.
238 diff = bp->tx_prod - bp->tx_cons;
239 if (unlikely(diff >= TX_DESC_CNT)) {
241 if (diff == TX_DESC_CNT)
242 diff = MAX_TX_DESC_CNT;
244 return (bp->tx_ring_size - diff);
248 bnx2_reg_rd_ind(struct bnx2 *bp, u32 offset)
252 spin_lock_bh(&bp->indirect_lock);
253 REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
254 val = REG_RD(bp, BNX2_PCICFG_REG_WINDOW);
255 spin_unlock_bh(&bp->indirect_lock);
260 bnx2_reg_wr_ind(struct bnx2 *bp, u32 offset, u32 val)
262 spin_lock_bh(&bp->indirect_lock);
263 REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
264 REG_WR(bp, BNX2_PCICFG_REG_WINDOW, val);
265 spin_unlock_bh(&bp->indirect_lock);
269 bnx2_ctx_wr(struct bnx2 *bp, u32 cid_addr, u32 offset, u32 val)
272 spin_lock_bh(&bp->indirect_lock);
273 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
276 REG_WR(bp, BNX2_CTX_CTX_DATA, val);
277 REG_WR(bp, BNX2_CTX_CTX_CTRL,
278 offset | BNX2_CTX_CTX_CTRL_WRITE_REQ);
279 for (i = 0; i < 5; i++) {
281 val = REG_RD(bp, BNX2_CTX_CTX_CTRL);
282 if ((val & BNX2_CTX_CTX_CTRL_WRITE_REQ) == 0)
287 REG_WR(bp, BNX2_CTX_DATA_ADR, offset);
288 REG_WR(bp, BNX2_CTX_DATA, val);
290 spin_unlock_bh(&bp->indirect_lock);
294 bnx2_read_phy(struct bnx2 *bp, u32 reg, u32 *val)
299 if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
300 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
301 val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
303 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
304 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
309 val1 = (bp->phy_addr << 21) | (reg << 16) |
310 BNX2_EMAC_MDIO_COMM_COMMAND_READ | BNX2_EMAC_MDIO_COMM_DISEXT |
311 BNX2_EMAC_MDIO_COMM_START_BUSY;
312 REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
314 for (i = 0; i < 50; i++) {
317 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
318 if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
321 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
322 val1 &= BNX2_EMAC_MDIO_COMM_DATA;
328 if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY) {
337 if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
338 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
339 val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
341 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
342 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
351 bnx2_write_phy(struct bnx2 *bp, u32 reg, u32 val)
356 if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
357 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
358 val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
360 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
361 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
366 val1 = (bp->phy_addr << 21) | (reg << 16) | val |
367 BNX2_EMAC_MDIO_COMM_COMMAND_WRITE |
368 BNX2_EMAC_MDIO_COMM_START_BUSY | BNX2_EMAC_MDIO_COMM_DISEXT;
369 REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
371 for (i = 0; i < 50; i++) {
374 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
375 if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
381 if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)
386 if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
387 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
388 val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
390 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
391 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
400 bnx2_disable_int(struct bnx2 *bp)
402 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
403 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
404 REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD);
408 bnx2_enable_int(struct bnx2 *bp)
410 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
411 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
412 BNX2_PCICFG_INT_ACK_CMD_MASK_INT | bp->last_status_idx);
414 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
415 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | bp->last_status_idx);
417 REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW);
421 bnx2_disable_int_sync(struct bnx2 *bp)
423 atomic_inc(&bp->intr_sem);
424 bnx2_disable_int(bp);
425 synchronize_irq(bp->pdev->irq);
429 bnx2_netif_stop(struct bnx2 *bp)
431 bnx2_disable_int_sync(bp);
432 if (netif_running(bp->dev)) {
433 napi_disable(&bp->napi);
434 netif_tx_disable(bp->dev);
435 bp->dev->trans_start = jiffies; /* prevent tx timeout */
440 bnx2_netif_start(struct bnx2 *bp)
442 if (atomic_dec_and_test(&bp->intr_sem)) {
443 if (netif_running(bp->dev)) {
444 netif_wake_queue(bp->dev);
445 napi_enable(&bp->napi);
452 bnx2_free_mem(struct bnx2 *bp)
456 for (i = 0; i < bp->ctx_pages; i++) {
457 if (bp->ctx_blk[i]) {
458 pci_free_consistent(bp->pdev, BCM_PAGE_SIZE,
460 bp->ctx_blk_mapping[i]);
461 bp->ctx_blk[i] = NULL;
464 if (bp->status_blk) {
465 pci_free_consistent(bp->pdev, bp->status_stats_size,
466 bp->status_blk, bp->status_blk_mapping);
467 bp->status_blk = NULL;
468 bp->stats_blk = NULL;
470 if (bp->tx_desc_ring) {
471 pci_free_consistent(bp->pdev, TXBD_RING_SIZE,
472 bp->tx_desc_ring, bp->tx_desc_mapping);
473 bp->tx_desc_ring = NULL;
475 kfree(bp->tx_buf_ring);
476 bp->tx_buf_ring = NULL;
477 for (i = 0; i < bp->rx_max_ring; i++) {
478 if (bp->rx_desc_ring[i])
479 pci_free_consistent(bp->pdev, RXBD_RING_SIZE,
481 bp->rx_desc_mapping[i]);
482 bp->rx_desc_ring[i] = NULL;
484 vfree(bp->rx_buf_ring);
485 bp->rx_buf_ring = NULL;
489 bnx2_alloc_mem(struct bnx2 *bp)
491 int i, status_blk_size;
493 bp->tx_buf_ring = kzalloc(SW_TXBD_RING_SIZE, GFP_KERNEL);
494 if (bp->tx_buf_ring == NULL)
497 bp->tx_desc_ring = pci_alloc_consistent(bp->pdev, TXBD_RING_SIZE,
498 &bp->tx_desc_mapping);
499 if (bp->tx_desc_ring == NULL)
502 bp->rx_buf_ring = vmalloc(SW_RXBD_RING_SIZE * bp->rx_max_ring);
503 if (bp->rx_buf_ring == NULL)
506 memset(bp->rx_buf_ring, 0, SW_RXBD_RING_SIZE * bp->rx_max_ring);
508 for (i = 0; i < bp->rx_max_ring; i++) {
509 bp->rx_desc_ring[i] =
510 pci_alloc_consistent(bp->pdev, RXBD_RING_SIZE,
511 &bp->rx_desc_mapping[i]);
512 if (bp->rx_desc_ring[i] == NULL)
517 /* Combine status and statistics blocks into one allocation. */
518 status_blk_size = L1_CACHE_ALIGN(sizeof(struct status_block));
519 bp->status_stats_size = status_blk_size +
520 sizeof(struct statistics_block);
522 bp->status_blk = pci_alloc_consistent(bp->pdev, bp->status_stats_size,
523 &bp->status_blk_mapping);
524 if (bp->status_blk == NULL)
527 memset(bp->status_blk, 0, bp->status_stats_size);
529 bp->stats_blk = (void *) ((unsigned long) bp->status_blk +
532 bp->stats_blk_mapping = bp->status_blk_mapping + status_blk_size;
534 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
535 bp->ctx_pages = 0x2000 / BCM_PAGE_SIZE;
536 if (bp->ctx_pages == 0)
538 for (i = 0; i < bp->ctx_pages; i++) {
539 bp->ctx_blk[i] = pci_alloc_consistent(bp->pdev,
541 &bp->ctx_blk_mapping[i]);
542 if (bp->ctx_blk[i] == NULL)
554 bnx2_report_fw_link(struct bnx2 *bp)
556 u32 fw_link_status = 0;
558 if (bp->phy_flags & REMOTE_PHY_CAP_FLAG)
564 switch (bp->line_speed) {
566 if (bp->duplex == DUPLEX_HALF)
567 fw_link_status = BNX2_LINK_STATUS_10HALF;
569 fw_link_status = BNX2_LINK_STATUS_10FULL;
572 if (bp->duplex == DUPLEX_HALF)
573 fw_link_status = BNX2_LINK_STATUS_100HALF;
575 fw_link_status = BNX2_LINK_STATUS_100FULL;
578 if (bp->duplex == DUPLEX_HALF)
579 fw_link_status = BNX2_LINK_STATUS_1000HALF;
581 fw_link_status = BNX2_LINK_STATUS_1000FULL;
584 if (bp->duplex == DUPLEX_HALF)
585 fw_link_status = BNX2_LINK_STATUS_2500HALF;
587 fw_link_status = BNX2_LINK_STATUS_2500FULL;
591 fw_link_status |= BNX2_LINK_STATUS_LINK_UP;
594 fw_link_status |= BNX2_LINK_STATUS_AN_ENABLED;
596 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
597 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
599 if (!(bmsr & BMSR_ANEGCOMPLETE) ||
600 bp->phy_flags & PHY_PARALLEL_DETECT_FLAG)
601 fw_link_status |= BNX2_LINK_STATUS_PARALLEL_DET;
603 fw_link_status |= BNX2_LINK_STATUS_AN_COMPLETE;
607 fw_link_status = BNX2_LINK_STATUS_LINK_DOWN;
609 REG_WR_IND(bp, bp->shmem_base + BNX2_LINK_STATUS, fw_link_status);
613 bnx2_xceiver_str(struct bnx2 *bp)
615 return ((bp->phy_port == PORT_FIBRE) ? "SerDes" :
616 ((bp->phy_flags & PHY_SERDES_FLAG) ? "Remote Copper" :
621 bnx2_report_link(struct bnx2 *bp)
624 netif_carrier_on(bp->dev);
625 printk(KERN_INFO PFX "%s NIC %s Link is Up, ", bp->dev->name,
626 bnx2_xceiver_str(bp));
628 printk("%d Mbps ", bp->line_speed);
630 if (bp->duplex == DUPLEX_FULL)
631 printk("full duplex");
633 printk("half duplex");
636 if (bp->flow_ctrl & FLOW_CTRL_RX) {
637 printk(", receive ");
638 if (bp->flow_ctrl & FLOW_CTRL_TX)
639 printk("& transmit ");
642 printk(", transmit ");
644 printk("flow control ON");
649 netif_carrier_off(bp->dev);
650 printk(KERN_ERR PFX "%s NIC %s Link is Down\n", bp->dev->name,
651 bnx2_xceiver_str(bp));
654 bnx2_report_fw_link(bp);
658 bnx2_resolve_flow_ctrl(struct bnx2 *bp)
660 u32 local_adv, remote_adv;
663 if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) !=
664 (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) {
666 if (bp->duplex == DUPLEX_FULL) {
667 bp->flow_ctrl = bp->req_flow_ctrl;
672 if (bp->duplex != DUPLEX_FULL) {
676 if ((bp->phy_flags & PHY_SERDES_FLAG) &&
677 (CHIP_NUM(bp) == CHIP_NUM_5708)) {
680 bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
681 if (val & BCM5708S_1000X_STAT1_TX_PAUSE)
682 bp->flow_ctrl |= FLOW_CTRL_TX;
683 if (val & BCM5708S_1000X_STAT1_RX_PAUSE)
684 bp->flow_ctrl |= FLOW_CTRL_RX;
688 bnx2_read_phy(bp, bp->mii_adv, &local_adv);
689 bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
691 if (bp->phy_flags & PHY_SERDES_FLAG) {
692 u32 new_local_adv = 0;
693 u32 new_remote_adv = 0;
695 if (local_adv & ADVERTISE_1000XPAUSE)
696 new_local_adv |= ADVERTISE_PAUSE_CAP;
697 if (local_adv & ADVERTISE_1000XPSE_ASYM)
698 new_local_adv |= ADVERTISE_PAUSE_ASYM;
699 if (remote_adv & ADVERTISE_1000XPAUSE)
700 new_remote_adv |= ADVERTISE_PAUSE_CAP;
701 if (remote_adv & ADVERTISE_1000XPSE_ASYM)
702 new_remote_adv |= ADVERTISE_PAUSE_ASYM;
704 local_adv = new_local_adv;
705 remote_adv = new_remote_adv;
708 /* See Table 28B-3 of 802.3ab-1999 spec. */
709 if (local_adv & ADVERTISE_PAUSE_CAP) {
710 if(local_adv & ADVERTISE_PAUSE_ASYM) {
711 if (remote_adv & ADVERTISE_PAUSE_CAP) {
712 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
714 else if (remote_adv & ADVERTISE_PAUSE_ASYM) {
715 bp->flow_ctrl = FLOW_CTRL_RX;
719 if (remote_adv & ADVERTISE_PAUSE_CAP) {
720 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
724 else if (local_adv & ADVERTISE_PAUSE_ASYM) {
725 if ((remote_adv & ADVERTISE_PAUSE_CAP) &&
726 (remote_adv & ADVERTISE_PAUSE_ASYM)) {
728 bp->flow_ctrl = FLOW_CTRL_TX;
734 bnx2_5709s_linkup(struct bnx2 *bp)
740 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_GP_STATUS);
741 bnx2_read_phy(bp, MII_BNX2_GP_TOP_AN_STATUS1, &val);
742 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
744 if ((bp->autoneg & AUTONEG_SPEED) == 0) {
745 bp->line_speed = bp->req_line_speed;
746 bp->duplex = bp->req_duplex;
749 speed = val & MII_BNX2_GP_TOP_AN_SPEED_MSK;
751 case MII_BNX2_GP_TOP_AN_SPEED_10:
752 bp->line_speed = SPEED_10;
754 case MII_BNX2_GP_TOP_AN_SPEED_100:
755 bp->line_speed = SPEED_100;
757 case MII_BNX2_GP_TOP_AN_SPEED_1G:
758 case MII_BNX2_GP_TOP_AN_SPEED_1GKV:
759 bp->line_speed = SPEED_1000;
761 case MII_BNX2_GP_TOP_AN_SPEED_2_5G:
762 bp->line_speed = SPEED_2500;
765 if (val & MII_BNX2_GP_TOP_AN_FD)
766 bp->duplex = DUPLEX_FULL;
768 bp->duplex = DUPLEX_HALF;
773 bnx2_5708s_linkup(struct bnx2 *bp)
778 bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
779 switch (val & BCM5708S_1000X_STAT1_SPEED_MASK) {
780 case BCM5708S_1000X_STAT1_SPEED_10:
781 bp->line_speed = SPEED_10;
783 case BCM5708S_1000X_STAT1_SPEED_100:
784 bp->line_speed = SPEED_100;
786 case BCM5708S_1000X_STAT1_SPEED_1G:
787 bp->line_speed = SPEED_1000;
789 case BCM5708S_1000X_STAT1_SPEED_2G5:
790 bp->line_speed = SPEED_2500;
793 if (val & BCM5708S_1000X_STAT1_FD)
794 bp->duplex = DUPLEX_FULL;
796 bp->duplex = DUPLEX_HALF;
802 bnx2_5706s_linkup(struct bnx2 *bp)
804 u32 bmcr, local_adv, remote_adv, common;
807 bp->line_speed = SPEED_1000;
809 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
810 if (bmcr & BMCR_FULLDPLX) {
811 bp->duplex = DUPLEX_FULL;
814 bp->duplex = DUPLEX_HALF;
817 if (!(bmcr & BMCR_ANENABLE)) {
821 bnx2_read_phy(bp, bp->mii_adv, &local_adv);
822 bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
824 common = local_adv & remote_adv;
825 if (common & (ADVERTISE_1000XHALF | ADVERTISE_1000XFULL)) {
827 if (common & ADVERTISE_1000XFULL) {
828 bp->duplex = DUPLEX_FULL;
831 bp->duplex = DUPLEX_HALF;
839 bnx2_copper_linkup(struct bnx2 *bp)
843 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
844 if (bmcr & BMCR_ANENABLE) {
845 u32 local_adv, remote_adv, common;
847 bnx2_read_phy(bp, MII_CTRL1000, &local_adv);
848 bnx2_read_phy(bp, MII_STAT1000, &remote_adv);
850 common = local_adv & (remote_adv >> 2);
851 if (common & ADVERTISE_1000FULL) {
852 bp->line_speed = SPEED_1000;
853 bp->duplex = DUPLEX_FULL;
855 else if (common & ADVERTISE_1000HALF) {
856 bp->line_speed = SPEED_1000;
857 bp->duplex = DUPLEX_HALF;
860 bnx2_read_phy(bp, bp->mii_adv, &local_adv);
861 bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
863 common = local_adv & remote_adv;
864 if (common & ADVERTISE_100FULL) {
865 bp->line_speed = SPEED_100;
866 bp->duplex = DUPLEX_FULL;
868 else if (common & ADVERTISE_100HALF) {
869 bp->line_speed = SPEED_100;
870 bp->duplex = DUPLEX_HALF;
872 else if (common & ADVERTISE_10FULL) {
873 bp->line_speed = SPEED_10;
874 bp->duplex = DUPLEX_FULL;
876 else if (common & ADVERTISE_10HALF) {
877 bp->line_speed = SPEED_10;
878 bp->duplex = DUPLEX_HALF;
887 if (bmcr & BMCR_SPEED100) {
888 bp->line_speed = SPEED_100;
891 bp->line_speed = SPEED_10;
893 if (bmcr & BMCR_FULLDPLX) {
894 bp->duplex = DUPLEX_FULL;
897 bp->duplex = DUPLEX_HALF;
905 bnx2_set_mac_link(struct bnx2 *bp)
909 REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x2620);
910 if (bp->link_up && (bp->line_speed == SPEED_1000) &&
911 (bp->duplex == DUPLEX_HALF)) {
912 REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x26ff);
915 /* Configure the EMAC mode register. */
916 val = REG_RD(bp, BNX2_EMAC_MODE);
918 val &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
919 BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK |
920 BNX2_EMAC_MODE_25G_MODE);
923 switch (bp->line_speed) {
925 if (CHIP_NUM(bp) != CHIP_NUM_5706) {
926 val |= BNX2_EMAC_MODE_PORT_MII_10M;
931 val |= BNX2_EMAC_MODE_PORT_MII;
934 val |= BNX2_EMAC_MODE_25G_MODE;
937 val |= BNX2_EMAC_MODE_PORT_GMII;
942 val |= BNX2_EMAC_MODE_PORT_GMII;
945 /* Set the MAC to operate in the appropriate duplex mode. */
946 if (bp->duplex == DUPLEX_HALF)
947 val |= BNX2_EMAC_MODE_HALF_DUPLEX;
948 REG_WR(bp, BNX2_EMAC_MODE, val);
950 /* Enable/disable rx PAUSE. */
951 bp->rx_mode &= ~BNX2_EMAC_RX_MODE_FLOW_EN;
953 if (bp->flow_ctrl & FLOW_CTRL_RX)
954 bp->rx_mode |= BNX2_EMAC_RX_MODE_FLOW_EN;
955 REG_WR(bp, BNX2_EMAC_RX_MODE, bp->rx_mode);
957 /* Enable/disable tx PAUSE. */
958 val = REG_RD(bp, BNX2_EMAC_TX_MODE);
959 val &= ~BNX2_EMAC_TX_MODE_FLOW_EN;
961 if (bp->flow_ctrl & FLOW_CTRL_TX)
962 val |= BNX2_EMAC_TX_MODE_FLOW_EN;
963 REG_WR(bp, BNX2_EMAC_TX_MODE, val);
965 /* Acknowledge the interrupt. */
966 REG_WR(bp, BNX2_EMAC_STATUS, BNX2_EMAC_STATUS_LINK_CHANGE);
972 bnx2_enable_bmsr1(struct bnx2 *bp)
974 if ((bp->phy_flags & PHY_SERDES_FLAG) &&
975 (CHIP_NUM(bp) == CHIP_NUM_5709))
976 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
977 MII_BNX2_BLK_ADDR_GP_STATUS);
981 bnx2_disable_bmsr1(struct bnx2 *bp)
983 if ((bp->phy_flags & PHY_SERDES_FLAG) &&
984 (CHIP_NUM(bp) == CHIP_NUM_5709))
985 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
986 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
990 bnx2_test_and_enable_2g5(struct bnx2 *bp)
995 if (!(bp->phy_flags & PHY_2_5G_CAPABLE_FLAG))
998 if (bp->autoneg & AUTONEG_SPEED)
999 bp->advertising |= ADVERTISED_2500baseX_Full;
1001 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1002 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
1004 bnx2_read_phy(bp, bp->mii_up1, &up1);
1005 if (!(up1 & BCM5708S_UP1_2G5)) {
1006 up1 |= BCM5708S_UP1_2G5;
1007 bnx2_write_phy(bp, bp->mii_up1, up1);
1011 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1012 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1013 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1019 bnx2_test_and_disable_2g5(struct bnx2 *bp)
1024 if (!(bp->phy_flags & PHY_2_5G_CAPABLE_FLAG))
1027 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1028 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
1030 bnx2_read_phy(bp, bp->mii_up1, &up1);
1031 if (up1 & BCM5708S_UP1_2G5) {
1032 up1 &= ~BCM5708S_UP1_2G5;
1033 bnx2_write_phy(bp, bp->mii_up1, up1);
1037 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1038 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1039 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1045 bnx2_enable_forced_2g5(struct bnx2 *bp)
1049 if (!(bp->phy_flags & PHY_2_5G_CAPABLE_FLAG))
1052 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1055 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1056 MII_BNX2_BLK_ADDR_SERDES_DIG);
1057 bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_MISC1, &val);
1058 val &= ~MII_BNX2_SD_MISC1_FORCE_MSK;
1059 val |= MII_BNX2_SD_MISC1_FORCE | MII_BNX2_SD_MISC1_FORCE_2_5G;
1060 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val);
1062 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1063 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1064 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1066 } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
1067 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1068 bmcr |= BCM5708S_BMCR_FORCE_2500;
1071 if (bp->autoneg & AUTONEG_SPEED) {
1072 bmcr &= ~BMCR_ANENABLE;
1073 if (bp->req_duplex == DUPLEX_FULL)
1074 bmcr |= BMCR_FULLDPLX;
1076 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
1080 bnx2_disable_forced_2g5(struct bnx2 *bp)
1084 if (!(bp->phy_flags & PHY_2_5G_CAPABLE_FLAG))
1087 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1090 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1091 MII_BNX2_BLK_ADDR_SERDES_DIG);
1092 bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_MISC1, &val);
1093 val &= ~MII_BNX2_SD_MISC1_FORCE;
1094 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val);
1096 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1097 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1098 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1100 } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
1101 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1102 bmcr &= ~BCM5708S_BMCR_FORCE_2500;
1105 if (bp->autoneg & AUTONEG_SPEED)
1106 bmcr |= BMCR_SPEED1000 | BMCR_ANENABLE | BMCR_ANRESTART;
1107 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
1111 bnx2_set_link(struct bnx2 *bp)
1116 if (bp->loopback == MAC_LOOPBACK || bp->loopback == PHY_LOOPBACK) {
1121 if (bp->phy_flags & REMOTE_PHY_CAP_FLAG)
1124 link_up = bp->link_up;
1126 bnx2_enable_bmsr1(bp);
1127 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
1128 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
1129 bnx2_disable_bmsr1(bp);
1131 if ((bp->phy_flags & PHY_SERDES_FLAG) &&
1132 (CHIP_NUM(bp) == CHIP_NUM_5706)) {
1135 val = REG_RD(bp, BNX2_EMAC_STATUS);
1136 if (val & BNX2_EMAC_STATUS_LINK)
1137 bmsr |= BMSR_LSTATUS;
1139 bmsr &= ~BMSR_LSTATUS;
1142 if (bmsr & BMSR_LSTATUS) {
1145 if (bp->phy_flags & PHY_SERDES_FLAG) {
1146 if (CHIP_NUM(bp) == CHIP_NUM_5706)
1147 bnx2_5706s_linkup(bp);
1148 else if (CHIP_NUM(bp) == CHIP_NUM_5708)
1149 bnx2_5708s_linkup(bp);
1150 else if (CHIP_NUM(bp) == CHIP_NUM_5709)
1151 bnx2_5709s_linkup(bp);
1154 bnx2_copper_linkup(bp);
1156 bnx2_resolve_flow_ctrl(bp);
1159 if ((bp->phy_flags & PHY_SERDES_FLAG) &&
1160 (bp->autoneg & AUTONEG_SPEED))
1161 bnx2_disable_forced_2g5(bp);
1163 bp->phy_flags &= ~PHY_PARALLEL_DETECT_FLAG;
1167 if (bp->link_up != link_up) {
1168 bnx2_report_link(bp);
1171 bnx2_set_mac_link(bp);
1177 bnx2_reset_phy(struct bnx2 *bp)
1182 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_RESET);
1184 #define PHY_RESET_MAX_WAIT 100
1185 for (i = 0; i < PHY_RESET_MAX_WAIT; i++) {
1188 bnx2_read_phy(bp, bp->mii_bmcr, ®);
1189 if (!(reg & BMCR_RESET)) {
1194 if (i == PHY_RESET_MAX_WAIT) {
1201 bnx2_phy_get_pause_adv(struct bnx2 *bp)
1205 if ((bp->req_flow_ctrl & (FLOW_CTRL_RX | FLOW_CTRL_TX)) ==
1206 (FLOW_CTRL_RX | FLOW_CTRL_TX)) {
1208 if (bp->phy_flags & PHY_SERDES_FLAG) {
1209 adv = ADVERTISE_1000XPAUSE;
1212 adv = ADVERTISE_PAUSE_CAP;
1215 else if (bp->req_flow_ctrl & FLOW_CTRL_TX) {
1216 if (bp->phy_flags & PHY_SERDES_FLAG) {
1217 adv = ADVERTISE_1000XPSE_ASYM;
1220 adv = ADVERTISE_PAUSE_ASYM;
1223 else if (bp->req_flow_ctrl & FLOW_CTRL_RX) {
1224 if (bp->phy_flags & PHY_SERDES_FLAG) {
1225 adv = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1228 adv = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1234 static int bnx2_fw_sync(struct bnx2 *, u32, int);
1237 bnx2_setup_remote_phy(struct bnx2 *bp, u8 port)
1239 u32 speed_arg = 0, pause_adv;
1241 pause_adv = bnx2_phy_get_pause_adv(bp);
1243 if (bp->autoneg & AUTONEG_SPEED) {
1244 speed_arg |= BNX2_NETLINK_SET_LINK_ENABLE_AUTONEG;
1245 if (bp->advertising & ADVERTISED_10baseT_Half)
1246 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_10HALF;
1247 if (bp->advertising & ADVERTISED_10baseT_Full)
1248 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_10FULL;
1249 if (bp->advertising & ADVERTISED_100baseT_Half)
1250 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_100HALF;
1251 if (bp->advertising & ADVERTISED_100baseT_Full)
1252 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_100FULL;
1253 if (bp->advertising & ADVERTISED_1000baseT_Full)
1254 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_1GFULL;
1255 if (bp->advertising & ADVERTISED_2500baseX_Full)
1256 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_2G5FULL;
1258 if (bp->req_line_speed == SPEED_2500)
1259 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_2G5FULL;
1260 else if (bp->req_line_speed == SPEED_1000)
1261 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_1GFULL;
1262 else if (bp->req_line_speed == SPEED_100) {
1263 if (bp->req_duplex == DUPLEX_FULL)
1264 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_100FULL;
1266 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_100HALF;
1267 } else if (bp->req_line_speed == SPEED_10) {
1268 if (bp->req_duplex == DUPLEX_FULL)
1269 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_10FULL;
1271 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_10HALF;
1275 if (pause_adv & (ADVERTISE_1000XPAUSE | ADVERTISE_PAUSE_CAP))
1276 speed_arg |= BNX2_NETLINK_SET_LINK_FC_SYM_PAUSE;
1277 if (pause_adv & (ADVERTISE_1000XPSE_ASYM | ADVERTISE_1000XPSE_ASYM))
1278 speed_arg |= BNX2_NETLINK_SET_LINK_FC_ASYM_PAUSE;
1280 if (port == PORT_TP)
1281 speed_arg |= BNX2_NETLINK_SET_LINK_PHY_APP_REMOTE |
1282 BNX2_NETLINK_SET_LINK_ETH_AT_WIRESPEED;
1284 REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_MB_ARG0, speed_arg);
1286 spin_unlock_bh(&bp->phy_lock);
1287 bnx2_fw_sync(bp, BNX2_DRV_MSG_CODE_CMD_SET_LINK, 0);
1288 spin_lock_bh(&bp->phy_lock);
1294 bnx2_setup_serdes_phy(struct bnx2 *bp, u8 port)
1299 if (bp->phy_flags & REMOTE_PHY_CAP_FLAG)
1300 return (bnx2_setup_remote_phy(bp, port));
1302 if (!(bp->autoneg & AUTONEG_SPEED)) {
1304 int force_link_down = 0;
1306 if (bp->req_line_speed == SPEED_2500) {
1307 if (!bnx2_test_and_enable_2g5(bp))
1308 force_link_down = 1;
1309 } else if (bp->req_line_speed == SPEED_1000) {
1310 if (bnx2_test_and_disable_2g5(bp))
1311 force_link_down = 1;
1313 bnx2_read_phy(bp, bp->mii_adv, &adv);
1314 adv &= ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF);
1316 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1317 new_bmcr = bmcr & ~BMCR_ANENABLE;
1318 new_bmcr |= BMCR_SPEED1000;
1320 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1321 if (bp->req_line_speed == SPEED_2500)
1322 bnx2_enable_forced_2g5(bp);
1323 else if (bp->req_line_speed == SPEED_1000) {
1324 bnx2_disable_forced_2g5(bp);
1325 new_bmcr &= ~0x2000;
1328 } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
1329 if (bp->req_line_speed == SPEED_2500)
1330 new_bmcr |= BCM5708S_BMCR_FORCE_2500;
1332 new_bmcr = bmcr & ~BCM5708S_BMCR_FORCE_2500;
1335 if (bp->req_duplex == DUPLEX_FULL) {
1336 adv |= ADVERTISE_1000XFULL;
1337 new_bmcr |= BMCR_FULLDPLX;
1340 adv |= ADVERTISE_1000XHALF;
1341 new_bmcr &= ~BMCR_FULLDPLX;
1343 if ((new_bmcr != bmcr) || (force_link_down)) {
1344 /* Force a link down visible on the other side */
1346 bnx2_write_phy(bp, bp->mii_adv, adv &
1347 ~(ADVERTISE_1000XFULL |
1348 ADVERTISE_1000XHALF));
1349 bnx2_write_phy(bp, bp->mii_bmcr, bmcr |
1350 BMCR_ANRESTART | BMCR_ANENABLE);
1353 netif_carrier_off(bp->dev);
1354 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
1355 bnx2_report_link(bp);
1357 bnx2_write_phy(bp, bp->mii_adv, adv);
1358 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
1360 bnx2_resolve_flow_ctrl(bp);
1361 bnx2_set_mac_link(bp);
1366 bnx2_test_and_enable_2g5(bp);
1368 if (bp->advertising & ADVERTISED_1000baseT_Full)
1369 new_adv |= ADVERTISE_1000XFULL;
1371 new_adv |= bnx2_phy_get_pause_adv(bp);
1373 bnx2_read_phy(bp, bp->mii_adv, &adv);
1374 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1376 bp->serdes_an_pending = 0;
1377 if ((adv != new_adv) || ((bmcr & BMCR_ANENABLE) == 0)) {
1378 /* Force a link down visible on the other side */
1380 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
1381 spin_unlock_bh(&bp->phy_lock);
1383 spin_lock_bh(&bp->phy_lock);
1386 bnx2_write_phy(bp, bp->mii_adv, new_adv);
1387 bnx2_write_phy(bp, bp->mii_bmcr, bmcr | BMCR_ANRESTART |
1389 /* Speed up link-up time when the link partner
1390 * does not autonegotiate which is very common
1391 * in blade servers. Some blade servers use
1392 * IPMI for kerboard input and it's important
1393 * to minimize link disruptions. Autoneg. involves
1394 * exchanging base pages plus 3 next pages and
1395 * normally completes in about 120 msec.
1397 bp->current_interval = SERDES_AN_TIMEOUT;
1398 bp->serdes_an_pending = 1;
1399 mod_timer(&bp->timer, jiffies + bp->current_interval);
1401 bnx2_resolve_flow_ctrl(bp);
1402 bnx2_set_mac_link(bp);
1408 #define ETHTOOL_ALL_FIBRE_SPEED \
1409 (bp->phy_flags & PHY_2_5G_CAPABLE_FLAG) ? \
1410 (ADVERTISED_2500baseX_Full | ADVERTISED_1000baseT_Full) :\
1411 (ADVERTISED_1000baseT_Full)
1413 #define ETHTOOL_ALL_COPPER_SPEED \
1414 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full | \
1415 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full | \
1416 ADVERTISED_1000baseT_Full)
1418 #define PHY_ALL_10_100_SPEED (ADVERTISE_10HALF | ADVERTISE_10FULL | \
1419 ADVERTISE_100HALF | ADVERTISE_100FULL | ADVERTISE_CSMA)
1421 #define PHY_ALL_1000_SPEED (ADVERTISE_1000HALF | ADVERTISE_1000FULL)
1424 bnx2_set_default_remote_link(struct bnx2 *bp)
1428 if (bp->phy_port == PORT_TP)
1429 link = REG_RD_IND(bp, bp->shmem_base + BNX2_RPHY_COPPER_LINK);
1431 link = REG_RD_IND(bp, bp->shmem_base + BNX2_RPHY_SERDES_LINK);
1433 if (link & BNX2_NETLINK_SET_LINK_ENABLE_AUTONEG) {
1434 bp->req_line_speed = 0;
1435 bp->autoneg |= AUTONEG_SPEED;
1436 bp->advertising = ADVERTISED_Autoneg;
1437 if (link & BNX2_NETLINK_SET_LINK_SPEED_10HALF)
1438 bp->advertising |= ADVERTISED_10baseT_Half;
1439 if (link & BNX2_NETLINK_SET_LINK_SPEED_10FULL)
1440 bp->advertising |= ADVERTISED_10baseT_Full;
1441 if (link & BNX2_NETLINK_SET_LINK_SPEED_100HALF)
1442 bp->advertising |= ADVERTISED_100baseT_Half;
1443 if (link & BNX2_NETLINK_SET_LINK_SPEED_100FULL)
1444 bp->advertising |= ADVERTISED_100baseT_Full;
1445 if (link & BNX2_NETLINK_SET_LINK_SPEED_1GFULL)
1446 bp->advertising |= ADVERTISED_1000baseT_Full;
1447 if (link & BNX2_NETLINK_SET_LINK_SPEED_2G5FULL)
1448 bp->advertising |= ADVERTISED_2500baseX_Full;
1451 bp->advertising = 0;
1452 bp->req_duplex = DUPLEX_FULL;
1453 if (link & BNX2_NETLINK_SET_LINK_SPEED_10) {
1454 bp->req_line_speed = SPEED_10;
1455 if (link & BNX2_NETLINK_SET_LINK_SPEED_10HALF)
1456 bp->req_duplex = DUPLEX_HALF;
1458 if (link & BNX2_NETLINK_SET_LINK_SPEED_100) {
1459 bp->req_line_speed = SPEED_100;
1460 if (link & BNX2_NETLINK_SET_LINK_SPEED_100HALF)
1461 bp->req_duplex = DUPLEX_HALF;
1463 if (link & BNX2_NETLINK_SET_LINK_SPEED_1GFULL)
1464 bp->req_line_speed = SPEED_1000;
1465 if (link & BNX2_NETLINK_SET_LINK_SPEED_2G5FULL)
1466 bp->req_line_speed = SPEED_2500;
1471 bnx2_set_default_link(struct bnx2 *bp)
1473 if (bp->phy_flags & REMOTE_PHY_CAP_FLAG)
1474 return bnx2_set_default_remote_link(bp);
1476 bp->autoneg = AUTONEG_SPEED | AUTONEG_FLOW_CTRL;
1477 bp->req_line_speed = 0;
1478 if (bp->phy_flags & PHY_SERDES_FLAG) {
1481 bp->advertising = ETHTOOL_ALL_FIBRE_SPEED | ADVERTISED_Autoneg;
1483 reg = REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_HW_CFG_CONFIG);
1484 reg &= BNX2_PORT_HW_CFG_CFG_DFLT_LINK_MASK;
1485 if (reg == BNX2_PORT_HW_CFG_CFG_DFLT_LINK_1G) {
1487 bp->req_line_speed = bp->line_speed = SPEED_1000;
1488 bp->req_duplex = DUPLEX_FULL;
1491 bp->advertising = ETHTOOL_ALL_COPPER_SPEED | ADVERTISED_Autoneg;
1495 bnx2_send_heart_beat(struct bnx2 *bp)
1500 spin_lock(&bp->indirect_lock);
1501 msg = (u32) (++bp->fw_drv_pulse_wr_seq & BNX2_DRV_PULSE_SEQ_MASK);
1502 addr = bp->shmem_base + BNX2_DRV_PULSE_MB;
1503 REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, addr);
1504 REG_WR(bp, BNX2_PCICFG_REG_WINDOW, msg);
1505 spin_unlock(&bp->indirect_lock);
1509 bnx2_remote_phy_event(struct bnx2 *bp)
1512 u8 link_up = bp->link_up;
1515 msg = REG_RD_IND(bp, bp->shmem_base + BNX2_LINK_STATUS);
1517 if (msg & BNX2_LINK_STATUS_HEART_BEAT_EXPIRED)
1518 bnx2_send_heart_beat(bp);
1520 msg &= ~BNX2_LINK_STATUS_HEART_BEAT_EXPIRED;
1522 if ((msg & BNX2_LINK_STATUS_LINK_UP) == BNX2_LINK_STATUS_LINK_DOWN)
1528 speed = msg & BNX2_LINK_STATUS_SPEED_MASK;
1529 bp->duplex = DUPLEX_FULL;
1531 case BNX2_LINK_STATUS_10HALF:
1532 bp->duplex = DUPLEX_HALF;
1533 case BNX2_LINK_STATUS_10FULL:
1534 bp->line_speed = SPEED_10;
1536 case BNX2_LINK_STATUS_100HALF:
1537 bp->duplex = DUPLEX_HALF;
1538 case BNX2_LINK_STATUS_100BASE_T4:
1539 case BNX2_LINK_STATUS_100FULL:
1540 bp->line_speed = SPEED_100;
1542 case BNX2_LINK_STATUS_1000HALF:
1543 bp->duplex = DUPLEX_HALF;
1544 case BNX2_LINK_STATUS_1000FULL:
1545 bp->line_speed = SPEED_1000;
1547 case BNX2_LINK_STATUS_2500HALF:
1548 bp->duplex = DUPLEX_HALF;
1549 case BNX2_LINK_STATUS_2500FULL:
1550 bp->line_speed = SPEED_2500;
1557 spin_lock(&bp->phy_lock);
1559 if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) !=
1560 (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) {
1561 if (bp->duplex == DUPLEX_FULL)
1562 bp->flow_ctrl = bp->req_flow_ctrl;
1564 if (msg & BNX2_LINK_STATUS_TX_FC_ENABLED)
1565 bp->flow_ctrl |= FLOW_CTRL_TX;
1566 if (msg & BNX2_LINK_STATUS_RX_FC_ENABLED)
1567 bp->flow_ctrl |= FLOW_CTRL_RX;
1570 old_port = bp->phy_port;
1571 if (msg & BNX2_LINK_STATUS_SERDES_LINK)
1572 bp->phy_port = PORT_FIBRE;
1574 bp->phy_port = PORT_TP;
1576 if (old_port != bp->phy_port)
1577 bnx2_set_default_link(bp);
1579 spin_unlock(&bp->phy_lock);
1581 if (bp->link_up != link_up)
1582 bnx2_report_link(bp);
1584 bnx2_set_mac_link(bp);
1588 bnx2_set_remote_link(struct bnx2 *bp)
1592 evt_code = REG_RD_IND(bp, bp->shmem_base + BNX2_FW_EVT_CODE_MB);
1594 case BNX2_FW_EVT_CODE_LINK_EVENT:
1595 bnx2_remote_phy_event(bp);
1597 case BNX2_FW_EVT_CODE_SW_TIMER_EXPIRATION_EVENT:
1599 bnx2_send_heart_beat(bp);
1606 bnx2_setup_copper_phy(struct bnx2 *bp)
1611 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1613 if (bp->autoneg & AUTONEG_SPEED) {
1614 u32 adv_reg, adv1000_reg;
1615 u32 new_adv_reg = 0;
1616 u32 new_adv1000_reg = 0;
1618 bnx2_read_phy(bp, bp->mii_adv, &adv_reg);
1619 adv_reg &= (PHY_ALL_10_100_SPEED | ADVERTISE_PAUSE_CAP |
1620 ADVERTISE_PAUSE_ASYM);
1622 bnx2_read_phy(bp, MII_CTRL1000, &adv1000_reg);
1623 adv1000_reg &= PHY_ALL_1000_SPEED;
1625 if (bp->advertising & ADVERTISED_10baseT_Half)
1626 new_adv_reg |= ADVERTISE_10HALF;
1627 if (bp->advertising & ADVERTISED_10baseT_Full)
1628 new_adv_reg |= ADVERTISE_10FULL;
1629 if (bp->advertising & ADVERTISED_100baseT_Half)
1630 new_adv_reg |= ADVERTISE_100HALF;
1631 if (bp->advertising & ADVERTISED_100baseT_Full)
1632 new_adv_reg |= ADVERTISE_100FULL;
1633 if (bp->advertising & ADVERTISED_1000baseT_Full)
1634 new_adv1000_reg |= ADVERTISE_1000FULL;
1636 new_adv_reg |= ADVERTISE_CSMA;
1638 new_adv_reg |= bnx2_phy_get_pause_adv(bp);
1640 if ((adv1000_reg != new_adv1000_reg) ||
1641 (adv_reg != new_adv_reg) ||
1642 ((bmcr & BMCR_ANENABLE) == 0)) {
1644 bnx2_write_phy(bp, bp->mii_adv, new_adv_reg);
1645 bnx2_write_phy(bp, MII_CTRL1000, new_adv1000_reg);
1646 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_ANRESTART |
1649 else if (bp->link_up) {
1650 /* Flow ctrl may have changed from auto to forced */
1651 /* or vice-versa. */
1653 bnx2_resolve_flow_ctrl(bp);
1654 bnx2_set_mac_link(bp);
1660 if (bp->req_line_speed == SPEED_100) {
1661 new_bmcr |= BMCR_SPEED100;
1663 if (bp->req_duplex == DUPLEX_FULL) {
1664 new_bmcr |= BMCR_FULLDPLX;
1666 if (new_bmcr != bmcr) {
1669 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
1670 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
1672 if (bmsr & BMSR_LSTATUS) {
1673 /* Force link down */
1674 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
1675 spin_unlock_bh(&bp->phy_lock);
1677 spin_lock_bh(&bp->phy_lock);
1679 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
1680 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
1683 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
1685 /* Normally, the new speed is setup after the link has
1686 * gone down and up again. In some cases, link will not go
1687 * down so we need to set up the new speed here.
1689 if (bmsr & BMSR_LSTATUS) {
1690 bp->line_speed = bp->req_line_speed;
1691 bp->duplex = bp->req_duplex;
1692 bnx2_resolve_flow_ctrl(bp);
1693 bnx2_set_mac_link(bp);
1696 bnx2_resolve_flow_ctrl(bp);
1697 bnx2_set_mac_link(bp);
1703 bnx2_setup_phy(struct bnx2 *bp, u8 port)
1705 if (bp->loopback == MAC_LOOPBACK)
1708 if (bp->phy_flags & PHY_SERDES_FLAG) {
1709 return (bnx2_setup_serdes_phy(bp, port));
1712 return (bnx2_setup_copper_phy(bp));
1717 bnx2_init_5709s_phy(struct bnx2 *bp)
1721 bp->mii_bmcr = MII_BMCR + 0x10;
1722 bp->mii_bmsr = MII_BMSR + 0x10;
1723 bp->mii_bmsr1 = MII_BNX2_GP_TOP_AN_STATUS1;
1724 bp->mii_adv = MII_ADVERTISE + 0x10;
1725 bp->mii_lpa = MII_LPA + 0x10;
1726 bp->mii_up1 = MII_BNX2_OVER1G_UP1;
1728 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_AER);
1729 bnx2_write_phy(bp, MII_BNX2_AER_AER, MII_BNX2_AER_AER_AN_MMD);
1731 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1734 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_SERDES_DIG);
1736 bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_1000XCTL1, &val);
1737 val &= ~MII_BNX2_SD_1000XCTL1_AUTODET;
1738 val |= MII_BNX2_SD_1000XCTL1_FIBER;
1739 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_1000XCTL1, val);
1741 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
1742 bnx2_read_phy(bp, MII_BNX2_OVER1G_UP1, &val);
1743 if (bp->phy_flags & PHY_2_5G_CAPABLE_FLAG)
1744 val |= BCM5708S_UP1_2G5;
1746 val &= ~BCM5708S_UP1_2G5;
1747 bnx2_write_phy(bp, MII_BNX2_OVER1G_UP1, val);
1749 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_BAM_NXTPG);
1750 bnx2_read_phy(bp, MII_BNX2_BAM_NXTPG_CTL, &val);
1751 val |= MII_BNX2_NXTPG_CTL_T2 | MII_BNX2_NXTPG_CTL_BAM;
1752 bnx2_write_phy(bp, MII_BNX2_BAM_NXTPG_CTL, val);
1754 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_CL73_USERB0);
1756 val = MII_BNX2_CL73_BAM_EN | MII_BNX2_CL73_BAM_STA_MGR_EN |
1757 MII_BNX2_CL73_BAM_NP_AFT_BP_EN;
1758 bnx2_write_phy(bp, MII_BNX2_CL73_BAM_CTL1, val);
1760 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1766 bnx2_init_5708s_phy(struct bnx2 *bp)
1772 bp->mii_up1 = BCM5708S_UP1;
1774 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG3);
1775 bnx2_write_phy(bp, BCM5708S_DIG_3_0, BCM5708S_DIG_3_0_USE_IEEE);
1776 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
1778 bnx2_read_phy(bp, BCM5708S_1000X_CTL1, &val);
1779 val |= BCM5708S_1000X_CTL1_FIBER_MODE | BCM5708S_1000X_CTL1_AUTODET_EN;
1780 bnx2_write_phy(bp, BCM5708S_1000X_CTL1, val);
1782 bnx2_read_phy(bp, BCM5708S_1000X_CTL2, &val);
1783 val |= BCM5708S_1000X_CTL2_PLLEL_DET_EN;
1784 bnx2_write_phy(bp, BCM5708S_1000X_CTL2, val);
1786 if (bp->phy_flags & PHY_2_5G_CAPABLE_FLAG) {
1787 bnx2_read_phy(bp, BCM5708S_UP1, &val);
1788 val |= BCM5708S_UP1_2G5;
1789 bnx2_write_phy(bp, BCM5708S_UP1, val);
1792 if ((CHIP_ID(bp) == CHIP_ID_5708_A0) ||
1793 (CHIP_ID(bp) == CHIP_ID_5708_B0) ||
1794 (CHIP_ID(bp) == CHIP_ID_5708_B1)) {
1795 /* increase tx signal amplitude */
1796 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
1797 BCM5708S_BLK_ADDR_TX_MISC);
1798 bnx2_read_phy(bp, BCM5708S_TX_ACTL1, &val);
1799 val &= ~BCM5708S_TX_ACTL1_DRIVER_VCM;
1800 bnx2_write_phy(bp, BCM5708S_TX_ACTL1, val);
1801 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
1804 val = REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_HW_CFG_CONFIG) &
1805 BNX2_PORT_HW_CFG_CFG_TXCTL3_MASK;
1810 is_backplane = REG_RD_IND(bp, bp->shmem_base +
1811 BNX2_SHARED_HW_CFG_CONFIG);
1812 if (is_backplane & BNX2_SHARED_HW_CFG_PHY_BACKPLANE) {
1813 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
1814 BCM5708S_BLK_ADDR_TX_MISC);
1815 bnx2_write_phy(bp, BCM5708S_TX_ACTL3, val);
1816 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
1817 BCM5708S_BLK_ADDR_DIG);
1824 bnx2_init_5706s_phy(struct bnx2 *bp)
1828 bp->phy_flags &= ~PHY_PARALLEL_DETECT_FLAG;
1830 if (CHIP_NUM(bp) == CHIP_NUM_5706)
1831 REG_WR(bp, BNX2_MISC_GP_HW_CTL0, 0x300);
1833 if (bp->dev->mtu > 1500) {
1836 /* Set extended packet length bit */
1837 bnx2_write_phy(bp, 0x18, 0x7);
1838 bnx2_read_phy(bp, 0x18, &val);
1839 bnx2_write_phy(bp, 0x18, (val & 0xfff8) | 0x4000);
1841 bnx2_write_phy(bp, 0x1c, 0x6c00);
1842 bnx2_read_phy(bp, 0x1c, &val);
1843 bnx2_write_phy(bp, 0x1c, (val & 0x3ff) | 0xec02);
1848 bnx2_write_phy(bp, 0x18, 0x7);
1849 bnx2_read_phy(bp, 0x18, &val);
1850 bnx2_write_phy(bp, 0x18, val & ~0x4007);
1852 bnx2_write_phy(bp, 0x1c, 0x6c00);
1853 bnx2_read_phy(bp, 0x1c, &val);
1854 bnx2_write_phy(bp, 0x1c, (val & 0x3fd) | 0xec00);
1861 bnx2_init_copper_phy(struct bnx2 *bp)
1867 if (bp->phy_flags & PHY_CRC_FIX_FLAG) {
1868 bnx2_write_phy(bp, 0x18, 0x0c00);
1869 bnx2_write_phy(bp, 0x17, 0x000a);
1870 bnx2_write_phy(bp, 0x15, 0x310b);
1871 bnx2_write_phy(bp, 0x17, 0x201f);
1872 bnx2_write_phy(bp, 0x15, 0x9506);
1873 bnx2_write_phy(bp, 0x17, 0x401f);
1874 bnx2_write_phy(bp, 0x15, 0x14e2);
1875 bnx2_write_phy(bp, 0x18, 0x0400);
1878 if (bp->phy_flags & PHY_DIS_EARLY_DAC_FLAG) {
1879 bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS,
1880 MII_BNX2_DSP_EXPAND_REG | 0x8);
1881 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &val);
1883 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val);
1886 if (bp->dev->mtu > 1500) {
1887 /* Set extended packet length bit */
1888 bnx2_write_phy(bp, 0x18, 0x7);
1889 bnx2_read_phy(bp, 0x18, &val);
1890 bnx2_write_phy(bp, 0x18, val | 0x4000);
1892 bnx2_read_phy(bp, 0x10, &val);
1893 bnx2_write_phy(bp, 0x10, val | 0x1);
1896 bnx2_write_phy(bp, 0x18, 0x7);
1897 bnx2_read_phy(bp, 0x18, &val);
1898 bnx2_write_phy(bp, 0x18, val & ~0x4007);
1900 bnx2_read_phy(bp, 0x10, &val);
1901 bnx2_write_phy(bp, 0x10, val & ~0x1);
1904 /* ethernet@wirespeed */
1905 bnx2_write_phy(bp, 0x18, 0x7007);
1906 bnx2_read_phy(bp, 0x18, &val);
1907 bnx2_write_phy(bp, 0x18, val | (1 << 15) | (1 << 4));
1913 bnx2_init_phy(struct bnx2 *bp)
1918 bp->phy_flags &= ~PHY_INT_MODE_MASK_FLAG;
1919 bp->phy_flags |= PHY_INT_MODE_LINK_READY_FLAG;
1921 bp->mii_bmcr = MII_BMCR;
1922 bp->mii_bmsr = MII_BMSR;
1923 bp->mii_bmsr1 = MII_BMSR;
1924 bp->mii_adv = MII_ADVERTISE;
1925 bp->mii_lpa = MII_LPA;
1927 REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
1929 if (bp->phy_flags & REMOTE_PHY_CAP_FLAG)
1932 bnx2_read_phy(bp, MII_PHYSID1, &val);
1933 bp->phy_id = val << 16;
1934 bnx2_read_phy(bp, MII_PHYSID2, &val);
1935 bp->phy_id |= val & 0xffff;
1937 if (bp->phy_flags & PHY_SERDES_FLAG) {
1938 if (CHIP_NUM(bp) == CHIP_NUM_5706)
1939 rc = bnx2_init_5706s_phy(bp);
1940 else if (CHIP_NUM(bp) == CHIP_NUM_5708)
1941 rc = bnx2_init_5708s_phy(bp);
1942 else if (CHIP_NUM(bp) == CHIP_NUM_5709)
1943 rc = bnx2_init_5709s_phy(bp);
1946 rc = bnx2_init_copper_phy(bp);
1951 rc = bnx2_setup_phy(bp, bp->phy_port);
1957 bnx2_set_mac_loopback(struct bnx2 *bp)
1961 mac_mode = REG_RD(bp, BNX2_EMAC_MODE);
1962 mac_mode &= ~BNX2_EMAC_MODE_PORT;
1963 mac_mode |= BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK;
1964 REG_WR(bp, BNX2_EMAC_MODE, mac_mode);
1969 static int bnx2_test_link(struct bnx2 *);
1972 bnx2_set_phy_loopback(struct bnx2 *bp)
1977 spin_lock_bh(&bp->phy_lock);
1978 rc = bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK | BMCR_FULLDPLX |
1980 spin_unlock_bh(&bp->phy_lock);
1984 for (i = 0; i < 10; i++) {
1985 if (bnx2_test_link(bp) == 0)
1990 mac_mode = REG_RD(bp, BNX2_EMAC_MODE);
1991 mac_mode &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
1992 BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK |
1993 BNX2_EMAC_MODE_25G_MODE);
1995 mac_mode |= BNX2_EMAC_MODE_PORT_GMII;
1996 REG_WR(bp, BNX2_EMAC_MODE, mac_mode);
2002 bnx2_fw_sync(struct bnx2 *bp, u32 msg_data, int silent)
2008 msg_data |= bp->fw_wr_seq;
2010 REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_MB, msg_data);
2012 /* wait for an acknowledgement. */
2013 for (i = 0; i < (FW_ACK_TIME_OUT_MS / 10); i++) {
2016 val = REG_RD_IND(bp, bp->shmem_base + BNX2_FW_MB);
2018 if ((val & BNX2_FW_MSG_ACK) == (msg_data & BNX2_DRV_MSG_SEQ))
2021 if ((msg_data & BNX2_DRV_MSG_DATA) == BNX2_DRV_MSG_DATA_WAIT0)
2024 /* If we timed out, inform the firmware that this is the case. */
2025 if ((val & BNX2_FW_MSG_ACK) != (msg_data & BNX2_DRV_MSG_SEQ)) {
2027 printk(KERN_ERR PFX "fw sync timeout, reset code = "
2030 msg_data &= ~BNX2_DRV_MSG_CODE;
2031 msg_data |= BNX2_DRV_MSG_CODE_FW_TIMEOUT;
2033 REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_MB, msg_data);
2038 if ((val & BNX2_FW_MSG_STATUS_MASK) != BNX2_FW_MSG_STATUS_OK)
2045 bnx2_init_5709_context(struct bnx2 *bp)
2050 val = BNX2_CTX_COMMAND_ENABLED | BNX2_CTX_COMMAND_MEM_INIT | (1 << 12);
2051 val |= (BCM_PAGE_BITS - 8) << 16;
2052 REG_WR(bp, BNX2_CTX_COMMAND, val);
2053 for (i = 0; i < 10; i++) {
2054 val = REG_RD(bp, BNX2_CTX_COMMAND);
2055 if (!(val & BNX2_CTX_COMMAND_MEM_INIT))
2059 if (val & BNX2_CTX_COMMAND_MEM_INIT)
2062 for (i = 0; i < bp->ctx_pages; i++) {
2065 REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA0,
2066 (bp->ctx_blk_mapping[i] & 0xffffffff) |
2067 BNX2_CTX_HOST_PAGE_TBL_DATA0_VALID);
2068 REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA1,
2069 (u64) bp->ctx_blk_mapping[i] >> 32);
2070 REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL, i |
2071 BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ);
2072 for (j = 0; j < 10; j++) {
2074 val = REG_RD(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL);
2075 if (!(val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ))
2079 if (val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) {
2088 bnx2_init_context(struct bnx2 *bp)
2094 u32 vcid_addr, pcid_addr, offset;
2099 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
2102 vcid_addr = GET_PCID_ADDR(vcid);
2104 new_vcid = 0x60 + (vcid & 0xf0) + (vcid & 0x7);
2109 pcid_addr = GET_PCID_ADDR(new_vcid);
2112 vcid_addr = GET_CID_ADDR(vcid);
2113 pcid_addr = vcid_addr;
2116 for (i = 0; i < (CTX_SIZE / PHY_CTX_SIZE); i++) {
2117 vcid_addr += (i << PHY_CTX_SHIFT);
2118 pcid_addr += (i << PHY_CTX_SHIFT);
2120 REG_WR(bp, BNX2_CTX_VIRT_ADDR, vcid_addr);
2121 REG_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr);
2123 /* Zero out the context. */
2124 for (offset = 0; offset < PHY_CTX_SIZE; offset += 4)
2125 CTX_WR(bp, vcid_addr, offset, 0);
2131 bnx2_alloc_bad_rbuf(struct bnx2 *bp)
2137 good_mbuf = kmalloc(512 * sizeof(u16), GFP_KERNEL);
2138 if (good_mbuf == NULL) {
2139 printk(KERN_ERR PFX "Failed to allocate memory in "
2140 "bnx2_alloc_bad_rbuf\n");
2144 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
2145 BNX2_MISC_ENABLE_SET_BITS_RX_MBUF_ENABLE);
2149 /* Allocate a bunch of mbufs and save the good ones in an array. */
2150 val = REG_RD_IND(bp, BNX2_RBUF_STATUS1);
2151 while (val & BNX2_RBUF_STATUS1_FREE_COUNT) {
2152 REG_WR_IND(bp, BNX2_RBUF_COMMAND, BNX2_RBUF_COMMAND_ALLOC_REQ);
2154 val = REG_RD_IND(bp, BNX2_RBUF_FW_BUF_ALLOC);
2156 val &= BNX2_RBUF_FW_BUF_ALLOC_VALUE;
2158 /* The addresses with Bit 9 set are bad memory blocks. */
2159 if (!(val & (1 << 9))) {
2160 good_mbuf[good_mbuf_cnt] = (u16) val;
2164 val = REG_RD_IND(bp, BNX2_RBUF_STATUS1);
2167 /* Free the good ones back to the mbuf pool thus discarding
2168 * all the bad ones. */
2169 while (good_mbuf_cnt) {
2172 val = good_mbuf[good_mbuf_cnt];
2173 val = (val << 9) | val | 1;
2175 REG_WR_IND(bp, BNX2_RBUF_FW_BUF_FREE, val);
2182 bnx2_set_mac_addr(struct bnx2 *bp)
2185 u8 *mac_addr = bp->dev->dev_addr;
2187 val = (mac_addr[0] << 8) | mac_addr[1];
2189 REG_WR(bp, BNX2_EMAC_MAC_MATCH0, val);
2191 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
2192 (mac_addr[4] << 8) | mac_addr[5];
2194 REG_WR(bp, BNX2_EMAC_MAC_MATCH1, val);
2198 bnx2_alloc_rx_skb(struct bnx2 *bp, u16 index)
2200 struct sk_buff *skb;
2201 struct sw_bd *rx_buf = &bp->rx_buf_ring[index];
2203 struct rx_bd *rxbd = &bp->rx_desc_ring[RX_RING(index)][RX_IDX(index)];
2204 unsigned long align;
2206 skb = netdev_alloc_skb(bp->dev, bp->rx_buf_size);
2211 if (unlikely((align = (unsigned long) skb->data & (BNX2_RX_ALIGN - 1))))
2212 skb_reserve(skb, BNX2_RX_ALIGN - align);
2214 mapping = pci_map_single(bp->pdev, skb->data, bp->rx_buf_use_size,
2215 PCI_DMA_FROMDEVICE);
2218 pci_unmap_addr_set(rx_buf, mapping, mapping);
2220 rxbd->rx_bd_haddr_hi = (u64) mapping >> 32;
2221 rxbd->rx_bd_haddr_lo = (u64) mapping & 0xffffffff;
2223 bp->rx_prod_bseq += bp->rx_buf_use_size;
2229 bnx2_phy_event_is_set(struct bnx2 *bp, u32 event)
2231 struct status_block *sblk = bp->status_blk;
2232 u32 new_link_state, old_link_state;
2235 new_link_state = sblk->status_attn_bits & event;
2236 old_link_state = sblk->status_attn_bits_ack & event;
2237 if (new_link_state != old_link_state) {
2239 REG_WR(bp, BNX2_PCICFG_STATUS_BIT_SET_CMD, event);
2241 REG_WR(bp, BNX2_PCICFG_STATUS_BIT_CLEAR_CMD, event);
2249 bnx2_phy_int(struct bnx2 *bp)
2251 if (bnx2_phy_event_is_set(bp, STATUS_ATTN_BITS_LINK_STATE)) {
2252 spin_lock(&bp->phy_lock);
2254 spin_unlock(&bp->phy_lock);
2256 if (bnx2_phy_event_is_set(bp, STATUS_ATTN_BITS_TIMER_ABORT))
2257 bnx2_set_remote_link(bp);
2262 bnx2_tx_int(struct bnx2 *bp)
2264 struct status_block *sblk = bp->status_blk;
2265 u16 hw_cons, sw_cons, sw_ring_cons;
2268 hw_cons = bp->hw_tx_cons = sblk->status_tx_quick_consumer_index0;
2269 if ((hw_cons & MAX_TX_DESC_CNT) == MAX_TX_DESC_CNT) {
2272 sw_cons = bp->tx_cons;
2274 while (sw_cons != hw_cons) {
2275 struct sw_bd *tx_buf;
2276 struct sk_buff *skb;
2279 sw_ring_cons = TX_RING_IDX(sw_cons);
2281 tx_buf = &bp->tx_buf_ring[sw_ring_cons];
2284 /* partial BD completions possible with TSO packets */
2285 if (skb_is_gso(skb)) {
2286 u16 last_idx, last_ring_idx;
2288 last_idx = sw_cons +
2289 skb_shinfo(skb)->nr_frags + 1;
2290 last_ring_idx = sw_ring_cons +
2291 skb_shinfo(skb)->nr_frags + 1;
2292 if (unlikely(last_ring_idx >= MAX_TX_DESC_CNT)) {
2295 if (((s16) ((s16) last_idx - (s16) hw_cons)) > 0) {
2300 pci_unmap_single(bp->pdev, pci_unmap_addr(tx_buf, mapping),
2301 skb_headlen(skb), PCI_DMA_TODEVICE);
2304 last = skb_shinfo(skb)->nr_frags;
2306 for (i = 0; i < last; i++) {
2307 sw_cons = NEXT_TX_BD(sw_cons);
2309 pci_unmap_page(bp->pdev,
2311 &bp->tx_buf_ring[TX_RING_IDX(sw_cons)],
2313 skb_shinfo(skb)->frags[i].size,
2317 sw_cons = NEXT_TX_BD(sw_cons);
2319 tx_free_bd += last + 1;
2323 hw_cons = bp->hw_tx_cons =
2324 sblk->status_tx_quick_consumer_index0;
2326 if ((hw_cons & MAX_TX_DESC_CNT) == MAX_TX_DESC_CNT) {
2331 bp->tx_cons = sw_cons;
2332 /* Need to make the tx_cons update visible to bnx2_start_xmit()
2333 * before checking for netif_queue_stopped(). Without the
2334 * memory barrier, there is a small possibility that bnx2_start_xmit()
2335 * will miss it and cause the queue to be stopped forever.
2339 if (unlikely(netif_queue_stopped(bp->dev)) &&
2340 (bnx2_tx_avail(bp) > bp->tx_wake_thresh)) {
2341 netif_tx_lock(bp->dev);
2342 if ((netif_queue_stopped(bp->dev)) &&
2343 (bnx2_tx_avail(bp) > bp->tx_wake_thresh))
2344 netif_wake_queue(bp->dev);
2345 netif_tx_unlock(bp->dev);
2350 bnx2_reuse_rx_skb(struct bnx2 *bp, struct sk_buff *skb,
2353 struct sw_bd *cons_rx_buf, *prod_rx_buf;
2354 struct rx_bd *cons_bd, *prod_bd;
2356 cons_rx_buf = &bp->rx_buf_ring[cons];
2357 prod_rx_buf = &bp->rx_buf_ring[prod];
2359 pci_dma_sync_single_for_device(bp->pdev,
2360 pci_unmap_addr(cons_rx_buf, mapping),
2361 bp->rx_offset + RX_COPY_THRESH, PCI_DMA_FROMDEVICE);
2363 bp->rx_prod_bseq += bp->rx_buf_use_size;
2365 prod_rx_buf->skb = skb;
2370 pci_unmap_addr_set(prod_rx_buf, mapping,
2371 pci_unmap_addr(cons_rx_buf, mapping));
2373 cons_bd = &bp->rx_desc_ring[RX_RING(cons)][RX_IDX(cons)];
2374 prod_bd = &bp->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
2375 prod_bd->rx_bd_haddr_hi = cons_bd->rx_bd_haddr_hi;
2376 prod_bd->rx_bd_haddr_lo = cons_bd->rx_bd_haddr_lo;
2380 bnx2_rx_skb(struct bnx2 *bp, struct sk_buff *skb, unsigned int len,
2381 dma_addr_t dma_addr, u32 ring_idx)
2384 u16 prod = ring_idx & 0xffff;
2386 err = bnx2_alloc_rx_skb(bp, prod);
2387 if (unlikely(err)) {
2388 bnx2_reuse_rx_skb(bp, skb, (u16) (ring_idx >> 16), prod);
2392 skb_reserve(skb, bp->rx_offset);
2393 pci_unmap_single(bp->pdev, dma_addr, bp->rx_buf_use_size,
2394 PCI_DMA_FROMDEVICE);
2401 bnx2_get_hw_rx_cons(struct bnx2 *bp)
2403 u16 cons = bp->status_blk->status_rx_quick_consumer_index0;
2405 if (unlikely((cons & MAX_RX_DESC_CNT) == MAX_RX_DESC_CNT))
2411 bnx2_rx_int(struct bnx2 *bp, int budget)
2413 u16 hw_cons, sw_cons, sw_ring_cons, sw_prod, sw_ring_prod;
2414 struct l2_fhdr *rx_hdr;
2417 hw_cons = bnx2_get_hw_rx_cons(bp);
2418 sw_cons = bp->rx_cons;
2419 sw_prod = bp->rx_prod;
2421 /* Memory barrier necessary as speculative reads of the rx
2422 * buffer can be ahead of the index in the status block
2425 while (sw_cons != hw_cons) {
2428 struct sw_bd *rx_buf;
2429 struct sk_buff *skb;
2430 dma_addr_t dma_addr;
2432 sw_ring_cons = RX_RING_IDX(sw_cons);
2433 sw_ring_prod = RX_RING_IDX(sw_prod);
2435 rx_buf = &bp->rx_buf_ring[sw_ring_cons];
2440 dma_addr = pci_unmap_addr(rx_buf, mapping);
2442 pci_dma_sync_single_for_cpu(bp->pdev, dma_addr,
2443 bp->rx_offset + RX_COPY_THRESH, PCI_DMA_FROMDEVICE);
2445 rx_hdr = (struct l2_fhdr *) skb->data;
2446 len = rx_hdr->l2_fhdr_pkt_len - 4;
2448 if ((status = rx_hdr->l2_fhdr_status) &
2449 (L2_FHDR_ERRORS_BAD_CRC |
2450 L2_FHDR_ERRORS_PHY_DECODE |
2451 L2_FHDR_ERRORS_ALIGNMENT |
2452 L2_FHDR_ERRORS_TOO_SHORT |
2453 L2_FHDR_ERRORS_GIANT_FRAME)) {
2455 bnx2_reuse_rx_skb(bp, skb, sw_ring_cons, sw_ring_prod);
2459 if (len <= bp->rx_copy_thresh) {
2460 struct sk_buff *new_skb;
2462 new_skb = netdev_alloc_skb(bp->dev, len + 2);
2463 if (new_skb == NULL) {
2464 bnx2_reuse_rx_skb(bp, skb, sw_ring_cons,
2470 skb_copy_from_linear_data_offset(skb, bp->rx_offset - 2,
2471 new_skb->data, len + 2);
2472 skb_reserve(new_skb, 2);
2473 skb_put(new_skb, len);
2475 bnx2_reuse_rx_skb(bp, skb,
2476 sw_ring_cons, sw_ring_prod);
2479 } else if (unlikely(bnx2_rx_skb(bp, skb, len, dma_addr,
2480 (sw_ring_cons << 16) | sw_ring_prod)))
2483 skb->protocol = eth_type_trans(skb, bp->dev);
2485 if ((len > (bp->dev->mtu + ETH_HLEN)) &&
2486 (ntohs(skb->protocol) != 0x8100)) {
2493 skb->ip_summed = CHECKSUM_NONE;
2495 (status & (L2_FHDR_STATUS_TCP_SEGMENT |
2496 L2_FHDR_STATUS_UDP_DATAGRAM))) {
2498 if (likely((status & (L2_FHDR_ERRORS_TCP_XSUM |
2499 L2_FHDR_ERRORS_UDP_XSUM)) == 0))
2500 skb->ip_summed = CHECKSUM_UNNECESSARY;
2504 if ((status & L2_FHDR_STATUS_L2_VLAN_TAG) && (bp->vlgrp != 0)) {
2505 vlan_hwaccel_receive_skb(skb, bp->vlgrp,
2506 rx_hdr->l2_fhdr_vlan_tag);
2510 netif_receive_skb(skb);
2512 bp->dev->last_rx = jiffies;
2516 sw_cons = NEXT_RX_BD(sw_cons);
2517 sw_prod = NEXT_RX_BD(sw_prod);
2519 if ((rx_pkt == budget))
2522 /* Refresh hw_cons to see if there is new work */
2523 if (sw_cons == hw_cons) {
2524 hw_cons = bnx2_get_hw_rx_cons(bp);
2528 bp->rx_cons = sw_cons;
2529 bp->rx_prod = sw_prod;
2531 REG_WR16(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BDIDX, sw_prod);
2533 REG_WR(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BSEQ, bp->rx_prod_bseq);
2541 /* MSI ISR - The only difference between this and the INTx ISR
2542 * is that the MSI interrupt is always serviced.
2545 bnx2_msi(int irq, void *dev_instance)
2547 struct net_device *dev = dev_instance;
2548 struct bnx2 *bp = netdev_priv(dev);
2550 prefetch(bp->status_blk);
2551 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
2552 BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
2553 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
2555 /* Return here if interrupt is disabled. */
2556 if (unlikely(atomic_read(&bp->intr_sem) != 0))
2559 netif_rx_schedule(dev, &bp->napi);
2565 bnx2_msi_1shot(int irq, void *dev_instance)
2567 struct net_device *dev = dev_instance;
2568 struct bnx2 *bp = netdev_priv(dev);
2570 prefetch(bp->status_blk);
2572 /* Return here if interrupt is disabled. */
2573 if (unlikely(atomic_read(&bp->intr_sem) != 0))
2576 netif_rx_schedule(dev, &bp->napi);
2582 bnx2_interrupt(int irq, void *dev_instance)
2584 struct net_device *dev = dev_instance;
2585 struct bnx2 *bp = netdev_priv(dev);
2586 struct status_block *sblk = bp->status_blk;
2588 /* When using INTx, it is possible for the interrupt to arrive
2589 * at the CPU before the status block posted prior to the
2590 * interrupt. Reading a register will flush the status block.
2591 * When using MSI, the MSI message will always complete after
2592 * the status block write.
2594 if ((sblk->status_idx == bp->last_status_idx) &&
2595 (REG_RD(bp, BNX2_PCICFG_MISC_STATUS) &
2596 BNX2_PCICFG_MISC_STATUS_INTA_VALUE))
2599 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
2600 BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
2601 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
2603 /* Read back to deassert IRQ immediately to avoid too many
2604 * spurious interrupts.
2606 REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD);
2608 /* Return here if interrupt is shared and is disabled. */
2609 if (unlikely(atomic_read(&bp->intr_sem) != 0))
2612 if (netif_rx_schedule_prep(dev, &bp->napi)) {
2613 bp->last_status_idx = sblk->status_idx;
2614 __netif_rx_schedule(dev, &bp->napi);
2620 #define STATUS_ATTN_EVENTS (STATUS_ATTN_BITS_LINK_STATE | \
2621 STATUS_ATTN_BITS_TIMER_ABORT)
2624 bnx2_has_work(struct bnx2 *bp)
2626 struct status_block *sblk = bp->status_blk;
2628 if ((bnx2_get_hw_rx_cons(bp) != bp->rx_cons) ||
2629 (sblk->status_tx_quick_consumer_index0 != bp->hw_tx_cons))
2632 if ((sblk->status_attn_bits & STATUS_ATTN_EVENTS) !=
2633 (sblk->status_attn_bits_ack & STATUS_ATTN_EVENTS))
2639 static int bnx2_poll_work(struct bnx2 *bp, int work_done, int budget)
2641 struct status_block *sblk = bp->status_blk;
2642 u32 status_attn_bits = sblk->status_attn_bits;
2643 u32 status_attn_bits_ack = sblk->status_attn_bits_ack;
2645 if ((status_attn_bits & STATUS_ATTN_EVENTS) !=
2646 (status_attn_bits_ack & STATUS_ATTN_EVENTS)) {
2650 /* This is needed to take care of transient status
2651 * during link changes.
2653 REG_WR(bp, BNX2_HC_COMMAND,
2654 bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
2655 REG_RD(bp, BNX2_HC_COMMAND);
2658 if (sblk->status_tx_quick_consumer_index0 != bp->hw_tx_cons)
2661 if (bnx2_get_hw_rx_cons(bp) != bp->rx_cons)
2662 work_done += bnx2_rx_int(bp, budget - work_done);
2667 static int bnx2_poll(struct napi_struct *napi, int budget)
2669 struct bnx2 *bp = container_of(napi, struct bnx2, napi);
2671 struct status_block *sblk = bp->status_blk;
2674 work_done = bnx2_poll_work(bp, work_done, budget);
2676 if (unlikely(work_done >= budget))
2679 /* bp->last_status_idx is used below to tell the hw how
2680 * much work has been processed, so we must read it before
2681 * checking for more work.
2683 bp->last_status_idx = sblk->status_idx;
2685 if (likely(!bnx2_has_work(bp))) {
2686 netif_rx_complete(bp->dev, napi);
2687 if (likely(bp->flags & USING_MSI_FLAG)) {
2688 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
2689 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
2690 bp->last_status_idx);
2693 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
2694 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
2695 BNX2_PCICFG_INT_ACK_CMD_MASK_INT |
2696 bp->last_status_idx);
2698 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
2699 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
2700 bp->last_status_idx);
2708 /* Called with rtnl_lock from vlan functions and also netif_tx_lock
2709 * from set_multicast.
2712 bnx2_set_rx_mode(struct net_device *dev)
2714 struct bnx2 *bp = netdev_priv(dev);
2715 u32 rx_mode, sort_mode;
2718 spin_lock_bh(&bp->phy_lock);
2720 rx_mode = bp->rx_mode & ~(BNX2_EMAC_RX_MODE_PROMISCUOUS |
2721 BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG);
2722 sort_mode = 1 | BNX2_RPM_SORT_USER0_BC_EN;
2724 if (!bp->vlgrp && !(bp->flags & ASF_ENABLE_FLAG))
2725 rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
2727 if (!(bp->flags & ASF_ENABLE_FLAG))
2728 rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
2730 if (dev->flags & IFF_PROMISC) {
2731 /* Promiscuous mode. */
2732 rx_mode |= BNX2_EMAC_RX_MODE_PROMISCUOUS;
2733 sort_mode |= BNX2_RPM_SORT_USER0_PROM_EN |
2734 BNX2_RPM_SORT_USER0_PROM_VLAN;
2736 else if (dev->flags & IFF_ALLMULTI) {
2737 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
2738 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
2741 sort_mode |= BNX2_RPM_SORT_USER0_MC_EN;
2744 /* Accept one or more multicast(s). */
2745 struct dev_mc_list *mclist;
2746 u32 mc_filter[NUM_MC_HASH_REGISTERS];
2751 memset(mc_filter, 0, 4 * NUM_MC_HASH_REGISTERS);
2753 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
2754 i++, mclist = mclist->next) {
2756 crc = ether_crc_le(ETH_ALEN, mclist->dmi_addr);
2758 regidx = (bit & 0xe0) >> 5;
2760 mc_filter[regidx] |= (1 << bit);
2763 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
2764 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
2768 sort_mode |= BNX2_RPM_SORT_USER0_MC_HSH_EN;
2771 if (rx_mode != bp->rx_mode) {
2772 bp->rx_mode = rx_mode;
2773 REG_WR(bp, BNX2_EMAC_RX_MODE, rx_mode);
2776 REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
2777 REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode);
2778 REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode | BNX2_RPM_SORT_USER0_ENA);
2780 spin_unlock_bh(&bp->phy_lock);
2784 load_rv2p_fw(struct bnx2 *bp, u32 *rv2p_code, u32 rv2p_code_len,
2791 for (i = 0; i < rv2p_code_len; i += 8) {
2792 REG_WR(bp, BNX2_RV2P_INSTR_HIGH, cpu_to_le32(*rv2p_code));
2794 REG_WR(bp, BNX2_RV2P_INSTR_LOW, cpu_to_le32(*rv2p_code));
2797 if (rv2p_proc == RV2P_PROC1) {
2798 val = (i / 8) | BNX2_RV2P_PROC1_ADDR_CMD_RDWR;
2799 REG_WR(bp, BNX2_RV2P_PROC1_ADDR_CMD, val);
2802 val = (i / 8) | BNX2_RV2P_PROC2_ADDR_CMD_RDWR;
2803 REG_WR(bp, BNX2_RV2P_PROC2_ADDR_CMD, val);
2807 /* Reset the processor, un-stall is done later. */
2808 if (rv2p_proc == RV2P_PROC1) {
2809 REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC1_RESET);
2812 REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC2_RESET);
2817 load_cpu_fw(struct bnx2 *bp, struct cpu_reg *cpu_reg, struct fw_info *fw)
2824 val = REG_RD_IND(bp, cpu_reg->mode);
2825 val |= cpu_reg->mode_value_halt;
2826 REG_WR_IND(bp, cpu_reg->mode, val);
2827 REG_WR_IND(bp, cpu_reg->state, cpu_reg->state_value_clear);
2829 /* Load the Text area. */
2830 offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base);
2834 rc = zlib_inflate_blob(fw->text, FW_BUF_SIZE, fw->gz_text,
2839 for (j = 0; j < (fw->text_len / 4); j++, offset += 4) {
2840 REG_WR_IND(bp, offset, cpu_to_le32(fw->text[j]));
2844 /* Load the Data area. */
2845 offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base);
2849 for (j = 0; j < (fw->data_len / 4); j++, offset += 4) {
2850 REG_WR_IND(bp, offset, fw->data[j]);
2854 /* Load the SBSS area. */
2855 offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base);
2859 for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4) {
2860 REG_WR_IND(bp, offset, 0);
2864 /* Load the BSS area. */
2865 offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base);
2869 for (j = 0; j < (fw->bss_len/4); j++, offset += 4) {
2870 REG_WR_IND(bp, offset, 0);
2874 /* Load the Read-Only area. */
2875 offset = cpu_reg->spad_base +
2876 (fw->rodata_addr - cpu_reg->mips_view_base);
2880 for (j = 0; j < (fw->rodata_len / 4); j++, offset += 4) {
2881 REG_WR_IND(bp, offset, fw->rodata[j]);
2885 /* Clear the pre-fetch instruction. */
2886 REG_WR_IND(bp, cpu_reg->inst, 0);
2887 REG_WR_IND(bp, cpu_reg->pc, fw->start_addr);
2889 /* Start the CPU. */
2890 val = REG_RD_IND(bp, cpu_reg->mode);
2891 val &= ~cpu_reg->mode_value_halt;
2892 REG_WR_IND(bp, cpu_reg->state, cpu_reg->state_value_clear);
2893 REG_WR_IND(bp, cpu_reg->mode, val);
2899 bnx2_init_cpus(struct bnx2 *bp)
2901 struct cpu_reg cpu_reg;
2906 /* Initialize the RV2P processor. */
2907 text = vmalloc(FW_BUF_SIZE);
2910 rc = zlib_inflate_blob(text, FW_BUF_SIZE, bnx2_rv2p_proc1, sizeof(bnx2_rv2p_proc1));
2914 load_rv2p_fw(bp, text, rc /* == len */, RV2P_PROC1);
2916 rc = zlib_inflate_blob(text, FW_BUF_SIZE, bnx2_rv2p_proc2, sizeof(bnx2_rv2p_proc2));
2920 load_rv2p_fw(bp, text, rc /* == len */, RV2P_PROC2);
2922 /* Initialize the RX Processor. */
2923 cpu_reg.mode = BNX2_RXP_CPU_MODE;
2924 cpu_reg.mode_value_halt = BNX2_RXP_CPU_MODE_SOFT_HALT;
2925 cpu_reg.mode_value_sstep = BNX2_RXP_CPU_MODE_STEP_ENA;
2926 cpu_reg.state = BNX2_RXP_CPU_STATE;
2927 cpu_reg.state_value_clear = 0xffffff;
2928 cpu_reg.gpr0 = BNX2_RXP_CPU_REG_FILE;
2929 cpu_reg.evmask = BNX2_RXP_CPU_EVENT_MASK;
2930 cpu_reg.pc = BNX2_RXP_CPU_PROGRAM_COUNTER;
2931 cpu_reg.inst = BNX2_RXP_CPU_INSTRUCTION;
2932 cpu_reg.bp = BNX2_RXP_CPU_HW_BREAKPOINT;
2933 cpu_reg.spad_base = BNX2_RXP_SCRATCH;
2934 cpu_reg.mips_view_base = 0x8000000;
2936 if (CHIP_NUM(bp) == CHIP_NUM_5709)
2937 fw = &bnx2_rxp_fw_09;
2939 fw = &bnx2_rxp_fw_06;
2942 rc = load_cpu_fw(bp, &cpu_reg, fw);
2946 /* Initialize the TX Processor. */
2947 cpu_reg.mode = BNX2_TXP_CPU_MODE;
2948 cpu_reg.mode_value_halt = BNX2_TXP_CPU_MODE_SOFT_HALT;
2949 cpu_reg.mode_value_sstep = BNX2_TXP_CPU_MODE_STEP_ENA;
2950 cpu_reg.state = BNX2_TXP_CPU_STATE;
2951 cpu_reg.state_value_clear = 0xffffff;
2952 cpu_reg.gpr0 = BNX2_TXP_CPU_REG_FILE;
2953 cpu_reg.evmask = BNX2_TXP_CPU_EVENT_MASK;
2954 cpu_reg.pc = BNX2_TXP_CPU_PROGRAM_COUNTER;
2955 cpu_reg.inst = BNX2_TXP_CPU_INSTRUCTION;
2956 cpu_reg.bp = BNX2_TXP_CPU_HW_BREAKPOINT;
2957 cpu_reg.spad_base = BNX2_TXP_SCRATCH;
2958 cpu_reg.mips_view_base = 0x8000000;
2960 if (CHIP_NUM(bp) == CHIP_NUM_5709)
2961 fw = &bnx2_txp_fw_09;
2963 fw = &bnx2_txp_fw_06;
2966 rc = load_cpu_fw(bp, &cpu_reg, fw);
2970 /* Initialize the TX Patch-up Processor. */
2971 cpu_reg.mode = BNX2_TPAT_CPU_MODE;
2972 cpu_reg.mode_value_halt = BNX2_TPAT_CPU_MODE_SOFT_HALT;
2973 cpu_reg.mode_value_sstep = BNX2_TPAT_CPU_MODE_STEP_ENA;
2974 cpu_reg.state = BNX2_TPAT_CPU_STATE;
2975 cpu_reg.state_value_clear = 0xffffff;
2976 cpu_reg.gpr0 = BNX2_TPAT_CPU_REG_FILE;
2977 cpu_reg.evmask = BNX2_TPAT_CPU_EVENT_MASK;
2978 cpu_reg.pc = BNX2_TPAT_CPU_PROGRAM_COUNTER;
2979 cpu_reg.inst = BNX2_TPAT_CPU_INSTRUCTION;
2980 cpu_reg.bp = BNX2_TPAT_CPU_HW_BREAKPOINT;
2981 cpu_reg.spad_base = BNX2_TPAT_SCRATCH;
2982 cpu_reg.mips_view_base = 0x8000000;
2984 if (CHIP_NUM(bp) == CHIP_NUM_5709)
2985 fw = &bnx2_tpat_fw_09;
2987 fw = &bnx2_tpat_fw_06;
2990 rc = load_cpu_fw(bp, &cpu_reg, fw);
2994 /* Initialize the Completion Processor. */
2995 cpu_reg.mode = BNX2_COM_CPU_MODE;
2996 cpu_reg.mode_value_halt = BNX2_COM_CPU_MODE_SOFT_HALT;
2997 cpu_reg.mode_value_sstep = BNX2_COM_CPU_MODE_STEP_ENA;
2998 cpu_reg.state = BNX2_COM_CPU_STATE;
2999 cpu_reg.state_value_clear = 0xffffff;
3000 cpu_reg.gpr0 = BNX2_COM_CPU_REG_FILE;
3001 cpu_reg.evmask = BNX2_COM_CPU_EVENT_MASK;
3002 cpu_reg.pc = BNX2_COM_CPU_PROGRAM_COUNTER;
3003 cpu_reg.inst = BNX2_COM_CPU_INSTRUCTION;
3004 cpu_reg.bp = BNX2_COM_CPU_HW_BREAKPOINT;
3005 cpu_reg.spad_base = BNX2_COM_SCRATCH;
3006 cpu_reg.mips_view_base = 0x8000000;
3008 if (CHIP_NUM(bp) == CHIP_NUM_5709)
3009 fw = &bnx2_com_fw_09;
3011 fw = &bnx2_com_fw_06;
3014 rc = load_cpu_fw(bp, &cpu_reg, fw);
3018 /* Initialize the Command Processor. */
3019 cpu_reg.mode = BNX2_CP_CPU_MODE;
3020 cpu_reg.mode_value_halt = BNX2_CP_CPU_MODE_SOFT_HALT;
3021 cpu_reg.mode_value_sstep = BNX2_CP_CPU_MODE_STEP_ENA;
3022 cpu_reg.state = BNX2_CP_CPU_STATE;
3023 cpu_reg.state_value_clear = 0xffffff;
3024 cpu_reg.gpr0 = BNX2_CP_CPU_REG_FILE;
3025 cpu_reg.evmask = BNX2_CP_CPU_EVENT_MASK;
3026 cpu_reg.pc = BNX2_CP_CPU_PROGRAM_COUNTER;
3027 cpu_reg.inst = BNX2_CP_CPU_INSTRUCTION;
3028 cpu_reg.bp = BNX2_CP_CPU_HW_BREAKPOINT;
3029 cpu_reg.spad_base = BNX2_CP_SCRATCH;
3030 cpu_reg.mips_view_base = 0x8000000;
3032 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
3033 fw = &bnx2_cp_fw_09;
3036 rc = load_cpu_fw(bp, &cpu_reg, fw);
3046 bnx2_set_power_state(struct bnx2 *bp, pci_power_t state)
3050 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &pmcsr);
3056 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
3057 (pmcsr & ~PCI_PM_CTRL_STATE_MASK) |
3058 PCI_PM_CTRL_PME_STATUS);
3060 if (pmcsr & PCI_PM_CTRL_STATE_MASK)
3061 /* delay required during transition out of D3hot */
3064 val = REG_RD(bp, BNX2_EMAC_MODE);
3065 val |= BNX2_EMAC_MODE_MPKT_RCVD | BNX2_EMAC_MODE_ACPI_RCVD;
3066 val &= ~BNX2_EMAC_MODE_MPKT;
3067 REG_WR(bp, BNX2_EMAC_MODE, val);
3069 val = REG_RD(bp, BNX2_RPM_CONFIG);
3070 val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
3071 REG_WR(bp, BNX2_RPM_CONFIG, val);
3082 autoneg = bp->autoneg;
3083 advertising = bp->advertising;
3085 if (bp->phy_port == PORT_TP) {
3086 bp->autoneg = AUTONEG_SPEED;
3087 bp->advertising = ADVERTISED_10baseT_Half |
3088 ADVERTISED_10baseT_Full |
3089 ADVERTISED_100baseT_Half |
3090 ADVERTISED_100baseT_Full |
3094 spin_lock_bh(&bp->phy_lock);
3095 bnx2_setup_phy(bp, bp->phy_port);
3096 spin_unlock_bh(&bp->phy_lock);
3098 bp->autoneg = autoneg;
3099 bp->advertising = advertising;
3101 bnx2_set_mac_addr(bp);
3103 val = REG_RD(bp, BNX2_EMAC_MODE);
3105 /* Enable port mode. */
3106 val &= ~BNX2_EMAC_MODE_PORT;
3107 val |= BNX2_EMAC_MODE_MPKT_RCVD |
3108 BNX2_EMAC_MODE_ACPI_RCVD |
3109 BNX2_EMAC_MODE_MPKT;
3110 if (bp->phy_port == PORT_TP)
3111 val |= BNX2_EMAC_MODE_PORT_MII;
3113 val |= BNX2_EMAC_MODE_PORT_GMII;
3114 if (bp->line_speed == SPEED_2500)
3115 val |= BNX2_EMAC_MODE_25G_MODE;
3118 REG_WR(bp, BNX2_EMAC_MODE, val);
3120 /* receive all multicast */
3121 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
3122 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
3125 REG_WR(bp, BNX2_EMAC_RX_MODE,
3126 BNX2_EMAC_RX_MODE_SORT_MODE);
3128 val = 1 | BNX2_RPM_SORT_USER0_BC_EN |
3129 BNX2_RPM_SORT_USER0_MC_EN;
3130 REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
3131 REG_WR(bp, BNX2_RPM_SORT_USER0, val);
3132 REG_WR(bp, BNX2_RPM_SORT_USER0, val |
3133 BNX2_RPM_SORT_USER0_ENA);
3135 /* Need to enable EMAC and RPM for WOL. */
3136 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
3137 BNX2_MISC_ENABLE_SET_BITS_RX_PARSER_MAC_ENABLE |
3138 BNX2_MISC_ENABLE_SET_BITS_TX_HEADER_Q_ENABLE |
3139 BNX2_MISC_ENABLE_SET_BITS_EMAC_ENABLE);
3141 val = REG_RD(bp, BNX2_RPM_CONFIG);
3142 val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
3143 REG_WR(bp, BNX2_RPM_CONFIG, val);
3145 wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
3148 wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
3151 if (!(bp->flags & NO_WOL_FLAG))
3152 bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT3 | wol_msg, 0);
3154 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
3155 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
3156 (CHIP_ID(bp) == CHIP_ID_5706_A1)) {
3165 pmcsr |= PCI_PM_CTRL_PME_ENABLE;
3167 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
3170 /* No more memory access after this point until
3171 * device is brought back to D0.
3183 bnx2_acquire_nvram_lock(struct bnx2 *bp)
3188 /* Request access to the flash interface. */
3189 REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_SET2);
3190 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3191 val = REG_RD(bp, BNX2_NVM_SW_ARB);
3192 if (val & BNX2_NVM_SW_ARB_ARB_ARB2)
3198 if (j >= NVRAM_TIMEOUT_COUNT)
3205 bnx2_release_nvram_lock(struct bnx2 *bp)
3210 /* Relinquish nvram interface. */
3211 REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_CLR2);
3213 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3214 val = REG_RD(bp, BNX2_NVM_SW_ARB);
3215 if (!(val & BNX2_NVM_SW_ARB_ARB_ARB2))
3221 if (j >= NVRAM_TIMEOUT_COUNT)
3229 bnx2_enable_nvram_write(struct bnx2 *bp)
3233 val = REG_RD(bp, BNX2_MISC_CFG);
3234 REG_WR(bp, BNX2_MISC_CFG, val | BNX2_MISC_CFG_NVM_WR_EN_PCI);
3236 if (bp->flash_info->flags & BNX2_NV_WREN) {
3239 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
3240 REG_WR(bp, BNX2_NVM_COMMAND,
3241 BNX2_NVM_COMMAND_WREN | BNX2_NVM_COMMAND_DOIT);
3243 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3246 val = REG_RD(bp, BNX2_NVM_COMMAND);
3247 if (val & BNX2_NVM_COMMAND_DONE)
3251 if (j >= NVRAM_TIMEOUT_COUNT)
3258 bnx2_disable_nvram_write(struct bnx2 *bp)
3262 val = REG_RD(bp, BNX2_MISC_CFG);
3263 REG_WR(bp, BNX2_MISC_CFG, val & ~BNX2_MISC_CFG_NVM_WR_EN);
3268 bnx2_enable_nvram_access(struct bnx2 *bp)
3272 val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
3273 /* Enable both bits, even on read. */
3274 REG_WR(bp, BNX2_NVM_ACCESS_ENABLE,
3275 val | BNX2_NVM_ACCESS_ENABLE_EN | BNX2_NVM_ACCESS_ENABLE_WR_EN);
3279 bnx2_disable_nvram_access(struct bnx2 *bp)
3283 val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
3284 /* Disable both bits, even after read. */
3285 REG_WR(bp, BNX2_NVM_ACCESS_ENABLE,
3286 val & ~(BNX2_NVM_ACCESS_ENABLE_EN |
3287 BNX2_NVM_ACCESS_ENABLE_WR_EN));
3291 bnx2_nvram_erase_page(struct bnx2 *bp, u32 offset)
3296 if (bp->flash_info->flags & BNX2_NV_BUFFERED)
3297 /* Buffered flash, no erase needed */
3300 /* Build an erase command */
3301 cmd = BNX2_NVM_COMMAND_ERASE | BNX2_NVM_COMMAND_WR |
3302 BNX2_NVM_COMMAND_DOIT;
3304 /* Need to clear DONE bit separately. */
3305 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
3307 /* Address of the NVRAM to read from. */
3308 REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
3310 /* Issue an erase command. */
3311 REG_WR(bp, BNX2_NVM_COMMAND, cmd);
3313 /* Wait for completion. */
3314 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3319 val = REG_RD(bp, BNX2_NVM_COMMAND);
3320 if (val & BNX2_NVM_COMMAND_DONE)
3324 if (j >= NVRAM_TIMEOUT_COUNT)
3331 bnx2_nvram_read_dword(struct bnx2 *bp, u32 offset, u8 *ret_val, u32 cmd_flags)
3336 /* Build the command word. */
3337 cmd = BNX2_NVM_COMMAND_DOIT | cmd_flags;
3339 /* Calculate an offset of a buffered flash, not needed for 5709. */
3340 if (bp->flash_info->flags & BNX2_NV_TRANSLATE) {
3341 offset = ((offset / bp->flash_info->page_size) <<
3342 bp->flash_info->page_bits) +
3343 (offset % bp->flash_info->page_size);
3346 /* Need to clear DONE bit separately. */
3347 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
3349 /* Address of the NVRAM to read from. */
3350 REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
3352 /* Issue a read command. */
3353 REG_WR(bp, BNX2_NVM_COMMAND, cmd);
3355 /* Wait for completion. */
3356 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3361 val = REG_RD(bp, BNX2_NVM_COMMAND);
3362 if (val & BNX2_NVM_COMMAND_DONE) {
3363 val = REG_RD(bp, BNX2_NVM_READ);
3365 val = be32_to_cpu(val);
3366 memcpy(ret_val, &val, 4);
3370 if (j >= NVRAM_TIMEOUT_COUNT)
3378 bnx2_nvram_write_dword(struct bnx2 *bp, u32 offset, u8 *val, u32 cmd_flags)
3383 /* Build the command word. */
3384 cmd = BNX2_NVM_COMMAND_DOIT | BNX2_NVM_COMMAND_WR | cmd_flags;
3386 /* Calculate an offset of a buffered flash, not needed for 5709. */
3387 if (bp->flash_info->flags & BNX2_NV_TRANSLATE) {
3388 offset = ((offset / bp->flash_info->page_size) <<
3389 bp->flash_info->page_bits) +
3390 (offset % bp->flash_info->page_size);
3393 /* Need to clear DONE bit separately. */
3394 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
3396 memcpy(&val32, val, 4);
3397 val32 = cpu_to_be32(val32);
3399 /* Write the data. */
3400 REG_WR(bp, BNX2_NVM_WRITE, val32);
3402 /* Address of the NVRAM to write to. */
3403 REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
3405 /* Issue the write command. */
3406 REG_WR(bp, BNX2_NVM_COMMAND, cmd);
3408 /* Wait for completion. */
3409 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3412 if (REG_RD(bp, BNX2_NVM_COMMAND) & BNX2_NVM_COMMAND_DONE)
3415 if (j >= NVRAM_TIMEOUT_COUNT)
3422 bnx2_init_nvram(struct bnx2 *bp)
3425 int j, entry_count, rc = 0;
3426 struct flash_spec *flash;
3428 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
3429 bp->flash_info = &flash_5709;
3430 goto get_flash_size;
3433 /* Determine the selected interface. */
3434 val = REG_RD(bp, BNX2_NVM_CFG1);
3436 entry_count = ARRAY_SIZE(flash_table);
3438 if (val & 0x40000000) {
3440 /* Flash interface has been reconfigured */
3441 for (j = 0, flash = &flash_table[0]; j < entry_count;
3443 if ((val & FLASH_BACKUP_STRAP_MASK) ==
3444 (flash->config1 & FLASH_BACKUP_STRAP_MASK)) {
3445 bp->flash_info = flash;
3452 /* Not yet been reconfigured */
3454 if (val & (1 << 23))
3455 mask = FLASH_BACKUP_STRAP_MASK;
3457 mask = FLASH_STRAP_MASK;
3459 for (j = 0, flash = &flash_table[0]; j < entry_count;
3462 if ((val & mask) == (flash->strapping & mask)) {
3463 bp->flash_info = flash;
3465 /* Request access to the flash interface. */
3466 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
3469 /* Enable access to flash interface */
3470 bnx2_enable_nvram_access(bp);
3472 /* Reconfigure the flash interface */
3473 REG_WR(bp, BNX2_NVM_CFG1, flash->config1);
3474 REG_WR(bp, BNX2_NVM_CFG2, flash->config2);
3475 REG_WR(bp, BNX2_NVM_CFG3, flash->config3);
3476 REG_WR(bp, BNX2_NVM_WRITE1, flash->write1);
3478 /* Disable access to flash interface */
3479 bnx2_disable_nvram_access(bp);
3480 bnx2_release_nvram_lock(bp);
3485 } /* if (val & 0x40000000) */
3487 if (j == entry_count) {
3488 bp->flash_info = NULL;
3489 printk(KERN_ALERT PFX "Unknown flash/EEPROM type.\n");
3494 val = REG_RD_IND(bp, bp->shmem_base + BNX2_SHARED_HW_CFG_CONFIG2);
3495 val &= BNX2_SHARED_HW_CFG2_NVM_SIZE_MASK;
3497 bp->flash_size = val;
3499 bp->flash_size = bp->flash_info->total_size;
3505 bnx2_nvram_read(struct bnx2 *bp, u32 offset, u8 *ret_buf,
3509 u32 cmd_flags, offset32, len32, extra;
3514 /* Request access to the flash interface. */
3515 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
3518 /* Enable access to flash interface */
3519 bnx2_enable_nvram_access(bp);
3532 pre_len = 4 - (offset & 3);
3534 if (pre_len >= len32) {
3536 cmd_flags = BNX2_NVM_COMMAND_FIRST |
3537 BNX2_NVM_COMMAND_LAST;
3540 cmd_flags = BNX2_NVM_COMMAND_FIRST;
3543 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
3548 memcpy(ret_buf, buf + (offset & 3), pre_len);
3555 extra = 4 - (len32 & 3);
3556 len32 = (len32 + 4) & ~3;
3563 cmd_flags = BNX2_NVM_COMMAND_LAST;
3565 cmd_flags = BNX2_NVM_COMMAND_FIRST |
3566 BNX2_NVM_COMMAND_LAST;
3568 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
3570 memcpy(ret_buf, buf, 4 - extra);
3572 else if (len32 > 0) {
3575 /* Read the first word. */
3579 cmd_flags = BNX2_NVM_COMMAND_FIRST;
3581 rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, cmd_flags);
3583 /* Advance to the next dword. */
3588 while (len32 > 4 && rc == 0) {
3589 rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, 0);
3591 /* Advance to the next dword. */
3600 cmd_flags = BNX2_NVM_COMMAND_LAST;
3601 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
3603 memcpy(ret_buf, buf, 4 - extra);
3606 /* Disable access to flash interface */
3607 bnx2_disable_nvram_access(bp);
3609 bnx2_release_nvram_lock(bp);
3615 bnx2_nvram_write(struct bnx2 *bp, u32 offset, u8 *data_buf,
3618 u32 written, offset32, len32;
3619 u8 *buf, start[4], end[4], *align_buf = NULL, *flash_buffer = NULL;
3621 int align_start, align_end;
3626 align_start = align_end = 0;
3628 if ((align_start = (offset32 & 3))) {
3630 len32 += align_start;
3633 if ((rc = bnx2_nvram_read(bp, offset32, start, 4)))
3638 align_end = 4 - (len32 & 3);
3640 if ((rc = bnx2_nvram_read(bp, offset32 + len32 - 4, end, 4)))
3644 if (align_start || align_end) {
3645 align_buf = kmalloc(len32, GFP_KERNEL);
3646 if (align_buf == NULL)
3649 memcpy(align_buf, start, 4);
3652 memcpy(align_buf + len32 - 4, end, 4);
3654 memcpy(align_buf + align_start, data_buf, buf_size);
3658 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
3659 flash_buffer = kmalloc(264, GFP_KERNEL);
3660 if (flash_buffer == NULL) {
3662 goto nvram_write_end;
3667 while ((written < len32) && (rc == 0)) {
3668 u32 page_start, page_end, data_start, data_end;
3669 u32 addr, cmd_flags;
3672 /* Find the page_start addr */
3673 page_start = offset32 + written;
3674 page_start -= (page_start % bp->flash_info->page_size);
3675 /* Find the page_end addr */
3676 page_end = page_start + bp->flash_info->page_size;
3677 /* Find the data_start addr */
3678 data_start = (written == 0) ? offset32 : page_start;
3679 /* Find the data_end addr */
3680 data_end = (page_end > offset32 + len32) ?
3681 (offset32 + len32) : page_end;
3683 /* Request access to the flash interface. */
3684 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
3685 goto nvram_write_end;
3687 /* Enable access to flash interface */
3688 bnx2_enable_nvram_access(bp);
3690 cmd_flags = BNX2_NVM_COMMAND_FIRST;
3691 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
3694 /* Read the whole page into the buffer
3695 * (non-buffer flash only) */
3696 for (j = 0; j < bp->flash_info->page_size; j += 4) {
3697 if (j == (bp->flash_info->page_size - 4)) {
3698 cmd_flags |= BNX2_NVM_COMMAND_LAST;
3700 rc = bnx2_nvram_read_dword(bp,
3706 goto nvram_write_end;
3712 /* Enable writes to flash interface (unlock write-protect) */
3713 if ((rc = bnx2_enable_nvram_write(bp)) != 0)
3714 goto nvram_write_end;
3716 /* Loop to write back the buffer data from page_start to
3719 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
3720 /* Erase the page */
3721 if ((rc = bnx2_nvram_erase_page(bp, page_start)) != 0)
3722 goto nvram_write_end;
3724 /* Re-enable the write again for the actual write */
3725 bnx2_enable_nvram_write(bp);
3727 for (addr = page_start; addr < data_start;
3728 addr += 4, i += 4) {
3730 rc = bnx2_nvram_write_dword(bp, addr,
3731 &flash_buffer[i], cmd_flags);
3734 goto nvram_write_end;
3740 /* Loop to write the new data from data_start to data_end */
3741 for (addr = data_start; addr < data_end; addr += 4, i += 4) {
3742 if ((addr == page_end - 4) ||
3743 ((bp->flash_info->flags & BNX2_NV_BUFFERED) &&
3744 (addr == data_end - 4))) {
3746 cmd_flags |= BNX2_NVM_COMMAND_LAST;
3748 rc = bnx2_nvram_write_dword(bp, addr, buf,
3752 goto nvram_write_end;
3758 /* Loop to write back the buffer data from data_end
3760 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
3761 for (addr = data_end; addr < page_end;
3762 addr += 4, i += 4) {
3764 if (addr == page_end-4) {
3765 cmd_flags = BNX2_NVM_COMMAND_LAST;
3767 rc = bnx2_nvram_write_dword(bp, addr,
3768 &flash_buffer[i], cmd_flags);
3771 goto nvram_write_end;
3777 /* Disable writes to flash interface (lock write-protect) */
3778 bnx2_disable_nvram_write(bp);
3780 /* Disable access to flash interface */
3781 bnx2_disable_nvram_access(bp);
3782 bnx2_release_nvram_lock(bp);
3784 /* Increment written */
3785 written += data_end - data_start;
3789 kfree(flash_buffer);
3795 bnx2_init_remote_phy(struct bnx2 *bp)
3799 bp->phy_flags &= ~REMOTE_PHY_CAP_FLAG;
3800 if (!(bp->phy_flags & PHY_SERDES_FLAG))
3803 val = REG_RD_IND(bp, bp->shmem_base + BNX2_FW_CAP_MB);
3804 if ((val & BNX2_FW_CAP_SIGNATURE_MASK) != BNX2_FW_CAP_SIGNATURE)
3807 if (val & BNX2_FW_CAP_REMOTE_PHY_CAPABLE) {
3808 bp->phy_flags |= REMOTE_PHY_CAP_FLAG;
3810 val = REG_RD_IND(bp, bp->shmem_base + BNX2_LINK_STATUS);
3811 if (val & BNX2_LINK_STATUS_SERDES_LINK)
3812 bp->phy_port = PORT_FIBRE;
3814 bp->phy_port = PORT_TP;
3816 if (netif_running(bp->dev)) {
3819 if (val & BNX2_LINK_STATUS_LINK_UP) {
3821 netif_carrier_on(bp->dev);
3824 netif_carrier_off(bp->dev);
3826 sig = BNX2_DRV_ACK_CAP_SIGNATURE |
3827 BNX2_FW_CAP_REMOTE_PHY_CAPABLE;
3828 REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_ACK_CAP_MB,
3835 bnx2_reset_chip(struct bnx2 *bp, u32 reset_code)
3841 /* Wait for the current PCI transaction to complete before
3842 * issuing a reset. */
3843 REG_WR(bp, BNX2_MISC_ENABLE_CLR_BITS,
3844 BNX2_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE |
3845 BNX2_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE |
3846 BNX2_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE |
3847 BNX2_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE);
3848 val = REG_RD(bp, BNX2_MISC_ENABLE_CLR_BITS);
3851 /* Wait for the firmware to tell us it is ok to issue a reset. */
3852 bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT0 | reset_code, 1);
3854 /* Deposit a driver reset signature so the firmware knows that
3855 * this is a soft reset. */
3856 REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_RESET_SIGNATURE,
3857 BNX2_DRV_RESET_SIGNATURE_MAGIC);
3859 /* Do a dummy read to force the chip to complete all current transaction
3860 * before we issue a reset. */
3861 val = REG_RD(bp, BNX2_MISC_ID);
3863 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
3864 REG_WR(bp, BNX2_MISC_COMMAND, BNX2_MISC_COMMAND_SW_RESET);
3865 REG_RD(bp, BNX2_MISC_COMMAND);
3868 val = BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
3869 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
3871 pci_write_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG, val);
3874 val = BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
3875 BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
3876 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
3879 REG_WR(bp, BNX2_PCICFG_MISC_CONFIG, val);
3881 /* Reading back any register after chip reset will hang the
3882 * bus on 5706 A0 and A1. The msleep below provides plenty
3883 * of margin for write posting.
3885 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
3886 (CHIP_ID(bp) == CHIP_ID_5706_A1))
3889 /* Reset takes approximate 30 usec */
3890 for (i = 0; i < 10; i++) {
3891 val = REG_RD(bp, BNX2_PCICFG_MISC_CONFIG);
3892 if ((val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
3893 BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0)
3898 if (val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
3899 BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) {
3900 printk(KERN_ERR PFX "Chip reset did not complete\n");
3905 /* Make sure byte swapping is properly configured. */
3906 val = REG_RD(bp, BNX2_PCI_SWAP_DIAG0);
3907 if (val != 0x01020304) {
3908 printk(KERN_ERR PFX "Chip not in correct endian mode\n");
3912 /* Wait for the firmware to finish its initialization. */
3913 rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT1 | reset_code, 0);
3917 spin_lock_bh(&bp->phy_lock);
3918 old_port = bp->phy_port;
3919 bnx2_init_remote_phy(bp);
3920 if ((bp->phy_flags & REMOTE_PHY_CAP_FLAG) && old_port != bp->phy_port)
3921 bnx2_set_default_remote_link(bp);
3922 spin_unlock_bh(&bp->phy_lock);
3924 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
3925 /* Adjust the voltage regular to two steps lower. The default
3926 * of this register is 0x0000000e. */
3927 REG_WR(bp, BNX2_MISC_VREG_CONTROL, 0x000000fa);
3929 /* Remove bad rbuf memory from the free pool. */
3930 rc = bnx2_alloc_bad_rbuf(bp);
3937 bnx2_init_chip(struct bnx2 *bp)
3942 /* Make sure the interrupt is not active. */
3943 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
3945 val = BNX2_DMA_CONFIG_DATA_BYTE_SWAP |
3946 BNX2_DMA_CONFIG_DATA_WORD_SWAP |
3948 BNX2_DMA_CONFIG_CNTL_BYTE_SWAP |
3950 BNX2_DMA_CONFIG_CNTL_WORD_SWAP |
3951 DMA_READ_CHANS << 12 |
3952 DMA_WRITE_CHANS << 16;
3954 val |= (0x2 << 20) | (1 << 11);
3956 if ((bp->flags & PCIX_FLAG) && (bp->bus_speed_mhz == 133))
3959 if ((CHIP_NUM(bp) == CHIP_NUM_5706) &&
3960 (CHIP_ID(bp) != CHIP_ID_5706_A0) && !(bp->flags & PCIX_FLAG))
3961 val |= BNX2_DMA_CONFIG_CNTL_PING_PONG_DMA;
3963 REG_WR(bp, BNX2_DMA_CONFIG, val);
3965 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
3966 val = REG_RD(bp, BNX2_TDMA_CONFIG);
3967 val |= BNX2_TDMA_CONFIG_ONE_DMA;
3968 REG_WR(bp, BNX2_TDMA_CONFIG, val);
3971 if (bp->flags & PCIX_FLAG) {
3974 pci_read_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
3976 pci_write_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
3977 val16 & ~PCI_X_CMD_ERO);
3980 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
3981 BNX2_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE |
3982 BNX2_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE |
3983 BNX2_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE);
3985 /* Initialize context mapping and zero out the quick contexts. The
3986 * context block must have already been enabled. */
3987 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
3988 rc = bnx2_init_5709_context(bp);
3992 bnx2_init_context(bp);
3994 if ((rc = bnx2_init_cpus(bp)) != 0)
3997 bnx2_init_nvram(bp);
3999 bnx2_set_mac_addr(bp);
4001 val = REG_RD(bp, BNX2_MQ_CONFIG);
4002 val &= ~BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE;
4003 val |= BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_256;
4004 if (CHIP_ID(bp) == CHIP_ID_5709_A0 || CHIP_ID(bp) == CHIP_ID_5709_A1)
4005 val |= BNX2_MQ_CONFIG_HALT_DIS;
4007 REG_WR(bp, BNX2_MQ_CONFIG, val);
4009 val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE);
4010 REG_WR(bp, BNX2_MQ_KNL_BYP_WIND_START, val);
4011 REG_WR(bp, BNX2_MQ_KNL_WIND_END, val);
4013 val = (BCM_PAGE_BITS - 8) << 24;
4014 REG_WR(bp, BNX2_RV2P_CONFIG, val);
4016 /* Configure page size. */
4017 val = REG_RD(bp, BNX2_TBDR_CONFIG);
4018 val &= ~BNX2_TBDR_CONFIG_PAGE_SIZE;
4019 val |= (BCM_PAGE_BITS - 8) << 24 | 0x40;
4020 REG_WR(bp, BNX2_TBDR_CONFIG, val);
4022 val = bp->mac_addr[0] +
4023 (bp->mac_addr[1] << 8) +
4024 (bp->mac_addr[2] << 16) +
4026 (bp->mac_addr[4] << 8) +
4027 (bp->mac_addr[5] << 16);
4028 REG_WR(bp, BNX2_EMAC_BACKOFF_SEED, val);
4030 /* Program the MTU. Also include 4 bytes for CRC32. */
4031 val = bp->dev->mtu + ETH_HLEN + 4;
4032 if (val > (MAX_ETHERNET_PACKET_SIZE + 4))
4033 val |= BNX2_EMAC_RX_MTU_SIZE_JUMBO_ENA;
4034 REG_WR(bp, BNX2_EMAC_RX_MTU_SIZE, val);
4036 bp->last_status_idx = 0;
4037 bp->rx_mode = BNX2_EMAC_RX_MODE_SORT_MODE;
4039 /* Set up how to generate a link change interrupt. */
4040 REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
4042 REG_WR(bp, BNX2_HC_STATUS_ADDR_L,
4043 (u64) bp->status_blk_mapping & 0xffffffff);
4044 REG_WR(bp, BNX2_HC_STATUS_ADDR_H, (u64) bp->status_blk_mapping >> 32);
4046 REG_WR(bp, BNX2_HC_STATISTICS_ADDR_L,
4047 (u64) bp->stats_blk_mapping & 0xffffffff);
4048 REG_WR(bp, BNX2_HC_STATISTICS_ADDR_H,
4049 (u64) bp->stats_blk_mapping >> 32);
4051 REG_WR(bp, BNX2_HC_TX_QUICK_CONS_TRIP,
4052 (bp->tx_quick_cons_trip_int << 16) | bp->tx_quick_cons_trip);
4054 REG_WR(bp, BNX2_HC_RX_QUICK_CONS_TRIP,
4055 (bp->rx_quick_cons_trip_int << 16) | bp->rx_quick_cons_trip);
4057 REG_WR(bp, BNX2_HC_COMP_PROD_TRIP,
4058 (bp->comp_prod_trip_int << 16) | bp->comp_prod_trip);
4060 REG_WR(bp, BNX2_HC_TX_TICKS, (bp->tx_ticks_int << 16) | bp->tx_ticks);
4062 REG_WR(bp, BNX2_HC_RX_TICKS, (bp->rx_ticks_int << 16) | bp->rx_ticks);
4064 REG_WR(bp, BNX2_HC_COM_TICKS,
4065 (bp->com_ticks_int << 16) | bp->com_ticks);
4067 REG_WR(bp, BNX2_HC_CMD_TICKS,
4068 (bp->cmd_ticks_int << 16) | bp->cmd_ticks);
4070 if (CHIP_NUM(bp) == CHIP_NUM_5708)
4071 REG_WR(bp, BNX2_HC_STATS_TICKS, 0);
4073 REG_WR(bp, BNX2_HC_STATS_TICKS, bp->stats_ticks);
4074 REG_WR(bp, BNX2_HC_STAT_COLLECT_TICKS, 0xbb8); /* 3ms */
4076 if (CHIP_ID(bp) == CHIP_ID_5706_A1)
4077 val = BNX2_HC_CONFIG_COLLECT_STATS;
4079 val = BNX2_HC_CONFIG_RX_TMR_MODE | BNX2_HC_CONFIG_TX_TMR_MODE |
4080 BNX2_HC_CONFIG_COLLECT_STATS;
4083 if (bp->flags & ONE_SHOT_MSI_FLAG)
4084 val |= BNX2_HC_CONFIG_ONE_SHOT;
4086 REG_WR(bp, BNX2_HC_CONFIG, val);
4088 /* Clear internal stats counters. */
4089 REG_WR(bp, BNX2_HC_COMMAND, BNX2_HC_COMMAND_CLR_STAT_NOW);
4091 REG_WR(bp, BNX2_HC_ATTN_BITS_ENABLE, STATUS_ATTN_EVENTS);
4093 /* Initialize the receive filter. */
4094 bnx2_set_rx_mode(bp->dev);
4096 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4097 val = REG_RD(bp, BNX2_MISC_NEW_CORE_CTL);
4098 val |= BNX2_MISC_NEW_CORE_CTL_DMA_ENABLE;
4099 REG_WR(bp, BNX2_MISC_NEW_CORE_CTL, val);
4101 rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT2 | BNX2_DRV_MSG_CODE_RESET,
4104 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS, BNX2_MISC_ENABLE_DEFAULT);
4105 REG_RD(bp, BNX2_MISC_ENABLE_SET_BITS);
4109 bp->hc_cmd = REG_RD(bp, BNX2_HC_COMMAND);
4115 bnx2_init_tx_context(struct bnx2 *bp, u32 cid)
4117 u32 val, offset0, offset1, offset2, offset3;
4119 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4120 offset0 = BNX2_L2CTX_TYPE_XI;
4121 offset1 = BNX2_L2CTX_CMD_TYPE_XI;
4122 offset2 = BNX2_L2CTX_TBDR_BHADDR_HI_XI;
4123 offset3 = BNX2_L2CTX_TBDR_BHADDR_LO_XI;
4125 offset0 = BNX2_L2CTX_TYPE;
4126 offset1 = BNX2_L2CTX_CMD_TYPE;
4127 offset2 = BNX2_L2CTX_TBDR_BHADDR_HI;
4128 offset3 = BNX2_L2CTX_TBDR_BHADDR_LO;
4130 val = BNX2_L2CTX_TYPE_TYPE_L2 | BNX2_L2CTX_TYPE_SIZE_L2;
4131 CTX_WR(bp, GET_CID_ADDR(cid), offset0, val);
4133 val = BNX2_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16);
4134 CTX_WR(bp, GET_CID_ADDR(cid), offset1, val);
4136 val = (u64) bp->tx_desc_mapping >> 32;
4137 CTX_WR(bp, GET_CID_ADDR(cid), offset2, val);
4139 val = (u64) bp->tx_desc_mapping & 0xffffffff;
4140 CTX_WR(bp, GET_CID_ADDR(cid), offset3, val);
4144 bnx2_init_tx_ring(struct bnx2 *bp)
4149 bp->tx_wake_thresh = bp->tx_ring_size / 2;
4151 txbd = &bp->tx_desc_ring[MAX_TX_DESC_CNT];
4153 txbd->tx_bd_haddr_hi = (u64) bp->tx_desc_mapping >> 32;
4154 txbd->tx_bd_haddr_lo = (u64) bp->tx_desc_mapping & 0xffffffff;
4159 bp->tx_prod_bseq = 0;
4162 bp->tx_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_TX_HOST_BIDX;
4163 bp->tx_bseq_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_TX_HOST_BSEQ;
4165 bnx2_init_tx_context(bp, cid);
4169 bnx2_init_rxbd_rings(struct rx_bd *rx_ring[], dma_addr_t dma[], u32 buf_size,
4175 for (i = 0; i < num_rings; i++) {
4178 rxbd = &rx_ring[i][0];
4179 for (j = 0; j < MAX_RX_DESC_CNT; j++, rxbd++) {
4180 rxbd->rx_bd_len = buf_size;
4181 rxbd->rx_bd_flags = RX_BD_FLAGS_START | RX_BD_FLAGS_END;
4183 if (i == (num_rings - 1))
4187 rxbd->rx_bd_haddr_hi = (u64) dma[j] >> 32;
4188 rxbd->rx_bd_haddr_lo = (u64) dma[j] & 0xffffffff;
4193 bnx2_init_rx_ring(struct bnx2 *bp)
4196 u16 prod, ring_prod;
4197 u32 val, rx_cid_addr = GET_CID_ADDR(RX_CID);
4201 bp->rx_prod_bseq = 0;
4203 bnx2_init_rxbd_rings(bp->rx_desc_ring, bp->rx_desc_mapping,
4204 bp->rx_buf_use_size, bp->rx_max_ring);
4206 CTX_WR(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, 0);
4208 val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE;
4209 val |= BNX2_L2CTX_CTX_TYPE_SIZE_L2;
4211 CTX_WR(bp, rx_cid_addr, BNX2_L2CTX_CTX_TYPE, val);
4213 val = (u64) bp->rx_desc_mapping[0] >> 32;
4214 CTX_WR(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_HI, val);
4216 val = (u64) bp->rx_desc_mapping[0] & 0xffffffff;
4217 CTX_WR(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_LO, val);
4219 ring_prod = prod = bp->rx_prod;
4220 for (i = 0; i < bp->rx_ring_size; i++) {
4221 if (bnx2_alloc_rx_skb(bp, ring_prod) < 0) {
4224 prod = NEXT_RX_BD(prod);
4225 ring_prod = RX_RING_IDX(prod);
4229 REG_WR16(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BDIDX, prod);
4231 REG_WR(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BSEQ, bp->rx_prod_bseq);
4234 static u32 bnx2_find_max_ring(u32 ring_size, u32 max_size)
4236 u32 max, num_rings = 1;
4238 while (ring_size > MAX_RX_DESC_CNT) {
4239 ring_size -= MAX_RX_DESC_CNT;
4242 /* round to next power of 2 */
4244 while ((max & num_rings) == 0)
4247 if (num_rings != max)
4254 bnx2_set_rx_ring_size(struct bnx2 *bp, u32 size)
4258 /* 8 for CRC and VLAN */
4259 rx_size = bp->dev->mtu + ETH_HLEN + bp->rx_offset + 8;
4261 bp->rx_copy_thresh = RX_COPY_THRESH;
4263 bp->rx_buf_use_size = rx_size;
4265 bp->rx_buf_size = bp->rx_buf_use_size + BNX2_RX_ALIGN;
4266 bp->rx_ring_size = size;
4267 bp->rx_max_ring = bnx2_find_max_ring(size, MAX_RX_RINGS);
4268 bp->rx_max_ring_idx = (bp->rx_max_ring * RX_DESC_CNT) - 1;
4272 bnx2_free_tx_skbs(struct bnx2 *bp)
4276 if (bp->tx_buf_ring == NULL)
4279 for (i = 0; i < TX_DESC_CNT; ) {
4280 struct sw_bd *tx_buf = &bp->tx_buf_ring[i];
4281 struct sk_buff *skb = tx_buf->skb;
4289 pci_unmap_single(bp->pdev, pci_unmap_addr(tx_buf, mapping),
4290 skb_headlen(skb), PCI_DMA_TODEVICE);
4294 last = skb_shinfo(skb)->nr_frags;
4295 for (j = 0; j < last; j++) {
4296 tx_buf = &bp->tx_buf_ring[i + j + 1];
4297 pci_unmap_page(bp->pdev,
4298 pci_unmap_addr(tx_buf, mapping),
4299 skb_shinfo(skb)->frags[j].size,
4309 bnx2_free_rx_skbs(struct bnx2 *bp)
4313 if (bp->rx_buf_ring == NULL)
4316 for (i = 0; i < bp->rx_max_ring_idx; i++) {
4317 struct sw_bd *rx_buf = &bp->rx_buf_ring[i];
4318 struct sk_buff *skb = rx_buf->skb;
4323 pci_unmap_single(bp->pdev, pci_unmap_addr(rx_buf, mapping),
4324 bp->rx_buf_use_size, PCI_DMA_FROMDEVICE);
4333 bnx2_free_skbs(struct bnx2 *bp)
4335 bnx2_free_tx_skbs(bp);
4336 bnx2_free_rx_skbs(bp);
4340 bnx2_reset_nic(struct bnx2 *bp, u32 reset_code)
4344 rc = bnx2_reset_chip(bp, reset_code);
4349 if ((rc = bnx2_init_chip(bp)) != 0)
4352 bnx2_init_tx_ring(bp);
4353 bnx2_init_rx_ring(bp);
4358 bnx2_init_nic(struct bnx2 *bp)
4362 if ((rc = bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET)) != 0)
4365 spin_lock_bh(&bp->phy_lock);
4368 spin_unlock_bh(&bp->phy_lock);
4373 bnx2_test_registers(struct bnx2 *bp)
4377 static const struct {
4380 #define BNX2_FL_NOT_5709 1
4384 { 0x006c, 0, 0x00000000, 0x0000003f },
4385 { 0x0090, 0, 0xffffffff, 0x00000000 },
4386 { 0x0094, 0, 0x00000000, 0x00000000 },
4388 { 0x0404, BNX2_FL_NOT_5709, 0x00003f00, 0x00000000 },
4389 { 0x0418, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
4390 { 0x041c, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
4391 { 0x0420, BNX2_FL_NOT_5709, 0x00000000, 0x80ffffff },
4392 { 0x0424, BNX2_FL_NOT_5709, 0x00000000, 0x00000000 },
4393 { 0x0428, BNX2_FL_NOT_5709, 0x00000000, 0x00000001 },
4394 { 0x0450, BNX2_FL_NOT_5709, 0x00000000, 0x0000ffff },
4395 { 0x0454, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
4396 { 0x0458, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
4398 { 0x0808, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
4399 { 0x0854, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
4400 { 0x0868, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
4401 { 0x086c, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
4402 { 0x0870, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
4403 { 0x0874, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
4405 { 0x0c00, BNX2_FL_NOT_5709, 0x00000000, 0x00000001 },
4406 { 0x0c04, BNX2_FL_NOT_5709, 0x00000000, 0x03ff0001 },
4407 { 0x0c08, BNX2_FL_NOT_5709, 0x0f0ff073, 0x00000000 },
4409 { 0x1000, 0, 0x00000000, 0x00000001 },
4410 { 0x1004, 0, 0x00000000, 0x000f0001 },
4412 { 0x1408, 0, 0x01c00800, 0x00000000 },
4413 { 0x149c, 0, 0x8000ffff, 0x00000000 },
4414 { 0x14a8, 0, 0x00000000, 0x000001ff },
4415 { 0x14ac, 0, 0x0fffffff, 0x10000000 },
4416 { 0x14b0, 0, 0x00000002, 0x00000001 },
4417 { 0x14b8, 0, 0x00000000, 0x00000000 },
4418 { 0x14c0, 0, 0x00000000, 0x00000009 },
4419 { 0x14c4, 0, 0x00003fff, 0x00000000 },
4420 { 0x14cc, 0, 0x00000000, 0x00000001 },
4421 { 0x14d0, 0, 0xffffffff, 0x00000000 },
4423 { 0x1800, 0, 0x00000000, 0x00000001 },
4424 { 0x1804, 0, 0x00000000, 0x00000003 },
4426 { 0x2800, 0, 0x00000000, 0x00000001 },
4427 { 0x2804, 0, 0x00000000, 0x00003f01 },
4428 { 0x2808, 0, 0x0f3f3f03, 0x00000000 },
4429 { 0x2810, 0, 0xffff0000, 0x00000000 },
4430 { 0x2814, 0, 0xffff0000, 0x00000000 },
4431 { 0x2818, 0, 0xffff0000, 0x00000000 },
4432 { 0x281c, 0, 0xffff0000, 0x00000000 },
4433 { 0x2834, 0, 0xffffffff, 0x00000000 },
4434 { 0x2840, 0, 0x00000000, 0xffffffff },
4435 { 0x2844, 0, 0x00000000, 0xffffffff },
4436 { 0x2848, 0, 0xffffffff, 0x00000000 },
4437 { 0x284c, 0, 0xf800f800, 0x07ff07ff },
4439 { 0x2c00, 0, 0x00000000, 0x00000011 },
4440 { 0x2c04, 0, 0x00000000, 0x00030007 },
4442 { 0x3c00, 0, 0x00000000, 0x00000001 },
4443 { 0x3c04, 0, 0x00000000, 0x00070000 },
4444 { 0x3c08, 0, 0x00007f71, 0x07f00000 },
4445 { 0x3c0c, 0, 0x1f3ffffc, 0x00000000 },
4446 { 0x3c10, 0, 0xffffffff, 0x00000000 },
4447 { 0x3c14, 0, 0x00000000, 0xffffffff },
4448 { 0x3c18, 0, 0x00000000, 0xffffffff },
4449 { 0x3c1c, 0, 0xfffff000, 0x00000000 },
4450 { 0x3c20, 0, 0xffffff00, 0x00000000 },
4452 { 0x5004, 0, 0x00000000, 0x0000007f },
4453 { 0x5008, 0, 0x0f0007ff, 0x00000000 },
4455 { 0x5c00, 0, 0x00000000, 0x00000001 },
4456 { 0x5c04, 0, 0x00000000, 0x0003000f },
4457 { 0x5c08, 0, 0x00000003, 0x00000000 },
4458 { 0x5c0c, 0, 0x0000fff8, 0x00000000 },
4459 { 0x5c10, 0, 0x00000000, 0xffffffff },
4460 { 0x5c80, 0, 0x00000000, 0x0f7113f1 },
4461 { 0x5c84, 0, 0x00000000, 0x0000f333 },
4462 { 0x5c88, 0, 0x00000000, 0x00077373 },
4463 { 0x5c8c, 0, 0x00000000, 0x0007f737 },
4465 { 0x6808, 0, 0x0000ff7f, 0x00000000 },
4466 { 0x680c, 0, 0xffffffff, 0x00000000 },
4467 { 0x6810, 0, 0xffffffff, 0x00000000 },
4468 { 0x6814, 0, 0xffffffff, 0x00000000 },
4469 { 0x6818, 0, 0xffffffff, 0x00000000 },
4470 { 0x681c, 0, 0xffffffff, 0x00000000 },
4471 { 0x6820, 0, 0x00ff00ff, 0x00000000 },
4472 { 0x6824, 0, 0x00ff00ff, 0x00000000 },
4473 { 0x6828, 0, 0x00ff00ff, 0x00000000 },
4474 { 0x682c, 0, 0x03ff03ff, 0x00000000 },
4475 { 0x6830, 0, 0x03ff03ff, 0x00000000 },
4476 { 0x6834, 0, 0x03ff03ff, 0x00000000 },
4477 { 0x6838, 0, 0x03ff03ff, 0x00000000 },
4478 { 0x683c, 0, 0x0000ffff, 0x00000000 },
4479 { 0x6840, 0, 0x00000ff0, 0x00000000 },
4480 { 0x6844, 0, 0x00ffff00, 0x00000000 },
4481 { 0x684c, 0, 0xffffffff, 0x00000000 },
4482 { 0x6850, 0, 0x7f7f7f7f, 0x00000000 },
4483 { 0x6854, 0, 0x7f7f7f7f, 0x00000000 },
4484 { 0x6858, 0, 0x7f7f7f7f, 0x00000000 },
4485 { 0x685c, 0, 0x7f7f7f7f, 0x00000000 },
4486 { 0x6908, 0, 0x00000000, 0x0001ff0f },
4487 { 0x690c, 0, 0x00000000, 0x0ffe00f0 },
4489 { 0xffff, 0, 0x00000000, 0x00000000 },
4494 if (CHIP_NUM(bp) == CHIP_NUM_5709)
4497 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
4498 u32 offset, rw_mask, ro_mask, save_val, val;
4499 u16 flags = reg_tbl[i].flags;
4501 if (is_5709 && (flags & BNX2_FL_NOT_5709))
4504 offset = (u32) reg_tbl[i].offset;
4505 rw_mask = reg_tbl[i].rw_mask;
4506 ro_mask = reg_tbl[i].ro_mask;
4508 save_val = readl(bp->regview + offset);
4510 writel(0, bp->regview + offset);
4512 val = readl(bp->regview + offset);
4513 if ((val & rw_mask) != 0) {
4517 if ((val & ro_mask) != (save_val & ro_mask)) {
4521 writel(0xffffffff, bp->regview + offset);
4523 val = readl(bp->regview + offset);
4524 if ((val & rw_mask) != rw_mask) {
4528 if ((val & ro_mask) != (save_val & ro_mask)) {
4532 writel(save_val, bp->regview + offset);
4536 writel(save_val, bp->regview + offset);
4544 bnx2_do_mem_test(struct bnx2 *bp, u32 start, u32 size)
4546 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0x55555555,
4547 0xaaaaaaaa , 0xaa55aa55, 0x55aa55aa };
4550 for (i = 0; i < sizeof(test_pattern) / 4; i++) {
4553 for (offset = 0; offset < size; offset += 4) {
4555 REG_WR_IND(bp, start + offset, test_pattern[i]);
4557 if (REG_RD_IND(bp, start + offset) !=
4567 bnx2_test_memory(struct bnx2 *bp)
4571 static struct mem_entry {
4574 } mem_tbl_5706[] = {
4575 { 0x60000, 0x4000 },
4576 { 0xa0000, 0x3000 },
4577 { 0xe0000, 0x4000 },
4578 { 0x120000, 0x4000 },
4579 { 0x1a0000, 0x4000 },
4580 { 0x160000, 0x4000 },
4584 { 0x60000, 0x4000 },
4585 { 0xa0000, 0x3000 },
4586 { 0xe0000, 0x4000 },
4587 { 0x120000, 0x4000 },
4588 { 0x1a0000, 0x4000 },
4591 struct mem_entry *mem_tbl;
4593 if (CHIP_NUM(bp) == CHIP_NUM_5709)
4594 mem_tbl = mem_tbl_5709;
4596 mem_tbl = mem_tbl_5706;
4598 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
4599 if ((ret = bnx2_do_mem_test(bp, mem_tbl[i].offset,
4600 mem_tbl[i].len)) != 0) {
4608 #define BNX2_MAC_LOOPBACK 0
4609 #define BNX2_PHY_LOOPBACK 1
4612 bnx2_run_loopback(struct bnx2 *bp, int loopback_mode)
4614 unsigned int pkt_size, num_pkts, i;
4615 struct sk_buff *skb, *rx_skb;
4616 unsigned char *packet;
4617 u16 rx_start_idx, rx_idx;
4620 struct sw_bd *rx_buf;
4621 struct l2_fhdr *rx_hdr;
4624 if (loopback_mode == BNX2_MAC_LOOPBACK) {
4625 bp->loopback = MAC_LOOPBACK;
4626 bnx2_set_mac_loopback(bp);
4628 else if (loopback_mode == BNX2_PHY_LOOPBACK) {
4629 if (bp->phy_flags & REMOTE_PHY_CAP_FLAG)
4632 bp->loopback = PHY_LOOPBACK;
4633 bnx2_set_phy_loopback(bp);
4639 skb = netdev_alloc_skb(bp->dev, pkt_size);
4642 packet = skb_put(skb, pkt_size);
4643 memcpy(packet, bp->dev->dev_addr, 6);
4644 memset(packet + 6, 0x0, 8);
4645 for (i = 14; i < pkt_size; i++)
4646 packet[i] = (unsigned char) (i & 0xff);
4648 map = pci_map_single(bp->pdev, skb->data, pkt_size,
4651 REG_WR(bp, BNX2_HC_COMMAND,
4652 bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
4654 REG_RD(bp, BNX2_HC_COMMAND);
4657 rx_start_idx = bp->status_blk->status_rx_quick_consumer_index0;
4661 txbd = &bp->tx_desc_ring[TX_RING_IDX(bp->tx_prod)];
4663 txbd->tx_bd_haddr_hi = (u64) map >> 32;
4664 txbd->tx_bd_haddr_lo = (u64) map & 0xffffffff;
4665 txbd->tx_bd_mss_nbytes = pkt_size;
4666 txbd->tx_bd_vlan_tag_flags = TX_BD_FLAGS_START | TX_BD_FLAGS_END;
4669 bp->tx_prod = NEXT_TX_BD(bp->tx_prod);
4670 bp->tx_prod_bseq += pkt_size;
4672 REG_WR16(bp, bp->tx_bidx_addr, bp->tx_prod);
4673 REG_WR(bp, bp->tx_bseq_addr, bp->tx_prod_bseq);
4677 REG_WR(bp, BNX2_HC_COMMAND,
4678 bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
4680 REG_RD(bp, BNX2_HC_COMMAND);
4684 pci_unmap_single(bp->pdev, map, pkt_size, PCI_DMA_TODEVICE);
4687 if (bp->status_blk->status_tx_quick_consumer_index0 != bp->tx_prod) {
4688 goto loopback_test_done;
4691 rx_idx = bp->status_blk->status_rx_quick_consumer_index0;
4692 if (rx_idx != rx_start_idx + num_pkts) {
4693 goto loopback_test_done;
4696 rx_buf = &bp->rx_buf_ring[rx_start_idx];
4697 rx_skb = rx_buf->skb;
4699 rx_hdr = (struct l2_fhdr *) rx_skb->data;
4700 skb_reserve(rx_skb, bp->rx_offset);
4702 pci_dma_sync_single_for_cpu(bp->pdev,
4703 pci_unmap_addr(rx_buf, mapping),
4704 bp->rx_buf_size, PCI_DMA_FROMDEVICE);
4706 if (rx_hdr->l2_fhdr_status &
4707 (L2_FHDR_ERRORS_BAD_CRC |
4708 L2_FHDR_ERRORS_PHY_DECODE |
4709 L2_FHDR_ERRORS_ALIGNMENT |
4710 L2_FHDR_ERRORS_TOO_SHORT |
4711 L2_FHDR_ERRORS_GIANT_FRAME)) {
4713 goto loopback_test_done;
4716 if ((rx_hdr->l2_fhdr_pkt_len - 4) != pkt_size) {
4717 goto loopback_test_done;
4720 for (i = 14; i < pkt_size; i++) {
4721 if (*(rx_skb->data + i) != (unsigned char) (i & 0xff)) {
4722 goto loopback_test_done;
4733 #define BNX2_MAC_LOOPBACK_FAILED 1
4734 #define BNX2_PHY_LOOPBACK_FAILED 2
4735 #define BNX2_LOOPBACK_FAILED (BNX2_MAC_LOOPBACK_FAILED | \
4736 BNX2_PHY_LOOPBACK_FAILED)
4739 bnx2_test_loopback(struct bnx2 *bp)
4743 if (!netif_running(bp->dev))
4744 return BNX2_LOOPBACK_FAILED;
4746 bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET);
4747 spin_lock_bh(&bp->phy_lock);
4749 spin_unlock_bh(&bp->phy_lock);
4750 if (bnx2_run_loopback(bp, BNX2_MAC_LOOPBACK))
4751 rc |= BNX2_MAC_LOOPBACK_FAILED;
4752 if (bnx2_run_loopback(bp, BNX2_PHY_LOOPBACK))
4753 rc |= BNX2_PHY_LOOPBACK_FAILED;
4757 #define NVRAM_SIZE 0x200
4758 #define CRC32_RESIDUAL 0xdebb20e3
4761 bnx2_test_nvram(struct bnx2 *bp)
4763 u32 buf[NVRAM_SIZE / 4];
4764 u8 *data = (u8 *) buf;
4768 if ((rc = bnx2_nvram_read(bp, 0, data, 4)) != 0)
4769 goto test_nvram_done;
4771 magic = be32_to_cpu(buf[0]);
4772 if (magic != 0x669955aa) {
4774 goto test_nvram_done;
4777 if ((rc = bnx2_nvram_read(bp, 0x100, data, NVRAM_SIZE)) != 0)
4778 goto test_nvram_done;
4780 csum = ether_crc_le(0x100, data);
4781 if (csum != CRC32_RESIDUAL) {
4783 goto test_nvram_done;
4786 csum = ether_crc_le(0x100, data + 0x100);
4787 if (csum != CRC32_RESIDUAL) {
4796 bnx2_test_link(struct bnx2 *bp)
4800 if (bp->phy_flags & REMOTE_PHY_CAP_FLAG) {
4805 spin_lock_bh(&bp->phy_lock);
4806 bnx2_enable_bmsr1(bp);
4807 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
4808 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
4809 bnx2_disable_bmsr1(bp);
4810 spin_unlock_bh(&bp->phy_lock);
4812 if (bmsr & BMSR_LSTATUS) {
4819 bnx2_test_intr(struct bnx2 *bp)
4824 if (!netif_running(bp->dev))
4827 status_idx = REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff;
4829 /* This register is not touched during run-time. */
4830 REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW);
4831 REG_RD(bp, BNX2_HC_COMMAND);
4833 for (i = 0; i < 10; i++) {
4834 if ((REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff) !=
4840 msleep_interruptible(10);
4849 bnx2_5706_serdes_timer(struct bnx2 *bp)
4851 spin_lock(&bp->phy_lock);
4852 if (bp->serdes_an_pending)
4853 bp->serdes_an_pending--;
4854 else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) {
4857 bp->current_interval = bp->timer_interval;
4859 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
4861 if (bmcr & BMCR_ANENABLE) {
4864 bnx2_write_phy(bp, 0x1c, 0x7c00);
4865 bnx2_read_phy(bp, 0x1c, &phy1);
4867 bnx2_write_phy(bp, 0x17, 0x0f01);
4868 bnx2_read_phy(bp, 0x15, &phy2);
4869 bnx2_write_phy(bp, 0x17, 0x0f01);
4870 bnx2_read_phy(bp, 0x15, &phy2);
4872 if ((phy1 & 0x10) && /* SIGNAL DETECT */
4873 !(phy2 & 0x20)) { /* no CONFIG */
4875 bmcr &= ~BMCR_ANENABLE;
4876 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
4877 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
4878 bp->phy_flags |= PHY_PARALLEL_DETECT_FLAG;
4882 else if ((bp->link_up) && (bp->autoneg & AUTONEG_SPEED) &&
4883 (bp->phy_flags & PHY_PARALLEL_DETECT_FLAG)) {
4886 bnx2_write_phy(bp, 0x17, 0x0f01);
4887 bnx2_read_phy(bp, 0x15, &phy2);
4891 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
4892 bmcr |= BMCR_ANENABLE;
4893 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
4895 bp->phy_flags &= ~PHY_PARALLEL_DETECT_FLAG;
4898 bp->current_interval = bp->timer_interval;
4900 spin_unlock(&bp->phy_lock);
4904 bnx2_5708_serdes_timer(struct bnx2 *bp)
4906 if (bp->phy_flags & REMOTE_PHY_CAP_FLAG)
4909 if ((bp->phy_flags & PHY_2_5G_CAPABLE_FLAG) == 0) {
4910 bp->serdes_an_pending = 0;
4914 spin_lock(&bp->phy_lock);
4915 if (bp->serdes_an_pending)
4916 bp->serdes_an_pending--;
4917 else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) {
4920 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
4921 if (bmcr & BMCR_ANENABLE) {
4922 bnx2_enable_forced_2g5(bp);
4923 bp->current_interval = SERDES_FORCED_TIMEOUT;
4925 bnx2_disable_forced_2g5(bp);
4926 bp->serdes_an_pending = 2;
4927 bp->current_interval = bp->timer_interval;
4931 bp->current_interval = bp->timer_interval;
4933 spin_unlock(&bp->phy_lock);
4937 bnx2_timer(unsigned long data)
4939 struct bnx2 *bp = (struct bnx2 *) data;
4941 if (!netif_running(bp->dev))
4944 if (atomic_read(&bp->intr_sem) != 0)
4945 goto bnx2_restart_timer;
4947 bnx2_send_heart_beat(bp);
4949 bp->stats_blk->stat_FwRxDrop = REG_RD_IND(bp, BNX2_FW_RX_DROP_COUNT);
4951 /* workaround occasional corrupted counters */
4952 if (CHIP_NUM(bp) == CHIP_NUM_5708 && bp->stats_ticks)
4953 REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd |
4954 BNX2_HC_COMMAND_STATS_NOW);
4956 if (bp->phy_flags & PHY_SERDES_FLAG) {
4957 if (CHIP_NUM(bp) == CHIP_NUM_5706)
4958 bnx2_5706_serdes_timer(bp);
4960 bnx2_5708_serdes_timer(bp);
4964 mod_timer(&bp->timer, jiffies + bp->current_interval);
4968 bnx2_request_irq(struct bnx2 *bp)
4970 struct net_device *dev = bp->dev;
4973 if (bp->flags & USING_MSI_FLAG) {
4974 irq_handler_t fn = bnx2_msi;
4976 if (bp->flags & ONE_SHOT_MSI_FLAG)
4977 fn = bnx2_msi_1shot;
4979 rc = request_irq(bp->pdev->irq, fn, 0, dev->name, dev);
4981 rc = request_irq(bp->pdev->irq, bnx2_interrupt,
4982 IRQF_SHARED, dev->name, dev);
4987 bnx2_free_irq(struct bnx2 *bp)
4989 struct net_device *dev = bp->dev;
4991 if (bp->flags & USING_MSI_FLAG) {
4992 free_irq(bp->pdev->irq, dev);
4993 pci_disable_msi(bp->pdev);
4994 bp->flags &= ~(USING_MSI_FLAG | ONE_SHOT_MSI_FLAG);
4996 free_irq(bp->pdev->irq, dev);
4999 /* Called with rtnl_lock */
5001 bnx2_open(struct net_device *dev)
5003 struct bnx2 *bp = netdev_priv(dev);
5006 netif_carrier_off(dev);
5008 bnx2_set_power_state(bp, PCI_D0);
5009 bnx2_disable_int(bp);
5011 rc = bnx2_alloc_mem(bp);
5015 napi_enable(&bp->napi);
5017 if ((bp->flags & MSI_CAP_FLAG) && !disable_msi) {
5018 if (pci_enable_msi(bp->pdev) == 0) {
5019 bp->flags |= USING_MSI_FLAG;
5020 if (CHIP_NUM(bp) == CHIP_NUM_5709)
5021 bp->flags |= ONE_SHOT_MSI_FLAG;
5024 rc = bnx2_request_irq(bp);
5027 napi_disable(&bp->napi);
5032 rc = bnx2_init_nic(bp);
5035 napi_disable(&bp->napi);
5042 mod_timer(&bp->timer, jiffies + bp->current_interval);
5044 atomic_set(&bp->intr_sem, 0);
5046 bnx2_enable_int(bp);
5048 if (bp->flags & USING_MSI_FLAG) {
5049 /* Test MSI to make sure it is working
5050 * If MSI test fails, go back to INTx mode
5052 if (bnx2_test_intr(bp) != 0) {
5053 printk(KERN_WARNING PFX "%s: No interrupt was generated"
5054 " using MSI, switching to INTx mode. Please"
5055 " report this failure to the PCI maintainer"
5056 " and include system chipset information.\n",
5059 bnx2_disable_int(bp);
5062 rc = bnx2_init_nic(bp);
5065 rc = bnx2_request_irq(bp);
5068 napi_disable(&bp->napi);
5071 del_timer_sync(&bp->timer);
5074 bnx2_enable_int(bp);
5077 if (bp->flags & USING_MSI_FLAG) {
5078 printk(KERN_INFO PFX "%s: using MSI\n", dev->name);
5081 netif_start_queue(dev);
5087 bnx2_reset_task(struct work_struct *work)
5089 struct bnx2 *bp = container_of(work, struct bnx2, reset_task);
5091 if (!netif_running(bp->dev))
5094 bp->in_reset_task = 1;
5095 bnx2_netif_stop(bp);
5099 atomic_set(&bp->intr_sem, 1);
5100 bnx2_netif_start(bp);
5101 bp->in_reset_task = 0;
5105 bnx2_tx_timeout(struct net_device *dev)
5107 struct bnx2 *bp = netdev_priv(dev);
5109 /* This allows the netif to be shutdown gracefully before resetting */
5110 schedule_work(&bp->reset_task);
5114 /* Called with rtnl_lock */
5116 bnx2_vlan_rx_register(struct net_device *dev, struct vlan_group *vlgrp)
5118 struct bnx2 *bp = netdev_priv(dev);
5120 bnx2_netif_stop(bp);
5123 bnx2_set_rx_mode(dev);
5125 bnx2_netif_start(bp);
5129 /* Called with netif_tx_lock.
5130 * bnx2_tx_int() runs without netif_tx_lock unless it needs to call
5131 * netif_wake_queue().
5134 bnx2_start_xmit(struct sk_buff *skb, struct net_device *dev)
5136 struct bnx2 *bp = netdev_priv(dev);
5139 struct sw_bd *tx_buf;
5140 u32 len, vlan_tag_flags, last_frag, mss;
5141 u16 prod, ring_prod;
5144 if (unlikely(bnx2_tx_avail(bp) < (skb_shinfo(skb)->nr_frags + 1))) {
5145 netif_stop_queue(dev);
5146 printk(KERN_ERR PFX "%s: BUG! Tx ring full when queue awake!\n",
5149 return NETDEV_TX_BUSY;
5151 len = skb_headlen(skb);
5153 ring_prod = TX_RING_IDX(prod);
5156 if (skb->ip_summed == CHECKSUM_PARTIAL) {
5157 vlan_tag_flags |= TX_BD_FLAGS_TCP_UDP_CKSUM;
5160 if (bp->vlgrp != 0 && vlan_tx_tag_present(skb)) {
5162 (TX_BD_FLAGS_VLAN_TAG | (vlan_tx_tag_get(skb) << 16));
5164 if ((mss = skb_shinfo(skb)->gso_size)) {
5165 u32 tcp_opt_len, ip_tcp_len;
5168 vlan_tag_flags |= TX_BD_FLAGS_SW_LSO;
5170 tcp_opt_len = tcp_optlen(skb);
5172 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6) {
5173 u32 tcp_off = skb_transport_offset(skb) -
5174 sizeof(struct ipv6hdr) - ETH_HLEN;
5176 vlan_tag_flags |= ((tcp_opt_len >> 2) << 8) |
5177 TX_BD_FLAGS_SW_FLAGS;
5178 if (likely(tcp_off == 0))
5179 vlan_tag_flags &= ~TX_BD_FLAGS_TCP6_OFF0_MSK;
5182 vlan_tag_flags |= ((tcp_off & 0x3) <<
5183 TX_BD_FLAGS_TCP6_OFF0_SHL) |
5184 ((tcp_off & 0x10) <<
5185 TX_BD_FLAGS_TCP6_OFF4_SHL);
5186 mss |= (tcp_off & 0xc) << TX_BD_TCP6_OFF2_SHL;
5189 if (skb_header_cloned(skb) &&
5190 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5192 return NETDEV_TX_OK;
5195 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5199 iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
5200 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5204 if (tcp_opt_len || (iph->ihl > 5)) {
5205 vlan_tag_flags |= ((iph->ihl - 5) +
5206 (tcp_opt_len >> 2)) << 8;
5212 mapping = pci_map_single(bp->pdev, skb->data, len, PCI_DMA_TODEVICE);
5214 tx_buf = &bp->tx_buf_ring[ring_prod];
5216 pci_unmap_addr_set(tx_buf, mapping, mapping);
5218 txbd = &bp->tx_desc_ring[ring_prod];
5220 txbd->tx_bd_haddr_hi = (u64) mapping >> 32;
5221 txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff;
5222 txbd->tx_bd_mss_nbytes = len | (mss << 16);
5223 txbd->tx_bd_vlan_tag_flags = vlan_tag_flags | TX_BD_FLAGS_START;
5225 last_frag = skb_shinfo(skb)->nr_frags;
5227 for (i = 0; i < last_frag; i++) {
5228 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5230 prod = NEXT_TX_BD(prod);
5231 ring_prod = TX_RING_IDX(prod);
5232 txbd = &bp->tx_desc_ring[ring_prod];
5235 mapping = pci_map_page(bp->pdev, frag->page, frag->page_offset,
5236 len, PCI_DMA_TODEVICE);
5237 pci_unmap_addr_set(&bp->tx_buf_ring[ring_prod],
5240 txbd->tx_bd_haddr_hi = (u64) mapping >> 32;
5241 txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff;
5242 txbd->tx_bd_mss_nbytes = len | (mss << 16);
5243 txbd->tx_bd_vlan_tag_flags = vlan_tag_flags;
5246 txbd->tx_bd_vlan_tag_flags |= TX_BD_FLAGS_END;
5248 prod = NEXT_TX_BD(prod);
5249 bp->tx_prod_bseq += skb->len;
5251 REG_WR16(bp, bp->tx_bidx_addr, prod);
5252 REG_WR(bp, bp->tx_bseq_addr, bp->tx_prod_bseq);
5257 dev->trans_start = jiffies;
5259 if (unlikely(bnx2_tx_avail(bp) <= MAX_SKB_FRAGS)) {
5260 netif_stop_queue(dev);
5261 if (bnx2_tx_avail(bp) > bp->tx_wake_thresh)
5262 netif_wake_queue(dev);
5265 return NETDEV_TX_OK;
5268 /* Called with rtnl_lock */
5270 bnx2_close(struct net_device *dev)
5272 struct bnx2 *bp = netdev_priv(dev);
5275 /* Calling flush_scheduled_work() may deadlock because
5276 * linkwatch_event() may be on the workqueue and it will try to get
5277 * the rtnl_lock which we are holding.
5279 while (bp->in_reset_task)
5282 bnx2_disable_int_sync(bp);
5283 napi_disable(&bp->napi);
5284 del_timer_sync(&bp->timer);
5285 if (bp->flags & NO_WOL_FLAG)
5286 reset_code = BNX2_DRV_MSG_CODE_UNLOAD_LNK_DN;
5288 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
5290 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
5291 bnx2_reset_chip(bp, reset_code);
5296 netif_carrier_off(bp->dev);
5297 bnx2_set_power_state(bp, PCI_D3hot);
5301 #define GET_NET_STATS64(ctr) \
5302 (unsigned long) ((unsigned long) (ctr##_hi) << 32) + \
5303 (unsigned long) (ctr##_lo)
5305 #define GET_NET_STATS32(ctr) \
5308 #if (BITS_PER_LONG == 64)
5309 #define GET_NET_STATS GET_NET_STATS64
5311 #define GET_NET_STATS GET_NET_STATS32
5314 static struct net_device_stats *
5315 bnx2_get_stats(struct net_device *dev)
5317 struct bnx2 *bp = netdev_priv(dev);
5318 struct statistics_block *stats_blk = bp->stats_blk;
5319 struct net_device_stats *net_stats = &bp->net_stats;
5321 if (bp->stats_blk == NULL) {
5324 net_stats->rx_packets =
5325 GET_NET_STATS(stats_blk->stat_IfHCInUcastPkts) +
5326 GET_NET_STATS(stats_blk->stat_IfHCInMulticastPkts) +
5327 GET_NET_STATS(stats_blk->stat_IfHCInBroadcastPkts);
5329 net_stats->tx_packets =
5330 GET_NET_STATS(stats_blk->stat_IfHCOutUcastPkts) +
5331 GET_NET_STATS(stats_blk->stat_IfHCOutMulticastPkts) +
5332 GET_NET_STATS(stats_blk->stat_IfHCOutBroadcastPkts);
5334 net_stats->rx_bytes =
5335 GET_NET_STATS(stats_blk->stat_IfHCInOctets);
5337 net_stats->tx_bytes =
5338 GET_NET_STATS(stats_blk->stat_IfHCOutOctets);
5340 net_stats->multicast =
5341 GET_NET_STATS(stats_blk->stat_IfHCOutMulticastPkts);
5343 net_stats->collisions =
5344 (unsigned long) stats_blk->stat_EtherStatsCollisions;
5346 net_stats->rx_length_errors =
5347 (unsigned long) (stats_blk->stat_EtherStatsUndersizePkts +
5348 stats_blk->stat_EtherStatsOverrsizePkts);
5350 net_stats->rx_over_errors =
5351 (unsigned long) stats_blk->stat_IfInMBUFDiscards;
5353 net_stats->rx_frame_errors =
5354 (unsigned long) stats_blk->stat_Dot3StatsAlignmentErrors;
5356 net_stats->rx_crc_errors =
5357 (unsigned long) stats_blk->stat_Dot3StatsFCSErrors;
5359 net_stats->rx_errors = net_stats->rx_length_errors +
5360 net_stats->rx_over_errors + net_stats->rx_frame_errors +
5361 net_stats->rx_crc_errors;
5363 net_stats->tx_aborted_errors =
5364 (unsigned long) (stats_blk->stat_Dot3StatsExcessiveCollisions +
5365 stats_blk->stat_Dot3StatsLateCollisions);
5367 if ((CHIP_NUM(bp) == CHIP_NUM_5706) ||
5368 (CHIP_ID(bp) == CHIP_ID_5708_A0))
5369 net_stats->tx_carrier_errors = 0;
5371 net_stats->tx_carrier_errors =
5373 stats_blk->stat_Dot3StatsCarrierSenseErrors;
5376 net_stats->tx_errors =
5378 stats_blk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors
5380 net_stats->tx_aborted_errors +
5381 net_stats->tx_carrier_errors;
5383 net_stats->rx_missed_errors =
5384 (unsigned long) (stats_blk->stat_IfInMBUFDiscards +
5385 stats_blk->stat_FwRxDrop);
5390 /* All ethtool functions called with rtnl_lock */
5393 bnx2_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
5395 struct bnx2 *bp = netdev_priv(dev);
5396 int support_serdes = 0, support_copper = 0;
5398 cmd->supported = SUPPORTED_Autoneg;
5399 if (bp->phy_flags & REMOTE_PHY_CAP_FLAG) {
5402 } else if (bp->phy_port == PORT_FIBRE)
5407 if (support_serdes) {
5408 cmd->supported |= SUPPORTED_1000baseT_Full |
5410 if (bp->phy_flags & PHY_2_5G_CAPABLE_FLAG)
5411 cmd->supported |= SUPPORTED_2500baseX_Full;
5414 if (support_copper) {
5415 cmd->supported |= SUPPORTED_10baseT_Half |
5416 SUPPORTED_10baseT_Full |
5417 SUPPORTED_100baseT_Half |
5418 SUPPORTED_100baseT_Full |
5419 SUPPORTED_1000baseT_Full |
5424 spin_lock_bh(&bp->phy_lock);
5425 cmd->port = bp->phy_port;
5426 cmd->advertising = bp->advertising;
5428 if (bp->autoneg & AUTONEG_SPEED) {
5429 cmd->autoneg = AUTONEG_ENABLE;
5432 cmd->autoneg = AUTONEG_DISABLE;
5435 if (netif_carrier_ok(dev)) {
5436 cmd->speed = bp->line_speed;
5437 cmd->duplex = bp->duplex;
5443 spin_unlock_bh(&bp->phy_lock);
5445 cmd->transceiver = XCVR_INTERNAL;
5446 cmd->phy_address = bp->phy_addr;
5452 bnx2_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
5454 struct bnx2 *bp = netdev_priv(dev);
5455 u8 autoneg = bp->autoneg;
5456 u8 req_duplex = bp->req_duplex;
5457 u16 req_line_speed = bp->req_line_speed;
5458 u32 advertising = bp->advertising;
5461 spin_lock_bh(&bp->phy_lock);
5463 if (cmd->port != PORT_TP && cmd->port != PORT_FIBRE)
5464 goto err_out_unlock;
5466 if (cmd->port != bp->phy_port && !(bp->phy_flags & REMOTE_PHY_CAP_FLAG))
5467 goto err_out_unlock;
5469 if (cmd->autoneg == AUTONEG_ENABLE) {
5470 autoneg |= AUTONEG_SPEED;
5472 cmd->advertising &= ETHTOOL_ALL_COPPER_SPEED;
5474 /* allow advertising 1 speed */
5475 if ((cmd->advertising == ADVERTISED_10baseT_Half) ||
5476 (cmd->advertising == ADVERTISED_10baseT_Full) ||
5477 (cmd->advertising == ADVERTISED_100baseT_Half) ||
5478 (cmd->advertising == ADVERTISED_100baseT_Full)) {
5480 if (cmd->port == PORT_FIBRE)
5481 goto err_out_unlock;
5483 advertising = cmd->advertising;
5485 } else if (cmd->advertising == ADVERTISED_2500baseX_Full) {
5486 if (!(bp->phy_flags & PHY_2_5G_CAPABLE_FLAG) ||
5487 (cmd->port == PORT_TP))
5488 goto err_out_unlock;
5489 } else if (cmd->advertising == ADVERTISED_1000baseT_Full)
5490 advertising = cmd->advertising;
5491 else if (cmd->advertising == ADVERTISED_1000baseT_Half)
5492 goto err_out_unlock;
5494 if (cmd->port == PORT_FIBRE)
5495 advertising = ETHTOOL_ALL_FIBRE_SPEED;
5497 advertising = ETHTOOL_ALL_COPPER_SPEED;
5499 advertising |= ADVERTISED_Autoneg;
5502 if (cmd->port == PORT_FIBRE) {
5503 if ((cmd->speed != SPEED_1000 &&
5504 cmd->speed != SPEED_2500) ||
5505 (cmd->duplex != DUPLEX_FULL))
5506 goto err_out_unlock;
5508 if (cmd->speed == SPEED_2500 &&
5509 !(bp->phy_flags & PHY_2_5G_CAPABLE_FLAG))
5510 goto err_out_unlock;
5512 else if (cmd->speed == SPEED_1000 || cmd->speed == SPEED_2500)
5513 goto err_out_unlock;
5515 autoneg &= ~AUTONEG_SPEED;
5516 req_line_speed = cmd->speed;
5517 req_duplex = cmd->duplex;
5521 bp->autoneg = autoneg;
5522 bp->advertising = advertising;
5523 bp->req_line_speed = req_line_speed;
5524 bp->req_duplex = req_duplex;
5526 err = bnx2_setup_phy(bp, cmd->port);
5529 spin_unlock_bh(&bp->phy_lock);
5535 bnx2_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
5537 struct bnx2 *bp = netdev_priv(dev);
5539 strcpy(info->driver, DRV_MODULE_NAME);
5540 strcpy(info->version, DRV_MODULE_VERSION);
5541 strcpy(info->bus_info, pci_name(bp->pdev));
5542 strcpy(info->fw_version, bp->fw_version);
5545 #define BNX2_REGDUMP_LEN (32 * 1024)
5548 bnx2_get_regs_len(struct net_device *dev)
5550 return BNX2_REGDUMP_LEN;
5554 bnx2_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *_p)
5556 u32 *p = _p, i, offset;
5558 struct bnx2 *bp = netdev_priv(dev);
5559 u32 reg_boundaries[] = { 0x0000, 0x0098, 0x0400, 0x045c,
5560 0x0800, 0x0880, 0x0c00, 0x0c10,
5561 0x0c30, 0x0d08, 0x1000, 0x101c,
5562 0x1040, 0x1048, 0x1080, 0x10a4,
5563 0x1400, 0x1490, 0x1498, 0x14f0,
5564 0x1500, 0x155c, 0x1580, 0x15dc,
5565 0x1600, 0x1658, 0x1680, 0x16d8,
5566 0x1800, 0x1820, 0x1840, 0x1854,
5567 0x1880, 0x1894, 0x1900, 0x1984,
5568 0x1c00, 0x1c0c, 0x1c40, 0x1c54,
5569 0x1c80, 0x1c94, 0x1d00, 0x1d84,
5570 0x2000, 0x2030, 0x23c0, 0x2400,
5571 0x2800, 0x2820, 0x2830, 0x2850,
5572 0x2b40, 0x2c10, 0x2fc0, 0x3058,
5573 0x3c00, 0x3c94, 0x4000, 0x4010,
5574 0x4080, 0x4090, 0x43c0, 0x4458,
5575 0x4c00, 0x4c18, 0x4c40, 0x4c54,
5576 0x4fc0, 0x5010, 0x53c0, 0x5444,
5577 0x5c00, 0x5c18, 0x5c80, 0x5c90,
5578 0x5fc0, 0x6000, 0x6400, 0x6428,
5579 0x6800, 0x6848, 0x684c, 0x6860,
5580 0x6888, 0x6910, 0x8000 };
5584 memset(p, 0, BNX2_REGDUMP_LEN);
5586 if (!netif_running(bp->dev))
5590 offset = reg_boundaries[0];
5592 while (offset < BNX2_REGDUMP_LEN) {
5593 *p++ = REG_RD(bp, offset);
5595 if (offset == reg_boundaries[i + 1]) {
5596 offset = reg_boundaries[i + 2];
5597 p = (u32 *) (orig_p + offset);
5604 bnx2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
5606 struct bnx2 *bp = netdev_priv(dev);
5608 if (bp->flags & NO_WOL_FLAG) {
5613 wol->supported = WAKE_MAGIC;
5615 wol->wolopts = WAKE_MAGIC;
5619 memset(&wol->sopass, 0, sizeof(wol->sopass));
5623 bnx2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
5625 struct bnx2 *bp = netdev_priv(dev);
5627 if (wol->wolopts & ~WAKE_MAGIC)
5630 if (wol->wolopts & WAKE_MAGIC) {
5631 if (bp->flags & NO_WOL_FLAG)
5643 bnx2_nway_reset(struct net_device *dev)
5645 struct bnx2 *bp = netdev_priv(dev);
5648 if (!(bp->autoneg & AUTONEG_SPEED)) {
5652 spin_lock_bh(&bp->phy_lock);
5654 if (bp->phy_flags & REMOTE_PHY_CAP_FLAG) {
5657 rc = bnx2_setup_remote_phy(bp, bp->phy_port);
5658 spin_unlock_bh(&bp->phy_lock);
5662 /* Force a link down visible on the other side */
5663 if (bp->phy_flags & PHY_SERDES_FLAG) {
5664 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
5665 spin_unlock_bh(&bp->phy_lock);
5669 spin_lock_bh(&bp->phy_lock);
5671 bp->current_interval = SERDES_AN_TIMEOUT;
5672 bp->serdes_an_pending = 1;
5673 mod_timer(&bp->timer, jiffies + bp->current_interval);
5676 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
5677 bmcr &= ~BMCR_LOOPBACK;
5678 bnx2_write_phy(bp, bp->mii_bmcr, bmcr | BMCR_ANRESTART | BMCR_ANENABLE);
5680 spin_unlock_bh(&bp->phy_lock);
5686 bnx2_get_eeprom_len(struct net_device *dev)
5688 struct bnx2 *bp = netdev_priv(dev);
5690 if (bp->flash_info == NULL)
5693 return (int) bp->flash_size;
5697 bnx2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
5700 struct bnx2 *bp = netdev_priv(dev);
5703 /* parameters already validated in ethtool_get_eeprom */
5705 rc = bnx2_nvram_read(bp, eeprom->offset, eebuf, eeprom->len);
5711 bnx2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
5714 struct bnx2 *bp = netdev_priv(dev);
5717 /* parameters already validated in ethtool_set_eeprom */
5719 rc = bnx2_nvram_write(bp, eeprom->offset, eebuf, eeprom->len);
5725 bnx2_get_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
5727 struct bnx2 *bp = netdev_priv(dev);
5729 memset(coal, 0, sizeof(struct ethtool_coalesce));
5731 coal->rx_coalesce_usecs = bp->rx_ticks;
5732 coal->rx_max_coalesced_frames = bp->rx_quick_cons_trip;
5733 coal->rx_coalesce_usecs_irq = bp->rx_ticks_int;
5734 coal->rx_max_coalesced_frames_irq = bp->rx_quick_cons_trip_int;
5736 coal->tx_coalesce_usecs = bp->tx_ticks;
5737 coal->tx_max_coalesced_frames = bp->tx_quick_cons_trip;
5738 coal->tx_coalesce_usecs_irq = bp->tx_ticks_int;
5739 coal->tx_max_coalesced_frames_irq = bp->tx_quick_cons_trip_int;
5741 coal->stats_block_coalesce_usecs = bp->stats_ticks;
5747 bnx2_set_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
5749 struct bnx2 *bp = netdev_priv(dev);
5751 bp->rx_ticks = (u16) coal->rx_coalesce_usecs;
5752 if (bp->rx_ticks > 0x3ff) bp->rx_ticks = 0x3ff;
5754 bp->rx_quick_cons_trip = (u16) coal->rx_max_coalesced_frames;
5755 if (bp->rx_quick_cons_trip > 0xff) bp->rx_quick_cons_trip = 0xff;
5757 bp->rx_ticks_int = (u16) coal->rx_coalesce_usecs_irq;
5758 if (bp->rx_ticks_int > 0x3ff) bp->rx_ticks_int = 0x3ff;
5760 bp->rx_quick_cons_trip_int = (u16) coal->rx_max_coalesced_frames_irq;
5761 if (bp->rx_quick_cons_trip_int > 0xff)
5762 bp->rx_quick_cons_trip_int = 0xff;
5764 bp->tx_ticks = (u16) coal->tx_coalesce_usecs;
5765 if (bp->tx_ticks > 0x3ff) bp->tx_ticks = 0x3ff;
5767 bp->tx_quick_cons_trip = (u16) coal->tx_max_coalesced_frames;
5768 if (bp->tx_quick_cons_trip > 0xff) bp->tx_quick_cons_trip = 0xff;
5770 bp->tx_ticks_int = (u16) coal->tx_coalesce_usecs_irq;
5771 if (bp->tx_ticks_int > 0x3ff) bp->tx_ticks_int = 0x3ff;
5773 bp->tx_quick_cons_trip_int = (u16) coal->tx_max_coalesced_frames_irq;
5774 if (bp->tx_quick_cons_trip_int > 0xff) bp->tx_quick_cons_trip_int =
5777 bp->stats_ticks = coal->stats_block_coalesce_usecs;
5778 if (CHIP_NUM(bp) == CHIP_NUM_5708) {
5779 if (bp->stats_ticks != 0 && bp->stats_ticks != USEC_PER_SEC)
5780 bp->stats_ticks = USEC_PER_SEC;
5782 if (bp->stats_ticks > BNX2_HC_STATS_TICKS_HC_STAT_TICKS)
5783 bp->stats_ticks = BNX2_HC_STATS_TICKS_HC_STAT_TICKS;
5784 bp->stats_ticks &= BNX2_HC_STATS_TICKS_HC_STAT_TICKS;
5786 if (netif_running(bp->dev)) {
5787 bnx2_netif_stop(bp);
5789 bnx2_netif_start(bp);
5796 bnx2_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
5798 struct bnx2 *bp = netdev_priv(dev);
5800 ering->rx_max_pending = MAX_TOTAL_RX_DESC_CNT;
5801 ering->rx_mini_max_pending = 0;
5802 ering->rx_jumbo_max_pending = 0;
5804 ering->rx_pending = bp->rx_ring_size;
5805 ering->rx_mini_pending = 0;
5806 ering->rx_jumbo_pending = 0;
5808 ering->tx_max_pending = MAX_TX_DESC_CNT;
5809 ering->tx_pending = bp->tx_ring_size;
5813 bnx2_change_ring_size(struct bnx2 *bp, u32 rx, u32 tx)
5815 if (netif_running(bp->dev)) {
5816 bnx2_netif_stop(bp);
5817 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_RESET);
5822 bnx2_set_rx_ring_size(bp, rx);
5823 bp->tx_ring_size = tx;
5825 if (netif_running(bp->dev)) {
5828 rc = bnx2_alloc_mem(bp);
5832 bnx2_netif_start(bp);
5838 bnx2_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
5840 struct bnx2 *bp = netdev_priv(dev);
5843 if ((ering->rx_pending > MAX_TOTAL_RX_DESC_CNT) ||
5844 (ering->tx_pending > MAX_TX_DESC_CNT) ||
5845 (ering->tx_pending <= MAX_SKB_FRAGS)) {
5849 rc = bnx2_change_ring_size(bp, ering->rx_pending, ering->tx_pending);
5854 bnx2_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
5856 struct bnx2 *bp = netdev_priv(dev);
5858 epause->autoneg = ((bp->autoneg & AUTONEG_FLOW_CTRL) != 0);
5859 epause->rx_pause = ((bp->flow_ctrl & FLOW_CTRL_RX) != 0);
5860 epause->tx_pause = ((bp->flow_ctrl & FLOW_CTRL_TX) != 0);
5864 bnx2_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
5866 struct bnx2 *bp = netdev_priv(dev);
5868 bp->req_flow_ctrl = 0;
5869 if (epause->rx_pause)
5870 bp->req_flow_ctrl |= FLOW_CTRL_RX;
5871 if (epause->tx_pause)
5872 bp->req_flow_ctrl |= FLOW_CTRL_TX;
5874 if (epause->autoneg) {
5875 bp->autoneg |= AUTONEG_FLOW_CTRL;
5878 bp->autoneg &= ~AUTONEG_FLOW_CTRL;
5881 spin_lock_bh(&bp->phy_lock);
5883 bnx2_setup_phy(bp, bp->phy_port);
5885 spin_unlock_bh(&bp->phy_lock);
5891 bnx2_get_rx_csum(struct net_device *dev)
5893 struct bnx2 *bp = netdev_priv(dev);
5899 bnx2_set_rx_csum(struct net_device *dev, u32 data)
5901 struct bnx2 *bp = netdev_priv(dev);
5908 bnx2_set_tso(struct net_device *dev, u32 data)
5910 struct bnx2 *bp = netdev_priv(dev);
5913 dev->features |= NETIF_F_TSO | NETIF_F_TSO_ECN;
5914 if (CHIP_NUM(bp) == CHIP_NUM_5709)
5915 dev->features |= NETIF_F_TSO6;
5917 dev->features &= ~(NETIF_F_TSO | NETIF_F_TSO6 |
5922 #define BNX2_NUM_STATS 46
5925 char string[ETH_GSTRING_LEN];
5926 } bnx2_stats_str_arr[BNX2_NUM_STATS] = {
5928 { "rx_error_bytes" },
5930 { "tx_error_bytes" },
5931 { "rx_ucast_packets" },
5932 { "rx_mcast_packets" },
5933 { "rx_bcast_packets" },
5934 { "tx_ucast_packets" },
5935 { "tx_mcast_packets" },
5936 { "tx_bcast_packets" },
5937 { "tx_mac_errors" },
5938 { "tx_carrier_errors" },
5939 { "rx_crc_errors" },
5940 { "rx_align_errors" },
5941 { "tx_single_collisions" },
5942 { "tx_multi_collisions" },
5944 { "tx_excess_collisions" },
5945 { "tx_late_collisions" },
5946 { "tx_total_collisions" },
5949 { "rx_undersize_packets" },
5950 { "rx_oversize_packets" },
5951 { "rx_64_byte_packets" },
5952 { "rx_65_to_127_byte_packets" },
5953 { "rx_128_to_255_byte_packets" },
5954 { "rx_256_to_511_byte_packets" },
5955 { "rx_512_to_1023_byte_packets" },
5956 { "rx_1024_to_1522_byte_packets" },
5957 { "rx_1523_to_9022_byte_packets" },
5958 { "tx_64_byte_packets" },
5959 { "tx_65_to_127_byte_packets" },
5960 { "tx_128_to_255_byte_packets" },
5961 { "tx_256_to_511_byte_packets" },
5962 { "tx_512_to_1023_byte_packets" },
5963 { "tx_1024_to_1522_byte_packets" },
5964 { "tx_1523_to_9022_byte_packets" },
5965 { "rx_xon_frames" },
5966 { "rx_xoff_frames" },
5967 { "tx_xon_frames" },
5968 { "tx_xoff_frames" },
5969 { "rx_mac_ctrl_frames" },
5970 { "rx_filtered_packets" },
5972 { "rx_fw_discards" },
5975 #define STATS_OFFSET32(offset_name) (offsetof(struct statistics_block, offset_name) / 4)
5977 static const unsigned long bnx2_stats_offset_arr[BNX2_NUM_STATS] = {
5978 STATS_OFFSET32(stat_IfHCInOctets_hi),
5979 STATS_OFFSET32(stat_IfHCInBadOctets_hi),
5980 STATS_OFFSET32(stat_IfHCOutOctets_hi),
5981 STATS_OFFSET32(stat_IfHCOutBadOctets_hi),
5982 STATS_OFFSET32(stat_IfHCInUcastPkts_hi),
5983 STATS_OFFSET32(stat_IfHCInMulticastPkts_hi),
5984 STATS_OFFSET32(stat_IfHCInBroadcastPkts_hi),
5985 STATS_OFFSET32(stat_IfHCOutUcastPkts_hi),
5986 STATS_OFFSET32(stat_IfHCOutMulticastPkts_hi),
5987 STATS_OFFSET32(stat_IfHCOutBroadcastPkts_hi),
5988 STATS_OFFSET32(stat_emac_tx_stat_dot3statsinternalmactransmiterrors),
5989 STATS_OFFSET32(stat_Dot3StatsCarrierSenseErrors),
5990 STATS_OFFSET32(stat_Dot3StatsFCSErrors),
5991 STATS_OFFSET32(stat_Dot3StatsAlignmentErrors),
5992 STATS_OFFSET32(stat_Dot3StatsSingleCollisionFrames),
5993 STATS_OFFSET32(stat_Dot3StatsMultipleCollisionFrames),
5994 STATS_OFFSET32(stat_Dot3StatsDeferredTransmissions),
5995 STATS_OFFSET32(stat_Dot3StatsExcessiveCollisions),
5996 STATS_OFFSET32(stat_Dot3StatsLateCollisions),
5997 STATS_OFFSET32(stat_EtherStatsCollisions),
5998 STATS_OFFSET32(stat_EtherStatsFragments),
5999 STATS_OFFSET32(stat_EtherStatsJabbers),
6000 STATS_OFFSET32(stat_EtherStatsUndersizePkts),
6001 STATS_OFFSET32(stat_EtherStatsOverrsizePkts),
6002 STATS_OFFSET32(stat_EtherStatsPktsRx64Octets),
6003 STATS_OFFSET32(stat_EtherStatsPktsRx65Octetsto127Octets),
6004 STATS_OFFSET32(stat_EtherStatsPktsRx128Octetsto255Octets),
6005 STATS_OFFSET32(stat_EtherStatsPktsRx256Octetsto511Octets),
6006 STATS_OFFSET32(stat_EtherStatsPktsRx512Octetsto1023Octets),
6007 STATS_OFFSET32(stat_EtherStatsPktsRx1024Octetsto1522Octets),
6008 STATS_OFFSET32(stat_EtherStatsPktsRx1523Octetsto9022Octets),
6009 STATS_OFFSET32(stat_EtherStatsPktsTx64Octets),
6010 STATS_OFFSET32(stat_EtherStatsPktsTx65Octetsto127Octets),
6011 STATS_OFFSET32(stat_EtherStatsPktsTx128Octetsto255Octets),
6012 STATS_OFFSET32(stat_EtherStatsPktsTx256Octetsto511Octets),
6013 STATS_OFFSET32(stat_EtherStatsPktsTx512Octetsto1023Octets),
6014 STATS_OFFSET32(stat_EtherStatsPktsTx1024Octetsto1522Octets),
6015 STATS_OFFSET32(stat_EtherStatsPktsTx1523Octetsto9022Octets),
6016 STATS_OFFSET32(stat_XonPauseFramesReceived),
6017 STATS_OFFSET32(stat_XoffPauseFramesReceived),
6018 STATS_OFFSET32(stat_OutXonSent),
6019 STATS_OFFSET32(stat_OutXoffSent),
6020 STATS_OFFSET32(stat_MacControlFramesReceived),
6021 STATS_OFFSET32(stat_IfInFramesL2FilterDiscards),
6022 STATS_OFFSET32(stat_IfInMBUFDiscards),
6023 STATS_OFFSET32(stat_FwRxDrop),
6026 /* stat_IfHCInBadOctets and stat_Dot3StatsCarrierSenseErrors are
6027 * skipped because of errata.
6029 static u8 bnx2_5706_stats_len_arr[BNX2_NUM_STATS] = {
6030 8,0,8,8,8,8,8,8,8,8,
6031 4,0,4,4,4,4,4,4,4,4,
6032 4,4,4,4,4,4,4,4,4,4,
6033 4,4,4,4,4,4,4,4,4,4,
6037 static u8 bnx2_5708_stats_len_arr[BNX2_NUM_STATS] = {
6038 8,0,8,8,8,8,8,8,8,8,
6039 4,4,4,4,4,4,4,4,4,4,
6040 4,4,4,4,4,4,4,4,4,4,
6041 4,4,4,4,4,4,4,4,4,4,
6045 #define BNX2_NUM_TESTS 6
6048 char string[ETH_GSTRING_LEN];
6049 } bnx2_tests_str_arr[BNX2_NUM_TESTS] = {
6050 { "register_test (offline)" },
6051 { "memory_test (offline)" },
6052 { "loopback_test (offline)" },
6053 { "nvram_test (online)" },
6054 { "interrupt_test (online)" },
6055 { "link_test (online)" },
6059 bnx2_get_sset_count(struct net_device *dev, int sset)
6063 return BNX2_NUM_TESTS;
6065 return BNX2_NUM_STATS;
6072 bnx2_self_test(struct net_device *dev, struct ethtool_test *etest, u64 *buf)
6074 struct bnx2 *bp = netdev_priv(dev);
6076 memset(buf, 0, sizeof(u64) * BNX2_NUM_TESTS);
6077 if (etest->flags & ETH_TEST_FL_OFFLINE) {
6080 bnx2_netif_stop(bp);
6081 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_DIAG);
6084 if (bnx2_test_registers(bp) != 0) {
6086 etest->flags |= ETH_TEST_FL_FAILED;
6088 if (bnx2_test_memory(bp) != 0) {
6090 etest->flags |= ETH_TEST_FL_FAILED;
6092 if ((buf[2] = bnx2_test_loopback(bp)) != 0)
6093 etest->flags |= ETH_TEST_FL_FAILED;
6095 if (!netif_running(bp->dev)) {
6096 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_RESET);
6100 bnx2_netif_start(bp);
6103 /* wait for link up */
6104 for (i = 0; i < 7; i++) {
6107 msleep_interruptible(1000);
6111 if (bnx2_test_nvram(bp) != 0) {
6113 etest->flags |= ETH_TEST_FL_FAILED;
6115 if (bnx2_test_intr(bp) != 0) {
6117 etest->flags |= ETH_TEST_FL_FAILED;
6120 if (bnx2_test_link(bp) != 0) {
6122 etest->flags |= ETH_TEST_FL_FAILED;
6128 bnx2_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
6130 switch (stringset) {
6132 memcpy(buf, bnx2_stats_str_arr,
6133 sizeof(bnx2_stats_str_arr));
6136 memcpy(buf, bnx2_tests_str_arr,
6137 sizeof(bnx2_tests_str_arr));
6143 bnx2_get_ethtool_stats(struct net_device *dev,
6144 struct ethtool_stats *stats, u64 *buf)
6146 struct bnx2 *bp = netdev_priv(dev);
6148 u32 *hw_stats = (u32 *) bp->stats_blk;
6149 u8 *stats_len_arr = NULL;
6151 if (hw_stats == NULL) {
6152 memset(buf, 0, sizeof(u64) * BNX2_NUM_STATS);
6156 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
6157 (CHIP_ID(bp) == CHIP_ID_5706_A1) ||
6158 (CHIP_ID(bp) == CHIP_ID_5706_A2) ||
6159 (CHIP_ID(bp) == CHIP_ID_5708_A0))
6160 stats_len_arr = bnx2_5706_stats_len_arr;
6162 stats_len_arr = bnx2_5708_stats_len_arr;
6164 for (i = 0; i < BNX2_NUM_STATS; i++) {
6165 if (stats_len_arr[i] == 0) {
6166 /* skip this counter */
6170 if (stats_len_arr[i] == 4) {
6171 /* 4-byte counter */
6173 *(hw_stats + bnx2_stats_offset_arr[i]);
6176 /* 8-byte counter */
6177 buf[i] = (((u64) *(hw_stats +
6178 bnx2_stats_offset_arr[i])) << 32) +
6179 *(hw_stats + bnx2_stats_offset_arr[i] + 1);
6184 bnx2_phys_id(struct net_device *dev, u32 data)
6186 struct bnx2 *bp = netdev_priv(dev);
6193 save = REG_RD(bp, BNX2_MISC_CFG);
6194 REG_WR(bp, BNX2_MISC_CFG, BNX2_MISC_CFG_LEDMODE_MAC);
6196 for (i = 0; i < (data * 2); i++) {
6198 REG_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE);
6201 REG_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE |
6202 BNX2_EMAC_LED_1000MB_OVERRIDE |
6203 BNX2_EMAC_LED_100MB_OVERRIDE |
6204 BNX2_EMAC_LED_10MB_OVERRIDE |
6205 BNX2_EMAC_LED_TRAFFIC_OVERRIDE |
6206 BNX2_EMAC_LED_TRAFFIC);
6208 msleep_interruptible(500);
6209 if (signal_pending(current))
6212 REG_WR(bp, BNX2_EMAC_LED, 0);
6213 REG_WR(bp, BNX2_MISC_CFG, save);
6218 bnx2_set_tx_csum(struct net_device *dev, u32 data)
6220 struct bnx2 *bp = netdev_priv(dev);
6222 if (CHIP_NUM(bp) == CHIP_NUM_5709)
6223 return (ethtool_op_set_tx_ipv6_csum(dev, data));
6225 return (ethtool_op_set_tx_csum(dev, data));
6228 static const struct ethtool_ops bnx2_ethtool_ops = {
6229 .get_settings = bnx2_get_settings,
6230 .set_settings = bnx2_set_settings,
6231 .get_drvinfo = bnx2_get_drvinfo,
6232 .get_regs_len = bnx2_get_regs_len,
6233 .get_regs = bnx2_get_regs,
6234 .get_wol = bnx2_get_wol,
6235 .set_wol = bnx2_set_wol,
6236 .nway_reset = bnx2_nway_reset,
6237 .get_link = ethtool_op_get_link,
6238 .get_eeprom_len = bnx2_get_eeprom_len,
6239 .get_eeprom = bnx2_get_eeprom,
6240 .set_eeprom = bnx2_set_eeprom,
6241 .get_coalesce = bnx2_get_coalesce,
6242 .set_coalesce = bnx2_set_coalesce,
6243 .get_ringparam = bnx2_get_ringparam,
6244 .set_ringparam = bnx2_set_ringparam,
6245 .get_pauseparam = bnx2_get_pauseparam,
6246 .set_pauseparam = bnx2_set_pauseparam,
6247 .get_rx_csum = bnx2_get_rx_csum,
6248 .set_rx_csum = bnx2_set_rx_csum,
6249 .set_tx_csum = bnx2_set_tx_csum,
6250 .set_sg = ethtool_op_set_sg,
6251 .set_tso = bnx2_set_tso,
6252 .self_test = bnx2_self_test,
6253 .get_strings = bnx2_get_strings,
6254 .phys_id = bnx2_phys_id,
6255 .get_ethtool_stats = bnx2_get_ethtool_stats,
6256 .get_sset_count = bnx2_get_sset_count,
6259 /* Called with rtnl_lock */
6261 bnx2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
6263 struct mii_ioctl_data *data = if_mii(ifr);
6264 struct bnx2 *bp = netdev_priv(dev);
6269 data->phy_id = bp->phy_addr;
6275 if (bp->phy_flags & REMOTE_PHY_CAP_FLAG)
6278 if (!netif_running(dev))
6281 spin_lock_bh(&bp->phy_lock);
6282 err = bnx2_read_phy(bp, data->reg_num & 0x1f, &mii_regval);
6283 spin_unlock_bh(&bp->phy_lock);
6285 data->val_out = mii_regval;
6291 if (!capable(CAP_NET_ADMIN))
6294 if (bp->phy_flags & REMOTE_PHY_CAP_FLAG)
6297 if (!netif_running(dev))
6300 spin_lock_bh(&bp->phy_lock);
6301 err = bnx2_write_phy(bp, data->reg_num & 0x1f, data->val_in);
6302 spin_unlock_bh(&bp->phy_lock);
6313 /* Called with rtnl_lock */
6315 bnx2_change_mac_addr(struct net_device *dev, void *p)
6317 struct sockaddr *addr = p;
6318 struct bnx2 *bp = netdev_priv(dev);
6320 if (!is_valid_ether_addr(addr->sa_data))
6323 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
6324 if (netif_running(dev))
6325 bnx2_set_mac_addr(bp);
6330 /* Called with rtnl_lock */
6332 bnx2_change_mtu(struct net_device *dev, int new_mtu)
6334 struct bnx2 *bp = netdev_priv(dev);
6336 if (((new_mtu + ETH_HLEN) > MAX_ETHERNET_JUMBO_PACKET_SIZE) ||
6337 ((new_mtu + ETH_HLEN) < MIN_ETHERNET_PACKET_SIZE))
6341 return (bnx2_change_ring_size(bp, bp->rx_ring_size, bp->tx_ring_size));
6344 #if defined(HAVE_POLL_CONTROLLER) || defined(CONFIG_NET_POLL_CONTROLLER)
6346 poll_bnx2(struct net_device *dev)
6348 struct bnx2 *bp = netdev_priv(dev);
6350 disable_irq(bp->pdev->irq);
6351 bnx2_interrupt(bp->pdev->irq, dev);
6352 enable_irq(bp->pdev->irq);
6356 static void __devinit
6357 bnx2_get_5709_media(struct bnx2 *bp)
6359 u32 val = REG_RD(bp, BNX2_MISC_DUAL_MEDIA_CTRL);
6360 u32 bond_id = val & BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID;
6363 if (bond_id == BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_C)
6365 else if (bond_id == BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_S) {
6366 bp->phy_flags |= PHY_SERDES_FLAG;
6370 if (val & BNX2_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE)
6371 strap = (val & BNX2_MISC_DUAL_MEDIA_CTRL_PHY_CTRL) >> 21;
6373 strap = (val & BNX2_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP) >> 8;
6375 if (PCI_FUNC(bp->pdev->devfn) == 0) {
6380 bp->phy_flags |= PHY_SERDES_FLAG;
6388 bp->phy_flags |= PHY_SERDES_FLAG;
6394 static void __devinit
6395 bnx2_get_pci_speed(struct bnx2 *bp)
6399 reg = REG_RD(bp, BNX2_PCICFG_MISC_STATUS);
6400 if (reg & BNX2_PCICFG_MISC_STATUS_PCIX_DET) {
6403 bp->flags |= PCIX_FLAG;
6405 clkreg = REG_RD(bp, BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS);
6407 clkreg &= BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET;
6409 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ:
6410 bp->bus_speed_mhz = 133;
6413 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ:
6414 bp->bus_speed_mhz = 100;
6417 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ:
6418 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ:
6419 bp->bus_speed_mhz = 66;
6422 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ:
6423 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ:
6424 bp->bus_speed_mhz = 50;
6427 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW:
6428 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ:
6429 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ:
6430 bp->bus_speed_mhz = 33;
6435 if (reg & BNX2_PCICFG_MISC_STATUS_M66EN)
6436 bp->bus_speed_mhz = 66;
6438 bp->bus_speed_mhz = 33;
6441 if (reg & BNX2_PCICFG_MISC_STATUS_32BIT_DET)
6442 bp->flags |= PCI_32BIT_FLAG;
6446 static int __devinit
6447 bnx2_init_board(struct pci_dev *pdev, struct net_device *dev)
6450 unsigned long mem_len;
6453 u64 dma_mask, persist_dma_mask;
6455 SET_NETDEV_DEV(dev, &pdev->dev);
6456 bp = netdev_priv(dev);
6461 /* enable device (incl. PCI PM wakeup), and bus-mastering */
6462 rc = pci_enable_device(pdev);
6464 dev_err(&pdev->dev, "Cannot enable PCI device, aborting.\n");
6468 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
6470 "Cannot find PCI device base address, aborting.\n");
6472 goto err_out_disable;
6475 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
6477 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting.\n");
6478 goto err_out_disable;
6481 pci_set_master(pdev);
6483 bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
6484 if (bp->pm_cap == 0) {
6486 "Cannot find power management capability, aborting.\n");
6488 goto err_out_release;
6494 spin_lock_init(&bp->phy_lock);
6495 spin_lock_init(&bp->indirect_lock);
6496 INIT_WORK(&bp->reset_task, bnx2_reset_task);
6498 dev->base_addr = dev->mem_start = pci_resource_start(pdev, 0);
6499 mem_len = MB_GET_CID_ADDR(TX_TSS_CID + 1);
6500 dev->mem_end = dev->mem_start + mem_len;
6501 dev->irq = pdev->irq;
6503 bp->regview = ioremap_nocache(dev->base_addr, mem_len);
6506 dev_err(&pdev->dev, "Cannot map register space, aborting.\n");
6508 goto err_out_release;
6511 /* Configure byte swap and enable write to the reg_window registers.
6512 * Rely on CPU to do target byte swapping on big endian systems
6513 * The chip's target access swapping will not swap all accesses
6515 pci_write_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG,
6516 BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
6517 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP);
6519 bnx2_set_power_state(bp, PCI_D0);
6521 bp->chip_id = REG_RD(bp, BNX2_MISC_ID);
6523 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
6524 if (pci_find_capability(pdev, PCI_CAP_ID_EXP) == 0) {
6526 "Cannot find PCIE capability, aborting.\n");
6530 bp->flags |= PCIE_FLAG;
6532 bp->pcix_cap = pci_find_capability(pdev, PCI_CAP_ID_PCIX);
6533 if (bp->pcix_cap == 0) {
6535 "Cannot find PCIX capability, aborting.\n");
6541 if (CHIP_ID(bp) != CHIP_ID_5706_A0 && CHIP_ID(bp) != CHIP_ID_5706_A1) {
6542 if (pci_find_capability(pdev, PCI_CAP_ID_MSI))
6543 bp->flags |= MSI_CAP_FLAG;
6546 /* 5708 cannot support DMA addresses > 40-bit. */
6547 if (CHIP_NUM(bp) == CHIP_NUM_5708)
6548 persist_dma_mask = dma_mask = DMA_40BIT_MASK;
6550 persist_dma_mask = dma_mask = DMA_64BIT_MASK;
6552 /* Configure DMA attributes. */
6553 if (pci_set_dma_mask(pdev, dma_mask) == 0) {
6554 dev->features |= NETIF_F_HIGHDMA;
6555 rc = pci_set_consistent_dma_mask(pdev, persist_dma_mask);
6558 "pci_set_consistent_dma_mask failed, aborting.\n");
6561 } else if ((rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK)) != 0) {
6562 dev_err(&pdev->dev, "System does not support DMA, aborting.\n");
6566 if (!(bp->flags & PCIE_FLAG))
6567 bnx2_get_pci_speed(bp);
6569 /* 5706A0 may falsely detect SERR and PERR. */
6570 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
6571 reg = REG_RD(bp, PCI_COMMAND);
6572 reg &= ~(PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
6573 REG_WR(bp, PCI_COMMAND, reg);
6575 else if ((CHIP_ID(bp) == CHIP_ID_5706_A1) &&
6576 !(bp->flags & PCIX_FLAG)) {
6579 "5706 A1 can only be used in a PCIX bus, aborting.\n");
6583 bnx2_init_nvram(bp);
6585 reg = REG_RD_IND(bp, BNX2_SHM_HDR_SIGNATURE);
6587 if ((reg & BNX2_SHM_HDR_SIGNATURE_SIG_MASK) ==
6588 BNX2_SHM_HDR_SIGNATURE_SIG) {
6589 u32 off = PCI_FUNC(pdev->devfn) << 2;
6591 bp->shmem_base = REG_RD_IND(bp, BNX2_SHM_HDR_ADDR_0 + off);
6593 bp->shmem_base = HOST_VIEW_SHMEM_BASE;
6595 /* Get the permanent MAC address. First we need to make sure the
6596 * firmware is actually running.
6598 reg = REG_RD_IND(bp, bp->shmem_base + BNX2_DEV_INFO_SIGNATURE);
6600 if ((reg & BNX2_DEV_INFO_SIGNATURE_MAGIC_MASK) !=
6601 BNX2_DEV_INFO_SIGNATURE_MAGIC) {
6602 dev_err(&pdev->dev, "Firmware not running, aborting.\n");
6607 reg = REG_RD_IND(bp, bp->shmem_base + BNX2_DEV_INFO_BC_REV);
6608 for (i = 0, j = 0; i < 3; i++) {
6611 num = (u8) (reg >> (24 - (i * 8)));
6612 for (k = 100, skip0 = 1; k >= 1; num %= k, k /= 10) {
6613 if (num >= k || !skip0 || k == 1) {
6614 bp->fw_version[j++] = (num / k) + '0';
6619 bp->fw_version[j++] = '.';
6621 reg = REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_FEATURE);
6622 if (reg & BNX2_PORT_FEATURE_WOL_ENABLED)
6625 if (reg & BNX2_PORT_FEATURE_ASF_ENABLED) {
6626 bp->flags |= ASF_ENABLE_FLAG;
6628 for (i = 0; i < 30; i++) {
6629 reg = REG_RD_IND(bp, bp->shmem_base +
6630 BNX2_BC_STATE_CONDITION);
6631 if (reg & BNX2_CONDITION_MFW_RUN_MASK)
6636 reg = REG_RD_IND(bp, bp->shmem_base + BNX2_BC_STATE_CONDITION);
6637 reg &= BNX2_CONDITION_MFW_RUN_MASK;
6638 if (reg != BNX2_CONDITION_MFW_RUN_UNKNOWN &&
6639 reg != BNX2_CONDITION_MFW_RUN_NONE) {
6641 u32 addr = REG_RD_IND(bp, bp->shmem_base + BNX2_MFW_VER_PTR);
6643 bp->fw_version[j++] = ' ';
6644 for (i = 0; i < 3; i++) {
6645 reg = REG_RD_IND(bp, addr + i * 4);
6647 memcpy(&bp->fw_version[j], ®, 4);
6652 reg = REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_HW_CFG_MAC_UPPER);
6653 bp->mac_addr[0] = (u8) (reg >> 8);
6654 bp->mac_addr[1] = (u8) reg;
6656 reg = REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_HW_CFG_MAC_LOWER);
6657 bp->mac_addr[2] = (u8) (reg >> 24);
6658 bp->mac_addr[3] = (u8) (reg >> 16);
6659 bp->mac_addr[4] = (u8) (reg >> 8);
6660 bp->mac_addr[5] = (u8) reg;
6662 bp->rx_offset = sizeof(struct l2_fhdr) + 2;
6664 bp->tx_ring_size = MAX_TX_DESC_CNT;
6665 bnx2_set_rx_ring_size(bp, 255);
6669 bp->tx_quick_cons_trip_int = 20;
6670 bp->tx_quick_cons_trip = 20;
6671 bp->tx_ticks_int = 80;
6674 bp->rx_quick_cons_trip_int = 6;
6675 bp->rx_quick_cons_trip = 6;
6676 bp->rx_ticks_int = 18;
6679 bp->stats_ticks = USEC_PER_SEC & BNX2_HC_STATS_TICKS_HC_STAT_TICKS;
6681 bp->timer_interval = HZ;
6682 bp->current_interval = HZ;
6686 /* Disable WOL support if we are running on a SERDES chip. */
6687 if (CHIP_NUM(bp) == CHIP_NUM_5709)
6688 bnx2_get_5709_media(bp);
6689 else if (CHIP_BOND_ID(bp) & CHIP_BOND_ID_SERDES_BIT)
6690 bp->phy_flags |= PHY_SERDES_FLAG;
6692 bp->phy_port = PORT_TP;
6693 if (bp->phy_flags & PHY_SERDES_FLAG) {
6694 bp->phy_port = PORT_FIBRE;
6695 reg = REG_RD_IND(bp, bp->shmem_base +
6696 BNX2_SHARED_HW_CFG_CONFIG);
6697 if (!(reg & BNX2_SHARED_HW_CFG_GIG_LINK_ON_VAUX)) {
6698 bp->flags |= NO_WOL_FLAG;
6701 if (CHIP_NUM(bp) != CHIP_NUM_5706) {
6703 if (reg & BNX2_SHARED_HW_CFG_PHY_2_5G)
6704 bp->phy_flags |= PHY_2_5G_CAPABLE_FLAG;
6706 bnx2_init_remote_phy(bp);
6708 } else if (CHIP_NUM(bp) == CHIP_NUM_5706 ||
6709 CHIP_NUM(bp) == CHIP_NUM_5708)
6710 bp->phy_flags |= PHY_CRC_FIX_FLAG;
6711 else if (CHIP_NUM(bp) == CHIP_NUM_5709 &&
6712 (CHIP_REV(bp) == CHIP_REV_Ax ||
6713 CHIP_REV(bp) == CHIP_REV_Bx))
6714 bp->phy_flags |= PHY_DIS_EARLY_DAC_FLAG;
6716 if ((CHIP_ID(bp) == CHIP_ID_5708_A0) ||
6717 (CHIP_ID(bp) == CHIP_ID_5708_B0) ||
6718 (CHIP_ID(bp) == CHIP_ID_5708_B1)) {
6719 bp->flags |= NO_WOL_FLAG;
6723 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
6724 bp->tx_quick_cons_trip_int =
6725 bp->tx_quick_cons_trip;
6726 bp->tx_ticks_int = bp->tx_ticks;
6727 bp->rx_quick_cons_trip_int =
6728 bp->rx_quick_cons_trip;
6729 bp->rx_ticks_int = bp->rx_ticks;
6730 bp->comp_prod_trip_int = bp->comp_prod_trip;
6731 bp->com_ticks_int = bp->com_ticks;
6732 bp->cmd_ticks_int = bp->cmd_ticks;
6735 /* Disable MSI on 5706 if AMD 8132 bridge is found.
6737 * MSI is defined to be 32-bit write. The 5706 does 64-bit MSI writes
6738 * with byte enables disabled on the unused 32-bit word. This is legal
6739 * but causes problems on the AMD 8132 which will eventually stop
6740 * responding after a while.
6742 * AMD believes this incompatibility is unique to the 5706, and
6743 * prefers to locally disable MSI rather than globally disabling it.
6745 if (CHIP_NUM(bp) == CHIP_NUM_5706 && disable_msi == 0) {
6746 struct pci_dev *amd_8132 = NULL;
6748 while ((amd_8132 = pci_get_device(PCI_VENDOR_ID_AMD,
6749 PCI_DEVICE_ID_AMD_8132_BRIDGE,
6752 if (amd_8132->revision >= 0x10 &&
6753 amd_8132->revision <= 0x13) {
6755 pci_dev_put(amd_8132);
6761 bnx2_set_default_link(bp);
6762 bp->req_flow_ctrl = FLOW_CTRL_RX | FLOW_CTRL_TX;
6764 init_timer(&bp->timer);
6765 bp->timer.expires = RUN_AT(bp->timer_interval);
6766 bp->timer.data = (unsigned long) bp;
6767 bp->timer.function = bnx2_timer;
6773 iounmap(bp->regview);
6778 pci_release_regions(pdev);
6781 pci_disable_device(pdev);
6782 pci_set_drvdata(pdev, NULL);
6788 static char * __devinit
6789 bnx2_bus_string(struct bnx2 *bp, char *str)
6793 if (bp->flags & PCIE_FLAG) {
6794 s += sprintf(s, "PCI Express");
6796 s += sprintf(s, "PCI");
6797 if (bp->flags & PCIX_FLAG)
6798 s += sprintf(s, "-X");
6799 if (bp->flags & PCI_32BIT_FLAG)
6800 s += sprintf(s, " 32-bit");
6802 s += sprintf(s, " 64-bit");
6803 s += sprintf(s, " %dMHz", bp->bus_speed_mhz);
6808 static int __devinit
6809 bnx2_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
6811 static int version_printed = 0;
6812 struct net_device *dev = NULL;
6816 DECLARE_MAC_BUF(mac);
6818 if (version_printed++ == 0)
6819 printk(KERN_INFO "%s", version);
6821 /* dev zeroed in init_etherdev */
6822 dev = alloc_etherdev(sizeof(*bp));
6827 rc = bnx2_init_board(pdev, dev);
6833 dev->open = bnx2_open;
6834 dev->hard_start_xmit = bnx2_start_xmit;
6835 dev->stop = bnx2_close;
6836 dev->get_stats = bnx2_get_stats;
6837 dev->set_multicast_list = bnx2_set_rx_mode;
6838 dev->do_ioctl = bnx2_ioctl;
6839 dev->set_mac_address = bnx2_change_mac_addr;
6840 dev->change_mtu = bnx2_change_mtu;
6841 dev->tx_timeout = bnx2_tx_timeout;
6842 dev->watchdog_timeo = TX_TIMEOUT;
6844 dev->vlan_rx_register = bnx2_vlan_rx_register;
6846 dev->ethtool_ops = &bnx2_ethtool_ops;
6848 bp = netdev_priv(dev);
6849 netif_napi_add(dev, &bp->napi, bnx2_poll, 64);
6851 #if defined(HAVE_POLL_CONTROLLER) || defined(CONFIG_NET_POLL_CONTROLLER)
6852 dev->poll_controller = poll_bnx2;
6855 pci_set_drvdata(pdev, dev);
6857 memcpy(dev->dev_addr, bp->mac_addr, 6);
6858 memcpy(dev->perm_addr, bp->mac_addr, 6);
6859 bp->name = board_info[ent->driver_data].name;
6861 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
6862 if (CHIP_NUM(bp) == CHIP_NUM_5709)
6863 dev->features |= NETIF_F_IPV6_CSUM;
6866 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
6868 dev->features |= NETIF_F_TSO | NETIF_F_TSO_ECN;
6869 if (CHIP_NUM(bp) == CHIP_NUM_5709)
6870 dev->features |= NETIF_F_TSO6;
6872 if ((rc = register_netdev(dev))) {
6873 dev_err(&pdev->dev, "Cannot register net device\n");
6875 iounmap(bp->regview);
6876 pci_release_regions(pdev);
6877 pci_disable_device(pdev);
6878 pci_set_drvdata(pdev, NULL);
6883 printk(KERN_INFO "%s: %s (%c%d) %s found at mem %lx, "
6884 "IRQ %d, node addr %s\n",
6887 ((CHIP_ID(bp) & 0xf000) >> 12) + 'A',
6888 ((CHIP_ID(bp) & 0x0ff0) >> 4),
6889 bnx2_bus_string(bp, str),
6891 bp->pdev->irq, print_mac(mac, dev->dev_addr));
6896 static void __devexit
6897 bnx2_remove_one(struct pci_dev *pdev)
6899 struct net_device *dev = pci_get_drvdata(pdev);
6900 struct bnx2 *bp = netdev_priv(dev);
6902 flush_scheduled_work();
6904 unregister_netdev(dev);
6907 iounmap(bp->regview);
6910 pci_release_regions(pdev);
6911 pci_disable_device(pdev);
6912 pci_set_drvdata(pdev, NULL);
6916 bnx2_suspend(struct pci_dev *pdev, pm_message_t state)
6918 struct net_device *dev = pci_get_drvdata(pdev);
6919 struct bnx2 *bp = netdev_priv(dev);
6922 /* PCI register 4 needs to be saved whether netif_running() or not.
6923 * MSI address and data need to be saved if using MSI and
6926 pci_save_state(pdev);
6927 if (!netif_running(dev))
6930 flush_scheduled_work();
6931 bnx2_netif_stop(bp);
6932 netif_device_detach(dev);
6933 del_timer_sync(&bp->timer);
6934 if (bp->flags & NO_WOL_FLAG)
6935 reset_code = BNX2_DRV_MSG_CODE_UNLOAD_LNK_DN;
6937 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
6939 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
6940 bnx2_reset_chip(bp, reset_code);
6942 bnx2_set_power_state(bp, pci_choose_state(pdev, state));
6947 bnx2_resume(struct pci_dev *pdev)
6949 struct net_device *dev = pci_get_drvdata(pdev);
6950 struct bnx2 *bp = netdev_priv(dev);
6952 pci_restore_state(pdev);
6953 if (!netif_running(dev))
6956 bnx2_set_power_state(bp, PCI_D0);
6957 netif_device_attach(dev);
6959 bnx2_netif_start(bp);
6963 static struct pci_driver bnx2_pci_driver = {
6964 .name = DRV_MODULE_NAME,
6965 .id_table = bnx2_pci_tbl,
6966 .probe = bnx2_init_one,
6967 .remove = __devexit_p(bnx2_remove_one),
6968 .suspend = bnx2_suspend,
6969 .resume = bnx2_resume,
6972 static int __init bnx2_init(void)
6974 return pci_register_driver(&bnx2_pci_driver);
6977 static void __exit bnx2_cleanup(void)
6979 pci_unregister_driver(&bnx2_pci_driver);
6982 module_init(bnx2_init);
6983 module_exit(bnx2_cleanup);