1 /* bnx2x_hsi.h: Broadcom Everest network driver.
3 * Copyright (c) 2007-2008 Broadcom Corporation
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
15 /****************************************************************************
16 * Shared HW configuration *
17 ****************************************************************************/
18 struct shared_hw_cfg { /* NVRAM Offset */
19 /* Up to 16 bytes of NULL-terminated string */
20 u8 part_num[16]; /* 0x104 */
22 u32 config; /* 0x114 */
23 #define SHARED_HW_CFG_MDIO_VOLTAGE_MASK 0x00000001
24 #define SHARED_HW_CFG_MDIO_VOLTAGE_SHIFT 0
25 #define SHARED_HW_CFG_MDIO_VOLTAGE_1_2V 0x00000000
26 #define SHARED_HW_CFG_MDIO_VOLTAGE_2_5V 0x00000001
27 #define SHARED_HW_CFG_MCP_RST_ON_CORE_RST_EN 0x00000002
29 #define SHARED_HW_CFG_PORT_SWAP 0x00000004
31 #define SHARED_HW_CFG_BEACON_WOL_EN 0x00000008
33 #define SHARED_HW_CFG_MFW_SELECT_MASK 0x00000700
34 #define SHARED_HW_CFG_MFW_SELECT_SHIFT 8
35 /* Whatever MFW found in NVM
36 (if multiple found, priority order is: NC-SI, UMP, IPMI) */
37 #define SHARED_HW_CFG_MFW_SELECT_DEFAULT 0x00000000
38 #define SHARED_HW_CFG_MFW_SELECT_NC_SI 0x00000100
39 #define SHARED_HW_CFG_MFW_SELECT_UMP 0x00000200
40 #define SHARED_HW_CFG_MFW_SELECT_IPMI 0x00000300
41 /* Use SPIO4 as an arbiter between: 0-NC_SI, 1-IPMI
42 (can only be used when an add-in board, not BMC, pulls-down SPIO4) */
43 #define SHARED_HW_CFG_MFW_SELECT_SPIO4_NC_SI_IPMI 0x00000400
44 /* Use SPIO4 as an arbiter between: 0-UMP, 1-IPMI
45 (can only be used when an add-in board, not BMC, pulls-down SPIO4) */
46 #define SHARED_HW_CFG_MFW_SELECT_SPIO4_UMP_IPMI 0x00000500
47 /* Use SPIO4 as an arbiter between: 0-NC-SI, 1-UMP
48 (can only be used when an add-in board, not BMC, pulls-down SPIO4) */
49 #define SHARED_HW_CFG_MFW_SELECT_SPIO4_NC_SI_UMP 0x00000600
51 #define SHARED_HW_CFG_LED_MODE_MASK 0x000f0000
52 #define SHARED_HW_CFG_LED_MODE_SHIFT 16
53 #define SHARED_HW_CFG_LED_MAC1 0x00000000
54 #define SHARED_HW_CFG_LED_PHY1 0x00010000
55 #define SHARED_HW_CFG_LED_PHY2 0x00020000
56 #define SHARED_HW_CFG_LED_PHY3 0x00030000
57 #define SHARED_HW_CFG_LED_MAC2 0x00040000
58 #define SHARED_HW_CFG_LED_PHY4 0x00050000
59 #define SHARED_HW_CFG_LED_PHY5 0x00060000
60 #define SHARED_HW_CFG_LED_PHY6 0x00070000
61 #define SHARED_HW_CFG_LED_MAC3 0x00080000
62 #define SHARED_HW_CFG_LED_PHY7 0x00090000
63 #define SHARED_HW_CFG_LED_PHY9 0x000a0000
64 #define SHARED_HW_CFG_LED_PHY11 0x000b0000
65 #define SHARED_HW_CFG_LED_MAC4 0x000c0000
66 #define SHARED_HW_CFG_LED_PHY8 0x000d0000
68 #define SHARED_HW_CFG_AN_ENABLE_MASK 0x3f000000
69 #define SHARED_HW_CFG_AN_ENABLE_SHIFT 24
70 #define SHARED_HW_CFG_AN_ENABLE_CL37 0x01000000
71 #define SHARED_HW_CFG_AN_ENABLE_CL73 0x02000000
72 #define SHARED_HW_CFG_AN_ENABLE_BAM 0x04000000
73 #define SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION 0x08000000
74 #define SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT 0x10000000
75 #define SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY 0x20000000
77 u32 config2; /* 0x118 */
78 /* one time auto detect grace period (in sec) */
79 #define SHARED_HW_CFG_GRACE_PERIOD_MASK 0x000000ff
80 #define SHARED_HW_CFG_GRACE_PERIOD_SHIFT 0
82 #define SHARED_HW_CFG_PCIE_GEN2_ENABLED 0x00000100
84 /* The default value for the core clock is 250MHz and it is
85 achieved by setting the clock change to 4 */
86 #define SHARED_HW_CFG_CLOCK_CHANGE_MASK 0x00000e00
87 #define SHARED_HW_CFG_CLOCK_CHANGE_SHIFT 9
89 #define SHARED_HW_CFG_SMBUS_TIMING_100KHZ 0x00000000
90 #define SHARED_HW_CFG_SMBUS_TIMING_400KHZ 0x00001000
92 #define SHARED_HW_CFG_HIDE_PORT1 0x00002000
94 u32 power_dissipated; /* 0x11c */
95 #define SHARED_HW_CFG_POWER_DIS_CMN_MASK 0xff000000
96 #define SHARED_HW_CFG_POWER_DIS_CMN_SHIFT 24
98 #define SHARED_HW_CFG_POWER_MGNT_SCALE_MASK 0x00ff0000
99 #define SHARED_HW_CFG_POWER_MGNT_SCALE_SHIFT 16
100 #define SHARED_HW_CFG_POWER_MGNT_UNKNOWN_SCALE 0x00000000
101 #define SHARED_HW_CFG_POWER_MGNT_DOT_1_WATT 0x00010000
102 #define SHARED_HW_CFG_POWER_MGNT_DOT_01_WATT 0x00020000
103 #define SHARED_HW_CFG_POWER_MGNT_DOT_001_WATT 0x00030000
105 u32 ump_nc_si_config; /* 0x120 */
106 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MASK 0x00000003
107 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_SHIFT 0
108 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MAC 0x00000000
109 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_PHY 0x00000001
110 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MII 0x00000000
111 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_RMII 0x00000002
113 #define SHARED_HW_CFG_UMP_NC_SI_NUM_DEVS_MASK 0x00000f00
114 #define SHARED_HW_CFG_UMP_NC_SI_NUM_DEVS_SHIFT 8
116 #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_MASK 0x00ff0000
117 #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_SHIFT 16
118 #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_NONE 0x00000000
119 #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_BCM5221 0x00010000
121 u32 board; /* 0x124 */
122 #define SHARED_HW_CFG_BOARD_TYPE_MASK 0x0000ffff
123 #define SHARED_HW_CFG_BOARD_TYPE_SHIFT 0
124 #define SHARED_HW_CFG_BOARD_TYPE_NONE 0x00000000
125 #define SHARED_HW_CFG_BOARD_TYPE_BCM957710T1000 0x00000001
126 #define SHARED_HW_CFG_BOARD_TYPE_BCM957710T1001 0x00000002
127 #define SHARED_HW_CFG_BOARD_TYPE_BCM957710T1002G 0x00000003
128 #define SHARED_HW_CFG_BOARD_TYPE_BCM957710T1004G 0x00000004
129 #define SHARED_HW_CFG_BOARD_TYPE_BCM957710T1007G 0x00000005
130 #define SHARED_HW_CFG_BOARD_TYPE_BCM957710T1015G 0x00000006
131 #define SHARED_HW_CFG_BOARD_TYPE_BCM957710A1020G 0x00000007
132 #define SHARED_HW_CFG_BOARD_TYPE_BCM957710T1003G 0x00000008
133 #define SHARED_HW_CFG_BOARD_TYPE_BCM957710A1022G 0x00000009
134 #define SHARED_HW_CFG_BOARD_TYPE_BCM957710A1021G 0x0000000a
135 #define SHARED_HW_CFG_BOARD_TYPE_BCM957710A1023G 0x0000000b
136 #define SHARED_HW_CFG_BOARD_TYPE_BCM957710A1033G 0x0000000c
137 #define SHARED_HW_CFG_BOARD_TYPE_BCM957711T1101 0x0000000d
138 #define SHARED_HW_CFG_BOARD_TYPE_BCM957711ET1201 0x0000000e
139 #define SHARED_HW_CFG_BOARD_TYPE_BCM957711A1133G 0x0000000f
140 #define SHARED_HW_CFG_BOARD_TYPE_BCM957711EA1233G 0x00000010
142 #define SHARED_HW_CFG_BOARD_VER_MASK 0xffff0000
143 #define SHARED_HW_CFG_BOARD_VER_SHIFT 16
144 #define SHARED_HW_CFG_BOARD_MAJOR_VER_MASK 0xf0000000
145 #define SHARED_HW_CFG_BOARD_MAJOR_VER_SHIFT 28
146 #define SHARED_HW_CFG_BOARD_MINOR_VER_MASK 0x0f000000
147 #define SHARED_HW_CFG_BOARD_MINOR_VER_SHIFT 24
148 #define SHARED_HW_CFG_BOARD_REV_MASK 0x00ff0000
149 #define SHARED_HW_CFG_BOARD_REV_SHIFT 16
151 u32 reserved; /* 0x128 */
156 /****************************************************************************
157 * Port HW configuration *
158 ****************************************************************************/
159 struct port_hw_cfg { /* port 0: 0x12c port 1: 0x2bc */
162 #define PORT_HW_CFG_PCI_VENDOR_ID_MASK 0xffff0000
163 #define PORT_HW_CFG_PCI_DEVICE_ID_MASK 0x0000ffff
166 #define PORT_HW_CFG_PCI_SUBSYS_DEVICE_ID_MASK 0xffff0000
167 #define PORT_HW_CFG_PCI_SUBSYS_VENDOR_ID_MASK 0x0000ffff
169 u32 power_dissipated;
170 #define PORT_HW_CFG_POWER_DIS_D3_MASK 0xff000000
171 #define PORT_HW_CFG_POWER_DIS_D3_SHIFT 24
172 #define PORT_HW_CFG_POWER_DIS_D2_MASK 0x00ff0000
173 #define PORT_HW_CFG_POWER_DIS_D2_SHIFT 16
174 #define PORT_HW_CFG_POWER_DIS_D1_MASK 0x0000ff00
175 #define PORT_HW_CFG_POWER_DIS_D1_SHIFT 8
176 #define PORT_HW_CFG_POWER_DIS_D0_MASK 0x000000ff
177 #define PORT_HW_CFG_POWER_DIS_D0_SHIFT 0
180 #define PORT_HW_CFG_POWER_CONS_D3_MASK 0xff000000
181 #define PORT_HW_CFG_POWER_CONS_D3_SHIFT 24
182 #define PORT_HW_CFG_POWER_CONS_D2_MASK 0x00ff0000
183 #define PORT_HW_CFG_POWER_CONS_D2_SHIFT 16
184 #define PORT_HW_CFG_POWER_CONS_D1_MASK 0x0000ff00
185 #define PORT_HW_CFG_POWER_CONS_D1_SHIFT 8
186 #define PORT_HW_CFG_POWER_CONS_D0_MASK 0x000000ff
187 #define PORT_HW_CFG_POWER_CONS_D0_SHIFT 0
190 #define PORT_HW_CFG_UPPERMAC_MASK 0x0000ffff
191 #define PORT_HW_CFG_UPPERMAC_SHIFT 0
194 u32 iscsi_mac_upper; /* Upper 16 bits are always zeroes */
197 u32 rdma_mac_upper; /* Upper 16 bits are always zeroes */
201 /* for external PHY, or forced mode or during AN */
202 #define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_MASK 0xffff0000
203 #define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_SHIFT 16
205 #define PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_MASK 0x0000ffff
206 #define PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_SHIFT 0
208 u16 serdes_tx_driver_pre_emphasis[16];
209 u16 serdes_rx_driver_equalizer[16];
211 u32 xgxs_config_lane0;
212 u32 xgxs_config_lane1;
213 u32 xgxs_config_lane2;
214 u32 xgxs_config_lane3;
215 /* for external PHY, or forced mode or during AN */
216 #define PORT_HW_CFG_XGXS_TX_DRV_PRE_EMPHASIS_MASK 0xffff0000
217 #define PORT_HW_CFG_XGXS_TX_DRV_PRE_EMPHASIS_SHIFT 16
219 #define PORT_HW_CFG_XGXS_RX_DRV_EQUALIZER_MASK 0x0000ffff
220 #define PORT_HW_CFG_XGXS_RX_DRV_EQUALIZER_SHIFT 0
222 u16 xgxs_tx_driver_pre_emphasis_lane0[16];
223 u16 xgxs_tx_driver_pre_emphasis_lane1[16];
224 u16 xgxs_tx_driver_pre_emphasis_lane2[16];
225 u16 xgxs_tx_driver_pre_emphasis_lane3[16];
227 u16 xgxs_rx_driver_equalizer_lane0[16];
228 u16 xgxs_rx_driver_equalizer_lane1[16];
229 u16 xgxs_rx_driver_equalizer_lane2[16];
230 u16 xgxs_rx_driver_equalizer_lane3[16];
233 #define PORT_HW_CFG_LANE_SWAP_CFG_MASK 0x0000ffff
234 #define PORT_HW_CFG_LANE_SWAP_CFG_SHIFT 0
235 #define PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK 0x000000ff
236 #define PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT 0
237 #define PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK 0x0000ff00
238 #define PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT 8
239 #define PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK 0x0000c000
240 #define PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT 14
242 #define PORT_HW_CFG_LANE_SWAP_CFG_01230123 0x00001b1b
244 #define PORT_HW_CFG_LANE_SWAP_CFG_01233210 0x00001be4
246 #define PORT_HW_CFG_LANE_SWAP_CFG_31203120 0x0000d8d8
248 #define PORT_HW_CFG_LANE_SWAP_CFG_32103210 0x0000e4e4
250 u32 external_phy_config;
251 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_MASK 0xff000000
252 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_SHIFT 24
253 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT 0x00000000
254 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482 0x01000000
255 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN 0xff000000
257 #define PORT_HW_CFG_SERDES_EXT_PHY_ADDR_MASK 0x00ff0000
258 #define PORT_HW_CFG_SERDES_EXT_PHY_ADDR_SHIFT 16
260 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK 0x0000ff00
261 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SHIFT 8
262 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT 0x00000000
263 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8071 0x00000100
264 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072 0x00000200
265 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073 0x00000300
266 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705 0x00000400
267 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706 0x00000500
268 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8276 0x00000600
269 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481 0x00000700
270 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101 0x00000800
271 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE 0x0000fd00
272 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN 0x0000ff00
274 #define PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK 0x000000ff
275 #define PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT 0
277 u32 speed_capability_mask;
278 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK 0xffff0000
279 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_SHIFT 16
280 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL 0x00010000
281 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF 0x00020000
282 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF 0x00040000
283 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL 0x00080000
284 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_1G 0x00100000
285 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G 0x00200000
286 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10G 0x00400000
287 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_12G 0x00800000
288 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_12_5G 0x01000000
289 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_13G 0x02000000
290 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_15G 0x04000000
291 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_16G 0x08000000
292 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_RESERVED 0xf0000000
294 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_MASK 0x0000ffff
295 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_SHIFT 0
296 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10M_FULL 0x00000001
297 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10M_HALF 0x00000002
298 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_100M_HALF 0x00000004
299 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_100M_FULL 0x00000008
300 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_1G 0x00000010
301 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_2_5G 0x00000020
302 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10G 0x00000040
303 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_12G 0x00000080
304 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_12_5G 0x00000100
305 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_13G 0x00000200
306 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_15G 0x00000400
307 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_16G 0x00000800
308 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_RESERVED 0x0000f000
315 /****************************************************************************
316 * Shared Feature configuration *
317 ****************************************************************************/
318 struct shared_feat_cfg { /* NVRAM Offset */
320 u32 config; /* 0x450 */
321 #define SHARED_FEATURE_BMC_ECHO_MODE_EN 0x00000001
322 #define SHARED_FEATURE_MF_MODE_DISABLED 0x00000100
327 /****************************************************************************
328 * Port Feature configuration *
329 ****************************************************************************/
330 struct port_feat_cfg { /* port 0: 0x454 port 1: 0x4c8 */
333 #define PORT_FEATURE_BAR1_SIZE_MASK 0x0000000f
334 #define PORT_FEATURE_BAR1_SIZE_SHIFT 0
335 #define PORT_FEATURE_BAR1_SIZE_DISABLED 0x00000000
336 #define PORT_FEATURE_BAR1_SIZE_64K 0x00000001
337 #define PORT_FEATURE_BAR1_SIZE_128K 0x00000002
338 #define PORT_FEATURE_BAR1_SIZE_256K 0x00000003
339 #define PORT_FEATURE_BAR1_SIZE_512K 0x00000004
340 #define PORT_FEATURE_BAR1_SIZE_1M 0x00000005
341 #define PORT_FEATURE_BAR1_SIZE_2M 0x00000006
342 #define PORT_FEATURE_BAR1_SIZE_4M 0x00000007
343 #define PORT_FEATURE_BAR1_SIZE_8M 0x00000008
344 #define PORT_FEATURE_BAR1_SIZE_16M 0x00000009
345 #define PORT_FEATURE_BAR1_SIZE_32M 0x0000000a
346 #define PORT_FEATURE_BAR1_SIZE_64M 0x0000000b
347 #define PORT_FEATURE_BAR1_SIZE_128M 0x0000000c
348 #define PORT_FEATURE_BAR1_SIZE_256M 0x0000000d
349 #define PORT_FEATURE_BAR1_SIZE_512M 0x0000000e
350 #define PORT_FEATURE_BAR1_SIZE_1G 0x0000000f
351 #define PORT_FEATURE_BAR2_SIZE_MASK 0x000000f0
352 #define PORT_FEATURE_BAR2_SIZE_SHIFT 4
353 #define PORT_FEATURE_BAR2_SIZE_DISABLED 0x00000000
354 #define PORT_FEATURE_BAR2_SIZE_64K 0x00000010
355 #define PORT_FEATURE_BAR2_SIZE_128K 0x00000020
356 #define PORT_FEATURE_BAR2_SIZE_256K 0x00000030
357 #define PORT_FEATURE_BAR2_SIZE_512K 0x00000040
358 #define PORT_FEATURE_BAR2_SIZE_1M 0x00000050
359 #define PORT_FEATURE_BAR2_SIZE_2M 0x00000060
360 #define PORT_FEATURE_BAR2_SIZE_4M 0x00000070
361 #define PORT_FEATURE_BAR2_SIZE_8M 0x00000080
362 #define PORT_FEATURE_BAR2_SIZE_16M 0x00000090
363 #define PORT_FEATURE_BAR2_SIZE_32M 0x000000a0
364 #define PORT_FEATURE_BAR2_SIZE_64M 0x000000b0
365 #define PORT_FEATURE_BAR2_SIZE_128M 0x000000c0
366 #define PORT_FEATURE_BAR2_SIZE_256M 0x000000d0
367 #define PORT_FEATURE_BAR2_SIZE_512M 0x000000e0
368 #define PORT_FEATURE_BAR2_SIZE_1G 0x000000f0
369 #define PORT_FEATURE_EN_SIZE_MASK 0x07000000
370 #define PORT_FEATURE_EN_SIZE_SHIFT 24
371 #define PORT_FEATURE_WOL_ENABLED 0x01000000
372 #define PORT_FEATURE_MBA_ENABLED 0x02000000
373 #define PORT_FEATURE_MFW_ENABLED 0x04000000
376 /* Default is used when driver sets to "auto" mode */
377 #define PORT_FEATURE_WOL_DEFAULT_MASK 0x00000003
378 #define PORT_FEATURE_WOL_DEFAULT_SHIFT 0
379 #define PORT_FEATURE_WOL_DEFAULT_DISABLE 0x00000000
380 #define PORT_FEATURE_WOL_DEFAULT_MAGIC 0x00000001
381 #define PORT_FEATURE_WOL_DEFAULT_ACPI 0x00000002
382 #define PORT_FEATURE_WOL_DEFAULT_MAGIC_AND_ACPI 0x00000003
383 #define PORT_FEATURE_WOL_RES_PAUSE_CAP 0x00000004
384 #define PORT_FEATURE_WOL_RES_ASYM_PAUSE_CAP 0x00000008
385 #define PORT_FEATURE_WOL_ACPI_UPON_MGMT 0x00000010
388 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK 0x00000003
389 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_SHIFT 0
390 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE 0x00000000
391 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_RPL 0x00000001
392 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_BOOTP 0x00000002
393 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB 0x00000003
394 #define PORT_FEATURE_MBA_RES_PAUSE_CAP 0x00000100
395 #define PORT_FEATURE_MBA_RES_ASYM_PAUSE_CAP 0x00000200
396 #define PORT_FEATURE_MBA_SETUP_PROMPT_ENABLE 0x00000400
397 #define PORT_FEATURE_MBA_HOTKEY_CTRL_S 0x00000000
398 #define PORT_FEATURE_MBA_HOTKEY_CTRL_B 0x00000800
399 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_MASK 0x000ff000
400 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_SHIFT 12
401 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_DISABLED 0x00000000
402 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_2K 0x00001000
403 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_4K 0x00002000
404 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_8K 0x00003000
405 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_16K 0x00004000
406 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_32K 0x00005000
407 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_64K 0x00006000
408 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_128K 0x00007000
409 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_256K 0x00008000
410 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_512K 0x00009000
411 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_1M 0x0000a000
412 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_2M 0x0000b000
413 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_4M 0x0000c000
414 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_8M 0x0000d000
415 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_16M 0x0000e000
416 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_32M 0x0000f000
417 #define PORT_FEATURE_MBA_MSG_TIMEOUT_MASK 0x00f00000
418 #define PORT_FEATURE_MBA_MSG_TIMEOUT_SHIFT 20
419 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_MASK 0x03000000
420 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_SHIFT 24
421 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_AUTO 0x00000000
422 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_BBS 0x01000000
423 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT18H 0x02000000
424 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT19H 0x03000000
425 #define PORT_FEATURE_MBA_LINK_SPEED_MASK 0x3c000000
426 #define PORT_FEATURE_MBA_LINK_SPEED_SHIFT 26
427 #define PORT_FEATURE_MBA_LINK_SPEED_AUTO 0x00000000
428 #define PORT_FEATURE_MBA_LINK_SPEED_10HD 0x04000000
429 #define PORT_FEATURE_MBA_LINK_SPEED_10FD 0x08000000
430 #define PORT_FEATURE_MBA_LINK_SPEED_100HD 0x0c000000
431 #define PORT_FEATURE_MBA_LINK_SPEED_100FD 0x10000000
432 #define PORT_FEATURE_MBA_LINK_SPEED_1GBPS 0x14000000
433 #define PORT_FEATURE_MBA_LINK_SPEED_2_5GBPS 0x18000000
434 #define PORT_FEATURE_MBA_LINK_SPEED_10GBPS_CX4 0x1c000000
435 #define PORT_FEATURE_MBA_LINK_SPEED_10GBPS_KX4 0x20000000
436 #define PORT_FEATURE_MBA_LINK_SPEED_10GBPS_KR 0x24000000
437 #define PORT_FEATURE_MBA_LINK_SPEED_12GBPS 0x28000000
438 #define PORT_FEATURE_MBA_LINK_SPEED_12_5GBPS 0x2c000000
439 #define PORT_FEATURE_MBA_LINK_SPEED_13GBPS 0x30000000
440 #define PORT_FEATURE_MBA_LINK_SPEED_15GBPS 0x34000000
441 #define PORT_FEATURE_MBA_LINK_SPEED_16GBPS 0x38000000
444 #define PORT_FEATURE_BMC_LINK_OVERRIDE_DEFAULT 0x00000000
445 #define PORT_FEATURE_BMC_LINK_OVERRIDE_EN 0x00000001
448 #define PORT_FEATURE_MBA_VLAN_TAG_MASK 0x0000ffff
449 #define PORT_FEATURE_MBA_VLAN_TAG_SHIFT 0
450 #define PORT_FEATURE_MBA_VLAN_EN 0x00010000
453 #define PORT_FEATURE_RESOURCE_CFG_VALID 0x00000001
454 #define PORT_FEATURE_RESOURCE_CFG_DIAG 0x00000002
455 #define PORT_FEATURE_RESOURCE_CFG_L2 0x00000004
456 #define PORT_FEATURE_RESOURCE_CFG_ISCSI 0x00000008
457 #define PORT_FEATURE_RESOURCE_CFG_RDMA 0x00000010
461 #define PORT_FEATURE_SMBUS_EN 0x00000001
462 #define PORT_FEATURE_SMBUS_ADDR_MASK 0x000000fe
463 #define PORT_FEATURE_SMBUS_ADDR_SHIFT 1
467 u32 link_config; /* Used as HW defaults for the driver */
468 #define PORT_FEATURE_CONNECTED_SWITCH_MASK 0x03000000
469 #define PORT_FEATURE_CONNECTED_SWITCH_SHIFT 24
470 /* (forced) low speed switch (< 10G) */
471 #define PORT_FEATURE_CON_SWITCH_1G_SWITCH 0x00000000
472 /* (forced) high speed switch (>= 10G) */
473 #define PORT_FEATURE_CON_SWITCH_10G_SWITCH 0x01000000
474 #define PORT_FEATURE_CON_SWITCH_AUTO_DETECT 0x02000000
475 #define PORT_FEATURE_CON_SWITCH_ONE_TIME_DETECT 0x03000000
477 #define PORT_FEATURE_LINK_SPEED_MASK 0x000f0000
478 #define PORT_FEATURE_LINK_SPEED_SHIFT 16
479 #define PORT_FEATURE_LINK_SPEED_AUTO 0x00000000
480 #define PORT_FEATURE_LINK_SPEED_10M_FULL 0x00010000
481 #define PORT_FEATURE_LINK_SPEED_10M_HALF 0x00020000
482 #define PORT_FEATURE_LINK_SPEED_100M_HALF 0x00030000
483 #define PORT_FEATURE_LINK_SPEED_100M_FULL 0x00040000
484 #define PORT_FEATURE_LINK_SPEED_1G 0x00050000
485 #define PORT_FEATURE_LINK_SPEED_2_5G 0x00060000
486 #define PORT_FEATURE_LINK_SPEED_10G_CX4 0x00070000
487 #define PORT_FEATURE_LINK_SPEED_10G_KX4 0x00080000
488 #define PORT_FEATURE_LINK_SPEED_10G_KR 0x00090000
489 #define PORT_FEATURE_LINK_SPEED_12G 0x000a0000
490 #define PORT_FEATURE_LINK_SPEED_12_5G 0x000b0000
491 #define PORT_FEATURE_LINK_SPEED_13G 0x000c0000
492 #define PORT_FEATURE_LINK_SPEED_15G 0x000d0000
493 #define PORT_FEATURE_LINK_SPEED_16G 0x000e0000
495 #define PORT_FEATURE_FLOW_CONTROL_MASK 0x00000700
496 #define PORT_FEATURE_FLOW_CONTROL_SHIFT 8
497 #define PORT_FEATURE_FLOW_CONTROL_AUTO 0x00000000
498 #define PORT_FEATURE_FLOW_CONTROL_TX 0x00000100
499 #define PORT_FEATURE_FLOW_CONTROL_RX 0x00000200
500 #define PORT_FEATURE_FLOW_CONTROL_BOTH 0x00000300
501 #define PORT_FEATURE_FLOW_CONTROL_NONE 0x00000400
503 /* The default for MCP link configuration,
504 uses the same defines as link_config */
505 u32 mfw_wol_link_cfg;
512 /****************************************************************************
513 * Device Information *
514 ****************************************************************************/
515 struct dev_info { /* size */
517 u32 bc_rev; /* 8 bits each: major, minor, build */ /* 4 */
519 struct shared_hw_cfg shared_hw_config; /* 40 */
521 struct port_hw_cfg port_hw_config[PORT_MAX]; /* 400*2=800 */
523 struct shared_feat_cfg shared_feature_config; /* 4 */
525 struct port_feat_cfg port_feature_config[PORT_MAX];/* 116*2=232 */
538 #define E1_FUNC_MAX 2
539 #define E1H_FUNC_MAX 8
549 /* This value (in milliseconds) determines the frequency of the driver
550 * issuing the PULSE message code. The firmware monitors this periodic
551 * pulse to determine when to switch to an OS-absent mode. */
552 #define DRV_PULSE_PERIOD_MS 250
554 /* This value (in milliseconds) determines how long the driver should
555 * wait for an acknowledgement from the firmware before timing out. Once
556 * the firmware has timed out, the driver will assume there is no firmware
557 * running and there won't be any firmware-driver synchronization during a
559 #define FW_ACK_TIME_OUT_MS 5000
561 #define FW_ACK_POLL_TIME_MS 1
563 #define FW_ACK_NUM_OF_POLL (FW_ACK_TIME_OUT_MS/FW_ACK_POLL_TIME_MS)
565 /* LED Blink rate that will achieve ~15.9Hz */
566 #define LED_BLINK_RATE_VAL 480
568 /****************************************************************************
569 * Driver <-> FW Mailbox *
570 ****************************************************************************/
574 /* Driver should update this field on any link change event */
576 #define LINK_STATUS_LINK_FLAG_MASK 0x00000001
577 #define LINK_STATUS_LINK_UP 0x00000001
578 #define LINK_STATUS_SPEED_AND_DUPLEX_MASK 0x0000001E
579 #define LINK_STATUS_SPEED_AND_DUPLEX_AN_NOT_COMPLETE (0<<1)
580 #define LINK_STATUS_SPEED_AND_DUPLEX_10THD (1<<1)
581 #define LINK_STATUS_SPEED_AND_DUPLEX_10TFD (2<<1)
582 #define LINK_STATUS_SPEED_AND_DUPLEX_100TXHD (3<<1)
583 #define LINK_STATUS_SPEED_AND_DUPLEX_100T4 (4<<1)
584 #define LINK_STATUS_SPEED_AND_DUPLEX_100TXFD (5<<1)
585 #define LINK_STATUS_SPEED_AND_DUPLEX_1000THD (6<<1)
586 #define LINK_STATUS_SPEED_AND_DUPLEX_1000TFD (7<<1)
587 #define LINK_STATUS_SPEED_AND_DUPLEX_1000XFD (7<<1)
588 #define LINK_STATUS_SPEED_AND_DUPLEX_2500THD (8<<1)
589 #define LINK_STATUS_SPEED_AND_DUPLEX_2500TFD (9<<1)
590 #define LINK_STATUS_SPEED_AND_DUPLEX_2500XFD (9<<1)
591 #define LINK_STATUS_SPEED_AND_DUPLEX_10GTFD (10<<1)
592 #define LINK_STATUS_SPEED_AND_DUPLEX_10GXFD (10<<1)
593 #define LINK_STATUS_SPEED_AND_DUPLEX_12GTFD (11<<1)
594 #define LINK_STATUS_SPEED_AND_DUPLEX_12GXFD (11<<1)
595 #define LINK_STATUS_SPEED_AND_DUPLEX_12_5GTFD (12<<1)
596 #define LINK_STATUS_SPEED_AND_DUPLEX_12_5GXFD (12<<1)
597 #define LINK_STATUS_SPEED_AND_DUPLEX_13GTFD (13<<1)
598 #define LINK_STATUS_SPEED_AND_DUPLEX_13GXFD (13<<1)
599 #define LINK_STATUS_SPEED_AND_DUPLEX_15GTFD (14<<1)
600 #define LINK_STATUS_SPEED_AND_DUPLEX_15GXFD (14<<1)
601 #define LINK_STATUS_SPEED_AND_DUPLEX_16GTFD (15<<1)
602 #define LINK_STATUS_SPEED_AND_DUPLEX_16GXFD (15<<1)
604 #define LINK_STATUS_AUTO_NEGOTIATE_FLAG_MASK 0x00000020
605 #define LINK_STATUS_AUTO_NEGOTIATE_ENABLED 0x00000020
607 #define LINK_STATUS_AUTO_NEGOTIATE_COMPLETE 0x00000040
608 #define LINK_STATUS_PARALLEL_DETECTION_FLAG_MASK 0x00000080
609 #define LINK_STATUS_PARALLEL_DETECTION_USED 0x00000080
611 #define LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE 0x00000200
612 #define LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE 0x00000400
613 #define LINK_STATUS_LINK_PARTNER_100T4_CAPABLE 0x00000800
614 #define LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE 0x00001000
615 #define LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE 0x00002000
616 #define LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE 0x00004000
617 #define LINK_STATUS_LINK_PARTNER_10THD_CAPABLE 0x00008000
619 #define LINK_STATUS_TX_FLOW_CONTROL_FLAG_MASK 0x00010000
620 #define LINK_STATUS_TX_FLOW_CONTROL_ENABLED 0x00010000
622 #define LINK_STATUS_RX_FLOW_CONTROL_FLAG_MASK 0x00020000
623 #define LINK_STATUS_RX_FLOW_CONTROL_ENABLED 0x00020000
625 #define LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK 0x000C0000
626 #define LINK_STATUS_LINK_PARTNER_NOT_PAUSE_CAPABLE (0<<18)
627 #define LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE (1<<18)
628 #define LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE (2<<18)
629 #define LINK_STATUS_LINK_PARTNER_BOTH_PAUSE (3<<18)
631 #define LINK_STATUS_SERDES_LINK 0x00100000
633 #define LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE 0x00200000
634 #define LINK_STATUS_LINK_PARTNER_2500XHD_CAPABLE 0x00400000
635 #define LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE 0x00800000
636 #define LINK_STATUS_LINK_PARTNER_12GXFD_CAPABLE 0x01000000
637 #define LINK_STATUS_LINK_PARTNER_12_5GXFD_CAPABLE 0x02000000
638 #define LINK_STATUS_LINK_PARTNER_13GXFD_CAPABLE 0x04000000
639 #define LINK_STATUS_LINK_PARTNER_15GXFD_CAPABLE 0x08000000
640 #define LINK_STATUS_LINK_PARTNER_16GXFD_CAPABLE 0x10000000
652 #define DRV_MSG_CODE_MASK 0xffff0000
653 #define DRV_MSG_CODE_LOAD_REQ 0x10000000
654 #define DRV_MSG_CODE_LOAD_DONE 0x11000000
655 #define DRV_MSG_CODE_UNLOAD_REQ_WOL_EN 0x20000000
656 #define DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS 0x20010000
657 #define DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP 0x20020000
658 #define DRV_MSG_CODE_UNLOAD_DONE 0x21000000
659 #define DRV_MSG_CODE_DIAG_ENTER_REQ 0x50000000
660 #define DRV_MSG_CODE_DIAG_EXIT_REQ 0x60000000
661 #define DRV_MSG_CODE_VALIDATE_KEY 0x70000000
662 #define DRV_MSG_CODE_GET_CURR_KEY 0x80000000
663 #define DRV_MSG_CODE_GET_UPGRADE_KEY 0x81000000
664 #define DRV_MSG_CODE_GET_MANUF_KEY 0x82000000
665 #define DRV_MSG_CODE_LOAD_L2B_PRAM 0x90000000
667 #define BIOS_MSG_CODE_LIC_CHALLENGE 0xff010000
668 #define BIOS_MSG_CODE_LIC_RESPONSE 0xff020000
669 #define BIOS_MSG_CODE_VIRT_MAC_PRIM 0xff030000
670 #define BIOS_MSG_CODE_VIRT_MAC_ISCSI 0xff040000
672 #define DRV_MSG_SEQ_NUMBER_MASK 0x0000ffff
677 #define FW_MSG_CODE_MASK 0xffff0000
678 #define FW_MSG_CODE_DRV_LOAD_COMMON 0x10100000
679 #define FW_MSG_CODE_DRV_LOAD_PORT 0x10110000
680 #define FW_MSG_CODE_DRV_LOAD_FUNCTION 0x10120000
681 #define FW_MSG_CODE_DRV_LOAD_REFUSED 0x10200000
682 #define FW_MSG_CODE_DRV_LOAD_DONE 0x11100000
683 #define FW_MSG_CODE_DRV_UNLOAD_COMMON 0x20100000
684 #define FW_MSG_CODE_DRV_UNLOAD_PORT 0x20110000
685 #define FW_MSG_CODE_DRV_UNLOAD_FUNCTION 0x20120000
686 #define FW_MSG_CODE_DRV_UNLOAD_DONE 0x21100000
687 #define FW_MSG_CODE_DIAG_ENTER_DONE 0x50100000
688 #define FW_MSG_CODE_DIAG_REFUSE 0x50200000
689 #define FW_MSG_CODE_DIAG_EXIT_DONE 0x60100000
690 #define FW_MSG_CODE_VALIDATE_KEY_SUCCESS 0x70100000
691 #define FW_MSG_CODE_VALIDATE_KEY_FAILURE 0x70200000
692 #define FW_MSG_CODE_GET_KEY_DONE 0x80100000
693 #define FW_MSG_CODE_NO_KEY 0x80f00000
694 #define FW_MSG_CODE_LIC_INFO_NOT_READY 0x80f80000
695 #define FW_MSG_CODE_L2B_PRAM_LOADED 0x90100000
696 #define FW_MSG_CODE_L2B_PRAM_T_LOAD_FAILURE 0x90210000
697 #define FW_MSG_CODE_L2B_PRAM_C_LOAD_FAILURE 0x90220000
698 #define FW_MSG_CODE_L2B_PRAM_X_LOAD_FAILURE 0x90230000
699 #define FW_MSG_CODE_L2B_PRAM_U_LOAD_FAILURE 0x90240000
701 #define FW_MSG_CODE_LIC_CHALLENGE 0xff010000
702 #define FW_MSG_CODE_LIC_RESPONSE 0xff020000
703 #define FW_MSG_CODE_VIRT_MAC_PRIM 0xff030000
704 #define FW_MSG_CODE_VIRT_MAC_ISCSI 0xff040000
706 #define FW_MSG_SEQ_NUMBER_MASK 0x0000ffff
711 #define DRV_PULSE_SEQ_MASK 0x00007fff
712 #define DRV_PULSE_SYSTEM_TIME_MASK 0xffff0000
713 /* The system time is in the format of
714 * (year-2001)*12*32 + month*32 + day. */
715 #define DRV_PULSE_ALWAYS_ALIVE 0x00008000
716 /* Indicate to the firmware not to go into the
717 * OS-absent when it is not getting driver pulse.
718 * This is used for debugging as well for PXE(MBA). */
721 #define MCP_PULSE_SEQ_MASK 0x00007fff
722 #define MCP_PULSE_ALWAYS_ALIVE 0x00008000
723 /* Indicates to the driver not to assert due to lack
725 #define MCP_EVENT_MASK 0xffff0000
726 #define MCP_EVENT_OTHER_DRIVER_RESET_REQ 0x00010000
728 u32 iscsi_boot_signature;
729 u32 iscsi_boot_block_offset;
732 #define DRV_STATUS_PMF 0x00000001
735 #define VIRT_MAC_SIGN_MASK 0xffff0000
736 #define VIRT_MAC_SIGNATURE 0x564d0000
742 /****************************************************************************
743 * Management firmware state *
744 ****************************************************************************/
745 /* Allocate 440 bytes for management firmware */
746 #define MGMTFW_STATE_WORD_SIZE 110
748 struct mgmtfw_state {
749 u32 opaque[MGMTFW_STATE_WORD_SIZE];
753 /****************************************************************************
754 * Multi-Function configuration *
755 ****************************************************************************/
756 struct shared_mf_cfg {
759 #define SHARED_MF_CLP_SET_DEFAULT 0x00000000
761 #define SHARED_MF_CLP_EXIT 0x00000001
763 #define SHARED_MF_CLP_EXIT_DONE 0x00010000
769 u32 dynamic_cfg; /* device control channel */
770 #define PORT_MF_CFG_OUTER_VLAN_TAG_MASK 0x0000ffff
771 #define PORT_MF_CFG_OUTER_VLAN_TAG_SHIFT 0
772 #define PORT_MF_CFG_DYNAMIC_CFG_ENABLED 0x00010000
773 #define PORT_MF_CFG_DYNAMIC_CFG_DEFAULT 0x00000000
783 /* function 0 of each port cannot be hidden */
784 #define FUNC_MF_CFG_FUNC_HIDE 0x00000001
786 #define FUNC_MF_CFG_PROTOCOL_MASK 0x00000007
787 #define FUNC_MF_CFG_PROTOCOL_ETHERNET 0x00000002
788 #define FUNC_MF_CFG_PROTOCOL_ETHERNET_WITH_RDMA 0x00000004
789 #define FUNC_MF_CFG_PROTOCOL_ISCSI 0x00000006
790 #define FUNC_MF_CFG_PROTOCOL_DEFAULT\
791 FUNC_MF_CFG_PROTOCOL_ETHERNET_WITH_RDMA
793 #define FUNC_MF_CFG_FUNC_DISABLED 0x00000008
796 /* 0 - low priority, 3 - high priority */
797 #define FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK 0x00000300
798 #define FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT 8
799 #define FUNC_MF_CFG_TRANSMIT_PRIORITY_DEFAULT 0x00000000
802 /* value range - 0..100, increments in 100Mbps */
803 #define FUNC_MF_CFG_MIN_BW_MASK 0x00ff0000
804 #define FUNC_MF_CFG_MIN_BW_SHIFT 16
805 #define FUNC_MF_CFG_MIN_BW_DEFAULT 0x00000000
806 #define FUNC_MF_CFG_MAX_BW_MASK 0xff000000
807 #define FUNC_MF_CFG_MAX_BW_SHIFT 24
808 #define FUNC_MF_CFG_MAX_BW_DEFAULT 0x64000000
810 u32 mac_upper; /* MAC */
811 #define FUNC_MF_CFG_UPPERMAC_MASK 0x0000ffff
812 #define FUNC_MF_CFG_UPPERMAC_SHIFT 0
813 #define FUNC_MF_CFG_UPPERMAC_DEFAULT FUNC_MF_CFG_UPPERMAC_MASK
815 #define FUNC_MF_CFG_LOWERMAC_DEFAULT 0xffffffff
817 u32 e1hov_tag; /* VNI */
818 #define FUNC_MF_CFG_E1HOV_TAG_MASK 0x0000ffff
819 #define FUNC_MF_CFG_E1HOV_TAG_SHIFT 0
820 #define FUNC_MF_CFG_E1HOV_TAG_DEFAULT FUNC_MF_CFG_E1HOV_TAG_MASK
828 struct shared_mf_cfg shared_mf_config;
829 struct port_mf_cfg port_mf_config[PORT_MAX];
831 struct func_mf_cfg func_mf_config[E1_FUNC_MAX];
833 struct func_mf_cfg func_mf_config[E1H_FUNC_MAX];
839 /****************************************************************************
840 * Shared Memory Region *
841 ****************************************************************************/
842 struct shmem_region { /* SharedMem Offset (size) */
844 u32 validity_map[PORT_MAX]; /* 0x0 (4*2 = 0x8) */
845 #define SHR_MEM_FORMAT_REV_ID ('A'<<24)
846 #define SHR_MEM_FORMAT_REV_MASK 0xff000000
848 #define SHR_MEM_VALIDITY_PCI_CFG 0x00100000
849 #define SHR_MEM_VALIDITY_MB 0x00200000
850 #define SHR_MEM_VALIDITY_DEV_INFO 0x00400000
851 #define SHR_MEM_VALIDITY_RESERVED 0x00000007
852 /* One licensing bit should be set */
853 #define SHR_MEM_VALIDITY_LIC_KEY_IN_EFFECT_MASK 0x00000038
854 #define SHR_MEM_VALIDITY_LIC_MANUF_KEY_IN_EFFECT 0x00000008
855 #define SHR_MEM_VALIDITY_LIC_UPGRADE_KEY_IN_EFFECT 0x00000010
856 #define SHR_MEM_VALIDITY_LIC_NO_KEY_IN_EFFECT 0x00000020
858 #define SHR_MEM_VALIDITY_ACTIVE_MFW_UNKNOWN 0x00000000
859 #define SHR_MEM_VALIDITY_ACTIVE_MFW_IPMI 0x00000040
860 #define SHR_MEM_VALIDITY_ACTIVE_MFW_UMP 0x00000080
861 #define SHR_MEM_VALIDITY_ACTIVE_MFW_NCSI 0x000000c0
862 #define SHR_MEM_VALIDITY_ACTIVE_MFW_NONE 0x000001c0
863 #define SHR_MEM_VALIDITY_ACTIVE_MFW_MASK 0x000001c0
865 struct dev_info dev_info; /* 0x8 (0x438) */
867 u8 reserved[52*PORT_MAX];
869 /* FW information (for internal FW use) */
870 u32 fw_info_fio_offset; /* 0x4a8 (0x4) */
871 struct mgmtfw_state mgmtfw_state; /* 0x4ac (0x1b8) */
873 struct drv_port_mb port_mb[PORT_MAX]; /* 0x664 (16*2=0x20) */
874 struct drv_func_mb func_mb[E1H_FUNC_MAX];
876 struct mf_cfg mf_cfg;
882 u32 rx_stat_ifhcinoctets;
883 u32 rx_stat_ifhcinbadoctets;
884 u32 rx_stat_etherstatsfragments;
885 u32 rx_stat_ifhcinucastpkts;
886 u32 rx_stat_ifhcinmulticastpkts;
887 u32 rx_stat_ifhcinbroadcastpkts;
888 u32 rx_stat_dot3statsfcserrors;
889 u32 rx_stat_dot3statsalignmenterrors;
890 u32 rx_stat_dot3statscarriersenseerrors;
891 u32 rx_stat_xonpauseframesreceived;
892 u32 rx_stat_xoffpauseframesreceived;
893 u32 rx_stat_maccontrolframesreceived;
894 u32 rx_stat_xoffstateentered;
895 u32 rx_stat_dot3statsframestoolong;
896 u32 rx_stat_etherstatsjabbers;
897 u32 rx_stat_etherstatsundersizepkts;
898 u32 rx_stat_etherstatspkts64octets;
899 u32 rx_stat_etherstatspkts65octetsto127octets;
900 u32 rx_stat_etherstatspkts128octetsto255octets;
901 u32 rx_stat_etherstatspkts256octetsto511octets;
902 u32 rx_stat_etherstatspkts512octetsto1023octets;
903 u32 rx_stat_etherstatspkts1024octetsto1522octets;
904 u32 rx_stat_etherstatspktsover1522octets;
906 u32 rx_stat_falsecarriererrors;
908 u32 tx_stat_ifhcoutoctets;
909 u32 tx_stat_ifhcoutbadoctets;
910 u32 tx_stat_etherstatscollisions;
911 u32 tx_stat_outxonsent;
912 u32 tx_stat_outxoffsent;
913 u32 tx_stat_flowcontroldone;
914 u32 tx_stat_dot3statssinglecollisionframes;
915 u32 tx_stat_dot3statsmultiplecollisionframes;
916 u32 tx_stat_dot3statsdeferredtransmissions;
917 u32 tx_stat_dot3statsexcessivecollisions;
918 u32 tx_stat_dot3statslatecollisions;
919 u32 tx_stat_ifhcoutucastpkts;
920 u32 tx_stat_ifhcoutmulticastpkts;
921 u32 tx_stat_ifhcoutbroadcastpkts;
922 u32 tx_stat_etherstatspkts64octets;
923 u32 tx_stat_etherstatspkts65octetsto127octets;
924 u32 tx_stat_etherstatspkts128octetsto255octets;
925 u32 tx_stat_etherstatspkts256octetsto511octets;
926 u32 tx_stat_etherstatspkts512octetsto1023octets;
927 u32 tx_stat_etherstatspkts1024octetsto1522octets;
928 u32 tx_stat_etherstatspktsover1522octets;
929 u32 tx_stat_dot3statsinternalmactransmiterrors;
934 u32 tx_stat_gtpkt_lo;
935 u32 tx_stat_gtpkt_hi;
936 u32 tx_stat_gtxpf_lo;
937 u32 tx_stat_gtxpf_hi;
938 u32 tx_stat_gtfcs_lo;
939 u32 tx_stat_gtfcs_hi;
940 u32 tx_stat_gtmca_lo;
941 u32 tx_stat_gtmca_hi;
942 u32 tx_stat_gtbca_lo;
943 u32 tx_stat_gtbca_hi;
944 u32 tx_stat_gtfrg_lo;
945 u32 tx_stat_gtfrg_hi;
946 u32 tx_stat_gtovr_lo;
947 u32 tx_stat_gtovr_hi;
950 u32 tx_stat_gt127_lo;
951 u32 tx_stat_gt127_hi;
952 u32 tx_stat_gt255_lo;
953 u32 tx_stat_gt255_hi;
954 u32 tx_stat_gt511_lo;
955 u32 tx_stat_gt511_hi;
956 u32 tx_stat_gt1023_lo;
957 u32 tx_stat_gt1023_hi;
958 u32 tx_stat_gt1518_lo;
959 u32 tx_stat_gt1518_hi;
960 u32 tx_stat_gt2047_lo;
961 u32 tx_stat_gt2047_hi;
962 u32 tx_stat_gt4095_lo;
963 u32 tx_stat_gt4095_hi;
964 u32 tx_stat_gt9216_lo;
965 u32 tx_stat_gt9216_hi;
966 u32 tx_stat_gt16383_lo;
967 u32 tx_stat_gt16383_hi;
968 u32 tx_stat_gtmax_lo;
969 u32 tx_stat_gtmax_hi;
970 u32 tx_stat_gtufl_lo;
971 u32 tx_stat_gtufl_hi;
972 u32 tx_stat_gterr_lo;
973 u32 tx_stat_gterr_hi;
974 u32 tx_stat_gtbyt_lo;
975 u32 tx_stat_gtbyt_hi;
979 u32 rx_stat_gr127_lo;
980 u32 rx_stat_gr127_hi;
981 u32 rx_stat_gr255_lo;
982 u32 rx_stat_gr255_hi;
983 u32 rx_stat_gr511_lo;
984 u32 rx_stat_gr511_hi;
985 u32 rx_stat_gr1023_lo;
986 u32 rx_stat_gr1023_hi;
987 u32 rx_stat_gr1518_lo;
988 u32 rx_stat_gr1518_hi;
989 u32 rx_stat_gr2047_lo;
990 u32 rx_stat_gr2047_hi;
991 u32 rx_stat_gr4095_lo;
992 u32 rx_stat_gr4095_hi;
993 u32 rx_stat_gr9216_lo;
994 u32 rx_stat_gr9216_hi;
995 u32 rx_stat_gr16383_lo;
996 u32 rx_stat_gr16383_hi;
997 u32 rx_stat_grmax_lo;
998 u32 rx_stat_grmax_hi;
999 u32 rx_stat_grpkt_lo;
1000 u32 rx_stat_grpkt_hi;
1001 u32 rx_stat_grfcs_lo;
1002 u32 rx_stat_grfcs_hi;
1003 u32 rx_stat_grmca_lo;
1004 u32 rx_stat_grmca_hi;
1005 u32 rx_stat_grbca_lo;
1006 u32 rx_stat_grbca_hi;
1007 u32 rx_stat_grxcf_lo;
1008 u32 rx_stat_grxcf_hi;
1009 u32 rx_stat_grxpf_lo;
1010 u32 rx_stat_grxpf_hi;
1011 u32 rx_stat_grxuo_lo;
1012 u32 rx_stat_grxuo_hi;
1013 u32 rx_stat_grjbr_lo;
1014 u32 rx_stat_grjbr_hi;
1015 u32 rx_stat_grovr_lo;
1016 u32 rx_stat_grovr_hi;
1017 u32 rx_stat_grflr_lo;
1018 u32 rx_stat_grflr_hi;
1019 u32 rx_stat_grmeg_lo;
1020 u32 rx_stat_grmeg_hi;
1021 u32 rx_stat_grmeb_lo;
1022 u32 rx_stat_grmeb_hi;
1023 u32 rx_stat_grbyt_lo;
1024 u32 rx_stat_grbyt_hi;
1025 u32 rx_stat_grund_lo;
1026 u32 rx_stat_grund_hi;
1027 u32 rx_stat_grfrg_lo;
1028 u32 rx_stat_grfrg_hi;
1029 u32 rx_stat_grerb_lo;
1030 u32 rx_stat_grerb_hi;
1031 u32 rx_stat_grfre_lo;
1032 u32 rx_stat_grfre_hi;
1033 u32 rx_stat_gripj_lo;
1034 u32 rx_stat_gripj_hi;
1039 struct emac_stats emac_stats;
1040 struct bmac_stats bmac_stats;
1046 u32 rx_stat_ifhcinbadoctets_hi;
1047 u32 rx_stat_ifhcinbadoctets_lo;
1049 /* out_bad_octets */
1050 u32 tx_stat_ifhcoutbadoctets_hi;
1051 u32 tx_stat_ifhcoutbadoctets_lo;
1053 /* crc_receive_errors */
1054 u32 rx_stat_dot3statsfcserrors_hi;
1055 u32 rx_stat_dot3statsfcserrors_lo;
1056 /* alignment_errors */
1057 u32 rx_stat_dot3statsalignmenterrors_hi;
1058 u32 rx_stat_dot3statsalignmenterrors_lo;
1059 /* carrier_sense_errors */
1060 u32 rx_stat_dot3statscarriersenseerrors_hi;
1061 u32 rx_stat_dot3statscarriersenseerrors_lo;
1062 /* false_carrier_detections */
1063 u32 rx_stat_falsecarriererrors_hi;
1064 u32 rx_stat_falsecarriererrors_lo;
1066 /* runt_packets_received */
1067 u32 rx_stat_etherstatsundersizepkts_hi;
1068 u32 rx_stat_etherstatsundersizepkts_lo;
1069 /* jabber_packets_received */
1070 u32 rx_stat_dot3statsframestoolong_hi;
1071 u32 rx_stat_dot3statsframestoolong_lo;
1073 /* error_runt_packets_received */
1074 u32 rx_stat_etherstatsfragments_hi;
1075 u32 rx_stat_etherstatsfragments_lo;
1076 /* error_jabber_packets_received */
1077 u32 rx_stat_etherstatsjabbers_hi;
1078 u32 rx_stat_etherstatsjabbers_lo;
1080 /* control_frames_received */
1081 u32 rx_stat_maccontrolframesreceived_hi;
1082 u32 rx_stat_maccontrolframesreceived_lo;
1083 u32 rx_stat_bmac_xpf_hi;
1084 u32 rx_stat_bmac_xpf_lo;
1085 u32 rx_stat_bmac_xcf_hi;
1086 u32 rx_stat_bmac_xcf_lo;
1088 /* xoff_state_entered */
1089 u32 rx_stat_xoffstateentered_hi;
1090 u32 rx_stat_xoffstateentered_lo;
1091 /* pause_xon_frames_received */
1092 u32 rx_stat_xonpauseframesreceived_hi;
1093 u32 rx_stat_xonpauseframesreceived_lo;
1094 /* pause_xoff_frames_received */
1095 u32 rx_stat_xoffpauseframesreceived_hi;
1096 u32 rx_stat_xoffpauseframesreceived_lo;
1097 /* pause_xon_frames_transmitted */
1098 u32 tx_stat_outxonsent_hi;
1099 u32 tx_stat_outxonsent_lo;
1100 /* pause_xoff_frames_transmitted */
1101 u32 tx_stat_outxoffsent_hi;
1102 u32 tx_stat_outxoffsent_lo;
1103 /* flow_control_done */
1104 u32 tx_stat_flowcontroldone_hi;
1105 u32 tx_stat_flowcontroldone_lo;
1107 /* ether_stats_collisions */
1108 u32 tx_stat_etherstatscollisions_hi;
1109 u32 tx_stat_etherstatscollisions_lo;
1110 /* single_collision_transmit_frames */
1111 u32 tx_stat_dot3statssinglecollisionframes_hi;
1112 u32 tx_stat_dot3statssinglecollisionframes_lo;
1113 /* multiple_collision_transmit_frames */
1114 u32 tx_stat_dot3statsmultiplecollisionframes_hi;
1115 u32 tx_stat_dot3statsmultiplecollisionframes_lo;
1116 /* deferred_transmissions */
1117 u32 tx_stat_dot3statsdeferredtransmissions_hi;
1118 u32 tx_stat_dot3statsdeferredtransmissions_lo;
1119 /* excessive_collision_frames */
1120 u32 tx_stat_dot3statsexcessivecollisions_hi;
1121 u32 tx_stat_dot3statsexcessivecollisions_lo;
1122 /* late_collision_frames */
1123 u32 tx_stat_dot3statslatecollisions_hi;
1124 u32 tx_stat_dot3statslatecollisions_lo;
1126 /* frames_transmitted_64_bytes */
1127 u32 tx_stat_etherstatspkts64octets_hi;
1128 u32 tx_stat_etherstatspkts64octets_lo;
1129 /* frames_transmitted_65_127_bytes */
1130 u32 tx_stat_etherstatspkts65octetsto127octets_hi;
1131 u32 tx_stat_etherstatspkts65octetsto127octets_lo;
1132 /* frames_transmitted_128_255_bytes */
1133 u32 tx_stat_etherstatspkts128octetsto255octets_hi;
1134 u32 tx_stat_etherstatspkts128octetsto255octets_lo;
1135 /* frames_transmitted_256_511_bytes */
1136 u32 tx_stat_etherstatspkts256octetsto511octets_hi;
1137 u32 tx_stat_etherstatspkts256octetsto511octets_lo;
1138 /* frames_transmitted_512_1023_bytes */
1139 u32 tx_stat_etherstatspkts512octetsto1023octets_hi;
1140 u32 tx_stat_etherstatspkts512octetsto1023octets_lo;
1141 /* frames_transmitted_1024_1522_bytes */
1142 u32 tx_stat_etherstatspkts1024octetsto1522octets_hi;
1143 u32 tx_stat_etherstatspkts1024octetsto1522octets_lo;
1144 /* frames_transmitted_1523_9022_bytes */
1145 u32 tx_stat_etherstatspktsover1522octets_hi;
1146 u32 tx_stat_etherstatspktsover1522octets_lo;
1147 u32 tx_stat_bmac_2047_hi;
1148 u32 tx_stat_bmac_2047_lo;
1149 u32 tx_stat_bmac_4095_hi;
1150 u32 tx_stat_bmac_4095_lo;
1151 u32 tx_stat_bmac_9216_hi;
1152 u32 tx_stat_bmac_9216_lo;
1153 u32 tx_stat_bmac_16383_hi;
1154 u32 tx_stat_bmac_16383_lo;
1156 /* internal_mac_transmit_errors */
1157 u32 tx_stat_dot3statsinternalmactransmiterrors_hi;
1158 u32 tx_stat_dot3statsinternalmactransmiterrors_lo;
1160 /* if_out_discards */
1161 u32 tx_stat_bmac_ufl_hi;
1162 u32 tx_stat_bmac_ufl_lo;
1166 #define MAC_STX_IDX_MAX 2
1168 struct host_port_stats {
1169 u32 host_port_stats_start;
1171 struct mac_stx mac_stx[MAC_STX_IDX_MAX];
1176 u32 host_port_stats_end;
1180 struct host_func_stats {
1181 u32 host_func_stats_start;
1183 u32 total_bytes_received_hi;
1184 u32 total_bytes_received_lo;
1186 u32 total_bytes_transmitted_hi;
1187 u32 total_bytes_transmitted_lo;
1189 u32 total_unicast_packets_received_hi;
1190 u32 total_unicast_packets_received_lo;
1192 u32 total_multicast_packets_received_hi;
1193 u32 total_multicast_packets_received_lo;
1195 u32 total_broadcast_packets_received_hi;
1196 u32 total_broadcast_packets_received_lo;
1198 u32 total_unicast_packets_transmitted_hi;
1199 u32 total_unicast_packets_transmitted_lo;
1201 u32 total_multicast_packets_transmitted_hi;
1202 u32 total_multicast_packets_transmitted_lo;
1204 u32 total_broadcast_packets_transmitted_hi;
1205 u32 total_broadcast_packets_transmitted_lo;
1207 u32 valid_bytes_received_hi;
1208 u32 valid_bytes_received_lo;
1210 u32 host_func_stats_end;
1214 #define BCM_5710_FW_MAJOR_VERSION 4
1215 #define BCM_5710_FW_MINOR_VERSION 8
1216 #define BCM_5710_FW_REVISION_VERSION 53
1217 #define BCM_5710_FW_ENGINEERING_VERSION 0
1218 #define BCM_5710_FW_COMPILE_FLAGS 1
1224 struct atten_def_status_block {
1227 #if defined(__BIG_ENDIAN)
1228 u16 attn_bits_index;
1231 #elif defined(__LITTLE_ENDIAN)
1234 u16 attn_bits_index;
1241 * common data for all protocols
1243 struct doorbell_hdr {
1245 #define DOORBELL_HDR_RX (0x1<<0)
1246 #define DOORBELL_HDR_RX_SHIFT 0
1247 #define DOORBELL_HDR_DB_TYPE (0x1<<1)
1248 #define DOORBELL_HDR_DB_TYPE_SHIFT 1
1249 #define DOORBELL_HDR_DPM_SIZE (0x3<<2)
1250 #define DOORBELL_HDR_DPM_SIZE_SHIFT 2
1251 #define DOORBELL_HDR_CONN_TYPE (0xF<<4)
1252 #define DOORBELL_HDR_CONN_TYPE_SHIFT 4
1256 * doorbell message sent to the chip
1259 #if defined(__BIG_ENDIAN)
1262 struct doorbell_hdr header;
1263 #elif defined(__LITTLE_ENDIAN)
1264 struct doorbell_hdr header;
1272 * IGU driver acknowledgement register
1274 struct igu_ack_register {
1275 #if defined(__BIG_ENDIAN)
1276 u16 sb_id_and_flags;
1277 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID (0x1F<<0)
1278 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT 0
1279 #define IGU_ACK_REGISTER_STORM_ID (0x7<<5)
1280 #define IGU_ACK_REGISTER_STORM_ID_SHIFT 5
1281 #define IGU_ACK_REGISTER_UPDATE_INDEX (0x1<<8)
1282 #define IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT 8
1283 #define IGU_ACK_REGISTER_INTERRUPT_MODE (0x3<<9)
1284 #define IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT 9
1285 #define IGU_ACK_REGISTER_RESERVED (0x1F<<11)
1286 #define IGU_ACK_REGISTER_RESERVED_SHIFT 11
1287 u16 status_block_index;
1288 #elif defined(__LITTLE_ENDIAN)
1289 u16 status_block_index;
1290 u16 sb_id_and_flags;
1291 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID (0x1F<<0)
1292 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT 0
1293 #define IGU_ACK_REGISTER_STORM_ID (0x7<<5)
1294 #define IGU_ACK_REGISTER_STORM_ID_SHIFT 5
1295 #define IGU_ACK_REGISTER_UPDATE_INDEX (0x1<<8)
1296 #define IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT 8
1297 #define IGU_ACK_REGISTER_INTERRUPT_MODE (0x3<<9)
1298 #define IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT 9
1299 #define IGU_ACK_REGISTER_RESERVED (0x1F<<11)
1300 #define IGU_ACK_REGISTER_RESERVED_SHIFT 11
1306 * Parser parsing flags field
1308 struct parsing_flags {
1310 #define PARSING_FLAGS_ETHERNET_ADDRESS_TYPE (0x1<<0)
1311 #define PARSING_FLAGS_ETHERNET_ADDRESS_TYPE_SHIFT 0
1312 #define PARSING_FLAGS_VLAN (0x1<<1)
1313 #define PARSING_FLAGS_VLAN_SHIFT 1
1314 #define PARSING_FLAGS_EXTRA_VLAN (0x1<<2)
1315 #define PARSING_FLAGS_EXTRA_VLAN_SHIFT 2
1316 #define PARSING_FLAGS_OVER_ETHERNET_PROTOCOL (0x3<<3)
1317 #define PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT 3
1318 #define PARSING_FLAGS_IP_OPTIONS (0x1<<5)
1319 #define PARSING_FLAGS_IP_OPTIONS_SHIFT 5
1320 #define PARSING_FLAGS_FRAGMENTATION_STATUS (0x1<<6)
1321 #define PARSING_FLAGS_FRAGMENTATION_STATUS_SHIFT 6
1322 #define PARSING_FLAGS_OVER_IP_PROTOCOL (0x3<<7)
1323 #define PARSING_FLAGS_OVER_IP_PROTOCOL_SHIFT 7
1324 #define PARSING_FLAGS_PURE_ACK_INDICATION (0x1<<9)
1325 #define PARSING_FLAGS_PURE_ACK_INDICATION_SHIFT 9
1326 #define PARSING_FLAGS_TCP_OPTIONS_EXIST (0x1<<10)
1327 #define PARSING_FLAGS_TCP_OPTIONS_EXIST_SHIFT 10
1328 #define PARSING_FLAGS_TIME_STAMP_EXIST_FLAG (0x1<<11)
1329 #define PARSING_FLAGS_TIME_STAMP_EXIST_FLAG_SHIFT 11
1330 #define PARSING_FLAGS_CONNECTION_MATCH (0x1<<12)
1331 #define PARSING_FLAGS_CONNECTION_MATCH_SHIFT 12
1332 #define PARSING_FLAGS_LLC_SNAP (0x1<<13)
1333 #define PARSING_FLAGS_LLC_SNAP_SHIFT 13
1334 #define PARSING_FLAGS_RESERVED0 (0x3<<14)
1335 #define PARSING_FLAGS_RESERVED0_SHIFT 14
1346 * dmae command structure
1348 struct dmae_command {
1350 #define DMAE_COMMAND_SRC (0x1<<0)
1351 #define DMAE_COMMAND_SRC_SHIFT 0
1352 #define DMAE_COMMAND_DST (0x3<<1)
1353 #define DMAE_COMMAND_DST_SHIFT 1
1354 #define DMAE_COMMAND_C_DST (0x1<<3)
1355 #define DMAE_COMMAND_C_DST_SHIFT 3
1356 #define DMAE_COMMAND_C_TYPE_ENABLE (0x1<<4)
1357 #define DMAE_COMMAND_C_TYPE_ENABLE_SHIFT 4
1358 #define DMAE_COMMAND_C_TYPE_CRC_ENABLE (0x1<<5)
1359 #define DMAE_COMMAND_C_TYPE_CRC_ENABLE_SHIFT 5
1360 #define DMAE_COMMAND_C_TYPE_CRC_OFFSET (0x7<<6)
1361 #define DMAE_COMMAND_C_TYPE_CRC_OFFSET_SHIFT 6
1362 #define DMAE_COMMAND_ENDIANITY (0x3<<9)
1363 #define DMAE_COMMAND_ENDIANITY_SHIFT 9
1364 #define DMAE_COMMAND_PORT (0x1<<11)
1365 #define DMAE_COMMAND_PORT_SHIFT 11
1366 #define DMAE_COMMAND_CRC_RESET (0x1<<12)
1367 #define DMAE_COMMAND_CRC_RESET_SHIFT 12
1368 #define DMAE_COMMAND_SRC_RESET (0x1<<13)
1369 #define DMAE_COMMAND_SRC_RESET_SHIFT 13
1370 #define DMAE_COMMAND_DST_RESET (0x1<<14)
1371 #define DMAE_COMMAND_DST_RESET_SHIFT 14
1372 #define DMAE_COMMAND_E1HVN (0x3<<15)
1373 #define DMAE_COMMAND_E1HVN_SHIFT 15
1374 #define DMAE_COMMAND_RESERVED0 (0x7FFF<<17)
1375 #define DMAE_COMMAND_RESERVED0_SHIFT 17
1380 #if defined(__BIG_ENDIAN)
1383 #elif defined(__LITTLE_ENDIAN)
1392 #if defined(__BIG_ENDIAN)
1395 #elif defined(__LITTLE_ENDIAN)
1399 #if defined(__BIG_ENDIAN)
1402 #elif defined(__LITTLE_ENDIAN)
1406 #if defined(__BIG_ENDIAN)
1409 #elif defined(__LITTLE_ENDIAN)
1416 struct double_regpair {
1425 * The eth storm context of Ustorm (configuration part)
1427 struct ustorm_eth_st_context_config {
1428 #if defined(__BIG_ENDIAN)
1430 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_MC_ALIGNMENT (0x1<<0)
1431 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_MC_ALIGNMENT_SHIFT 0
1432 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_DYNAMIC_HC (0x1<<1)
1433 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_DYNAMIC_HC_SHIFT 1
1434 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_TPA (0x1<<2)
1435 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_TPA_SHIFT 2
1436 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_SGE_RING (0x1<<3)
1437 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_SGE_RING_SHIFT 3
1438 #define __USTORM_ETH_ST_CONTEXT_CONFIG_RESERVED0 (0xF<<4)
1439 #define __USTORM_ETH_ST_CONTEXT_CONFIG_RESERVED0_SHIFT 4
1442 u8 sb_index_numbers;
1443 #define USTORM_ETH_ST_CONTEXT_CONFIG_CQE_SB_INDEX_NUMBER (0xF<<0)
1444 #define USTORM_ETH_ST_CONTEXT_CONFIG_CQE_SB_INDEX_NUMBER_SHIFT 0
1445 #define USTORM_ETH_ST_CONTEXT_CONFIG_BD_SB_INDEX_NUMBER (0xF<<4)
1446 #define USTORM_ETH_ST_CONTEXT_CONFIG_BD_SB_INDEX_NUMBER_SHIFT 4
1447 #elif defined(__LITTLE_ENDIAN)
1448 u8 sb_index_numbers;
1449 #define USTORM_ETH_ST_CONTEXT_CONFIG_CQE_SB_INDEX_NUMBER (0xF<<0)
1450 #define USTORM_ETH_ST_CONTEXT_CONFIG_CQE_SB_INDEX_NUMBER_SHIFT 0
1451 #define USTORM_ETH_ST_CONTEXT_CONFIG_BD_SB_INDEX_NUMBER (0xF<<4)
1452 #define USTORM_ETH_ST_CONTEXT_CONFIG_BD_SB_INDEX_NUMBER_SHIFT 4
1456 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_MC_ALIGNMENT (0x1<<0)
1457 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_MC_ALIGNMENT_SHIFT 0
1458 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_DYNAMIC_HC (0x1<<1)
1459 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_DYNAMIC_HC_SHIFT 1
1460 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_TPA (0x1<<2)
1461 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_TPA_SHIFT 2
1462 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_SGE_RING (0x1<<3)
1463 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_SGE_RING_SHIFT 3
1464 #define __USTORM_ETH_ST_CONTEXT_CONFIG_RESERVED0 (0xF<<4)
1465 #define __USTORM_ETH_ST_CONTEXT_CONFIG_RESERVED0_SHIFT 4
1467 #if defined(__BIG_ENDIAN)
1469 u8 statistics_counter_id;
1470 u8 mc_alignment_log_size;
1471 #elif defined(__LITTLE_ENDIAN)
1472 u8 mc_alignment_log_size;
1473 u8 statistics_counter_id;
1476 #if defined(__BIG_ENDIAN)
1477 u8 __local_sge_prod;
1480 #elif defined(__LITTLE_ENDIAN)
1483 u8 __local_sge_prod;
1486 u32 bd_page_base_lo;
1487 u32 bd_page_base_hi;
1488 u32 sge_page_base_lo;
1489 u32 sge_page_base_hi;
1493 * The eth Rx Buffer Descriptor
1501 * The eth Rx SGE Descriptor
1509 * Local BDs and SGEs rings (in ETH)
1511 struct eth_local_rx_rings {
1512 struct eth_rx_bd __local_bd_ring[16];
1513 struct eth_rx_sge __local_sge_ring[12];
1517 * The eth storm context of Ustorm
1519 struct ustorm_eth_st_context {
1520 struct ustorm_eth_st_context_config common;
1521 struct eth_local_rx_rings __rings;
1525 * The eth storm context of Tstorm
1527 struct tstorm_eth_st_context {
1528 u32 __reserved0[28];
1532 * The eth aggregative context section of Xstorm
1534 struct xstorm_eth_extra_ag_context_section {
1535 #if defined(__BIG_ENDIAN)
1539 #elif defined(__LITTLE_ENDIAN)
1548 #if defined(__BIG_ENDIAN)
1551 u16 __tcp_agg_vars2;
1552 #elif defined(__LITTLE_ENDIAN)
1553 u16 __tcp_agg_vars2;
1561 #if defined(__BIG_ENDIAN)
1564 #elif defined(__LITTLE_ENDIAN)
1568 #if defined(__BIG_ENDIAN)
1573 #elif defined(__LITTLE_ENDIAN)
1579 u32 __tcp_agg_vars6;
1580 #if defined(__BIG_ENDIAN)
1582 u16 __tcp_agg_vars7;
1583 #elif defined(__LITTLE_ENDIAN)
1584 u16 __tcp_agg_vars7;
1589 #if defined(__BIG_ENDIAN)
1593 #elif defined(__LITTLE_ENDIAN)
1601 * The eth aggregative context of Xstorm
1603 struct xstorm_eth_ag_context {
1604 #if defined(__BIG_ENDIAN)
1608 #elif defined(__LITTLE_ENDIAN)
1613 #if defined(__BIG_ENDIAN)
1618 #elif defined(__LITTLE_ENDIAN)
1624 u32 __more_packets_to_send;
1625 #if defined(__BIG_ENDIAN)
1628 #elif defined(__LITTLE_ENDIAN)
1632 struct xstorm_eth_extra_ag_context_section __extra_section;
1633 #if defined(__BIG_ENDIAN)
1637 #elif defined(__LITTLE_ENDIAN)
1642 #if defined(__BIG_ENDIAN)
1645 #elif defined(__LITTLE_ENDIAN)
1649 #if defined(__BIG_ENDIAN)
1653 #elif defined(__LITTLE_ENDIAN)
1658 #if defined(__BIG_ENDIAN)
1661 #elif defined(__LITTLE_ENDIAN)
1666 #if defined(__BIG_ENDIAN)
1669 #elif defined(__LITTLE_ENDIAN)
1673 #if defined(__BIG_ENDIAN)
1678 #elif defined(__LITTLE_ENDIAN)
1684 #if defined(__BIG_ENDIAN)
1686 u16 __bd_ind_max_val;
1687 #elif defined(__LITTLE_ENDIAN)
1688 u16 __bd_ind_max_val;
1697 * The eth aggregative context section of Tstorm
1699 struct tstorm_eth_extra_ag_context_section {
1701 #if defined(__BIG_ENDIAN)
1705 #elif defined(__LITTLE_ENDIAN)
1710 #if defined(__BIG_ENDIAN)
1714 #elif defined(__LITTLE_ENDIAN)
1724 u32 __tcp_agg_vars1;
1731 * The eth aggregative context of Tstorm
1733 struct tstorm_eth_ag_context {
1734 #if defined(__BIG_ENDIAN)
1738 #elif defined(__LITTLE_ENDIAN)
1743 #if defined(__BIG_ENDIAN)
1746 #elif defined(__LITTLE_ENDIAN)
1750 struct tstorm_eth_extra_ag_context_section __extra_section;
1754 * The eth aggregative context of Cstorm
1756 struct cstorm_eth_ag_context {
1758 #if defined(__BIG_ENDIAN)
1762 #elif defined(__LITTLE_ENDIAN)
1767 u32 __num_of_treated_packet;
1768 u32 __last_packet_treated;
1769 #if defined(__BIG_ENDIAN)
1772 #elif defined(__LITTLE_ENDIAN)
1776 #if defined(__BIG_ENDIAN)
1781 #elif defined(__LITTLE_ENDIAN)
1787 #if defined(__BIG_ENDIAN)
1790 #elif defined(__LITTLE_ENDIAN)
1795 #if defined(__BIG_ENDIAN)
1798 #elif defined(__LITTLE_ENDIAN)
1802 #if defined(__BIG_ENDIAN)
1803 u16 __packet_index_th;
1805 #elif defined(__LITTLE_ENDIAN)
1807 u16 __packet_index_th;
1812 * The eth aggregative context of Ustorm
1814 struct ustorm_eth_ag_context {
1815 #if defined(__BIG_ENDIAN)
1816 u8 __aux_counter_flags;
1820 #elif defined(__LITTLE_ENDIAN)
1824 u8 __aux_counter_flags;
1826 #if defined(__BIG_ENDIAN)
1830 #elif defined(__LITTLE_ENDIAN)
1836 #if defined(__BIG_ENDIAN)
1840 #elif defined(__LITTLE_ENDIAN)
1847 #if defined(__BIG_ENDIAN)
1850 #elif defined(__LITTLE_ENDIAN)
1854 #if defined(__BIG_ENDIAN)
1856 u8 __decision_rules;
1857 u8 __decision_rule_enable_bits;
1858 #elif defined(__LITTLE_ENDIAN)
1859 u8 __decision_rule_enable_bits;
1860 u8 __decision_rules;
1866 * Timers connection context
1868 struct timers_block_context {
1873 #define __TIMERS_BLOCK_CONTEXT_NUM_OF_ACTIVE_TIMERS (0x3<<0)
1874 #define __TIMERS_BLOCK_CONTEXT_NUM_OF_ACTIVE_TIMERS_SHIFT 0
1875 #define TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG (0x1<<2)
1876 #define TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG_SHIFT 2
1877 #define __TIMERS_BLOCK_CONTEXT_RESERVED0 (0x1FFFFFFF<<3)
1878 #define __TIMERS_BLOCK_CONTEXT_RESERVED0_SHIFT 3
1882 * structure for easy accessibility to assembler
1884 struct eth_tx_bd_flags {
1886 #define ETH_TX_BD_FLAGS_VLAN_TAG (0x1<<0)
1887 #define ETH_TX_BD_FLAGS_VLAN_TAG_SHIFT 0
1888 #define ETH_TX_BD_FLAGS_IP_CSUM (0x1<<1)
1889 #define ETH_TX_BD_FLAGS_IP_CSUM_SHIFT 1
1890 #define ETH_TX_BD_FLAGS_TCP_CSUM (0x1<<2)
1891 #define ETH_TX_BD_FLAGS_TCP_CSUM_SHIFT 2
1892 #define ETH_TX_BD_FLAGS_END_BD (0x1<<3)
1893 #define ETH_TX_BD_FLAGS_END_BD_SHIFT 3
1894 #define ETH_TX_BD_FLAGS_START_BD (0x1<<4)
1895 #define ETH_TX_BD_FLAGS_START_BD_SHIFT 4
1896 #define ETH_TX_BD_FLAGS_HDR_POOL (0x1<<5)
1897 #define ETH_TX_BD_FLAGS_HDR_POOL_SHIFT 5
1898 #define ETH_TX_BD_FLAGS_SW_LSO (0x1<<6)
1899 #define ETH_TX_BD_FLAGS_SW_LSO_SHIFT 6
1900 #define ETH_TX_BD_FLAGS_IPV6 (0x1<<7)
1901 #define ETH_TX_BD_FLAGS_IPV6_SHIFT 7
1905 * The eth Tx Buffer Descriptor
1913 struct eth_tx_bd_flags bd_flags;
1915 #define ETH_TX_BD_HDR_NBDS (0x3F<<0)
1916 #define ETH_TX_BD_HDR_NBDS_SHIFT 0
1917 #define ETH_TX_BD_ETH_ADDR_TYPE (0x3<<6)
1918 #define ETH_TX_BD_ETH_ADDR_TYPE_SHIFT 6
1922 * Tx parsing BD structure for ETH,Relevant in START
1924 struct eth_tx_parse_bd {
1926 #define ETH_TX_PARSE_BD_IP_HDR_START_OFFSET (0xF<<0)
1927 #define ETH_TX_PARSE_BD_IP_HDR_START_OFFSET_SHIFT 0
1928 #define ETH_TX_PARSE_BD_CS_ANY_FLG (0x1<<4)
1929 #define ETH_TX_PARSE_BD_CS_ANY_FLG_SHIFT 4
1930 #define ETH_TX_PARSE_BD_PSEUDO_CS_WITHOUT_LEN (0x1<<5)
1931 #define ETH_TX_PARSE_BD_PSEUDO_CS_WITHOUT_LEN_SHIFT 5
1932 #define ETH_TX_PARSE_BD_LLC_SNAP_EN (0x1<<6)
1933 #define ETH_TX_PARSE_BD_LLC_SNAP_EN_SHIFT 6
1934 #define ETH_TX_PARSE_BD_NS_FLG (0x1<<7)
1935 #define ETH_TX_PARSE_BD_NS_FLG_SHIFT 7
1937 #define ETH_TX_PARSE_BD_FIN_FLG (0x1<<0)
1938 #define ETH_TX_PARSE_BD_FIN_FLG_SHIFT 0
1939 #define ETH_TX_PARSE_BD_SYN_FLG (0x1<<1)
1940 #define ETH_TX_PARSE_BD_SYN_FLG_SHIFT 1
1941 #define ETH_TX_PARSE_BD_RST_FLG (0x1<<2)
1942 #define ETH_TX_PARSE_BD_RST_FLG_SHIFT 2
1943 #define ETH_TX_PARSE_BD_PSH_FLG (0x1<<3)
1944 #define ETH_TX_PARSE_BD_PSH_FLG_SHIFT 3
1945 #define ETH_TX_PARSE_BD_ACK_FLG (0x1<<4)
1946 #define ETH_TX_PARSE_BD_ACK_FLG_SHIFT 4
1947 #define ETH_TX_PARSE_BD_URG_FLG (0x1<<5)
1948 #define ETH_TX_PARSE_BD_URG_FLG_SHIFT 5
1949 #define ETH_TX_PARSE_BD_ECE_FLG (0x1<<6)
1950 #define ETH_TX_PARSE_BD_ECE_FLG_SHIFT 6
1951 #define ETH_TX_PARSE_BD_CWR_FLG (0x1<<7)
1952 #define ETH_TX_PARSE_BD_CWR_FLG_SHIFT 7
1957 u16 tcp_pseudo_csum;
1963 * The last BD in the BD memory will hold a pointer to the next BD memory
1965 struct eth_tx_next_bd {
1972 * union for 3 Bd types
1974 union eth_tx_bd_types {
1975 struct eth_tx_bd reg_bd;
1976 struct eth_tx_parse_bd parse_bd;
1977 struct eth_tx_next_bd next_bd;
1981 * The eth storm context of Xstorm
1983 struct xstorm_eth_st_context {
1984 u32 tx_bd_page_base_lo;
1985 u32 tx_bd_page_base_hi;
1986 #if defined(__BIG_ENDIAN)
1989 #define XSTORM_ETH_ST_CONTEXT_STATISTICS_COUNTER_ID (0x7F<<0)
1990 #define XSTORM_ETH_ST_CONTEXT_STATISTICS_COUNTER_ID_SHIFT 0
1991 #define XSTORM_ETH_ST_CONTEXT_STATISTICS_ENABLE (0x1<<7)
1992 #define XSTORM_ETH_ST_CONTEXT_STATISTICS_ENABLE_SHIFT 7
1993 u8 __local_tx_bd_prod;
1994 #elif defined(__LITTLE_ENDIAN)
1995 u8 __local_tx_bd_prod;
1997 #define XSTORM_ETH_ST_CONTEXT_STATISTICS_COUNTER_ID (0x7F<<0)
1998 #define XSTORM_ETH_ST_CONTEXT_STATISTICS_COUNTER_ID_SHIFT 0
1999 #define XSTORM_ETH_ST_CONTEXT_STATISTICS_ENABLE (0x1<<7)
2000 #define XSTORM_ETH_ST_CONTEXT_STATISTICS_ENABLE_SHIFT 7
2003 u32 db_data_addr_lo;
2004 u32 db_data_addr_hi;
2008 union eth_tx_bd_types __bds[13];
2012 * The eth storm context of Cstorm
2014 struct cstorm_eth_st_context {
2015 #if defined(__BIG_ENDIAN)
2019 #elif defined(__LITTLE_ENDIAN)
2028 * Ethernet connection context
2030 struct eth_context {
2031 struct ustorm_eth_st_context ustorm_st_context;
2032 struct tstorm_eth_st_context tstorm_st_context;
2033 struct xstorm_eth_ag_context xstorm_ag_context;
2034 struct tstorm_eth_ag_context tstorm_ag_context;
2035 struct cstorm_eth_ag_context cstorm_ag_context;
2036 struct ustorm_eth_ag_context ustorm_ag_context;
2037 struct timers_block_context timers_context;
2038 struct xstorm_eth_st_context xstorm_st_context;
2039 struct cstorm_eth_st_context cstorm_st_context;
2046 struct eth_tx_doorbell {
2047 #if defined(__BIG_ENDIAN)
2050 #define ETH_TX_DOORBELL_NUM_BDS (0x3F<<0)
2051 #define ETH_TX_DOORBELL_NUM_BDS_SHIFT 0
2052 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG (0x1<<6)
2053 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG_SHIFT 6
2054 #define ETH_TX_DOORBELL_SPARE (0x1<<7)
2055 #define ETH_TX_DOORBELL_SPARE_SHIFT 7
2056 struct doorbell_hdr hdr;
2057 #elif defined(__LITTLE_ENDIAN)
2058 struct doorbell_hdr hdr;
2060 #define ETH_TX_DOORBELL_NUM_BDS (0x3F<<0)
2061 #define ETH_TX_DOORBELL_NUM_BDS_SHIFT 0
2062 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG (0x1<<6)
2063 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG_SHIFT 6
2064 #define ETH_TX_DOORBELL_SPARE (0x1<<7)
2065 #define ETH_TX_DOORBELL_SPARE_SHIFT 7
2072 * ustorm status block
2074 struct ustorm_def_status_block {
2075 u16 index_values[HC_USTORM_DEF_SB_NUM_INDICES];
2076 u16 status_block_index;
2083 * cstorm status block
2085 struct cstorm_def_status_block {
2086 u16 index_values[HC_CSTORM_DEF_SB_NUM_INDICES];
2087 u16 status_block_index;
2094 * xstorm status block
2096 struct xstorm_def_status_block {
2097 u16 index_values[HC_XSTORM_DEF_SB_NUM_INDICES];
2098 u16 status_block_index;
2105 * tstorm status block
2107 struct tstorm_def_status_block {
2108 u16 index_values[HC_TSTORM_DEF_SB_NUM_INDICES];
2109 u16 status_block_index;
2118 struct host_def_status_block {
2119 struct atten_def_status_block atten_status_block;
2120 struct ustorm_def_status_block u_def_status_block;
2121 struct cstorm_def_status_block c_def_status_block;
2122 struct xstorm_def_status_block x_def_status_block;
2123 struct tstorm_def_status_block t_def_status_block;
2128 * ustorm status block
2130 struct ustorm_status_block {
2131 u16 index_values[HC_USTORM_SB_NUM_INDICES];
2132 u16 status_block_index;
2139 * cstorm status block
2141 struct cstorm_status_block {
2142 u16 index_values[HC_CSTORM_SB_NUM_INDICES];
2143 u16 status_block_index;
2152 struct host_status_block {
2153 struct ustorm_status_block u_status_block;
2154 struct cstorm_status_block c_status_block;
2159 * The data for RSS setup ramrod
2161 struct eth_client_setup_ramrod_data {
2170 * L2 dynamic host coalescing init parameters
2172 struct eth_dynamic_hc_config {
2179 * regular eth FP CQE parameters struct
2181 struct eth_fast_path_rx_cqe {
2182 u8 type_error_flags;
2183 #define ETH_FAST_PATH_RX_CQE_TYPE (0x1<<0)
2184 #define ETH_FAST_PATH_RX_CQE_TYPE_SHIFT 0
2185 #define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG (0x1<<1)
2186 #define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG_SHIFT 1
2187 #define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG (0x1<<2)
2188 #define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG_SHIFT 2
2189 #define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG (0x1<<3)
2190 #define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG_SHIFT 3
2191 #define ETH_FAST_PATH_RX_CQE_START_FLG (0x1<<4)
2192 #define ETH_FAST_PATH_RX_CQE_START_FLG_SHIFT 4
2193 #define ETH_FAST_PATH_RX_CQE_END_FLG (0x1<<5)
2194 #define ETH_FAST_PATH_RX_CQE_END_FLG_SHIFT 5
2195 #define ETH_FAST_PATH_RX_CQE_RESERVED0 (0x3<<6)
2196 #define ETH_FAST_PATH_RX_CQE_RESERVED0_SHIFT 6
2198 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE (0x7<<0)
2199 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE_SHIFT 0
2200 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG (0x1<<3)
2201 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG_SHIFT 3
2202 #define ETH_FAST_PATH_RX_CQE_BROADCAST_FLG (0x1<<4)
2203 #define ETH_FAST_PATH_RX_CQE_BROADCAST_FLG_SHIFT 4
2204 #define ETH_FAST_PATH_RX_CQE_MAC_MATCH_FLG (0x1<<5)
2205 #define ETH_FAST_PATH_RX_CQE_MAC_MATCH_FLG_SHIFT 5
2206 #define ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG (0x1<<6)
2207 #define ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG_SHIFT 6
2208 #define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG (0x1<<7)
2209 #define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG_SHIFT 7
2210 u8 placement_offset;
2212 u32 rss_hash_result;
2216 struct parsing_flags pars_flags;
2222 * The data for RSS setup ramrod
2224 struct eth_halt_ramrod_data {
2231 * The data for statistics query ramrod
2233 struct eth_query_ramrod_data {
2234 #if defined(__BIG_ENDIAN)
2238 #elif defined(__LITTLE_ENDIAN)
2248 * Place holder for ramrods protocol specific data
2250 struct ramrod_data {
2256 * union for ramrod data for Ethernet protocol (CQE) (force size of 16 bits)
2258 union eth_ramrod_data {
2259 struct ramrod_data general;
2264 * Rx Last BD in page (in ETH)
2266 struct eth_rx_bd_next_page {
2274 * Eth Rx Cqe structure- general structure for ramrods
2276 struct common_ramrod_eth_rx_cqe {
2278 #define COMMON_RAMROD_ETH_RX_CQE_TYPE (0x1<<0)
2279 #define COMMON_RAMROD_ETH_RX_CQE_TYPE_SHIFT 0
2280 #define COMMON_RAMROD_ETH_RX_CQE_RESERVED0 (0x7F<<1)
2281 #define COMMON_RAMROD_ETH_RX_CQE_RESERVED0_SHIFT 1
2284 u32 conn_and_cmd_data;
2285 #define COMMON_RAMROD_ETH_RX_CQE_CID (0xFFFFFF<<0)
2286 #define COMMON_RAMROD_ETH_RX_CQE_CID_SHIFT 0
2287 #define COMMON_RAMROD_ETH_RX_CQE_CMD_ID (0xFF<<24)
2288 #define COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT 24
2289 struct ramrod_data protocol_data;
2294 * Rx Last CQE in page (in ETH)
2296 struct eth_rx_cqe_next_page {
2303 * union for all eth rx cqe types (fix their sizes)
2306 struct eth_fast_path_rx_cqe fast_path_cqe;
2307 struct common_ramrod_eth_rx_cqe ramrod_cqe;
2308 struct eth_rx_cqe_next_page next_page_cqe;
2313 * common data for all protocols
2316 u32 conn_and_cmd_data;
2317 #define SPE_HDR_CID (0xFFFFFF<<0)
2318 #define SPE_HDR_CID_SHIFT 0
2319 #define SPE_HDR_CMD_ID (0xFF<<24)
2320 #define SPE_HDR_CMD_ID_SHIFT 24
2322 #define SPE_HDR_CONN_TYPE (0xFF<<0)
2323 #define SPE_HDR_CONN_TYPE_SHIFT 0
2324 #define SPE_HDR_COMMON_RAMROD (0xFF<<8)
2325 #define SPE_HDR_COMMON_RAMROD_SHIFT 8
2330 * Ethernet slow path element
2332 union eth_specific_data {
2333 u8 protocol_data[8];
2334 struct regpair mac_config_addr;
2335 struct eth_client_setup_ramrod_data client_setup_ramrod_data;
2336 struct eth_halt_ramrod_data halt_ramrod_data;
2337 struct regpair leading_cqe_addr;
2338 struct regpair update_data_addr;
2339 struct eth_query_ramrod_data query_ramrod_data;
2343 * Ethernet slow path element
2347 union eth_specific_data data;
2352 * doorbell data in host memory
2354 struct eth_tx_db_data {
2362 * Common configuration parameters per function in Tstorm
2364 struct tstorm_eth_function_common_config {
2365 #if defined(__BIG_ENDIAN)
2366 u8 leading_client_id;
2369 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY (0x1<<0)
2370 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY_SHIFT 0
2371 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY (0x1<<1)
2372 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY_SHIFT 1
2373 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY (0x1<<2)
2374 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY_SHIFT 2
2375 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY (0x1<<3)
2376 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY_SHIFT 3
2377 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE (0x7<<4)
2378 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE_SHIFT 4
2379 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_DEFAULT_ENABLE (0x1<<7)
2380 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_DEFAULT_ENABLE_SHIFT 7
2381 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_IN_CAM (0x1<<8)
2382 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_IN_CAM_SHIFT 8
2383 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_E1HOV_IN_CAM (0x1<<9)
2384 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_E1HOV_IN_CAM_SHIFT 9
2385 #define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0 (0x3F<<10)
2386 #define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0_SHIFT 10
2387 #elif defined(__LITTLE_ENDIAN)
2389 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY (0x1<<0)
2390 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY_SHIFT 0
2391 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY (0x1<<1)
2392 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY_SHIFT 1
2393 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY (0x1<<2)
2394 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY_SHIFT 2
2395 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY (0x1<<3)
2396 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY_SHIFT 3
2397 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE (0x7<<4)
2398 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE_SHIFT 4
2399 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_DEFAULT_ENABLE (0x1<<7)
2400 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_DEFAULT_ENABLE_SHIFT 7
2401 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_IN_CAM (0x1<<8)
2402 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_IN_CAM_SHIFT 8
2403 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_E1HOV_IN_CAM (0x1<<9)
2404 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_E1HOV_IN_CAM_SHIFT 9
2405 #define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0 (0x3F<<10)
2406 #define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0_SHIFT 10
2408 u8 leading_client_id;
2414 * parameters for eth update ramrod
2416 struct eth_update_ramrod_data {
2417 struct tstorm_eth_function_common_config func_config;
2418 u8 indirectionTable[128];
2423 * MAC filtering configuration command header
2425 struct mac_configuration_hdr {
2433 * MAC address in list for ramrod
2435 struct tstorm_cam_entry {
2437 u16 middle_mac_addr;
2440 #define TSTORM_CAM_ENTRY_PORT_ID (0x1<<0)
2441 #define TSTORM_CAM_ENTRY_PORT_ID_SHIFT 0
2442 #define TSTORM_CAM_ENTRY_RSRVVAL0 (0x7<<1)
2443 #define TSTORM_CAM_ENTRY_RSRVVAL0_SHIFT 1
2444 #define TSTORM_CAM_ENTRY_RESERVED0 (0xFFF<<4)
2445 #define TSTORM_CAM_ENTRY_RESERVED0_SHIFT 4
2449 * MAC filtering: CAM target table entry
2451 struct tstorm_cam_target_table_entry {
2453 #define TSTORM_CAM_TARGET_TABLE_ENTRY_BROADCAST (0x1<<0)
2454 #define TSTORM_CAM_TARGET_TABLE_ENTRY_BROADCAST_SHIFT 0
2455 #define TSTORM_CAM_TARGET_TABLE_ENTRY_OVERRIDE_VLAN_REMOVAL (0x1<<1)
2456 #define TSTORM_CAM_TARGET_TABLE_ENTRY_OVERRIDE_VLAN_REMOVAL_SHIFT 1
2457 #define TSTORM_CAM_TARGET_TABLE_ENTRY_ACTION_TYPE (0x1<<2)
2458 #define TSTORM_CAM_TARGET_TABLE_ENTRY_ACTION_TYPE_SHIFT 2
2459 #define TSTORM_CAM_TARGET_TABLE_ENTRY_RDMA_MAC (0x1<<3)
2460 #define TSTORM_CAM_TARGET_TABLE_ENTRY_RDMA_MAC_SHIFT 3
2461 #define TSTORM_CAM_TARGET_TABLE_ENTRY_RESERVED0 (0xF<<4)
2462 #define TSTORM_CAM_TARGET_TABLE_ENTRY_RESERVED0_SHIFT 4
2468 * MAC address in list for ramrod
2470 struct mac_configuration_entry {
2471 struct tstorm_cam_entry cam_entry;
2472 struct tstorm_cam_target_table_entry target_table_entry;
2476 * MAC filtering configuration command
2478 struct mac_configuration_cmd {
2479 struct mac_configuration_hdr hdr;
2480 struct mac_configuration_entry config_table[64];
2485 * MAC address in list for ramrod
2487 struct mac_configuration_entry_e1h {
2489 u16 middle_mac_addr;
2495 #define MAC_CONFIGURATION_ENTRY_E1H_PORT (0x1<<0)
2496 #define MAC_CONFIGURATION_ENTRY_E1H_PORT_SHIFT 0
2497 #define MAC_CONFIGURATION_ENTRY_E1H_ACTION_TYPE (0x1<<1)
2498 #define MAC_CONFIGURATION_ENTRY_E1H_ACTION_TYPE_SHIFT 1
2499 #define MAC_CONFIGURATION_ENTRY_E1H_RDMA_MAC (0x1<<2)
2500 #define MAC_CONFIGURATION_ENTRY_E1H_RDMA_MAC_SHIFT 2
2501 #define MAC_CONFIGURATION_ENTRY_E1H_RESERVED0 (0x1F<<3)
2502 #define MAC_CONFIGURATION_ENTRY_E1H_RESERVED0_SHIFT 3
2506 * MAC filtering configuration command
2508 struct mac_configuration_cmd_e1h {
2509 struct mac_configuration_hdr hdr;
2510 struct mac_configuration_entry_e1h config_table[32];
2515 * approximate-match multicast filtering for E1H per function in Tstorm
2517 struct tstorm_eth_approximate_match_multicast_filtering {
2518 u32 mcast_add_hash_bit_array[8];
2523 * Configuration parameters per client in Tstorm
2525 struct tstorm_eth_client_config {
2526 #if defined(__BIG_ENDIAN)
2527 u8 max_sges_for_packet;
2528 u8 statistics_counter_id;
2530 #elif defined(__LITTLE_ENDIAN)
2532 u8 statistics_counter_id;
2533 u8 max_sges_for_packet;
2535 #if defined(__BIG_ENDIAN)
2537 #define TSTORM_ETH_CLIENT_CONFIG_DROP_IP_CS_ERR (0x1<<0)
2538 #define TSTORM_ETH_CLIENT_CONFIG_DROP_IP_CS_ERR_SHIFT 0
2539 #define TSTORM_ETH_CLIENT_CONFIG_DROP_TCP_CS_ERR (0x1<<1)
2540 #define TSTORM_ETH_CLIENT_CONFIG_DROP_TCP_CS_ERR_SHIFT 1
2541 #define TSTORM_ETH_CLIENT_CONFIG_DROP_TTL0 (0x1<<2)
2542 #define TSTORM_ETH_CLIENT_CONFIG_DROP_TTL0_SHIFT 2
2543 #define TSTORM_ETH_CLIENT_CONFIG_DROP_UDP_CS_ERR (0x1<<3)
2544 #define TSTORM_ETH_CLIENT_CONFIG_DROP_UDP_CS_ERR_SHIFT 3
2545 #define __TSTORM_ETH_CLIENT_CONFIG_RESERVED1 (0xFFF<<4)
2546 #define __TSTORM_ETH_CLIENT_CONFIG_RESERVED1_SHIFT 4
2548 #define TSTORM_ETH_CLIENT_CONFIG_VLAN_REM_ENABLE (0x1<<0)
2549 #define TSTORM_ETH_CLIENT_CONFIG_VLAN_REM_ENABLE_SHIFT 0
2550 #define TSTORM_ETH_CLIENT_CONFIG_E1HOV_REM_ENABLE (0x1<<1)
2551 #define TSTORM_ETH_CLIENT_CONFIG_E1HOV_REM_ENABLE_SHIFT 1
2552 #define TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE (0x1<<2)
2553 #define TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE_SHIFT 2
2554 #define TSTORM_ETH_CLIENT_CONFIG_ENABLE_SGE_RING (0x1<<3)
2555 #define TSTORM_ETH_CLIENT_CONFIG_ENABLE_SGE_RING_SHIFT 3
2556 #define __TSTORM_ETH_CLIENT_CONFIG_RESERVED0 (0xFFF<<4)
2557 #define __TSTORM_ETH_CLIENT_CONFIG_RESERVED0_SHIFT 4
2558 #elif defined(__LITTLE_ENDIAN)
2560 #define TSTORM_ETH_CLIENT_CONFIG_VLAN_REM_ENABLE (0x1<<0)
2561 #define TSTORM_ETH_CLIENT_CONFIG_VLAN_REM_ENABLE_SHIFT 0
2562 #define TSTORM_ETH_CLIENT_CONFIG_E1HOV_REM_ENABLE (0x1<<1)
2563 #define TSTORM_ETH_CLIENT_CONFIG_E1HOV_REM_ENABLE_SHIFT 1
2564 #define TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE (0x1<<2)
2565 #define TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE_SHIFT 2
2566 #define TSTORM_ETH_CLIENT_CONFIG_ENABLE_SGE_RING (0x1<<3)
2567 #define TSTORM_ETH_CLIENT_CONFIG_ENABLE_SGE_RING_SHIFT 3
2568 #define __TSTORM_ETH_CLIENT_CONFIG_RESERVED0 (0xFFF<<4)
2569 #define __TSTORM_ETH_CLIENT_CONFIG_RESERVED0_SHIFT 4
2571 #define TSTORM_ETH_CLIENT_CONFIG_DROP_IP_CS_ERR (0x1<<0)
2572 #define TSTORM_ETH_CLIENT_CONFIG_DROP_IP_CS_ERR_SHIFT 0
2573 #define TSTORM_ETH_CLIENT_CONFIG_DROP_TCP_CS_ERR (0x1<<1)
2574 #define TSTORM_ETH_CLIENT_CONFIG_DROP_TCP_CS_ERR_SHIFT 1
2575 #define TSTORM_ETH_CLIENT_CONFIG_DROP_TTL0 (0x1<<2)
2576 #define TSTORM_ETH_CLIENT_CONFIG_DROP_TTL0_SHIFT 2
2577 #define TSTORM_ETH_CLIENT_CONFIG_DROP_UDP_CS_ERR (0x1<<3)
2578 #define TSTORM_ETH_CLIENT_CONFIG_DROP_UDP_CS_ERR_SHIFT 3
2579 #define __TSTORM_ETH_CLIENT_CONFIG_RESERVED1 (0xFFF<<4)
2580 #define __TSTORM_ETH_CLIENT_CONFIG_RESERVED1_SHIFT 4
2586 * MAC filtering configuration parameters per port in Tstorm
2588 struct tstorm_eth_mac_filter_config {
2590 u32 ucast_accept_all;
2592 u32 mcast_accept_all;
2594 u32 bcast_accept_all;
2602 * common flag to indicate existance of TPA.
2604 struct tstorm_eth_tpa_exist {
2605 #if defined(__BIG_ENDIAN)
2609 #elif defined(__LITTLE_ENDIAN)
2619 * Three RX producers for ETH
2621 struct ustorm_eth_rx_producers {
2622 #if defined(__BIG_ENDIAN)
2625 #elif defined(__LITTLE_ENDIAN)
2629 #if defined(__BIG_ENDIAN)
2632 #elif defined(__LITTLE_ENDIAN)
2640 * per-port SAFC demo variables
2642 struct cmng_flags_per_port {
2643 u8 con_number[NUM_OF_PROTOCOLS];
2644 #if defined(__BIG_ENDIAN)
2646 u8 rate_shaping_enable;
2647 u8 cmng_protocol_enable;
2649 #elif defined(__LITTLE_ENDIAN)
2651 u8 cmng_protocol_enable;
2652 u8 rate_shaping_enable;
2659 * per-port rate shaping variables
2661 struct rate_shaping_vars_per_port {
2662 u32 rs_periodic_timeout;
2668 * per-port fairness variables
2670 struct fairness_vars_per_port {
2673 u32 fairness_timeout;
2678 * per-port SAFC variables
2680 struct safc_struct_per_port {
2681 #if defined(__BIG_ENDIAN)
2684 u8 safc_timeout_usec;
2685 #elif defined(__LITTLE_ENDIAN)
2686 u8 safc_timeout_usec;
2690 u16 cos_to_pause_mask[NUM_OF_SAFC_BITS];
2695 * Per-port congestion management variables
2697 struct cmng_struct_per_port {
2698 struct rate_shaping_vars_per_port rs_vars;
2699 struct fairness_vars_per_port fair_vars;
2700 struct safc_struct_per_port safc_vars;
2701 struct cmng_flags_per_port flags;
2706 * Protocol-common statistics collected by the Xstorm (per client)
2708 struct xstorm_per_client_stats {
2709 struct regpair total_sent_bytes;
2710 u32 total_sent_pkts;
2711 u32 unicast_pkts_sent;
2712 struct regpair unicast_bytes_sent;
2713 struct regpair multicast_bytes_sent;
2714 u32 multicast_pkts_sent;
2715 u32 broadcast_pkts_sent;
2716 struct regpair broadcast_bytes_sent;
2724 * Common statistics collected by the Xstorm (per port)
2726 struct xstorm_common_stats {
2727 struct xstorm_per_client_stats client_statistics[MAX_X_STAT_COUNTER_ID];
2732 * Protocol-common statistics collected by the Tstorm (per port)
2734 struct tstorm_per_port_stats {
2735 u32 mac_filter_discard;
2736 u32 xxoverflow_discard;
2737 u32 brb_truncate_discard;
2743 * Protocol-common statistics collected by the Tstorm (per client)
2745 struct tstorm_per_client_stats {
2746 struct regpair total_rcv_bytes;
2747 struct regpair rcv_unicast_bytes;
2748 struct regpair rcv_broadcast_bytes;
2749 struct regpair rcv_multicast_bytes;
2750 struct regpair rcv_error_bytes;
2751 u32 checksum_discard;
2752 u32 packets_too_big_discard;
2754 u32 rcv_unicast_pkts;
2755 u32 rcv_broadcast_pkts;
2756 u32 rcv_multicast_pkts;
2757 u32 no_buff_discard;
2765 * Protocol-common statistics collected by the Tstorm
2767 struct tstorm_common_stats {
2768 struct tstorm_per_port_stats port_statistics;
2769 struct tstorm_per_client_stats client_statistics[MAX_T_STAT_COUNTER_ID];
2773 * Eth statistics query structure for the eth_stats_query ramrod
2775 struct eth_stats_query {
2776 struct xstorm_common_stats xstorm_common;
2777 struct tstorm_common_stats tstorm_common;
2782 * per-vnic fairness variables
2784 struct fairness_vars_per_vn {
2785 u32 protocol_credit_delta[NUM_OF_PROTOCOLS];
2786 u32 vn_credit_delta;
2792 * FW version stored in the Xstorm RAM
2795 #if defined(__BIG_ENDIAN)
2800 #elif defined(__LITTLE_ENDIAN)
2807 #define FW_VERSION_OPTIMIZED (0x1<<0)
2808 #define FW_VERSION_OPTIMIZED_SHIFT 0
2809 #define FW_VERSION_BIG_ENDIEN (0x1<<1)
2810 #define FW_VERSION_BIG_ENDIEN_SHIFT 1
2811 #define FW_VERSION_CHIP_VERSION (0x3<<2)
2812 #define FW_VERSION_CHIP_VERSION_SHIFT 2
2813 #define __FW_VERSION_RESERVED (0xFFFFFFF<<4)
2814 #define __FW_VERSION_RESERVED_SHIFT 4
2819 * FW version stored in first line of pram
2821 struct pram_fw_version {
2827 #define PRAM_FW_VERSION_OPTIMIZED (0x1<<0)
2828 #define PRAM_FW_VERSION_OPTIMIZED_SHIFT 0
2829 #define PRAM_FW_VERSION_STORM_ID (0x3<<1)
2830 #define PRAM_FW_VERSION_STORM_ID_SHIFT 1
2831 #define PRAM_FW_VERSION_BIG_ENDIEN (0x1<<3)
2832 #define PRAM_FW_VERSION_BIG_ENDIEN_SHIFT 3
2833 #define PRAM_FW_VERSION_CHIP_VERSION (0x3<<4)
2834 #define PRAM_FW_VERSION_CHIP_VERSION_SHIFT 4
2835 #define __PRAM_FW_VERSION_RESERVED0 (0x3<<6)
2836 #define __PRAM_FW_VERSION_RESERVED0_SHIFT 6
2841 * a single rate shaping counter. can be used as protocol or vnic counter
2843 struct rate_shaping_counter {
2845 #if defined(__BIG_ENDIAN)
2848 #elif defined(__LITTLE_ENDIAN)
2856 * per-vnic rate shaping variables
2858 struct rate_shaping_vars_per_vn {
2859 struct rate_shaping_counter protocol_counters[NUM_OF_PROTOCOLS];
2860 struct rate_shaping_counter vn_counter;
2865 * The send queue element
2867 struct slow_path_element {
2869 u8 protocol_data[8];
2874 * eth/toe flags that indicate if to query
2876 struct stats_indication_flags {