drivers/net/chelsio/subr.c

   1 /*****************************************************************************
   2  *                                                                           *
   3  * File: subr.c                                                              *
   4  * $Revision: 1.27 $                                                         *
   5  * $Date: 2005/06/22 01:08:36 $                                              *
   6  * Description:                                                              *
   7  *  Various subroutines (intr,pio,etc.) used by Chelsio 10G Ethernet driver. *
   8  *  part of the Chelsio 10Gb Ethernet Driver.                                *
   9  *                                                                           *
  10  * This program is free software; you can redistribute it and/or modify      *
  11  * it under the terms of the GNU General Public License, version 2, as       *
  12  * published by the Free Software Foundation.                                *
  13  *                                                                           *
  14  * You should have received a copy of the GNU General Public License along   *
  15  * with this program; if not, write to the Free Software Foundation, Inc.,   *
  16  * 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.                 *
  17  *                                                                           *
  18  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR IMPLIED    *
  19  * WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF      *
  20  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.                     *
  21  *                                                                           *
  22  * http://www.chelsio.com                                                    *
  23  *                                                                           *
  24  * Copyright (c) 2003 - 2005 Chelsio Communications, Inc.                    *
  25  * All rights reserved.                                                      *
  26  *                                                                           *
  27  * Maintainers: maintainers@chelsio.com                                      *
  28  *                                                                           *
  29  * Authors: Dimitrios Michailidis   <dm@chelsio.com>                         *
  30  *          Tina Yang               <tainay@chelsio.com>                     *
  31  *          Felix Marti             <felix@chelsio.com>                      *
  32  *          Scott Bardone           <sbardone@chelsio.com>                   *
  33  *          Kurt Ottaway            <kottaway@chelsio.com>                   *
  34  *          Frank DiMambro          <frank@chelsio.com>                      *
  35  *                                                                           *
  36  * History:                                                                  *
  37  *                                                                           *
  38  ****************************************************************************/
  39
  40 #include "common.h"
  41 #include "elmer0.h"
  42 #include "regs.h"
  43 #include "gmac.h"
  44 #include "cphy.h"
  45 #include "sge.h"
  46 #include "tp.h"
  47 #include "espi.h"
  48
  49 /**
  50  *      t1_wait_op_done - wait until an operation is completed
  51  *      @adapter: the adapter performing the operation
  52  *      @reg: the register to check for completion
  53  *      @mask: a single-bit field within @reg that indicates completion
  54  *      @polarity: the value of the field when the operation is completed
  55  *      @attempts: number of check iterations
  56  *      @delay: delay in usecs between iterations
  57  *
  58  *      Wait until an operation is completed by checking a bit in a register
  59  *      up to @attempts times.  Returns %0 if the operation completes and %1
  60  *      otherwise.
  61  */
  62 static int t1_wait_op_done(adapter_t *adapter, int reg, u32 mask, int polarity,
  63                            int attempts, int delay)
  64 {
  65         while (1) {
  66                 u32 val = readl(adapter->regs + reg) & mask;
  67
  68                 if (!!val == polarity)
  69                         return 0;
  70                 if (--attempts == 0)
  71                         return 1;
  72                 if (delay)
  73                         udelay(delay);
  74         }
  75 }
  76
  77 #define TPI_ATTEMPTS 50
  78
  79 /*
  80  * Write a register over the TPI interface (unlocked and locked versions).
  81  */
  82 int __t1_tpi_write(adapter_t *adapter, u32 addr, u32 value)
  83 {
  84         int tpi_busy;
  85
  86         writel(addr, adapter->regs + A_TPI_ADDR);
  87         writel(value, adapter->regs + A_TPI_WR_DATA);
  88         writel(F_TPIWR, adapter->regs + A_TPI_CSR);
  89
  90         tpi_busy = t1_wait_op_done(adapter, A_TPI_CSR, F_TPIRDY, 1,
  91                                    TPI_ATTEMPTS, 3);
  92         if (tpi_busy)
  93                 CH_ALERT("%s: TPI write to 0x%x failed\n",
  94                          adapter->name, addr);
  95         return tpi_busy;
  96 }
  97
  98 int t1_tpi_write(adapter_t *adapter, u32 addr, u32 value)
  99 {
 100         int ret;
 101
 102         spin_lock(&adapter->tpi_lock);
 103         ret = __t1_tpi_write(adapter, addr, value);
 104         spin_unlock(&adapter->tpi_lock);
 105         return ret;
 106 }
 107
 108 /*
 109  * Read a register over the TPI interface (unlocked and locked versions).
 110  */
 111 int __t1_tpi_read(adapter_t *adapter, u32 addr, u32 *valp)
 112 {
 113         int tpi_busy;
 114
 115         writel(addr, adapter->regs + A_TPI_ADDR);
 116         writel(0, adapter->regs + A_TPI_CSR);
 117
 118         tpi_busy = t1_wait_op_done(adapter, A_TPI_CSR, F_TPIRDY, 1,
 119                                    TPI_ATTEMPTS, 3);
 120         if (tpi_busy)
 121                 CH_ALERT("%s: TPI read from 0x%x failed\n",
 122                          adapter->name, addr);
 123         else
 124                 *valp = readl(adapter->regs + A_TPI_RD_DATA);
 125         return tpi_busy;
 126 }
 127
 128 int t1_tpi_read(adapter_t *adapter, u32 addr, u32 *valp)
 129 {
 130         int ret;
 131
 132         spin_lock(&adapter->tpi_lock);
 133         ret = __t1_tpi_read(adapter, addr, valp);
 134         spin_unlock(&adapter->tpi_lock);
 135         return ret;
 136 }
 137
 138 /*
 139  * Set a TPI parameter.
 140  */
 141 static void t1_tpi_par(adapter_t *adapter, u32 value)
 142 {
 143         writel(V_TPIPAR(value), adapter->regs + A_TPI_PAR);
 144 }
 145
 146 /*
 147  * Called when a port's link settings change to propagate the new values to the
 148  * associated PHY and MAC.  After performing the common tasks it invokes an
 149  * OS-specific handler.
 150  */
 151 void t1_link_changed(adapter_t *adapter, int port_id)
 152 {
 153         int link_ok, speed, duplex, fc;
 154         struct cphy *phy = adapter->port[port_id].phy;
 155         struct link_config *lc = &adapter->port[port_id].link_config;
 156
 157         phy->ops->get_link_status(phy, &link_ok, &speed, &duplex, &fc);
 158
 159         lc->speed = speed < 0 ? SPEED_INVALID : speed;
 160         lc->duplex = duplex < 0 ? DUPLEX_INVALID : duplex;
 161         if (!(lc->requested_fc & PAUSE_AUTONEG))
 162                 fc = lc->requested_fc & (PAUSE_RX | PAUSE_TX);
 163
 164         if (link_ok && speed >= 0 && lc->autoneg == AUTONEG_ENABLE) {
 165                 /* Set MAC speed, duplex, and flow control to match PHY. */
 166                 struct cmac *mac = adapter->port[port_id].mac;
 167
 168                 mac->ops->set_speed_duplex_fc(mac, speed, duplex, fc);
 169                 lc->fc = (unsigned char)fc;
 170         }
 171         t1_link_negotiated(adapter, port_id, link_ok, speed, duplex, fc);
 172 }
 173
 174 static int t1_pci_intr_handler(adapter_t *adapter)
 175 {
 176         u32 pcix_cause;
 177
 178         pci_read_config_dword(adapter->pdev, A_PCICFG_INTR_CAUSE, &pcix_cause);
 179
 180         if (pcix_cause) {
 181                 pci_write_config_dword(adapter->pdev, A_PCICFG_INTR_CAUSE,
 182                                        pcix_cause);
 183                 t1_fatal_err(adapter);    /* PCI errors are fatal */
 184         }
 185         return 0;
 186 }
 187
 188
 189 /*
 190  * Wait until Elmer's MI1 interface is ready for new operations.
 191  */
 192 static int mi1_wait_until_ready(adapter_t *adapter, int mi1_reg)
 193 {
 194         int attempts = 100, busy;
 195
 196         do {
 197                 u32 val;
 198
 199                 __t1_tpi_read(adapter, mi1_reg, &val);
 200                 busy = val & F_MI1_OP_BUSY;
 201                 if (busy)
 202                         udelay(10);
 203         } while (busy && --attempts);
 204         if (busy)
 205                 CH_ALERT("%s: MDIO operation timed out\n",
 206                          adapter->name);
 207         return busy;
 208 }
 209
 210 /*
 211  * MI1 MDIO initialization.
 212  */
 213 static void mi1_mdio_init(adapter_t *adapter, const struct board_info *bi)
 214 {
 215         u32 clkdiv = bi->clock_elmer0 / (2 * bi->mdio_mdc) - 1;
 216         u32 val = F_MI1_PREAMBLE_ENABLE | V_MI1_MDI_INVERT(bi->mdio_mdiinv) |
 217                 V_MI1_MDI_ENABLE(bi->mdio_mdien) | V_MI1_CLK_DIV(clkdiv);
 218
 219         if (!(bi->caps & SUPPORTED_10000baseT_Full))
 220                 val |= V_MI1_SOF(1);
 221         t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_CFG, val);
 222 }
 223
 224 static int mi1_mdio_ext_read(adapter_t *adapter, int phy_addr, int mmd_addr,
 225                              int reg_addr, unsigned int *valp)
 226 {
 227         u32 addr = V_MI1_REG_ADDR(mmd_addr) | V_MI1_PHY_ADDR(phy_addr);
 228
 229         spin_lock(&adapter->tpi_lock);
 230
 231         /* Write the address we want. */
 232         __t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_ADDR, addr);
 233         __t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_DATA, reg_addr);
 234         __t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_OP,
 235                        MI1_OP_INDIRECT_ADDRESS);
 236         mi1_wait_until_ready(adapter, A_ELMER0_PORT0_MI1_OP);
 237
 238         /* Write the operation we want. */
 239         __t1_tpi_write(adapter,
 240                         A_ELMER0_PORT0_MI1_OP, MI1_OP_INDIRECT_READ);
 241         mi1_wait_until_ready(adapter, A_ELMER0_PORT0_MI1_OP);
 242
 243         /* Read the data. */
 244         __t1_tpi_read(adapter, A_ELMER0_PORT0_MI1_DATA, valp);
 245         spin_unlock(&adapter->tpi_lock);
 246         return 0;
 247 }
 248
 249 static int mi1_mdio_ext_write(adapter_t *adapter, int phy_addr, int mmd_addr,
 250                               int reg_addr, unsigned int val)
 251 {
 252         u32 addr = V_MI1_REG_ADDR(mmd_addr) | V_MI1_PHY_ADDR(phy_addr);
 253
 254         spin_lock(&adapter->tpi_lock);
 255
 256         /* Write the address we want. */
 257         __t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_ADDR, addr);
 258         __t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_DATA, reg_addr);
 259         __t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_OP,
 260                        MI1_OP_INDIRECT_ADDRESS);
 261         mi1_wait_until_ready(adapter, A_ELMER0_PORT0_MI1_OP);
 262
 263         /* Write the data. */
 264         __t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_DATA, val);
 265         __t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_OP, MI1_OP_INDIRECT_WRITE);
 266         mi1_wait_until_ready(adapter, A_ELMER0_PORT0_MI1_OP);
 267         spin_unlock(&adapter->tpi_lock);
 268         return 0;
 269 }
 270
 271 static struct mdio_ops mi1_mdio_ext_ops = {
 272         mi1_mdio_init,
 273         mi1_mdio_ext_read,
 274         mi1_mdio_ext_write
 275 };
 276
 277 enum {
 278         CH_BRD_T110_1CU,
 279         CH_BRD_N110_1F,
 280         CH_BRD_N210_1F,
 281         CH_BRD_T210_1F,
 282         CH_BRD_T210_1CU,
 283         CH_BRD_N204_4CU,
 284 };
 285
 286 static struct board_info t1_board[] = {
 287
 288 { CHBT_BOARD_CHT110, 1/*ports#*/,
 289   SUPPORTED_10000baseT_Full /*caps*/, CHBT_TERM_T1,
 290   CHBT_MAC_PM3393, CHBT_PHY_MY3126,
 291   125000000/*clk-core*/, 150000000/*clk-mc3*/, 125000000/*clk-mc4*/,
 292   1/*espi-ports*/, 0/*clk-cspi*/, 44/*clk-elmer0*/, 1/*mdien*/,
 293   1/*mdiinv*/, 1/*mdc*/, 1/*phybaseaddr*/, &t1_pm3393_ops,
 294   &t1_my3126_ops, &mi1_mdio_ext_ops,
 295   "Chelsio T110 1x10GBase-CX4 TOE" },
 296
 297 { CHBT_BOARD_N110, 1/*ports#*/,
 298   SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE /*caps*/, CHBT_TERM_T1,
 299   CHBT_MAC_PM3393, CHBT_PHY_88X2010,
 300   125000000/*clk-core*/, 0/*clk-mc3*/, 0/*clk-mc4*/,
 301   1/*espi-ports*/, 0/*clk-cspi*/, 44/*clk-elmer0*/, 0/*mdien*/,
 302   0/*mdiinv*/, 1/*mdc*/, 0/*phybaseaddr*/, &t1_pm3393_ops,
 303   &t1_mv88x201x_ops, &mi1_mdio_ext_ops,
 304   "Chelsio N110 1x10GBaseX NIC" },
 305
 306 { CHBT_BOARD_N210, 1/*ports#*/,
 307   SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE /*caps*/, CHBT_TERM_T2,
 308   CHBT_MAC_PM3393, CHBT_PHY_88X2010,
 309   125000000/*clk-core*/, 0/*clk-mc3*/, 0/*clk-mc4*/,
 310   1/*espi-ports*/, 0/*clk-cspi*/, 44/*clk-elmer0*/, 0/*mdien*/,
 311   0/*mdiinv*/, 1/*mdc*/, 0/*phybaseaddr*/, &t1_pm3393_ops,
 312   &t1_mv88x201x_ops, &mi1_mdio_ext_ops,
 313   "Chelsio N210 1x10GBaseX NIC" },
 314
 315 { CHBT_BOARD_CHT210, 1/*ports#*/,
 316   SUPPORTED_10000baseT_Full /*caps*/, CHBT_TERM_T2,
 317   CHBT_MAC_PM3393, CHBT_PHY_88X2010,
 318   125000000/*clk-core*/, 133000000/*clk-mc3*/, 125000000/*clk-mc4*/,
 319   1/*espi-ports*/, 0/*clk-cspi*/, 44/*clk-elmer0*/, 0/*mdien*/,
 320   0/*mdiinv*/, 1/*mdc*/, 0/*phybaseaddr*/, &t1_pm3393_ops,
 321   &t1_mv88x201x_ops, &mi1_mdio_ext_ops,
 322   "Chelsio T210 1x10GBaseX TOE" },
 323
 324 { CHBT_BOARD_CHT210, 1/*ports#*/,
 325   SUPPORTED_10000baseT_Full /*caps*/, CHBT_TERM_T2,
 326   CHBT_MAC_PM3393, CHBT_PHY_MY3126,
 327   125000000/*clk-core*/, 133000000/*clk-mc3*/, 125000000/*clk-mc4*/,
 328   1/*espi-ports*/, 0/*clk-cspi*/, 44/*clk-elmer0*/, 1/*mdien*/,
 329   1/*mdiinv*/, 1/*mdc*/, 1/*phybaseaddr*/, &t1_pm3393_ops,
 330   &t1_my3126_ops, &mi1_mdio_ext_ops,
 331   "Chelsio T210 1x10GBase-CX4 TOE" },
 332
 333
 334 };
 335
 336 struct pci_device_id t1_pci_tbl[] = {
 337         CH_DEVICE(8, 0, CH_BRD_T110_1CU),
 338         CH_DEVICE(8, 1, CH_BRD_T110_1CU),
 339         CH_DEVICE(7, 0, CH_BRD_N110_1F),
 340         CH_DEVICE(10, 1, CH_BRD_N210_1F),
 341         CH_DEVICE(11, 1, CH_BRD_T210_1F),
 342         CH_DEVICE(14, 1, CH_BRD_T210_1CU),
 343         CH_DEVICE(16, 1, CH_BRD_N204_4CU),
 344         { 0 }
 345 };
 346
 347 MODULE_DEVICE_TABLE(pci, t1_pci_tbl);
 348
 349 /*
 350  * Return the board_info structure with a given index.  Out-of-range indices
 351  * return NULL.
 352  */
 353 const struct board_info *t1_get_board_info(unsigned int board_id)
 354 {
 355         return board_id < ARRAY_SIZE(t1_board) ? &t1_board[board_id] : NULL;
 356 }
 357
 358 struct chelsio_vpd_t {
 359         u32 format_version;
 360         u8 serial_number[16];
 361         u8 mac_base_address[6];
 362         u8 pad[2];           /* make multiple-of-4 size requirement explicit */
 363 };
 364
 365 #define EEPROMSIZE        (8 * 1024)
 366 #define EEPROM_MAX_POLL   4
 367
 368 /*
 369  * Read SEEPROM. A zero is written to the flag register when the addres is
 370  * written to the Control register. The hardware device will set the flag to a
 371  * one when 4B have been transferred to the Data register.
 372  */
 373 int t1_seeprom_read(adapter_t *adapter, u32 addr, u32 *data)
 374 {
 375         int i = EEPROM_MAX_POLL;
 376         u16 val;
 377
 378         if (addr >= EEPROMSIZE || (addr & 3))
 379                 return -EINVAL;
 380
 381         pci_write_config_word(adapter->pdev, A_PCICFG_VPD_ADDR, (u16)addr);
 382         do {
 383                 udelay(50);
 384                 pci_read_config_word(adapter->pdev, A_PCICFG_VPD_ADDR, &val);
 385         } while (!(val & F_VPD_OP_FLAG) && --i);
 386
 387         if (!(val & F_VPD_OP_FLAG)) {
 388                 CH_ERR("%s: reading EEPROM address 0x%x failed\n",
 389                        adapter->name, addr);
 390                 return -EIO;
 391         }
 392         pci_read_config_dword(adapter->pdev, A_PCICFG_VPD_DATA, data);
 393         *data = le32_to_cpu(*data);
 394         return 0;
 395 }
 396
 397 static int t1_eeprom_vpd_get(adapter_t *adapter, struct chelsio_vpd_t *vpd)
 398 {
 399         int addr, ret = 0;
 400
 401         for (addr = 0; !ret && addr < sizeof(*vpd); addr += sizeof(u32))
 402                 ret = t1_seeprom_read(adapter, addr,
 403                                       (u32 *)((u8 *)vpd + addr));
 404
 405         return ret;
 406 }
 407
 408 /*
 409  * Read a port's MAC address from the VPD ROM.
 410  */
 411 static int vpd_macaddress_get(adapter_t *adapter, int index, u8 mac_addr[])
 412 {
 413         struct chelsio_vpd_t vpd;
 414
 415         if (t1_eeprom_vpd_get(adapter, &vpd))
 416                 return 1;
 417         memcpy(mac_addr, vpd.mac_base_address, 5);
 418         mac_addr[5] = vpd.mac_base_address[5] + index;
 419         return 0;
 420 }
 421
 422 /*
 423  * Set up the MAC/PHY according to the requested link settings.
 424  *
 425  * If the PHY can auto-negotiate first decide what to advertise, then
 426  * enable/disable auto-negotiation as desired and reset.
 427  *
 428  * If the PHY does not auto-negotiate we just reset it.
 429  *
 430  * If auto-negotiation is off set the MAC to the proper speed/duplex/FC,
 431  * otherwise do it later based on the outcome of auto-negotiation.
 432  */
 433 int t1_link_start(struct cphy *phy, struct cmac *mac, struct link_config *lc)
 434 {
 435         unsigned int fc = lc->requested_fc & (PAUSE_RX | PAUSE_TX);
 436
 437         if (lc->supported & SUPPORTED_Autoneg) {
 438                 lc->advertising &= ~(ADVERTISED_ASYM_PAUSE | ADVERTISED_PAUSE);
 439                 if (fc) {
 440                         if (fc == ((PAUSE_RX | PAUSE_TX) &
 441                                    (mac->adapter->params.nports < 2)))
 442                                 lc->advertising |= ADVERTISED_PAUSE;
 443                         else {
 444                                 lc->advertising |= ADVERTISED_ASYM_PAUSE;
 445                                 if (fc == PAUSE_RX)
 446                                         lc->advertising |= ADVERTISED_PAUSE;
 447                         }
 448                 }
 449                 phy->ops->advertise(phy, lc->advertising);
 450
 451                 if (lc->autoneg == AUTONEG_DISABLE) {
 452                         lc->speed = lc->requested_speed;
 453                         lc->duplex = lc->requested_duplex;
 454                         lc->fc = (unsigned char)fc;
 455                         mac->ops->set_speed_duplex_fc(mac, lc->speed,
 456                                                       lc->duplex, fc);
 457                         /* Also disables autoneg */
 458                         phy->state = PHY_AUTONEG_RDY;
 459                         phy->ops->set_speed_duplex(phy, lc->speed, lc->duplex);
 460                         phy->ops->reset(phy, 0);
 461                 } else {
 462                         phy->state = PHY_AUTONEG_EN;
 463                         phy->ops->autoneg_enable(phy); /* also resets PHY */
 464                 }
 465         } else {
 466                 phy->state = PHY_AUTONEG_RDY;
 467                 mac->ops->set_speed_duplex_fc(mac, -1, -1, fc);
 468                 lc->fc = (unsigned char)fc;
 469                 phy->ops->reset(phy, 0);
 470         }
 471         return 0;
 472 }
 473
 474 /*
 475  * External interrupt handler for boards using elmer0.
 476  */
 477 int t1_elmer0_ext_intr_handler(adapter_t *adapter)
 478 {
 479         struct cphy *phy;
 480         int phy_cause;
 481         u32 cause;
 482
 483         t1_tpi_read(adapter, A_ELMER0_INT_CAUSE, &cause);
 484
 485         switch (board_info(adapter)->board) {
 486         case CHBT_BOARD_CHT210:
 487         case CHBT_BOARD_N210:
 488         case CHBT_BOARD_N110:
 489                 if (cause & ELMER0_GP_BIT6) { /* Marvell 88x2010 interrupt */
 490                         phy = adapter->port[0].phy;
 491                         phy_cause = phy->ops->interrupt_handler(phy);
 492                         if (phy_cause & cphy_cause_link_change)
 493                                 t1_link_changed(adapter, 0);
 494                 }
 495                 break;
 496         case CHBT_BOARD_8000:
 497         case CHBT_BOARD_CHT110:
 498                 CH_DBG(adapter, INTR, "External interrupt cause 0x%x\n",
 499                        cause);
 500                 if (cause & ELMER0_GP_BIT1) {        /* PMC3393 INTB */
 501                         struct cmac *mac = adapter->port[0].mac;
 502
 503                         mac->ops->interrupt_handler(mac);
 504                 }
 505                 if (cause & ELMER0_GP_BIT5) {        /* XPAK MOD_DETECT */
 506                         u32 mod_detect;
 507
 508                         t1_tpi_read(adapter,
 509                                         A_ELMER0_GPI_STAT, &mod_detect);
 510                         CH_MSG(adapter, INFO, LINK, "XPAK %s\n",
 511                                mod_detect ? "removed" : "inserted");
 512                 }
 513                 break;
 514         }
 515         t1_tpi_write(adapter, A_ELMER0_INT_CAUSE, cause);
 516         return 0;
 517 }
 518
 519 /* Enables all interrupts. */
 520 void t1_interrupts_enable(adapter_t *adapter)
 521 {
 522         unsigned int i;
 523
 524         adapter->slow_intr_mask = F_PL_INTR_SGE_ERR | F_PL_INTR_TP;
 525
 526         t1_sge_intr_enable(adapter->sge);
 527         t1_tp_intr_enable(adapter->tp);
 528         if (adapter->espi) {
 529                 adapter->slow_intr_mask |= F_PL_INTR_ESPI;
 530                 t1_espi_intr_enable(adapter->espi);
 531         }
 532
 533         /* Enable MAC/PHY interrupts for each port. */
 534         for_each_port(adapter, i) {
 535                 adapter->port[i].mac->ops->interrupt_enable(adapter->port[i].mac);
 536                 adapter->port[i].phy->ops->interrupt_enable(adapter->port[i].phy);
 537         }
 538
 539         /* Enable PCIX & external chip interrupts on ASIC boards. */
 540         if (t1_is_asic(adapter)) {
 541                 u32 pl_intr = readl(adapter->regs + A_PL_ENABLE);
 542
 543                 /* PCI-X interrupts */
 544                 pci_write_config_dword(adapter->pdev, A_PCICFG_INTR_ENABLE,
 545                                        0xffffffff);
 546
 547                 adapter->slow_intr_mask |= F_PL_INTR_EXT | F_PL_INTR_PCIX;
 548                 pl_intr |= F_PL_INTR_EXT | F_PL_INTR_PCIX;
 549                 writel(pl_intr, adapter->regs + A_PL_ENABLE);
 550         }
 551 }
 552
 553 /* Disables all interrupts. */
 554 void t1_interrupts_disable(adapter_t* adapter)
 555 {
 556         unsigned int i;
 557
 558         t1_sge_intr_disable(adapter->sge);
 559         t1_tp_intr_disable(adapter->tp);
 560         if (adapter->espi)
 561                 t1_espi_intr_disable(adapter->espi);
 562
 563         /* Disable MAC/PHY interrupts for each port. */
 564         for_each_port(adapter, i) {
 565                 adapter->port[i].mac->ops->interrupt_disable(adapter->port[i].mac);
 566                 adapter->port[i].phy->ops->interrupt_disable(adapter->port[i].phy);
 567         }
 568
 569         /* Disable PCIX & external chip interrupts. */
 570         if (t1_is_asic(adapter))
 571                 writel(0, adapter->regs + A_PL_ENABLE);
 572
 573         /* PCI-X interrupts */
 574         pci_write_config_dword(adapter->pdev, A_PCICFG_INTR_ENABLE, 0);
 575
 576         adapter->slow_intr_mask = 0;
 577 }
 578
 579 /* Clears all interrupts */
 580 void t1_interrupts_clear(adapter_t* adapter)
 581 {
 582         unsigned int i;
 583
 584         t1_sge_intr_clear(adapter->sge);
 585         t1_tp_intr_clear(adapter->tp);
 586         if (adapter->espi)
 587                 t1_espi_intr_clear(adapter->espi);
 588
 589         /* Clear MAC/PHY interrupts for each port. */
 590         for_each_port(adapter, i) {
 591                 adapter->port[i].mac->ops->interrupt_clear(adapter->port[i].mac);
 592                 adapter->port[i].phy->ops->interrupt_clear(adapter->port[i].phy);
 593         }
 594
 595         /* Enable interrupts for external devices. */
 596         if (t1_is_asic(adapter)) {
 597                 u32 pl_intr = readl(adapter->regs + A_PL_CAUSE);
 598
 599                 writel(pl_intr | F_PL_INTR_EXT | F_PL_INTR_PCIX,
 600                        adapter->regs + A_PL_CAUSE);
 601         }
 602
 603         /* PCI-X interrupts */
 604         pci_write_config_dword(adapter->pdev, A_PCICFG_INTR_CAUSE, 0xffffffff);
 605 }
 606
 607 /*
 608  * Slow path interrupt handler for ASICs.
 609  */
 610 static int asic_slow_intr(adapter_t *adapter)
 611 {
 612         u32 cause = readl(adapter->regs + A_PL_CAUSE);
 613
 614         cause &= adapter->slow_intr_mask;
 615         if (!cause)
 616                 return 0;
 617         if (cause & F_PL_INTR_SGE_ERR)
 618                 t1_sge_intr_error_handler(adapter->sge);
 619         if (cause & F_PL_INTR_TP)
 620                 t1_tp_intr_handler(adapter->tp);
 621         if (cause & F_PL_INTR_ESPI)
 622                 t1_espi_intr_handler(adapter->espi);
 623         if (cause & F_PL_INTR_PCIX)
 624                 t1_pci_intr_handler(adapter);
 625         if (cause & F_PL_INTR_EXT)
 626                 t1_elmer0_ext_intr_handler(adapter);
 627
 628         /* Clear the interrupts just processed. */
 629         writel(cause, adapter->regs + A_PL_CAUSE);
 630         readl(adapter->regs + A_PL_CAUSE); /* flush writes */
 631         return 1;
 632 }
 633
 634 int t1_slow_intr_handler(adapter_t *adapter)
 635 {
 636         return asic_slow_intr(adapter);
 637 }
 638
 639 /* Power sequencing is a work-around for Intel's XPAKs. */
 640 static void power_sequence_xpak(adapter_t* adapter)
 641 {
 642         u32 mod_detect;
 643         u32 gpo;
 644
 645         /* Check for XPAK */
 646         t1_tpi_read(adapter, A_ELMER0_GPI_STAT, &mod_detect);
 647         if (!(ELMER0_GP_BIT5 & mod_detect)) {
 648                 /* XPAK is present */
 649                 t1_tpi_read(adapter, A_ELMER0_GPO, &gpo);
 650                 gpo |= ELMER0_GP_BIT18;
 651                 t1_tpi_write(adapter, A_ELMER0_GPO, gpo);
 652         }
 653 }
 654
 655 int __devinit t1_get_board_rev(adapter_t *adapter, const struct board_info *bi,
 656                                struct adapter_params *p)
 657 {
 658         p->chip_version = bi->chip_term;
 659         p->is_asic = (p->chip_version != CHBT_TERM_FPGA);
 660         if (p->chip_version == CHBT_TERM_T1 ||
 661             p->chip_version == CHBT_TERM_T2 ||
 662             p->chip_version == CHBT_TERM_FPGA) {
 663                 u32 val = readl(adapter->regs + A_TP_PC_CONFIG);
 664
 665                 val = G_TP_PC_REV(val);
 666                 if (val == 2)
 667                         p->chip_revision = TERM_T1B;
 668                 else if (val == 3)
 669                         p->chip_revision = TERM_T2;
 670                 else
 671                         return -1;
 672         } else
 673                 return -1;
 674         return 0;
 675 }
 676
 677 /*
 678  * Enable board components other than the Chelsio chip, such as external MAC
 679  * and PHY.
 680  */
 681 static int board_init(adapter_t *adapter, const struct board_info *bi)
 682 {
 683         switch (bi->board) {
 684         case CHBT_BOARD_8000:
 685         case CHBT_BOARD_N110:
 686         case CHBT_BOARD_N210:
 687         case CHBT_BOARD_CHT210:
 688         case CHBT_BOARD_COUGAR:
 689                 t1_tpi_par(adapter, 0xf);
 690                 t1_tpi_write(adapter, A_ELMER0_GPO, 0x800);
 691                 break;
 692         case CHBT_BOARD_CHT110:
 693                 t1_tpi_par(adapter, 0xf);
 694                 t1_tpi_write(adapter, A_ELMER0_GPO, 0x1800);
 695
 696                 /* TBD XXX Might not need.  This fixes a problem
 697                  *         described in the Intel SR XPAK errata.
 698                  */
 699                 power_sequence_xpak(adapter);
 700                 break;
 701         }
 702         return 0;
 703 }
 704
 705 /*
 706  * Initialize and configure the Terminator HW modules.  Note that external
 707  * MAC and PHYs are initialized separately.
 708  */
 709 int t1_init_hw_modules(adapter_t *adapter)
 710 {
 711         int err = -EIO;
 712         const struct board_info *bi = board_info(adapter);
 713
 714         if (!bi->clock_mc4) {
 715                 u32 val = readl(adapter->regs + A_MC4_CFG);
 716
 717                 writel(val | F_READY | F_MC4_SLOW, adapter->regs + A_MC4_CFG);
 718                 writel(F_M_BUS_ENABLE | F_TCAM_RESET,
 719                        adapter->regs + A_MC5_CONFIG);
 720         }
 721
 722         if (adapter->espi && t1_espi_init(adapter->espi, bi->chip_mac,
 723                                           bi->espi_nports))
 724                 goto out_err;
 725
 726         if (t1_tp_reset(adapter->tp, &adapter->params.tp, bi->clock_core))
 727                 goto out_err;
 728
 729         err = t1_sge_configure(adapter->sge, &adapter->params.sge);
 730         if (err)
 731                 goto out_err;
 732
 733         err = 0;
 734  out_err:
 735         return err;
 736 }
 737
 738 /*
 739  * Determine a card's PCI mode.
 740  */
 741 static void __devinit get_pci_mode(adapter_t *adapter, struct chelsio_pci_params *p)
 742 {
 743         static const unsigned short speed_map[] = { 33, 66, 100, 133 };
 744         u32 pci_mode;
 745
 746         pci_read_config_dword(adapter->pdev, A_PCICFG_MODE, &pci_mode);
 747         p->speed = speed_map[G_PCI_MODE_CLK(pci_mode)];
 748         p->width = (pci_mode & F_PCI_MODE_64BIT) ? 64 : 32;
 749         p->is_pcix = (pci_mode & F_PCI_MODE_PCIX) != 0;
 750 }
 751
 752 /*
 753  * Release the structures holding the SW per-Terminator-HW-module state.
 754  */
 755 void t1_free_sw_modules(adapter_t *adapter)
 756 {
 757         unsigned int i;
 758
 759         for_each_port(adapter, i) {
 760                 struct cmac *mac = adapter->port[i].mac;
 761                 struct cphy *phy = adapter->port[i].phy;
 762
 763                 if (mac)
 764                         mac->ops->destroy(mac);
 765                 if (phy)
 766                         phy->ops->destroy(phy);
 767         }
 768
 769         if (adapter->sge)
 770                 t1_sge_destroy(adapter->sge);
 771         if (adapter->tp)
 772                 t1_tp_destroy(adapter->tp);
 773         if (adapter->espi)
 774                 t1_espi_destroy(adapter->espi);
 775 }
 776
 777 static void __devinit init_link_config(struct link_config *lc,
 778                                        const struct board_info *bi)
 779 {
 780         lc->supported = bi->caps;
 781         lc->requested_speed = lc->speed = SPEED_INVALID;
 782         lc->requested_duplex = lc->duplex = DUPLEX_INVALID;
 783         lc->requested_fc = lc->fc = PAUSE_RX | PAUSE_TX;
 784         if (lc->supported & SUPPORTED_Autoneg) {
 785                 lc->advertising = lc->supported;
 786                 lc->autoneg = AUTONEG_ENABLE;
 787                 lc->requested_fc |= PAUSE_AUTONEG;
 788         } else {
 789                 lc->advertising = 0;
 790                 lc->autoneg = AUTONEG_DISABLE;
 791         }
 792 }
 793
 794
 795 /*
 796  * Allocate and initialize the data structures that hold the SW state of
 797  * the Terminator HW modules.
 798  */
 799 int __devinit t1_init_sw_modules(adapter_t *adapter,
 800                                  const struct board_info *bi)
 801 {
 802         unsigned int i;
 803
 804         adapter->params.brd_info = bi;
 805         adapter->params.nports = bi->port_number;
 806         adapter->params.stats_update_period = bi->gmac->stats_update_period;
 807
 808         adapter->sge = t1_sge_create(adapter, &adapter->params.sge);
 809         if (!adapter->sge) {
 810                 CH_ERR("%s: SGE initialization failed\n",
 811                        adapter->name);
 812                 goto error;
 813         }
 814
 815         if (bi->espi_nports && !(adapter->espi = t1_espi_create(adapter))) {
 816                 CH_ERR("%s: ESPI initialization failed\n",
 817                        adapter->name);
 818                 goto error;
 819         }
 820
 821         adapter->tp = t1_tp_create(adapter, &adapter->params.tp);
 822         if (!adapter->tp) {
 823                 CH_ERR("%s: TP initialization failed\n",
 824                        adapter->name);
 825                 goto error;
 826         }
 827
 828         board_init(adapter, bi);
 829         bi->mdio_ops->init(adapter, bi);
 830         if (bi->gphy->reset)
 831                 bi->gphy->reset(adapter);
 832         if (bi->gmac->reset)
 833                 bi->gmac->reset(adapter);
 834
 835         for_each_port(adapter, i) {
 836                 u8 hw_addr[6];
 837                 struct cmac *mac;
 838                 int phy_addr = bi->mdio_phybaseaddr + i;
 839
 840                 adapter->port[i].phy = bi->gphy->create(adapter, phy_addr,
 841                                                         bi->mdio_ops);
 842                 if (!adapter->port[i].phy) {
 843                         CH_ERR("%s: PHY %d initialization failed\n",
 844                                adapter->name, i);
 845                         goto error;
 846                 }
 847
 848                 adapter->port[i].mac = mac = bi->gmac->create(adapter, i);
 849                 if (!mac) {
 850                         CH_ERR("%s: MAC %d initialization failed\n",
 851                                adapter->name, i);
 852                         goto error;
 853                 }
 854
 855                 /*
 856                  * Get the port's MAC addresses either from the EEPROM if one
 857                  * exists or the one hardcoded in the MAC.
 858                  */
 859                 if (!t1_is_asic(adapter) || bi->chip_mac == CHBT_MAC_DUMMY)
 860                         mac->ops->macaddress_get(mac, hw_addr);
 861                 else if (vpd_macaddress_get(adapter, i, hw_addr)) {
 862                         CH_ERR("%s: could not read MAC address from VPD ROM\n",
 863                                adapter->port[i].dev->name);
 864                         goto error;
 865                 }
 866                 memcpy(adapter->port[i].dev->dev_addr, hw_addr, ETH_ALEN);
 867                 init_link_config(&adapter->port[i].link_config, bi);
 868         }
 869
 870         get_pci_mode(adapter, &adapter->params.pci);
 871         t1_interrupts_clear(adapter);
 872         return 0;
 873
 874 error:
 875         t1_free_sw_modules(adapter);
 876         return -1;
 877 }