1 /*******************************************************************************
3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2006 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *******************************************************************************/
30 * Shared functions for accessing and configuring the MAC
36 static int32_t e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask);
37 static void e1000_swfw_sync_release(struct e1000_hw *hw, uint16_t mask);
38 static int32_t e1000_read_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t *data);
39 static int32_t e1000_write_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t data);
40 static int32_t e1000_get_software_semaphore(struct e1000_hw *hw);
41 static void e1000_release_software_semaphore(struct e1000_hw *hw);
43 static uint8_t e1000_arc_subsystem_valid(struct e1000_hw *hw);
44 static int32_t e1000_check_downshift(struct e1000_hw *hw);
45 static int32_t e1000_check_polarity(struct e1000_hw *hw, e1000_rev_polarity *polarity);
46 static void e1000_clear_hw_cntrs(struct e1000_hw *hw);
47 static void e1000_clear_vfta(struct e1000_hw *hw);
48 static int32_t e1000_commit_shadow_ram(struct e1000_hw *hw);
49 static int32_t e1000_config_dsp_after_link_change(struct e1000_hw *hw, boolean_t link_up);
50 static int32_t e1000_config_fc_after_link_up(struct e1000_hw *hw);
51 static int32_t e1000_detect_gig_phy(struct e1000_hw *hw);
52 static int32_t e1000_erase_ich8_4k_segment(struct e1000_hw *hw, uint32_t bank);
53 static int32_t e1000_get_auto_rd_done(struct e1000_hw *hw);
54 static int32_t e1000_get_cable_length(struct e1000_hw *hw, uint16_t *min_length, uint16_t *max_length);
55 static int32_t e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw);
56 static int32_t e1000_get_phy_cfg_done(struct e1000_hw *hw);
57 static int32_t e1000_get_software_flag(struct e1000_hw *hw);
58 static int32_t e1000_ich8_cycle_init(struct e1000_hw *hw);
59 static int32_t e1000_ich8_flash_cycle(struct e1000_hw *hw, uint32_t timeout);
60 static int32_t e1000_id_led_init(struct e1000_hw *hw);
61 static int32_t e1000_init_lcd_from_nvm_config_region(struct e1000_hw *hw, uint32_t cnf_base_addr, uint32_t cnf_size);
62 static int32_t e1000_init_lcd_from_nvm(struct e1000_hw *hw);
63 static void e1000_init_rx_addrs(struct e1000_hw *hw);
64 static void e1000_initialize_hardware_bits(struct e1000_hw *hw);
65 static boolean_t e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw);
66 static int32_t e1000_kumeran_lock_loss_workaround(struct e1000_hw *hw);
67 static int32_t e1000_mng_enable_host_if(struct e1000_hw *hw);
68 static int32_t e1000_mng_host_if_write(struct e1000_hw *hw, uint8_t *buffer, uint16_t length, uint16_t offset, uint8_t *sum);
69 static int32_t e1000_mng_write_cmd_header(struct e1000_hw* hw, struct e1000_host_mng_command_header* hdr);
70 static int32_t e1000_mng_write_commit(struct e1000_hw *hw);
71 static int32_t e1000_phy_ife_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info);
72 static int32_t e1000_phy_igp_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info);
73 static int32_t e1000_read_eeprom_eerd(struct e1000_hw *hw, uint16_t offset, uint16_t words, uint16_t *data);
74 static int32_t e1000_write_eeprom_eewr(struct e1000_hw *hw, uint16_t offset, uint16_t words, uint16_t *data);
75 static int32_t e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd);
76 static int32_t e1000_phy_m88_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info);
77 static void e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw);
78 static int32_t e1000_read_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t *data);
79 static int32_t e1000_verify_write_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t byte);
80 static int32_t e1000_write_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t byte);
81 static int32_t e1000_read_ich8_word(struct e1000_hw *hw, uint32_t index, uint16_t *data);
82 static int32_t e1000_read_ich8_data(struct e1000_hw *hw, uint32_t index, uint32_t size, uint16_t *data);
83 static int32_t e1000_write_ich8_data(struct e1000_hw *hw, uint32_t index, uint32_t size, uint16_t data);
84 static int32_t e1000_read_eeprom_ich8(struct e1000_hw *hw, uint16_t offset, uint16_t words, uint16_t *data);
85 static int32_t e1000_write_eeprom_ich8(struct e1000_hw *hw, uint16_t offset, uint16_t words, uint16_t *data);
86 static void e1000_release_software_flag(struct e1000_hw *hw);
87 static int32_t e1000_set_d3_lplu_state(struct e1000_hw *hw, boolean_t active);
88 static int32_t e1000_set_d0_lplu_state(struct e1000_hw *hw, boolean_t active);
89 static int32_t e1000_set_pci_ex_no_snoop(struct e1000_hw *hw, uint32_t no_snoop);
90 static void e1000_set_pci_express_master_disable(struct e1000_hw *hw);
91 static int32_t e1000_wait_autoneg(struct e1000_hw *hw);
92 static void e1000_write_reg_io(struct e1000_hw *hw, uint32_t offset, uint32_t value);
93 static int32_t e1000_set_phy_type(struct e1000_hw *hw);
94 static void e1000_phy_init_script(struct e1000_hw *hw);
95 static int32_t e1000_setup_copper_link(struct e1000_hw *hw);
96 static int32_t e1000_setup_fiber_serdes_link(struct e1000_hw *hw);
97 static int32_t e1000_adjust_serdes_amplitude(struct e1000_hw *hw);
98 static int32_t e1000_phy_force_speed_duplex(struct e1000_hw *hw);
99 static int32_t e1000_config_mac_to_phy(struct e1000_hw *hw);
100 static void e1000_raise_mdi_clk(struct e1000_hw *hw, uint32_t *ctrl);
101 static void e1000_lower_mdi_clk(struct e1000_hw *hw, uint32_t *ctrl);
102 static void e1000_shift_out_mdi_bits(struct e1000_hw *hw, uint32_t data,
104 static uint16_t e1000_shift_in_mdi_bits(struct e1000_hw *hw);
105 static int32_t e1000_phy_reset_dsp(struct e1000_hw *hw);
106 static int32_t e1000_write_eeprom_spi(struct e1000_hw *hw, uint16_t offset,
107 uint16_t words, uint16_t *data);
108 static int32_t e1000_write_eeprom_microwire(struct e1000_hw *hw,
109 uint16_t offset, uint16_t words,
111 static int32_t e1000_spi_eeprom_ready(struct e1000_hw *hw);
112 static void e1000_raise_ee_clk(struct e1000_hw *hw, uint32_t *eecd);
113 static void e1000_lower_ee_clk(struct e1000_hw *hw, uint32_t *eecd);
114 static void e1000_shift_out_ee_bits(struct e1000_hw *hw, uint16_t data,
116 static int32_t e1000_write_phy_reg_ex(struct e1000_hw *hw, uint32_t reg_addr,
118 static int32_t e1000_read_phy_reg_ex(struct e1000_hw *hw,uint32_t reg_addr,
120 static uint16_t e1000_shift_in_ee_bits(struct e1000_hw *hw, uint16_t count);
121 static int32_t e1000_acquire_eeprom(struct e1000_hw *hw);
122 static void e1000_release_eeprom(struct e1000_hw *hw);
123 static void e1000_standby_eeprom(struct e1000_hw *hw);
124 static int32_t e1000_set_vco_speed(struct e1000_hw *hw);
125 static int32_t e1000_polarity_reversal_workaround(struct e1000_hw *hw);
126 static int32_t e1000_set_phy_mode(struct e1000_hw *hw);
127 static int32_t e1000_host_if_read_cookie(struct e1000_hw *hw, uint8_t *buffer);
128 static uint8_t e1000_calculate_mng_checksum(char *buffer, uint32_t length);
129 static int32_t e1000_configure_kmrn_for_10_100(struct e1000_hw *hw,
131 static int32_t e1000_configure_kmrn_for_1000(struct e1000_hw *hw);
133 /* IGP cable length table */
135 uint16_t e1000_igp_cable_length_table[IGP01E1000_AGC_LENGTH_TABLE_SIZE] =
136 { 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
137 5, 10, 10, 10, 10, 10, 10, 10, 20, 20, 20, 20, 20, 25, 25, 25,
138 25, 25, 25, 25, 30, 30, 30, 30, 40, 40, 40, 40, 40, 40, 40, 40,
139 40, 50, 50, 50, 50, 50, 50, 50, 60, 60, 60, 60, 60, 60, 60, 60,
140 60, 70, 70, 70, 70, 70, 70, 80, 80, 80, 80, 80, 80, 90, 90, 90,
141 90, 90, 90, 90, 90, 90, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100,
142 100, 100, 100, 100, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110,
143 110, 110, 110, 110, 110, 110, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120};
146 uint16_t e1000_igp_2_cable_length_table[IGP02E1000_AGC_LENGTH_TABLE_SIZE] =
147 { 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21,
148 0, 0, 0, 3, 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41,
149 6, 10, 14, 18, 22, 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61,
150 21, 26, 31, 35, 40, 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82,
151 40, 45, 51, 56, 61, 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104,
152 60, 66, 72, 77, 82, 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121,
153 83, 89, 95, 100, 105, 109, 113, 116, 119, 122, 124,
154 104, 109, 114, 118, 121, 124};
156 /******************************************************************************
157 * Set the phy type member in the hw struct.
159 * hw - Struct containing variables accessed by shared code
160 *****************************************************************************/
162 e1000_set_phy_type(struct e1000_hw *hw)
164 DEBUGFUNC("e1000_set_phy_type");
166 if (hw->mac_type == e1000_undefined)
167 return -E1000_ERR_PHY_TYPE;
169 switch (hw->phy_id) {
170 case M88E1000_E_PHY_ID:
171 case M88E1000_I_PHY_ID:
172 case M88E1011_I_PHY_ID:
173 case M88E1111_I_PHY_ID:
174 hw->phy_type = e1000_phy_m88;
176 case IGP01E1000_I_PHY_ID:
177 if (hw->mac_type == e1000_82541 ||
178 hw->mac_type == e1000_82541_rev_2 ||
179 hw->mac_type == e1000_82547 ||
180 hw->mac_type == e1000_82547_rev_2) {
181 hw->phy_type = e1000_phy_igp;
184 case IGP03E1000_E_PHY_ID:
185 hw->phy_type = e1000_phy_igp_3;
188 case IFE_PLUS_E_PHY_ID:
190 hw->phy_type = e1000_phy_ife;
192 case GG82563_E_PHY_ID:
193 if (hw->mac_type == e1000_80003es2lan) {
194 hw->phy_type = e1000_phy_gg82563;
199 /* Should never have loaded on this device */
200 hw->phy_type = e1000_phy_undefined;
201 return -E1000_ERR_PHY_TYPE;
204 return E1000_SUCCESS;
207 /******************************************************************************
208 * IGP phy init script - initializes the GbE PHY
210 * hw - Struct containing variables accessed by shared code
211 *****************************************************************************/
213 e1000_phy_init_script(struct e1000_hw *hw)
216 uint16_t phy_saved_data;
218 DEBUGFUNC("e1000_phy_init_script");
220 if (hw->phy_init_script) {
223 /* Save off the current value of register 0x2F5B to be restored at
224 * the end of this routine. */
225 ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
227 /* Disabled the PHY transmitter */
228 e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
232 e1000_write_phy_reg(hw,0x0000,0x0140);
236 switch (hw->mac_type) {
239 e1000_write_phy_reg(hw, 0x1F95, 0x0001);
241 e1000_write_phy_reg(hw, 0x1F71, 0xBD21);
243 e1000_write_phy_reg(hw, 0x1F79, 0x0018);
245 e1000_write_phy_reg(hw, 0x1F30, 0x1600);
247 e1000_write_phy_reg(hw, 0x1F31, 0x0014);
249 e1000_write_phy_reg(hw, 0x1F32, 0x161C);
251 e1000_write_phy_reg(hw, 0x1F94, 0x0003);
253 e1000_write_phy_reg(hw, 0x1F96, 0x003F);
255 e1000_write_phy_reg(hw, 0x2010, 0x0008);
258 case e1000_82541_rev_2:
259 case e1000_82547_rev_2:
260 e1000_write_phy_reg(hw, 0x1F73, 0x0099);
266 e1000_write_phy_reg(hw, 0x0000, 0x3300);
270 /* Now enable the transmitter */
271 e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
273 if (hw->mac_type == e1000_82547) {
274 uint16_t fused, fine, coarse;
276 /* Move to analog registers page */
277 e1000_read_phy_reg(hw, IGP01E1000_ANALOG_SPARE_FUSE_STATUS, &fused);
279 if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) {
280 e1000_read_phy_reg(hw, IGP01E1000_ANALOG_FUSE_STATUS, &fused);
282 fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK;
283 coarse = fused & IGP01E1000_ANALOG_FUSE_COARSE_MASK;
285 if (coarse > IGP01E1000_ANALOG_FUSE_COARSE_THRESH) {
286 coarse -= IGP01E1000_ANALOG_FUSE_COARSE_10;
287 fine -= IGP01E1000_ANALOG_FUSE_FINE_1;
288 } else if (coarse == IGP01E1000_ANALOG_FUSE_COARSE_THRESH)
289 fine -= IGP01E1000_ANALOG_FUSE_FINE_10;
291 fused = (fused & IGP01E1000_ANALOG_FUSE_POLY_MASK) |
292 (fine & IGP01E1000_ANALOG_FUSE_FINE_MASK) |
293 (coarse & IGP01E1000_ANALOG_FUSE_COARSE_MASK);
295 e1000_write_phy_reg(hw, IGP01E1000_ANALOG_FUSE_CONTROL, fused);
296 e1000_write_phy_reg(hw, IGP01E1000_ANALOG_FUSE_BYPASS,
297 IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL);
303 /******************************************************************************
304 * Set the mac type member in the hw struct.
306 * hw - Struct containing variables accessed by shared code
307 *****************************************************************************/
309 e1000_set_mac_type(struct e1000_hw *hw)
311 DEBUGFUNC("e1000_set_mac_type");
313 switch (hw->device_id) {
314 case E1000_DEV_ID_82542:
315 switch (hw->revision_id) {
316 case E1000_82542_2_0_REV_ID:
317 hw->mac_type = e1000_82542_rev2_0;
319 case E1000_82542_2_1_REV_ID:
320 hw->mac_type = e1000_82542_rev2_1;
323 /* Invalid 82542 revision ID */
324 return -E1000_ERR_MAC_TYPE;
327 case E1000_DEV_ID_82543GC_FIBER:
328 case E1000_DEV_ID_82543GC_COPPER:
329 hw->mac_type = e1000_82543;
331 case E1000_DEV_ID_82544EI_COPPER:
332 case E1000_DEV_ID_82544EI_FIBER:
333 case E1000_DEV_ID_82544GC_COPPER:
334 case E1000_DEV_ID_82544GC_LOM:
335 hw->mac_type = e1000_82544;
337 case E1000_DEV_ID_82540EM:
338 case E1000_DEV_ID_82540EM_LOM:
339 case E1000_DEV_ID_82540EP:
340 case E1000_DEV_ID_82540EP_LOM:
341 case E1000_DEV_ID_82540EP_LP:
342 hw->mac_type = e1000_82540;
344 case E1000_DEV_ID_82545EM_COPPER:
345 case E1000_DEV_ID_82545EM_FIBER:
346 hw->mac_type = e1000_82545;
348 case E1000_DEV_ID_82545GM_COPPER:
349 case E1000_DEV_ID_82545GM_FIBER:
350 case E1000_DEV_ID_82545GM_SERDES:
351 hw->mac_type = e1000_82545_rev_3;
353 case E1000_DEV_ID_82546EB_COPPER:
354 case E1000_DEV_ID_82546EB_FIBER:
355 case E1000_DEV_ID_82546EB_QUAD_COPPER:
356 hw->mac_type = e1000_82546;
358 case E1000_DEV_ID_82546GB_COPPER:
359 case E1000_DEV_ID_82546GB_FIBER:
360 case E1000_DEV_ID_82546GB_SERDES:
361 case E1000_DEV_ID_82546GB_PCIE:
362 case E1000_DEV_ID_82546GB_QUAD_COPPER:
363 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:
364 hw->mac_type = e1000_82546_rev_3;
366 case E1000_DEV_ID_82541EI:
367 case E1000_DEV_ID_82541EI_MOBILE:
368 case E1000_DEV_ID_82541ER_LOM:
369 hw->mac_type = e1000_82541;
371 case E1000_DEV_ID_82541ER:
372 case E1000_DEV_ID_82541GI:
373 case E1000_DEV_ID_82541GI_LF:
374 case E1000_DEV_ID_82541GI_MOBILE:
375 hw->mac_type = e1000_82541_rev_2;
377 case E1000_DEV_ID_82547EI:
378 case E1000_DEV_ID_82547EI_MOBILE:
379 hw->mac_type = e1000_82547;
381 case E1000_DEV_ID_82547GI:
382 hw->mac_type = e1000_82547_rev_2;
384 case E1000_DEV_ID_82571EB_COPPER:
385 case E1000_DEV_ID_82571EB_FIBER:
386 case E1000_DEV_ID_82571EB_SERDES:
387 case E1000_DEV_ID_82571EB_QUAD_COPPER:
388 case E1000_DEV_ID_82571EB_QUAD_COPPER_LOWPROFILE:
389 hw->mac_type = e1000_82571;
391 case E1000_DEV_ID_82572EI_COPPER:
392 case E1000_DEV_ID_82572EI_FIBER:
393 case E1000_DEV_ID_82572EI_SERDES:
394 case E1000_DEV_ID_82572EI:
395 hw->mac_type = e1000_82572;
397 case E1000_DEV_ID_82573E:
398 case E1000_DEV_ID_82573E_IAMT:
399 case E1000_DEV_ID_82573L:
400 hw->mac_type = e1000_82573;
402 case E1000_DEV_ID_80003ES2LAN_COPPER_SPT:
403 case E1000_DEV_ID_80003ES2LAN_SERDES_SPT:
404 case E1000_DEV_ID_80003ES2LAN_COPPER_DPT:
405 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
406 hw->mac_type = e1000_80003es2lan;
408 case E1000_DEV_ID_ICH8_IGP_M_AMT:
409 case E1000_DEV_ID_ICH8_IGP_AMT:
410 case E1000_DEV_ID_ICH8_IGP_C:
411 case E1000_DEV_ID_ICH8_IFE:
412 case E1000_DEV_ID_ICH8_IFE_GT:
413 case E1000_DEV_ID_ICH8_IFE_G:
414 case E1000_DEV_ID_ICH8_IGP_M:
415 hw->mac_type = e1000_ich8lan;
418 /* Should never have loaded on this device */
419 return -E1000_ERR_MAC_TYPE;
422 switch (hw->mac_type) {
424 hw->swfwhw_semaphore_present = TRUE;
425 hw->asf_firmware_present = TRUE;
427 case e1000_80003es2lan:
428 hw->swfw_sync_present = TRUE;
433 hw->eeprom_semaphore_present = TRUE;
437 case e1000_82541_rev_2:
438 case e1000_82547_rev_2:
439 hw->asf_firmware_present = TRUE;
445 return E1000_SUCCESS;
448 /*****************************************************************************
449 * Set media type and TBI compatibility.
451 * hw - Struct containing variables accessed by shared code
452 * **************************************************************************/
454 e1000_set_media_type(struct e1000_hw *hw)
458 DEBUGFUNC("e1000_set_media_type");
460 if (hw->mac_type != e1000_82543) {
461 /* tbi_compatibility is only valid on 82543 */
462 hw->tbi_compatibility_en = FALSE;
465 switch (hw->device_id) {
466 case E1000_DEV_ID_82545GM_SERDES:
467 case E1000_DEV_ID_82546GB_SERDES:
468 case E1000_DEV_ID_82571EB_SERDES:
469 case E1000_DEV_ID_82572EI_SERDES:
470 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
471 hw->media_type = e1000_media_type_internal_serdes;
474 switch (hw->mac_type) {
475 case e1000_82542_rev2_0:
476 case e1000_82542_rev2_1:
477 hw->media_type = e1000_media_type_fiber;
481 /* The STATUS_TBIMODE bit is reserved or reused for the this
484 hw->media_type = e1000_media_type_copper;
487 status = E1000_READ_REG(hw, STATUS);
488 if (status & E1000_STATUS_TBIMODE) {
489 hw->media_type = e1000_media_type_fiber;
490 /* tbi_compatibility not valid on fiber */
491 hw->tbi_compatibility_en = FALSE;
493 hw->media_type = e1000_media_type_copper;
500 /******************************************************************************
501 * Reset the transmit and receive units; mask and clear all interrupts.
503 * hw - Struct containing variables accessed by shared code
504 *****************************************************************************/
506 e1000_reset_hw(struct e1000_hw *hw)
514 uint32_t extcnf_ctrl;
517 DEBUGFUNC("e1000_reset_hw");
519 /* For 82542 (rev 2.0), disable MWI before issuing a device reset */
520 if (hw->mac_type == e1000_82542_rev2_0) {
521 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
522 e1000_pci_clear_mwi(hw);
525 if (hw->bus_type == e1000_bus_type_pci_express) {
526 /* Prevent the PCI-E bus from sticking if there is no TLP connection
527 * on the last TLP read/write transaction when MAC is reset.
529 if (e1000_disable_pciex_master(hw) != E1000_SUCCESS) {
530 DEBUGOUT("PCI-E Master disable polling has failed.\n");
534 /* Clear interrupt mask to stop board from generating interrupts */
535 DEBUGOUT("Masking off all interrupts\n");
536 E1000_WRITE_REG(hw, IMC, 0xffffffff);
538 /* Disable the Transmit and Receive units. Then delay to allow
539 * any pending transactions to complete before we hit the MAC with
542 E1000_WRITE_REG(hw, RCTL, 0);
543 E1000_WRITE_REG(hw, TCTL, E1000_TCTL_PSP);
544 E1000_WRITE_FLUSH(hw);
546 /* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */
547 hw->tbi_compatibility_on = FALSE;
549 /* Delay to allow any outstanding PCI transactions to complete before
550 * resetting the device
554 ctrl = E1000_READ_REG(hw, CTRL);
556 /* Must reset the PHY before resetting the MAC */
557 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
558 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_PHY_RST));
562 /* Must acquire the MDIO ownership before MAC reset.
563 * Ownership defaults to firmware after a reset. */
564 if (hw->mac_type == e1000_82573) {
567 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL);
568 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
571 E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl);
572 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL);
574 if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP)
577 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
584 /* Workaround for ICH8 bit corruption issue in FIFO memory */
585 if (hw->mac_type == e1000_ich8lan) {
586 /* Set Tx and Rx buffer allocation to 8k apiece. */
587 E1000_WRITE_REG(hw, PBA, E1000_PBA_8K);
588 /* Set Packet Buffer Size to 16k. */
589 E1000_WRITE_REG(hw, PBS, E1000_PBS_16K);
592 /* Issue a global reset to the MAC. This will reset the chip's
593 * transmit, receive, DMA, and link units. It will not effect
594 * the current PCI configuration. The global reset bit is self-
595 * clearing, and should clear within a microsecond.
597 DEBUGOUT("Issuing a global reset to MAC\n");
599 switch (hw->mac_type) {
605 case e1000_82541_rev_2:
606 /* These controllers can't ack the 64-bit write when issuing the
607 * reset, so use IO-mapping as a workaround to issue the reset */
608 E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_RST));
610 case e1000_82545_rev_3:
611 case e1000_82546_rev_3:
612 /* Reset is performed on a shadow of the control register */
613 E1000_WRITE_REG(hw, CTRL_DUP, (ctrl | E1000_CTRL_RST));
616 if (!hw->phy_reset_disable &&
617 e1000_check_phy_reset_block(hw) == E1000_SUCCESS) {
618 /* e1000_ich8lan PHY HW reset requires MAC CORE reset
619 * at the same time to make sure the interface between
620 * MAC and the external PHY is reset.
622 ctrl |= E1000_CTRL_PHY_RST;
625 e1000_get_software_flag(hw);
626 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST));
630 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST));
634 /* After MAC reset, force reload of EEPROM to restore power-on settings to
635 * device. Later controllers reload the EEPROM automatically, so just wait
636 * for reload to complete.
638 switch (hw->mac_type) {
639 case e1000_82542_rev2_0:
640 case e1000_82542_rev2_1:
643 /* Wait for reset to complete */
645 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
646 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
647 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
648 E1000_WRITE_FLUSH(hw);
649 /* Wait for EEPROM reload */
653 case e1000_82541_rev_2:
655 case e1000_82547_rev_2:
656 /* Wait for EEPROM reload */
660 if (e1000_is_onboard_nvm_eeprom(hw) == FALSE) {
662 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
663 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
664 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
665 E1000_WRITE_FLUSH(hw);
669 /* Auto read done will delay 5ms or poll based on mac type */
670 ret_val = e1000_get_auto_rd_done(hw);
676 /* Disable HW ARPs on ASF enabled adapters */
677 if (hw->mac_type >= e1000_82540 && hw->mac_type <= e1000_82547_rev_2) {
678 manc = E1000_READ_REG(hw, MANC);
679 manc &= ~(E1000_MANC_ARP_EN);
680 E1000_WRITE_REG(hw, MANC, manc);
683 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
684 e1000_phy_init_script(hw);
686 /* Configure activity LED after PHY reset */
687 led_ctrl = E1000_READ_REG(hw, LEDCTL);
688 led_ctrl &= IGP_ACTIVITY_LED_MASK;
689 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
690 E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
693 /* Clear interrupt mask to stop board from generating interrupts */
694 DEBUGOUT("Masking off all interrupts\n");
695 E1000_WRITE_REG(hw, IMC, 0xffffffff);
697 /* Clear any pending interrupt events. */
698 icr = E1000_READ_REG(hw, ICR);
700 /* If MWI was previously enabled, reenable it. */
701 if (hw->mac_type == e1000_82542_rev2_0) {
702 if (hw->pci_cmd_word & PCI_COMMAND_INVALIDATE)
703 e1000_pci_set_mwi(hw);
706 if (hw->mac_type == e1000_ich8lan) {
707 uint32_t kab = E1000_READ_REG(hw, KABGTXD);
708 kab |= E1000_KABGTXD_BGSQLBIAS;
709 E1000_WRITE_REG(hw, KABGTXD, kab);
712 return E1000_SUCCESS;
715 /******************************************************************************
717 * Initialize a number of hardware-dependent bits
719 * hw: Struct containing variables accessed by shared code
721 * This function contains hardware limitation workarounds for PCI-E adapters
723 *****************************************************************************/
725 e1000_initialize_hardware_bits(struct e1000_hw *hw)
727 if ((hw->mac_type >= e1000_82571) && (!hw->initialize_hw_bits_disable)) {
728 /* Settings common to all PCI-express silicon */
729 uint32_t reg_ctrl, reg_ctrl_ext;
730 uint32_t reg_tarc0, reg_tarc1;
732 uint32_t reg_txdctl, reg_txdctl1;
734 /* link autonegotiation/sync workarounds */
735 reg_tarc0 = E1000_READ_REG(hw, TARC0);
736 reg_tarc0 &= ~((1 << 30)|(1 << 29)|(1 << 28)|(1 << 27));
738 /* Enable not-done TX descriptor counting */
739 reg_txdctl = E1000_READ_REG(hw, TXDCTL);
740 reg_txdctl |= E1000_TXDCTL_COUNT_DESC;
741 E1000_WRITE_REG(hw, TXDCTL, reg_txdctl);
742 reg_txdctl1 = E1000_READ_REG(hw, TXDCTL1);
743 reg_txdctl1 |= E1000_TXDCTL_COUNT_DESC;
744 E1000_WRITE_REG(hw, TXDCTL1, reg_txdctl1);
746 switch (hw->mac_type) {
749 /* Clear PHY TX compatible mode bits */
750 reg_tarc1 = E1000_READ_REG(hw, TARC1);
751 reg_tarc1 &= ~((1 << 30)|(1 << 29));
753 /* link autonegotiation/sync workarounds */
754 reg_tarc0 |= ((1 << 26)|(1 << 25)|(1 << 24)|(1 << 23));
756 /* TX ring control fixes */
757 reg_tarc1 |= ((1 << 26)|(1 << 25)|(1 << 24));
759 /* Multiple read bit is reversed polarity */
760 reg_tctl = E1000_READ_REG(hw, TCTL);
761 if (reg_tctl & E1000_TCTL_MULR)
762 reg_tarc1 &= ~(1 << 28);
764 reg_tarc1 |= (1 << 28);
766 E1000_WRITE_REG(hw, TARC1, reg_tarc1);
769 reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
770 reg_ctrl_ext &= ~(1 << 23);
771 reg_ctrl_ext |= (1 << 22);
773 /* TX byte count fix */
774 reg_ctrl = E1000_READ_REG(hw, CTRL);
775 reg_ctrl &= ~(1 << 29);
777 E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext);
778 E1000_WRITE_REG(hw, CTRL, reg_ctrl);
780 case e1000_80003es2lan:
781 /* improve small packet performace for fiber/serdes */
782 if ((hw->media_type == e1000_media_type_fiber) ||
783 (hw->media_type == e1000_media_type_internal_serdes)) {
784 reg_tarc0 &= ~(1 << 20);
787 /* Multiple read bit is reversed polarity */
788 reg_tctl = E1000_READ_REG(hw, TCTL);
789 reg_tarc1 = E1000_READ_REG(hw, TARC1);
790 if (reg_tctl & E1000_TCTL_MULR)
791 reg_tarc1 &= ~(1 << 28);
793 reg_tarc1 |= (1 << 28);
795 E1000_WRITE_REG(hw, TARC1, reg_tarc1);
798 /* Reduce concurrent DMA requests to 3 from 4 */
799 if ((hw->revision_id < 3) ||
800 ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) &&
801 (hw->device_id != E1000_DEV_ID_ICH8_IGP_M)))
802 reg_tarc0 |= ((1 << 29)|(1 << 28));
804 reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
805 reg_ctrl_ext |= (1 << 22);
806 E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext);
808 /* workaround TX hang with TSO=on */
809 reg_tarc0 |= ((1 << 27)|(1 << 26)|(1 << 24)|(1 << 23));
811 /* Multiple read bit is reversed polarity */
812 reg_tctl = E1000_READ_REG(hw, TCTL);
813 reg_tarc1 = E1000_READ_REG(hw, TARC1);
814 if (reg_tctl & E1000_TCTL_MULR)
815 reg_tarc1 &= ~(1 << 28);
817 reg_tarc1 |= (1 << 28);
819 /* workaround TX hang with TSO=on */
820 reg_tarc1 |= ((1 << 30)|(1 << 26)|(1 << 24));
822 E1000_WRITE_REG(hw, TARC1, reg_tarc1);
828 E1000_WRITE_REG(hw, TARC0, reg_tarc0);
832 /******************************************************************************
833 * Performs basic configuration of the adapter.
835 * hw - Struct containing variables accessed by shared code
837 * Assumes that the controller has previously been reset and is in a
838 * post-reset uninitialized state. Initializes the receive address registers,
839 * multicast table, and VLAN filter table. Calls routines to setup link
840 * configuration and flow control settings. Clears all on-chip counters. Leaves
841 * the transmit and receive units disabled and uninitialized.
842 *****************************************************************************/
844 e1000_init_hw(struct e1000_hw *hw)
849 uint16_t pcix_cmd_word;
850 uint16_t pcix_stat_hi_word;
857 DEBUGFUNC("e1000_init_hw");
859 /* force full DMA clock frequency for 10/100 on ICH8 A0-B0 */
860 if ((hw->mac_type == e1000_ich8lan) &&
861 ((hw->revision_id < 3) ||
862 ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) &&
863 (hw->device_id != E1000_DEV_ID_ICH8_IGP_M)))) {
864 reg_data = E1000_READ_REG(hw, STATUS);
865 reg_data &= ~0x80000000;
866 E1000_WRITE_REG(hw, STATUS, reg_data);
869 /* Initialize Identification LED */
870 ret_val = e1000_id_led_init(hw);
872 DEBUGOUT("Error Initializing Identification LED\n");
876 /* Set the media type and TBI compatibility */
877 e1000_set_media_type(hw);
879 /* Must be called after e1000_set_media_type because media_type is used */
880 e1000_initialize_hardware_bits(hw);
882 /* Disabling VLAN filtering. */
883 DEBUGOUT("Initializing the IEEE VLAN\n");
884 /* VET hardcoded to standard value and VFTA removed in ICH8 LAN */
885 if (hw->mac_type != e1000_ich8lan) {
886 if (hw->mac_type < e1000_82545_rev_3)
887 E1000_WRITE_REG(hw, VET, 0);
888 e1000_clear_vfta(hw);
891 /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */
892 if (hw->mac_type == e1000_82542_rev2_0) {
893 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
894 e1000_pci_clear_mwi(hw);
895 E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST);
896 E1000_WRITE_FLUSH(hw);
900 /* Setup the receive address. This involves initializing all of the Receive
901 * Address Registers (RARs 0 - 15).
903 e1000_init_rx_addrs(hw);
905 /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */
906 if (hw->mac_type == e1000_82542_rev2_0) {
907 E1000_WRITE_REG(hw, RCTL, 0);
908 E1000_WRITE_FLUSH(hw);
910 if (hw->pci_cmd_word & PCI_COMMAND_INVALIDATE)
911 e1000_pci_set_mwi(hw);
914 /* Zero out the Multicast HASH table */
915 DEBUGOUT("Zeroing the MTA\n");
916 mta_size = E1000_MC_TBL_SIZE;
917 if (hw->mac_type == e1000_ich8lan)
918 mta_size = E1000_MC_TBL_SIZE_ICH8LAN;
919 for (i = 0; i < mta_size; i++) {
920 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
921 /* use write flush to prevent Memory Write Block (MWB) from
922 * occuring when accessing our register space */
923 E1000_WRITE_FLUSH(hw);
926 /* Set the PCI priority bit correctly in the CTRL register. This
927 * determines if the adapter gives priority to receives, or if it
928 * gives equal priority to transmits and receives. Valid only on
929 * 82542 and 82543 silicon.
931 if (hw->dma_fairness && hw->mac_type <= e1000_82543) {
932 ctrl = E1000_READ_REG(hw, CTRL);
933 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PRIOR);
936 switch (hw->mac_type) {
937 case e1000_82545_rev_3:
938 case e1000_82546_rev_3:
941 /* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */
942 if (hw->bus_type == e1000_bus_type_pcix) {
943 e1000_read_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd_word);
944 e1000_read_pci_cfg(hw, PCIX_STATUS_REGISTER_HI,
946 cmd_mmrbc = (pcix_cmd_word & PCIX_COMMAND_MMRBC_MASK) >>
947 PCIX_COMMAND_MMRBC_SHIFT;
948 stat_mmrbc = (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >>
949 PCIX_STATUS_HI_MMRBC_SHIFT;
950 if (stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K)
951 stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K;
952 if (cmd_mmrbc > stat_mmrbc) {
953 pcix_cmd_word &= ~PCIX_COMMAND_MMRBC_MASK;
954 pcix_cmd_word |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT;
955 e1000_write_pci_cfg(hw, PCIX_COMMAND_REGISTER,
962 /* More time needed for PHY to initialize */
963 if (hw->mac_type == e1000_ich8lan)
966 /* Call a subroutine to configure the link and setup flow control. */
967 ret_val = e1000_setup_link(hw);
969 /* Set the transmit descriptor write-back policy */
970 if (hw->mac_type > e1000_82544) {
971 ctrl = E1000_READ_REG(hw, TXDCTL);
972 ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB;
973 E1000_WRITE_REG(hw, TXDCTL, ctrl);
976 if (hw->mac_type == e1000_82573) {
977 e1000_enable_tx_pkt_filtering(hw);
980 switch (hw->mac_type) {
983 case e1000_80003es2lan:
984 /* Enable retransmit on late collisions */
985 reg_data = E1000_READ_REG(hw, TCTL);
986 reg_data |= E1000_TCTL_RTLC;
987 E1000_WRITE_REG(hw, TCTL, reg_data);
989 /* Configure Gigabit Carry Extend Padding */
990 reg_data = E1000_READ_REG(hw, TCTL_EXT);
991 reg_data &= ~E1000_TCTL_EXT_GCEX_MASK;
992 reg_data |= DEFAULT_80003ES2LAN_TCTL_EXT_GCEX;
993 E1000_WRITE_REG(hw, TCTL_EXT, reg_data);
995 /* Configure Transmit Inter-Packet Gap */
996 reg_data = E1000_READ_REG(hw, TIPG);
997 reg_data &= ~E1000_TIPG_IPGT_MASK;
998 reg_data |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000;
999 E1000_WRITE_REG(hw, TIPG, reg_data);
1001 reg_data = E1000_READ_REG_ARRAY(hw, FFLT, 0x0001);
1002 reg_data &= ~0x00100000;
1003 E1000_WRITE_REG_ARRAY(hw, FFLT, 0x0001, reg_data);
1008 ctrl = E1000_READ_REG(hw, TXDCTL1);
1009 ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB;
1010 E1000_WRITE_REG(hw, TXDCTL1, ctrl);
1015 if (hw->mac_type == e1000_82573) {
1016 uint32_t gcr = E1000_READ_REG(hw, GCR);
1017 gcr |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX;
1018 E1000_WRITE_REG(hw, GCR, gcr);
1021 /* Clear all of the statistics registers (clear on read). It is
1022 * important that we do this after we have tried to establish link
1023 * because the symbol error count will increment wildly if there
1026 e1000_clear_hw_cntrs(hw);
1028 /* ICH8 No-snoop bits are opposite polarity.
1029 * Set to snoop by default after reset. */
1030 if (hw->mac_type == e1000_ich8lan)
1031 e1000_set_pci_ex_no_snoop(hw, PCI_EX_82566_SNOOP_ALL);
1033 if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER ||
1034 hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) {
1035 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
1036 /* Relaxed ordering must be disabled to avoid a parity
1037 * error crash in a PCI slot. */
1038 ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
1039 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
1045 /******************************************************************************
1046 * Adjust SERDES output amplitude based on EEPROM setting.
1048 * hw - Struct containing variables accessed by shared code.
1049 *****************************************************************************/
1051 e1000_adjust_serdes_amplitude(struct e1000_hw *hw)
1053 uint16_t eeprom_data;
1056 DEBUGFUNC("e1000_adjust_serdes_amplitude");
1058 if (hw->media_type != e1000_media_type_internal_serdes)
1059 return E1000_SUCCESS;
1061 switch (hw->mac_type) {
1062 case e1000_82545_rev_3:
1063 case e1000_82546_rev_3:
1066 return E1000_SUCCESS;
1069 ret_val = e1000_read_eeprom(hw, EEPROM_SERDES_AMPLITUDE, 1, &eeprom_data);
1074 if (eeprom_data != EEPROM_RESERVED_WORD) {
1075 /* Adjust SERDES output amplitude only. */
1076 eeprom_data &= EEPROM_SERDES_AMPLITUDE_MASK;
1077 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_EXT_CTRL, eeprom_data);
1082 return E1000_SUCCESS;
1085 /******************************************************************************
1086 * Configures flow control and link settings.
1088 * hw - Struct containing variables accessed by shared code
1090 * Determines which flow control settings to use. Calls the apropriate media-
1091 * specific link configuration function. Configures the flow control settings.
1092 * Assuming the adapter has a valid link partner, a valid link should be
1093 * established. Assumes the hardware has previously been reset and the
1094 * transmitter and receiver are not enabled.
1095 *****************************************************************************/
1097 e1000_setup_link(struct e1000_hw *hw)
1101 uint16_t eeprom_data;
1103 DEBUGFUNC("e1000_setup_link");
1105 /* In the case of the phy reset being blocked, we already have a link.
1106 * We do not have to set it up again. */
1107 if (e1000_check_phy_reset_block(hw))
1108 return E1000_SUCCESS;
1110 /* Read and store word 0x0F of the EEPROM. This word contains bits
1111 * that determine the hardware's default PAUSE (flow control) mode,
1112 * a bit that determines whether the HW defaults to enabling or
1113 * disabling auto-negotiation, and the direction of the
1114 * SW defined pins. If there is no SW over-ride of the flow
1115 * control setting, then the variable hw->fc will
1116 * be initialized based on a value in the EEPROM.
1118 if (hw->fc == E1000_FC_DEFAULT) {
1119 switch (hw->mac_type) {
1122 hw->fc = E1000_FC_FULL;
1125 ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG,
1128 DEBUGOUT("EEPROM Read Error\n");
1129 return -E1000_ERR_EEPROM;
1131 if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0)
1132 hw->fc = E1000_FC_NONE;
1133 else if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) ==
1134 EEPROM_WORD0F_ASM_DIR)
1135 hw->fc = E1000_FC_TX_PAUSE;
1137 hw->fc = E1000_FC_FULL;
1142 /* We want to save off the original Flow Control configuration just
1143 * in case we get disconnected and then reconnected into a different
1144 * hub or switch with different Flow Control capabilities.
1146 if (hw->mac_type == e1000_82542_rev2_0)
1147 hw->fc &= (~E1000_FC_TX_PAUSE);
1149 if ((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1))
1150 hw->fc &= (~E1000_FC_RX_PAUSE);
1152 hw->original_fc = hw->fc;
1154 DEBUGOUT1("After fix-ups FlowControl is now = %x\n", hw->fc);
1156 /* Take the 4 bits from EEPROM word 0x0F that determine the initial
1157 * polarity value for the SW controlled pins, and setup the
1158 * Extended Device Control reg with that info.
1159 * This is needed because one of the SW controlled pins is used for
1160 * signal detection. So this should be done before e1000_setup_pcs_link()
1161 * or e1000_phy_setup() is called.
1163 if (hw->mac_type == e1000_82543) {
1164 ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG,
1167 DEBUGOUT("EEPROM Read Error\n");
1168 return -E1000_ERR_EEPROM;
1170 ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) <<
1172 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
1175 /* Call the necessary subroutine to configure the link. */
1176 ret_val = (hw->media_type == e1000_media_type_copper) ?
1177 e1000_setup_copper_link(hw) :
1178 e1000_setup_fiber_serdes_link(hw);
1180 /* Initialize the flow control address, type, and PAUSE timer
1181 * registers to their default values. This is done even if flow
1182 * control is disabled, because it does not hurt anything to
1183 * initialize these registers.
1185 DEBUGOUT("Initializing the Flow Control address, type and timer regs\n");
1187 /* FCAL/H and FCT are hardcoded to standard values in e1000_ich8lan. */
1188 if (hw->mac_type != e1000_ich8lan) {
1189 E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE);
1190 E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH);
1191 E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW);
1194 E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time);
1196 /* Set the flow control receive threshold registers. Normally,
1197 * these registers will be set to a default threshold that may be
1198 * adjusted later by the driver's runtime code. However, if the
1199 * ability to transmit pause frames in not enabled, then these
1200 * registers will be set to 0.
1202 if (!(hw->fc & E1000_FC_TX_PAUSE)) {
1203 E1000_WRITE_REG(hw, FCRTL, 0);
1204 E1000_WRITE_REG(hw, FCRTH, 0);
1206 /* We need to set up the Receive Threshold high and low water marks
1207 * as well as (optionally) enabling the transmission of XON frames.
1209 if (hw->fc_send_xon) {
1210 E1000_WRITE_REG(hw, FCRTL, (hw->fc_low_water | E1000_FCRTL_XONE));
1211 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
1213 E1000_WRITE_REG(hw, FCRTL, hw->fc_low_water);
1214 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
1220 /******************************************************************************
1221 * Sets up link for a fiber based or serdes based adapter
1223 * hw - Struct containing variables accessed by shared code
1225 * Manipulates Physical Coding Sublayer functions in order to configure
1226 * link. Assumes the hardware has been previously reset and the transmitter
1227 * and receiver are not enabled.
1228 *****************************************************************************/
1230 e1000_setup_fiber_serdes_link(struct e1000_hw *hw)
1236 uint32_t signal = 0;
1239 DEBUGFUNC("e1000_setup_fiber_serdes_link");
1241 /* On 82571 and 82572 Fiber connections, SerDes loopback mode persists
1242 * until explicitly turned off or a power cycle is performed. A read to
1243 * the register does not indicate its status. Therefore, we ensure
1244 * loopback mode is disabled during initialization.
1246 if (hw->mac_type == e1000_82571 || hw->mac_type == e1000_82572)
1247 E1000_WRITE_REG(hw, SCTL, E1000_DISABLE_SERDES_LOOPBACK);
1249 /* On adapters with a MAC newer than 82544, SWDP 1 will be
1250 * set when the optics detect a signal. On older adapters, it will be
1251 * cleared when there is a signal. This applies to fiber media only.
1252 * If we're on serdes media, adjust the output amplitude to value
1253 * set in the EEPROM.
1255 ctrl = E1000_READ_REG(hw, CTRL);
1256 if (hw->media_type == e1000_media_type_fiber)
1257 signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0;
1259 ret_val = e1000_adjust_serdes_amplitude(hw);
1263 /* Take the link out of reset */
1264 ctrl &= ~(E1000_CTRL_LRST);
1266 /* Adjust VCO speed to improve BER performance */
1267 ret_val = e1000_set_vco_speed(hw);
1271 e1000_config_collision_dist(hw);
1273 /* Check for a software override of the flow control settings, and setup
1274 * the device accordingly. If auto-negotiation is enabled, then software
1275 * will have to set the "PAUSE" bits to the correct value in the Tranmsit
1276 * Config Word Register (TXCW) and re-start auto-negotiation. However, if
1277 * auto-negotiation is disabled, then software will have to manually
1278 * configure the two flow control enable bits in the CTRL register.
1280 * The possible values of the "fc" parameter are:
1281 * 0: Flow control is completely disabled
1282 * 1: Rx flow control is enabled (we can receive pause frames, but
1283 * not send pause frames).
1284 * 2: Tx flow control is enabled (we can send pause frames but we do
1285 * not support receiving pause frames).
1286 * 3: Both Rx and TX flow control (symmetric) are enabled.
1290 /* Flow control is completely disabled by a software over-ride. */
1291 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);
1293 case E1000_FC_RX_PAUSE:
1294 /* RX Flow control is enabled and TX Flow control is disabled by a
1295 * software over-ride. Since there really isn't a way to advertise
1296 * that we are capable of RX Pause ONLY, we will advertise that we
1297 * support both symmetric and asymmetric RX PAUSE. Later, we will
1298 * disable the adapter's ability to send PAUSE frames.
1300 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
1302 case E1000_FC_TX_PAUSE:
1303 /* TX Flow control is enabled, and RX Flow control is disabled, by a
1304 * software over-ride.
1306 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);
1309 /* Flow control (both RX and TX) is enabled by a software over-ride. */
1310 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
1313 DEBUGOUT("Flow control param set incorrectly\n");
1314 return -E1000_ERR_CONFIG;
1318 /* Since auto-negotiation is enabled, take the link out of reset (the link
1319 * will be in reset, because we previously reset the chip). This will
1320 * restart auto-negotiation. If auto-neogtiation is successful then the
1321 * link-up status bit will be set and the flow control enable bits (RFCE
1322 * and TFCE) will be set according to their negotiated value.
1324 DEBUGOUT("Auto-negotiation enabled\n");
1326 E1000_WRITE_REG(hw, TXCW, txcw);
1327 E1000_WRITE_REG(hw, CTRL, ctrl);
1328 E1000_WRITE_FLUSH(hw);
1333 /* If we have a signal (the cable is plugged in) then poll for a "Link-Up"
1334 * indication in the Device Status Register. Time-out if a link isn't
1335 * seen in 500 milliseconds seconds (Auto-negotiation should complete in
1336 * less than 500 milliseconds even if the other end is doing it in SW).
1337 * For internal serdes, we just assume a signal is present, then poll.
1339 if (hw->media_type == e1000_media_type_internal_serdes ||
1340 (E1000_READ_REG(hw, CTRL) & E1000_CTRL_SWDPIN1) == signal) {
1341 DEBUGOUT("Looking for Link\n");
1342 for (i = 0; i < (LINK_UP_TIMEOUT / 10); i++) {
1344 status = E1000_READ_REG(hw, STATUS);
1345 if (status & E1000_STATUS_LU) break;
1347 if (i == (LINK_UP_TIMEOUT / 10)) {
1348 DEBUGOUT("Never got a valid link from auto-neg!!!\n");
1349 hw->autoneg_failed = 1;
1350 /* AutoNeg failed to achieve a link, so we'll call
1351 * e1000_check_for_link. This routine will force the link up if
1352 * we detect a signal. This will allow us to communicate with
1353 * non-autonegotiating link partners.
1355 ret_val = e1000_check_for_link(hw);
1357 DEBUGOUT("Error while checking for link\n");
1360 hw->autoneg_failed = 0;
1362 hw->autoneg_failed = 0;
1363 DEBUGOUT("Valid Link Found\n");
1366 DEBUGOUT("No Signal Detected\n");
1368 return E1000_SUCCESS;
1371 /******************************************************************************
1372 * Make sure we have a valid PHY and change PHY mode before link setup.
1374 * hw - Struct containing variables accessed by shared code
1375 ******************************************************************************/
1377 e1000_copper_link_preconfig(struct e1000_hw *hw)
1383 DEBUGFUNC("e1000_copper_link_preconfig");
1385 ctrl = E1000_READ_REG(hw, CTRL);
1386 /* With 82543, we need to force speed and duplex on the MAC equal to what
1387 * the PHY speed and duplex configuration is. In addition, we need to
1388 * perform a hardware reset on the PHY to take it out of reset.
1390 if (hw->mac_type > e1000_82543) {
1391 ctrl |= E1000_CTRL_SLU;
1392 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1393 E1000_WRITE_REG(hw, CTRL, ctrl);
1395 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX | E1000_CTRL_SLU);
1396 E1000_WRITE_REG(hw, CTRL, ctrl);
1397 ret_val = e1000_phy_hw_reset(hw);
1402 /* Make sure we have a valid PHY */
1403 ret_val = e1000_detect_gig_phy(hw);
1405 DEBUGOUT("Error, did not detect valid phy.\n");
1408 DEBUGOUT1("Phy ID = %x \n", hw->phy_id);
1410 /* Set PHY to class A mode (if necessary) */
1411 ret_val = e1000_set_phy_mode(hw);
1415 if ((hw->mac_type == e1000_82545_rev_3) ||
1416 (hw->mac_type == e1000_82546_rev_3)) {
1417 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1418 phy_data |= 0x00000008;
1419 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1422 if (hw->mac_type <= e1000_82543 ||
1423 hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547 ||
1424 hw->mac_type == e1000_82541_rev_2 || hw->mac_type == e1000_82547_rev_2)
1425 hw->phy_reset_disable = FALSE;
1427 return E1000_SUCCESS;
1431 /********************************************************************
1432 * Copper link setup for e1000_phy_igp series.
1434 * hw - Struct containing variables accessed by shared code
1435 *********************************************************************/
1437 e1000_copper_link_igp_setup(struct e1000_hw *hw)
1443 DEBUGFUNC("e1000_copper_link_igp_setup");
1445 if (hw->phy_reset_disable)
1446 return E1000_SUCCESS;
1448 ret_val = e1000_phy_reset(hw);
1450 DEBUGOUT("Error Resetting the PHY\n");
1454 /* Wait 15ms for MAC to configure PHY from eeprom settings */
1456 if (hw->mac_type != e1000_ich8lan) {
1457 /* Configure activity LED after PHY reset */
1458 led_ctrl = E1000_READ_REG(hw, LEDCTL);
1459 led_ctrl &= IGP_ACTIVITY_LED_MASK;
1460 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
1461 E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
1464 /* The NVM settings will configure LPLU in D3 for IGP2 and IGP3 PHYs */
1465 if (hw->phy_type == e1000_phy_igp) {
1466 /* disable lplu d3 during driver init */
1467 ret_val = e1000_set_d3_lplu_state(hw, FALSE);
1469 DEBUGOUT("Error Disabling LPLU D3\n");
1474 /* disable lplu d0 during driver init */
1475 ret_val = e1000_set_d0_lplu_state(hw, FALSE);
1477 DEBUGOUT("Error Disabling LPLU D0\n");
1480 /* Configure mdi-mdix settings */
1481 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
1485 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
1486 hw->dsp_config_state = e1000_dsp_config_disabled;
1487 /* Force MDI for earlier revs of the IGP PHY */
1488 phy_data &= ~(IGP01E1000_PSCR_AUTO_MDIX | IGP01E1000_PSCR_FORCE_MDI_MDIX);
1492 hw->dsp_config_state = e1000_dsp_config_enabled;
1493 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1497 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1500 phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
1504 phy_data |= IGP01E1000_PSCR_AUTO_MDIX;
1508 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
1512 /* set auto-master slave resolution settings */
1514 e1000_ms_type phy_ms_setting = hw->master_slave;
1516 if (hw->ffe_config_state == e1000_ffe_config_active)
1517 hw->ffe_config_state = e1000_ffe_config_enabled;
1519 if (hw->dsp_config_state == e1000_dsp_config_activated)
1520 hw->dsp_config_state = e1000_dsp_config_enabled;
1522 /* when autonegotiation advertisment is only 1000Mbps then we
1523 * should disable SmartSpeed and enable Auto MasterSlave
1524 * resolution as hardware default. */
1525 if (hw->autoneg_advertised == ADVERTISE_1000_FULL) {
1526 /* Disable SmartSpeed */
1527 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1531 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1532 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1536 /* Set auto Master/Slave resolution process */
1537 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
1540 phy_data &= ~CR_1000T_MS_ENABLE;
1541 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
1546 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
1550 /* load defaults for future use */
1551 hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ?
1552 ((phy_data & CR_1000T_MS_VALUE) ?
1553 e1000_ms_force_master :
1554 e1000_ms_force_slave) :
1557 switch (phy_ms_setting) {
1558 case e1000_ms_force_master:
1559 phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
1561 case e1000_ms_force_slave:
1562 phy_data |= CR_1000T_MS_ENABLE;
1563 phy_data &= ~(CR_1000T_MS_VALUE);
1566 phy_data &= ~CR_1000T_MS_ENABLE;
1570 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
1575 return E1000_SUCCESS;
1578 /********************************************************************
1579 * Copper link setup for e1000_phy_gg82563 series.
1581 * hw - Struct containing variables accessed by shared code
1582 *********************************************************************/
1584 e1000_copper_link_ggp_setup(struct e1000_hw *hw)
1590 DEBUGFUNC("e1000_copper_link_ggp_setup");
1592 if (!hw->phy_reset_disable) {
1594 /* Enable CRS on TX for half-duplex operation. */
1595 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL,
1600 phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
1601 /* Use 25MHz for both link down and 1000BASE-T for Tx clock */
1602 phy_data |= GG82563_MSCR_TX_CLK_1000MBPS_25MHZ;
1604 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL,
1610 * MDI/MDI-X = 0 (default)
1611 * 0 - Auto for all speeds
1614 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
1616 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_SPEC_CTRL, &phy_data);
1620 phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK;
1624 phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDI;
1627 phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDIX;
1631 phy_data |= GG82563_PSCR_CROSSOVER_MODE_AUTO;
1636 * disable_polarity_correction = 0 (default)
1637 * Automatic Correction for Reversed Cable Polarity
1641 phy_data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
1642 if (hw->disable_polarity_correction == 1)
1643 phy_data |= GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
1644 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_SPEC_CTRL, phy_data);
1649 /* SW Reset the PHY so all changes take effect */
1650 ret_val = e1000_phy_reset(hw);
1652 DEBUGOUT("Error Resetting the PHY\n");
1655 } /* phy_reset_disable */
1657 if (hw->mac_type == e1000_80003es2lan) {
1658 /* Bypass RX and TX FIFO's */
1659 ret_val = e1000_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_FIFO_CTRL,
1660 E1000_KUMCTRLSTA_FIFO_CTRL_RX_BYPASS |
1661 E1000_KUMCTRLSTA_FIFO_CTRL_TX_BYPASS);
1665 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_SPEC_CTRL_2, &phy_data);
1669 phy_data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG;
1670 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_SPEC_CTRL_2, phy_data);
1675 reg_data = E1000_READ_REG(hw, CTRL_EXT);
1676 reg_data &= ~(E1000_CTRL_EXT_LINK_MODE_MASK);
1677 E1000_WRITE_REG(hw, CTRL_EXT, reg_data);
1679 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_PWR_MGMT_CTRL,
1684 /* Do not init these registers when the HW is in IAMT mode, since the
1685 * firmware will have already initialized them. We only initialize
1686 * them if the HW is not in IAMT mode.
1688 if (e1000_check_mng_mode(hw) == FALSE) {
1689 /* Enable Electrical Idle on the PHY */
1690 phy_data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE;
1691 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_PWR_MGMT_CTRL,
1696 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1701 phy_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1702 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1709 /* Workaround: Disable padding in Kumeran interface in the MAC
1710 * and in the PHY to avoid CRC errors.
1712 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_INBAND_CTRL,
1716 phy_data |= GG82563_ICR_DIS_PADDING;
1717 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_INBAND_CTRL,
1723 return E1000_SUCCESS;
1726 /********************************************************************
1727 * Copper link setup for e1000_phy_m88 series.
1729 * hw - Struct containing variables accessed by shared code
1730 *********************************************************************/
1732 e1000_copper_link_mgp_setup(struct e1000_hw *hw)
1737 DEBUGFUNC("e1000_copper_link_mgp_setup");
1739 if (hw->phy_reset_disable)
1740 return E1000_SUCCESS;
1742 /* Enable CRS on TX. This must be set for half-duplex operation. */
1743 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1747 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1750 * MDI/MDI-X = 0 (default)
1751 * 0 - Auto for all speeds
1754 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
1756 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1760 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
1763 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
1766 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
1770 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
1775 * disable_polarity_correction = 0 (default)
1776 * Automatic Correction for Reversed Cable Polarity
1780 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
1781 if (hw->disable_polarity_correction == 1)
1782 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
1783 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1787 if (hw->phy_revision < M88E1011_I_REV_4) {
1788 /* Force TX_CLK in the Extended PHY Specific Control Register
1791 ret_val = e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
1795 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1797 if ((hw->phy_revision == E1000_REVISION_2) &&
1798 (hw->phy_id == M88E1111_I_PHY_ID)) {
1799 /* Vidalia Phy, set the downshift counter to 5x */
1800 phy_data &= ~(M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK);
1801 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
1802 ret_val = e1000_write_phy_reg(hw,
1803 M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
1807 /* Configure Master and Slave downshift values */
1808 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
1809 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
1810 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
1811 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
1812 ret_val = e1000_write_phy_reg(hw,
1813 M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
1819 /* SW Reset the PHY so all changes take effect */
1820 ret_val = e1000_phy_reset(hw);
1822 DEBUGOUT("Error Resetting the PHY\n");
1826 return E1000_SUCCESS;
1829 /********************************************************************
1830 * Setup auto-negotiation and flow control advertisements,
1831 * and then perform auto-negotiation.
1833 * hw - Struct containing variables accessed by shared code
1834 *********************************************************************/
1836 e1000_copper_link_autoneg(struct e1000_hw *hw)
1841 DEBUGFUNC("e1000_copper_link_autoneg");
1843 /* Perform some bounds checking on the hw->autoneg_advertised
1844 * parameter. If this variable is zero, then set it to the default.
1846 hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT;
1848 /* If autoneg_advertised is zero, we assume it was not defaulted
1849 * by the calling code so we set to advertise full capability.
1851 if (hw->autoneg_advertised == 0)
1852 hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT;
1854 /* IFE phy only supports 10/100 */
1855 if (hw->phy_type == e1000_phy_ife)
1856 hw->autoneg_advertised &= AUTONEG_ADVERTISE_10_100_ALL;
1858 DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
1859 ret_val = e1000_phy_setup_autoneg(hw);
1861 DEBUGOUT("Error Setting up Auto-Negotiation\n");
1864 DEBUGOUT("Restarting Auto-Neg\n");
1866 /* Restart auto-negotiation by setting the Auto Neg Enable bit and
1867 * the Auto Neg Restart bit in the PHY control register.
1869 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
1873 phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
1874 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
1878 /* Does the user want to wait for Auto-Neg to complete here, or
1879 * check at a later time (for example, callback routine).
1881 if (hw->wait_autoneg_complete) {
1882 ret_val = e1000_wait_autoneg(hw);
1884 DEBUGOUT("Error while waiting for autoneg to complete\n");
1889 hw->get_link_status = TRUE;
1891 return E1000_SUCCESS;
1894 /******************************************************************************
1895 * Config the MAC and the PHY after link is up.
1896 * 1) Set up the MAC to the current PHY speed/duplex
1897 * if we are on 82543. If we
1898 * are on newer silicon, we only need to configure
1899 * collision distance in the Transmit Control Register.
1900 * 2) Set up flow control on the MAC to that established with
1902 * 3) Config DSP to improve Gigabit link quality for some PHY revisions.
1904 * hw - Struct containing variables accessed by shared code
1905 ******************************************************************************/
1907 e1000_copper_link_postconfig(struct e1000_hw *hw)
1910 DEBUGFUNC("e1000_copper_link_postconfig");
1912 if (hw->mac_type >= e1000_82544) {
1913 e1000_config_collision_dist(hw);
1915 ret_val = e1000_config_mac_to_phy(hw);
1917 DEBUGOUT("Error configuring MAC to PHY settings\n");
1921 ret_val = e1000_config_fc_after_link_up(hw);
1923 DEBUGOUT("Error Configuring Flow Control\n");
1927 /* Config DSP to improve Giga link quality */
1928 if (hw->phy_type == e1000_phy_igp) {
1929 ret_val = e1000_config_dsp_after_link_change(hw, TRUE);
1931 DEBUGOUT("Error Configuring DSP after link up\n");
1936 return E1000_SUCCESS;
1939 /******************************************************************************
1940 * Detects which PHY is present and setup the speed and duplex
1942 * hw - Struct containing variables accessed by shared code
1943 ******************************************************************************/
1945 e1000_setup_copper_link(struct e1000_hw *hw)
1952 DEBUGFUNC("e1000_setup_copper_link");
1954 switch (hw->mac_type) {
1955 case e1000_80003es2lan:
1957 /* Set the mac to wait the maximum time between each
1958 * iteration and increase the max iterations when
1959 * polling the phy; this fixes erroneous timeouts at 10Mbps. */
1960 ret_val = e1000_write_kmrn_reg(hw, GG82563_REG(0x34, 4), 0xFFFF);
1963 ret_val = e1000_read_kmrn_reg(hw, GG82563_REG(0x34, 9), ®_data);
1967 ret_val = e1000_write_kmrn_reg(hw, GG82563_REG(0x34, 9), reg_data);
1974 /* Check if it is a valid PHY and set PHY mode if necessary. */
1975 ret_val = e1000_copper_link_preconfig(hw);
1979 switch (hw->mac_type) {
1980 case e1000_80003es2lan:
1981 /* Kumeran registers are written-only */
1982 reg_data = E1000_KUMCTRLSTA_INB_CTRL_LINK_STATUS_TX_TIMEOUT_DEFAULT;
1983 reg_data |= E1000_KUMCTRLSTA_INB_CTRL_DIS_PADDING;
1984 ret_val = e1000_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_INB_CTRL,
1993 if (hw->phy_type == e1000_phy_igp ||
1994 hw->phy_type == e1000_phy_igp_3 ||
1995 hw->phy_type == e1000_phy_igp_2) {
1996 ret_val = e1000_copper_link_igp_setup(hw);
1999 } else if (hw->phy_type == e1000_phy_m88) {
2000 ret_val = e1000_copper_link_mgp_setup(hw);
2003 } else if (hw->phy_type == e1000_phy_gg82563) {
2004 ret_val = e1000_copper_link_ggp_setup(hw);
2010 /* Setup autoneg and flow control advertisement
2011 * and perform autonegotiation */
2012 ret_val = e1000_copper_link_autoneg(hw);
2016 /* PHY will be set to 10H, 10F, 100H,or 100F
2017 * depending on value from forced_speed_duplex. */
2018 DEBUGOUT("Forcing speed and duplex\n");
2019 ret_val = e1000_phy_force_speed_duplex(hw);
2021 DEBUGOUT("Error Forcing Speed and Duplex\n");
2026 /* Check link status. Wait up to 100 microseconds for link to become
2029 for (i = 0; i < 10; i++) {
2030 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
2033 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
2037 if (phy_data & MII_SR_LINK_STATUS) {
2038 /* Config the MAC and PHY after link is up */
2039 ret_val = e1000_copper_link_postconfig(hw);
2043 DEBUGOUT("Valid link established!!!\n");
2044 return E1000_SUCCESS;
2049 DEBUGOUT("Unable to establish link!!!\n");
2050 return E1000_SUCCESS;
2053 /******************************************************************************
2054 * Configure the MAC-to-PHY interface for 10/100Mbps
2056 * hw - Struct containing variables accessed by shared code
2057 ******************************************************************************/
2059 e1000_configure_kmrn_for_10_100(struct e1000_hw *hw, uint16_t duplex)
2061 int32_t ret_val = E1000_SUCCESS;
2065 DEBUGFUNC("e1000_configure_kmrn_for_10_100");
2067 reg_data = E1000_KUMCTRLSTA_HD_CTRL_10_100_DEFAULT;
2068 ret_val = e1000_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_HD_CTRL,
2073 /* Configure Transmit Inter-Packet Gap */
2074 tipg = E1000_READ_REG(hw, TIPG);
2075 tipg &= ~E1000_TIPG_IPGT_MASK;
2076 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_10_100;
2077 E1000_WRITE_REG(hw, TIPG, tipg);
2079 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data);
2084 if (duplex == HALF_DUPLEX)
2085 reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER;
2087 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
2089 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
2095 e1000_configure_kmrn_for_1000(struct e1000_hw *hw)
2097 int32_t ret_val = E1000_SUCCESS;
2101 DEBUGFUNC("e1000_configure_kmrn_for_1000");
2103 reg_data = E1000_KUMCTRLSTA_HD_CTRL_1000_DEFAULT;
2104 ret_val = e1000_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_HD_CTRL,
2109 /* Configure Transmit Inter-Packet Gap */
2110 tipg = E1000_READ_REG(hw, TIPG);
2111 tipg &= ~E1000_TIPG_IPGT_MASK;
2112 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000;
2113 E1000_WRITE_REG(hw, TIPG, tipg);
2115 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data);
2120 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
2121 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
2126 /******************************************************************************
2127 * Configures PHY autoneg and flow control advertisement settings
2129 * hw - Struct containing variables accessed by shared code
2130 ******************************************************************************/
2132 e1000_phy_setup_autoneg(struct e1000_hw *hw)
2135 uint16_t mii_autoneg_adv_reg;
2136 uint16_t mii_1000t_ctrl_reg;
2138 DEBUGFUNC("e1000_phy_setup_autoneg");
2140 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
2141 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
2145 if (hw->phy_type != e1000_phy_ife) {
2146 /* Read the MII 1000Base-T Control Register (Address 9). */
2147 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg);
2151 mii_1000t_ctrl_reg=0;
2153 /* Need to parse both autoneg_advertised and fc and set up
2154 * the appropriate PHY registers. First we will parse for
2155 * autoneg_advertised software override. Since we can advertise
2156 * a plethora of combinations, we need to check each bit
2160 /* First we clear all the 10/100 mb speed bits in the Auto-Neg
2161 * Advertisement Register (Address 4) and the 1000 mb speed bits in
2162 * the 1000Base-T Control Register (Address 9).
2164 mii_autoneg_adv_reg &= ~REG4_SPEED_MASK;
2165 mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK;
2167 DEBUGOUT1("autoneg_advertised %x\n", hw->autoneg_advertised);
2169 /* Do we want to advertise 10 Mb Half Duplex? */
2170 if (hw->autoneg_advertised & ADVERTISE_10_HALF) {
2171 DEBUGOUT("Advertise 10mb Half duplex\n");
2172 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
2175 /* Do we want to advertise 10 Mb Full Duplex? */
2176 if (hw->autoneg_advertised & ADVERTISE_10_FULL) {
2177 DEBUGOUT("Advertise 10mb Full duplex\n");
2178 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
2181 /* Do we want to advertise 100 Mb Half Duplex? */
2182 if (hw->autoneg_advertised & ADVERTISE_100_HALF) {
2183 DEBUGOUT("Advertise 100mb Half duplex\n");
2184 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
2187 /* Do we want to advertise 100 Mb Full Duplex? */
2188 if (hw->autoneg_advertised & ADVERTISE_100_FULL) {
2189 DEBUGOUT("Advertise 100mb Full duplex\n");
2190 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
2193 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
2194 if (hw->autoneg_advertised & ADVERTISE_1000_HALF) {
2195 DEBUGOUT("Advertise 1000mb Half duplex requested, request denied!\n");
2198 /* Do we want to advertise 1000 Mb Full Duplex? */
2199 if (hw->autoneg_advertised & ADVERTISE_1000_FULL) {
2200 DEBUGOUT("Advertise 1000mb Full duplex\n");
2201 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
2202 if (hw->phy_type == e1000_phy_ife) {
2203 DEBUGOUT("e1000_phy_ife is a 10/100 PHY. Gigabit speed is not supported.\n");
2207 /* Check for a software override of the flow control settings, and
2208 * setup the PHY advertisement registers accordingly. If
2209 * auto-negotiation is enabled, then software will have to set the
2210 * "PAUSE" bits to the correct value in the Auto-Negotiation
2211 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-negotiation.
2213 * The possible values of the "fc" parameter are:
2214 * 0: Flow control is completely disabled
2215 * 1: Rx flow control is enabled (we can receive pause frames
2216 * but not send pause frames).
2217 * 2: Tx flow control is enabled (we can send pause frames
2218 * but we do not support receiving pause frames).
2219 * 3: Both Rx and TX flow control (symmetric) are enabled.
2220 * other: No software override. The flow control configuration
2221 * in the EEPROM is used.
2224 case E1000_FC_NONE: /* 0 */
2225 /* Flow control (RX & TX) is completely disabled by a
2226 * software over-ride.
2228 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
2230 case E1000_FC_RX_PAUSE: /* 1 */
2231 /* RX Flow control is enabled, and TX Flow control is
2232 * disabled, by a software over-ride.
2234 /* Since there really isn't a way to advertise that we are
2235 * capable of RX Pause ONLY, we will advertise that we
2236 * support both symmetric and asymmetric RX PAUSE. Later
2237 * (in e1000_config_fc_after_link_up) we will disable the
2238 *hw's ability to send PAUSE frames.
2240 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
2242 case E1000_FC_TX_PAUSE: /* 2 */
2243 /* TX Flow control is enabled, and RX Flow control is
2244 * disabled, by a software over-ride.
2246 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
2247 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
2249 case E1000_FC_FULL: /* 3 */
2250 /* Flow control (both RX and TX) is enabled by a software
2253 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
2256 DEBUGOUT("Flow control param set incorrectly\n");
2257 return -E1000_ERR_CONFIG;
2260 ret_val = e1000_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
2264 DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
2266 if (hw->phy_type != e1000_phy_ife) {
2267 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, mii_1000t_ctrl_reg);
2272 return E1000_SUCCESS;
2275 /******************************************************************************
2276 * Force PHY speed and duplex settings to hw->forced_speed_duplex
2278 * hw - Struct containing variables accessed by shared code
2279 ******************************************************************************/
2281 e1000_phy_force_speed_duplex(struct e1000_hw *hw)
2285 uint16_t mii_ctrl_reg;
2286 uint16_t mii_status_reg;
2290 DEBUGFUNC("e1000_phy_force_speed_duplex");
2292 /* Turn off Flow control if we are forcing speed and duplex. */
2293 hw->fc = E1000_FC_NONE;
2295 DEBUGOUT1("hw->fc = %d\n", hw->fc);
2297 /* Read the Device Control Register. */
2298 ctrl = E1000_READ_REG(hw, CTRL);
2300 /* Set the bits to Force Speed and Duplex in the Device Ctrl Reg. */
2301 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
2302 ctrl &= ~(DEVICE_SPEED_MASK);
2304 /* Clear the Auto Speed Detect Enable bit. */
2305 ctrl &= ~E1000_CTRL_ASDE;
2307 /* Read the MII Control Register. */
2308 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &mii_ctrl_reg);
2312 /* We need to disable autoneg in order to force link and duplex. */
2314 mii_ctrl_reg &= ~MII_CR_AUTO_NEG_EN;
2316 /* Are we forcing Full or Half Duplex? */
2317 if (hw->forced_speed_duplex == e1000_100_full ||
2318 hw->forced_speed_duplex == e1000_10_full) {
2319 /* We want to force full duplex so we SET the full duplex bits in the
2320 * Device and MII Control Registers.
2322 ctrl |= E1000_CTRL_FD;
2323 mii_ctrl_reg |= MII_CR_FULL_DUPLEX;
2324 DEBUGOUT("Full Duplex\n");
2326 /* We want to force half duplex so we CLEAR the full duplex bits in
2327 * the Device and MII Control Registers.
2329 ctrl &= ~E1000_CTRL_FD;
2330 mii_ctrl_reg &= ~MII_CR_FULL_DUPLEX;
2331 DEBUGOUT("Half Duplex\n");
2334 /* Are we forcing 100Mbps??? */
2335 if (hw->forced_speed_duplex == e1000_100_full ||
2336 hw->forced_speed_duplex == e1000_100_half) {
2337 /* Set the 100Mb bit and turn off the 1000Mb and 10Mb bits. */
2338 ctrl |= E1000_CTRL_SPD_100;
2339 mii_ctrl_reg |= MII_CR_SPEED_100;
2340 mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10);
2341 DEBUGOUT("Forcing 100mb ");
2343 /* Set the 10Mb bit and turn off the 1000Mb and 100Mb bits. */
2344 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
2345 mii_ctrl_reg |= MII_CR_SPEED_10;
2346 mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100);
2347 DEBUGOUT("Forcing 10mb ");
2350 e1000_config_collision_dist(hw);
2352 /* Write the configured values back to the Device Control Reg. */
2353 E1000_WRITE_REG(hw, CTRL, ctrl);
2355 if ((hw->phy_type == e1000_phy_m88) ||
2356 (hw->phy_type == e1000_phy_gg82563)) {
2357 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
2361 /* Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI
2362 * forced whenever speed are duplex are forced.
2364 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
2365 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
2369 DEBUGOUT1("M88E1000 PSCR: %x \n", phy_data);
2371 /* Need to reset the PHY or these changes will be ignored */
2372 mii_ctrl_reg |= MII_CR_RESET;
2374 /* Disable MDI-X support for 10/100 */
2375 } else if (hw->phy_type == e1000_phy_ife) {
2376 ret_val = e1000_read_phy_reg(hw, IFE_PHY_MDIX_CONTROL, &phy_data);
2380 phy_data &= ~IFE_PMC_AUTO_MDIX;
2381 phy_data &= ~IFE_PMC_FORCE_MDIX;
2383 ret_val = e1000_write_phy_reg(hw, IFE_PHY_MDIX_CONTROL, phy_data);
2388 /* Clear Auto-Crossover to force MDI manually. IGP requires MDI
2389 * forced whenever speed or duplex are forced.
2391 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
2395 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
2396 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
2398 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
2403 /* Write back the modified PHY MII control register. */
2404 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, mii_ctrl_reg);
2410 /* The wait_autoneg_complete flag may be a little misleading here.
2411 * Since we are forcing speed and duplex, Auto-Neg is not enabled.
2412 * But we do want to delay for a period while forcing only so we
2413 * don't generate false No Link messages. So we will wait here
2414 * only if the user has set wait_autoneg_complete to 1, which is
2417 if (hw->wait_autoneg_complete) {
2418 /* We will wait for autoneg to complete. */
2419 DEBUGOUT("Waiting for forced speed/duplex link.\n");
2422 /* We will wait for autoneg to complete or 4.5 seconds to expire. */
2423 for (i = PHY_FORCE_TIME; i > 0; i--) {
2424 /* Read the MII Status Register and wait for Auto-Neg Complete bit
2427 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
2431 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
2435 if (mii_status_reg & MII_SR_LINK_STATUS) break;
2439 ((hw->phy_type == e1000_phy_m88) ||
2440 (hw->phy_type == e1000_phy_gg82563))) {
2441 /* We didn't get link. Reset the DSP and wait again for link. */
2442 ret_val = e1000_phy_reset_dsp(hw);
2444 DEBUGOUT("Error Resetting PHY DSP\n");
2448 /* This loop will early-out if the link condition has been met. */
2449 for (i = PHY_FORCE_TIME; i > 0; i--) {
2450 if (mii_status_reg & MII_SR_LINK_STATUS) break;
2452 /* Read the MII Status Register and wait for Auto-Neg Complete bit
2455 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
2459 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
2465 if (hw->phy_type == e1000_phy_m88) {
2466 /* Because we reset the PHY above, we need to re-force TX_CLK in the
2467 * Extended PHY Specific Control Register to 25MHz clock. This value
2468 * defaults back to a 2.5MHz clock when the PHY is reset.
2470 ret_val = e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
2474 phy_data |= M88E1000_EPSCR_TX_CLK_25;
2475 ret_val = e1000_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
2479 /* In addition, because of the s/w reset above, we need to enable CRS on
2480 * TX. This must be set for both full and half duplex operation.
2482 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
2486 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
2487 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
2491 if ((hw->mac_type == e1000_82544 || hw->mac_type == e1000_82543) &&
2492 (!hw->autoneg) && (hw->forced_speed_duplex == e1000_10_full ||
2493 hw->forced_speed_duplex == e1000_10_half)) {
2494 ret_val = e1000_polarity_reversal_workaround(hw);
2498 } else if (hw->phy_type == e1000_phy_gg82563) {
2499 /* The TX_CLK of the Extended PHY Specific Control Register defaults
2500 * to 2.5MHz on a reset. We need to re-force it back to 25MHz, if
2501 * we're not in a forced 10/duplex configuration. */
2502 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, &phy_data);
2506 phy_data &= ~GG82563_MSCR_TX_CLK_MASK;
2507 if ((hw->forced_speed_duplex == e1000_10_full) ||
2508 (hw->forced_speed_duplex == e1000_10_half))
2509 phy_data |= GG82563_MSCR_TX_CLK_10MBPS_2_5MHZ;
2511 phy_data |= GG82563_MSCR_TX_CLK_100MBPS_25MHZ;
2513 /* Also due to the reset, we need to enable CRS on Tx. */
2514 phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
2516 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, phy_data);
2520 return E1000_SUCCESS;
2523 /******************************************************************************
2524 * Sets the collision distance in the Transmit Control register
2526 * hw - Struct containing variables accessed by shared code
2528 * Link should have been established previously. Reads the speed and duplex
2529 * information from the Device Status register.
2530 ******************************************************************************/
2532 e1000_config_collision_dist(struct e1000_hw *hw)
2534 uint32_t tctl, coll_dist;
2536 DEBUGFUNC("e1000_config_collision_dist");
2538 if (hw->mac_type < e1000_82543)
2539 coll_dist = E1000_COLLISION_DISTANCE_82542;
2541 coll_dist = E1000_COLLISION_DISTANCE;
2543 tctl = E1000_READ_REG(hw, TCTL);
2545 tctl &= ~E1000_TCTL_COLD;
2546 tctl |= coll_dist << E1000_COLD_SHIFT;
2548 E1000_WRITE_REG(hw, TCTL, tctl);
2549 E1000_WRITE_FLUSH(hw);
2552 /******************************************************************************
2553 * Sets MAC speed and duplex settings to reflect the those in the PHY
2555 * hw - Struct containing variables accessed by shared code
2556 * mii_reg - data to write to the MII control register
2558 * The contents of the PHY register containing the needed information need to
2560 ******************************************************************************/
2562 e1000_config_mac_to_phy(struct e1000_hw *hw)
2568 DEBUGFUNC("e1000_config_mac_to_phy");
2570 /* 82544 or newer MAC, Auto Speed Detection takes care of
2571 * MAC speed/duplex configuration.*/
2572 if (hw->mac_type >= e1000_82544)
2573 return E1000_SUCCESS;
2575 /* Read the Device Control Register and set the bits to Force Speed
2578 ctrl = E1000_READ_REG(hw, CTRL);
2579 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
2580 ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS);
2582 /* Set up duplex in the Device Control and Transmit Control
2583 * registers depending on negotiated values.
2585 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
2589 if (phy_data & M88E1000_PSSR_DPLX)
2590 ctrl |= E1000_CTRL_FD;
2592 ctrl &= ~E1000_CTRL_FD;
2594 e1000_config_collision_dist(hw);
2596 /* Set up speed in the Device Control register depending on
2597 * negotiated values.
2599 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS)
2600 ctrl |= E1000_CTRL_SPD_1000;
2601 else if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS)
2602 ctrl |= E1000_CTRL_SPD_100;
2604 /* Write the configured values back to the Device Control Reg. */
2605 E1000_WRITE_REG(hw, CTRL, ctrl);
2606 return E1000_SUCCESS;
2609 /******************************************************************************
2610 * Forces the MAC's flow control settings.
2612 * hw - Struct containing variables accessed by shared code
2614 * Sets the TFCE and RFCE bits in the device control register to reflect
2615 * the adapter settings. TFCE and RFCE need to be explicitly set by
2616 * software when a Copper PHY is used because autonegotiation is managed
2617 * by the PHY rather than the MAC. Software must also configure these
2618 * bits when link is forced on a fiber connection.
2619 *****************************************************************************/
2621 e1000_force_mac_fc(struct e1000_hw *hw)
2625 DEBUGFUNC("e1000_force_mac_fc");
2627 /* Get the current configuration of the Device Control Register */
2628 ctrl = E1000_READ_REG(hw, CTRL);
2630 /* Because we didn't get link via the internal auto-negotiation
2631 * mechanism (we either forced link or we got link via PHY
2632 * auto-neg), we have to manually enable/disable transmit an
2633 * receive flow control.
2635 * The "Case" statement below enables/disable flow control
2636 * according to the "hw->fc" parameter.
2638 * The possible values of the "fc" parameter are:
2639 * 0: Flow control is completely disabled
2640 * 1: Rx flow control is enabled (we can receive pause
2641 * frames but not send pause frames).
2642 * 2: Tx flow control is enabled (we can send pause frames
2643 * frames but we do not receive pause frames).
2644 * 3: Both Rx and TX flow control (symmetric) is enabled.
2645 * other: No other values should be possible at this point.
2650 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
2652 case E1000_FC_RX_PAUSE:
2653 ctrl &= (~E1000_CTRL_TFCE);
2654 ctrl |= E1000_CTRL_RFCE;
2656 case E1000_FC_TX_PAUSE:
2657 ctrl &= (~E1000_CTRL_RFCE);
2658 ctrl |= E1000_CTRL_TFCE;
2661 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
2664 DEBUGOUT("Flow control param set incorrectly\n");
2665 return -E1000_ERR_CONFIG;
2668 /* Disable TX Flow Control for 82542 (rev 2.0) */
2669 if (hw->mac_type == e1000_82542_rev2_0)
2670 ctrl &= (~E1000_CTRL_TFCE);
2672 E1000_WRITE_REG(hw, CTRL, ctrl);
2673 return E1000_SUCCESS;
2676 /******************************************************************************
2677 * Configures flow control settings after link is established
2679 * hw - Struct containing variables accessed by shared code
2681 * Should be called immediately after a valid link has been established.
2682 * Forces MAC flow control settings if link was forced. When in MII/GMII mode
2683 * and autonegotiation is enabled, the MAC flow control settings will be set
2684 * based on the flow control negotiated by the PHY. In TBI mode, the TFCE
2685 * and RFCE bits will be automaticaly set to the negotiated flow control mode.
2686 *****************************************************************************/
2688 e1000_config_fc_after_link_up(struct e1000_hw *hw)
2691 uint16_t mii_status_reg;
2692 uint16_t mii_nway_adv_reg;
2693 uint16_t mii_nway_lp_ability_reg;
2697 DEBUGFUNC("e1000_config_fc_after_link_up");
2699 /* Check for the case where we have fiber media and auto-neg failed
2700 * so we had to force link. In this case, we need to force the
2701 * configuration of the MAC to match the "fc" parameter.
2703 if (((hw->media_type == e1000_media_type_fiber) && (hw->autoneg_failed)) ||
2704 ((hw->media_type == e1000_media_type_internal_serdes) &&
2705 (hw->autoneg_failed)) ||
2706 ((hw->media_type == e1000_media_type_copper) && (!hw->autoneg))) {
2707 ret_val = e1000_force_mac_fc(hw);
2709 DEBUGOUT("Error forcing flow control settings\n");
2714 /* Check for the case where we have copper media and auto-neg is
2715 * enabled. In this case, we need to check and see if Auto-Neg
2716 * has completed, and if so, how the PHY and link partner has
2717 * flow control configured.
2719 if ((hw->media_type == e1000_media_type_copper) && hw->autoneg) {
2720 /* Read the MII Status Register and check to see if AutoNeg
2721 * has completed. We read this twice because this reg has
2722 * some "sticky" (latched) bits.
2724 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
2727 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
2731 if (mii_status_reg & MII_SR_AUTONEG_COMPLETE) {
2732 /* The AutoNeg process has completed, so we now need to
2733 * read both the Auto Negotiation Advertisement Register
2734 * (Address 4) and the Auto_Negotiation Base Page Ability
2735 * Register (Address 5) to determine how flow control was
2738 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV,
2742 ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY,
2743 &mii_nway_lp_ability_reg);
2747 /* Two bits in the Auto Negotiation Advertisement Register
2748 * (Address 4) and two bits in the Auto Negotiation Base
2749 * Page Ability Register (Address 5) determine flow control
2750 * for both the PHY and the link partner. The following
2751 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
2752 * 1999, describes these PAUSE resolution bits and how flow
2753 * control is determined based upon these settings.
2754 * NOTE: DC = Don't Care
2756 * LOCAL DEVICE | LINK PARTNER
2757 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
2758 *-------|---------|-------|---------|--------------------
2759 * 0 | 0 | DC | DC | E1000_FC_NONE
2760 * 0 | 1 | 0 | DC | E1000_FC_NONE
2761 * 0 | 1 | 1 | 0 | E1000_FC_NONE
2762 * 0 | 1 | 1 | 1 | E1000_FC_TX_PAUSE
2763 * 1 | 0 | 0 | DC | E1000_FC_NONE
2764 * 1 | DC | 1 | DC | E1000_FC_FULL
2765 * 1 | 1 | 0 | 0 | E1000_FC_NONE
2766 * 1 | 1 | 0 | 1 | E1000_FC_RX_PAUSE
2769 /* Are both PAUSE bits set to 1? If so, this implies
2770 * Symmetric Flow Control is enabled at both ends. The
2771 * ASM_DIR bits are irrelevant per the spec.
2773 * For Symmetric Flow Control:
2775 * LOCAL DEVICE | LINK PARTNER
2776 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
2777 *-------|---------|-------|---------|--------------------
2778 * 1 | DC | 1 | DC | E1000_FC_FULL
2781 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
2782 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
2783 /* Now we need to check if the user selected RX ONLY
2784 * of pause frames. In this case, we had to advertise
2785 * FULL flow control because we could not advertise RX
2786 * ONLY. Hence, we must now check to see if we need to
2787 * turn OFF the TRANSMISSION of PAUSE frames.
2789 if (hw->original_fc == E1000_FC_FULL) {
2790 hw->fc = E1000_FC_FULL;
2791 DEBUGOUT("Flow Control = FULL.\n");
2793 hw->fc = E1000_FC_RX_PAUSE;
2794 DEBUGOUT("Flow Control = RX PAUSE frames only.\n");
2797 /* For receiving PAUSE frames ONLY.
2799 * LOCAL DEVICE | LINK PARTNER
2800 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
2801 *-------|---------|-------|---------|--------------------
2802 * 0 | 1 | 1 | 1 | E1000_FC_TX_PAUSE
2805 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
2806 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
2807 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
2808 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
2809 hw->fc = E1000_FC_TX_PAUSE;
2810 DEBUGOUT("Flow Control = TX PAUSE frames only.\n");
2812 /* For transmitting PAUSE frames ONLY.
2814 * LOCAL DEVICE | LINK PARTNER
2815 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
2816 *-------|---------|-------|---------|--------------------
2817 * 1 | 1 | 0 | 1 | E1000_FC_RX_PAUSE
2820 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
2821 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
2822 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
2823 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
2824 hw->fc = E1000_FC_RX_PAUSE;
2825 DEBUGOUT("Flow Control = RX PAUSE frames only.\n");
2827 /* Per the IEEE spec, at this point flow control should be
2828 * disabled. However, we want to consider that we could
2829 * be connected to a legacy switch that doesn't advertise
2830 * desired flow control, but can be forced on the link
2831 * partner. So if we advertised no flow control, that is
2832 * what we will resolve to. If we advertised some kind of
2833 * receive capability (Rx Pause Only or Full Flow Control)
2834 * and the link partner advertised none, we will configure
2835 * ourselves to enable Rx Flow Control only. We can do
2836 * this safely for two reasons: If the link partner really
2837 * didn't want flow control enabled, and we enable Rx, no
2838 * harm done since we won't be receiving any PAUSE frames
2839 * anyway. If the intent on the link partner was to have
2840 * flow control enabled, then by us enabling RX only, we
2841 * can at least receive pause frames and process them.
2842 * This is a good idea because in most cases, since we are
2843 * predominantly a server NIC, more times than not we will
2844 * be asked to delay transmission of packets than asking
2845 * our link partner to pause transmission of frames.
2847 else if ((hw->original_fc == E1000_FC_NONE ||
2848 hw->original_fc == E1000_FC_TX_PAUSE) ||
2849 hw->fc_strict_ieee) {
2850 hw->fc = E1000_FC_NONE;
2851 DEBUGOUT("Flow Control = NONE.\n");
2853 hw->fc = E1000_FC_RX_PAUSE;
2854 DEBUGOUT("Flow Control = RX PAUSE frames only.\n");
2857 /* Now we need to do one last check... If we auto-
2858 * negotiated to HALF DUPLEX, flow control should not be
2859 * enabled per IEEE 802.3 spec.
2861 ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex);
2863 DEBUGOUT("Error getting link speed and duplex\n");
2867 if (duplex == HALF_DUPLEX)
2868 hw->fc = E1000_FC_NONE;
2870 /* Now we call a subroutine to actually force the MAC
2871 * controller to use the correct flow control settings.
2873 ret_val = e1000_force_mac_fc(hw);
2875 DEBUGOUT("Error forcing flow control settings\n");
2879 DEBUGOUT("Copper PHY and Auto Neg has not completed.\n");
2882 return E1000_SUCCESS;
2885 /******************************************************************************
2886 * Checks to see if the link status of the hardware has changed.
2888 * hw - Struct containing variables accessed by shared code
2890 * Called by any function that needs to check the link status of the adapter.
2891 *****************************************************************************/
2893 e1000_check_for_link(struct e1000_hw *hw)
2900 uint32_t signal = 0;
2904 DEBUGFUNC("e1000_check_for_link");
2906 ctrl = E1000_READ_REG(hw, CTRL);
2907 status = E1000_READ_REG(hw, STATUS);
2909 /* On adapters with a MAC newer than 82544, SW Defineable pin 1 will be
2910 * set when the optics detect a signal. On older adapters, it will be
2911 * cleared when there is a signal. This applies to fiber media only.
2913 if ((hw->media_type == e1000_media_type_fiber) ||
2914 (hw->media_type == e1000_media_type_internal_serdes)) {
2915 rxcw = E1000_READ_REG(hw, RXCW);
2917 if (hw->media_type == e1000_media_type_fiber) {
2918 signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0;
2919 if (status & E1000_STATUS_LU)
2920 hw->get_link_status = FALSE;
2924 /* If we have a copper PHY then we only want to go out to the PHY
2925 * registers to see if Auto-Neg has completed and/or if our link
2926 * status has changed. The get_link_status flag will be set if we
2927 * receive a Link Status Change interrupt or we have Rx Sequence
2930 if ((hw->media_type == e1000_media_type_copper) && hw->get_link_status) {
2931 /* First we want to see if the MII Status Register reports
2932 * link. If so, then we want to get the current speed/duplex
2934 * Read the register twice since the link bit is sticky.
2936 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
2939 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
2943 if (phy_data & MII_SR_LINK_STATUS) {
2944 hw->get_link_status = FALSE;
2945 /* Check if there was DownShift, must be checked immediately after
2947 e1000_check_downshift(hw);
2949 /* If we are on 82544 or 82543 silicon and speed/duplex
2950 * are forced to 10H or 10F, then we will implement the polarity
2951 * reversal workaround. We disable interrupts first, and upon
2952 * returning, place the devices interrupt state to its previous
2953 * value except for the link status change interrupt which will
2954 * happen due to the execution of this workaround.
2957 if ((hw->mac_type == e1000_82544 || hw->mac_type == e1000_82543) &&
2959 (hw->forced_speed_duplex == e1000_10_full ||
2960 hw->forced_speed_duplex == e1000_10_half)) {
2961 E1000_WRITE_REG(hw, IMC, 0xffffffff);
2962 ret_val = e1000_polarity_reversal_workaround(hw);
2963 icr = E1000_READ_REG(hw, ICR);
2964 E1000_WRITE_REG(hw, ICS, (icr & ~E1000_ICS_LSC));
2965 E1000_WRITE_REG(hw, IMS, IMS_ENABLE_MASK);
2969 /* No link detected */
2970 e1000_config_dsp_after_link_change(hw, FALSE);
2974 /* If we are forcing speed/duplex, then we simply return since
2975 * we have already determined whether we have link or not.
2977 if (!hw->autoneg) return -E1000_ERR_CONFIG;
2979 /* optimize the dsp settings for the igp phy */
2980 e1000_config_dsp_after_link_change(hw, TRUE);
2982 /* We have a M88E1000 PHY and Auto-Neg is enabled. If we
2983 * have Si on board that is 82544 or newer, Auto
2984 * Speed Detection takes care of MAC speed/duplex
2985 * configuration. So we only need to configure Collision
2986 * Distance in the MAC. Otherwise, we need to force
2987 * speed/duplex on the MAC to the current PHY speed/duplex
2990 if (hw->mac_type >= e1000_82544)
2991 e1000_config_collision_dist(hw);
2993 ret_val = e1000_config_mac_to_phy(hw);
2995 DEBUGOUT("Error configuring MAC to PHY settings\n");
3000 /* Configure Flow Control now that Auto-Neg has completed. First, we
3001 * need to restore the desired flow control settings because we may
3002 * have had to re-autoneg with a different link partner.
3004 ret_val = e1000_config_fc_after_link_up(hw);
3006 DEBUGOUT("Error configuring flow control\n");
3010 /* At this point we know that we are on copper and we have
3011 * auto-negotiated link. These are conditions for checking the link
3012 * partner capability register. We use the link speed to determine if
3013 * TBI compatibility needs to be turned on or off. If the link is not
3014 * at gigabit speed, then TBI compatibility is not needed. If we are
3015 * at gigabit speed, we turn on TBI compatibility.
3017 if (hw->tbi_compatibility_en) {
3018 uint16_t speed, duplex;
3019 ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex);
3021 DEBUGOUT("Error getting link speed and duplex\n");
3024 if (speed != SPEED_1000) {
3025 /* If link speed is not set to gigabit speed, we do not need
3026 * to enable TBI compatibility.
3028 if (hw->tbi_compatibility_on) {
3029 /* If we previously were in the mode, turn it off. */
3030 rctl = E1000_READ_REG(hw, RCTL);
3031 rctl &= ~E1000_RCTL_SBP;
3032 E1000_WRITE_REG(hw, RCTL, rctl);
3033 hw->tbi_compatibility_on = FALSE;
3036 /* If TBI compatibility is was previously off, turn it on. For
3037 * compatibility with a TBI link partner, we will store bad
3038 * packets. Some frames have an additional byte on the end and
3039 * will look like CRC errors to to the hardware.
3041 if (!hw->tbi_compatibility_on) {
3042 hw->tbi_compatibility_on = TRUE;
3043 rctl = E1000_READ_REG(hw, RCTL);
3044 rctl |= E1000_RCTL_SBP;
3045 E1000_WRITE_REG(hw, RCTL, rctl);
3050 /* If we don't have link (auto-negotiation failed or link partner cannot
3051 * auto-negotiate), the cable is plugged in (we have signal), and our
3052 * link partner is not trying to auto-negotiate with us (we are receiving
3053 * idles or data), we need to force link up. We also need to give
3054 * auto-negotiation time to complete, in case the cable was just plugged
3055 * in. The autoneg_failed flag does this.
3057 else if ((((hw->media_type == e1000_media_type_fiber) &&
3058 ((ctrl & E1000_CTRL_SWDPIN1) == signal)) ||
3059 (hw->media_type == e1000_media_type_internal_serdes)) &&
3060 (!(status & E1000_STATUS_LU)) &&
3061 (!(rxcw & E1000_RXCW_C))) {
3062 if (hw->autoneg_failed == 0) {
3063 hw->autoneg_failed = 1;
3066 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\n");
3068 /* Disable auto-negotiation in the TXCW register */
3069 E1000_WRITE_REG(hw, TXCW, (hw->txcw & ~E1000_TXCW_ANE));
3071 /* Force link-up and also force full-duplex. */
3072 ctrl = E1000_READ_REG(hw, CTRL);
3073 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
3074 E1000_WRITE_REG(hw, CTRL, ctrl);
3076 /* Configure Flow Control after forcing link up. */
3077 ret_val = e1000_config_fc_after_link_up(hw);
3079 DEBUGOUT("Error configuring flow control\n");
3083 /* If we are forcing link and we are receiving /C/ ordered sets, re-enable
3084 * auto-negotiation in the TXCW register and disable forced link in the
3085 * Device Control register in an attempt to auto-negotiate with our link
3088 else if (((hw->media_type == e1000_media_type_fiber) ||
3089 (hw->media_type == e1000_media_type_internal_serdes)) &&
3090 (ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
3091 DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n");
3092 E1000_WRITE_REG(hw, TXCW, hw->txcw);
3093 E1000_WRITE_REG(hw, CTRL, (ctrl & ~E1000_CTRL_SLU));
3095 hw->serdes_link_down = FALSE;
3097 /* If we force link for non-auto-negotiation switch, check link status
3098 * based on MAC synchronization for internal serdes media type.
3100 else if ((hw->media_type == e1000_media_type_internal_serdes) &&
3101 !(E1000_TXCW_ANE & E1000_READ_REG(hw, TXCW))) {
3102 /* SYNCH bit and IV bit are sticky. */
3104 if (E1000_RXCW_SYNCH & E1000_READ_REG(hw, RXCW)) {
3105 if (!(rxcw & E1000_RXCW_IV)) {
3106 hw->serdes_link_down = FALSE;
3107 DEBUGOUT("SERDES: Link is up.\n");
3110 hw->serdes_link_down = TRUE;
3111 DEBUGOUT("SERDES: Link is down.\n");
3114 if ((hw->media_type == e1000_media_type_internal_serdes) &&
3115 (E1000_TXCW_ANE & E1000_READ_REG(hw, TXCW))) {
3116 hw->serdes_link_down = !(E1000_STATUS_LU & E1000_READ_REG(hw, STATUS));
3118 return E1000_SUCCESS;
3121 /******************************************************************************
3122 * Detects the current speed and duplex settings of the hardware.
3124 * hw - Struct containing variables accessed by shared code
3125 * speed - Speed of the connection
3126 * duplex - Duplex setting of the connection
3127 *****************************************************************************/
3129 e1000_get_speed_and_duplex(struct e1000_hw *hw,
3137 DEBUGFUNC("e1000_get_speed_and_duplex");
3139 if (hw->mac_type >= e1000_82543) {
3140 status = E1000_READ_REG(hw, STATUS);
3141 if (status & E1000_STATUS_SPEED_1000) {
3142 *speed = SPEED_1000;
3143 DEBUGOUT("1000 Mbs, ");
3144 } else if (status & E1000_STATUS_SPEED_100) {
3146 DEBUGOUT("100 Mbs, ");
3149 DEBUGOUT("10 Mbs, ");
3152 if (status & E1000_STATUS_FD) {
3153 *duplex = FULL_DUPLEX;
3154 DEBUGOUT("Full Duplex\n");
3156 *duplex = HALF_DUPLEX;
3157 DEBUGOUT(" Half Duplex\n");
3160 DEBUGOUT("1000 Mbs, Full Duplex\n");
3161 *speed = SPEED_1000;
3162 *duplex = FULL_DUPLEX;
3165 /* IGP01 PHY may advertise full duplex operation after speed downgrade even
3166 * if it is operating at half duplex. Here we set the duplex settings to
3167 * match the duplex in the link partner's capabilities.
3169 if (hw->phy_type == e1000_phy_igp && hw->speed_downgraded) {
3170 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data);
3174 if (!(phy_data & NWAY_ER_LP_NWAY_CAPS))
3175 *duplex = HALF_DUPLEX;
3177 ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY, &phy_data);
3180 if ((*speed == SPEED_100 && !(phy_data & NWAY_LPAR_100TX_FD_CAPS)) ||
3181 (*speed == SPEED_10 && !(phy_data & NWAY_LPAR_10T_FD_CAPS)))
3182 *duplex = HALF_DUPLEX;
3186 if ((hw->mac_type == e1000_80003es2lan) &&
3187 (hw->media_type == e1000_media_type_copper)) {
3188 if (*speed == SPEED_1000)
3189 ret_val = e1000_configure_kmrn_for_1000(hw);
3191 ret_val = e1000_configure_kmrn_for_10_100(hw, *duplex);
3196 if ((hw->phy_type == e1000_phy_igp_3) && (*speed == SPEED_1000)) {
3197 ret_val = e1000_kumeran_lock_loss_workaround(hw);
3202 return E1000_SUCCESS;
3205 /******************************************************************************
3206 * Blocks until autoneg completes or times out (~4.5 seconds)
3208 * hw - Struct containing variables accessed by shared code
3209 ******************************************************************************/
3211 e1000_wait_autoneg(struct e1000_hw *hw)
3217 DEBUGFUNC("e1000_wait_autoneg");
3218 DEBUGOUT("Waiting for Auto-Neg to complete.\n");
3220 /* We will wait for autoneg to complete or 4.5 seconds to expire. */
3221 for (i = PHY_AUTO_NEG_TIME; i > 0; i--) {
3222 /* Read the MII Status Register and wait for Auto-Neg
3223 * Complete bit to be set.
3225 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
3228 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
3231 if (phy_data & MII_SR_AUTONEG_COMPLETE) {
3232 return E1000_SUCCESS;
3236 return E1000_SUCCESS;
3239 /******************************************************************************
3240 * Raises the Management Data Clock
3242 * hw - Struct containing variables accessed by shared code
3243 * ctrl - Device control register's current value
3244 ******************************************************************************/
3246 e1000_raise_mdi_clk(struct e1000_hw *hw,
3249 /* Raise the clock input to the Management Data Clock (by setting the MDC
3250 * bit), and then delay 10 microseconds.
3252 E1000_WRITE_REG(hw, CTRL, (*ctrl | E1000_CTRL_MDC));
3253 E1000_WRITE_FLUSH(hw);
3257 /******************************************************************************
3258 * Lowers the Management Data Clock
3260 * hw - Struct containing variables accessed by shared code
3261 * ctrl - Device control register's current value
3262 ******************************************************************************/
3264 e1000_lower_mdi_clk(struct e1000_hw *hw,
3267 /* Lower the clock input to the Management Data Clock (by clearing the MDC
3268 * bit), and then delay 10 microseconds.
3270 E1000_WRITE_REG(hw, CTRL, (*ctrl & ~E1000_CTRL_MDC));
3271 E1000_WRITE_FLUSH(hw);
3275 /******************************************************************************
3276 * Shifts data bits out to the PHY
3278 * hw - Struct containing variables accessed by shared code
3279 * data - Data to send out to the PHY
3280 * count - Number of bits to shift out
3282 * Bits are shifted out in MSB to LSB order.
3283 ******************************************************************************/
3285 e1000_shift_out_mdi_bits(struct e1000_hw *hw,
3292 /* We need to shift "count" number of bits out to the PHY. So, the value
3293 * in the "data" parameter will be shifted out to the PHY one bit at a
3294 * time. In order to do this, "data" must be broken down into bits.
3297 mask <<= (count - 1);
3299 ctrl = E1000_READ_REG(hw, CTRL);
3301 /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */
3302 ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR);
3305 /* A "1" is shifted out to the PHY by setting the MDIO bit to "1" and
3306 * then raising and lowering the Management Data Clock. A "0" is
3307 * shifted out to the PHY by setting the MDIO bit to "0" and then
3308 * raising and lowering the clock.
3311 ctrl |= E1000_CTRL_MDIO;
3313 ctrl &= ~E1000_CTRL_MDIO;
3315 E1000_WRITE_REG(hw, CTRL, ctrl);
3316 E1000_WRITE_FLUSH(hw);
3320 e1000_raise_mdi_clk(hw, &ctrl);
3321 e1000_lower_mdi_clk(hw, &ctrl);
3327 /******************************************************************************
3328 * Shifts data bits in from the PHY
3330 * hw - Struct containing variables accessed by shared code
3332 * Bits are shifted in in MSB to LSB order.
3333 ******************************************************************************/
3335 e1000_shift_in_mdi_bits(struct e1000_hw *hw)
3341 /* In order to read a register from the PHY, we need to shift in a total
3342 * of 18 bits from the PHY. The first two bit (turnaround) times are used
3343 * to avoid contention on the MDIO pin when a read operation is performed.
3344 * These two bits are ignored by us and thrown away. Bits are "shifted in"
3345 * by raising the input to the Management Data Clock (setting the MDC bit),
3346 * and then reading the value of the MDIO bit.
3348 ctrl = E1000_READ_REG(hw, CTRL);
3350 /* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as input. */
3351 ctrl &= ~E1000_CTRL_MDIO_DIR;
3352 ctrl &= ~E1000_CTRL_MDIO;
3354 E1000_WRITE_REG(hw, CTRL, ctrl);
3355 E1000_WRITE_FLUSH(hw);
3357 /* Raise and Lower the clock before reading in the data. This accounts for
3358 * the turnaround bits. The first clock occurred when we clocked out the
3359 * last bit of the Register Address.
3361 e1000_raise_mdi_clk(hw, &ctrl);
3362 e1000_lower_mdi_clk(hw, &ctrl);
3364 for (data = 0, i = 0; i < 16; i++) {
3366 e1000_raise_mdi_clk(hw, &ctrl);
3367 ctrl = E1000_READ_REG(hw, CTRL);
3368 /* Check to see if we shifted in a "1". */
3369 if (ctrl & E1000_CTRL_MDIO)
3371 e1000_lower_mdi_clk(hw, &ctrl);
3374 e1000_raise_mdi_clk(hw, &ctrl);
3375 e1000_lower_mdi_clk(hw, &ctrl);
3381 e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask)
3383 uint32_t swfw_sync = 0;
3384 uint32_t swmask = mask;
3385 uint32_t fwmask = mask << 16;
3386 int32_t timeout = 200;
3388 DEBUGFUNC("e1000_swfw_sync_acquire");
3390 if (hw->swfwhw_semaphore_present)
3391 return e1000_get_software_flag(hw);
3393 if (!hw->swfw_sync_present)
3394 return e1000_get_hw_eeprom_semaphore(hw);
3397 if (e1000_get_hw_eeprom_semaphore(hw))
3398 return -E1000_ERR_SWFW_SYNC;
3400 swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC);
3401 if (!(swfw_sync & (fwmask | swmask))) {
3405 /* firmware currently using resource (fwmask) */
3406 /* or other software thread currently using resource (swmask) */
3407 e1000_put_hw_eeprom_semaphore(hw);
3413 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n");
3414 return -E1000_ERR_SWFW_SYNC;
3417 swfw_sync |= swmask;
3418 E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync);
3420 e1000_put_hw_eeprom_semaphore(hw);
3421 return E1000_SUCCESS;
3425 e1000_swfw_sync_release(struct e1000_hw *hw, uint16_t mask)
3428 uint32_t swmask = mask;
3430 DEBUGFUNC("e1000_swfw_sync_release");
3432 if (hw->swfwhw_semaphore_present) {
3433 e1000_release_software_flag(hw);
3437 if (!hw->swfw_sync_present) {
3438 e1000_put_hw_eeprom_semaphore(hw);
3442 /* if (e1000_get_hw_eeprom_semaphore(hw))
3443 * return -E1000_ERR_SWFW_SYNC; */
3444 while (e1000_get_hw_eeprom_semaphore(hw) != E1000_SUCCESS);
3447 swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC);
3448 swfw_sync &= ~swmask;
3449 E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync);
3451 e1000_put_hw_eeprom_semaphore(hw);
3454 /*****************************************************************************
3455 * Reads the value from a PHY register, if the value is on a specific non zero
3456 * page, sets the page first.
3457 * hw - Struct containing variables accessed by shared code
3458 * reg_addr - address of the PHY register to read
3459 ******************************************************************************/
3461 e1000_read_phy_reg(struct e1000_hw *hw,
3468 DEBUGFUNC("e1000_read_phy_reg");
3470 if ((hw->mac_type == e1000_80003es2lan) &&
3471 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
3472 swfw = E1000_SWFW_PHY1_SM;
3474 swfw = E1000_SWFW_PHY0_SM;
3476 if (e1000_swfw_sync_acquire(hw, swfw))
3477 return -E1000_ERR_SWFW_SYNC;
3479 if ((hw->phy_type == e1000_phy_igp ||
3480 hw->phy_type == e1000_phy_igp_3 ||
3481 hw->phy_type == e1000_phy_igp_2) &&
3482 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
3483 ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
3484 (uint16_t)reg_addr);
3486 e1000_swfw_sync_release(hw, swfw);
3489 } else if (hw->phy_type == e1000_phy_gg82563) {
3490 if (((reg_addr & MAX_PHY_REG_ADDRESS) > MAX_PHY_MULTI_PAGE_REG) ||
3491 (hw->mac_type == e1000_80003es2lan)) {
3492 /* Select Configuration Page */
3493 if ((reg_addr & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
3494 ret_val = e1000_write_phy_reg_ex(hw, GG82563_PHY_PAGE_SELECT,
3495 (uint16_t)((uint16_t)reg_addr >> GG82563_PAGE_SHIFT));
3497 /* Use Alternative Page Select register to access
3498 * registers 30 and 31
3500 ret_val = e1000_write_phy_reg_ex(hw,
3501 GG82563_PHY_PAGE_SELECT_ALT,
3502 (uint16_t)((uint16_t)reg_addr >> GG82563_PAGE_SHIFT));
3506 e1000_swfw_sync_release(hw, swfw);
3512 ret_val = e1000_read_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr,
3515 e1000_swfw_sync_release(hw, swfw);
3520 e1000_read_phy_reg_ex(struct e1000_hw *hw, uint32_t reg_addr,
3525 const uint32_t phy_addr = 1;
3527 DEBUGFUNC("e1000_read_phy_reg_ex");
3529 if (reg_addr > MAX_PHY_REG_ADDRESS) {
3530 DEBUGOUT1("PHY Address %d is out of range\n", reg_addr);
3531 return -E1000_ERR_PARAM;
3534 if (hw->mac_type > e1000_82543) {
3535 /* Set up Op-code, Phy Address, and register address in the MDI
3536 * Control register. The MAC will take care of interfacing with the
3537 * PHY to retrieve the desired data.
3539 mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) |
3540 (phy_addr << E1000_MDIC_PHY_SHIFT) |
3541 (E1000_MDIC_OP_READ));
3543 E1000_WRITE_REG(hw, MDIC, mdic);
3545 /* Poll the ready bit to see if the MDI read completed */
3546 for (i = 0; i < 64; i++) {
3548 mdic = E1000_READ_REG(hw, MDIC);
3549 if (mdic & E1000_MDIC_READY) break;
3551 if (!(mdic & E1000_MDIC_READY)) {
3552 DEBUGOUT("MDI Read did not complete\n");
3553 return -E1000_ERR_PHY;
3555 if (mdic & E1000_MDIC_ERROR) {
3556 DEBUGOUT("MDI Error\n");
3557 return -E1000_ERR_PHY;
3559 *phy_data = (uint16_t) mdic;
3561 /* We must first send a preamble through the MDIO pin to signal the
3562 * beginning of an MII instruction. This is done by sending 32
3563 * consecutive "1" bits.
3565 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
3567 /* Now combine the next few fields that are required for a read
3568 * operation. We use this method instead of calling the
3569 * e1000_shift_out_mdi_bits routine five different times. The format of
3570 * a MII read instruction consists of a shift out of 14 bits and is
3571 * defined as follows:
3572 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr>
3573 * followed by a shift in of 18 bits. This first two bits shifted in
3574 * are TurnAround bits used to avoid contention on the MDIO pin when a
3575 * READ operation is performed. These two bits are thrown away
3576 * followed by a shift in of 16 bits which contains the desired data.
3578 mdic = ((reg_addr) | (phy_addr << 5) |
3579 (PHY_OP_READ << 10) | (PHY_SOF << 12));
3581 e1000_shift_out_mdi_bits(hw, mdic, 14);
3583 /* Now that we've shifted out the read command to the MII, we need to
3584 * "shift in" the 16-bit value (18 total bits) of the requested PHY
3587 *phy_data = e1000_shift_in_mdi_bits(hw);
3589 return E1000_SUCCESS;
3592 /******************************************************************************
3593 * Writes a value to a PHY register
3595 * hw - Struct containing variables accessed by shared code
3596 * reg_addr - address of the PHY register to write
3597 * data - data to write to the PHY
3598 ******************************************************************************/
3600 e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr,
3606 DEBUGFUNC("e1000_write_phy_reg");
3608 if ((hw->mac_type == e1000_80003es2lan) &&
3609 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
3610 swfw = E1000_SWFW_PHY1_SM;
3612 swfw = E1000_SWFW_PHY0_SM;
3614 if (e1000_swfw_sync_acquire(hw, swfw))
3615 return -E1000_ERR_SWFW_SYNC;
3617 if ((hw->phy_type == e1000_phy_igp ||
3618 hw->phy_type == e1000_phy_igp_3 ||
3619 hw->phy_type == e1000_phy_igp_2) &&
3620 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
3621 ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
3622 (uint16_t)reg_addr);
3624 e1000_swfw_sync_release(hw, swfw);
3627 } else if (hw->phy_type == e1000_phy_gg82563) {
3628 if (((reg_addr & MAX_PHY_REG_ADDRESS) > MAX_PHY_MULTI_PAGE_REG) ||
3629 (hw->mac_type == e1000_80003es2lan)) {
3630 /* Select Configuration Page */
3631 if ((reg_addr & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
3632 ret_val = e1000_write_phy_reg_ex(hw, GG82563_PHY_PAGE_SELECT,
3633 (uint16_t)((uint16_t)reg_addr >> GG82563_PAGE_SHIFT));
3635 /* Use Alternative Page Select register to access
3636 * registers 30 and 31
3638 ret_val = e1000_write_phy_reg_ex(hw,
3639 GG82563_PHY_PAGE_SELECT_ALT,
3640 (uint16_t)((uint16_t)reg_addr >> GG82563_PAGE_SHIFT));
3644 e1000_swfw_sync_release(hw, swfw);
3650 ret_val = e1000_write_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr,
3653 e1000_swfw_sync_release(hw, swfw);
3658 e1000_write_phy_reg_ex(struct e1000_hw *hw, uint32_t reg_addr,
3663 const uint32_t phy_addr = 1;
3665 DEBUGFUNC("e1000_write_phy_reg_ex");
3667 if (reg_addr > MAX_PHY_REG_ADDRESS) {
3668 DEBUGOUT1("PHY Address %d is out of range\n", reg_addr);
3669 return -E1000_ERR_PARAM;
3672 if (hw->mac_type > e1000_82543) {
3673 /* Set up Op-code, Phy Address, register address, and data intended
3674 * for the PHY register in the MDI Control register. The MAC will take
3675 * care of interfacing with the PHY to send the desired data.
3677 mdic = (((uint32_t) phy_data) |
3678 (reg_addr << E1000_MDIC_REG_SHIFT) |
3679 (phy_addr << E1000_MDIC_PHY_SHIFT) |
3680 (E1000_MDIC_OP_WRITE));
3682 E1000_WRITE_REG(hw, MDIC, mdic);
3684 /* Poll the ready bit to see if the MDI read completed */
3685 for (i = 0; i < 641; i++) {
3687 mdic = E1000_READ_REG(hw, MDIC);
3688 if (mdic & E1000_MDIC_READY) break;
3690 if (!(mdic & E1000_MDIC_READY)) {
3691 DEBUGOUT("MDI Write did not complete\n");
3692 return -E1000_ERR_PHY;
3695 /* We'll need to use the SW defined pins to shift the write command
3696 * out to the PHY. We first send a preamble to the PHY to signal the
3697 * beginning of the MII instruction. This is done by sending 32
3698 * consecutive "1" bits.
3700 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
3702 /* Now combine the remaining required fields that will indicate a
3703 * write operation. We use this method instead of calling the
3704 * e1000_shift_out_mdi_bits routine for each field in the command. The
3705 * format of a MII write instruction is as follows:
3706 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>.
3708 mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) |
3709 (PHY_OP_WRITE << 12) | (PHY_SOF << 14));
3711 mdic |= (uint32_t) phy_data;
3713 e1000_shift_out_mdi_bits(hw, mdic, 32);
3716 return E1000_SUCCESS;
3720 e1000_read_kmrn_reg(struct e1000_hw *hw,
3726 DEBUGFUNC("e1000_read_kmrn_reg");
3728 if ((hw->mac_type == e1000_80003es2lan) &&
3729 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
3730 swfw = E1000_SWFW_PHY1_SM;
3732 swfw = E1000_SWFW_PHY0_SM;
3734 if (e1000_swfw_sync_acquire(hw, swfw))
3735 return -E1000_ERR_SWFW_SYNC;
3737 /* Write register address */
3738 reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) &
3739 E1000_KUMCTRLSTA_OFFSET) |
3740 E1000_KUMCTRLSTA_REN;
3741 E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val);
3744 /* Read the data returned */
3745 reg_val = E1000_READ_REG(hw, KUMCTRLSTA);
3746 *data = (uint16_t)reg_val;
3748 e1000_swfw_sync_release(hw, swfw);
3749 return E1000_SUCCESS;
3753 e1000_write_kmrn_reg(struct e1000_hw *hw,
3759 DEBUGFUNC("e1000_write_kmrn_reg");
3761 if ((hw->mac_type == e1000_80003es2lan) &&
3762 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
3763 swfw = E1000_SWFW_PHY1_SM;
3765 swfw = E1000_SWFW_PHY0_SM;
3767 if (e1000_swfw_sync_acquire(hw, swfw))
3768 return -E1000_ERR_SWFW_SYNC;
3770 reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) &
3771 E1000_KUMCTRLSTA_OFFSET) | data;
3772 E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val);
3775 e1000_swfw_sync_release(hw, swfw);
3776 return E1000_SUCCESS;
3779 /******************************************************************************
3780 * Returns the PHY to the power-on reset state
3782 * hw - Struct containing variables accessed by shared code
3783 ******************************************************************************/
3785 e1000_phy_hw_reset(struct e1000_hw *hw)
3787 uint32_t ctrl, ctrl_ext;
3792 DEBUGFUNC("e1000_phy_hw_reset");
3794 /* In the case of the phy reset being blocked, it's not an error, we
3795 * simply return success without performing the reset. */
3796 ret_val = e1000_check_phy_reset_block(hw);
3798 return E1000_SUCCESS;
3800 DEBUGOUT("Resetting Phy...\n");
3802 if (hw->mac_type > e1000_82543) {
3803 if ((hw->mac_type == e1000_80003es2lan) &&
3804 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
3805 swfw = E1000_SWFW_PHY1_SM;
3807 swfw = E1000_SWFW_PHY0_SM;
3809 if (e1000_swfw_sync_acquire(hw, swfw)) {
3810 DEBUGOUT("Unable to acquire swfw sync\n");
3811 return -E1000_ERR_SWFW_SYNC;
3813 /* Read the device control register and assert the E1000_CTRL_PHY_RST
3814 * bit. Then, take it out of reset.
3815 * For pre-e1000_82571 hardware, we delay for 10ms between the assert
3816 * and deassert. For e1000_82571 hardware and later, we instead delay
3817 * for 50us between and 10ms after the deassertion.
3819 ctrl = E1000_READ_REG(hw, CTRL);
3820 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PHY_RST);
3821 E1000_WRITE_FLUSH(hw);
3823 if (hw->mac_type < e1000_82571)
3828 E1000_WRITE_REG(hw, CTRL, ctrl);
3829 E1000_WRITE_FLUSH(hw);
3831 if (hw->mac_type >= e1000_82571)
3834 e1000_swfw_sync_release(hw, swfw);
3836 /* Read the Extended Device Control Register, assert the PHY_RESET_DIR
3837 * bit to put the PHY into reset. Then, take it out of reset.
3839 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
3840 ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR;
3841 ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA;
3842 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
3843 E1000_WRITE_FLUSH(hw);
3845 ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA;
3846 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
3847 E1000_WRITE_FLUSH(hw);
3851 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
3852 /* Configure activity LED after PHY reset */
3853 led_ctrl = E1000_READ_REG(hw, LEDCTL);
3854 led_ctrl &= IGP_ACTIVITY_LED_MASK;
3855 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
3856 E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
3859 /* Wait for FW to finish PHY configuration. */
3860 ret_val = e1000_get_phy_cfg_done(hw);
3861 if (ret_val != E1000_SUCCESS)
3863 e1000_release_software_semaphore(hw);
3865 if ((hw->mac_type == e1000_ich8lan) && (hw->phy_type == e1000_phy_igp_3))
3866 ret_val = e1000_init_lcd_from_nvm(hw);
3871 /******************************************************************************
3874 * hw - Struct containing variables accessed by shared code
3876 * Sets bit 15 of the MII Control register
3877 ******************************************************************************/
3879 e1000_phy_reset(struct e1000_hw *hw)
3884 DEBUGFUNC("e1000_phy_reset");
3886 /* In the case of the phy reset being blocked, it's not an error, we
3887 * simply return success without performing the reset. */
3888 ret_val = e1000_check_phy_reset_block(hw);
3890 return E1000_SUCCESS;
3892 switch (hw->phy_type) {
3894 case e1000_phy_igp_2:
3895 case e1000_phy_igp_3:
3897 ret_val = e1000_phy_hw_reset(hw);
3902 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
3906 phy_data |= MII_CR_RESET;
3907 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
3915 if (hw->phy_type == e1000_phy_igp || hw->phy_type == e1000_phy_igp_2)
3916 e1000_phy_init_script(hw);
3918 return E1000_SUCCESS;
3921 /******************************************************************************
3922 * Work-around for 82566 power-down: on D3 entry-
3923 * 1) disable gigabit link
3924 * 2) write VR power-down enable
3926 * if successful continue, else issue LCD reset and repeat
3928 * hw - struct containing variables accessed by shared code
3929 ******************************************************************************/
3931 e1000_phy_powerdown_workaround(struct e1000_hw *hw)
3937 DEBUGFUNC("e1000_phy_powerdown_workaround");
3939 if (hw->phy_type != e1000_phy_igp_3)
3944 reg = E1000_READ_REG(hw, PHY_CTRL);
3945 E1000_WRITE_REG(hw, PHY_CTRL, reg | E1000_PHY_CTRL_GBE_DISABLE |
3946 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
3948 /* Write VR power-down enable - bits 9:8 should be 10b */
3949 e1000_read_phy_reg(hw, IGP3_VR_CTRL, &phy_data);
3950 phy_data |= (1 << 9);
3951 phy_data &= ~(1 << 8);
3952 e1000_write_phy_reg(hw, IGP3_VR_CTRL, phy_data);
3954 /* Read it back and test */
3955 e1000_read_phy_reg(hw, IGP3_VR_CTRL, &phy_data);
3956 if (((phy_data & IGP3_VR_CTRL_MODE_MASK) == IGP3_VR_CTRL_MODE_SHUT) || retry)
3959 /* Issue PHY reset and repeat at most one more time */
3960 reg = E1000_READ_REG(hw, CTRL);
3961 E1000_WRITE_REG(hw, CTRL, reg | E1000_CTRL_PHY_RST);
3969 /******************************************************************************
3970 * Work-around for 82566 Kumeran PCS lock loss:
3971 * On link status change (i.e. PCI reset, speed change) and link is up and
3973 * 0) if workaround is optionally disabled do nothing
3974 * 1) wait 1ms for Kumeran link to come up
3975 * 2) check Kumeran Diagnostic register PCS lock loss bit
3976 * 3) if not set the link is locked (all is good), otherwise...
3978 * 5) repeat up to 10 times
3979 * Note: this is only called for IGP3 copper when speed is 1gb.
3981 * hw - struct containing variables accessed by shared code
3982 ******************************************************************************/
3984 e1000_kumeran_lock_loss_workaround(struct e1000_hw *hw)
3991 if (hw->kmrn_lock_loss_workaround_disabled)
3992 return E1000_SUCCESS;
3994 /* Make sure link is up before proceeding. If not just return.
3995 * Attempting this while link is negotiating fouled up link
3997 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
3998 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
4000 if (phy_data & MII_SR_LINK_STATUS) {
4001 for (cnt = 0; cnt < 10; cnt++) {
4002 /* read once to clear */
4003 ret_val = e1000_read_phy_reg(hw, IGP3_KMRN_DIAG, &phy_data);
4006 /* and again to get new status */
4007 ret_val = e1000_read_phy_reg(hw, IGP3_KMRN_DIAG, &phy_data);
4011 /* check for PCS lock */
4012 if (!(phy_data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
4013 return E1000_SUCCESS;
4015 /* Issue PHY reset */
4016 e1000_phy_hw_reset(hw);
4019 /* Disable GigE link negotiation */
4020 reg = E1000_READ_REG(hw, PHY_CTRL);
4021 E1000_WRITE_REG(hw, PHY_CTRL, reg | E1000_PHY_CTRL_GBE_DISABLE |
4022 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
4024 /* unable to acquire PCS lock */
4025 return E1000_ERR_PHY;
4028 return E1000_SUCCESS;
4031 /******************************************************************************
4032 * Probes the expected PHY address for known PHY IDs
4034 * hw - Struct containing variables accessed by shared code
4035 ******************************************************************************/
4037 e1000_detect_gig_phy(struct e1000_hw *hw)
4039 int32_t phy_init_status, ret_val;
4040 uint16_t phy_id_high, phy_id_low;
4041 boolean_t match = FALSE;
4043 DEBUGFUNC("e1000_detect_gig_phy");
4045 if (hw->phy_id != 0)
4046 return E1000_SUCCESS;
4048 /* The 82571 firmware may still be configuring the PHY. In this
4049 * case, we cannot access the PHY until the configuration is done. So
4050 * we explicitly set the PHY values. */
4051 if (hw->mac_type == e1000_82571 ||
4052 hw->mac_type == e1000_82572) {
4053 hw->phy_id = IGP01E1000_I_PHY_ID;
4054 hw->phy_type = e1000_phy_igp_2;
4055 return E1000_SUCCESS;
4058 /* ESB-2 PHY reads require e1000_phy_gg82563 to be set because of a work-
4059 * around that forces PHY page 0 to be set or the reads fail. The rest of
4060 * the code in this routine uses e1000_read_phy_reg to read the PHY ID.
4061 * So for ESB-2 we need to have this set so our reads won't fail. If the
4062 * attached PHY is not a e1000_phy_gg82563, the routines below will figure
4063 * this out as well. */
4064 if (hw->mac_type == e1000_80003es2lan)
4065 hw->phy_type = e1000_phy_gg82563;
4067 /* Read the PHY ID Registers to identify which PHY is onboard. */
4068 ret_val = e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high);
4072 hw->phy_id = (uint32_t) (phy_id_high << 16);
4074 ret_val = e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low);
4078 hw->phy_id |= (uint32_t) (phy_id_low & PHY_REVISION_MASK);
4079 hw->phy_revision = (uint32_t) phy_id_low & ~PHY_REVISION_MASK;
4081 switch (hw->mac_type) {
4083 if (hw->phy_id == M88E1000_E_PHY_ID) match = TRUE;
4086 if (hw->phy_id == M88E1000_I_PHY_ID) match = TRUE;
4090 case e1000_82545_rev_3:
4092 case e1000_82546_rev_3:
4093 if (hw->phy_id == M88E1011_I_PHY_ID) match = TRUE;
4096 case e1000_82541_rev_2:
4098 case e1000_82547_rev_2:
4099 if (hw->phy_id == IGP01E1000_I_PHY_ID) match = TRUE;
4102 if (hw->phy_id == M88E1111_I_PHY_ID) match = TRUE;
4104 case e1000_80003es2lan:
4105 if (hw->phy_id == GG82563_E_PHY_ID) match = TRUE;
4108 if (hw->phy_id == IGP03E1000_E_PHY_ID) match = TRUE;
4109 if (hw->phy_id == IFE_E_PHY_ID) match = TRUE;
4110 if (hw->phy_id == IFE_PLUS_E_PHY_ID) match = TRUE;
4111 if (hw->phy_id == IFE_C_E_PHY_ID) match = TRUE;
4114 DEBUGOUT1("Invalid MAC type %d\n", hw->mac_type);
4115 return -E1000_ERR_CONFIG;
4117 phy_init_status = e1000_set_phy_type(hw);
4119 if ((match) && (phy_init_status == E1000_SUCCESS)) {
4120 DEBUGOUT1("PHY ID 0x%X detected\n", hw->phy_id);
4121 return E1000_SUCCESS;
4123 DEBUGOUT1("Invalid PHY ID 0x%X\n", hw->phy_id);
4124 return -E1000_ERR_PHY;
4127 /******************************************************************************
4128 * Resets the PHY's DSP
4130 * hw - Struct containing variables accessed by shared code
4131 ******************************************************************************/
4133 e1000_phy_reset_dsp(struct e1000_hw *hw)
4136 DEBUGFUNC("e1000_phy_reset_dsp");
4139 if (hw->phy_type != e1000_phy_gg82563) {
4140 ret_val = e1000_write_phy_reg(hw, 29, 0x001d);
4143 ret_val = e1000_write_phy_reg(hw, 30, 0x00c1);
4145 ret_val = e1000_write_phy_reg(hw, 30, 0x0000);
4147 ret_val = E1000_SUCCESS;
4153 /******************************************************************************
4154 * Get PHY information from various PHY registers for igp PHY only.
4156 * hw - Struct containing variables accessed by shared code
4157 * phy_info - PHY information structure
4158 ******************************************************************************/
4160 e1000_phy_igp_get_info(struct e1000_hw *hw,
4161 struct e1000_phy_info *phy_info)
4164 uint16_t phy_data, min_length, max_length, average;
4165 e1000_rev_polarity polarity;
4167 DEBUGFUNC("e1000_phy_igp_get_info");
4169 /* The downshift status is checked only once, after link is established,
4170 * and it stored in the hw->speed_downgraded parameter. */
4171 phy_info->downshift = (e1000_downshift)hw->speed_downgraded;
4173 /* IGP01E1000 does not need to support it. */
4174 phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_normal;
4176 /* IGP01E1000 always correct polarity reversal */
4177 phy_info->polarity_correction = e1000_polarity_reversal_enabled;
4179 /* Check polarity status */
4180 ret_val = e1000_check_polarity(hw, &polarity);
4184 phy_info->cable_polarity = polarity;
4186 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS, &phy_data);
4190 phy_info->mdix_mode = (e1000_auto_x_mode)((phy_data & IGP01E1000_PSSR_MDIX) >>
4191 IGP01E1000_PSSR_MDIX_SHIFT);
4193 if ((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
4194 IGP01E1000_PSSR_SPEED_1000MBPS) {
4195 /* Local/Remote Receiver Information are only valid at 1000 Mbps */
4196 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data);
4200 phy_info->local_rx = ((phy_data & SR_1000T_LOCAL_RX_STATUS) >>
4201 SR_1000T_LOCAL_RX_STATUS_SHIFT) ?
4202 e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
4203 phy_info->remote_rx = ((phy_data & SR_1000T_REMOTE_RX_STATUS) >>
4204 SR_1000T_REMOTE_RX_STATUS_SHIFT) ?
4205 e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
4207 /* Get cable length */
4208 ret_val = e1000_get_cable_length(hw, &min_length, &max_length);
4212 /* Translate to old method */
4213 average = (max_length + min_length) / 2;
4215 if (average <= e1000_igp_cable_length_50)
4216 phy_info->cable_length = e1000_cable_length_50;
4217 else if (average <= e1000_igp_cable_length_80)
4218 phy_info->cable_length = e1000_cable_length_50_80;
4219 else if (average <= e1000_igp_cable_length_110)
4220 phy_info->cable_length = e1000_cable_length_80_110;
4221 else if (average <= e1000_igp_cable_length_140)
4222 phy_info->cable_length = e1000_cable_length_110_140;
4224 phy_info->cable_length = e1000_cable_length_140;
4227 return E1000_SUCCESS;
4230 /******************************************************************************
4231 * Get PHY information from various PHY registers for ife PHY only.
4233 * hw - Struct containing variables accessed by shared code
4234 * phy_info - PHY information structure
4235 ******************************************************************************/
4237 e1000_phy_ife_get_info(struct e1000_hw *hw,
4238 struct e1000_phy_info *phy_info)
4242 e1000_rev_polarity polarity;
4244 DEBUGFUNC("e1000_phy_ife_get_info");
4246 phy_info->downshift = (e1000_downshift)hw->speed_downgraded;
4247 phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_normal;
4249 ret_val = e1000_read_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL, &phy_data);
4252 phy_info->polarity_correction =
4253 ((phy_data & IFE_PSC_AUTO_POLARITY_DISABLE) >>
4254 IFE_PSC_AUTO_POLARITY_DISABLE_SHIFT) ?
4255 e1000_polarity_reversal_disabled : e1000_polarity_reversal_enabled;
4257 if (phy_info->polarity_correction == e1000_polarity_reversal_enabled) {
4258 ret_val = e1000_check_polarity(hw, &polarity);
4262 /* Polarity is forced. */
4263 polarity = ((phy_data & IFE_PSC_FORCE_POLARITY) >>
4264 IFE_PSC_FORCE_POLARITY_SHIFT) ?
4265 e1000_rev_polarity_reversed : e1000_rev_polarity_normal;
4267 phy_info->cable_polarity = polarity;
4269 ret_val = e1000_read_phy_reg(hw, IFE_PHY_MDIX_CONTROL, &phy_data);
4273 phy_info->mdix_mode = (e1000_auto_x_mode)
4274 ((phy_data & (IFE_PMC_AUTO_MDIX | IFE_PMC_FORCE_MDIX)) >>
4275 IFE_PMC_MDIX_MODE_SHIFT);
4277 return E1000_SUCCESS;
4280 /******************************************************************************
4281 * Get PHY information from various PHY registers fot m88 PHY only.
4283 * hw - Struct containing variables accessed by shared code
4284 * phy_info - PHY information structure
4285 ******************************************************************************/
4287 e1000_phy_m88_get_info(struct e1000_hw *hw,
4288 struct e1000_phy_info *phy_info)
4292 e1000_rev_polarity polarity;
4294 DEBUGFUNC("e1000_phy_m88_get_info");
4296 /* The downshift status is checked only once, after link is established,
4297 * and it stored in the hw->speed_downgraded parameter. */
4298 phy_info->downshift = (e1000_downshift)hw->speed_downgraded;
4300 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
4304 phy_info->extended_10bt_distance =
4305 ((phy_data & M88E1000_PSCR_10BT_EXT_DIST_ENABLE) >>
4306 M88E1000_PSCR_10BT_EXT_DIST_ENABLE_SHIFT) ?
4307 e1000_10bt_ext_dist_enable_lower : e1000_10bt_ext_dist_enable_normal;
4309 phy_info->polarity_correction =
4310 ((phy_data & M88E1000_PSCR_POLARITY_REVERSAL) >>
4311 M88E1000_PSCR_POLARITY_REVERSAL_SHIFT) ?
4312 e1000_polarity_reversal_disabled : e1000_polarity_reversal_enabled;
4314 /* Check polarity status */
4315 ret_val = e1000_check_polarity(hw, &polarity);
4318 phy_info->cable_polarity = polarity;
4320 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
4324 phy_info->mdix_mode = (e1000_auto_x_mode)((phy_data & M88E1000_PSSR_MDIX) >>
4325 M88E1000_PSSR_MDIX_SHIFT);
4327 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) {
4328 /* Cable Length Estimation and Local/Remote Receiver Information
4329 * are only valid at 1000 Mbps.
4331 if (hw->phy_type != e1000_phy_gg82563) {
4332 phy_info->cable_length = (e1000_cable_length)((phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
4333 M88E1000_PSSR_CABLE_LENGTH_SHIFT);
4335 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_DSP_DISTANCE,
4340 phy_info->cable_length = (e1000_cable_length)(phy_data & GG82563_DSPD_CABLE_LENGTH);
4343 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data);
4347 phy_info->local_rx = ((phy_data & SR_1000T_LOCAL_RX_STATUS) >>
4348 SR_1000T_LOCAL_RX_STATUS_SHIFT) ?
4349 e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
4350 phy_info->remote_rx = ((phy_data & SR_1000T_REMOTE_RX_STATUS) >>
4351 SR_1000T_REMOTE_RX_STATUS_SHIFT) ?
4352 e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
4356 return E1000_SUCCESS;
4359 /******************************************************************************
4360 * Get PHY information from various PHY registers
4362 * hw - Struct containing variables accessed by shared code
4363 * phy_info - PHY information structure
4364 ******************************************************************************/
4366 e1000_phy_get_info(struct e1000_hw *hw,
4367 struct e1000_phy_info *phy_info)
4372 DEBUGFUNC("e1000_phy_get_info");
4374 phy_info->cable_length = e1000_cable_length_undefined;
4375 phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_undefined;
4376 phy_info->cable_polarity = e1000_rev_polarity_undefined;
4377 phy_info->downshift = e1000_downshift_undefined;
4378 phy_info->polarity_correction = e1000_polarity_reversal_undefined;
4379 phy_info->mdix_mode = e1000_auto_x_mode_undefined;
4380 phy_info->local_rx = e1000_1000t_rx_status_undefined;
4381 phy_info->remote_rx = e1000_1000t_rx_status_undefined;
4383 if (hw->media_type != e1000_media_type_copper) {
4384 DEBUGOUT("PHY info is only valid for copper media\n");
4385 return -E1000_ERR_CONFIG;
4388 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
4392 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
4396 if ((phy_data & MII_SR_LINK_STATUS) != MII_SR_LINK_STATUS) {
4397 DEBUGOUT("PHY info is only valid if link is up\n");
4398 return -E1000_ERR_CONFIG;
4401 if (hw->phy_type == e1000_phy_igp ||
4402 hw->phy_type == e1000_phy_igp_3 ||
4403 hw->phy_type == e1000_phy_igp_2)
4404 return e1000_phy_igp_get_info(hw, phy_info);
4405 else if (hw->phy_type == e1000_phy_ife)
4406 return e1000_phy_ife_get_info(hw, phy_info);
4408 return e1000_phy_m88_get_info(hw, phy_info);
4412 e1000_validate_mdi_setting(struct e1000_hw *hw)
4414 DEBUGFUNC("e1000_validate_mdi_settings");
4416 if (!hw->autoneg && (hw->mdix == 0 || hw->mdix == 3)) {
4417 DEBUGOUT("Invalid MDI setting detected\n");
4419 return -E1000_ERR_CONFIG;
4421 return E1000_SUCCESS;
4425 /******************************************************************************
4426 * Sets up eeprom variables in the hw struct. Must be called after mac_type
4427 * is configured. Additionally, if this is ICH8, the flash controller GbE
4428 * registers must be mapped, or this will crash.
4430 * hw - Struct containing variables accessed by shared code
4431 *****************************************************************************/
4433 e1000_init_eeprom_params(struct e1000_hw *hw)
4435 struct e1000_eeprom_info *eeprom = &hw->eeprom;
4436 uint32_t eecd = E1000_READ_REG(hw, EECD);
4437 int32_t ret_val = E1000_SUCCESS;
4438 uint16_t eeprom_size;
4440 DEBUGFUNC("e1000_init_eeprom_params");
4442 switch (hw->mac_type) {
4443 case e1000_82542_rev2_0:
4444 case e1000_82542_rev2_1:
4447 eeprom->type = e1000_eeprom_microwire;
4448 eeprom->word_size = 64;
4449 eeprom->opcode_bits = 3;
4450 eeprom->address_bits = 6;
4451 eeprom->delay_usec = 50;
4452 eeprom->use_eerd = FALSE;
4453 eeprom->use_eewr = FALSE;
4457 case e1000_82545_rev_3:
4459 case e1000_82546_rev_3:
4460 eeprom->type = e1000_eeprom_microwire;
4461 eeprom->opcode_bits = 3;
4462 eeprom->delay_usec = 50;
4463 if (eecd & E1000_EECD_SIZE) {
4464 eeprom->word_size = 256;
4465 eeprom->address_bits = 8;
4467 eeprom->word_size = 64;
4468 eeprom->address_bits = 6;
4470 eeprom->use_eerd = FALSE;
4471 eeprom->use_eewr = FALSE;
4474 case e1000_82541_rev_2:
4476 case e1000_82547_rev_2:
4477 if (eecd & E1000_EECD_TYPE) {
4478 eeprom->type = e1000_eeprom_spi;
4479 eeprom->opcode_bits = 8;
4480 eeprom->delay_usec = 1;
4481 if (eecd & E1000_EECD_ADDR_BITS) {
4482 eeprom->page_size = 32;
4483 eeprom->address_bits = 16;
4485 eeprom->page_size = 8;
4486 eeprom->address_bits = 8;
4489 eeprom->type = e1000_eeprom_microwire;
4490 eeprom->opcode_bits = 3;
4491 eeprom->delay_usec = 50;
4492 if (eecd & E1000_EECD_ADDR_BITS) {
4493 eeprom->word_size = 256;
4494 eeprom->address_bits = 8;
4496 eeprom->word_size = 64;
4497 eeprom->address_bits = 6;
4500 eeprom->use_eerd = FALSE;
4501 eeprom->use_eewr = FALSE;
4505 eeprom->type = e1000_eeprom_spi;
4506 eeprom->opcode_bits = 8;
4507 eeprom->delay_usec = 1;
4508 if (eecd & E1000_EECD_ADDR_BITS) {
4509 eeprom->page_size = 32;
4510 eeprom->address_bits = 16;
4512 eeprom->page_size = 8;
4513 eeprom->address_bits = 8;
4515 eeprom->use_eerd = FALSE;
4516 eeprom->use_eewr = FALSE;
4519 eeprom->type = e1000_eeprom_spi;
4520 eeprom->opcode_bits = 8;
4521 eeprom->delay_usec = 1;
4522 if (eecd & E1000_EECD_ADDR_BITS) {
4523 eeprom->page_size = 32;
4524 eeprom->address_bits = 16;
4526 eeprom->page_size = 8;
4527 eeprom->address_bits = 8;
4529 eeprom->use_eerd = TRUE;
4530 eeprom->use_eewr = TRUE;
4531 if (e1000_is_onboard_nvm_eeprom(hw) == FALSE) {
4532 eeprom->type = e1000_eeprom_flash;
4533 eeprom->word_size = 2048;
4535 /* Ensure that the Autonomous FLASH update bit is cleared due to
4536 * Flash update issue on parts which use a FLASH for NVM. */
4537 eecd &= ~E1000_EECD_AUPDEN;
4538 E1000_WRITE_REG(hw, EECD, eecd);
4541 case e1000_80003es2lan:
4542 eeprom->type = e1000_eeprom_spi;
4543 eeprom->opcode_bits = 8;
4544 eeprom->delay_usec = 1;
4545 if (eecd & E1000_EECD_ADDR_BITS) {
4546 eeprom->page_size = 32;
4547 eeprom->address_bits = 16;
4549 eeprom->page_size = 8;
4550 eeprom->address_bits = 8;
4552 eeprom->use_eerd = TRUE;
4553 eeprom->use_eewr = FALSE;
4558 uint32_t flash_size = E1000_READ_ICH_FLASH_REG(hw, ICH_FLASH_GFPREG);
4560 eeprom->type = e1000_eeprom_ich8;
4561 eeprom->use_eerd = FALSE;
4562 eeprom->use_eewr = FALSE;
4563 eeprom->word_size = E1000_SHADOW_RAM_WORDS;
4565 /* Zero the shadow RAM structure. But don't load it from NVM
4566 * so as to save time for driver init */
4567 if (hw->eeprom_shadow_ram != NULL) {
4568 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
4569 hw->eeprom_shadow_ram[i].modified = FALSE;
4570 hw->eeprom_shadow_ram[i].eeprom_word = 0xFFFF;
4574 hw->flash_base_addr = (flash_size & ICH_GFPREG_BASE_MASK) *
4575 ICH_FLASH_SECTOR_SIZE;
4577 hw->flash_bank_size = ((flash_size >> 16) & ICH_GFPREG_BASE_MASK) + 1;
4578 hw->flash_bank_size -= (flash_size & ICH_GFPREG_BASE_MASK);
4580 hw->flash_bank_size *= ICH_FLASH_SECTOR_SIZE;
4582 hw->flash_bank_size /= 2 * sizeof(uint16_t);
4590 if (eeprom->type == e1000_eeprom_spi) {
4591 /* eeprom_size will be an enum [0..8] that maps to eeprom sizes 128B to
4592 * 32KB (incremented by powers of 2).
4594 if (hw->mac_type <= e1000_82547_rev_2) {
4595 /* Set to default value for initial eeprom read. */
4596 eeprom->word_size = 64;
4597 ret_val = e1000_read_eeprom(hw, EEPROM_CFG, 1, &eeprom_size);
4600 eeprom_size = (eeprom_size & EEPROM_SIZE_MASK) >> EEPROM_SIZE_SHIFT;
4601 /* 256B eeprom size was not supported in earlier hardware, so we
4602 * bump eeprom_size up one to ensure that "1" (which maps to 256B)
4603 * is never the result used in the shifting logic below. */
4607 eeprom_size = (uint16_t)((eecd & E1000_EECD_SIZE_EX_MASK) >>
4608 E1000_EECD_SIZE_EX_SHIFT);
4611 eeprom->word_size = 1 << (eeprom_size + EEPROM_WORD_SIZE_SHIFT);
4616 /******************************************************************************
4617 * Raises the EEPROM's clock input.
4619 * hw - Struct containing variables accessed by shared code
4620 * eecd - EECD's current value
4621 *****************************************************************************/
4623 e1000_raise_ee_clk(struct e1000_hw *hw,
4626 /* Raise the clock input to the EEPROM (by setting the SK bit), and then
4627 * wait <delay> microseconds.
4629 *eecd = *eecd | E1000_EECD_SK;
4630 E1000_WRITE_REG(hw, EECD, *eecd);
4631 E1000_WRITE_FLUSH(hw);
4632 udelay(hw->eeprom.delay_usec);
4635 /******************************************************************************
4636 * Lowers the EEPROM's clock input.
4638 * hw - Struct containing variables accessed by shared code
4639 * eecd - EECD's current value
4640 *****************************************************************************/
4642 e1000_lower_ee_clk(struct e1000_hw *hw,
4645 /* Lower the clock input to the EEPROM (by clearing the SK bit), and then
4646 * wait 50 microseconds.
4648 *eecd = *eecd & ~E1000_EECD_SK;
4649 E1000_WRITE_REG(hw, EECD, *eecd);
4650 E1000_WRITE_FLUSH(hw);
4651 udelay(hw->eeprom.delay_usec);
4654 /******************************************************************************
4655 * Shift data bits out to the EEPROM.
4657 * hw - Struct containing variables accessed by shared code
4658 * data - data to send to the EEPROM
4659 * count - number of bits to shift out
4660 *****************************************************************************/
4662 e1000_shift_out_ee_bits(struct e1000_hw *hw,
4666 struct e1000_eeprom_info *eeprom = &hw->eeprom;
4670 /* We need to shift "count" bits out to the EEPROM. So, value in the
4671 * "data" parameter will be shifted out to the EEPROM one bit at a time.
4672 * In order to do this, "data" must be broken down into bits.
4674 mask = 0x01 << (count - 1);
4675 eecd = E1000_READ_REG(hw, EECD);
4676 if (eeprom->type == e1000_eeprom_microwire) {
4677 eecd &= ~E1000_EECD_DO;
4678 } else if (eeprom->type == e1000_eeprom_spi) {
4679 eecd |= E1000_EECD_DO;
4682 /* A "1" is shifted out to the EEPROM by setting bit "DI" to a "1",
4683 * and then raising and then lowering the clock (the SK bit controls
4684 * the clock input to the EEPROM). A "0" is shifted out to the EEPROM
4685 * by setting "DI" to "0" and then raising and then lowering the clock.
4687 eecd &= ~E1000_EECD_DI;
4690 eecd |= E1000_EECD_DI;
4692 E1000_WRITE_REG(hw, EECD, eecd);
4693 E1000_WRITE_FLUSH(hw);
4695 udelay(eeprom->delay_usec);
4697 e1000_raise_ee_clk(hw, &eecd);
4698 e1000_lower_ee_clk(hw, &eecd);
4704 /* We leave the "DI" bit set to "0" when we leave this routine. */
4705 eecd &= ~E1000_EECD_DI;
4706 E1000_WRITE_REG(hw, EECD, eecd);
4709 /******************************************************************************
4710 * Shift data bits in from the EEPROM
4712 * hw - Struct containing variables accessed by shared code
4713 *****************************************************************************/
4715 e1000_shift_in_ee_bits(struct e1000_hw *hw,
4722 /* In order to read a register from the EEPROM, we need to shift 'count'
4723 * bits in from the EEPROM. Bits are "shifted in" by raising the clock
4724 * input to the EEPROM (setting the SK bit), and then reading the value of
4725 * the "DO" bit. During this "shifting in" process the "DI" bit should
4729 eecd = E1000_READ_REG(hw, EECD);
4731 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
4734 for (i = 0; i < count; i++) {
4736 e1000_raise_ee_clk(hw, &eecd);
4738 eecd = E1000_READ_REG(hw, EECD);
4740 eecd &= ~(E1000_EECD_DI);
4741 if (eecd & E1000_EECD_DO)
4744 e1000_lower_ee_clk(hw, &eecd);
4750 /******************************************************************************
4751 * Prepares EEPROM for access
4753 * hw - Struct containing variables accessed by shared code
4755 * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This
4756 * function should be called before issuing a command to the EEPROM.
4757 *****************************************************************************/
4759 e1000_acquire_eeprom(struct e1000_hw *hw)
4761 struct e1000_eeprom_info *eeprom = &hw->eeprom;
4764 DEBUGFUNC("e1000_acquire_eeprom");
4766 if (e1000_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM))
4767 return -E1000_ERR_SWFW_SYNC;
4768 eecd = E1000_READ_REG(hw, EECD);
4770 if (hw->mac_type != e1000_82573) {
4771 /* Request EEPROM Access */
4772 if (hw->mac_type > e1000_82544) {
4773 eecd |= E1000_EECD_REQ;
4774 E1000_WRITE_REG(hw, EECD, eecd);
4775 eecd = E1000_READ_REG(hw, EECD);
4776 while ((!(eecd & E1000_EECD_GNT)) &&
4777 (i < E1000_EEPROM_GRANT_ATTEMPTS)) {
4780 eecd = E1000_READ_REG(hw, EECD);
4782 if (!(eecd & E1000_EECD_GNT)) {
4783 eecd &= ~E1000_EECD_REQ;
4784 E1000_WRITE_REG(hw, EECD, eecd);
4785 DEBUGOUT("Could not acquire EEPROM grant\n");
4786 e1000_swfw_sync_release(hw, E1000_SWFW_EEP_SM);
4787 return -E1000_ERR_EEPROM;
4792 /* Setup EEPROM for Read/Write */
4794 if (eeprom->type == e1000_eeprom_microwire) {
4795 /* Clear SK and DI */
4796 eecd &= ~(E1000_EECD_DI | E1000_EECD_SK);
4797 E1000_WRITE_REG(hw, EECD, eecd);
4800 eecd |= E1000_EECD_CS;
4801 E1000_WRITE_REG(hw, EECD, eecd);
4802 } else if (eeprom->type == e1000_eeprom_spi) {
4803 /* Clear SK and CS */
4804 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
4805 E1000_WRITE_REG(hw, EECD, eecd);
4809 return E1000_SUCCESS;
4812 /******************************************************************************
4813 * Returns EEPROM to a "standby" state
4815 * hw - Struct containing variables accessed by shared code
4816 *****************************************************************************/
4818 e1000_standby_eeprom(struct e1000_hw *hw)
4820 struct e1000_eeprom_info *eeprom = &hw->eeprom;
4823 eecd = E1000_READ_REG(hw, EECD);
4825 if (eeprom->type == e1000_eeprom_microwire) {
4826 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
4827 E1000_WRITE_REG(hw, EECD, eecd);
4828 E1000_WRITE_FLUSH(hw);
4829 udelay(eeprom->delay_usec);
4832 eecd |= E1000_EECD_SK;
4833 E1000_WRITE_REG(hw, EECD, eecd);
4834 E1000_WRITE_FLUSH(hw);
4835 udelay(eeprom->delay_usec);
4838 eecd |= E1000_EECD_CS;
4839 E1000_WRITE_REG(hw, EECD, eecd);
4840 E1000_WRITE_FLUSH(hw);
4841 udelay(eeprom->delay_usec);
4844 eecd &= ~E1000_EECD_SK;
4845 E1000_WRITE_REG(hw, EECD, eecd);
4846 E1000_WRITE_FLUSH(hw);
4847 udelay(eeprom->delay_usec);
4848 } else if (eeprom->type == e1000_eeprom_spi) {
4849 /* Toggle CS to flush commands */
4850 eecd |= E1000_EECD_CS;
4851 E1000_WRITE_REG(hw, EECD, eecd);
4852 E1000_WRITE_FLUSH(hw);
4853 udelay(eeprom->delay_usec);
4854 eecd &= ~E1000_EECD_CS;
4855 E1000_WRITE_REG(hw, EECD, eecd);
4856 E1000_WRITE_FLUSH(hw);
4857 udelay(eeprom->delay_usec);
4861 /******************************************************************************
4862 * Terminates a command by inverting the EEPROM's chip select pin
4864 * hw - Struct containing variables accessed by shared code
4865 *****************************************************************************/
4867 e1000_release_eeprom(struct e1000_hw *hw)
4871 DEBUGFUNC("e1000_release_eeprom");
4873 eecd = E1000_READ_REG(hw, EECD);
4875 if (hw->eeprom.type == e1000_eeprom_spi) {
4876 eecd |= E1000_EECD_CS; /* Pull CS high */
4877 eecd &= ~E1000_EECD_SK; /* Lower SCK */
4879 E1000_WRITE_REG(hw, EECD, eecd);
4881 udelay(hw->eeprom.delay_usec);
4882 } else if (hw->eeprom.type == e1000_eeprom_microwire) {
4883 /* cleanup eeprom */
4885 /* CS on Microwire is active-high */
4886 eecd &= ~(E1000_EECD_CS | E1000_EECD_DI);
4888 E1000_WRITE_REG(hw, EECD, eecd);
4890 /* Rising edge of clock */
4891 eecd |= E1000_EECD_SK;
4892 E1000_WRITE_REG(hw, EECD, eecd);
4893 E1000_WRITE_FLUSH(hw);
4894 udelay(hw->eeprom.delay_usec);
4896 /* Falling edge of clock */
4897 eecd &= ~E1000_EECD_SK;
4898 E1000_WRITE_REG(hw, EECD, eecd);
4899 E1000_WRITE_FLUSH(hw);
4900 udelay(hw->eeprom.delay_usec);
4903 /* Stop requesting EEPROM access */
4904 if (hw->mac_type > e1000_82544) {
4905 eecd &= ~E1000_EECD_REQ;
4906 E1000_WRITE_REG(hw, EECD, eecd);
4909 e1000_swfw_sync_release(hw, E1000_SWFW_EEP_SM);
4912 /******************************************************************************
4913 * Reads a 16 bit word from the EEPROM.
4915 * hw - Struct containing variables accessed by shared code
4916 *****************************************************************************/
4918 e1000_spi_eeprom_ready(struct e1000_hw *hw)
4920 uint16_t retry_count = 0;
4921 uint8_t spi_stat_reg;
4923 DEBUGFUNC("e1000_spi_eeprom_ready");
4925 /* Read "Status Register" repeatedly until the LSB is cleared. The
4926 * EEPROM will signal that the command has been completed by clearing
4927 * bit 0 of the internal status register. If it's not cleared within
4928 * 5 milliseconds, then error out.
4932 e1000_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI,
4933 hw->eeprom.opcode_bits);
4934 spi_stat_reg = (uint8_t)e1000_shift_in_ee_bits(hw, 8);
4935 if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI))
4941 e1000_standby_eeprom(hw);
4942 } while (retry_count < EEPROM_MAX_RETRY_SPI);
4944 /* ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and
4945 * only 0-5mSec on 5V devices)
4947 if (retry_count >= EEPROM_MAX_RETRY_SPI) {
4948 DEBUGOUT("SPI EEPROM Status error\n");
4949 return -E1000_ERR_EEPROM;
4952 return E1000_SUCCESS;
4955 /******************************************************************************
4956 * Reads a 16 bit word from the EEPROM.
4958 * hw - Struct containing variables accessed by shared code
4959 * offset - offset of word in the EEPROM to read
4960 * data - word read from the EEPROM
4961 * words - number of words to read
4962 *****************************************************************************/
4964 e1000_read_eeprom(struct e1000_hw *hw,
4969 struct e1000_eeprom_info *eeprom = &hw->eeprom;
4972 DEBUGFUNC("e1000_read_eeprom");
4974 /* If eeprom is not yet detected, do so now */
4975 if (eeprom->word_size == 0)
4976 e1000_init_eeprom_params(hw);
4978 /* A check for invalid values: offset too large, too many words, and not
4981 if ((offset >= eeprom->word_size) || (words > eeprom->word_size - offset) ||
4983 DEBUGOUT2("\"words\" parameter out of bounds. Words = %d, size = %d\n", offset, eeprom->word_size);
4984 return -E1000_ERR_EEPROM;
4987 /* EEPROM's that don't use EERD to read require us to bit-bang the SPI
4988 * directly. In this case, we need to acquire the EEPROM so that
4989 * FW or other port software does not interrupt.
4991 if (e1000_is_onboard_nvm_eeprom(hw) == TRUE &&
4992 hw->eeprom.use_eerd == FALSE) {
4993 /* Prepare the EEPROM for bit-bang reading */
4994 if (e1000_acquire_eeprom(hw) != E1000_SUCCESS)
4995 return -E1000_ERR_EEPROM;
4998 /* Eerd register EEPROM access requires no eeprom aquire/release */
4999 if (eeprom->use_eerd == TRUE)
5000 return e1000_read_eeprom_eerd(hw, offset, words, data);
5002 /* ICH EEPROM access is done via the ICH flash controller */
5003 if (eeprom->type == e1000_eeprom_ich8)
5004 return e1000_read_eeprom_ich8(hw, offset, words, data);
5006 /* Set up the SPI or Microwire EEPROM for bit-bang reading. We have
5007 * acquired the EEPROM at this point, so any returns should relase it */
5008 if (eeprom->type == e1000_eeprom_spi) {
5010 uint8_t read_opcode = EEPROM_READ_OPCODE_SPI;
5012 if (e1000_spi_eeprom_ready(hw)) {
5013 e1000_release_eeprom(hw);
5014 return -E1000_ERR_EEPROM;
5017 e1000_standby_eeprom(hw);
5019 /* Some SPI eeproms use the 8th address bit embedded in the opcode */
5020 if ((eeprom->address_bits == 8) && (offset >= 128))
5021 read_opcode |= EEPROM_A8_OPCODE_SPI;
5023 /* Send the READ command (opcode + addr) */
5024 e1000_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits);
5025 e1000_shift_out_ee_bits(hw, (uint16_t)(offset*2), eeprom->address_bits);
5027 /* Read the data. The address of the eeprom internally increments with
5028 * each byte (spi) being read, saving on the overhead of eeprom setup
5029 * and tear-down. The address counter will roll over if reading beyond
5030 * the size of the eeprom, thus allowing the entire memory to be read
5031 * starting from any offset. */
5032 for (i = 0; i < words; i++) {
5033 word_in = e1000_shift_in_ee_bits(hw, 16);
5034 data[i] = (word_in >> 8) | (word_in << 8);
5036 } else if (eeprom->type == e1000_eeprom_microwire) {
5037 for (i = 0; i < words; i++) {
5038 /* Send the READ command (opcode + addr) */
5039 e1000_shift_out_ee_bits(hw, EEPROM_READ_OPCODE_MICROWIRE,
5040 eeprom->opcode_bits);
5041 e1000_shift_out_ee_bits(hw, (uint16_t)(offset + i),
5042 eeprom->address_bits);
5044 /* Read the data. For microwire, each word requires the overhead
5045 * of eeprom setup and tear-down. */
5046 data[i] = e1000_shift_in_ee_bits(hw, 16);
5047 e1000_standby_eeprom(hw);
5051 /* End this read operation */
5052 e1000_release_eeprom(hw);
5054 return E1000_SUCCESS;
5057 /******************************************************************************
5058 * Reads a 16 bit word from the EEPROM using the EERD register.
5060 * hw - Struct containing variables accessed by shared code
5061 * offset - offset of word in the EEPROM to read
5062 * data - word read from the EEPROM
5063 * words - number of words to read
5064 *****************************************************************************/
5066 e1000_read_eeprom_eerd(struct e1000_hw *hw,
5071 uint32_t i, eerd = 0;
5074 for (i = 0; i < words; i++) {
5075 eerd = ((offset+i) << E1000_EEPROM_RW_ADDR_SHIFT) +
5076 E1000_EEPROM_RW_REG_START;
5078 E1000_WRITE_REG(hw, EERD, eerd);
5079 error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_READ);
5084 data[i] = (E1000_READ_REG(hw, EERD) >> E1000_EEPROM_RW_REG_DATA);
5091 /******************************************************************************
5092 * Writes a 16 bit word from the EEPROM using the EEWR register.
5094 * hw - Struct containing variables accessed by shared code
5095 * offset - offset of word in the EEPROM to read
5096 * data - word read from the EEPROM
5097 * words - number of words to read
5098 *****************************************************************************/
5100 e1000_write_eeprom_eewr(struct e1000_hw *hw,
5105 uint32_t register_value = 0;
5109 if (e1000_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM))
5110 return -E1000_ERR_SWFW_SYNC;
5112 for (i = 0; i < words; i++) {
5113 register_value = (data[i] << E1000_EEPROM_RW_REG_DATA) |
5114 ((offset+i) << E1000_EEPROM_RW_ADDR_SHIFT) |
5115 E1000_EEPROM_RW_REG_START;
5117 error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_WRITE);
5122 E1000_WRITE_REG(hw, EEWR, register_value);
5124 error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_WRITE);
5131 e1000_swfw_sync_release(hw, E1000_SWFW_EEP_SM);
5135 /******************************************************************************
5136 * Polls the status bit (bit 1) of the EERD to determine when the read is done.
5138 * hw - Struct containing variables accessed by shared code
5139 *****************************************************************************/
5141 e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd)
5143 uint32_t attempts = 100000;
5144 uint32_t i, reg = 0;
5145 int32_t done = E1000_ERR_EEPROM;
5147 for (i = 0; i < attempts; i++) {
5148 if (eerd == E1000_EEPROM_POLL_READ)
5149 reg = E1000_READ_REG(hw, EERD);
5151 reg = E1000_READ_REG(hw, EEWR);
5153 if (reg & E1000_EEPROM_RW_REG_DONE) {
5154 done = E1000_SUCCESS;
5163 /***************************************************************************
5164 * Description: Determines if the onboard NVM is FLASH or EEPROM.
5166 * hw - Struct containing variables accessed by shared code
5167 ****************************************************************************/
5169 e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw)
5173 DEBUGFUNC("e1000_is_onboard_nvm_eeprom");
5175 if (hw->mac_type == e1000_ich8lan)
5178 if (hw->mac_type == e1000_82573) {
5179 eecd = E1000_READ_REG(hw, EECD);
5181 /* Isolate bits 15 & 16 */
5182 eecd = ((eecd >> 15) & 0x03);
5184 /* If both bits are set, device is Flash type */
5192 /******************************************************************************
5193 * Verifies that the EEPROM has a valid checksum
5195 * hw - Struct containing variables accessed by shared code
5197 * Reads the first 64 16 bit words of the EEPROM and sums the values read.
5198 * If the the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is
5200 *****************************************************************************/
5202 e1000_validate_eeprom_checksum(struct e1000_hw *hw)
5204 uint16_t checksum = 0;
5205 uint16_t i, eeprom_data;
5207 DEBUGFUNC("e1000_validate_eeprom_checksum");
5209 if ((hw->mac_type == e1000_82573) &&
5210 (e1000_is_onboard_nvm_eeprom(hw) == FALSE)) {
5211 /* Check bit 4 of word 10h. If it is 0, firmware is done updating
5212 * 10h-12h. Checksum may need to be fixed. */
5213 e1000_read_eeprom(hw, 0x10, 1, &eeprom_data);
5214 if ((eeprom_data & 0x10) == 0) {
5215 /* Read 0x23 and check bit 15. This bit is a 1 when the checksum
5216 * has already been fixed. If the checksum is still wrong and this
5217 * bit is a 1, we need to return bad checksum. Otherwise, we need
5218 * to set this bit to a 1 and update the checksum. */
5219 e1000_read_eeprom(hw, 0x23, 1, &eeprom_data);
5220 if ((eeprom_data & 0x8000) == 0) {
5221 eeprom_data |= 0x8000;
5222 e1000_write_eeprom(hw, 0x23, 1, &eeprom_data);
5223 e1000_update_eeprom_checksum(hw);
5228 if (hw->mac_type == e1000_ich8lan) {
5229 /* Drivers must allocate the shadow ram structure for the
5230 * EEPROM checksum to be updated. Otherwise, this bit as well
5231 * as the checksum must both be set correctly for this
5232 * validation to pass.
5234 e1000_read_eeprom(hw, 0x19, 1, &eeprom_data);
5235 if ((eeprom_data & 0x40) == 0) {
5236 eeprom_data |= 0x40;
5237 e1000_write_eeprom(hw, 0x19, 1, &eeprom_data);
5238 e1000_update_eeprom_checksum(hw);
5242 for (i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++) {
5243 if (e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) {
5244 DEBUGOUT("EEPROM Read Error\n");
5245 return -E1000_ERR_EEPROM;
5247 checksum += eeprom_data;
5250 if (checksum == (uint16_t) EEPROM_SUM)
5251 return E1000_SUCCESS;
5253 DEBUGOUT("EEPROM Checksum Invalid\n");
5254 return -E1000_ERR_EEPROM;
5258 /******************************************************************************
5259 * Calculates the EEPROM checksum and writes it to the EEPROM
5261 * hw - Struct containing variables accessed by shared code
5263 * Sums the first 63 16 bit words of the EEPROM. Subtracts the sum from 0xBABA.
5264 * Writes the difference to word offset 63 of the EEPROM.
5265 *****************************************************************************/
5267 e1000_update_eeprom_checksum(struct e1000_hw *hw)
5270 uint16_t checksum = 0;
5271 uint16_t i, eeprom_data;
5273 DEBUGFUNC("e1000_update_eeprom_checksum");
5275 for (i = 0; i < EEPROM_CHECKSUM_REG; i++) {
5276 if (e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) {
5277 DEBUGOUT("EEPROM Read Error\n");
5278 return -E1000_ERR_EEPROM;
5280 checksum += eeprom_data;
5282 checksum = (uint16_t) EEPROM_SUM - checksum;
5283 if (e1000_write_eeprom(hw, EEPROM_CHECKSUM_REG, 1, &checksum) < 0) {
5284 DEBUGOUT("EEPROM Write Error\n");
5285 return -E1000_ERR_EEPROM;
5286 } else if (hw->eeprom.type == e1000_eeprom_flash) {
5287 e1000_commit_shadow_ram(hw);
5288 } else if (hw->eeprom.type == e1000_eeprom_ich8) {
5289 e1000_commit_shadow_ram(hw);
5290 /* Reload the EEPROM, or else modifications will not appear
5291 * until after next adapter reset. */
5292 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
5293 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
5294 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
5297 return E1000_SUCCESS;
5300 /******************************************************************************
5301 * Parent function for writing words to the different EEPROM types.
5303 * hw - Struct containing variables accessed by shared code
5304 * offset - offset within the EEPROM to be written to
5305 * words - number of words to write
5306 * data - 16 bit word to be written to the EEPROM
5308 * If e1000_update_eeprom_checksum is not called after this function, the
5309 * EEPROM will most likely contain an invalid checksum.
5310 *****************************************************************************/
5312 e1000_write_eeprom(struct e1000_hw *hw,
5317 struct e1000_eeprom_info *eeprom = &hw->eeprom;
5320 DEBUGFUNC("e1000_write_eeprom");
5322 /* If eeprom is not yet detected, do so now */
5323 if (eeprom->word_size == 0)
5324 e1000_init_eeprom_params(hw);
5326 /* A check for invalid values: offset too large, too many words, and not
5329 if ((offset >= eeprom->word_size) || (words > eeprom->word_size - offset) ||
5331 DEBUGOUT("\"words\" parameter out of bounds\n");
5332 return -E1000_ERR_EEPROM;
5335 /* 82573 writes only through eewr */
5336 if (eeprom->use_eewr == TRUE)
5337 return e1000_write_eeprom_eewr(hw, offset, words, data);
5339 if (eeprom->type == e1000_eeprom_ich8)
5340 return e1000_write_eeprom_ich8(hw, offset, words, data);
5342 /* Prepare the EEPROM for writing */
5343 if (e1000_acquire_eeprom(hw) != E1000_SUCCESS)
5344 return -E1000_ERR_EEPROM;
5346 if (eeprom->type == e1000_eeprom_microwire) {
5347 status = e1000_write_eeprom_microwire(hw, offset, words, data);
5349 status = e1000_write_eeprom_spi(hw, offset, words, data);
5353 /* Done with writing */
5354 e1000_release_eeprom(hw);
5359 /******************************************************************************
5360 * Writes a 16 bit word to a given offset in an SPI EEPROM.
5362 * hw - Struct containing variables accessed by shared code
5363 * offset - offset within the EEPROM to be written to
5364 * words - number of words to write
5365 * data - pointer to array of 8 bit words to be written to the EEPROM
5367 *****************************************************************************/
5369 e1000_write_eeprom_spi(struct e1000_hw *hw,
5374 struct e1000_eeprom_info *eeprom = &hw->eeprom;
5377 DEBUGFUNC("e1000_write_eeprom_spi");
5379 while (widx < words) {
5380 uint8_t write_opcode = EEPROM_WRITE_OPCODE_SPI;
5382 if (e1000_spi_eeprom_ready(hw)) return -E1000_ERR_EEPROM;
5384 e1000_standby_eeprom(hw);
5386 /* Send the WRITE ENABLE command (8 bit opcode ) */
5387 e1000_shift_out_ee_bits(hw, EEPROM_WREN_OPCODE_SPI,
5388 eeprom->opcode_bits);
5390 e1000_standby_eeprom(hw);
5392 /* Some SPI eeproms use the 8th address bit embedded in the opcode */
5393 if ((eeprom->address_bits == 8) && (offset >= 128))
5394 write_opcode |= EEPROM_A8_OPCODE_SPI;
5396 /* Send the Write command (8-bit opcode + addr) */
5397 e1000_shift_out_ee_bits(hw, write_opcode, eeprom->opcode_bits);
5399 e1000_shift_out_ee_bits(hw, (uint16_t)((offset + widx)*2),
5400 eeprom->address_bits);
5404 /* Loop to allow for up to whole page write (32 bytes) of eeprom */
5405 while (widx < words) {
5406 uint16_t word_out = data[widx];
5407 word_out = (word_out >> 8) | (word_out << 8);
5408 e1000_shift_out_ee_bits(hw, word_out, 16);
5411 /* Some larger eeprom sizes are capable of a 32-byte PAGE WRITE
5412 * operation, while the smaller eeproms are capable of an 8-byte
5413 * PAGE WRITE operation. Break the inner loop to pass new address
5415 if ((((offset + widx)*2) % eeprom->page_size) == 0) {
5416 e1000_standby_eeprom(hw);
5422 return E1000_SUCCESS;
5425 /******************************************************************************
5426 * Writes a 16 bit word to a given offset in a Microwire EEPROM.
5428 * hw - Struct containing variables accessed by shared code
5429 * offset - offset within the EEPROM to be written to
5430 * words - number of words to write
5431 * data - pointer to array of 16 bit words to be written to the EEPROM
5433 *****************************************************************************/
5435 e1000_write_eeprom_microwire(struct e1000_hw *hw,
5440 struct e1000_eeprom_info *eeprom = &hw->eeprom;
5442 uint16_t words_written = 0;
5445 DEBUGFUNC("e1000_write_eeprom_microwire");
5447 /* Send the write enable command to the EEPROM (3-bit opcode plus
5448 * 6/8-bit dummy address beginning with 11). It's less work to include
5449 * the 11 of the dummy address as part of the opcode than it is to shift
5450 * it over the correct number of bits for the address. This puts the
5451 * EEPROM into write/erase mode.
5453 e1000_shift_out_ee_bits(hw, EEPROM_EWEN_OPCODE_MICROWIRE,
5454 (uint16_t)(eeprom->opcode_bits + 2));
5456 e1000_shift_out_ee_bits(hw, 0, (uint16_t)(eeprom->address_bits - 2));
5458 /* Prepare the EEPROM */
5459 e1000_standby_eeprom(hw);
5461 while (words_written < words) {
5462 /* Send the Write command (3-bit opcode + addr) */
5463 e1000_shift_out_ee_bits(hw, EEPROM_WRITE_OPCODE_MICROWIRE,
5464 eeprom->opcode_bits);
5466 e1000_shift_out_ee_bits(hw, (uint16_t)(offset + words_written),
5467 eeprom->address_bits);
5470 e1000_shift_out_ee_bits(hw, data[words_written], 16);
5472 /* Toggle the CS line. This in effect tells the EEPROM to execute
5473 * the previous command.
5475 e1000_standby_eeprom(hw);
5477 /* Read DO repeatedly until it is high (equal to '1'). The EEPROM will
5478 * signal that the command has been completed by raising the DO signal.
5479 * If DO does not go high in 10 milliseconds, then error out.
5481 for (i = 0; i < 200; i++) {
5482 eecd = E1000_READ_REG(hw, EECD);
5483 if (eecd & E1000_EECD_DO) break;
5487 DEBUGOUT("EEPROM Write did not complete\n");
5488 return -E1000_ERR_EEPROM;
5491 /* Recover from write */
5492 e1000_standby_eeprom(hw);
5497 /* Send the write disable command to the EEPROM (3-bit opcode plus
5498 * 6/8-bit dummy address beginning with 10). It's less work to include
5499 * the 10 of the dummy address as part of the opcode than it is to shift
5500 * it over the correct number of bits for the address. This takes the
5501 * EEPROM out of write/erase mode.
5503 e1000_shift_out_ee_bits(hw, EEPROM_EWDS_OPCODE_MICROWIRE,
5504 (uint16_t)(eeprom->opcode_bits + 2));
5506 e1000_shift_out_ee_bits(hw, 0, (uint16_t)(eeprom->address_bits - 2));
5508 return E1000_SUCCESS;
5511 /******************************************************************************
5512 * Flushes the cached eeprom to NVM. This is done by saving the modified values
5513 * in the eeprom cache and the non modified values in the currently active bank
5516 * hw - Struct containing variables accessed by shared code
5517 * offset - offset of word in the EEPROM to read
5518 * data - word read from the EEPROM
5519 * words - number of words to read
5520 *****************************************************************************/
5522 e1000_commit_shadow_ram(struct e1000_hw *hw)
5524 uint32_t attempts = 100000;
5528 int32_t error = E1000_SUCCESS;
5529 uint32_t old_bank_offset = 0;
5530 uint32_t new_bank_offset = 0;
5531 uint8_t low_byte = 0;
5532 uint8_t high_byte = 0;
5533 boolean_t sector_write_failed = FALSE;
5535 if (hw->mac_type == e1000_82573) {
5536 /* The flop register will be used to determine if flash type is STM */
5537 flop = E1000_READ_REG(hw, FLOP);
5538 for (i=0; i < attempts; i++) {
5539 eecd = E1000_READ_REG(hw, EECD);
5540 if ((eecd & E1000_EECD_FLUPD) == 0) {
5546 if (i == attempts) {
5547 return -E1000_ERR_EEPROM;
5550 /* If STM opcode located in bits 15:8 of flop, reset firmware */
5551 if ((flop & 0xFF00) == E1000_STM_OPCODE) {
5552 E1000_WRITE_REG(hw, HICR, E1000_HICR_FW_RESET);
5555 /* Perform the flash update */
5556 E1000_WRITE_REG(hw, EECD, eecd | E1000_EECD_FLUPD);
5558 for (i=0; i < attempts; i++) {
5559 eecd = E1000_READ_REG(hw, EECD);
5560 if ((eecd & E1000_EECD_FLUPD) == 0) {
5566 if (i == attempts) {
5567 return -E1000_ERR_EEPROM;
5571 if (hw->mac_type == e1000_ich8lan && hw->eeprom_shadow_ram != NULL) {
5572 /* We're writing to the opposite bank so if we're on bank 1,
5573 * write to bank 0 etc. We also need to erase the segment that
5574 * is going to be written */
5575 if (!(E1000_READ_REG(hw, EECD) & E1000_EECD_SEC1VAL)) {
5576 new_bank_offset = hw->flash_bank_size * 2;
5577 old_bank_offset = 0;
5578 e1000_erase_ich8_4k_segment(hw, 1);
5580 old_bank_offset = hw->flash_bank_size * 2;
5581 new_bank_offset = 0;
5582 e1000_erase_ich8_4k_segment(hw, 0);
5585 sector_write_failed = FALSE;
5586 /* Loop for every byte in the shadow RAM,
5587 * which is in units of words. */
5588 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
5589 /* Determine whether to write the value stored
5590 * in the other NVM bank or a modified value stored
5591 * in the shadow RAM */
5592 if (hw->eeprom_shadow_ram[i].modified == TRUE) {
5593 low_byte = (uint8_t)hw->eeprom_shadow_ram[i].eeprom_word;
5595 error = e1000_verify_write_ich8_byte(hw,
5596 (i << 1) + new_bank_offset, low_byte);
5598 if (error != E1000_SUCCESS)
5599 sector_write_failed = TRUE;
5602 (uint8_t)(hw->eeprom_shadow_ram[i].eeprom_word >> 8);
5606 e1000_read_ich8_byte(hw, (i << 1) + old_bank_offset,
5609 error = e1000_verify_write_ich8_byte(hw,
5610 (i << 1) + new_bank_offset, low_byte);
5612 if (error != E1000_SUCCESS)
5613 sector_write_failed = TRUE;
5615 e1000_read_ich8_byte(hw, (i << 1) + old_bank_offset + 1,
5621 /* If the write of the low byte was successful, go ahread and
5622 * write the high byte while checking to make sure that if it
5623 * is the signature byte, then it is handled properly */
5624 if (sector_write_failed == FALSE) {
5625 /* If the word is 0x13, then make sure the signature bits
5626 * (15:14) are 11b until the commit has completed.
5627 * This will allow us to write 10b which indicates the
5628 * signature is valid. We want to do this after the write
5629 * has completed so that we don't mark the segment valid
5630 * while the write is still in progress */
5631 if (i == E1000_ICH_NVM_SIG_WORD)
5632 high_byte = E1000_ICH_NVM_SIG_MASK | high_byte;
5634 error = e1000_verify_write_ich8_byte(hw,
5635 (i << 1) + new_bank_offset + 1, high_byte);
5636 if (error != E1000_SUCCESS)
5637 sector_write_failed = TRUE;
5640 /* If the write failed then break from the loop and
5641 * return an error */
5646 /* Don't bother writing the segment valid bits if sector
5647 * programming failed. */
5648 if (sector_write_failed == FALSE) {
5649 /* Finally validate the new segment by setting bit 15:14
5650 * to 10b in word 0x13 , this can be done without an
5651 * erase as well since these bits are 11 to start with
5652 * and we need to change bit 14 to 0b */
5653 e1000_read_ich8_byte(hw,
5654 E1000_ICH_NVM_SIG_WORD * 2 + 1 + new_bank_offset,
5657 error = e1000_verify_write_ich8_byte(hw,
5658 E1000_ICH_NVM_SIG_WORD * 2 + 1 + new_bank_offset, high_byte);
5659 /* And invalidate the previously valid segment by setting
5660 * its signature word (0x13) high_byte to 0b. This can be
5661 * done without an erase because flash erase sets all bits
5662 * to 1's. We can write 1's to 0's without an erase */
5663 if (error == E1000_SUCCESS) {
5664 error = e1000_verify_write_ich8_byte(hw,
5665 E1000_ICH_NVM_SIG_WORD * 2 + 1 + old_bank_offset, 0);
5668 /* Clear the now not used entry in the cache */
5669 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
5670 hw->eeprom_shadow_ram[i].modified = FALSE;
5671 hw->eeprom_shadow_ram[i].eeprom_word = 0xFFFF;
5679 /******************************************************************************
5680 * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the
5681 * second function of dual function devices
5683 * hw - Struct containing variables accessed by shared code
5684 *****************************************************************************/
5686 e1000_read_mac_addr(struct e1000_hw * hw)
5689 uint16_t eeprom_data, i;
5691 DEBUGFUNC("e1000_read_mac_addr");
5693 for (i = 0; i < NODE_ADDRESS_SIZE; i += 2) {
5695 if (e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) {
5696 DEBUGOUT("EEPROM Read Error\n");
5697 return -E1000_ERR_EEPROM;
5699 hw->perm_mac_addr[i] = (uint8_t) (eeprom_data & 0x00FF);
5700 hw->perm_mac_addr[i+1] = (uint8_t) (eeprom_data >> 8);
5703 switch (hw->mac_type) {
5707 case e1000_82546_rev_3:
5709 case e1000_80003es2lan:
5710 if (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)
5711 hw->perm_mac_addr[5] ^= 0x01;
5715 for (i = 0; i < NODE_ADDRESS_SIZE; i++)
5716 hw->mac_addr[i] = hw->perm_mac_addr[i];
5717 return E1000_SUCCESS;
5720 /******************************************************************************
5721 * Initializes receive address filters.
5723 * hw - Struct containing variables accessed by shared code
5725 * Places the MAC address in receive address register 0 and clears the rest
5726 * of the receive addresss registers. Clears the multicast table. Assumes
5727 * the receiver is in reset when the routine is called.
5728 *****************************************************************************/
5730 e1000_init_rx_addrs(struct e1000_hw *hw)
5735 DEBUGFUNC("e1000_init_rx_addrs");
5737 /* Setup the receive address. */
5738 DEBUGOUT("Programming MAC Address into RAR[0]\n");
5740 e1000_rar_set(hw, hw->mac_addr, 0);
5742 rar_num = E1000_RAR_ENTRIES;
5744 /* Reserve a spot for the Locally Administered Address to work around
5745 * an 82571 issue in which a reset on one port will reload the MAC on
5746 * the other port. */
5747 if ((hw->mac_type == e1000_82571) && (hw->laa_is_present == TRUE))
5749 if (hw->mac_type == e1000_ich8lan)
5750 rar_num = E1000_RAR_ENTRIES_ICH8LAN;
5752 /* Zero out the other 15 receive addresses. */
5753 DEBUGOUT("Clearing RAR[1-15]\n");
5754 for (i = 1; i < rar_num; i++) {
5755 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
5756 E1000_WRITE_FLUSH(hw);
5757 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
5758 E1000_WRITE_FLUSH(hw);
5762 /******************************************************************************
5763 * Hashes an address to determine its location in the multicast table
5765 * hw - Struct containing variables accessed by shared code
5766 * mc_addr - the multicast address to hash
5767 *****************************************************************************/
5769 e1000_hash_mc_addr(struct e1000_hw *hw,
5772 uint32_t hash_value = 0;
5774 /* The portion of the address that is used for the hash table is
5775 * determined by the mc_filter_type setting.
5777 switch (hw->mc_filter_type) {
5778 /* [0] [1] [2] [3] [4] [5]
5783 if (hw->mac_type == e1000_ich8lan) {
5784 /* [47:38] i.e. 0x158 for above example address */
5785 hash_value = ((mc_addr[4] >> 6) | (((uint16_t) mc_addr[5]) << 2));
5787 /* [47:36] i.e. 0x563 for above example address */
5788 hash_value = ((mc_addr[4] >> 4) | (((uint16_t) mc_addr[5]) << 4));
5792 if (hw->mac_type == e1000_ich8lan) {
5793 /* [46:37] i.e. 0x2B1 for above example address */
5794 hash_value = ((mc_addr[4] >> 5) | (((uint16_t) mc_addr[5]) << 3));
5796 /* [46:35] i.e. 0xAC6 for above example address */
5797 hash_value = ((mc_addr[4] >> 3) | (((uint16_t) mc_addr[5]) << 5));
5801 if (hw->mac_type == e1000_ich8lan) {
5802 /*[45:36] i.e. 0x163 for above example address */
5803 hash_value = ((mc_addr[4] >> 4) | (((uint16_t) mc_addr[5]) << 4));
5805 /* [45:34] i.e. 0x5D8 for above example address */
5806 hash_value = ((mc_addr[4] >> 2) | (((uint16_t) mc_addr[5]) << 6));
5810 if (hw->mac_type == e1000_ich8lan) {
5811 /* [43:34] i.e. 0x18D for above example address */
5812 hash_value = ((mc_addr[4] >> 2) | (((uint16_t) mc_addr[5]) << 6));
5814 /* [43:32] i.e. 0x634 for above example address */
5815 hash_value = ((mc_addr[4]) | (((uint16_t) mc_addr[5]) << 8));
5820 hash_value &= 0xFFF;
5821 if (hw->mac_type == e1000_ich8lan)
5822 hash_value &= 0x3FF;
5827 /******************************************************************************
5828 * Sets the bit in the multicast table corresponding to the hash value.
5830 * hw - Struct containing variables accessed by shared code
5831 * hash_value - Multicast address hash value
5832 *****************************************************************************/
5834 e1000_mta_set(struct e1000_hw *hw,
5835 uint32_t hash_value)
5837 uint32_t hash_bit, hash_reg;
5841 /* The MTA is a register array of 128 32-bit registers.
5842 * It is treated like an array of 4096 bits. We want to set
5843 * bit BitArray[hash_value]. So we figure out what register
5844 * the bit is in, read it, OR in the new bit, then write
5845 * back the new value. The register is determined by the
5846 * upper 7 bits of the hash value and the bit within that
5847 * register are determined by the lower 5 bits of the value.
5849 hash_reg = (hash_value >> 5) & 0x7F;
5850 if (hw->mac_type == e1000_ich8lan)
5853 hash_bit = hash_value & 0x1F;
5855 mta = E1000_READ_REG_ARRAY(hw, MTA, hash_reg);
5857 mta |= (1 << hash_bit);
5859 /* If we are on an 82544 and we are trying to write an odd offset
5860 * in the MTA, save off the previous entry before writing and
5861 * restore the old value after writing.
5863 if ((hw->mac_type == e1000_82544) && ((hash_reg & 0x1) == 1)) {
5864 temp = E1000_READ_REG_ARRAY(hw, MTA, (hash_reg - 1));
5865 E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta);
5866 E1000_WRITE_FLUSH(hw);
5867 E1000_WRITE_REG_ARRAY(hw, MTA, (hash_reg - 1), temp);
5868 E1000_WRITE_FLUSH(hw);
5870 E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta);
5871 E1000_WRITE_FLUSH(hw);
5875 /******************************************************************************
5876 * Puts an ethernet address into a receive address register.
5878 * hw - Struct containing variables accessed by shared code
5879 * addr - Address to put into receive address register
5880 * index - Receive address register to write
5881 *****************************************************************************/
5883 e1000_rar_set(struct e1000_hw *hw,
5887 uint32_t rar_low, rar_high;
5889 /* HW expects these in little endian so we reverse the byte order
5890 * from network order (big endian) to little endian
5892 rar_low = ((uint32_t) addr[0] |
5893 ((uint32_t) addr[1] << 8) |
5894 ((uint32_t) addr[2] << 16) | ((uint32_t) addr[3] << 24));
5895 rar_high = ((uint32_t) addr[4] | ((uint32_t) addr[5] << 8));
5897 /* Disable Rx and flush all Rx frames before enabling RSS to avoid Rx
5901 * If there are any Rx frames queued up or otherwise present in the HW
5902 * before RSS is enabled, and then we enable RSS, the HW Rx unit will
5903 * hang. To work around this issue, we have to disable receives and
5904 * flush out all Rx frames before we enable RSS. To do so, we modify we
5905 * redirect all Rx traffic to manageability and then reset the HW.
5906 * This flushes away Rx frames, and (since the redirections to
5907 * manageability persists across resets) keeps new ones from coming in
5908 * while we work. Then, we clear the Address Valid AV bit for all MAC
5909 * addresses and undo the re-direction to manageability.
5910 * Now, frames are coming in again, but the MAC won't accept them, so
5911 * far so good. We now proceed to initialize RSS (if necessary) and
5912 * configure the Rx unit. Last, we re-enable the AV bits and continue
5915 switch (hw->mac_type) {
5918 case e1000_80003es2lan:
5919 if (hw->leave_av_bit_off == TRUE)
5922 /* Indicate to hardware the Address is Valid. */
5923 rar_high |= E1000_RAH_AV;
5927 E1000_WRITE_REG_ARRAY(hw, RA, (index << 1), rar_low);
5928 E1000_WRITE_FLUSH(hw);
5929 E1000_WRITE_REG_ARRAY(hw, RA, ((index << 1) + 1), rar_high);
5930 E1000_WRITE_FLUSH(hw);
5933 /******************************************************************************
5934 * Writes a value to the specified offset in the VLAN filter table.
5936 * hw - Struct containing variables accessed by shared code
5937 * offset - Offset in VLAN filer table to write
5938 * value - Value to write into VLAN filter table
5939 *****************************************************************************/
5941 e1000_write_vfta(struct e1000_hw *hw,
5947 if (hw->mac_type == e1000_ich8lan)
5950 if ((hw->mac_type == e1000_82544) && ((offset & 0x1) == 1)) {
5951 temp = E1000_READ_REG_ARRAY(hw, VFTA, (offset - 1));
5952 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value);
5953 E1000_WRITE_FLUSH(hw);
5954 E1000_WRITE_REG_ARRAY(hw, VFTA, (offset - 1), temp);
5955 E1000_WRITE_FLUSH(hw);
5957 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value);
5958 E1000_WRITE_FLUSH(hw);
5962 /******************************************************************************
5963 * Clears the VLAN filer table
5965 * hw - Struct containing variables accessed by shared code
5966 *****************************************************************************/
5968 e1000_clear_vfta(struct e1000_hw *hw)
5971 uint32_t vfta_value = 0;
5972 uint32_t vfta_offset = 0;
5973 uint32_t vfta_bit_in_reg = 0;
5975 if (hw->mac_type == e1000_ich8lan)
5978 if (hw->mac_type == e1000_82573) {
5979 if (hw->mng_cookie.vlan_id != 0) {
5980 /* The VFTA is a 4096b bit-field, each identifying a single VLAN
5981 * ID. The following operations determine which 32b entry
5982 * (i.e. offset) into the array we want to set the VLAN ID
5983 * (i.e. bit) of the manageability unit. */
5984 vfta_offset = (hw->mng_cookie.vlan_id >>
5985 E1000_VFTA_ENTRY_SHIFT) &
5986 E1000_VFTA_ENTRY_MASK;
5987 vfta_bit_in_reg = 1 << (hw->mng_cookie.vlan_id &
5988 E1000_VFTA_ENTRY_BIT_SHIFT_MASK);
5991 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
5992 /* If the offset we want to clear is the same offset of the
5993 * manageability VLAN ID, then clear all bits except that of the
5994 * manageability unit */
5995 vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0;
5996 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, vfta_value);
5997 E1000_WRITE_FLUSH(hw);
6002 e1000_id_led_init(struct e1000_hw * hw)
6005 const uint32_t ledctl_mask = 0x000000FF;
6006 const uint32_t ledctl_on = E1000_LEDCTL_MODE_LED_ON;
6007 const uint32_t ledctl_off = E1000_LEDCTL_MODE_LED_OFF;
6008 uint16_t eeprom_data, i, temp;
6009 const uint16_t led_mask = 0x0F;
6011 DEBUGFUNC("e1000_id_led_init");
6013 if (hw->mac_type < e1000_82540) {
6015 return E1000_SUCCESS;
6018 ledctl = E1000_READ_REG(hw, LEDCTL);
6019 hw->ledctl_default = ledctl;
6020 hw->ledctl_mode1 = hw->ledctl_default;
6021 hw->ledctl_mode2 = hw->ledctl_default;
6023 if (e1000_read_eeprom(hw, EEPROM_ID_LED_SETTINGS, 1, &eeprom_data) < 0) {
6024 DEBUGOUT("EEPROM Read Error\n");
6025 return -E1000_ERR_EEPROM;
6028 if ((hw->mac_type == e1000_82573) &&
6029 (eeprom_data == ID_LED_RESERVED_82573))
6030 eeprom_data = ID_LED_DEFAULT_82573;
6031 else if ((eeprom_data == ID_LED_RESERVED_0000) ||
6032 (eeprom_data == ID_LED_RESERVED_FFFF)) {
6033 if (hw->mac_type == e1000_ich8lan)
6034 eeprom_data = ID_LED_DEFAULT_ICH8LAN;
6036 eeprom_data = ID_LED_DEFAULT;
6039 for (i = 0; i < 4; i++) {
6040 temp = (eeprom_data >> (i << 2)) & led_mask;
6042 case ID_LED_ON1_DEF2:
6043 case ID_LED_ON1_ON2:
6044 case ID_LED_ON1_OFF2:
6045 hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
6046 hw->ledctl_mode1 |= ledctl_on << (i << 3);
6048 case ID_LED_OFF1_DEF2:
6049 case ID_LED_OFF1_ON2:
6050 case ID_LED_OFF1_OFF2:
6051 hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
6052 hw->ledctl_mode1 |= ledctl_off << (i << 3);
6059 case ID_LED_DEF1_ON2:
6060 case ID_LED_ON1_ON2:
6061 case ID_LED_OFF1_ON2:
6062 hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
6063 hw->ledctl_mode2 |= ledctl_on << (i << 3);
6065 case ID_LED_DEF1_OFF2:
6066 case ID_LED_ON1_OFF2:
6067 case ID_LED_OFF1_OFF2:
6068 hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
6069 hw->ledctl_mode2 |= ledctl_off << (i << 3);
6076 return E1000_SUCCESS;
6079 /******************************************************************************
6080 * Prepares SW controlable LED for use and saves the current state of the LED.
6082 * hw - Struct containing variables accessed by shared code
6083 *****************************************************************************/
6085 e1000_setup_led(struct e1000_hw *hw)
6088 int32_t ret_val = E1000_SUCCESS;
6090 DEBUGFUNC("e1000_setup_led");
6092 switch (hw->mac_type) {
6093 case e1000_82542_rev2_0:
6094 case e1000_82542_rev2_1:
6097 /* No setup necessary */
6101 case e1000_82541_rev_2:
6102 case e1000_82547_rev_2:
6103 /* Turn off PHY Smart Power Down (if enabled) */
6104 ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO,
6105 &hw->phy_spd_default);
6108 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
6109 (uint16_t)(hw->phy_spd_default &
6110 ~IGP01E1000_GMII_SPD));
6115 if (hw->media_type == e1000_media_type_fiber) {
6116 ledctl = E1000_READ_REG(hw, LEDCTL);
6117 /* Save current LEDCTL settings */
6118 hw->ledctl_default = ledctl;
6120 ledctl &= ~(E1000_LEDCTL_LED0_IVRT |
6121 E1000_LEDCTL_LED0_BLINK |
6122 E1000_LEDCTL_LED0_MODE_MASK);
6123 ledctl |= (E1000_LEDCTL_MODE_LED_OFF <<
6124 E1000_LEDCTL_LED0_MODE_SHIFT);
6125 E1000_WRITE_REG(hw, LEDCTL, ledctl);
6126 } else if (hw->media_type == e1000_media_type_copper)
6127 E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode1);
6131 return E1000_SUCCESS;
6135 /******************************************************************************
6136 * Used on 82571 and later Si that has LED blink bits.
6137 * Callers must use their own timer and should have already called
6138 * e1000_id_led_init()
6139 * Call e1000_cleanup led() to stop blinking
6141 * hw - Struct containing variables accessed by shared code
6142 *****************************************************************************/
6144 e1000_blink_led_start(struct e1000_hw *hw)
6147 uint32_t ledctl_blink = 0;
6149 DEBUGFUNC("e1000_id_led_blink_on");
6151 if (hw->mac_type < e1000_82571) {
6153 return E1000_SUCCESS;
6155 if (hw->media_type == e1000_media_type_fiber) {
6156 /* always blink LED0 for PCI-E fiber */
6157 ledctl_blink = E1000_LEDCTL_LED0_BLINK |
6158 (E1000_LEDCTL_MODE_LED_ON << E1000_LEDCTL_LED0_MODE_SHIFT);
6160 /* set the blink bit for each LED that's "on" (0x0E) in ledctl_mode2 */
6161 ledctl_blink = hw->ledctl_mode2;
6162 for (i=0; i < 4; i++)
6163 if (((hw->ledctl_mode2 >> (i * 8)) & 0xFF) ==
6164 E1000_LEDCTL_MODE_LED_ON)
6165 ledctl_blink |= (E1000_LEDCTL_LED0_BLINK << (i * 8));
6168 E1000_WRITE_REG(hw, LEDCTL, ledctl_blink);
6170 return E1000_SUCCESS;
6173 /******************************************************************************
6174 * Restores the saved state of the SW controlable LED.
6176 * hw - Struct containing variables accessed by shared code
6177 *****************************************************************************/
6179 e1000_cleanup_led(struct e1000_hw *hw)
6181 int32_t ret_val = E1000_SUCCESS;
6183 DEBUGFUNC("e1000_cleanup_led");
6185 switch (hw->mac_type) {
6186 case e1000_82542_rev2_0:
6187 case e1000_82542_rev2_1:
6190 /* No cleanup necessary */
6194 case e1000_82541_rev_2:
6195 case e1000_82547_rev_2:
6196 /* Turn on PHY Smart Power Down (if previously enabled) */
6197 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
6198 hw->phy_spd_default);
6203 if (hw->phy_type == e1000_phy_ife) {
6204 e1000_write_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0);
6207 /* Restore LEDCTL settings */
6208 E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_default);
6212 return E1000_SUCCESS;
6215 /******************************************************************************
6216 * Turns on the software controllable LED
6218 * hw - Struct containing variables accessed by shared code
6219 *****************************************************************************/
6221 e1000_led_on(struct e1000_hw *hw)
6223 uint32_t ctrl = E1000_READ_REG(hw, CTRL);
6225 DEBUGFUNC("e1000_led_on");
6227 switch (hw->mac_type) {
6228 case e1000_82542_rev2_0:
6229 case e1000_82542_rev2_1:
6231 /* Set SW Defineable Pin 0 to turn on the LED */
6232 ctrl |= E1000_CTRL_SWDPIN0;
6233 ctrl |= E1000_CTRL_SWDPIO0;
6236 if (hw->media_type == e1000_media_type_fiber) {
6237 /* Set SW Defineable Pin 0 to turn on the LED */
6238 ctrl |= E1000_CTRL_SWDPIN0;
6239 ctrl |= E1000_CTRL_SWDPIO0;
6241 /* Clear SW Defineable Pin 0 to turn on the LED */
6242 ctrl &= ~E1000_CTRL_SWDPIN0;
6243 ctrl |= E1000_CTRL_SWDPIO0;
6247 if (hw->media_type == e1000_media_type_fiber) {
6248 /* Clear SW Defineable Pin 0 to turn on the LED */
6249 ctrl &= ~E1000_CTRL_SWDPIN0;
6250 ctrl |= E1000_CTRL_SWDPIO0;
6251 } else if (hw->phy_type == e1000_phy_ife) {
6252 e1000_write_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
6253 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
6254 } else if (hw->media_type == e1000_media_type_copper) {
6255 E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode2);
6256 return E1000_SUCCESS;
6261 E1000_WRITE_REG(hw, CTRL, ctrl);
6263 return E1000_SUCCESS;
6266 /******************************************************************************
6267 * Turns off the software controllable LED
6269 * hw - Struct containing variables accessed by shared code
6270 *****************************************************************************/
6272 e1000_led_off(struct e1000_hw *hw)
6274 uint32_t ctrl = E1000_READ_REG(hw, CTRL);
6276 DEBUGFUNC("e1000_led_off");
6278 switch (hw->mac_type) {
6279 case e1000_82542_rev2_0:
6280 case e1000_82542_rev2_1:
6282 /* Clear SW Defineable Pin 0 to turn off the LED */
6283 ctrl &= ~E1000_CTRL_SWDPIN0;
6284 ctrl |= E1000_CTRL_SWDPIO0;
6287 if (hw->media_type == e1000_media_type_fiber) {
6288 /* Clear SW Defineable Pin 0 to turn off the LED */
6289 ctrl &= ~E1000_CTRL_SWDPIN0;
6290 ctrl |= E1000_CTRL_SWDPIO0;
6292 /* Set SW Defineable Pin 0 to turn off the LED */
6293 ctrl |= E1000_CTRL_SWDPIN0;
6294 ctrl |= E1000_CTRL_SWDPIO0;
6298 if (hw->media_type == e1000_media_type_fiber) {
6299 /* Set SW Defineable Pin 0 to turn off the LED */
6300 ctrl |= E1000_CTRL_SWDPIN0;
6301 ctrl |= E1000_CTRL_SWDPIO0;
6302 } else if (hw->phy_type == e1000_phy_ife) {
6303 e1000_write_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
6304 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_OFF));
6305 } else if (hw->media_type == e1000_media_type_copper) {
6306 E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode1);
6307 return E1000_SUCCESS;
6312 E1000_WRITE_REG(hw, CTRL, ctrl);
6314 return E1000_SUCCESS;
6317 /******************************************************************************
6318 * Clears all hardware statistics counters.
6320 * hw - Struct containing variables accessed by shared code
6321 *****************************************************************************/
6323 e1000_clear_hw_cntrs(struct e1000_hw *hw)
6325 volatile uint32_t temp;
6327 temp = E1000_READ_REG(hw, CRCERRS);
6328 temp = E1000_READ_REG(hw, SYMERRS);
6329 temp = E1000_READ_REG(hw, MPC);
6330 temp = E1000_READ_REG(hw, SCC);
6331 temp = E1000_READ_REG(hw, ECOL);
6332 temp = E1000_READ_REG(hw, MCC);
6333 temp = E1000_READ_REG(hw, LATECOL);
6334 temp = E1000_READ_REG(hw, COLC);
6335 temp = E1000_READ_REG(hw, DC);
6336 temp = E1000_READ_REG(hw, SEC);
6337 temp = E1000_READ_REG(hw, RLEC);
6338 temp = E1000_READ_REG(hw, XONRXC);
6339 temp = E1000_READ_REG(hw, XONTXC);
6340 temp = E1000_READ_REG(hw, XOFFRXC);
6341 temp = E1000_READ_REG(hw, XOFFTXC);
6342 temp = E1000_READ_REG(hw, FCRUC);
6344 if (hw->mac_type != e1000_ich8lan) {
6345 temp = E1000_READ_REG(hw, PRC64);
6346 temp = E1000_READ_REG(hw, PRC127);
6347 temp = E1000_READ_REG(hw, PRC255);
6348 temp = E1000_READ_REG(hw, PRC511);
6349 temp = E1000_READ_REG(hw, PRC1023);
6350 temp = E1000_READ_REG(hw, PRC1522);
6353 temp = E1000_READ_REG(hw, GPRC);
6354 temp = E1000_READ_REG(hw, BPRC);
6355 temp = E1000_READ_REG(hw, MPRC);
6356 temp = E1000_READ_REG(hw, GPTC);
6357 temp = E1000_READ_REG(hw, GORCL);
6358 temp = E1000_READ_REG(hw, GORCH);
6359 temp = E1000_READ_REG(hw, GOTCL);
6360 temp = E1000_READ_REG(hw, GOTCH);
6361 temp = E1000_READ_REG(hw, RNBC);
6362 temp = E1000_READ_REG(hw, RUC);
6363 temp = E1000_READ_REG(hw, RFC);
6364 temp = E1000_READ_REG(hw, ROC);
6365 temp = E1000_READ_REG(hw, RJC);
6366 temp = E1000_READ_REG(hw, TORL);
6367 temp = E1000_READ_REG(hw, TORH);
6368 temp = E1000_READ_REG(hw, TOTL);
6369 temp = E1000_READ_REG(hw, TOTH);
6370 temp = E1000_READ_REG(hw, TPR);
6371 temp = E1000_READ_REG(hw, TPT);
6373 if (hw->mac_type != e1000_ich8lan) {
6374 temp = E1000_READ_REG(hw, PTC64);
6375 temp = E1000_READ_REG(hw, PTC127);
6376 temp = E1000_READ_REG(hw, PTC255);
6377 temp = E1000_READ_REG(hw, PTC511);
6378 temp = E1000_READ_REG(hw, PTC1023);
6379 temp = E1000_READ_REG(hw, PTC1522);
6382 temp = E1000_READ_REG(hw, MPTC);
6383 temp = E1000_READ_REG(hw, BPTC);
6385 if (hw->mac_type < e1000_82543) return;
6387 temp = E1000_READ_REG(hw, ALGNERRC);
6388 temp = E1000_READ_REG(hw, RXERRC);
6389 temp = E1000_READ_REG(hw, TNCRS);
6390 temp = E1000_READ_REG(hw, CEXTERR);
6391 temp = E1000_READ_REG(hw, TSCTC);
6392 temp = E1000_READ_REG(hw, TSCTFC);
6394 if (hw->mac_type <= e1000_82544) return;
6396 temp = E1000_READ_REG(hw, MGTPRC);
6397 temp = E1000_READ_REG(hw, MGTPDC);
6398 temp = E1000_READ_REG(hw, MGTPTC);
6400 if (hw->mac_type <= e1000_82547_rev_2) return;
6402 temp = E1000_READ_REG(hw, IAC);
6403 temp = E1000_READ_REG(hw, ICRXOC);
6405 if (hw->mac_type == e1000_ich8lan) return;
6407 temp = E1000_READ_REG(hw, ICRXPTC);
6408 temp = E1000_READ_REG(hw, ICRXATC);
6409 temp = E1000_READ_REG(hw, ICTXPTC);
6410 temp = E1000_READ_REG(hw, ICTXATC);
6411 temp = E1000_READ_REG(hw, ICTXQEC);
6412 temp = E1000_READ_REG(hw, ICTXQMTC);
6413 temp = E1000_READ_REG(hw, ICRXDMTC);
6416 /******************************************************************************
6417 * Resets Adaptive IFS to its default state.
6419 * hw - Struct containing variables accessed by shared code
6421 * Call this after e1000_init_hw. You may override the IFS defaults by setting
6422 * hw->ifs_params_forced to TRUE. However, you must initialize hw->
6423 * current_ifs_val, ifs_min_val, ifs_max_val, ifs_step_size, and ifs_ratio
6424 * before calling this function.
6425 *****************************************************************************/
6427 e1000_reset_adaptive(struct e1000_hw *hw)
6429 DEBUGFUNC("e1000_reset_adaptive");
6431 if (hw->adaptive_ifs) {
6432 if (!hw->ifs_params_forced) {
6433 hw->current_ifs_val = 0;
6434 hw->ifs_min_val = IFS_MIN;
6435 hw->ifs_max_val = IFS_MAX;
6436 hw->ifs_step_size = IFS_STEP;
6437 hw->ifs_ratio = IFS_RATIO;
6439 hw->in_ifs_mode = FALSE;
6440 E1000_WRITE_REG(hw, AIT, 0);
6442 DEBUGOUT("Not in Adaptive IFS mode!\n");
6446 /******************************************************************************
6447 * Called during the callback/watchdog routine to update IFS value based on
6448 * the ratio of transmits to collisions.
6450 * hw - Struct containing variables accessed by shared code
6451 * tx_packets - Number of transmits since last callback
6452 * total_collisions - Number of collisions since last callback
6453 *****************************************************************************/
6455 e1000_update_adaptive(struct e1000_hw *hw)
6457 DEBUGFUNC("e1000_update_adaptive");
6459 if (hw->adaptive_ifs) {
6460 if ((hw->collision_delta * hw->ifs_ratio) > hw->tx_packet_delta) {
6461 if (hw->tx_packet_delta > MIN_NUM_XMITS) {
6462 hw->in_ifs_mode = TRUE;
6463 if (hw->current_ifs_val < hw->ifs_max_val) {
6464 if (hw->current_ifs_val == 0)
6465 hw->current_ifs_val = hw->ifs_min_val;
6467 hw->current_ifs_val += hw->ifs_step_size;
6468 E1000_WRITE_REG(hw, AIT, hw->current_ifs_val);
6472 if (hw->in_ifs_mode && (hw->tx_packet_delta <= MIN_NUM_XMITS)) {
6473 hw->current_ifs_val = 0;
6474 hw->in_ifs_mode = FALSE;
6475 E1000_WRITE_REG(hw, AIT, 0);
6479 DEBUGOUT("Not in Adaptive IFS mode!\n");
6483 /******************************************************************************
6484 * Adjusts the statistic counters when a frame is accepted by TBI_ACCEPT
6486 * hw - Struct containing variables accessed by shared code
6487 * frame_len - The length of the frame in question
6488 * mac_addr - The Ethernet destination address of the frame in question
6489 *****************************************************************************/
6491 e1000_tbi_adjust_stats(struct e1000_hw *hw,
6492 struct e1000_hw_stats *stats,
6498 /* First adjust the frame length. */
6500 /* We need to adjust the statistics counters, since the hardware
6501 * counters overcount this packet as a CRC error and undercount
6502 * the packet as a good packet
6504 /* This packet should not be counted as a CRC error. */
6506 /* This packet does count as a Good Packet Received. */
6509 /* Adjust the Good Octets received counters */
6510 carry_bit = 0x80000000 & stats->gorcl;
6511 stats->gorcl += frame_len;
6512 /* If the high bit of Gorcl (the low 32 bits of the Good Octets
6513 * Received Count) was one before the addition,
6514 * AND it is zero after, then we lost the carry out,
6515 * need to add one to Gorch (Good Octets Received Count High).
6516 * This could be simplified if all environments supported
6519 if (carry_bit && ((stats->gorcl & 0x80000000) == 0))
6521 /* Is this a broadcast or multicast? Check broadcast first,
6522 * since the test for a multicast frame will test positive on
6523 * a broadcast frame.
6525 if ((mac_addr[0] == (uint8_t) 0xff) && (mac_addr[1] == (uint8_t) 0xff))
6526 /* Broadcast packet */
6528 else if (*mac_addr & 0x01)
6529 /* Multicast packet */
6532 if (frame_len == hw->max_frame_size) {
6533 /* In this case, the hardware has overcounted the number of
6540 /* Adjust the bin counters when the extra byte put the frame in the
6541 * wrong bin. Remember that the frame_len was adjusted above.
6543 if (frame_len == 64) {
6546 } else if (frame_len == 127) {
6549 } else if (frame_len == 255) {
6552 } else if (frame_len == 511) {
6555 } else if (frame_len == 1023) {
6558 } else if (frame_len == 1522) {
6563 /******************************************************************************
6564 * Gets the current PCI bus type, speed, and width of the hardware
6566 * hw - Struct containing variables accessed by shared code
6567 *****************************************************************************/
6569 e1000_get_bus_info(struct e1000_hw *hw)
6572 uint16_t pci_ex_link_status;
6575 switch (hw->mac_type) {
6576 case e1000_82542_rev2_0:
6577 case e1000_82542_rev2_1:
6578 hw->bus_type = e1000_bus_type_unknown;
6579 hw->bus_speed = e1000_bus_speed_unknown;
6580 hw->bus_width = e1000_bus_width_unknown;
6585 case e1000_80003es2lan:
6586 hw->bus_type = e1000_bus_type_pci_express;
6587 hw->bus_speed = e1000_bus_speed_2500;
6588 ret_val = e1000_read_pcie_cap_reg(hw,
6590 &pci_ex_link_status);
6592 hw->bus_width = e1000_bus_width_unknown;
6594 hw->bus_width = (pci_ex_link_status & PCI_EX_LINK_WIDTH_MASK) >>
6595 PCI_EX_LINK_WIDTH_SHIFT;
6598 hw->bus_type = e1000_bus_type_pci_express;
6599 hw->bus_speed = e1000_bus_speed_2500;
6600 hw->bus_width = e1000_bus_width_pciex_1;
6603 status = E1000_READ_REG(hw, STATUS);
6604 hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ?
6605 e1000_bus_type_pcix : e1000_bus_type_pci;
6607 if (hw->device_id == E1000_DEV_ID_82546EB_QUAD_COPPER) {
6608 hw->bus_speed = (hw->bus_type == e1000_bus_type_pci) ?
6609 e1000_bus_speed_66 : e1000_bus_speed_120;
6610 } else if (hw->bus_type == e1000_bus_type_pci) {
6611 hw->bus_speed = (status & E1000_STATUS_PCI66) ?
6612 e1000_bus_speed_66 : e1000_bus_speed_33;
6614 switch (status & E1000_STATUS_PCIX_SPEED) {
6615 case E1000_STATUS_PCIX_SPEED_66:
6616 hw->bus_speed = e1000_bus_speed_66;
6618 case E1000_STATUS_PCIX_SPEED_100:
6619 hw->bus_speed = e1000_bus_speed_100;
6621 case E1000_STATUS_PCIX_SPEED_133:
6622 hw->bus_speed = e1000_bus_speed_133;
6625 hw->bus_speed = e1000_bus_speed_reserved;
6629 hw->bus_width = (status & E1000_STATUS_BUS64) ?
6630 e1000_bus_width_64 : e1000_bus_width_32;
6635 /******************************************************************************
6636 * Writes a value to one of the devices registers using port I/O (as opposed to
6637 * memory mapped I/O). Only 82544 and newer devices support port I/O.
6639 * hw - Struct containing variables accessed by shared code
6640 * offset - offset to write to
6641 * value - value to write
6642 *****************************************************************************/
6644 e1000_write_reg_io(struct e1000_hw *hw,
6648 unsigned long io_addr = hw->io_base;
6649 unsigned long io_data = hw->io_base + 4;
6651 e1000_io_write(hw, io_addr, offset);
6652 e1000_io_write(hw, io_data, value);
6655 /******************************************************************************
6656 * Estimates the cable length.
6658 * hw - Struct containing variables accessed by shared code
6659 * min_length - The estimated minimum length
6660 * max_length - The estimated maximum length
6662 * returns: - E1000_ERR_XXX
6665 * This function always returns a ranged length (minimum & maximum).
6666 * So for M88 phy's, this function interprets the one value returned from the
6667 * register to the minimum and maximum range.
6668 * For IGP phy's, the function calculates the range by the AGC registers.
6669 *****************************************************************************/
6671 e1000_get_cable_length(struct e1000_hw *hw,
6672 uint16_t *min_length,
6673 uint16_t *max_length)
6676 uint16_t agc_value = 0;
6677 uint16_t i, phy_data;
6678 uint16_t cable_length;
6680 DEBUGFUNC("e1000_get_cable_length");
6682 *min_length = *max_length = 0;
6684 /* Use old method for Phy older than IGP */
6685 if (hw->phy_type == e1000_phy_m88) {
6687 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
6691 cable_length = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
6692 M88E1000_PSSR_CABLE_LENGTH_SHIFT;
6694 /* Convert the enum value to ranged values */
6695 switch (cable_length) {
6696 case e1000_cable_length_50:
6698 *max_length = e1000_igp_cable_length_50;
6700 case e1000_cable_length_50_80:
6701 *min_length = e1000_igp_cable_length_50;
6702 *max_length = e1000_igp_cable_length_80;
6704 case e1000_cable_length_80_110:
6705 *min_length = e1000_igp_cable_length_80;
6706 *max_length = e1000_igp_cable_length_110;
6708 case e1000_cable_length_110_140:
6709 *min_length = e1000_igp_cable_length_110;
6710 *max_length = e1000_igp_cable_length_140;
6712 case e1000_cable_length_140:
6713 *min_length = e1000_igp_cable_length_140;
6714 *max_length = e1000_igp_cable_length_170;
6717 return -E1000_ERR_PHY;
6720 } else if (hw->phy_type == e1000_phy_gg82563) {
6721 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_DSP_DISTANCE,
6725 cable_length = phy_data & GG82563_DSPD_CABLE_LENGTH;
6727 switch (cable_length) {
6728 case e1000_gg_cable_length_60:
6730 *max_length = e1000_igp_cable_length_60;
6732 case e1000_gg_cable_length_60_115:
6733 *min_length = e1000_igp_cable_length_60;
6734 *max_length = e1000_igp_cable_length_115;
6736 case e1000_gg_cable_length_115_150:
6737 *min_length = e1000_igp_cable_length_115;
6738 *max_length = e1000_igp_cable_length_150;
6740 case e1000_gg_cable_length_150:
6741 *min_length = e1000_igp_cable_length_150;
6742 *max_length = e1000_igp_cable_length_180;
6745 return -E1000_ERR_PHY;
6748 } else if (hw->phy_type == e1000_phy_igp) { /* For IGP PHY */
6749 uint16_t cur_agc_value;
6750 uint16_t min_agc_value = IGP01E1000_AGC_LENGTH_TABLE_SIZE;
6751 uint16_t agc_reg_array[IGP01E1000_PHY_CHANNEL_NUM] =
6752 {IGP01E1000_PHY_AGC_A,
6753 IGP01E1000_PHY_AGC_B,
6754 IGP01E1000_PHY_AGC_C,
6755 IGP01E1000_PHY_AGC_D};
6756 /* Read the AGC registers for all channels */
6757 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
6759 ret_val = e1000_read_phy_reg(hw, agc_reg_array[i], &phy_data);
6763 cur_agc_value = phy_data >> IGP01E1000_AGC_LENGTH_SHIFT;
6765 /* Value bound check. */
6766 if ((cur_agc_value >= IGP01E1000_AGC_LENGTH_TABLE_SIZE - 1) ||
6767 (cur_agc_value == 0))
6768 return -E1000_ERR_PHY;
6770 agc_value += cur_agc_value;
6772 /* Update minimal AGC value. */
6773 if (min_agc_value > cur_agc_value)
6774 min_agc_value = cur_agc_value;
6777 /* Remove the minimal AGC result for length < 50m */
6778 if (agc_value < IGP01E1000_PHY_CHANNEL_NUM * e1000_igp_cable_length_50) {
6779 agc_value -= min_agc_value;
6781 /* Get the average length of the remaining 3 channels */
6782 agc_value /= (IGP01E1000_PHY_CHANNEL_NUM - 1);
6784 /* Get the average length of all the 4 channels. */
6785 agc_value /= IGP01E1000_PHY_CHANNEL_NUM;
6788 /* Set the range of the calculated length. */
6789 *min_length = ((e1000_igp_cable_length_table[agc_value] -
6790 IGP01E1000_AGC_RANGE) > 0) ?
6791 (e1000_igp_cable_length_table[agc_value] -
6792 IGP01E1000_AGC_RANGE) : 0;
6793 *max_length = e1000_igp_cable_length_table[agc_value] +
6794 IGP01E1000_AGC_RANGE;
6795 } else if (hw->phy_type == e1000_phy_igp_2 ||
6796 hw->phy_type == e1000_phy_igp_3) {
6797 uint16_t cur_agc_index, max_agc_index = 0;
6798 uint16_t min_agc_index = IGP02E1000_AGC_LENGTH_TABLE_SIZE - 1;
6799 uint16_t agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] =
6800 {IGP02E1000_PHY_AGC_A,
6801 IGP02E1000_PHY_AGC_B,
6802 IGP02E1000_PHY_AGC_C,
6803 IGP02E1000_PHY_AGC_D};
6804 /* Read the AGC registers for all channels */
6805 for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) {
6806 ret_val = e1000_read_phy_reg(hw, agc_reg_array[i], &phy_data);
6810 /* Getting bits 15:9, which represent the combination of course and
6811 * fine gain values. The result is a number that can be put into
6812 * the lookup table to obtain the approximate cable length. */
6813 cur_agc_index = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) &
6814 IGP02E1000_AGC_LENGTH_MASK;
6816 /* Array index bound check. */
6817 if ((cur_agc_index >= IGP02E1000_AGC_LENGTH_TABLE_SIZE) ||
6818 (cur_agc_index == 0))
6819 return -E1000_ERR_PHY;
6821 /* Remove min & max AGC values from calculation. */
6822 if (e1000_igp_2_cable_length_table[min_agc_index] >
6823 e1000_igp_2_cable_length_table[cur_agc_index])
6824 min_agc_index = cur_agc_index;
6825 if (e1000_igp_2_cable_length_table[max_agc_index] <
6826 e1000_igp_2_cable_length_table[cur_agc_index])
6827 max_agc_index = cur_agc_index;
6829 agc_value += e1000_igp_2_cable_length_table[cur_agc_index];
6832 agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] +
6833 e1000_igp_2_cable_length_table[max_agc_index]);
6834 agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2);
6836 /* Calculate cable length with the error range of +/- 10 meters. */
6837 *min_length = ((agc_value - IGP02E1000_AGC_RANGE) > 0) ?
6838 (agc_value - IGP02E1000_AGC_RANGE) : 0;
6839 *max_length = agc_value + IGP02E1000_AGC_RANGE;
6842 return E1000_SUCCESS;
6845 /******************************************************************************
6846 * Check the cable polarity
6848 * hw - Struct containing variables accessed by shared code
6849 * polarity - output parameter : 0 - Polarity is not reversed
6850 * 1 - Polarity is reversed.
6852 * returns: - E1000_ERR_XXX
6855 * For phy's older then IGP, this function simply reads the polarity bit in the
6856 * Phy Status register. For IGP phy's, this bit is valid only if link speed is
6857 * 10 Mbps. If the link speed is 100 Mbps there is no polarity so this bit will
6858 * return 0. If the link speed is 1000 Mbps the polarity status is in the
6859 * IGP01E1000_PHY_PCS_INIT_REG.
6860 *****************************************************************************/
6862 e1000_check_polarity(struct e1000_hw *hw,
6863 e1000_rev_polarity *polarity)
6868 DEBUGFUNC("e1000_check_polarity");
6870 if ((hw->phy_type == e1000_phy_m88) ||
6871 (hw->phy_type == e1000_phy_gg82563)) {
6872 /* return the Polarity bit in the Status register. */
6873 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
6877 *polarity = ((phy_data & M88E1000_PSSR_REV_POLARITY) >>
6878 M88E1000_PSSR_REV_POLARITY_SHIFT) ?
6879 e1000_rev_polarity_reversed : e1000_rev_polarity_normal;
6881 } else if (hw->phy_type == e1000_phy_igp ||
6882 hw->phy_type == e1000_phy_igp_3 ||
6883 hw->phy_type == e1000_phy_igp_2) {
6884 /* Read the Status register to check the speed */
6885 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS,
6890 /* If speed is 1000 Mbps, must read the IGP01E1000_PHY_PCS_INIT_REG to
6891 * find the polarity status */
6892 if ((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
6893 IGP01E1000_PSSR_SPEED_1000MBPS) {
6895 /* Read the GIG initialization PCS register (0x00B4) */
6896 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PCS_INIT_REG,
6901 /* Check the polarity bits */
6902 *polarity = (phy_data & IGP01E1000_PHY_POLARITY_MASK) ?
6903 e1000_rev_polarity_reversed : e1000_rev_polarity_normal;
6905 /* For 10 Mbps, read the polarity bit in the status register. (for
6906 * 100 Mbps this bit is always 0) */
6907 *polarity = (phy_data & IGP01E1000_PSSR_POLARITY_REVERSED) ?
6908 e1000_rev_polarity_reversed : e1000_rev_polarity_normal;
6910 } else if (hw->phy_type == e1000_phy_ife) {
6911 ret_val = e1000_read_phy_reg(hw, IFE_PHY_EXTENDED_STATUS_CONTROL,
6915 *polarity = ((phy_data & IFE_PESC_POLARITY_REVERSED) >>
6916 IFE_PESC_POLARITY_REVERSED_SHIFT) ?
6917 e1000_rev_polarity_reversed : e1000_rev_polarity_normal;
6919 return E1000_SUCCESS;
6922 /******************************************************************************
6923 * Check if Downshift occured
6925 * hw - Struct containing variables accessed by shared code
6926 * downshift - output parameter : 0 - No Downshift ocured.
6927 * 1 - Downshift ocured.
6929 * returns: - E1000_ERR_XXX
6932 * For phy's older then IGP, this function reads the Downshift bit in the Phy
6933 * Specific Status register. For IGP phy's, it reads the Downgrade bit in the
6934 * Link Health register. In IGP this bit is latched high, so the driver must
6935 * read it immediately after link is established.
6936 *****************************************************************************/
6938 e1000_check_downshift(struct e1000_hw *hw)
6943 DEBUGFUNC("e1000_check_downshift");
6945 if (hw->phy_type == e1000_phy_igp ||
6946 hw->phy_type == e1000_phy_igp_3 ||
6947 hw->phy_type == e1000_phy_igp_2) {
6948 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_LINK_HEALTH,
6953 hw->speed_downgraded = (phy_data & IGP01E1000_PLHR_SS_DOWNGRADE) ? 1 : 0;
6954 } else if ((hw->phy_type == e1000_phy_m88) ||
6955 (hw->phy_type == e1000_phy_gg82563)) {
6956 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
6961 hw->speed_downgraded = (phy_data & M88E1000_PSSR_DOWNSHIFT) >>
6962 M88E1000_PSSR_DOWNSHIFT_SHIFT;
6963 } else if (hw->phy_type == e1000_phy_ife) {
6964 /* e1000_phy_ife supports 10/100 speed only */
6965 hw->speed_downgraded = FALSE;
6968 return E1000_SUCCESS;
6971 /*****************************************************************************
6973 * 82541_rev_2 & 82547_rev_2 have the capability to configure the DSP when a
6974 * gigabit link is achieved to improve link quality.
6976 * hw: Struct containing variables accessed by shared code
6978 * returns: - E1000_ERR_PHY if fail to read/write the PHY
6979 * E1000_SUCCESS at any other case.
6981 ****************************************************************************/
6984 e1000_config_dsp_after_link_change(struct e1000_hw *hw,
6988 uint16_t phy_data, phy_saved_data, speed, duplex, i;
6989 uint16_t dsp_reg_array[IGP01E1000_PHY_CHANNEL_NUM] =
6990 {IGP01E1000_PHY_AGC_PARAM_A,
6991 IGP01E1000_PHY_AGC_PARAM_B,
6992 IGP01E1000_PHY_AGC_PARAM_C,
6993 IGP01E1000_PHY_AGC_PARAM_D};
6994 uint16_t min_length, max_length;
6996 DEBUGFUNC("e1000_config_dsp_after_link_change");
6998 if (hw->phy_type != e1000_phy_igp)
6999 return E1000_SUCCESS;
7002 ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex);
7004 DEBUGOUT("Error getting link speed and duplex\n");
7008 if (speed == SPEED_1000) {
7010 ret_val = e1000_get_cable_length(hw, &min_length, &max_length);
7014 if ((hw->dsp_config_state == e1000_dsp_config_enabled) &&
7015 min_length >= e1000_igp_cable_length_50) {
7017 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
7018 ret_val = e1000_read_phy_reg(hw, dsp_reg_array[i],
7023 phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX;
7025 ret_val = e1000_write_phy_reg(hw, dsp_reg_array[i],
7030 hw->dsp_config_state = e1000_dsp_config_activated;
7033 if ((hw->ffe_config_state == e1000_ffe_config_enabled) &&
7034 (min_length < e1000_igp_cable_length_50)) {
7036 uint16_t ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_20;
7037 uint32_t idle_errs = 0;
7039 /* clear previous idle error counts */
7040 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS,
7045 for (i = 0; i < ffe_idle_err_timeout; i++) {
7047 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS,
7052 idle_errs += (phy_data & SR_1000T_IDLE_ERROR_CNT);
7053 if (idle_errs > SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT) {
7054 hw->ffe_config_state = e1000_ffe_config_active;
7056 ret_val = e1000_write_phy_reg(hw,
7057 IGP01E1000_PHY_DSP_FFE,
7058 IGP01E1000_PHY_DSP_FFE_CM_CP);
7065 ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_100;
7070 if (hw->dsp_config_state == e1000_dsp_config_activated) {
7071 /* Save off the current value of register 0x2F5B to be restored at
7072 * the end of the routines. */
7073 ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
7078 /* Disable the PHY transmitter */
7079 ret_val = e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
7086 ret_val = e1000_write_phy_reg(hw, 0x0000,
7087 IGP01E1000_IEEE_FORCE_GIGA);
7090 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
7091 ret_val = e1000_read_phy_reg(hw, dsp_reg_array[i], &phy_data);
7095 phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX;
7096 phy_data |= IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS;
7098 ret_val = e1000_write_phy_reg(hw,dsp_reg_array[i], phy_data);
7103 ret_val = e1000_write_phy_reg(hw, 0x0000,
7104 IGP01E1000_IEEE_RESTART_AUTONEG);
7110 /* Now enable the transmitter */
7111 ret_val = e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
7116 hw->dsp_config_state = e1000_dsp_config_enabled;
7119 if (hw->ffe_config_state == e1000_ffe_config_active) {
7120 /* Save off the current value of register 0x2F5B to be restored at
7121 * the end of the routines. */
7122 ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
7127 /* Disable the PHY transmitter */
7128 ret_val = e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
7135 ret_val = e1000_write_phy_reg(hw, 0x0000,
7136 IGP01E1000_IEEE_FORCE_GIGA);
7139 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_DSP_FFE,
7140 IGP01E1000_PHY_DSP_FFE_DEFAULT);
7144 ret_val = e1000_write_phy_reg(hw, 0x0000,
7145 IGP01E1000_IEEE_RESTART_AUTONEG);
7151 /* Now enable the transmitter */
7152 ret_val = e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
7157 hw->ffe_config_state = e1000_ffe_config_enabled;
7160 return E1000_SUCCESS;
7163 /*****************************************************************************
7164 * Set PHY to class A mode
7165 * Assumes the following operations will follow to enable the new class mode.
7166 * 1. Do a PHY soft reset
7167 * 2. Restart auto-negotiation or force link.
7169 * hw - Struct containing variables accessed by shared code
7170 ****************************************************************************/
7172 e1000_set_phy_mode(struct e1000_hw *hw)
7175 uint16_t eeprom_data;
7177 DEBUGFUNC("e1000_set_phy_mode");
7179 if ((hw->mac_type == e1000_82545_rev_3) &&
7180 (hw->media_type == e1000_media_type_copper)) {
7181 ret_val = e1000_read_eeprom(hw, EEPROM_PHY_CLASS_WORD, 1, &eeprom_data);
7186 if ((eeprom_data != EEPROM_RESERVED_WORD) &&
7187 (eeprom_data & EEPROM_PHY_CLASS_A)) {
7188 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x000B);
7191 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x8104);
7195 hw->phy_reset_disable = FALSE;
7199 return E1000_SUCCESS;
7202 /*****************************************************************************
7204 * This function sets the lplu state according to the active flag. When
7205 * activating lplu this function also disables smart speed and vise versa.
7206 * lplu will not be activated unless the device autonegotiation advertisment
7207 * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes.
7208 * hw: Struct containing variables accessed by shared code
7209 * active - true to enable lplu false to disable lplu.
7211 * returns: - E1000_ERR_PHY if fail to read/write the PHY
7212 * E1000_SUCCESS at any other case.
7214 ****************************************************************************/
7217 e1000_set_d3_lplu_state(struct e1000_hw *hw,
7220 uint32_t phy_ctrl = 0;
7223 DEBUGFUNC("e1000_set_d3_lplu_state");
7225 if (hw->phy_type != e1000_phy_igp && hw->phy_type != e1000_phy_igp_2
7226 && hw->phy_type != e1000_phy_igp_3)
7227 return E1000_SUCCESS;
7229 /* During driver activity LPLU should not be used or it will attain link
7230 * from the lowest speeds starting from 10Mbps. The capability is used for
7231 * Dx transitions and states */
7232 if (hw->mac_type == e1000_82541_rev_2 || hw->mac_type == e1000_82547_rev_2) {
7233 ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO, &phy_data);
7236 } else if (hw->mac_type == e1000_ich8lan) {
7237 /* MAC writes into PHY register based on the state transition
7238 * and start auto-negotiation. SW driver can overwrite the settings
7239 * in CSR PHY power control E1000_PHY_CTRL register. */
7240 phy_ctrl = E1000_READ_REG(hw, PHY_CTRL);
7242 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data);
7248 if (hw->mac_type == e1000_82541_rev_2 ||
7249 hw->mac_type == e1000_82547_rev_2) {
7250 phy_data &= ~IGP01E1000_GMII_FLEX_SPD;
7251 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, phy_data);
7255 if (hw->mac_type == e1000_ich8lan) {
7256 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
7257 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
7259 phy_data &= ~IGP02E1000_PM_D3_LPLU;
7260 ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
7267 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during
7268 * Dx states where the power conservation is most important. During
7269 * driver activity we should enable SmartSpeed, so performance is
7271 if (hw->smart_speed == e1000_smart_speed_on) {
7272 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7277 phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
7278 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7282 } else if (hw->smart_speed == e1000_smart_speed_off) {
7283 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7288 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
7289 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7295 } else if ((hw->autoneg_advertised == AUTONEG_ADVERTISE_SPEED_DEFAULT) ||
7296 (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL ) ||
7297 (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_100_ALL)) {
7299 if (hw->mac_type == e1000_82541_rev_2 ||
7300 hw->mac_type == e1000_82547_rev_2) {
7301 phy_data |= IGP01E1000_GMII_FLEX_SPD;
7302 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, phy_data);
7306 if (hw->mac_type == e1000_ich8lan) {
7307 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
7308 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
7310 phy_data |= IGP02E1000_PM_D3_LPLU;
7311 ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
7318 /* When LPLU is enabled we should disable SmartSpeed */
7319 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data);
7323 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
7324 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, phy_data);
7329 return E1000_SUCCESS;
7332 /*****************************************************************************
7334 * This function sets the lplu d0 state according to the active flag. When
7335 * activating lplu this function also disables smart speed and vise versa.
7336 * lplu will not be activated unless the device autonegotiation advertisment
7337 * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes.
7338 * hw: Struct containing variables accessed by shared code
7339 * active - true to enable lplu false to disable lplu.
7341 * returns: - E1000_ERR_PHY if fail to read/write the PHY
7342 * E1000_SUCCESS at any other case.
7344 ****************************************************************************/
7347 e1000_set_d0_lplu_state(struct e1000_hw *hw,
7350 uint32_t phy_ctrl = 0;
7353 DEBUGFUNC("e1000_set_d0_lplu_state");
7355 if (hw->mac_type <= e1000_82547_rev_2)
7356 return E1000_SUCCESS;
7358 if (hw->mac_type == e1000_ich8lan) {
7359 phy_ctrl = E1000_READ_REG(hw, PHY_CTRL);
7361 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data);
7367 if (hw->mac_type == e1000_ich8lan) {
7368 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
7369 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
7371 phy_data &= ~IGP02E1000_PM_D0_LPLU;
7372 ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_data);
7377 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during
7378 * Dx states where the power conservation is most important. During
7379 * driver activity we should enable SmartSpeed, so performance is
7381 if (hw->smart_speed == e1000_smart_speed_on) {
7382 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7387 phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
7388 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7392 } else if (hw->smart_speed == e1000_smart_speed_off) {
7393 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7398 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
7399 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7408 if (hw->mac_type == e1000_ich8lan) {
7409 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
7410 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
7412 phy_data |= IGP02E1000_PM_D0_LPLU;
7413 ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_data);
7418 /* When LPLU is enabled we should disable SmartSpeed */
7419 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data);
7423 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
7424 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, phy_data);
7429 return E1000_SUCCESS;
7432 /******************************************************************************
7433 * Change VCO speed register to improve Bit Error Rate performance of SERDES.
7435 * hw - Struct containing variables accessed by shared code
7436 *****************************************************************************/
7438 e1000_set_vco_speed(struct e1000_hw *hw)
7441 uint16_t default_page = 0;
7444 DEBUGFUNC("e1000_set_vco_speed");
7446 switch (hw->mac_type) {
7447 case e1000_82545_rev_3:
7448 case e1000_82546_rev_3:
7451 return E1000_SUCCESS;
7454 /* Set PHY register 30, page 5, bit 8 to 0 */
7456 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, &default_page);
7460 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0005);
7464 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data);
7468 phy_data &= ~M88E1000_PHY_VCO_REG_BIT8;
7469 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data);
7473 /* Set PHY register 30, page 4, bit 11 to 1 */
7475 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0004);
7479 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data);
7483 phy_data |= M88E1000_PHY_VCO_REG_BIT11;
7484 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data);
7488 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, default_page);
7492 return E1000_SUCCESS;
7496 /*****************************************************************************
7497 * This function reads the cookie from ARC ram.
7499 * returns: - E1000_SUCCESS .
7500 ****************************************************************************/
7502 e1000_host_if_read_cookie(struct e1000_hw * hw, uint8_t *buffer)
7505 uint32_t offset = E1000_MNG_DHCP_COOKIE_OFFSET;
7506 uint8_t length = E1000_MNG_DHCP_COOKIE_LENGTH;
7508 length = (length >> 2);
7509 offset = (offset >> 2);
7511 for (i = 0; i < length; i++) {
7512 *((uint32_t *) buffer + i) =
7513 E1000_READ_REG_ARRAY_DWORD(hw, HOST_IF, offset + i);
7515 return E1000_SUCCESS;
7519 /*****************************************************************************
7520 * This function checks whether the HOST IF is enabled for command operaton
7521 * and also checks whether the previous command is completed.
7522 * It busy waits in case of previous command is not completed.
7524 * returns: - E1000_ERR_HOST_INTERFACE_COMMAND in case if is not ready or
7526 * - E1000_SUCCESS for success.
7527 ****************************************************************************/
7529 e1000_mng_enable_host_if(struct e1000_hw * hw)
7534 /* Check that the host interface is enabled. */
7535 hicr = E1000_READ_REG(hw, HICR);
7536 if ((hicr & E1000_HICR_EN) == 0) {
7537 DEBUGOUT("E1000_HOST_EN bit disabled.\n");
7538 return -E1000_ERR_HOST_INTERFACE_COMMAND;
7540 /* check the previous command is completed */
7541 for (i = 0; i < E1000_MNG_DHCP_COMMAND_TIMEOUT; i++) {
7542 hicr = E1000_READ_REG(hw, HICR);
7543 if (!(hicr & E1000_HICR_C))
7548 if (i == E1000_MNG_DHCP_COMMAND_TIMEOUT) {
7549 DEBUGOUT("Previous command timeout failed .\n");
7550 return -E1000_ERR_HOST_INTERFACE_COMMAND;
7552 return E1000_SUCCESS;
7555 /*****************************************************************************
7556 * This function writes the buffer content at the offset given on the host if.
7557 * It also does alignment considerations to do the writes in most efficient way.
7558 * Also fills up the sum of the buffer in *buffer parameter.
7560 * returns - E1000_SUCCESS for success.
7561 ****************************************************************************/
7563 e1000_mng_host_if_write(struct e1000_hw * hw, uint8_t *buffer,
7564 uint16_t length, uint16_t offset, uint8_t *sum)
7567 uint8_t *bufptr = buffer;
7569 uint16_t remaining, i, j, prev_bytes;
7571 /* sum = only sum of the data and it is not checksum */
7573 if (length == 0 || offset + length > E1000_HI_MAX_MNG_DATA_LENGTH) {
7574 return -E1000_ERR_PARAM;
7577 tmp = (uint8_t *)&data;
7578 prev_bytes = offset & 0x3;
7583 data = E1000_READ_REG_ARRAY_DWORD(hw, HOST_IF, offset);
7584 for (j = prev_bytes; j < sizeof(uint32_t); j++) {
7585 *(tmp + j) = *bufptr++;
7588 E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, offset, data);
7589 length -= j - prev_bytes;
7593 remaining = length & 0x3;
7594 length -= remaining;
7596 /* Calculate length in DWORDs */
7599 /* The device driver writes the relevant command block into the
7601 for (i = 0; i < length; i++) {
7602 for (j = 0; j < sizeof(uint32_t); j++) {
7603 *(tmp + j) = *bufptr++;
7607 E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, offset + i, data);
7610 for (j = 0; j < sizeof(uint32_t); j++) {
7612 *(tmp + j) = *bufptr++;
7618 E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, offset + i, data);
7621 return E1000_SUCCESS;
7625 /*****************************************************************************
7626 * This function writes the command header after does the checksum calculation.
7628 * returns - E1000_SUCCESS for success.
7629 ****************************************************************************/
7631 e1000_mng_write_cmd_header(struct e1000_hw * hw,
7632 struct e1000_host_mng_command_header * hdr)
7638 /* Write the whole command header structure which includes sum of
7641 uint16_t length = sizeof(struct e1000_host_mng_command_header);
7643 sum = hdr->checksum;
7646 buffer = (uint8_t *) hdr;
7651 hdr->checksum = 0 - sum;
7654 /* The device driver writes the relevant command block into the ram area. */
7655 for (i = 0; i < length; i++) {
7656 E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, i, *((uint32_t *) hdr + i));
7657 E1000_WRITE_FLUSH(hw);
7660 return E1000_SUCCESS;
7664 /*****************************************************************************
7665 * This function indicates to ARC that a new command is pending which completes
7666 * one write operation by the driver.
7668 * returns - E1000_SUCCESS for success.
7669 ****************************************************************************/
7671 e1000_mng_write_commit(struct e1000_hw * hw)
7675 hicr = E1000_READ_REG(hw, HICR);
7676 /* Setting this bit tells the ARC that a new command is pending. */
7677 E1000_WRITE_REG(hw, HICR, hicr | E1000_HICR_C);
7679 return E1000_SUCCESS;
7683 /*****************************************************************************
7684 * This function checks the mode of the firmware.
7686 * returns - TRUE when the mode is IAMT or FALSE.
7687 ****************************************************************************/
7689 e1000_check_mng_mode(struct e1000_hw *hw)
7693 fwsm = E1000_READ_REG(hw, FWSM);
7695 if (hw->mac_type == e1000_ich8lan) {
7696 if ((fwsm & E1000_FWSM_MODE_MASK) ==
7697 (E1000_MNG_ICH_IAMT_MODE << E1000_FWSM_MODE_SHIFT))
7699 } else if ((fwsm & E1000_FWSM_MODE_MASK) ==
7700 (E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT))
7707 /*****************************************************************************
7708 * This function writes the dhcp info .
7709 ****************************************************************************/
7711 e1000_mng_write_dhcp_info(struct e1000_hw * hw, uint8_t *buffer,
7715 struct e1000_host_mng_command_header hdr;
7717 hdr.command_id = E1000_MNG_DHCP_TX_PAYLOAD_CMD;
7718 hdr.command_length = length;
7723 ret_val = e1000_mng_enable_host_if(hw);
7724 if (ret_val == E1000_SUCCESS) {
7725 ret_val = e1000_mng_host_if_write(hw, buffer, length, sizeof(hdr),
7727 if (ret_val == E1000_SUCCESS) {
7728 ret_val = e1000_mng_write_cmd_header(hw, &hdr);
7729 if (ret_val == E1000_SUCCESS)
7730 ret_val = e1000_mng_write_commit(hw);
7737 /*****************************************************************************
7738 * This function calculates the checksum.
7740 * returns - checksum of buffer contents.
7741 ****************************************************************************/
7743 e1000_calculate_mng_checksum(char *buffer, uint32_t length)
7751 for (i=0; i < length; i++)
7754 return (uint8_t) (0 - sum);
7757 /*****************************************************************************
7758 * This function checks whether tx pkt filtering needs to be enabled or not.
7760 * returns - TRUE for packet filtering or FALSE.
7761 ****************************************************************************/
7763 e1000_enable_tx_pkt_filtering(struct e1000_hw *hw)
7765 /* called in init as well as watchdog timer functions */
7767 int32_t ret_val, checksum;
7768 boolean_t tx_filter = FALSE;
7769 struct e1000_host_mng_dhcp_cookie *hdr = &(hw->mng_cookie);
7770 uint8_t *buffer = (uint8_t *) &(hw->mng_cookie);
7772 if (e1000_check_mng_mode(hw)) {
7773 ret_val = e1000_mng_enable_host_if(hw);
7774 if (ret_val == E1000_SUCCESS) {
7775 ret_val = e1000_host_if_read_cookie(hw, buffer);
7776 if (ret_val == E1000_SUCCESS) {
7777 checksum = hdr->checksum;
7779 if ((hdr->signature == E1000_IAMT_SIGNATURE) &&
7780 checksum == e1000_calculate_mng_checksum((char *)buffer,
7781 E1000_MNG_DHCP_COOKIE_LENGTH)) {
7783 E1000_MNG_DHCP_COOKIE_STATUS_PARSING_SUPPORT)
7792 hw->tx_pkt_filtering = tx_filter;
7796 /******************************************************************************
7797 * Verifies the hardware needs to allow ARPs to be processed by the host
7799 * hw - Struct containing variables accessed by shared code
7801 * returns: - TRUE/FALSE
7803 *****************************************************************************/
7805 e1000_enable_mng_pass_thru(struct e1000_hw *hw)
7808 uint32_t fwsm, factps;
7810 if (hw->asf_firmware_present) {
7811 manc = E1000_READ_REG(hw, MANC);
7813 if (!(manc & E1000_MANC_RCV_TCO_EN) ||
7814 !(manc & E1000_MANC_EN_MAC_ADDR_FILTER))
7816 if (e1000_arc_subsystem_valid(hw) == TRUE) {
7817 fwsm = E1000_READ_REG(hw, FWSM);
7818 factps = E1000_READ_REG(hw, FACTPS);
7820 if (((fwsm & E1000_FWSM_MODE_MASK) ==
7821 (e1000_mng_mode_pt << E1000_FWSM_MODE_SHIFT)) &&
7822 (factps & E1000_FACTPS_MNGCG))
7825 if ((manc & E1000_MANC_SMBUS_EN) && !(manc & E1000_MANC_ASF_EN))
7832 e1000_polarity_reversal_workaround(struct e1000_hw *hw)
7835 uint16_t mii_status_reg;
7838 /* Polarity reversal workaround for forced 10F/10H links. */
7840 /* Disable the transmitter on the PHY */
7842 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019);
7845 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFFF);
7849 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000);
7853 /* This loop will early-out if the NO link condition has been met. */
7854 for (i = PHY_FORCE_TIME; i > 0; i--) {
7855 /* Read the MII Status Register and wait for Link Status bit
7859 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
7863 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
7867 if ((mii_status_reg & ~MII_SR_LINK_STATUS) == 0) break;
7871 /* Recommended delay time after link has been lost */
7874 /* Now we will re-enable th transmitter on the PHY */
7876 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019);
7880 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFF0);
7884 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFF00);
7888 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x0000);
7892 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000);
7896 /* This loop will early-out if the link condition has been met. */
7897 for (i = PHY_FORCE_TIME; i > 0; i--) {
7898 /* Read the MII Status Register and wait for Link Status bit
7902 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
7906 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
7910 if (mii_status_reg & MII_SR_LINK_STATUS) break;
7913 return E1000_SUCCESS;
7916 /***************************************************************************
7918 * Disables PCI-Express master access.
7920 * hw: Struct containing variables accessed by shared code
7924 ***************************************************************************/
7926 e1000_set_pci_express_master_disable(struct e1000_hw *hw)
7930 DEBUGFUNC("e1000_set_pci_express_master_disable");
7932 if (hw->bus_type != e1000_bus_type_pci_express)
7935 ctrl = E1000_READ_REG(hw, CTRL);
7936 ctrl |= E1000_CTRL_GIO_MASTER_DISABLE;
7937 E1000_WRITE_REG(hw, CTRL, ctrl);
7940 /*******************************************************************************
7942 * Disables PCI-Express master access and verifies there are no pending requests
7944 * hw: Struct containing variables accessed by shared code
7946 * returns: - E1000_ERR_MASTER_REQUESTS_PENDING if master disable bit hasn't
7947 * caused the master requests to be disabled.
7948 * E1000_SUCCESS master requests disabled.
7950 ******************************************************************************/
7952 e1000_disable_pciex_master(struct e1000_hw *hw)
7954 int32_t timeout = MASTER_DISABLE_TIMEOUT; /* 80ms */
7956 DEBUGFUNC("e1000_disable_pciex_master");
7958 if (hw->bus_type != e1000_bus_type_pci_express)
7959 return E1000_SUCCESS;
7961 e1000_set_pci_express_master_disable(hw);
7964 if (!(E1000_READ_REG(hw, STATUS) & E1000_STATUS_GIO_MASTER_ENABLE))
7972 DEBUGOUT("Master requests are pending.\n");
7973 return -E1000_ERR_MASTER_REQUESTS_PENDING;
7976 return E1000_SUCCESS;
7979 /*******************************************************************************
7981 * Check for EEPROM Auto Read bit done.
7983 * hw: Struct containing variables accessed by shared code
7985 * returns: - E1000_ERR_RESET if fail to reset MAC
7986 * E1000_SUCCESS at any other case.
7988 ******************************************************************************/
7990 e1000_get_auto_rd_done(struct e1000_hw *hw)
7992 int32_t timeout = AUTO_READ_DONE_TIMEOUT;
7994 DEBUGFUNC("e1000_get_auto_rd_done");
7996 switch (hw->mac_type) {
8003 case e1000_80003es2lan:
8006 if (E1000_READ_REG(hw, EECD) & E1000_EECD_AUTO_RD)
8013 DEBUGOUT("Auto read by HW from EEPROM has not completed.\n");
8014 return -E1000_ERR_RESET;
8019 /* PHY configuration from NVM just starts after EECD_AUTO_RD sets to high.
8020 * Need to wait for PHY configuration completion before accessing NVM
8022 if (hw->mac_type == e1000_82573)
8025 return E1000_SUCCESS;
8028 /***************************************************************************
8029 * Checks if the PHY configuration is done
8031 * hw: Struct containing variables accessed by shared code
8033 * returns: - E1000_ERR_RESET if fail to reset MAC
8034 * E1000_SUCCESS at any other case.
8036 ***************************************************************************/
8038 e1000_get_phy_cfg_done(struct e1000_hw *hw)
8040 int32_t timeout = PHY_CFG_TIMEOUT;
8041 uint32_t cfg_mask = E1000_EEPROM_CFG_DONE;
8043 DEBUGFUNC("e1000_get_phy_cfg_done");
8045 switch (hw->mac_type) {
8049 case e1000_80003es2lan:
8050 /* Separate *_CFG_DONE_* bit for each port */
8051 if (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)
8052 cfg_mask = E1000_EEPROM_CFG_DONE_PORT_1;
8057 if (E1000_READ_REG(hw, EEMNGCTL) & cfg_mask)
8064 DEBUGOUT("MNG configuration cycle has not completed.\n");
8065 return -E1000_ERR_RESET;
8070 return E1000_SUCCESS;
8073 /***************************************************************************
8075 * Using the combination of SMBI and SWESMBI semaphore bits when resetting
8076 * adapter or Eeprom access.
8078 * hw: Struct containing variables accessed by shared code
8080 * returns: - E1000_ERR_EEPROM if fail to access EEPROM.
8081 * E1000_SUCCESS at any other case.
8083 ***************************************************************************/
8085 e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw)
8090 DEBUGFUNC("e1000_get_hw_eeprom_semaphore");
8092 if (!hw->eeprom_semaphore_present)
8093 return E1000_SUCCESS;
8095 if (hw->mac_type == e1000_80003es2lan) {
8096 /* Get the SW semaphore. */
8097 if (e1000_get_software_semaphore(hw) != E1000_SUCCESS)
8098 return -E1000_ERR_EEPROM;
8101 /* Get the FW semaphore. */
8102 timeout = hw->eeprom.word_size + 1;
8104 swsm = E1000_READ_REG(hw, SWSM);
8105 swsm |= E1000_SWSM_SWESMBI;
8106 E1000_WRITE_REG(hw, SWSM, swsm);
8107 /* if we managed to set the bit we got the semaphore. */
8108 swsm = E1000_READ_REG(hw, SWSM);
8109 if (swsm & E1000_SWSM_SWESMBI)
8117 /* Release semaphores */
8118 e1000_put_hw_eeprom_semaphore(hw);
8119 DEBUGOUT("Driver can't access the Eeprom - SWESMBI bit is set.\n");
8120 return -E1000_ERR_EEPROM;
8123 return E1000_SUCCESS;
8126 /***************************************************************************
8127 * This function clears HW semaphore bits.
8129 * hw: Struct containing variables accessed by shared code
8133 ***************************************************************************/
8135 e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw)
8139 DEBUGFUNC("e1000_put_hw_eeprom_semaphore");
8141 if (!hw->eeprom_semaphore_present)
8144 swsm = E1000_READ_REG(hw, SWSM);
8145 if (hw->mac_type == e1000_80003es2lan) {
8146 /* Release both semaphores. */
8147 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
8149 swsm &= ~(E1000_SWSM_SWESMBI);
8150 E1000_WRITE_REG(hw, SWSM, swsm);
8153 /***************************************************************************
8155 * Obtaining software semaphore bit (SMBI) before resetting PHY.
8157 * hw: Struct containing variables accessed by shared code
8159 * returns: - E1000_ERR_RESET if fail to obtain semaphore.
8160 * E1000_SUCCESS at any other case.
8162 ***************************************************************************/
8164 e1000_get_software_semaphore(struct e1000_hw *hw)
8166 int32_t timeout = hw->eeprom.word_size + 1;
8169 DEBUGFUNC("e1000_get_software_semaphore");
8171 if (hw->mac_type != e1000_80003es2lan) {
8172 return E1000_SUCCESS;
8176 swsm = E1000_READ_REG(hw, SWSM);
8177 /* If SMBI bit cleared, it is now set and we hold the semaphore */
8178 if (!(swsm & E1000_SWSM_SMBI))
8185 DEBUGOUT("Driver can't access device - SMBI bit is set.\n");
8186 return -E1000_ERR_RESET;
8189 return E1000_SUCCESS;
8192 /***************************************************************************
8194 * Release semaphore bit (SMBI).
8196 * hw: Struct containing variables accessed by shared code
8198 ***************************************************************************/
8200 e1000_release_software_semaphore(struct e1000_hw *hw)
8204 DEBUGFUNC("e1000_release_software_semaphore");
8206 if (hw->mac_type != e1000_80003es2lan) {
8210 swsm = E1000_READ_REG(hw, SWSM);
8211 /* Release the SW semaphores.*/
8212 swsm &= ~E1000_SWSM_SMBI;
8213 E1000_WRITE_REG(hw, SWSM, swsm);
8216 /******************************************************************************
8217 * Checks if PHY reset is blocked due to SOL/IDER session, for example.
8218 * Returning E1000_BLK_PHY_RESET isn't necessarily an error. But it's up to
8219 * the caller to figure out how to deal with it.
8221 * hw - Struct containing variables accessed by shared code
8223 * returns: - E1000_BLK_PHY_RESET
8226 *****************************************************************************/
8228 e1000_check_phy_reset_block(struct e1000_hw *hw)
8233 if (hw->mac_type == e1000_ich8lan) {
8234 fwsm = E1000_READ_REG(hw, FWSM);
8235 return (fwsm & E1000_FWSM_RSPCIPHY) ? E1000_SUCCESS
8236 : E1000_BLK_PHY_RESET;
8239 if (hw->mac_type > e1000_82547_rev_2)
8240 manc = E1000_READ_REG(hw, MANC);
8241 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ?
8242 E1000_BLK_PHY_RESET : E1000_SUCCESS;
8246 e1000_arc_subsystem_valid(struct e1000_hw *hw)
8250 /* On 8257x silicon, registers in the range of 0x8800 - 0x8FFC
8251 * may not be provided a DMA clock when no manageability features are
8252 * enabled. We do not want to perform any reads/writes to these registers
8253 * if this is the case. We read FWSM to determine the manageability mode.
8255 switch (hw->mac_type) {
8259 case e1000_80003es2lan:
8260 fwsm = E1000_READ_REG(hw, FWSM);
8261 if ((fwsm & E1000_FWSM_MODE_MASK) != 0)
8273 /******************************************************************************
8274 * Configure PCI-Ex no-snoop
8276 * hw - Struct containing variables accessed by shared code.
8277 * no_snoop - Bitmap of no-snoop events.
8279 * returns: E1000_SUCCESS
8281 *****************************************************************************/
8283 e1000_set_pci_ex_no_snoop(struct e1000_hw *hw, uint32_t no_snoop)
8285 uint32_t gcr_reg = 0;
8287 DEBUGFUNC("e1000_set_pci_ex_no_snoop");
8289 if (hw->bus_type == e1000_bus_type_unknown)
8290 e1000_get_bus_info(hw);
8292 if (hw->bus_type != e1000_bus_type_pci_express)
8293 return E1000_SUCCESS;
8296 gcr_reg = E1000_READ_REG(hw, GCR);
8297 gcr_reg &= ~(PCI_EX_NO_SNOOP_ALL);
8298 gcr_reg |= no_snoop;
8299 E1000_WRITE_REG(hw, GCR, gcr_reg);
8301 if (hw->mac_type == e1000_ich8lan) {
8304 E1000_WRITE_REG(hw, GCR, PCI_EX_82566_SNOOP_ALL);
8306 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
8307 ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
8308 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
8311 return E1000_SUCCESS;
8314 /***************************************************************************
8316 * Get software semaphore FLAG bit (SWFLAG).
8317 * SWFLAG is used to synchronize the access to all shared resource between
8320 * hw: Struct containing variables accessed by shared code
8322 ***************************************************************************/
8324 e1000_get_software_flag(struct e1000_hw *hw)
8326 int32_t timeout = PHY_CFG_TIMEOUT;
8327 uint32_t extcnf_ctrl;
8329 DEBUGFUNC("e1000_get_software_flag");
8331 if (hw->mac_type == e1000_ich8lan) {
8333 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL);
8334 extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
8335 E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl);
8337 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL);
8338 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
8345 DEBUGOUT("FW or HW locks the resource too long.\n");
8346 return -E1000_ERR_CONFIG;
8350 return E1000_SUCCESS;
8353 /***************************************************************************
8355 * Release software semaphore FLAG bit (SWFLAG).
8356 * SWFLAG is used to synchronize the access to all shared resource between
8359 * hw: Struct containing variables accessed by shared code
8361 ***************************************************************************/
8363 e1000_release_software_flag(struct e1000_hw *hw)
8365 uint32_t extcnf_ctrl;
8367 DEBUGFUNC("e1000_release_software_flag");
8369 if (hw->mac_type == e1000_ich8lan) {
8370 extcnf_ctrl= E1000_READ_REG(hw, EXTCNF_CTRL);
8371 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
8372 E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl);
8378 /******************************************************************************
8379 * Reads a 16 bit word or words from the EEPROM using the ICH8's flash access
8382 * hw - Struct containing variables accessed by shared code
8383 * offset - offset of word in the EEPROM to read
8384 * data - word read from the EEPROM
8385 * words - number of words to read
8386 *****************************************************************************/
8388 e1000_read_eeprom_ich8(struct e1000_hw *hw, uint16_t offset, uint16_t words,
8391 int32_t error = E1000_SUCCESS;
8392 uint32_t flash_bank = 0;
8393 uint32_t act_offset = 0;
8394 uint32_t bank_offset = 0;
8398 /* We need to know which is the valid flash bank. In the event
8399 * that we didn't allocate eeprom_shadow_ram, we may not be
8400 * managing flash_bank. So it cannot be trusted and needs
8401 * to be updated with each read.
8403 /* Value of bit 22 corresponds to the flash bank we're on. */
8404 flash_bank = (E1000_READ_REG(hw, EECD) & E1000_EECD_SEC1VAL) ? 1 : 0;
8406 /* Adjust offset appropriately if we're on bank 1 - adjust for word size */
8407 bank_offset = flash_bank * (hw->flash_bank_size * 2);
8409 error = e1000_get_software_flag(hw);
8410 if (error != E1000_SUCCESS)
8413 for (i = 0; i < words; i++) {
8414 if (hw->eeprom_shadow_ram != NULL &&
8415 hw->eeprom_shadow_ram[offset+i].modified == TRUE) {
8416 data[i] = hw->eeprom_shadow_ram[offset+i].eeprom_word;
8418 /* The NVM part needs a byte offset, hence * 2 */
8419 act_offset = bank_offset + ((offset + i) * 2);
8420 error = e1000_read_ich8_word(hw, act_offset, &word);
8421 if (error != E1000_SUCCESS)
8427 e1000_release_software_flag(hw);
8432 /******************************************************************************
8433 * Writes a 16 bit word or words to the EEPROM using the ICH8's flash access
8434 * register. Actually, writes are written to the shadow ram cache in the hw
8435 * structure hw->e1000_shadow_ram. e1000_commit_shadow_ram flushes this to
8436 * the NVM, which occurs when the NVM checksum is updated.
8438 * hw - Struct containing variables accessed by shared code
8439 * offset - offset of word in the EEPROM to write
8440 * words - number of words to write
8441 * data - words to write to the EEPROM
8442 *****************************************************************************/
8444 e1000_write_eeprom_ich8(struct e1000_hw *hw, uint16_t offset, uint16_t words,
8448 int32_t error = E1000_SUCCESS;
8450 error = e1000_get_software_flag(hw);
8451 if (error != E1000_SUCCESS)
8454 /* A driver can write to the NVM only if it has eeprom_shadow_ram
8455 * allocated. Subsequent reads to the modified words are read from
8456 * this cached structure as well. Writes will only go into this
8457 * cached structure unless it's followed by a call to
8458 * e1000_update_eeprom_checksum() where it will commit the changes
8459 * and clear the "modified" field.
8461 if (hw->eeprom_shadow_ram != NULL) {
8462 for (i = 0; i < words; i++) {
8463 if ((offset + i) < E1000_SHADOW_RAM_WORDS) {
8464 hw->eeprom_shadow_ram[offset+i].modified = TRUE;
8465 hw->eeprom_shadow_ram[offset+i].eeprom_word = data[i];
8467 error = -E1000_ERR_EEPROM;
8472 /* Drivers have the option to not allocate eeprom_shadow_ram as long
8473 * as they don't perform any NVM writes. An attempt in doing so
8474 * will result in this error.
8476 error = -E1000_ERR_EEPROM;
8479 e1000_release_software_flag(hw);
8484 /******************************************************************************
8485 * This function does initial flash setup so that a new read/write/erase cycle
8488 * hw - The pointer to the hw structure
8489 ****************************************************************************/
8491 e1000_ich8_cycle_init(struct e1000_hw *hw)
8493 union ich8_hws_flash_status hsfsts;
8494 int32_t error = E1000_ERR_EEPROM;
8497 DEBUGFUNC("e1000_ich8_cycle_init");
8499 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
8501 /* May be check the Flash Des Valid bit in Hw status */
8502 if (hsfsts.hsf_status.fldesvalid == 0) {
8503 DEBUGOUT("Flash descriptor invalid. SW Sequencing must be used.");
8507 /* Clear FCERR in Hw status by writing 1 */
8508 /* Clear DAEL in Hw status by writing a 1 */
8509 hsfsts.hsf_status.flcerr = 1;
8510 hsfsts.hsf_status.dael = 1;
8512 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval);
8514 /* Either we should have a hardware SPI cycle in progress bit to check
8515 * against, in order to start a new cycle or FDONE bit should be changed
8516 * in the hardware so that it is 1 after harware reset, which can then be
8517 * used as an indication whether a cycle is in progress or has been
8518 * completed .. we should also have some software semaphore mechanism to
8519 * guard FDONE or the cycle in progress bit so that two threads access to
8520 * those bits can be sequentiallized or a way so that 2 threads dont
8521 * start the cycle at the same time */
8523 if (hsfsts.hsf_status.flcinprog == 0) {
8524 /* There is no cycle running at present, so we can start a cycle */
8525 /* Begin by setting Flash Cycle Done. */
8526 hsfsts.hsf_status.flcdone = 1;
8527 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval);
8528 error = E1000_SUCCESS;
8530 /* otherwise poll for sometime so the current cycle has a chance
8531 * to end before giving up. */
8532 for (i = 0; i < ICH_FLASH_COMMAND_TIMEOUT; i++) {
8533 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
8534 if (hsfsts.hsf_status.flcinprog == 0) {
8535 error = E1000_SUCCESS;
8540 if (error == E1000_SUCCESS) {
8541 /* Successful in waiting for previous cycle to timeout,
8542 * now set the Flash Cycle Done. */
8543 hsfsts.hsf_status.flcdone = 1;
8544 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval);
8546 DEBUGOUT("Flash controller busy, cannot get access");
8552 /******************************************************************************
8553 * This function starts a flash cycle and waits for its completion
8555 * hw - The pointer to the hw structure
8556 ****************************************************************************/
8558 e1000_ich8_flash_cycle(struct e1000_hw *hw, uint32_t timeout)
8560 union ich8_hws_flash_ctrl hsflctl;
8561 union ich8_hws_flash_status hsfsts;
8562 int32_t error = E1000_ERR_EEPROM;
8565 /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
8566 hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
8567 hsflctl.hsf_ctrl.flcgo = 1;
8568 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
8570 /* wait till FDONE bit is set to 1 */
8572 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
8573 if (hsfsts.hsf_status.flcdone == 1)
8577 } while (i < timeout);
8578 if (hsfsts.hsf_status.flcdone == 1 && hsfsts.hsf_status.flcerr == 0) {
8579 error = E1000_SUCCESS;
8584 /******************************************************************************
8585 * Reads a byte or word from the NVM using the ICH8 flash access registers.
8587 * hw - The pointer to the hw structure
8588 * index - The index of the byte or word to read.
8589 * size - Size of data to read, 1=byte 2=word
8590 * data - Pointer to the word to store the value read.
8591 *****************************************************************************/
8593 e1000_read_ich8_data(struct e1000_hw *hw, uint32_t index,
8594 uint32_t size, uint16_t* data)
8596 union ich8_hws_flash_status hsfsts;
8597 union ich8_hws_flash_ctrl hsflctl;
8598 uint32_t flash_linear_address;
8599 uint32_t flash_data = 0;
8600 int32_t error = -E1000_ERR_EEPROM;
8603 DEBUGFUNC("e1000_read_ich8_data");
8605 if (size < 1 || size > 2 || data == 0x0 ||
8606 index > ICH_FLASH_LINEAR_ADDR_MASK)
8609 flash_linear_address = (ICH_FLASH_LINEAR_ADDR_MASK & index) +
8610 hw->flash_base_addr;
8615 error = e1000_ich8_cycle_init(hw);
8616 if (error != E1000_SUCCESS)
8619 hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
8620 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
8621 hsflctl.hsf_ctrl.fldbcount = size - 1;
8622 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
8623 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
8625 /* Write the last 24 bits of index into Flash Linear address field in
8627 /* TODO: TBD maybe check the index against the size of flash */
8629 E1000_WRITE_ICH_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_address);
8631 error = e1000_ich8_flash_cycle(hw, ICH_FLASH_COMMAND_TIMEOUT);
8633 /* Check if FCERR is set to 1, if set to 1, clear it and try the whole
8634 * sequence a few more times, else read in (shift in) the Flash Data0,
8635 * the order is least significant byte first msb to lsb */
8636 if (error == E1000_SUCCESS) {
8637 flash_data = E1000_READ_ICH_FLASH_REG(hw, ICH_FLASH_FDATA0);
8639 *data = (uint8_t)(flash_data & 0x000000FF);
8640 } else if (size == 2) {
8641 *data = (uint16_t)(flash_data & 0x0000FFFF);
8645 /* If we've gotten here, then things are probably completely hosed,
8646 * but if the error condition is detected, it won't hurt to give
8647 * it another try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
8649 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
8650 if (hsfsts.hsf_status.flcerr == 1) {
8651 /* Repeat for some time before giving up. */
8653 } else if (hsfsts.hsf_status.flcdone == 0) {
8654 DEBUGOUT("Timeout error - flash cycle did not complete.");
8658 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
8663 /******************************************************************************
8664 * Writes One /two bytes to the NVM using the ICH8 flash access registers.
8666 * hw - The pointer to the hw structure
8667 * index - The index of the byte/word to read.
8668 * size - Size of data to read, 1=byte 2=word
8669 * data - The byte(s) to write to the NVM.
8670 *****************************************************************************/
8672 e1000_write_ich8_data(struct e1000_hw *hw, uint32_t index, uint32_t size,
8675 union ich8_hws_flash_status hsfsts;
8676 union ich8_hws_flash_ctrl hsflctl;
8677 uint32_t flash_linear_address;
8678 uint32_t flash_data = 0;
8679 int32_t error = -E1000_ERR_EEPROM;
8682 DEBUGFUNC("e1000_write_ich8_data");
8684 if (size < 1 || size > 2 || data > size * 0xff ||
8685 index > ICH_FLASH_LINEAR_ADDR_MASK)
8688 flash_linear_address = (ICH_FLASH_LINEAR_ADDR_MASK & index) +
8689 hw->flash_base_addr;
8694 error = e1000_ich8_cycle_init(hw);
8695 if (error != E1000_SUCCESS)
8698 hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
8699 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
8700 hsflctl.hsf_ctrl.fldbcount = size -1;
8701 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
8702 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
8704 /* Write the last 24 bits of index into Flash Linear address field in
8706 E1000_WRITE_ICH_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_address);
8709 flash_data = (uint32_t)data & 0x00FF;
8711 flash_data = (uint32_t)data;
8713 E1000_WRITE_ICH_FLASH_REG(hw, ICH_FLASH_FDATA0, flash_data);
8715 /* check if FCERR is set to 1 , if set to 1, clear it and try the whole
8716 * sequence a few more times else done */
8717 error = e1000_ich8_flash_cycle(hw, ICH_FLASH_COMMAND_TIMEOUT);
8718 if (error == E1000_SUCCESS) {
8721 /* If we're here, then things are most likely completely hosed,
8722 * but if the error condition is detected, it won't hurt to give
8723 * it another try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
8725 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
8726 if (hsfsts.hsf_status.flcerr == 1) {
8727 /* Repeat for some time before giving up. */
8729 } else if (hsfsts.hsf_status.flcdone == 0) {
8730 DEBUGOUT("Timeout error - flash cycle did not complete.");
8734 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
8739 /******************************************************************************
8740 * Reads a single byte from the NVM using the ICH8 flash access registers.
8742 * hw - pointer to e1000_hw structure
8743 * index - The index of the byte to read.
8744 * data - Pointer to a byte to store the value read.
8745 *****************************************************************************/
8747 e1000_read_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t* data)
8749 int32_t status = E1000_SUCCESS;
8752 status = e1000_read_ich8_data(hw, index, 1, &word);
8753 if (status == E1000_SUCCESS) {
8754 *data = (uint8_t)word;
8760 /******************************************************************************
8761 * Writes a single byte to the NVM using the ICH8 flash access registers.
8762 * Performs verification by reading back the value and then going through
8763 * a retry algorithm before giving up.
8765 * hw - pointer to e1000_hw structure
8766 * index - The index of the byte to write.
8767 * byte - The byte to write to the NVM.
8768 *****************************************************************************/
8770 e1000_verify_write_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t byte)
8772 int32_t error = E1000_SUCCESS;
8773 int32_t program_retries = 0;
8775 DEBUGOUT2("Byte := %2.2X Offset := %d\n", byte, index);
8777 error = e1000_write_ich8_byte(hw, index, byte);
8779 if (error != E1000_SUCCESS) {
8780 for (program_retries = 0; program_retries < 100; program_retries++) {
8781 DEBUGOUT2("Retrying \t Byte := %2.2X Offset := %d\n", byte, index);
8782 error = e1000_write_ich8_byte(hw, index, byte);
8784 if (error == E1000_SUCCESS)
8789 if (program_retries == 100)
8790 error = E1000_ERR_EEPROM;
8795 /******************************************************************************
8796 * Writes a single byte to the NVM using the ICH8 flash access registers.
8798 * hw - pointer to e1000_hw structure
8799 * index - The index of the byte to read.
8800 * data - The byte to write to the NVM.
8801 *****************************************************************************/
8803 e1000_write_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t data)
8805 int32_t status = E1000_SUCCESS;
8806 uint16_t word = (uint16_t)data;
8808 status = e1000_write_ich8_data(hw, index, 1, word);
8813 /******************************************************************************
8814 * Reads a word from the NVM using the ICH8 flash access registers.
8816 * hw - pointer to e1000_hw structure
8817 * index - The starting byte index of the word to read.
8818 * data - Pointer to a word to store the value read.
8819 *****************************************************************************/
8821 e1000_read_ich8_word(struct e1000_hw *hw, uint32_t index, uint16_t *data)
8823 int32_t status = E1000_SUCCESS;
8824 status = e1000_read_ich8_data(hw, index, 2, data);
8828 /******************************************************************************
8829 * Erases the bank specified. Each bank may be a 4, 8 or 64k block. Banks are 0
8832 * hw - pointer to e1000_hw structure
8833 * bank - 0 for first bank, 1 for second bank
8835 * Note that this function may actually erase as much as 8 or 64 KBytes. The
8836 * amount of NVM used in each bank is a *minimum* of 4 KBytes, but in fact the
8837 * bank size may be 4, 8 or 64 KBytes
8838 *****************************************************************************/
8840 e1000_erase_ich8_4k_segment(struct e1000_hw *hw, uint32_t bank)
8842 union ich8_hws_flash_status hsfsts;
8843 union ich8_hws_flash_ctrl hsflctl;
8844 uint32_t flash_linear_address;
8846 int32_t error = E1000_ERR_EEPROM;
8848 int32_t sub_sector_size = 0;
8851 int32_t error_flag = 0;
8853 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
8855 /* Determine HW Sector size: Read BERASE bits of Hw flash Status register */
8856 /* 00: The Hw sector is 256 bytes, hence we need to erase 16
8857 * consecutive sectors. The start index for the nth Hw sector can be
8858 * calculated as bank * 4096 + n * 256
8859 * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
8860 * The start index for the nth Hw sector can be calculated
8862 * 10: The HW sector is 8K bytes
8863 * 11: The Hw sector size is 64K bytes */
8864 if (hsfsts.hsf_status.berasesz == 0x0) {
8865 /* Hw sector size 256 */
8866 sub_sector_size = ICH_FLASH_SEG_SIZE_256;
8867 bank_size = ICH_FLASH_SECTOR_SIZE;
8868 iteration = ICH_FLASH_SECTOR_SIZE / ICH_FLASH_SEG_SIZE_256;
8869 } else if (hsfsts.hsf_status.berasesz == 0x1) {
8870 bank_size = ICH_FLASH_SEG_SIZE_4K;
8872 } else if (hsfsts.hsf_status.berasesz == 0x3) {
8873 bank_size = ICH_FLASH_SEG_SIZE_64K;
8879 for (j = 0; j < iteration ; j++) {
8883 error = e1000_ich8_cycle_init(hw);
8884 if (error != E1000_SUCCESS) {
8889 /* Write a value 11 (block Erase) in Flash Cycle field in Hw flash
8891 hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
8892 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
8893 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
8895 /* Write the last 24 bits of an index within the block into Flash
8896 * Linear address field in Flash Address. This probably needs to
8897 * be calculated here based off the on-chip erase sector size and
8898 * the software bank size (4, 8 or 64 KBytes) */
8899 flash_linear_address = bank * bank_size + j * sub_sector_size;
8900 flash_linear_address += hw->flash_base_addr;
8901 flash_linear_address &= ICH_FLASH_LINEAR_ADDR_MASK;
8903 E1000_WRITE_ICH_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_address);
8905 error = e1000_ich8_flash_cycle(hw, ICH_FLASH_ERASE_TIMEOUT);
8906 /* Check if FCERR is set to 1. If 1, clear it and try the whole
8907 * sequence a few more times else Done */
8908 if (error == E1000_SUCCESS) {
8911 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
8912 if (hsfsts.hsf_status.flcerr == 1) {
8913 /* repeat for some time before giving up */
8915 } else if (hsfsts.hsf_status.flcdone == 0) {
8920 } while ((count < ICH_FLASH_CYCLE_REPEAT_COUNT) && !error_flag);
8921 if (error_flag == 1)
8924 if (error_flag != 1)
8925 error = E1000_SUCCESS;
8930 e1000_init_lcd_from_nvm_config_region(struct e1000_hw *hw,
8931 uint32_t cnf_base_addr, uint32_t cnf_size)
8933 uint32_t ret_val = E1000_SUCCESS;
8934 uint16_t word_addr, reg_data, reg_addr;
8937 /* cnf_base_addr is in DWORD */
8938 word_addr = (uint16_t)(cnf_base_addr << 1);
8940 /* cnf_size is returned in size of dwords */
8941 for (i = 0; i < cnf_size; i++) {
8942 ret_val = e1000_read_eeprom(hw, (word_addr + i*2), 1, ®_data);
8946 ret_val = e1000_read_eeprom(hw, (word_addr + i*2 + 1), 1, ®_addr);
8950 ret_val = e1000_get_software_flag(hw);
8951 if (ret_val != E1000_SUCCESS)
8954 ret_val = e1000_write_phy_reg_ex(hw, (uint32_t)reg_addr, reg_data);
8956 e1000_release_software_flag(hw);
8963 /******************************************************************************
8964 * This function initializes the PHY from the NVM on ICH8 platforms. This
8965 * is needed due to an issue where the NVM configuration is not properly
8966 * autoloaded after power transitions. Therefore, after each PHY reset, we
8967 * will load the configuration data out of the NVM manually.
8969 * hw: Struct containing variables accessed by shared code
8970 *****************************************************************************/
8972 e1000_init_lcd_from_nvm(struct e1000_hw *hw)
8974 uint32_t reg_data, cnf_base_addr, cnf_size, ret_val, loop;
8976 if (hw->phy_type != e1000_phy_igp_3)
8977 return E1000_SUCCESS;
8979 /* Check if SW needs configure the PHY */
8980 reg_data = E1000_READ_REG(hw, FEXTNVM);
8981 if (!(reg_data & FEXTNVM_SW_CONFIG))
8982 return E1000_SUCCESS;
8984 /* Wait for basic configuration completes before proceeding*/
8987 reg_data = E1000_READ_REG(hw, STATUS) & E1000_STATUS_LAN_INIT_DONE;
8990 } while ((!reg_data) && (loop < 50));
8992 /* Clear the Init Done bit for the next init event */
8993 reg_data = E1000_READ_REG(hw, STATUS);
8994 reg_data &= ~E1000_STATUS_LAN_INIT_DONE;
8995 E1000_WRITE_REG(hw, STATUS, reg_data);
8997 /* Make sure HW does not configure LCD from PHY extended configuration
8998 before SW configuration */
8999 reg_data = E1000_READ_REG(hw, EXTCNF_CTRL);
9000 if ((reg_data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE) == 0x0000) {
9001 reg_data = E1000_READ_REG(hw, EXTCNF_SIZE);
9002 cnf_size = reg_data & E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH;
9005 reg_data = E1000_READ_REG(hw, EXTCNF_CTRL);
9006 cnf_base_addr = reg_data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER;
9007 /* cnf_base_addr is in DWORD */
9008 cnf_base_addr >>= 16;
9010 /* Configure LCD from extended configuration region. */
9011 ret_val = e1000_init_lcd_from_nvm_config_region(hw, cnf_base_addr,
9018 return E1000_SUCCESS;