2 * Driver for Marvell Discovery (MV643XX) and Marvell Orion ethernet ports
3 * Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com>
5 * Based on the 64360 driver from:
6 * Copyright (C) 2002 Rabeeh Khoury <rabeeh@galileo.co.il>
7 * Rabeeh Khoury <rabeeh@marvell.com>
9 * Copyright (C) 2003 PMC-Sierra, Inc.,
10 * written by Manish Lachwani
12 * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org>
14 * Copyright (C) 2004-2006 MontaVista Software, Inc.
15 * Dale Farnsworth <dale@farnsworth.org>
17 * Copyright (C) 2004 Steven J. Hill <sjhill1@rockwellcollins.com>
18 * <sjhill@realitydiluted.com>
20 * Copyright (C) 2007-2008 Marvell Semiconductor
21 * Lennert Buytenhek <buytenh@marvell.com>
23 * This program is free software; you can redistribute it and/or
24 * modify it under the terms of the GNU General Public License
25 * as published by the Free Software Foundation; either version 2
26 * of the License, or (at your option) any later version.
28 * This program is distributed in the hope that it will be useful,
29 * but WITHOUT ANY WARRANTY; without even the implied warranty of
30 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
31 * GNU General Public License for more details.
33 * You should have received a copy of the GNU General Public License
34 * along with this program; if not, write to the Free Software
35 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
38 #include <linux/init.h>
39 #include <linux/dma-mapping.h>
42 #include <linux/tcp.h>
43 #include <linux/udp.h>
44 #include <linux/etherdevice.h>
45 #include <linux/delay.h>
46 #include <linux/ethtool.h>
47 #include <linux/platform_device.h>
48 #include <linux/module.h>
49 #include <linux/kernel.h>
50 #include <linux/spinlock.h>
51 #include <linux/workqueue.h>
52 #include <linux/phy.h>
53 #include <linux/mv643xx_eth.h>
55 #include <linux/types.h>
56 #include <asm/system.h>
58 static char mv643xx_eth_driver_name[] = "mv643xx_eth";
59 static char mv643xx_eth_driver_version[] = "1.4";
63 * Registers shared between all ports.
65 #define PHY_ADDR 0x0000
66 #define SMI_REG 0x0004
67 #define SMI_BUSY 0x10000000
68 #define SMI_READ_VALID 0x08000000
69 #define SMI_OPCODE_READ 0x04000000
70 #define SMI_OPCODE_WRITE 0x00000000
71 #define ERR_INT_CAUSE 0x0080
72 #define ERR_INT_SMI_DONE 0x00000010
73 #define ERR_INT_MASK 0x0084
74 #define WINDOW_BASE(w) (0x0200 + ((w) << 3))
75 #define WINDOW_SIZE(w) (0x0204 + ((w) << 3))
76 #define WINDOW_REMAP_HIGH(w) (0x0280 + ((w) << 2))
77 #define WINDOW_BAR_ENABLE 0x0290
78 #define WINDOW_PROTECT(w) (0x0294 + ((w) << 4))
81 * Main per-port registers. These live at offset 0x0400 for
82 * port #0, 0x0800 for port #1, and 0x0c00 for port #2.
84 #define PORT_CONFIG 0x0000
85 #define UNICAST_PROMISCUOUS_MODE 0x00000001
86 #define PORT_CONFIG_EXT 0x0004
87 #define MAC_ADDR_LOW 0x0014
88 #define MAC_ADDR_HIGH 0x0018
89 #define SDMA_CONFIG 0x001c
90 #define PORT_SERIAL_CONTROL 0x003c
91 #define PORT_STATUS 0x0044
92 #define TX_FIFO_EMPTY 0x00000400
93 #define TX_IN_PROGRESS 0x00000080
94 #define PORT_SPEED_MASK 0x00000030
95 #define PORT_SPEED_1000 0x00000010
96 #define PORT_SPEED_100 0x00000020
97 #define PORT_SPEED_10 0x00000000
98 #define FLOW_CONTROL_ENABLED 0x00000008
99 #define FULL_DUPLEX 0x00000004
100 #define LINK_UP 0x00000002
101 #define TXQ_COMMAND 0x0048
102 #define TXQ_FIX_PRIO_CONF 0x004c
103 #define TX_BW_RATE 0x0050
104 #define TX_BW_MTU 0x0058
105 #define TX_BW_BURST 0x005c
106 #define INT_CAUSE 0x0060
107 #define INT_TX_END 0x07f80000
108 #define INT_RX 0x000003fc
109 #define INT_EXT 0x00000002
110 #define INT_CAUSE_EXT 0x0064
111 #define INT_EXT_LINK_PHY 0x00110000
112 #define INT_EXT_TX 0x000000ff
113 #define INT_MASK 0x0068
114 #define INT_MASK_EXT 0x006c
115 #define TX_FIFO_URGENT_THRESHOLD 0x0074
116 #define TXQ_FIX_PRIO_CONF_MOVED 0x00dc
117 #define TX_BW_RATE_MOVED 0x00e0
118 #define TX_BW_MTU_MOVED 0x00e8
119 #define TX_BW_BURST_MOVED 0x00ec
120 #define RXQ_CURRENT_DESC_PTR(q) (0x020c + ((q) << 4))
121 #define RXQ_COMMAND 0x0280
122 #define TXQ_CURRENT_DESC_PTR(q) (0x02c0 + ((q) << 2))
123 #define TXQ_BW_TOKENS(q) (0x0300 + ((q) << 4))
124 #define TXQ_BW_CONF(q) (0x0304 + ((q) << 4))
125 #define TXQ_BW_WRR_CONF(q) (0x0308 + ((q) << 4))
128 * Misc per-port registers.
130 #define MIB_COUNTERS(p) (0x1000 + ((p) << 7))
131 #define SPECIAL_MCAST_TABLE(p) (0x1400 + ((p) << 10))
132 #define OTHER_MCAST_TABLE(p) (0x1500 + ((p) << 10))
133 #define UNICAST_TABLE(p) (0x1600 + ((p) << 10))
137 * SDMA configuration register.
139 #define RX_BURST_SIZE_16_64BIT (4 << 1)
140 #define BLM_RX_NO_SWAP (1 << 4)
141 #define BLM_TX_NO_SWAP (1 << 5)
142 #define TX_BURST_SIZE_16_64BIT (4 << 22)
144 #if defined(__BIG_ENDIAN)
145 #define PORT_SDMA_CONFIG_DEFAULT_VALUE \
146 (RX_BURST_SIZE_16_64BIT | \
147 TX_BURST_SIZE_16_64BIT)
148 #elif defined(__LITTLE_ENDIAN)
149 #define PORT_SDMA_CONFIG_DEFAULT_VALUE \
150 (RX_BURST_SIZE_16_64BIT | \
153 TX_BURST_SIZE_16_64BIT)
155 #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
160 * Port serial control register.
162 #define SET_MII_SPEED_TO_100 (1 << 24)
163 #define SET_GMII_SPEED_TO_1000 (1 << 23)
164 #define SET_FULL_DUPLEX_MODE (1 << 21)
165 #define MAX_RX_PACKET_9700BYTE (5 << 17)
166 #define DISABLE_AUTO_NEG_SPEED_GMII (1 << 13)
167 #define DO_NOT_FORCE_LINK_FAIL (1 << 10)
168 #define SERIAL_PORT_CONTROL_RESERVED (1 << 9)
169 #define DISABLE_AUTO_NEG_FOR_FLOW_CTRL (1 << 3)
170 #define DISABLE_AUTO_NEG_FOR_DUPLEX (1 << 2)
171 #define FORCE_LINK_PASS (1 << 1)
172 #define SERIAL_PORT_ENABLE (1 << 0)
174 #define DEFAULT_RX_QUEUE_SIZE 128
175 #define DEFAULT_TX_QUEUE_SIZE 256
181 #if defined(__BIG_ENDIAN)
183 u16 byte_cnt; /* Descriptor buffer byte count */
184 u16 buf_size; /* Buffer size */
185 u32 cmd_sts; /* Descriptor command status */
186 u32 next_desc_ptr; /* Next descriptor pointer */
187 u32 buf_ptr; /* Descriptor buffer pointer */
191 u16 byte_cnt; /* buffer byte count */
192 u16 l4i_chk; /* CPU provided TCP checksum */
193 u32 cmd_sts; /* Command/status field */
194 u32 next_desc_ptr; /* Pointer to next descriptor */
195 u32 buf_ptr; /* pointer to buffer for this descriptor*/
197 #elif defined(__LITTLE_ENDIAN)
199 u32 cmd_sts; /* Descriptor command status */
200 u16 buf_size; /* Buffer size */
201 u16 byte_cnt; /* Descriptor buffer byte count */
202 u32 buf_ptr; /* Descriptor buffer pointer */
203 u32 next_desc_ptr; /* Next descriptor pointer */
207 u32 cmd_sts; /* Command/status field */
208 u16 l4i_chk; /* CPU provided TCP checksum */
209 u16 byte_cnt; /* buffer byte count */
210 u32 buf_ptr; /* pointer to buffer for this descriptor*/
211 u32 next_desc_ptr; /* Pointer to next descriptor */
214 #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
217 /* RX & TX descriptor command */
218 #define BUFFER_OWNED_BY_DMA 0x80000000
220 /* RX & TX descriptor status */
221 #define ERROR_SUMMARY 0x00000001
223 /* RX descriptor status */
224 #define LAYER_4_CHECKSUM_OK 0x40000000
225 #define RX_ENABLE_INTERRUPT 0x20000000
226 #define RX_FIRST_DESC 0x08000000
227 #define RX_LAST_DESC 0x04000000
229 /* TX descriptor command */
230 #define TX_ENABLE_INTERRUPT 0x00800000
231 #define GEN_CRC 0x00400000
232 #define TX_FIRST_DESC 0x00200000
233 #define TX_LAST_DESC 0x00100000
234 #define ZERO_PADDING 0x00080000
235 #define GEN_IP_V4_CHECKSUM 0x00040000
236 #define GEN_TCP_UDP_CHECKSUM 0x00020000
237 #define UDP_FRAME 0x00010000
238 #define MAC_HDR_EXTRA_4_BYTES 0x00008000
239 #define MAC_HDR_EXTRA_8_BYTES 0x00000200
241 #define TX_IHL_SHIFT 11
244 /* global *******************************************************************/
245 struct mv643xx_eth_shared_private {
247 * Ethernet controller base address.
252 * Points at the right SMI instance to use.
254 struct mv643xx_eth_shared_private *smi;
257 * Provides access to local SMI interface.
259 struct mii_bus *smi_bus;
262 * If we have access to the error interrupt pin (which is
263 * somewhat misnamed as it not only reflects internal errors
264 * but also reflects SMI completion), use that to wait for
265 * SMI access completion instead of polling the SMI busy bit.
268 wait_queue_head_t smi_busy_wait;
271 * Per-port MBUS window access register value.
276 * Hardware-specific parameters.
279 int extended_rx_coal_limit;
283 #define TX_BW_CONTROL_ABSENT 0
284 #define TX_BW_CONTROL_OLD_LAYOUT 1
285 #define TX_BW_CONTROL_NEW_LAYOUT 2
288 /* per-port *****************************************************************/
289 struct mib_counters {
290 u64 good_octets_received;
291 u32 bad_octets_received;
292 u32 internal_mac_transmit_err;
293 u32 good_frames_received;
294 u32 bad_frames_received;
295 u32 broadcast_frames_received;
296 u32 multicast_frames_received;
297 u32 frames_64_octets;
298 u32 frames_65_to_127_octets;
299 u32 frames_128_to_255_octets;
300 u32 frames_256_to_511_octets;
301 u32 frames_512_to_1023_octets;
302 u32 frames_1024_to_max_octets;
303 u64 good_octets_sent;
304 u32 good_frames_sent;
305 u32 excessive_collision;
306 u32 multicast_frames_sent;
307 u32 broadcast_frames_sent;
308 u32 unrec_mac_control_received;
310 u32 good_fc_received;
312 u32 undersize_received;
313 u32 fragments_received;
314 u32 oversize_received;
316 u32 mac_receive_error;
331 struct rx_desc *rx_desc_area;
332 dma_addr_t rx_desc_dma;
333 int rx_desc_area_size;
334 struct sk_buff **rx_skb;
346 struct tx_desc *tx_desc_area;
347 dma_addr_t tx_desc_dma;
348 int tx_desc_area_size;
350 struct sk_buff_head tx_skb;
352 unsigned long tx_packets;
353 unsigned long tx_bytes;
354 unsigned long tx_dropped;
357 struct mv643xx_eth_private {
358 struct mv643xx_eth_shared_private *shared;
362 struct net_device *dev;
364 struct phy_device *phy;
366 struct timer_list mib_counters_timer;
367 spinlock_t mib_counters_lock;
368 struct mib_counters mib_counters;
370 struct work_struct tx_timeout_task;
372 struct napi_struct napi;
381 struct sk_buff_head rx_recycle;
386 int default_rx_ring_size;
387 unsigned long rx_desc_sram_addr;
388 int rx_desc_sram_size;
390 struct timer_list rx_oom;
391 struct rx_queue rxq[8];
396 int default_tx_ring_size;
397 unsigned long tx_desc_sram_addr;
398 int tx_desc_sram_size;
400 struct tx_queue txq[8];
404 /* port register accessors **************************************************/
405 static inline u32 rdl(struct mv643xx_eth_private *mp, int offset)
407 return readl(mp->shared->base + offset);
410 static inline u32 rdlp(struct mv643xx_eth_private *mp, int offset)
412 return readl(mp->base + offset);
415 static inline void wrl(struct mv643xx_eth_private *mp, int offset, u32 data)
417 writel(data, mp->shared->base + offset);
420 static inline void wrlp(struct mv643xx_eth_private *mp, int offset, u32 data)
422 writel(data, mp->base + offset);
426 /* rxq/txq helper functions *************************************************/
427 static struct mv643xx_eth_private *rxq_to_mp(struct rx_queue *rxq)
429 return container_of(rxq, struct mv643xx_eth_private, rxq[rxq->index]);
432 static struct mv643xx_eth_private *txq_to_mp(struct tx_queue *txq)
434 return container_of(txq, struct mv643xx_eth_private, txq[txq->index]);
437 static void rxq_enable(struct rx_queue *rxq)
439 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
440 wrlp(mp, RXQ_COMMAND, 1 << rxq->index);
443 static void rxq_disable(struct rx_queue *rxq)
445 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
446 u8 mask = 1 << rxq->index;
448 wrlp(mp, RXQ_COMMAND, mask << 8);
449 while (rdlp(mp, RXQ_COMMAND) & mask)
453 static void txq_reset_hw_ptr(struct tx_queue *txq)
455 struct mv643xx_eth_private *mp = txq_to_mp(txq);
458 addr = (u32)txq->tx_desc_dma;
459 addr += txq->tx_curr_desc * sizeof(struct tx_desc);
460 wrlp(mp, TXQ_CURRENT_DESC_PTR(txq->index), addr);
463 static void txq_enable(struct tx_queue *txq)
465 struct mv643xx_eth_private *mp = txq_to_mp(txq);
466 wrlp(mp, TXQ_COMMAND, 1 << txq->index);
469 static void txq_disable(struct tx_queue *txq)
471 struct mv643xx_eth_private *mp = txq_to_mp(txq);
472 u8 mask = 1 << txq->index;
474 wrlp(mp, TXQ_COMMAND, mask << 8);
475 while (rdlp(mp, TXQ_COMMAND) & mask)
479 static void txq_maybe_wake(struct tx_queue *txq)
481 struct mv643xx_eth_private *mp = txq_to_mp(txq);
482 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
484 if (netif_tx_queue_stopped(nq)) {
485 __netif_tx_lock(nq, smp_processor_id());
486 if (txq->tx_ring_size - txq->tx_desc_count >= MAX_SKB_FRAGS + 1)
487 netif_tx_wake_queue(nq);
488 __netif_tx_unlock(nq);
493 /* rx napi ******************************************************************/
494 static int rxq_process(struct rx_queue *rxq, int budget)
496 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
497 struct net_device_stats *stats = &mp->dev->stats;
501 while (rx < budget && rxq->rx_desc_count) {
502 struct rx_desc *rx_desc;
503 unsigned int cmd_sts;
507 rx_desc = &rxq->rx_desc_area[rxq->rx_curr_desc];
509 cmd_sts = rx_desc->cmd_sts;
510 if (cmd_sts & BUFFER_OWNED_BY_DMA)
514 skb = rxq->rx_skb[rxq->rx_curr_desc];
515 rxq->rx_skb[rxq->rx_curr_desc] = NULL;
518 if (rxq->rx_curr_desc == rxq->rx_ring_size)
519 rxq->rx_curr_desc = 0;
521 dma_unmap_single(NULL, rx_desc->buf_ptr,
522 rx_desc->buf_size, DMA_FROM_DEVICE);
523 rxq->rx_desc_count--;
526 mp->work_rx_refill |= 1 << rxq->index;
528 byte_cnt = rx_desc->byte_cnt;
533 * Note that the descriptor byte count includes 2 dummy
534 * bytes automatically inserted by the hardware at the
535 * start of the packet (which we don't count), and a 4
536 * byte CRC at the end of the packet (which we do count).
539 stats->rx_bytes += byte_cnt - 2;
542 * In case we received a packet without first / last bits
543 * on, or the error summary bit is set, the packet needs
546 if (((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
547 (RX_FIRST_DESC | RX_LAST_DESC))
548 || (cmd_sts & ERROR_SUMMARY)) {
551 if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
552 (RX_FIRST_DESC | RX_LAST_DESC)) {
554 dev_printk(KERN_ERR, &mp->dev->dev,
555 "received packet spanning "
556 "multiple descriptors\n");
559 if (cmd_sts & ERROR_SUMMARY)
565 * The -4 is for the CRC in the trailer of the
568 skb_put(skb, byte_cnt - 2 - 4);
570 if (cmd_sts & LAYER_4_CHECKSUM_OK)
571 skb->ip_summed = CHECKSUM_UNNECESSARY;
572 skb->protocol = eth_type_trans(skb, mp->dev);
573 netif_receive_skb(skb);
578 mp->work_rx &= ~(1 << rxq->index);
583 static int rxq_refill(struct rx_queue *rxq, int budget)
585 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
589 while (refilled < budget && rxq->rx_desc_count < rxq->rx_ring_size) {
594 skb = __skb_dequeue(&mp->rx_recycle);
596 skb = dev_alloc_skb(mp->skb_size +
597 dma_get_cache_alignment() - 1);
600 mp->work_rx_oom |= 1 << rxq->index;
604 unaligned = (u32)skb->data & (dma_get_cache_alignment() - 1);
606 skb_reserve(skb, dma_get_cache_alignment() - unaligned);
609 rxq->rx_desc_count++;
611 rx = rxq->rx_used_desc++;
612 if (rxq->rx_used_desc == rxq->rx_ring_size)
613 rxq->rx_used_desc = 0;
615 rxq->rx_desc_area[rx].buf_ptr = dma_map_single(NULL, skb->data,
616 mp->skb_size, DMA_FROM_DEVICE);
617 rxq->rx_desc_area[rx].buf_size = mp->skb_size;
618 rxq->rx_skb[rx] = skb;
620 rxq->rx_desc_area[rx].cmd_sts = BUFFER_OWNED_BY_DMA |
625 * The hardware automatically prepends 2 bytes of
626 * dummy data to each received packet, so that the
627 * IP header ends up 16-byte aligned.
632 if (refilled < budget)
633 mp->work_rx_refill &= ~(1 << rxq->index);
640 /* tx ***********************************************************************/
641 static inline unsigned int has_tiny_unaligned_frags(struct sk_buff *skb)
645 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
646 skb_frag_t *fragp = &skb_shinfo(skb)->frags[frag];
647 if (fragp->size <= 8 && fragp->page_offset & 7)
654 static void txq_submit_frag_skb(struct tx_queue *txq, struct sk_buff *skb)
656 int nr_frags = skb_shinfo(skb)->nr_frags;
659 for (frag = 0; frag < nr_frags; frag++) {
660 skb_frag_t *this_frag;
662 struct tx_desc *desc;
664 this_frag = &skb_shinfo(skb)->frags[frag];
665 tx_index = txq->tx_curr_desc++;
666 if (txq->tx_curr_desc == txq->tx_ring_size)
667 txq->tx_curr_desc = 0;
668 desc = &txq->tx_desc_area[tx_index];
671 * The last fragment will generate an interrupt
672 * which will free the skb on TX completion.
674 if (frag == nr_frags - 1) {
675 desc->cmd_sts = BUFFER_OWNED_BY_DMA |
676 ZERO_PADDING | TX_LAST_DESC |
679 desc->cmd_sts = BUFFER_OWNED_BY_DMA;
683 desc->byte_cnt = this_frag->size;
684 desc->buf_ptr = dma_map_page(NULL, this_frag->page,
685 this_frag->page_offset,
691 static inline __be16 sum16_as_be(__sum16 sum)
693 return (__force __be16)sum;
696 static int txq_submit_skb(struct tx_queue *txq, struct sk_buff *skb)
698 struct mv643xx_eth_private *mp = txq_to_mp(txq);
699 int nr_frags = skb_shinfo(skb)->nr_frags;
701 struct tx_desc *desc;
706 cmd_sts = TX_FIRST_DESC | GEN_CRC | BUFFER_OWNED_BY_DMA;
709 if (skb->ip_summed == CHECKSUM_PARTIAL) {
712 BUG_ON(skb->protocol != htons(ETH_P_IP) &&
713 skb->protocol != htons(ETH_P_8021Q));
715 tag_bytes = (void *)ip_hdr(skb) - (void *)skb->data - ETH_HLEN;
716 if (unlikely(tag_bytes & ~12)) {
717 if (skb_checksum_help(skb) == 0)
724 cmd_sts |= MAC_HDR_EXTRA_4_BYTES;
726 cmd_sts |= MAC_HDR_EXTRA_8_BYTES;
728 cmd_sts |= GEN_TCP_UDP_CHECKSUM |
730 ip_hdr(skb)->ihl << TX_IHL_SHIFT;
732 switch (ip_hdr(skb)->protocol) {
734 cmd_sts |= UDP_FRAME;
735 l4i_chk = ntohs(sum16_as_be(udp_hdr(skb)->check));
738 l4i_chk = ntohs(sum16_as_be(tcp_hdr(skb)->check));
745 /* Errata BTS #50, IHL must be 5 if no HW checksum */
746 cmd_sts |= 5 << TX_IHL_SHIFT;
749 tx_index = txq->tx_curr_desc++;
750 if (txq->tx_curr_desc == txq->tx_ring_size)
751 txq->tx_curr_desc = 0;
752 desc = &txq->tx_desc_area[tx_index];
755 txq_submit_frag_skb(txq, skb);
756 length = skb_headlen(skb);
758 cmd_sts |= ZERO_PADDING | TX_LAST_DESC | TX_ENABLE_INTERRUPT;
762 desc->l4i_chk = l4i_chk;
763 desc->byte_cnt = length;
764 desc->buf_ptr = dma_map_single(NULL, skb->data, length, DMA_TO_DEVICE);
766 __skb_queue_tail(&txq->tx_skb, skb);
768 /* ensure all other descriptors are written before first cmd_sts */
770 desc->cmd_sts = cmd_sts;
772 /* clear TX_END status */
773 mp->work_tx_end &= ~(1 << txq->index);
775 /* ensure all descriptors are written before poking hardware */
779 txq->tx_desc_count += nr_frags + 1;
784 static int mv643xx_eth_xmit(struct sk_buff *skb, struct net_device *dev)
786 struct mv643xx_eth_private *mp = netdev_priv(dev);
788 struct tx_queue *txq;
789 struct netdev_queue *nq;
791 queue = skb_get_queue_mapping(skb);
792 txq = mp->txq + queue;
793 nq = netdev_get_tx_queue(dev, queue);
795 if (has_tiny_unaligned_frags(skb) && __skb_linearize(skb)) {
797 dev_printk(KERN_DEBUG, &dev->dev,
798 "failed to linearize skb with tiny "
799 "unaligned fragment\n");
800 return NETDEV_TX_BUSY;
803 if (txq->tx_ring_size - txq->tx_desc_count < MAX_SKB_FRAGS + 1) {
805 dev_printk(KERN_ERR, &dev->dev, "tx queue full?!\n");
810 if (!txq_submit_skb(txq, skb)) {
813 txq->tx_bytes += skb->len;
815 dev->trans_start = jiffies;
817 entries_left = txq->tx_ring_size - txq->tx_desc_count;
818 if (entries_left < MAX_SKB_FRAGS + 1)
819 netif_tx_stop_queue(nq);
826 /* tx napi ******************************************************************/
827 static void txq_kick(struct tx_queue *txq)
829 struct mv643xx_eth_private *mp = txq_to_mp(txq);
830 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
834 __netif_tx_lock(nq, smp_processor_id());
836 if (rdlp(mp, TXQ_COMMAND) & (1 << txq->index))
839 hw_desc_ptr = rdlp(mp, TXQ_CURRENT_DESC_PTR(txq->index));
840 expected_ptr = (u32)txq->tx_desc_dma +
841 txq->tx_curr_desc * sizeof(struct tx_desc);
843 if (hw_desc_ptr != expected_ptr)
847 __netif_tx_unlock(nq);
849 mp->work_tx_end &= ~(1 << txq->index);
852 static int txq_reclaim(struct tx_queue *txq, int budget, int force)
854 struct mv643xx_eth_private *mp = txq_to_mp(txq);
855 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
858 __netif_tx_lock(nq, smp_processor_id());
861 while (reclaimed < budget && txq->tx_desc_count > 0) {
863 struct tx_desc *desc;
867 tx_index = txq->tx_used_desc;
868 desc = &txq->tx_desc_area[tx_index];
869 cmd_sts = desc->cmd_sts;
871 if (cmd_sts & BUFFER_OWNED_BY_DMA) {
874 desc->cmd_sts = cmd_sts & ~BUFFER_OWNED_BY_DMA;
877 txq->tx_used_desc = tx_index + 1;
878 if (txq->tx_used_desc == txq->tx_ring_size)
879 txq->tx_used_desc = 0;
882 txq->tx_desc_count--;
885 if (cmd_sts & TX_LAST_DESC)
886 skb = __skb_dequeue(&txq->tx_skb);
888 if (cmd_sts & ERROR_SUMMARY) {
889 dev_printk(KERN_INFO, &mp->dev->dev, "tx error\n");
890 mp->dev->stats.tx_errors++;
893 if (cmd_sts & TX_FIRST_DESC) {
894 dma_unmap_single(NULL, desc->buf_ptr,
895 desc->byte_cnt, DMA_TO_DEVICE);
897 dma_unmap_page(NULL, desc->buf_ptr,
898 desc->byte_cnt, DMA_TO_DEVICE);
902 if (skb_queue_len(&mp->rx_recycle) <
903 mp->default_rx_ring_size &&
904 skb_recycle_check(skb, mp->skb_size))
905 __skb_queue_head(&mp->rx_recycle, skb);
911 __netif_tx_unlock(nq);
913 if (reclaimed < budget)
914 mp->work_tx &= ~(1 << txq->index);
920 /* tx rate control **********************************************************/
922 * Set total maximum TX rate (shared by all TX queues for this port)
923 * to 'rate' bits per second, with a maximum burst of 'burst' bytes.
925 static void tx_set_rate(struct mv643xx_eth_private *mp, int rate, int burst)
931 token_rate = ((rate / 1000) * 64) / (mp->shared->t_clk / 1000);
932 if (token_rate > 1023)
935 mtu = (mp->dev->mtu + 255) >> 8;
939 bucket_size = (burst + 255) >> 8;
940 if (bucket_size > 65535)
943 switch (mp->shared->tx_bw_control) {
944 case TX_BW_CONTROL_OLD_LAYOUT:
945 wrlp(mp, TX_BW_RATE, token_rate);
946 wrlp(mp, TX_BW_MTU, mtu);
947 wrlp(mp, TX_BW_BURST, bucket_size);
949 case TX_BW_CONTROL_NEW_LAYOUT:
950 wrlp(mp, TX_BW_RATE_MOVED, token_rate);
951 wrlp(mp, TX_BW_MTU_MOVED, mtu);
952 wrlp(mp, TX_BW_BURST_MOVED, bucket_size);
957 static void txq_set_rate(struct tx_queue *txq, int rate, int burst)
959 struct mv643xx_eth_private *mp = txq_to_mp(txq);
963 token_rate = ((rate / 1000) * 64) / (mp->shared->t_clk / 1000);
964 if (token_rate > 1023)
967 bucket_size = (burst + 255) >> 8;
968 if (bucket_size > 65535)
971 wrlp(mp, TXQ_BW_TOKENS(txq->index), token_rate << 14);
972 wrlp(mp, TXQ_BW_CONF(txq->index), (bucket_size << 10) | token_rate);
975 static void txq_set_fixed_prio_mode(struct tx_queue *txq)
977 struct mv643xx_eth_private *mp = txq_to_mp(txq);
982 * Turn on fixed priority mode.
985 switch (mp->shared->tx_bw_control) {
986 case TX_BW_CONTROL_OLD_LAYOUT:
987 off = TXQ_FIX_PRIO_CONF;
989 case TX_BW_CONTROL_NEW_LAYOUT:
990 off = TXQ_FIX_PRIO_CONF_MOVED;
996 val |= 1 << txq->index;
1001 static void txq_set_wrr(struct tx_queue *txq, int weight)
1003 struct mv643xx_eth_private *mp = txq_to_mp(txq);
1008 * Turn off fixed priority mode.
1011 switch (mp->shared->tx_bw_control) {
1012 case TX_BW_CONTROL_OLD_LAYOUT:
1013 off = TXQ_FIX_PRIO_CONF;
1015 case TX_BW_CONTROL_NEW_LAYOUT:
1016 off = TXQ_FIX_PRIO_CONF_MOVED;
1021 val = rdlp(mp, off);
1022 val &= ~(1 << txq->index);
1026 * Configure WRR weight for this queue.
1029 val = rdlp(mp, off);
1030 val = (val & ~0xff) | (weight & 0xff);
1031 wrlp(mp, TXQ_BW_WRR_CONF(txq->index), val);
1036 /* mii management interface *************************************************/
1037 static irqreturn_t mv643xx_eth_err_irq(int irq, void *dev_id)
1039 struct mv643xx_eth_shared_private *msp = dev_id;
1041 if (readl(msp->base + ERR_INT_CAUSE) & ERR_INT_SMI_DONE) {
1042 writel(~ERR_INT_SMI_DONE, msp->base + ERR_INT_CAUSE);
1043 wake_up(&msp->smi_busy_wait);
1050 static int smi_is_done(struct mv643xx_eth_shared_private *msp)
1052 return !(readl(msp->base + SMI_REG) & SMI_BUSY);
1055 static int smi_wait_ready(struct mv643xx_eth_shared_private *msp)
1057 if (msp->err_interrupt == NO_IRQ) {
1060 for (i = 0; !smi_is_done(msp); i++) {
1069 if (!smi_is_done(msp)) {
1070 wait_event_timeout(msp->smi_busy_wait, smi_is_done(msp),
1071 msecs_to_jiffies(100));
1072 if (!smi_is_done(msp))
1079 static int smi_bus_read(struct mii_bus *bus, int addr, int reg)
1081 struct mv643xx_eth_shared_private *msp = bus->priv;
1082 void __iomem *smi_reg = msp->base + SMI_REG;
1085 if (smi_wait_ready(msp)) {
1086 printk(KERN_WARNING "mv643xx_eth: SMI bus busy timeout\n");
1090 writel(SMI_OPCODE_READ | (reg << 21) | (addr << 16), smi_reg);
1092 if (smi_wait_ready(msp)) {
1093 printk(KERN_WARNING "mv643xx_eth: SMI bus busy timeout\n");
1097 ret = readl(smi_reg);
1098 if (!(ret & SMI_READ_VALID)) {
1099 printk(KERN_WARNING "mv643xx_eth: SMI bus read not valid\n");
1103 return ret & 0xffff;
1106 static int smi_bus_write(struct mii_bus *bus, int addr, int reg, u16 val)
1108 struct mv643xx_eth_shared_private *msp = bus->priv;
1109 void __iomem *smi_reg = msp->base + SMI_REG;
1111 if (smi_wait_ready(msp)) {
1112 printk(KERN_WARNING "mv643xx_eth: SMI bus busy timeout\n");
1116 writel(SMI_OPCODE_WRITE | (reg << 21) |
1117 (addr << 16) | (val & 0xffff), smi_reg);
1119 if (smi_wait_ready(msp)) {
1120 printk(KERN_WARNING "mv643xx_eth: SMI bus busy timeout\n");
1128 /* statistics ***************************************************************/
1129 static struct net_device_stats *mv643xx_eth_get_stats(struct net_device *dev)
1131 struct mv643xx_eth_private *mp = netdev_priv(dev);
1132 struct net_device_stats *stats = &dev->stats;
1133 unsigned long tx_packets = 0;
1134 unsigned long tx_bytes = 0;
1135 unsigned long tx_dropped = 0;
1138 for (i = 0; i < mp->txq_count; i++) {
1139 struct tx_queue *txq = mp->txq + i;
1141 tx_packets += txq->tx_packets;
1142 tx_bytes += txq->tx_bytes;
1143 tx_dropped += txq->tx_dropped;
1146 stats->tx_packets = tx_packets;
1147 stats->tx_bytes = tx_bytes;
1148 stats->tx_dropped = tx_dropped;
1153 static inline u32 mib_read(struct mv643xx_eth_private *mp, int offset)
1155 return rdl(mp, MIB_COUNTERS(mp->port_num) + offset);
1158 static void mib_counters_clear(struct mv643xx_eth_private *mp)
1162 for (i = 0; i < 0x80; i += 4)
1166 static void mib_counters_update(struct mv643xx_eth_private *mp)
1168 struct mib_counters *p = &mp->mib_counters;
1170 spin_lock(&mp->mib_counters_lock);
1171 p->good_octets_received += mib_read(mp, 0x00);
1172 p->good_octets_received += (u64)mib_read(mp, 0x04) << 32;
1173 p->bad_octets_received += mib_read(mp, 0x08);
1174 p->internal_mac_transmit_err += mib_read(mp, 0x0c);
1175 p->good_frames_received += mib_read(mp, 0x10);
1176 p->bad_frames_received += mib_read(mp, 0x14);
1177 p->broadcast_frames_received += mib_read(mp, 0x18);
1178 p->multicast_frames_received += mib_read(mp, 0x1c);
1179 p->frames_64_octets += mib_read(mp, 0x20);
1180 p->frames_65_to_127_octets += mib_read(mp, 0x24);
1181 p->frames_128_to_255_octets += mib_read(mp, 0x28);
1182 p->frames_256_to_511_octets += mib_read(mp, 0x2c);
1183 p->frames_512_to_1023_octets += mib_read(mp, 0x30);
1184 p->frames_1024_to_max_octets += mib_read(mp, 0x34);
1185 p->good_octets_sent += mib_read(mp, 0x38);
1186 p->good_octets_sent += (u64)mib_read(mp, 0x3c) << 32;
1187 p->good_frames_sent += mib_read(mp, 0x40);
1188 p->excessive_collision += mib_read(mp, 0x44);
1189 p->multicast_frames_sent += mib_read(mp, 0x48);
1190 p->broadcast_frames_sent += mib_read(mp, 0x4c);
1191 p->unrec_mac_control_received += mib_read(mp, 0x50);
1192 p->fc_sent += mib_read(mp, 0x54);
1193 p->good_fc_received += mib_read(mp, 0x58);
1194 p->bad_fc_received += mib_read(mp, 0x5c);
1195 p->undersize_received += mib_read(mp, 0x60);
1196 p->fragments_received += mib_read(mp, 0x64);
1197 p->oversize_received += mib_read(mp, 0x68);
1198 p->jabber_received += mib_read(mp, 0x6c);
1199 p->mac_receive_error += mib_read(mp, 0x70);
1200 p->bad_crc_event += mib_read(mp, 0x74);
1201 p->collision += mib_read(mp, 0x78);
1202 p->late_collision += mib_read(mp, 0x7c);
1203 spin_unlock(&mp->mib_counters_lock);
1205 mod_timer(&mp->mib_counters_timer, jiffies + 30 * HZ);
1208 static void mib_counters_timer_wrapper(unsigned long _mp)
1210 struct mv643xx_eth_private *mp = (void *)_mp;
1212 mib_counters_update(mp);
1216 /* ethtool ******************************************************************/
1217 struct mv643xx_eth_stats {
1218 char stat_string[ETH_GSTRING_LEN];
1225 { #m, FIELD_SIZEOF(struct net_device_stats, m), \
1226 offsetof(struct net_device, stats.m), -1 }
1228 #define MIBSTAT(m) \
1229 { #m, FIELD_SIZEOF(struct mib_counters, m), \
1230 -1, offsetof(struct mv643xx_eth_private, mib_counters.m) }
1232 static const struct mv643xx_eth_stats mv643xx_eth_stats[] = {
1241 MIBSTAT(good_octets_received),
1242 MIBSTAT(bad_octets_received),
1243 MIBSTAT(internal_mac_transmit_err),
1244 MIBSTAT(good_frames_received),
1245 MIBSTAT(bad_frames_received),
1246 MIBSTAT(broadcast_frames_received),
1247 MIBSTAT(multicast_frames_received),
1248 MIBSTAT(frames_64_octets),
1249 MIBSTAT(frames_65_to_127_octets),
1250 MIBSTAT(frames_128_to_255_octets),
1251 MIBSTAT(frames_256_to_511_octets),
1252 MIBSTAT(frames_512_to_1023_octets),
1253 MIBSTAT(frames_1024_to_max_octets),
1254 MIBSTAT(good_octets_sent),
1255 MIBSTAT(good_frames_sent),
1256 MIBSTAT(excessive_collision),
1257 MIBSTAT(multicast_frames_sent),
1258 MIBSTAT(broadcast_frames_sent),
1259 MIBSTAT(unrec_mac_control_received),
1261 MIBSTAT(good_fc_received),
1262 MIBSTAT(bad_fc_received),
1263 MIBSTAT(undersize_received),
1264 MIBSTAT(fragments_received),
1265 MIBSTAT(oversize_received),
1266 MIBSTAT(jabber_received),
1267 MIBSTAT(mac_receive_error),
1268 MIBSTAT(bad_crc_event),
1270 MIBSTAT(late_collision),
1274 mv643xx_eth_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1276 struct mv643xx_eth_private *mp = netdev_priv(dev);
1279 err = phy_read_status(mp->phy);
1281 err = phy_ethtool_gset(mp->phy, cmd);
1284 * The MAC does not support 1000baseT_Half.
1286 cmd->supported &= ~SUPPORTED_1000baseT_Half;
1287 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1293 mv643xx_eth_get_settings_phyless(struct net_device *dev,
1294 struct ethtool_cmd *cmd)
1296 struct mv643xx_eth_private *mp = netdev_priv(dev);
1299 port_status = rdlp(mp, PORT_STATUS);
1301 cmd->supported = SUPPORTED_MII;
1302 cmd->advertising = ADVERTISED_MII;
1303 switch (port_status & PORT_SPEED_MASK) {
1305 cmd->speed = SPEED_10;
1307 case PORT_SPEED_100:
1308 cmd->speed = SPEED_100;
1310 case PORT_SPEED_1000:
1311 cmd->speed = SPEED_1000;
1317 cmd->duplex = (port_status & FULL_DUPLEX) ? DUPLEX_FULL : DUPLEX_HALF;
1318 cmd->port = PORT_MII;
1319 cmd->phy_address = 0;
1320 cmd->transceiver = XCVR_INTERNAL;
1321 cmd->autoneg = AUTONEG_DISABLE;
1329 mv643xx_eth_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1331 struct mv643xx_eth_private *mp = netdev_priv(dev);
1334 * The MAC does not support 1000baseT_Half.
1336 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1338 return phy_ethtool_sset(mp->phy, cmd);
1342 mv643xx_eth_set_settings_phyless(struct net_device *dev,
1343 struct ethtool_cmd *cmd)
1348 static void mv643xx_eth_get_drvinfo(struct net_device *dev,
1349 struct ethtool_drvinfo *drvinfo)
1351 strncpy(drvinfo->driver, mv643xx_eth_driver_name, 32);
1352 strncpy(drvinfo->version, mv643xx_eth_driver_version, 32);
1353 strncpy(drvinfo->fw_version, "N/A", 32);
1354 strncpy(drvinfo->bus_info, "platform", 32);
1355 drvinfo->n_stats = ARRAY_SIZE(mv643xx_eth_stats);
1358 static int mv643xx_eth_nway_reset(struct net_device *dev)
1360 struct mv643xx_eth_private *mp = netdev_priv(dev);
1362 return genphy_restart_aneg(mp->phy);
1365 static int mv643xx_eth_nway_reset_phyless(struct net_device *dev)
1370 static u32 mv643xx_eth_get_link(struct net_device *dev)
1372 return !!netif_carrier_ok(dev);
1375 static void mv643xx_eth_get_strings(struct net_device *dev,
1376 uint32_t stringset, uint8_t *data)
1380 if (stringset == ETH_SS_STATS) {
1381 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
1382 memcpy(data + i * ETH_GSTRING_LEN,
1383 mv643xx_eth_stats[i].stat_string,
1389 static void mv643xx_eth_get_ethtool_stats(struct net_device *dev,
1390 struct ethtool_stats *stats,
1393 struct mv643xx_eth_private *mp = netdev_priv(dev);
1396 mv643xx_eth_get_stats(dev);
1397 mib_counters_update(mp);
1399 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
1400 const struct mv643xx_eth_stats *stat;
1403 stat = mv643xx_eth_stats + i;
1405 if (stat->netdev_off >= 0)
1406 p = ((void *)mp->dev) + stat->netdev_off;
1408 p = ((void *)mp) + stat->mp_off;
1410 data[i] = (stat->sizeof_stat == 8) ?
1411 *(uint64_t *)p : *(uint32_t *)p;
1415 static int mv643xx_eth_get_sset_count(struct net_device *dev, int sset)
1417 if (sset == ETH_SS_STATS)
1418 return ARRAY_SIZE(mv643xx_eth_stats);
1423 static const struct ethtool_ops mv643xx_eth_ethtool_ops = {
1424 .get_settings = mv643xx_eth_get_settings,
1425 .set_settings = mv643xx_eth_set_settings,
1426 .get_drvinfo = mv643xx_eth_get_drvinfo,
1427 .nway_reset = mv643xx_eth_nway_reset,
1428 .get_link = mv643xx_eth_get_link,
1429 .set_sg = ethtool_op_set_sg,
1430 .get_strings = mv643xx_eth_get_strings,
1431 .get_ethtool_stats = mv643xx_eth_get_ethtool_stats,
1432 .get_sset_count = mv643xx_eth_get_sset_count,
1435 static const struct ethtool_ops mv643xx_eth_ethtool_ops_phyless = {
1436 .get_settings = mv643xx_eth_get_settings_phyless,
1437 .set_settings = mv643xx_eth_set_settings_phyless,
1438 .get_drvinfo = mv643xx_eth_get_drvinfo,
1439 .nway_reset = mv643xx_eth_nway_reset_phyless,
1440 .get_link = mv643xx_eth_get_link,
1441 .set_sg = ethtool_op_set_sg,
1442 .get_strings = mv643xx_eth_get_strings,
1443 .get_ethtool_stats = mv643xx_eth_get_ethtool_stats,
1444 .get_sset_count = mv643xx_eth_get_sset_count,
1448 /* address handling *********************************************************/
1449 static void uc_addr_get(struct mv643xx_eth_private *mp, unsigned char *addr)
1451 unsigned int mac_h = rdlp(mp, MAC_ADDR_HIGH);
1452 unsigned int mac_l = rdlp(mp, MAC_ADDR_LOW);
1454 addr[0] = (mac_h >> 24) & 0xff;
1455 addr[1] = (mac_h >> 16) & 0xff;
1456 addr[2] = (mac_h >> 8) & 0xff;
1457 addr[3] = mac_h & 0xff;
1458 addr[4] = (mac_l >> 8) & 0xff;
1459 addr[5] = mac_l & 0xff;
1462 static void uc_addr_set(struct mv643xx_eth_private *mp, unsigned char *addr)
1464 wrlp(mp, MAC_ADDR_HIGH,
1465 (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3]);
1466 wrlp(mp, MAC_ADDR_LOW, (addr[4] << 8) | addr[5]);
1469 static u32 uc_addr_filter_mask(struct net_device *dev)
1471 struct dev_addr_list *uc_ptr;
1474 if (dev->flags & IFF_PROMISC)
1477 nibbles = 1 << (dev->dev_addr[5] & 0x0f);
1478 for (uc_ptr = dev->uc_list; uc_ptr != NULL; uc_ptr = uc_ptr->next) {
1479 if (memcmp(dev->dev_addr, uc_ptr->da_addr, 5))
1481 if ((dev->dev_addr[5] ^ uc_ptr->da_addr[5]) & 0xf0)
1484 nibbles |= 1 << (uc_ptr->da_addr[5] & 0x0f);
1490 static void mv643xx_eth_program_unicast_filter(struct net_device *dev)
1492 struct mv643xx_eth_private *mp = netdev_priv(dev);
1497 uc_addr_set(mp, dev->dev_addr);
1499 port_config = rdlp(mp, PORT_CONFIG);
1500 nibbles = uc_addr_filter_mask(dev);
1502 port_config |= UNICAST_PROMISCUOUS_MODE;
1503 wrlp(mp, PORT_CONFIG, port_config);
1507 for (i = 0; i < 16; i += 4) {
1508 int off = UNICAST_TABLE(mp->port_num) + i;
1525 port_config &= ~UNICAST_PROMISCUOUS_MODE;
1526 wrlp(mp, PORT_CONFIG, port_config);
1529 static int addr_crc(unsigned char *addr)
1534 for (i = 0; i < 6; i++) {
1537 crc = (crc ^ addr[i]) << 8;
1538 for (j = 7; j >= 0; j--) {
1539 if (crc & (0x100 << j))
1547 static void mv643xx_eth_program_multicast_filter(struct net_device *dev)
1549 struct mv643xx_eth_private *mp = netdev_priv(dev);
1552 struct dev_addr_list *addr;
1555 if (dev->flags & (IFF_PROMISC | IFF_ALLMULTI)) {
1561 port_num = mp->port_num;
1562 accept = 0x01010101;
1563 for (i = 0; i < 0x100; i += 4) {
1564 wrl(mp, SPECIAL_MCAST_TABLE(port_num) + i, accept);
1565 wrl(mp, OTHER_MCAST_TABLE(port_num) + i, accept);
1570 mc_spec = kmalloc(0x200, GFP_KERNEL);
1571 if (mc_spec == NULL)
1573 mc_other = mc_spec + (0x100 >> 2);
1575 memset(mc_spec, 0, 0x100);
1576 memset(mc_other, 0, 0x100);
1578 for (addr = dev->mc_list; addr != NULL; addr = addr->next) {
1579 u8 *a = addr->da_addr;
1583 if (memcmp(a, "\x01\x00\x5e\x00\x00", 5) == 0) {
1588 entry = addr_crc(a);
1591 table[entry >> 2] |= 1 << (entry & 3);
1594 for (i = 0; i < 0x100; i += 4) {
1595 wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i, mc_spec[i >> 2]);
1596 wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i, mc_other[i >> 2]);
1602 static void mv643xx_eth_set_rx_mode(struct net_device *dev)
1604 mv643xx_eth_program_unicast_filter(dev);
1605 mv643xx_eth_program_multicast_filter(dev);
1608 static int mv643xx_eth_set_mac_address(struct net_device *dev, void *addr)
1610 struct sockaddr *sa = addr;
1612 memcpy(dev->dev_addr, sa->sa_data, ETH_ALEN);
1614 netif_addr_lock_bh(dev);
1615 mv643xx_eth_program_unicast_filter(dev);
1616 netif_addr_unlock_bh(dev);
1622 /* rx/tx queue initialisation ***********************************************/
1623 static int rxq_init(struct mv643xx_eth_private *mp, int index)
1625 struct rx_queue *rxq = mp->rxq + index;
1626 struct rx_desc *rx_desc;
1632 rxq->rx_ring_size = mp->default_rx_ring_size;
1634 rxq->rx_desc_count = 0;
1635 rxq->rx_curr_desc = 0;
1636 rxq->rx_used_desc = 0;
1638 size = rxq->rx_ring_size * sizeof(struct rx_desc);
1640 if (index == 0 && size <= mp->rx_desc_sram_size) {
1641 rxq->rx_desc_area = ioremap(mp->rx_desc_sram_addr,
1642 mp->rx_desc_sram_size);
1643 rxq->rx_desc_dma = mp->rx_desc_sram_addr;
1645 rxq->rx_desc_area = dma_alloc_coherent(NULL, size,
1650 if (rxq->rx_desc_area == NULL) {
1651 dev_printk(KERN_ERR, &mp->dev->dev,
1652 "can't allocate rx ring (%d bytes)\n", size);
1655 memset(rxq->rx_desc_area, 0, size);
1657 rxq->rx_desc_area_size = size;
1658 rxq->rx_skb = kmalloc(rxq->rx_ring_size * sizeof(*rxq->rx_skb),
1660 if (rxq->rx_skb == NULL) {
1661 dev_printk(KERN_ERR, &mp->dev->dev,
1662 "can't allocate rx skb ring\n");
1666 rx_desc = (struct rx_desc *)rxq->rx_desc_area;
1667 for (i = 0; i < rxq->rx_ring_size; i++) {
1671 if (nexti == rxq->rx_ring_size)
1674 rx_desc[i].next_desc_ptr = rxq->rx_desc_dma +
1675 nexti * sizeof(struct rx_desc);
1682 if (index == 0 && size <= mp->rx_desc_sram_size)
1683 iounmap(rxq->rx_desc_area);
1685 dma_free_coherent(NULL, size,
1693 static void rxq_deinit(struct rx_queue *rxq)
1695 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
1700 for (i = 0; i < rxq->rx_ring_size; i++) {
1701 if (rxq->rx_skb[i]) {
1702 dev_kfree_skb(rxq->rx_skb[i]);
1703 rxq->rx_desc_count--;
1707 if (rxq->rx_desc_count) {
1708 dev_printk(KERN_ERR, &mp->dev->dev,
1709 "error freeing rx ring -- %d skbs stuck\n",
1710 rxq->rx_desc_count);
1713 if (rxq->index == 0 &&
1714 rxq->rx_desc_area_size <= mp->rx_desc_sram_size)
1715 iounmap(rxq->rx_desc_area);
1717 dma_free_coherent(NULL, rxq->rx_desc_area_size,
1718 rxq->rx_desc_area, rxq->rx_desc_dma);
1723 static int txq_init(struct mv643xx_eth_private *mp, int index)
1725 struct tx_queue *txq = mp->txq + index;
1726 struct tx_desc *tx_desc;
1732 txq->tx_ring_size = mp->default_tx_ring_size;
1734 txq->tx_desc_count = 0;
1735 txq->tx_curr_desc = 0;
1736 txq->tx_used_desc = 0;
1738 size = txq->tx_ring_size * sizeof(struct tx_desc);
1740 if (index == 0 && size <= mp->tx_desc_sram_size) {
1741 txq->tx_desc_area = ioremap(mp->tx_desc_sram_addr,
1742 mp->tx_desc_sram_size);
1743 txq->tx_desc_dma = mp->tx_desc_sram_addr;
1745 txq->tx_desc_area = dma_alloc_coherent(NULL, size,
1750 if (txq->tx_desc_area == NULL) {
1751 dev_printk(KERN_ERR, &mp->dev->dev,
1752 "can't allocate tx ring (%d bytes)\n", size);
1755 memset(txq->tx_desc_area, 0, size);
1757 txq->tx_desc_area_size = size;
1759 tx_desc = (struct tx_desc *)txq->tx_desc_area;
1760 for (i = 0; i < txq->tx_ring_size; i++) {
1761 struct tx_desc *txd = tx_desc + i;
1765 if (nexti == txq->tx_ring_size)
1769 txd->next_desc_ptr = txq->tx_desc_dma +
1770 nexti * sizeof(struct tx_desc);
1773 skb_queue_head_init(&txq->tx_skb);
1778 static void txq_deinit(struct tx_queue *txq)
1780 struct mv643xx_eth_private *mp = txq_to_mp(txq);
1783 txq_reclaim(txq, txq->tx_ring_size, 1);
1785 BUG_ON(txq->tx_used_desc != txq->tx_curr_desc);
1787 if (txq->index == 0 &&
1788 txq->tx_desc_area_size <= mp->tx_desc_sram_size)
1789 iounmap(txq->tx_desc_area);
1791 dma_free_coherent(NULL, txq->tx_desc_area_size,
1792 txq->tx_desc_area, txq->tx_desc_dma);
1796 /* netdev ops and related ***************************************************/
1797 static int mv643xx_eth_collect_events(struct mv643xx_eth_private *mp)
1802 int_cause = rdlp(mp, INT_CAUSE) & (INT_TX_END | INT_RX | INT_EXT);
1807 if (int_cause & INT_EXT)
1808 int_cause_ext = rdlp(mp, INT_CAUSE_EXT);
1810 int_cause &= INT_TX_END | INT_RX;
1812 wrlp(mp, INT_CAUSE, ~int_cause);
1813 mp->work_tx_end |= ((int_cause & INT_TX_END) >> 19) &
1814 ~(rdlp(mp, TXQ_COMMAND) & 0xff);
1815 mp->work_rx |= (int_cause & INT_RX) >> 2;
1818 int_cause_ext &= INT_EXT_LINK_PHY | INT_EXT_TX;
1819 if (int_cause_ext) {
1820 wrlp(mp, INT_CAUSE_EXT, ~int_cause_ext);
1821 if (int_cause_ext & INT_EXT_LINK_PHY)
1823 mp->work_tx |= int_cause_ext & INT_EXT_TX;
1829 static irqreturn_t mv643xx_eth_irq(int irq, void *dev_id)
1831 struct net_device *dev = (struct net_device *)dev_id;
1832 struct mv643xx_eth_private *mp = netdev_priv(dev);
1834 if (unlikely(!mv643xx_eth_collect_events(mp)))
1837 wrlp(mp, INT_MASK, 0);
1838 napi_schedule(&mp->napi);
1843 static void handle_link_event(struct mv643xx_eth_private *mp)
1845 struct net_device *dev = mp->dev;
1851 port_status = rdlp(mp, PORT_STATUS);
1852 if (!(port_status & LINK_UP)) {
1853 if (netif_carrier_ok(dev)) {
1856 printk(KERN_INFO "%s: link down\n", dev->name);
1858 netif_carrier_off(dev);
1860 for (i = 0; i < mp->txq_count; i++) {
1861 struct tx_queue *txq = mp->txq + i;
1863 txq_reclaim(txq, txq->tx_ring_size, 1);
1864 txq_reset_hw_ptr(txq);
1870 switch (port_status & PORT_SPEED_MASK) {
1874 case PORT_SPEED_100:
1877 case PORT_SPEED_1000:
1884 duplex = (port_status & FULL_DUPLEX) ? 1 : 0;
1885 fc = (port_status & FLOW_CONTROL_ENABLED) ? 1 : 0;
1887 printk(KERN_INFO "%s: link up, %d Mb/s, %s duplex, "
1888 "flow control %sabled\n", dev->name,
1889 speed, duplex ? "full" : "half",
1892 if (!netif_carrier_ok(dev))
1893 netif_carrier_on(dev);
1896 static int mv643xx_eth_poll(struct napi_struct *napi, int budget)
1898 struct mv643xx_eth_private *mp;
1901 mp = container_of(napi, struct mv643xx_eth_private, napi);
1903 mp->work_rx_refill |= mp->work_rx_oom;
1904 mp->work_rx_oom = 0;
1907 while (work_done < budget) {
1912 if (mp->work_link) {
1914 handle_link_event(mp);
1918 queue_mask = mp->work_tx | mp->work_tx_end |
1919 mp->work_rx | mp->work_rx_refill;
1921 if (mv643xx_eth_collect_events(mp))
1926 queue = fls(queue_mask) - 1;
1927 queue_mask = 1 << queue;
1929 work_tbd = budget - work_done;
1933 if (mp->work_tx_end & queue_mask) {
1934 txq_kick(mp->txq + queue);
1935 } else if (mp->work_tx & queue_mask) {
1936 work_done += txq_reclaim(mp->txq + queue, work_tbd, 0);
1937 txq_maybe_wake(mp->txq + queue);
1938 } else if (mp->work_rx & queue_mask) {
1939 work_done += rxq_process(mp->rxq + queue, work_tbd);
1940 } else if (mp->work_rx_refill & queue_mask) {
1941 work_done += rxq_refill(mp->rxq + queue, work_tbd);
1947 if (work_done < budget) {
1948 if (mp->work_rx_oom)
1949 mod_timer(&mp->rx_oom, jiffies + (HZ / 10));
1950 napi_complete(napi);
1951 wrlp(mp, INT_MASK, INT_TX_END | INT_RX | INT_EXT);
1957 static inline void oom_timer_wrapper(unsigned long data)
1959 struct mv643xx_eth_private *mp = (void *)data;
1961 napi_schedule(&mp->napi);
1964 static void phy_reset(struct mv643xx_eth_private *mp)
1968 data = phy_read(mp->phy, MII_BMCR);
1973 if (phy_write(mp->phy, MII_BMCR, data) < 0)
1977 data = phy_read(mp->phy, MII_BMCR);
1978 } while (data >= 0 && data & BMCR_RESET);
1981 static void port_start(struct mv643xx_eth_private *mp)
1987 * Perform PHY reset, if there is a PHY.
1989 if (mp->phy != NULL) {
1990 struct ethtool_cmd cmd;
1992 mv643xx_eth_get_settings(mp->dev, &cmd);
1994 mv643xx_eth_set_settings(mp->dev, &cmd);
1998 * Configure basic link parameters.
2000 pscr = rdlp(mp, PORT_SERIAL_CONTROL);
2002 pscr |= SERIAL_PORT_ENABLE;
2003 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
2005 pscr |= DO_NOT_FORCE_LINK_FAIL;
2006 if (mp->phy == NULL)
2007 pscr |= FORCE_LINK_PASS;
2008 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
2010 wrlp(mp, SDMA_CONFIG, PORT_SDMA_CONFIG_DEFAULT_VALUE);
2013 * Configure TX path and queues.
2015 tx_set_rate(mp, 1000000000, 16777216);
2016 for (i = 0; i < mp->txq_count; i++) {
2017 struct tx_queue *txq = mp->txq + i;
2019 txq_reset_hw_ptr(txq);
2020 txq_set_rate(txq, 1000000000, 16777216);
2021 txq_set_fixed_prio_mode(txq);
2025 * Add configured unicast address to address filter table.
2027 mv643xx_eth_program_unicast_filter(mp->dev);
2030 * Receive all unmatched unicast, TCP, UDP, BPDU and broadcast
2031 * frames to RX queue #0, and include the pseudo-header when
2032 * calculating receive checksums.
2034 wrlp(mp, PORT_CONFIG, 0x02000000);
2037 * Treat BPDUs as normal multicasts, and disable partition mode.
2039 wrlp(mp, PORT_CONFIG_EXT, 0x00000000);
2042 * Enable the receive queues.
2044 for (i = 0; i < mp->rxq_count; i++) {
2045 struct rx_queue *rxq = mp->rxq + i;
2048 addr = (u32)rxq->rx_desc_dma;
2049 addr += rxq->rx_curr_desc * sizeof(struct rx_desc);
2050 wrlp(mp, RXQ_CURRENT_DESC_PTR(i), addr);
2056 static void set_rx_coal(struct mv643xx_eth_private *mp, unsigned int delay)
2058 unsigned int coal = ((mp->shared->t_clk / 1000000) * delay) / 64;
2061 val = rdlp(mp, SDMA_CONFIG);
2062 if (mp->shared->extended_rx_coal_limit) {
2066 val |= (coal & 0x8000) << 10;
2067 val |= (coal & 0x7fff) << 7;
2072 val |= (coal & 0x3fff) << 8;
2074 wrlp(mp, SDMA_CONFIG, val);
2077 static void set_tx_coal(struct mv643xx_eth_private *mp, unsigned int delay)
2079 unsigned int coal = ((mp->shared->t_clk / 1000000) * delay) / 64;
2083 wrlp(mp, TX_FIFO_URGENT_THRESHOLD, (coal & 0x3fff) << 4);
2086 static void mv643xx_eth_recalc_skb_size(struct mv643xx_eth_private *mp)
2091 * Reserve 2+14 bytes for an ethernet header (the hardware
2092 * automatically prepends 2 bytes of dummy data to each
2093 * received packet), 16 bytes for up to four VLAN tags, and
2094 * 4 bytes for the trailing FCS -- 36 bytes total.
2096 skb_size = mp->dev->mtu + 36;
2099 * Make sure that the skb size is a multiple of 8 bytes, as
2100 * the lower three bits of the receive descriptor's buffer
2101 * size field are ignored by the hardware.
2103 mp->skb_size = (skb_size + 7) & ~7;
2106 static int mv643xx_eth_open(struct net_device *dev)
2108 struct mv643xx_eth_private *mp = netdev_priv(dev);
2112 wrlp(mp, INT_CAUSE, 0);
2113 wrlp(mp, INT_CAUSE_EXT, 0);
2114 rdlp(mp, INT_CAUSE_EXT);
2116 err = request_irq(dev->irq, mv643xx_eth_irq,
2117 IRQF_SHARED, dev->name, dev);
2119 dev_printk(KERN_ERR, &dev->dev, "can't assign irq\n");
2123 mv643xx_eth_recalc_skb_size(mp);
2125 napi_enable(&mp->napi);
2127 skb_queue_head_init(&mp->rx_recycle);
2129 for (i = 0; i < mp->rxq_count; i++) {
2130 err = rxq_init(mp, i);
2133 rxq_deinit(mp->rxq + i);
2137 rxq_refill(mp->rxq + i, INT_MAX);
2140 if (mp->work_rx_oom) {
2141 mp->rx_oom.expires = jiffies + (HZ / 10);
2142 add_timer(&mp->rx_oom);
2145 for (i = 0; i < mp->txq_count; i++) {
2146 err = txq_init(mp, i);
2149 txq_deinit(mp->txq + i);
2154 netif_carrier_off(dev);
2161 wrlp(mp, INT_MASK_EXT, INT_EXT_LINK_PHY | INT_EXT_TX);
2162 wrlp(mp, INT_MASK, INT_TX_END | INT_RX | INT_EXT);
2168 for (i = 0; i < mp->rxq_count; i++)
2169 rxq_deinit(mp->rxq + i);
2171 free_irq(dev->irq, dev);
2176 static void port_reset(struct mv643xx_eth_private *mp)
2181 for (i = 0; i < mp->rxq_count; i++)
2182 rxq_disable(mp->rxq + i);
2183 for (i = 0; i < mp->txq_count; i++)
2184 txq_disable(mp->txq + i);
2187 u32 ps = rdlp(mp, PORT_STATUS);
2189 if ((ps & (TX_IN_PROGRESS | TX_FIFO_EMPTY)) == TX_FIFO_EMPTY)
2194 /* Reset the Enable bit in the Configuration Register */
2195 data = rdlp(mp, PORT_SERIAL_CONTROL);
2196 data &= ~(SERIAL_PORT_ENABLE |
2197 DO_NOT_FORCE_LINK_FAIL |
2199 wrlp(mp, PORT_SERIAL_CONTROL, data);
2202 static int mv643xx_eth_stop(struct net_device *dev)
2204 struct mv643xx_eth_private *mp = netdev_priv(dev);
2207 wrlp(mp, INT_MASK, 0x00000000);
2210 del_timer_sync(&mp->mib_counters_timer);
2212 napi_disable(&mp->napi);
2214 del_timer_sync(&mp->rx_oom);
2216 netif_carrier_off(dev);
2218 free_irq(dev->irq, dev);
2221 mv643xx_eth_get_stats(dev);
2222 mib_counters_update(mp);
2224 skb_queue_purge(&mp->rx_recycle);
2226 for (i = 0; i < mp->rxq_count; i++)
2227 rxq_deinit(mp->rxq + i);
2228 for (i = 0; i < mp->txq_count; i++)
2229 txq_deinit(mp->txq + i);
2234 static int mv643xx_eth_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2236 struct mv643xx_eth_private *mp = netdev_priv(dev);
2238 if (mp->phy != NULL)
2239 return phy_mii_ioctl(mp->phy, if_mii(ifr), cmd);
2244 static int mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu)
2246 struct mv643xx_eth_private *mp = netdev_priv(dev);
2248 if (new_mtu < 64 || new_mtu > 9500)
2252 mv643xx_eth_recalc_skb_size(mp);
2253 tx_set_rate(mp, 1000000000, 16777216);
2255 if (!netif_running(dev))
2259 * Stop and then re-open the interface. This will allocate RX
2260 * skbs of the new MTU.
2261 * There is a possible danger that the open will not succeed,
2262 * due to memory being full.
2264 mv643xx_eth_stop(dev);
2265 if (mv643xx_eth_open(dev)) {
2266 dev_printk(KERN_ERR, &dev->dev,
2267 "fatal error on re-opening device after "
2274 static void tx_timeout_task(struct work_struct *ugly)
2276 struct mv643xx_eth_private *mp;
2278 mp = container_of(ugly, struct mv643xx_eth_private, tx_timeout_task);
2279 if (netif_running(mp->dev)) {
2280 netif_tx_stop_all_queues(mp->dev);
2283 netif_tx_wake_all_queues(mp->dev);
2287 static void mv643xx_eth_tx_timeout(struct net_device *dev)
2289 struct mv643xx_eth_private *mp = netdev_priv(dev);
2291 dev_printk(KERN_INFO, &dev->dev, "tx timeout\n");
2293 schedule_work(&mp->tx_timeout_task);
2296 #ifdef CONFIG_NET_POLL_CONTROLLER
2297 static void mv643xx_eth_netpoll(struct net_device *dev)
2299 struct mv643xx_eth_private *mp = netdev_priv(dev);
2301 wrlp(mp, INT_MASK, 0x00000000);
2304 mv643xx_eth_irq(dev->irq, dev);
2306 wrlp(mp, INT_MASK, INT_TX_END | INT_RX | INT_EXT);
2311 /* platform glue ************************************************************/
2313 mv643xx_eth_conf_mbus_windows(struct mv643xx_eth_shared_private *msp,
2314 struct mbus_dram_target_info *dram)
2316 void __iomem *base = msp->base;
2321 for (i = 0; i < 6; i++) {
2322 writel(0, base + WINDOW_BASE(i));
2323 writel(0, base + WINDOW_SIZE(i));
2325 writel(0, base + WINDOW_REMAP_HIGH(i));
2331 for (i = 0; i < dram->num_cs; i++) {
2332 struct mbus_dram_window *cs = dram->cs + i;
2334 writel((cs->base & 0xffff0000) |
2335 (cs->mbus_attr << 8) |
2336 dram->mbus_dram_target_id, base + WINDOW_BASE(i));
2337 writel((cs->size - 1) & 0xffff0000, base + WINDOW_SIZE(i));
2339 win_enable &= ~(1 << i);
2340 win_protect |= 3 << (2 * i);
2343 writel(win_enable, base + WINDOW_BAR_ENABLE);
2344 msp->win_protect = win_protect;
2347 static void infer_hw_params(struct mv643xx_eth_shared_private *msp)
2350 * Check whether we have a 14-bit coal limit field in bits
2351 * [21:8], or a 16-bit coal limit in bits [25,21:7] of the
2352 * SDMA config register.
2354 writel(0x02000000, msp->base + 0x0400 + SDMA_CONFIG);
2355 if (readl(msp->base + 0x0400 + SDMA_CONFIG) & 0x02000000)
2356 msp->extended_rx_coal_limit = 1;
2358 msp->extended_rx_coal_limit = 0;
2361 * Check whether the MAC supports TX rate control, and if
2362 * yes, whether its associated registers are in the old or
2365 writel(1, msp->base + 0x0400 + TX_BW_MTU_MOVED);
2366 if (readl(msp->base + 0x0400 + TX_BW_MTU_MOVED) & 1) {
2367 msp->tx_bw_control = TX_BW_CONTROL_NEW_LAYOUT;
2369 writel(7, msp->base + 0x0400 + TX_BW_RATE);
2370 if (readl(msp->base + 0x0400 + TX_BW_RATE) & 7)
2371 msp->tx_bw_control = TX_BW_CONTROL_OLD_LAYOUT;
2373 msp->tx_bw_control = TX_BW_CONTROL_ABSENT;
2377 static int mv643xx_eth_shared_probe(struct platform_device *pdev)
2379 static int mv643xx_eth_version_printed;
2380 struct mv643xx_eth_shared_platform_data *pd = pdev->dev.platform_data;
2381 struct mv643xx_eth_shared_private *msp;
2382 struct resource *res;
2385 if (!mv643xx_eth_version_printed++)
2386 printk(KERN_NOTICE "MV-643xx 10/100/1000 ethernet "
2387 "driver version %s\n", mv643xx_eth_driver_version);
2390 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2395 msp = kmalloc(sizeof(*msp), GFP_KERNEL);
2398 memset(msp, 0, sizeof(*msp));
2400 msp->base = ioremap(res->start, res->end - res->start + 1);
2401 if (msp->base == NULL)
2405 * Set up and register SMI bus.
2407 if (pd == NULL || pd->shared_smi == NULL) {
2408 msp->smi_bus = mdiobus_alloc();
2409 if (msp->smi_bus == NULL)
2412 msp->smi_bus->priv = msp;
2413 msp->smi_bus->name = "mv643xx_eth smi";
2414 msp->smi_bus->read = smi_bus_read;
2415 msp->smi_bus->write = smi_bus_write,
2416 snprintf(msp->smi_bus->id, MII_BUS_ID_SIZE, "%d", pdev->id);
2417 msp->smi_bus->parent = &pdev->dev;
2418 msp->smi_bus->phy_mask = 0xffffffff;
2419 if (mdiobus_register(msp->smi_bus) < 0)
2420 goto out_free_mii_bus;
2423 msp->smi = platform_get_drvdata(pd->shared_smi);
2426 msp->err_interrupt = NO_IRQ;
2427 init_waitqueue_head(&msp->smi_busy_wait);
2430 * Check whether the error interrupt is hooked up.
2432 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2436 err = request_irq(res->start, mv643xx_eth_err_irq,
2437 IRQF_SHARED, "mv643xx_eth", msp);
2439 writel(ERR_INT_SMI_DONE, msp->base + ERR_INT_MASK);
2440 msp->err_interrupt = res->start;
2445 * (Re-)program MBUS remapping windows if we are asked to.
2447 if (pd != NULL && pd->dram != NULL)
2448 mv643xx_eth_conf_mbus_windows(msp, pd->dram);
2451 * Detect hardware parameters.
2453 msp->t_clk = (pd != NULL && pd->t_clk != 0) ? pd->t_clk : 133000000;
2454 infer_hw_params(msp);
2456 platform_set_drvdata(pdev, msp);
2461 mdiobus_free(msp->smi_bus);
2470 static int mv643xx_eth_shared_remove(struct platform_device *pdev)
2472 struct mv643xx_eth_shared_private *msp = platform_get_drvdata(pdev);
2473 struct mv643xx_eth_shared_platform_data *pd = pdev->dev.platform_data;
2475 if (pd == NULL || pd->shared_smi == NULL) {
2476 mdiobus_free(msp->smi_bus);
2477 mdiobus_unregister(msp->smi_bus);
2479 if (msp->err_interrupt != NO_IRQ)
2480 free_irq(msp->err_interrupt, msp);
2487 static struct platform_driver mv643xx_eth_shared_driver = {
2488 .probe = mv643xx_eth_shared_probe,
2489 .remove = mv643xx_eth_shared_remove,
2491 .name = MV643XX_ETH_SHARED_NAME,
2492 .owner = THIS_MODULE,
2496 static void phy_addr_set(struct mv643xx_eth_private *mp, int phy_addr)
2498 int addr_shift = 5 * mp->port_num;
2501 data = rdl(mp, PHY_ADDR);
2502 data &= ~(0x1f << addr_shift);
2503 data |= (phy_addr & 0x1f) << addr_shift;
2504 wrl(mp, PHY_ADDR, data);
2507 static int phy_addr_get(struct mv643xx_eth_private *mp)
2511 data = rdl(mp, PHY_ADDR);
2513 return (data >> (5 * mp->port_num)) & 0x1f;
2516 static void set_params(struct mv643xx_eth_private *mp,
2517 struct mv643xx_eth_platform_data *pd)
2519 struct net_device *dev = mp->dev;
2521 if (is_valid_ether_addr(pd->mac_addr))
2522 memcpy(dev->dev_addr, pd->mac_addr, 6);
2524 uc_addr_get(mp, dev->dev_addr);
2526 mp->default_rx_ring_size = DEFAULT_RX_QUEUE_SIZE;
2527 if (pd->rx_queue_size)
2528 mp->default_rx_ring_size = pd->rx_queue_size;
2529 mp->rx_desc_sram_addr = pd->rx_sram_addr;
2530 mp->rx_desc_sram_size = pd->rx_sram_size;
2532 mp->rxq_count = pd->rx_queue_count ? : 1;
2534 mp->default_tx_ring_size = DEFAULT_TX_QUEUE_SIZE;
2535 if (pd->tx_queue_size)
2536 mp->default_tx_ring_size = pd->tx_queue_size;
2537 mp->tx_desc_sram_addr = pd->tx_sram_addr;
2538 mp->tx_desc_sram_size = pd->tx_sram_size;
2540 mp->txq_count = pd->tx_queue_count ? : 1;
2543 static struct phy_device *phy_scan(struct mv643xx_eth_private *mp,
2546 struct mii_bus *bus = mp->shared->smi->smi_bus;
2547 struct phy_device *phydev;
2552 if (phy_addr == MV643XX_ETH_PHY_ADDR_DEFAULT) {
2553 start = phy_addr_get(mp) & 0x1f;
2556 start = phy_addr & 0x1f;
2561 for (i = 0; i < num; i++) {
2562 int addr = (start + i) & 0x1f;
2564 if (bus->phy_map[addr] == NULL)
2565 mdiobus_scan(bus, addr);
2567 if (phydev == NULL) {
2568 phydev = bus->phy_map[addr];
2570 phy_addr_set(mp, addr);
2577 static void phy_init(struct mv643xx_eth_private *mp, int speed, int duplex)
2579 struct phy_device *phy = mp->phy;
2583 phy_attach(mp->dev, phy->dev.bus_id, 0, PHY_INTERFACE_MODE_GMII);
2586 phy->autoneg = AUTONEG_ENABLE;
2589 phy->advertising = phy->supported | ADVERTISED_Autoneg;
2591 phy->autoneg = AUTONEG_DISABLE;
2592 phy->advertising = 0;
2594 phy->duplex = duplex;
2596 phy_start_aneg(phy);
2599 static void init_pscr(struct mv643xx_eth_private *mp, int speed, int duplex)
2603 pscr = rdlp(mp, PORT_SERIAL_CONTROL);
2604 if (pscr & SERIAL_PORT_ENABLE) {
2605 pscr &= ~SERIAL_PORT_ENABLE;
2606 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
2609 pscr = MAX_RX_PACKET_9700BYTE | SERIAL_PORT_CONTROL_RESERVED;
2610 if (mp->phy == NULL) {
2611 pscr |= DISABLE_AUTO_NEG_SPEED_GMII;
2612 if (speed == SPEED_1000)
2613 pscr |= SET_GMII_SPEED_TO_1000;
2614 else if (speed == SPEED_100)
2615 pscr |= SET_MII_SPEED_TO_100;
2617 pscr |= DISABLE_AUTO_NEG_FOR_FLOW_CTRL;
2619 pscr |= DISABLE_AUTO_NEG_FOR_DUPLEX;
2620 if (duplex == DUPLEX_FULL)
2621 pscr |= SET_FULL_DUPLEX_MODE;
2624 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
2627 static int mv643xx_eth_probe(struct platform_device *pdev)
2629 struct mv643xx_eth_platform_data *pd;
2630 struct mv643xx_eth_private *mp;
2631 struct net_device *dev;
2632 struct resource *res;
2635 pd = pdev->dev.platform_data;
2637 dev_printk(KERN_ERR, &pdev->dev,
2638 "no mv643xx_eth_platform_data\n");
2642 if (pd->shared == NULL) {
2643 dev_printk(KERN_ERR, &pdev->dev,
2644 "no mv643xx_eth_platform_data->shared\n");
2648 dev = alloc_etherdev_mq(sizeof(struct mv643xx_eth_private), 8);
2652 mp = netdev_priv(dev);
2653 platform_set_drvdata(pdev, mp);
2655 mp->shared = platform_get_drvdata(pd->shared);
2656 mp->base = mp->shared->base + 0x0400 + (pd->port_number << 10);
2657 mp->port_num = pd->port_number;
2662 dev->real_num_tx_queues = mp->txq_count;
2664 if (pd->phy_addr != MV643XX_ETH_PHY_NONE)
2665 mp->phy = phy_scan(mp, pd->phy_addr);
2667 if (mp->phy != NULL) {
2668 phy_init(mp, pd->speed, pd->duplex);
2669 SET_ETHTOOL_OPS(dev, &mv643xx_eth_ethtool_ops);
2671 SET_ETHTOOL_OPS(dev, &mv643xx_eth_ethtool_ops_phyless);
2674 init_pscr(mp, pd->speed, pd->duplex);
2677 mib_counters_clear(mp);
2679 init_timer(&mp->mib_counters_timer);
2680 mp->mib_counters_timer.data = (unsigned long)mp;
2681 mp->mib_counters_timer.function = mib_counters_timer_wrapper;
2682 mp->mib_counters_timer.expires = jiffies + 30 * HZ;
2683 add_timer(&mp->mib_counters_timer);
2685 spin_lock_init(&mp->mib_counters_lock);
2687 INIT_WORK(&mp->tx_timeout_task, tx_timeout_task);
2689 netif_napi_add(dev, &mp->napi, mv643xx_eth_poll, 128);
2691 init_timer(&mp->rx_oom);
2692 mp->rx_oom.data = (unsigned long)mp;
2693 mp->rx_oom.function = oom_timer_wrapper;
2696 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2698 dev->irq = res->start;
2700 dev->get_stats = mv643xx_eth_get_stats;
2701 dev->hard_start_xmit = mv643xx_eth_xmit;
2702 dev->open = mv643xx_eth_open;
2703 dev->stop = mv643xx_eth_stop;
2704 dev->set_rx_mode = mv643xx_eth_set_rx_mode;
2705 dev->set_mac_address = mv643xx_eth_set_mac_address;
2706 dev->do_ioctl = mv643xx_eth_ioctl;
2707 dev->change_mtu = mv643xx_eth_change_mtu;
2708 dev->tx_timeout = mv643xx_eth_tx_timeout;
2709 #ifdef CONFIG_NET_POLL_CONTROLLER
2710 dev->poll_controller = mv643xx_eth_netpoll;
2712 dev->watchdog_timeo = 2 * HZ;
2715 dev->features = NETIF_F_SG | NETIF_F_IP_CSUM;
2716 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM;
2718 SET_NETDEV_DEV(dev, &pdev->dev);
2720 if (mp->shared->win_protect)
2721 wrl(mp, WINDOW_PROTECT(mp->port_num), mp->shared->win_protect);
2723 err = register_netdev(dev);
2727 dev_printk(KERN_NOTICE, &dev->dev, "port %d with MAC address %pM\n",
2728 mp->port_num, dev->dev_addr);
2730 if (mp->tx_desc_sram_size > 0)
2731 dev_printk(KERN_NOTICE, &dev->dev, "configured with sram\n");
2741 static int mv643xx_eth_remove(struct platform_device *pdev)
2743 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
2745 unregister_netdev(mp->dev);
2746 if (mp->phy != NULL)
2747 phy_detach(mp->phy);
2748 flush_scheduled_work();
2749 free_netdev(mp->dev);
2751 platform_set_drvdata(pdev, NULL);
2756 static void mv643xx_eth_shutdown(struct platform_device *pdev)
2758 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
2760 /* Mask all interrupts on ethernet port */
2761 wrlp(mp, INT_MASK, 0);
2764 if (netif_running(mp->dev))
2768 static struct platform_driver mv643xx_eth_driver = {
2769 .probe = mv643xx_eth_probe,
2770 .remove = mv643xx_eth_remove,
2771 .shutdown = mv643xx_eth_shutdown,
2773 .name = MV643XX_ETH_NAME,
2774 .owner = THIS_MODULE,
2778 static int __init mv643xx_eth_init_module(void)
2782 rc = platform_driver_register(&mv643xx_eth_shared_driver);
2784 rc = platform_driver_register(&mv643xx_eth_driver);
2786 platform_driver_unregister(&mv643xx_eth_shared_driver);
2791 module_init(mv643xx_eth_init_module);
2793 static void __exit mv643xx_eth_cleanup_module(void)
2795 platform_driver_unregister(&mv643xx_eth_driver);
2796 platform_driver_unregister(&mv643xx_eth_shared_driver);
2798 module_exit(mv643xx_eth_cleanup_module);
2800 MODULE_AUTHOR("Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, "
2801 "Manish Lachwani, Dale Farnsworth and Lennert Buytenhek");
2802 MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX");
2803 MODULE_LICENSE("GPL");
2804 MODULE_ALIAS("platform:" MV643XX_ETH_SHARED_NAME);
2805 MODULE_ALIAS("platform:" MV643XX_ETH_NAME);