drivers/net/niu.c

   1 /* niu.c: Neptune ethernet driver.
   2  *
   3  * Copyright (C) 2007 David S. Miller (davem@davemloft.net)
   4  */
   5
   6 #include <linux/module.h>
   7 #include <linux/init.h>
   8 #include <linux/pci.h>
   9 #include <linux/dma-mapping.h>
  10 #include <linux/netdevice.h>
  11 #include <linux/ethtool.h>
  12 #include <linux/etherdevice.h>
  13 #include <linux/platform_device.h>
  14 #include <linux/delay.h>
  15 #include <linux/bitops.h>
  16 #include <linux/mii.h>
  17 #include <linux/if_ether.h>
  18 #include <linux/if_vlan.h>
  19 #include <linux/ip.h>
  20 #include <linux/in.h>
  21 #include <linux/ipv6.h>
  22 #include <linux/log2.h>
  23 #include <linux/jiffies.h>
  24 #include <linux/crc32.h>
  25
  26 #include <linux/io.h>
  27
  28 #ifdef CONFIG_SPARC64
  29 #include <linux/of_device.h>
  30 #endif
  31
  32 #include "niu.h"
  33
  34 #define DRV_MODULE_NAME         "niu"
  35 #define PFX DRV_MODULE_NAME     ": "
  36 #define DRV_MODULE_VERSION      "0.7"
  37 #define DRV_MODULE_RELDATE      "February 18, 2008"
  38
  39 static char version[] __devinitdata =
  40         DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
  41
  42 MODULE_AUTHOR("David S. Miller (davem@davemloft.net)");
  43 MODULE_DESCRIPTION("NIU ethernet driver");
  44 MODULE_LICENSE("GPL");
  45 MODULE_VERSION(DRV_MODULE_VERSION);
  46
  47 #ifndef DMA_44BIT_MASK
  48 #define DMA_44BIT_MASK  0x00000fffffffffffULL
  49 #endif
  50
  51 #ifndef readq
  52 static u64 readq(void __iomem *reg)
  53 {
  54         return (((u64)readl(reg + 0x4UL) << 32) |
  55                 (u64)readl(reg));
  56 }
  57
  58 static void writeq(u64 val, void __iomem *reg)
  59 {
  60         writel(val & 0xffffffff, reg);
  61         writel(val >> 32, reg + 0x4UL);
  62 }
  63 #endif
  64
  65 static struct pci_device_id niu_pci_tbl[] = {
  66         {PCI_DEVICE(PCI_VENDOR_ID_SUN, 0xabcd)},
  67         {}
  68 };
  69
  70 MODULE_DEVICE_TABLE(pci, niu_pci_tbl);
  71
  72 #define NIU_TX_TIMEOUT                  (5 * HZ)
  73
  74 #define nr64(reg)               readq(np->regs + (reg))
  75 #define nw64(reg, val)          writeq((val), np->regs + (reg))
  76
  77 #define nr64_mac(reg)           readq(np->mac_regs + (reg))
  78 #define nw64_mac(reg, val)      writeq((val), np->mac_regs + (reg))
  79
  80 #define nr64_ipp(reg)           readq(np->regs + np->ipp_off + (reg))
  81 #define nw64_ipp(reg, val)      writeq((val), np->regs + np->ipp_off + (reg))
  82
  83 #define nr64_pcs(reg)           readq(np->regs + np->pcs_off + (reg))
  84 #define nw64_pcs(reg, val)      writeq((val), np->regs + np->pcs_off + (reg))
  85
  86 #define nr64_xpcs(reg)          readq(np->regs + np->xpcs_off + (reg))
  87 #define nw64_xpcs(reg, val)     writeq((val), np->regs + np->xpcs_off + (reg))
  88
  89 #define NIU_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK)
  90
  91 static int niu_debug;
  92 static int debug = -1;
  93 module_param(debug, int, 0);
  94 MODULE_PARM_DESC(debug, "NIU debug level");
  95
  96 #define niudbg(TYPE, f, a...) \
  97 do {    if ((np)->msg_enable & NETIF_MSG_##TYPE) \
  98                 printk(KERN_DEBUG PFX f, ## a); \
  99 } while (0)
 100
 101 #define niuinfo(TYPE, f, a...) \
 102 do {    if ((np)->msg_enable & NETIF_MSG_##TYPE) \
 103                 printk(KERN_INFO PFX f, ## a); \
 104 } while (0)
 105
 106 #define niuwarn(TYPE, f, a...) \
 107 do {    if ((np)->msg_enable & NETIF_MSG_##TYPE) \
 108                 printk(KERN_WARNING PFX f, ## a); \
 109 } while (0)
 110
 111 #define niu_lock_parent(np, flags) \
 112         spin_lock_irqsave(&np->parent->lock, flags)
 113 #define niu_unlock_parent(np, flags) \
 114         spin_unlock_irqrestore(&np->parent->lock, flags)
 115
 116 static int serdes_init_10g_serdes(struct niu *np);
 117
 118 static int __niu_wait_bits_clear_mac(struct niu *np, unsigned long reg,
 119                                      u64 bits, int limit, int delay)
 120 {
 121         while (--limit >= 0) {
 122                 u64 val = nr64_mac(reg);
 123
 124                 if (!(val & bits))
 125                         break;
 126                 udelay(delay);
 127         }
 128         if (limit < 0)
 129                 return -ENODEV;
 130         return 0;
 131 }
 132
 133 static int __niu_set_and_wait_clear_mac(struct niu *np, unsigned long reg,
 134                                         u64 bits, int limit, int delay,
 135                                         const char *reg_name)
 136 {
 137         int err;
 138
 139         nw64_mac(reg, bits);
 140         err = __niu_wait_bits_clear_mac(np, reg, bits, limit, delay);
 141         if (err)
 142                 dev_err(np->device, PFX "%s: bits (%llx) of register %s "
 143                         "would not clear, val[%llx]\n",
 144                         np->dev->name, (unsigned long long) bits, reg_name,
 145                         (unsigned long long) nr64_mac(reg));
 146         return err;
 147 }
 148
 149 #define niu_set_and_wait_clear_mac(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \
 150 ({      BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
 151         __niu_set_and_wait_clear_mac(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \
 152 })
 153
 154 static int __niu_wait_bits_clear_ipp(struct niu *np, unsigned long reg,
 155                                      u64 bits, int limit, int delay)
 156 {
 157         while (--limit >= 0) {
 158                 u64 val = nr64_ipp(reg);
 159
 160                 if (!(val & bits))
 161                         break;
 162                 udelay(delay);
 163         }
 164         if (limit < 0)
 165                 return -ENODEV;
 166         return 0;
 167 }
 168
 169 static int __niu_set_and_wait_clear_ipp(struct niu *np, unsigned long reg,
 170                                         u64 bits, int limit, int delay,
 171                                         const char *reg_name)
 172 {
 173         int err;
 174         u64 val;
 175
 176         val = nr64_ipp(reg);
 177         val |= bits;
 178         nw64_ipp(reg, val);
 179
 180         err = __niu_wait_bits_clear_ipp(np, reg, bits, limit, delay);
 181         if (err)
 182                 dev_err(np->device, PFX "%s: bits (%llx) of register %s "
 183                         "would not clear, val[%llx]\n",
 184                         np->dev->name, (unsigned long long) bits, reg_name,
 185                         (unsigned long long) nr64_ipp(reg));
 186         return err;
 187 }
 188
 189 #define niu_set_and_wait_clear_ipp(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \
 190 ({      BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
 191         __niu_set_and_wait_clear_ipp(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \
 192 })
 193
 194 static int __niu_wait_bits_clear(struct niu *np, unsigned long reg,
 195                                  u64 bits, int limit, int delay)
 196 {
 197         while (--limit >= 0) {
 198                 u64 val = nr64(reg);
 199
 200                 if (!(val & bits))
 201                         break;
 202                 udelay(delay);
 203         }
 204         if (limit < 0)
 205                 return -ENODEV;
 206         return 0;
 207 }
 208
 209 #define niu_wait_bits_clear(NP, REG, BITS, LIMIT, DELAY) \
 210 ({      BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
 211         __niu_wait_bits_clear(NP, REG, BITS, LIMIT, DELAY); \
 212 })
 213
 214 static int __niu_set_and_wait_clear(struct niu *np, unsigned long reg,
 215                                     u64 bits, int limit, int delay,
 216                                     const char *reg_name)
 217 {
 218         int err;
 219
 220         nw64(reg, bits);
 221         err = __niu_wait_bits_clear(np, reg, bits, limit, delay);
 222         if (err)
 223                 dev_err(np->device, PFX "%s: bits (%llx) of register %s "
 224                         "would not clear, val[%llx]\n",
 225                         np->dev->name, (unsigned long long) bits, reg_name,
 226                         (unsigned long long) nr64(reg));
 227         return err;
 228 }
 229
 230 #define niu_set_and_wait_clear(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \
 231 ({      BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
 232         __niu_set_and_wait_clear(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \
 233 })
 234
 235 static void niu_ldg_rearm(struct niu *np, struct niu_ldg *lp, int on)
 236 {
 237         u64 val = (u64) lp->timer;
 238
 239         if (on)
 240                 val |= LDG_IMGMT_ARM;
 241
 242         nw64(LDG_IMGMT(lp->ldg_num), val);
 243 }
 244
 245 static int niu_ldn_irq_enable(struct niu *np, int ldn, int on)
 246 {
 247         unsigned long mask_reg, bits;
 248         u64 val;
 249
 250         if (ldn < 0 || ldn > LDN_MAX)
 251                 return -EINVAL;
 252
 253         if (ldn < 64) {
 254                 mask_reg = LD_IM0(ldn);
 255                 bits = LD_IM0_MASK;
 256         } else {
 257                 mask_reg = LD_IM1(ldn - 64);
 258                 bits = LD_IM1_MASK;
 259         }
 260
 261         val = nr64(mask_reg);
 262         if (on)
 263                 val &= ~bits;
 264         else
 265                 val |= bits;
 266         nw64(mask_reg, val);
 267
 268         return 0;
 269 }
 270
 271 static int niu_enable_ldn_in_ldg(struct niu *np, struct niu_ldg *lp, int on)
 272 {
 273         struct niu_parent *parent = np->parent;
 274         int i;
 275
 276         for (i = 0; i <= LDN_MAX; i++) {
 277                 int err;
 278
 279                 if (parent->ldg_map[i] != lp->ldg_num)
 280                         continue;
 281
 282                 err = niu_ldn_irq_enable(np, i, on);
 283                 if (err)
 284                         return err;
 285         }
 286         return 0;
 287 }
 288
 289 static int niu_enable_interrupts(struct niu *np, int on)
 290 {
 291         int i;
 292
 293         for (i = 0; i < np->num_ldg; i++) {
 294                 struct niu_ldg *lp = &np->ldg[i];
 295                 int err;
 296
 297                 err = niu_enable_ldn_in_ldg(np, lp, on);
 298                 if (err)
 299                         return err;
 300         }
 301         for (i = 0; i < np->num_ldg; i++)
 302                 niu_ldg_rearm(np, &np->ldg[i], on);
 303
 304         return 0;
 305 }
 306
 307 static u32 phy_encode(u32 type, int port)
 308 {
 309         return (type << (port * 2));
 310 }
 311
 312 static u32 phy_decode(u32 val, int port)
 313 {
 314         return (val >> (port * 2)) & PORT_TYPE_MASK;
 315 }
 316
 317 static int mdio_wait(struct niu *np)
 318 {
 319         int limit = 1000;
 320         u64 val;
 321
 322         while (--limit > 0) {
 323                 val = nr64(MIF_FRAME_OUTPUT);
 324                 if ((val >> MIF_FRAME_OUTPUT_TA_SHIFT) & 0x1)
 325                         return val & MIF_FRAME_OUTPUT_DATA;
 326
 327                 udelay(10);
 328         }
 329
 330         return -ENODEV;
 331 }
 332
 333 static int mdio_read(struct niu *np, int port, int dev, int reg)
 334 {
 335         int err;
 336
 337         nw64(MIF_FRAME_OUTPUT, MDIO_ADDR_OP(port, dev, reg));
 338         err = mdio_wait(np);
 339         if (err < 0)
 340                 return err;
 341
 342         nw64(MIF_FRAME_OUTPUT, MDIO_READ_OP(port, dev));
 343         return mdio_wait(np);
 344 }
 345
 346 static int mdio_write(struct niu *np, int port, int dev, int reg, int data)
 347 {
 348         int err;
 349
 350         nw64(MIF_FRAME_OUTPUT, MDIO_ADDR_OP(port, dev, reg));
 351         err = mdio_wait(np);
 352         if (err < 0)
 353                 return err;
 354
 355         nw64(MIF_FRAME_OUTPUT, MDIO_WRITE_OP(port, dev, data));
 356         err = mdio_wait(np);
 357         if (err < 0)
 358                 return err;
 359
 360         return 0;
 361 }
 362
 363 static int mii_read(struct niu *np, int port, int reg)
 364 {
 365         nw64(MIF_FRAME_OUTPUT, MII_READ_OP(port, reg));
 366         return mdio_wait(np);
 367 }
 368
 369 static int mii_write(struct niu *np, int port, int reg, int data)
 370 {
 371         int err;
 372
 373         nw64(MIF_FRAME_OUTPUT, MII_WRITE_OP(port, reg, data));
 374         err = mdio_wait(np);
 375         if (err < 0)
 376                 return err;
 377
 378         return 0;
 379 }
 380
 381 static int esr2_set_tx_cfg(struct niu *np, unsigned long channel, u32 val)
 382 {
 383         int err;
 384
 385         err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
 386                          ESR2_TI_PLL_TX_CFG_L(channel),
 387                          val & 0xffff);
 388         if (!err)
 389                 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
 390                                  ESR2_TI_PLL_TX_CFG_H(channel),
 391                                  val >> 16);
 392         return err;
 393 }
 394
 395 static int esr2_set_rx_cfg(struct niu *np, unsigned long channel, u32 val)
 396 {
 397         int err;
 398
 399         err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
 400                          ESR2_TI_PLL_RX_CFG_L(channel),
 401                          val & 0xffff);
 402         if (!err)
 403                 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
 404                                  ESR2_TI_PLL_RX_CFG_H(channel),
 405                                  val >> 16);
 406         return err;
 407 }
 408
 409 /* Mode is always 10G fiber.  */
 410 static int serdes_init_niu(struct niu *np)
 411 {
 412         struct niu_link_config *lp = &np->link_config;
 413         u32 tx_cfg, rx_cfg;
 414         unsigned long i;
 415
 416         tx_cfg = (PLL_TX_CFG_ENTX | PLL_TX_CFG_SWING_1375MV);
 417         rx_cfg = (PLL_RX_CFG_ENRX | PLL_RX_CFG_TERM_0P8VDDT |
 418                   PLL_RX_CFG_ALIGN_ENA | PLL_RX_CFG_LOS_LTHRESH |
 419                   PLL_RX_CFG_EQ_LP_ADAPTIVE);
 420
 421         if (lp->loopback_mode == LOOPBACK_PHY) {
 422                 u16 test_cfg = PLL_TEST_CFG_LOOPBACK_CML_DIS;
 423
 424                 mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
 425                            ESR2_TI_PLL_TEST_CFG_L, test_cfg);
 426
 427                 tx_cfg |= PLL_TX_CFG_ENTEST;
 428                 rx_cfg |= PLL_RX_CFG_ENTEST;
 429         }
 430
 431         /* Initialize all 4 lanes of the SERDES.  */
 432         for (i = 0; i < 4; i++) {
 433                 int err = esr2_set_tx_cfg(np, i, tx_cfg);
 434                 if (err)
 435                         return err;
 436         }
 437
 438         for (i = 0; i < 4; i++) {
 439                 int err = esr2_set_rx_cfg(np, i, rx_cfg);
 440                 if (err)
 441                         return err;
 442         }
 443
 444         return 0;
 445 }
 446
 447 static int esr_read_rxtx_ctrl(struct niu *np, unsigned long chan, u32 *val)
 448 {
 449         int err;
 450
 451         err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR, ESR_RXTX_CTRL_L(chan));
 452         if (err >= 0) {
 453                 *val = (err & 0xffff);
 454                 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
 455                                 ESR_RXTX_CTRL_H(chan));
 456                 if (err >= 0)
 457                         *val |= ((err & 0xffff) << 16);
 458                 err = 0;
 459         }
 460         return err;
 461 }
 462
 463 static int esr_read_glue0(struct niu *np, unsigned long chan, u32 *val)
 464 {
 465         int err;
 466
 467         err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
 468                         ESR_GLUE_CTRL0_L(chan));
 469         if (err >= 0) {
 470                 *val = (err & 0xffff);
 471                 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
 472                                 ESR_GLUE_CTRL0_H(chan));
 473                 if (err >= 0) {
 474                         *val |= ((err & 0xffff) << 16);
 475                         err = 0;
 476                 }
 477         }
 478         return err;
 479 }
 480
 481 static int esr_read_reset(struct niu *np, u32 *val)
 482 {
 483         int err;
 484
 485         err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
 486                         ESR_RXTX_RESET_CTRL_L);
 487         if (err >= 0) {
 488                 *val = (err & 0xffff);
 489                 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
 490                                 ESR_RXTX_RESET_CTRL_H);
 491                 if (err >= 0) {
 492                         *val |= ((err & 0xffff) << 16);
 493                         err = 0;
 494                 }
 495         }
 496         return err;
 497 }
 498
 499 static int esr_write_rxtx_ctrl(struct niu *np, unsigned long chan, u32 val)
 500 {
 501         int err;
 502
 503         err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
 504                          ESR_RXTX_CTRL_L(chan), val & 0xffff);
 505         if (!err)
 506                 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
 507                                  ESR_RXTX_CTRL_H(chan), (val >> 16));
 508         return err;
 509 }
 510
 511 static int esr_write_glue0(struct niu *np, unsigned long chan, u32 val)
 512 {
 513         int err;
 514
 515         err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
 516                         ESR_GLUE_CTRL0_L(chan), val & 0xffff);
 517         if (!err)
 518                 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
 519                                  ESR_GLUE_CTRL0_H(chan), (val >> 16));
 520         return err;
 521 }
 522
 523 static int esr_reset(struct niu *np)
 524 {
 525         u32 reset;
 526         int err;
 527
 528         err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
 529                          ESR_RXTX_RESET_CTRL_L, 0x0000);
 530         if (err)
 531                 return err;
 532         err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
 533                          ESR_RXTX_RESET_CTRL_H, 0xffff);
 534         if (err)
 535                 return err;
 536         udelay(200);
 537
 538         err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
 539                          ESR_RXTX_RESET_CTRL_L, 0xffff);
 540         if (err)
 541                 return err;
 542         udelay(200);
 543
 544         err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
 545                          ESR_RXTX_RESET_CTRL_H, 0x0000);
 546         if (err)
 547                 return err;
 548         udelay(200);
 549
 550         err = esr_read_reset(np, &reset);
 551         if (err)
 552                 return err;
 553         if (reset != 0) {
 554                 dev_err(np->device, PFX "Port %u ESR_RESET "
 555                         "did not clear [%08x]\n",
 556                         np->port, reset);
 557                 return -ENODEV;
 558         }
 559
 560         return 0;
 561 }
 562
 563 static int serdes_init_10g(struct niu *np)
 564 {
 565         struct niu_link_config *lp = &np->link_config;
 566         unsigned long ctrl_reg, test_cfg_reg, i;
 567         u64 ctrl_val, test_cfg_val, sig, mask, val;
 568         int err;
 569
 570         switch (np->port) {
 571         case 0:
 572                 ctrl_reg = ENET_SERDES_0_CTRL_CFG;
 573                 test_cfg_reg = ENET_SERDES_0_TEST_CFG;
 574                 break;
 575         case 1:
 576                 ctrl_reg = ENET_SERDES_1_CTRL_CFG;
 577                 test_cfg_reg = ENET_SERDES_1_TEST_CFG;
 578                 break;
 579
 580         default:
 581                 return -EINVAL;
 582         }
 583         ctrl_val = (ENET_SERDES_CTRL_SDET_0 |
 584                     ENET_SERDES_CTRL_SDET_1 |
 585                     ENET_SERDES_CTRL_SDET_2 |
 586                     ENET_SERDES_CTRL_SDET_3 |
 587                     (0x5 << ENET_SERDES_CTRL_EMPH_0_SHIFT) |
 588                     (0x5 << ENET_SERDES_CTRL_EMPH_1_SHIFT) |
 589                     (0x5 << ENET_SERDES_CTRL_EMPH_2_SHIFT) |
 590                     (0x5 << ENET_SERDES_CTRL_EMPH_3_SHIFT) |
 591                     (0x1 << ENET_SERDES_CTRL_LADJ_0_SHIFT) |
 592                     (0x1 << ENET_SERDES_CTRL_LADJ_1_SHIFT) |
 593                     (0x1 << ENET_SERDES_CTRL_LADJ_2_SHIFT) |
 594                     (0x1 << ENET_SERDES_CTRL_LADJ_3_SHIFT));
 595         test_cfg_val = 0;
 596
 597         if (lp->loopback_mode == LOOPBACK_PHY) {
 598                 test_cfg_val |= ((ENET_TEST_MD_PAD_LOOPBACK <<
 599                                   ENET_SERDES_TEST_MD_0_SHIFT) |
 600                                  (ENET_TEST_MD_PAD_LOOPBACK <<
 601                                   ENET_SERDES_TEST_MD_1_SHIFT) |
 602                                  (ENET_TEST_MD_PAD_LOOPBACK <<
 603                                   ENET_SERDES_TEST_MD_2_SHIFT) |
 604                                  (ENET_TEST_MD_PAD_LOOPBACK <<
 605                                   ENET_SERDES_TEST_MD_3_SHIFT));
 606         }
 607
 608         nw64(ctrl_reg, ctrl_val);
 609         nw64(test_cfg_reg, test_cfg_val);
 610
 611         /* Initialize all 4 lanes of the SERDES.  */
 612         for (i = 0; i < 4; i++) {
 613                 u32 rxtx_ctrl, glue0;
 614
 615                 err = esr_read_rxtx_ctrl(np, i, &rxtx_ctrl);
 616                 if (err)
 617                         return err;
 618                 err = esr_read_glue0(np, i, &glue0);
 619                 if (err)
 620                         return err;
 621
 622                 rxtx_ctrl &= ~(ESR_RXTX_CTRL_VMUXLO);
 623                 rxtx_ctrl |= (ESR_RXTX_CTRL_ENSTRETCH |
 624                               (2 << ESR_RXTX_CTRL_VMUXLO_SHIFT));
 625
 626                 glue0 &= ~(ESR_GLUE_CTRL0_SRATE |
 627                            ESR_GLUE_CTRL0_THCNT |
 628                            ESR_GLUE_CTRL0_BLTIME);
 629                 glue0 |= (ESR_GLUE_CTRL0_RXLOSENAB |
 630                           (0xf << ESR_GLUE_CTRL0_SRATE_SHIFT) |
 631                           (0xff << ESR_GLUE_CTRL0_THCNT_SHIFT) |
 632                           (BLTIME_300_CYCLES <<
 633                            ESR_GLUE_CTRL0_BLTIME_SHIFT));
 634
 635                 err = esr_write_rxtx_ctrl(np, i, rxtx_ctrl);
 636                 if (err)
 637                         return err;
 638                 err = esr_write_glue0(np, i, glue0);
 639                 if (err)
 640                         return err;
 641         }
 642
 643         err = esr_reset(np);
 644         if (err)
 645                 return err;
 646
 647         sig = nr64(ESR_INT_SIGNALS);
 648         switch (np->port) {
 649         case 0:
 650                 mask = ESR_INT_SIGNALS_P0_BITS;
 651                 val = (ESR_INT_SRDY0_P0 |
 652                        ESR_INT_DET0_P0 |
 653                        ESR_INT_XSRDY_P0 |
 654                        ESR_INT_XDP_P0_CH3 |
 655                        ESR_INT_XDP_P0_CH2 |
 656                        ESR_INT_XDP_P0_CH1 |
 657                        ESR_INT_XDP_P0_CH0);
 658                 break;
 659
 660         case 1:
 661                 mask = ESR_INT_SIGNALS_P1_BITS;
 662                 val = (ESR_INT_SRDY0_P1 |
 663                        ESR_INT_DET0_P1 |
 664                        ESR_INT_XSRDY_P1 |
 665                        ESR_INT_XDP_P1_CH3 |
 666                        ESR_INT_XDP_P1_CH2 |
 667                        ESR_INT_XDP_P1_CH1 |
 668                        ESR_INT_XDP_P1_CH0);
 669                 break;
 670
 671         default:
 672                 return -EINVAL;
 673         }
 674
 675         if ((sig & mask) != val) {
 676                 dev_err(np->device, PFX "Port %u signal bits [%08x] are not "
 677                         "[%08x]\n", np->port, (int) (sig & mask), (int) val);
 678                 return -ENODEV;
 679         }
 680
 681         return 0;
 682 }
 683
 684 static int serdes_init_1g(struct niu *np)
 685 {
 686         u64 val;
 687
 688         val = nr64(ENET_SERDES_1_PLL_CFG);
 689         val &= ~ENET_SERDES_PLL_FBDIV2;
 690         switch (np->port) {
 691         case 0:
 692                 val |= ENET_SERDES_PLL_HRATE0;
 693                 break;
 694         case 1:
 695                 val |= ENET_SERDES_PLL_HRATE1;
 696                 break;
 697         case 2:
 698                 val |= ENET_SERDES_PLL_HRATE2;
 699                 break;
 700         case 3:
 701                 val |= ENET_SERDES_PLL_HRATE3;
 702                 break;
 703         default:
 704                 return -EINVAL;
 705         }
 706         nw64(ENET_SERDES_1_PLL_CFG, val);
 707
 708         return 0;
 709 }
 710
 711 static int serdes_init_1g_serdes(struct niu *np)
 712 {
 713         struct niu_link_config *lp = &np->link_config;
 714         unsigned long ctrl_reg, test_cfg_reg, pll_cfg, i;
 715         u64 ctrl_val, test_cfg_val, sig, mask, val;
 716         int err;
 717         u64 reset_val, val_rd;
 718
 719         val = ENET_SERDES_PLL_HRATE0 | ENET_SERDES_PLL_HRATE1 |
 720                 ENET_SERDES_PLL_HRATE2 | ENET_SERDES_PLL_HRATE3 |
 721                 ENET_SERDES_PLL_FBDIV0;
 722         switch (np->port) {
 723         case 0:
 724                 reset_val =  ENET_SERDES_RESET_0;
 725                 ctrl_reg = ENET_SERDES_0_CTRL_CFG;
 726                 test_cfg_reg = ENET_SERDES_0_TEST_CFG;
 727                 pll_cfg = ENET_SERDES_0_PLL_CFG;
 728                 break;
 729         case 1:
 730                 reset_val =  ENET_SERDES_RESET_1;
 731                 ctrl_reg = ENET_SERDES_1_CTRL_CFG;
 732                 test_cfg_reg = ENET_SERDES_1_TEST_CFG;
 733                 pll_cfg = ENET_SERDES_1_PLL_CFG;
 734                 break;
 735
 736         default:
 737                 return -EINVAL;
 738         }
 739         ctrl_val = (ENET_SERDES_CTRL_SDET_0 |
 740                     ENET_SERDES_CTRL_SDET_1 |
 741                     ENET_SERDES_CTRL_SDET_2 |
 742                     ENET_SERDES_CTRL_SDET_3 |
 743                     (0x5 << ENET_SERDES_CTRL_EMPH_0_SHIFT) |
 744                     (0x5 << ENET_SERDES_CTRL_EMPH_1_SHIFT) |
 745                     (0x5 << ENET_SERDES_CTRL_EMPH_2_SHIFT) |
 746                     (0x5 << ENET_SERDES_CTRL_EMPH_3_SHIFT) |
 747                     (0x1 << ENET_SERDES_CTRL_LADJ_0_SHIFT) |
 748                     (0x1 << ENET_SERDES_CTRL_LADJ_1_SHIFT) |
 749                     (0x1 << ENET_SERDES_CTRL_LADJ_2_SHIFT) |
 750                     (0x1 << ENET_SERDES_CTRL_LADJ_3_SHIFT));
 751         test_cfg_val = 0;
 752
 753         if (lp->loopback_mode == LOOPBACK_PHY) {
 754                 test_cfg_val |= ((ENET_TEST_MD_PAD_LOOPBACK <<
 755                                   ENET_SERDES_TEST_MD_0_SHIFT) |
 756                                  (ENET_TEST_MD_PAD_LOOPBACK <<
 757                                   ENET_SERDES_TEST_MD_1_SHIFT) |
 758                                  (ENET_TEST_MD_PAD_LOOPBACK <<
 759                                   ENET_SERDES_TEST_MD_2_SHIFT) |
 760                                  (ENET_TEST_MD_PAD_LOOPBACK <<
 761                                   ENET_SERDES_TEST_MD_3_SHIFT));
 762         }
 763
 764         nw64(ENET_SERDES_RESET, reset_val);
 765         mdelay(20);
 766         val_rd = nr64(ENET_SERDES_RESET);
 767         val_rd &= ~reset_val;
 768         nw64(pll_cfg, val);
 769         nw64(ctrl_reg, ctrl_val);
 770         nw64(test_cfg_reg, test_cfg_val);
 771         nw64(ENET_SERDES_RESET, val_rd);
 772         mdelay(2000);
 773
 774         /* Initialize all 4 lanes of the SERDES.  */
 775         for (i = 0; i < 4; i++) {
 776                 u32 rxtx_ctrl, glue0;
 777
 778                 err = esr_read_rxtx_ctrl(np, i, &rxtx_ctrl);
 779                 if (err)
 780                         return err;
 781                 err = esr_read_glue0(np, i, &glue0);
 782                 if (err)
 783                         return err;
 784
 785                 rxtx_ctrl &= ~(ESR_RXTX_CTRL_VMUXLO);
 786                 rxtx_ctrl |= (ESR_RXTX_CTRL_ENSTRETCH |
 787                               (2 << ESR_RXTX_CTRL_VMUXLO_SHIFT));
 788
 789                 glue0 &= ~(ESR_GLUE_CTRL0_SRATE |
 790                            ESR_GLUE_CTRL0_THCNT |
 791                            ESR_GLUE_CTRL0_BLTIME);
 792                 glue0 |= (ESR_GLUE_CTRL0_RXLOSENAB |
 793                           (0xf << ESR_GLUE_CTRL0_SRATE_SHIFT) |
 794                           (0xff << ESR_GLUE_CTRL0_THCNT_SHIFT) |
 795                           (BLTIME_300_CYCLES <<
 796                            ESR_GLUE_CTRL0_BLTIME_SHIFT));
 797
 798                 err = esr_write_rxtx_ctrl(np, i, rxtx_ctrl);
 799                 if (err)
 800                         return err;
 801                 err = esr_write_glue0(np, i, glue0);
 802                 if (err)
 803                         return err;
 804         }
 805
 806
 807         sig = nr64(ESR_INT_SIGNALS);
 808         switch (np->port) {
 809         case 0:
 810                 val = (ESR_INT_SRDY0_P0 | ESR_INT_DET0_P0);
 811                 mask = val;
 812                 break;
 813
 814         case 1:
 815                 val = (ESR_INT_SRDY0_P1 | ESR_INT_DET0_P1);
 816                 mask = val;
 817                 break;
 818
 819         default:
 820                 return -EINVAL;
 821         }
 822
 823         if ((sig & mask) != val) {
 824                 dev_err(np->device, PFX "Port %u signal bits [%08x] are not "
 825                         "[%08x]\n", np->port, (int) (sig & mask), (int) val);
 826                 return -ENODEV;
 827         }
 828
 829         return 0;
 830 }
 831
 832 static int link_status_1g_serdes(struct niu *np, int *link_up_p)
 833 {
 834         struct niu_link_config *lp = &np->link_config;
 835         int link_up;
 836         u64 val;
 837         u16 current_speed;
 838         unsigned long flags;
 839         u8 current_duplex;
 840
 841         link_up = 0;
 842         current_speed = SPEED_INVALID;
 843         current_duplex = DUPLEX_INVALID;
 844
 845         spin_lock_irqsave(&np->lock, flags);
 846
 847         val = nr64_pcs(PCS_MII_STAT);
 848
 849         if (val & PCS_MII_STAT_LINK_STATUS) {
 850                 link_up = 1;
 851                 current_speed = SPEED_1000;
 852                 current_duplex = DUPLEX_FULL;
 853         }
 854
 855         lp->active_speed = current_speed;
 856         lp->active_duplex = current_duplex;
 857         spin_unlock_irqrestore(&np->lock, flags);
 858
 859         *link_up_p = link_up;
 860         return 0;
 861 }
 862
 863
 864 static int link_status_10g_serdes(struct niu *np, int *link_up_p)
 865 {
 866         unsigned long flags;
 867         struct niu_link_config *lp = &np->link_config;
 868         int link_up = 0;
 869         int link_ok = 1;
 870         u64 val, val2;
 871         u16 current_speed;
 872         u8 current_duplex;
 873
 874         if (!(np->flags & NIU_FLAGS_10G))
 875                 return link_status_1g_serdes(np, link_up_p);
 876
 877         current_speed = SPEED_INVALID;
 878         current_duplex = DUPLEX_INVALID;
 879         spin_lock_irqsave(&np->lock, flags);
 880
 881         val = nr64_xpcs(XPCS_STATUS(0));
 882         val2 = nr64_mac(XMAC_INTER2);
 883         if (val2 & 0x01000000)
 884                 link_ok = 0;
 885
 886         if ((val & 0x1000ULL) && link_ok) {
 887                 link_up = 1;
 888                 current_speed = SPEED_10000;
 889                 current_duplex = DUPLEX_FULL;
 890         }
 891         lp->active_speed = current_speed;
 892         lp->active_duplex = current_duplex;
 893         spin_unlock_irqrestore(&np->lock, flags);
 894         *link_up_p = link_up;
 895         return 0;
 896 }
 897
 898
 899 static int link_status_1g_rgmii(struct niu *np, int *link_up_p)
 900 {
 901         struct niu_link_config *lp = &np->link_config;
 902         u16 current_speed, bmsr;
 903         unsigned long flags;
 904         u8 current_duplex;
 905         int err, link_up;
 906
 907         link_up = 0;
 908         current_speed = SPEED_INVALID;
 909         current_duplex = DUPLEX_INVALID;
 910
 911         spin_lock_irqsave(&np->lock, flags);
 912
 913         err = -EINVAL;
 914
 915         err = mii_read(np, np->phy_addr, MII_BMSR);
 916         if (err < 0)
 917                 goto out;
 918
 919         bmsr = err;
 920         if (bmsr & BMSR_LSTATUS) {
 921                 u16 adv, lpa, common, estat;
 922
 923                 err = mii_read(np, np->phy_addr, MII_ADVERTISE);
 924                 if (err < 0)
 925                         goto out;
 926                 adv = err;
 927
 928                 err = mii_read(np, np->phy_addr, MII_LPA);
 929                 if (err < 0)
 930                         goto out;
 931                 lpa = err;
 932
 933                 common = adv & lpa;
 934
 935                 err = mii_read(np, np->phy_addr, MII_ESTATUS);
 936                 if (err < 0)
 937                         goto out;
 938                 estat = err;
 939                 link_up = 1;
 940                 current_speed = SPEED_1000;
 941                 current_duplex = DUPLEX_FULL;
 942
 943         }
 944         lp->active_speed = current_speed;
 945         lp->active_duplex = current_duplex;
 946         err = 0;
 947
 948 out:
 949         spin_unlock_irqrestore(&np->lock, flags);
 950
 951         *link_up_p = link_up;
 952         return err;
 953 }
 954
 955
 956 static int bcm8704_reset(struct niu *np)
 957 {
 958         int err, limit;
 959
 960         err = mdio_read(np, np->phy_addr,
 961                         BCM8704_PHYXS_DEV_ADDR, MII_BMCR);
 962         if (err < 0)
 963                 return err;
 964         err |= BMCR_RESET;
 965         err = mdio_write(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
 966                          MII_BMCR, err);
 967         if (err)
 968                 return err;
 969
 970         limit = 1000;
 971         while (--limit >= 0) {
 972                 err = mdio_read(np, np->phy_addr,
 973                                 BCM8704_PHYXS_DEV_ADDR, MII_BMCR);
 974                 if (err < 0)
 975                         return err;
 976                 if (!(err & BMCR_RESET))
 977                         break;
 978         }
 979         if (limit < 0) {
 980                 dev_err(np->device, PFX "Port %u PHY will not reset "
 981                         "(bmcr=%04x)\n", np->port, (err & 0xffff));
 982                 return -ENODEV;
 983         }
 984         return 0;
 985 }
 986
 987 /* When written, certain PHY registers need to be read back twice
 988  * in order for the bits to settle properly.
 989  */
 990 static int bcm8704_user_dev3_readback(struct niu *np, int reg)
 991 {
 992         int err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, reg);
 993         if (err < 0)
 994                 return err;
 995         err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, reg);
 996         if (err < 0)
 997                 return err;
 998         return 0;
 999 }
1000
1001 static int bcm8704_init_user_dev3(struct niu *np)
1002 {
1003         int err;
1004
1005         err = mdio_write(np, np->phy_addr,
1006                          BCM8704_USER_DEV3_ADDR, BCM8704_USER_CONTROL,
1007                          (USER_CONTROL_OPTXRST_LVL |
1008                           USER_CONTROL_OPBIASFLT_LVL |
1009                           USER_CONTROL_OBTMPFLT_LVL |
1010                           USER_CONTROL_OPPRFLT_LVL |
1011                           USER_CONTROL_OPTXFLT_LVL |
1012                           USER_CONTROL_OPRXLOS_LVL |
1013                           USER_CONTROL_OPRXFLT_LVL |
1014                           USER_CONTROL_OPTXON_LVL |
1015                           (0x3f << USER_CONTROL_RES1_SHIFT)));
1016         if (err)
1017                 return err;
1018
1019         err = mdio_write(np, np->phy_addr,
1020                          BCM8704_USER_DEV3_ADDR, BCM8704_USER_PMD_TX_CONTROL,
1021                          (USER_PMD_TX_CTL_XFP_CLKEN |
1022                           (1 << USER_PMD_TX_CTL_TX_DAC_TXD_SH) |
1023                           (2 << USER_PMD_TX_CTL_TX_DAC_TXCK_SH) |
1024                           USER_PMD_TX_CTL_TSCK_LPWREN));
1025         if (err)
1026                 return err;
1027
1028         err = bcm8704_user_dev3_readback(np, BCM8704_USER_CONTROL);
1029         if (err)
1030                 return err;
1031         err = bcm8704_user_dev3_readback(np, BCM8704_USER_PMD_TX_CONTROL);
1032         if (err)
1033                 return err;
1034
1035         err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1036                         BCM8704_USER_OPT_DIGITAL_CTRL);
1037         if (err < 0)
1038                 return err;
1039         err &= ~USER_ODIG_CTRL_GPIOS;
1040         err |= (0x3 << USER_ODIG_CTRL_GPIOS_SHIFT);
1041         err = mdio_write(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1042                          BCM8704_USER_OPT_DIGITAL_CTRL, err);
1043         if (err)
1044                 return err;
1045
1046         mdelay(1000);
1047
1048         return 0;
1049 }
1050
1051 static int mrvl88x2011_act_led(struct niu *np, int val)
1052 {
1053         int     err;
1054
1055         err  = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR,
1056                 MRVL88X2011_LED_8_TO_11_CTL);
1057         if (err < 0)
1058                 return err;
1059
1060         err &= ~MRVL88X2011_LED(MRVL88X2011_LED_ACT,MRVL88X2011_LED_CTL_MASK);
1061         err |=  MRVL88X2011_LED(MRVL88X2011_LED_ACT,val);
1062
1063         return mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR,
1064                           MRVL88X2011_LED_8_TO_11_CTL, err);
1065 }
1066
1067 static int mrvl88x2011_led_blink_rate(struct niu *np, int rate)
1068 {
1069         int     err;
1070
1071         err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR,
1072                         MRVL88X2011_LED_BLINK_CTL);
1073         if (err >= 0) {
1074                 err &= ~MRVL88X2011_LED_BLKRATE_MASK;
1075                 err |= (rate << 4);
1076
1077                 err = mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR,
1078                                  MRVL88X2011_LED_BLINK_CTL, err);
1079         }
1080
1081         return err;
1082 }
1083
1084 static int xcvr_init_10g_mrvl88x2011(struct niu *np)
1085 {
1086         int     err;
1087
1088         /* Set LED functions */
1089         err = mrvl88x2011_led_blink_rate(np, MRVL88X2011_LED_BLKRATE_134MS);
1090         if (err)
1091                 return err;
1092
1093         /* led activity */
1094         err = mrvl88x2011_act_led(np, MRVL88X2011_LED_CTL_OFF);
1095         if (err)
1096                 return err;
1097
1098         err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,
1099                         MRVL88X2011_GENERAL_CTL);
1100         if (err < 0)
1101                 return err;
1102
1103         err |= MRVL88X2011_ENA_XFPREFCLK;
1104
1105         err = mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,
1106                          MRVL88X2011_GENERAL_CTL, err);
1107         if (err < 0)
1108                 return err;
1109
1110         err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1111                         MRVL88X2011_PMA_PMD_CTL_1);
1112         if (err < 0)
1113                 return err;
1114
1115         if (np->link_config.loopback_mode == LOOPBACK_MAC)
1116                 err |= MRVL88X2011_LOOPBACK;
1117         else
1118                 err &= ~MRVL88X2011_LOOPBACK;
1119
1120         err = mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1121                          MRVL88X2011_PMA_PMD_CTL_1, err);
1122         if (err < 0)
1123                 return err;
1124
1125         /* Enable PMD  */
1126         return mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1127                           MRVL88X2011_10G_PMD_TX_DIS, MRVL88X2011_ENA_PMDTX);
1128 }
1129
1130 static int xcvr_init_10g_bcm8704(struct niu *np)
1131 {
1132         struct niu_link_config *lp = &np->link_config;
1133         u16 analog_stat0, tx_alarm_status;
1134         int err;
1135
1136         err = bcm8704_reset(np);
1137         if (err)
1138                 return err;
1139
1140         err = bcm8704_init_user_dev3(np);
1141         if (err)
1142                 return err;
1143
1144         err = mdio_read(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
1145                         MII_BMCR);
1146         if (err < 0)
1147                 return err;
1148         err &= ~BMCR_LOOPBACK;
1149
1150         if (lp->loopback_mode == LOOPBACK_MAC)
1151                 err |= BMCR_LOOPBACK;
1152
1153         err = mdio_write(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
1154                          MII_BMCR, err);
1155         if (err)
1156                 return err;
1157
1158 #if 1
1159         err = mdio_read(np, np->phy_addr, BCM8704_PMA_PMD_DEV_ADDR,
1160                         MII_STAT1000);
1161         if (err < 0)
1162                 return err;
1163         pr_info(PFX "Port %u PMA_PMD(MII_STAT1000) [%04x]\n",
1164                 np->port, err);
1165
1166         err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, 0x20);
1167         if (err < 0)
1168                 return err;
1169         pr_info(PFX "Port %u USER_DEV3(0x20) [%04x]\n",
1170                 np->port, err);
1171
1172         err = mdio_read(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
1173                         MII_NWAYTEST);
1174         if (err < 0)
1175                 return err;
1176         pr_info(PFX "Port %u PHYXS(MII_NWAYTEST) [%04x]\n",
1177                 np->port, err);
1178 #endif
1179
1180         /* XXX dig this out it might not be so useful XXX */
1181         err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1182                         BCM8704_USER_ANALOG_STATUS0);
1183         if (err < 0)
1184                 return err;
1185         err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1186                         BCM8704_USER_ANALOG_STATUS0);
1187         if (err < 0)
1188                 return err;
1189         analog_stat0 = err;
1190
1191         err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1192                         BCM8704_USER_TX_ALARM_STATUS);
1193         if (err < 0)
1194                 return err;
1195         err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1196                         BCM8704_USER_TX_ALARM_STATUS);
1197         if (err < 0)
1198                 return err;
1199         tx_alarm_status = err;
1200
1201         if (analog_stat0 != 0x03fc) {
1202                 if ((analog_stat0 == 0x43bc) && (tx_alarm_status != 0)) {
1203                         pr_info(PFX "Port %u cable not connected "
1204                                 "or bad cable.\n", np->port);
1205                 } else if (analog_stat0 == 0x639c) {
1206                         pr_info(PFX "Port %u optical module is bad "
1207                                 "or missing.\n", np->port);
1208                 }
1209         }
1210
1211         return 0;
1212 }
1213
1214 static int xcvr_init_10g(struct niu *np)
1215 {
1216         int phy_id, err;
1217         u64 val;
1218
1219         val = nr64_mac(XMAC_CONFIG);
1220         val &= ~XMAC_CONFIG_LED_POLARITY;
1221         val |= XMAC_CONFIG_FORCE_LED_ON;
1222         nw64_mac(XMAC_CONFIG, val);
1223
1224         /* XXX shared resource, lock parent XXX */
1225         val = nr64(MIF_CONFIG);
1226         val |= MIF_CONFIG_INDIRECT_MODE;
1227         nw64(MIF_CONFIG, val);
1228
1229         phy_id = phy_decode(np->parent->port_phy, np->port);
1230         phy_id = np->parent->phy_probe_info.phy_id[phy_id][np->port];
1231
1232         /* handle different phy types */
1233         switch (phy_id & NIU_PHY_ID_MASK) {
1234         case NIU_PHY_ID_MRVL88X2011:
1235                 err = xcvr_init_10g_mrvl88x2011(np);
1236                 break;
1237
1238         default: /* bcom 8704 */
1239                 err = xcvr_init_10g_bcm8704(np);
1240                 break;
1241         }
1242
1243         return 0;
1244 }
1245
1246 static int mii_reset(struct niu *np)
1247 {
1248         int limit, err;
1249
1250         err = mii_write(np, np->phy_addr, MII_BMCR, BMCR_RESET);
1251         if (err)
1252                 return err;
1253
1254         limit = 1000;
1255         while (--limit >= 0) {
1256                 udelay(500);
1257                 err = mii_read(np, np->phy_addr, MII_BMCR);
1258                 if (err < 0)
1259                         return err;
1260                 if (!(err & BMCR_RESET))
1261                         break;
1262         }
1263         if (limit < 0) {
1264                 dev_err(np->device, PFX "Port %u MII would not reset, "
1265                         "bmcr[%04x]\n", np->port, err);
1266                 return -ENODEV;
1267         }
1268
1269         return 0;
1270 }
1271
1272
1273
1274 static int xcvr_init_1g_rgmii(struct niu *np)
1275 {
1276         int err;
1277         u64 val;
1278         u16 bmcr, bmsr, estat;
1279
1280         val = nr64(MIF_CONFIG);
1281         val &= ~MIF_CONFIG_INDIRECT_MODE;
1282         nw64(MIF_CONFIG, val);
1283
1284         err = mii_reset(np);
1285         if (err)
1286                 return err;
1287
1288         err = mii_read(np, np->phy_addr, MII_BMSR);
1289         if (err < 0)
1290                 return err;
1291         bmsr = err;
1292
1293         estat = 0;
1294         if (bmsr & BMSR_ESTATEN) {
1295                 err = mii_read(np, np->phy_addr, MII_ESTATUS);
1296                 if (err < 0)
1297                         return err;
1298                 estat = err;
1299         }
1300
1301         bmcr = 0;
1302         err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
1303         if (err)
1304                 return err;
1305
1306         if (bmsr & BMSR_ESTATEN) {
1307                 u16 ctrl1000 = 0;
1308
1309                 if (estat & ESTATUS_1000_TFULL)
1310                         ctrl1000 |= ADVERTISE_1000FULL;
1311                 err = mii_write(np, np->phy_addr, MII_CTRL1000, ctrl1000);
1312                 if (err)
1313                         return err;
1314         }
1315
1316         bmcr = (BMCR_SPEED1000 | BMCR_FULLDPLX);
1317
1318         err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
1319         if (err)
1320                 return err;
1321
1322         err = mii_read(np, np->phy_addr, MII_BMCR);
1323         if (err < 0)
1324                 return err;
1325         bmcr = mii_read(np, np->phy_addr, MII_BMCR);
1326
1327         err = mii_read(np, np->phy_addr, MII_BMSR);
1328         if (err < 0)
1329                 return err;
1330
1331         return 0;
1332 }
1333
1334
1335 static int mii_init_common(struct niu *np)
1336 {
1337         struct niu_link_config *lp = &np->link_config;
1338         u16 bmcr, bmsr, adv, estat;
1339         int err;
1340
1341         err = mii_reset(np);
1342         if (err)
1343                 return err;
1344
1345         err = mii_read(np, np->phy_addr, MII_BMSR);
1346         if (err < 0)
1347                 return err;
1348         bmsr = err;
1349
1350         estat = 0;
1351         if (bmsr & BMSR_ESTATEN) {
1352                 err = mii_read(np, np->phy_addr, MII_ESTATUS);
1353                 if (err < 0)
1354                         return err;
1355                 estat = err;
1356         }
1357
1358         bmcr = 0;
1359         err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
1360         if (err)
1361                 return err;
1362
1363         if (lp->loopback_mode == LOOPBACK_MAC) {
1364                 bmcr |= BMCR_LOOPBACK;
1365                 if (lp->active_speed == SPEED_1000)
1366                         bmcr |= BMCR_SPEED1000;
1367                 if (lp->active_duplex == DUPLEX_FULL)
1368                         bmcr |= BMCR_FULLDPLX;
1369         }
1370
1371         if (lp->loopback_mode == LOOPBACK_PHY) {
1372                 u16 aux;
1373
1374                 aux = (BCM5464R_AUX_CTL_EXT_LB |
1375                        BCM5464R_AUX_CTL_WRITE_1);
1376                 err = mii_write(np, np->phy_addr, BCM5464R_AUX_CTL, aux);
1377                 if (err)
1378                         return err;
1379         }
1380
1381         /* XXX configurable XXX */
1382         /* XXX for now don't advertise half-duplex or asym pause... XXX */
1383         adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP;
1384         if (bmsr & BMSR_10FULL)
1385                 adv |= ADVERTISE_10FULL;
1386         if (bmsr & BMSR_100FULL)
1387                 adv |= ADVERTISE_100FULL;
1388         err = mii_write(np, np->phy_addr, MII_ADVERTISE, adv);
1389         if (err)
1390                 return err;
1391
1392         if (bmsr & BMSR_ESTATEN) {
1393                 u16 ctrl1000 = 0;
1394
1395                 if (estat & ESTATUS_1000_TFULL)
1396                         ctrl1000 |= ADVERTISE_1000FULL;
1397                 err = mii_write(np, np->phy_addr, MII_CTRL1000, ctrl1000);
1398                 if (err)
1399                         return err;
1400         }
1401         bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
1402
1403         err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
1404         if (err)
1405                 return err;
1406
1407         err = mii_read(np, np->phy_addr, MII_BMCR);
1408         if (err < 0)
1409                 return err;
1410         err = mii_read(np, np->phy_addr, MII_BMSR);
1411         if (err < 0)
1412                 return err;
1413 #if 0
1414         pr_info(PFX "Port %u after MII init bmcr[%04x] bmsr[%04x]\n",
1415                 np->port, bmcr, bmsr);
1416 #endif
1417
1418         return 0;
1419 }
1420
1421 static int xcvr_init_1g(struct niu *np)
1422 {
1423         u64 val;
1424
1425         /* XXX shared resource, lock parent XXX */
1426         val = nr64(MIF_CONFIG);
1427         val &= ~MIF_CONFIG_INDIRECT_MODE;
1428         nw64(MIF_CONFIG, val);
1429
1430         return mii_init_common(np);
1431 }
1432
1433 static int niu_xcvr_init(struct niu *np)
1434 {
1435         const struct niu_phy_ops *ops = np->phy_ops;
1436         int err;
1437
1438         err = 0;
1439         if (ops->xcvr_init)
1440                 err = ops->xcvr_init(np);
1441
1442         return err;
1443 }
1444
1445 static int niu_serdes_init(struct niu *np)
1446 {
1447         const struct niu_phy_ops *ops = np->phy_ops;
1448         int err;
1449
1450         err = 0;
1451         if (ops->serdes_init)
1452                 err = ops->serdes_init(np);
1453
1454         return err;
1455 }
1456
1457 static void niu_init_xif(struct niu *);
1458 static void niu_handle_led(struct niu *, int status);
1459
1460 static int niu_link_status_common(struct niu *np, int link_up)
1461 {
1462         struct niu_link_config *lp = &np->link_config;
1463         struct net_device *dev = np->dev;
1464         unsigned long flags;
1465
1466         if (!netif_carrier_ok(dev) && link_up) {
1467                 niuinfo(LINK, "%s: Link is up at %s, %s duplex\n",
1468                        dev->name,
1469                        (lp->active_speed == SPEED_10000 ?
1470                         "10Gb/sec" :
1471                         (lp->active_speed == SPEED_1000 ?
1472                          "1Gb/sec" :
1473                          (lp->active_speed == SPEED_100 ?
1474                           "100Mbit/sec" : "10Mbit/sec"))),
1475                        (lp->active_duplex == DUPLEX_FULL ?
1476                         "full" : "half"));
1477
1478                 spin_lock_irqsave(&np->lock, flags);
1479                 niu_init_xif(np);
1480                 niu_handle_led(np, 1);
1481                 spin_unlock_irqrestore(&np->lock, flags);
1482
1483                 netif_carrier_on(dev);
1484         } else if (netif_carrier_ok(dev) && !link_up) {
1485                 niuwarn(LINK, "%s: Link is down\n", dev->name);
1486                 spin_lock_irqsave(&np->lock, flags);
1487                 niu_handle_led(np, 0);
1488                 spin_unlock_irqrestore(&np->lock, flags);
1489                 netif_carrier_off(dev);
1490         }
1491
1492         return 0;
1493 }
1494
1495 static int link_status_10g_mrvl(struct niu *np, int *link_up_p)
1496 {
1497         int err, link_up, pma_status, pcs_status;
1498
1499         link_up = 0;
1500
1501         err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1502                         MRVL88X2011_10G_PMD_STATUS_2);
1503         if (err < 0)
1504                 goto out;
1505
1506         /* Check PMA/PMD Register: 1.0001.2 == 1 */
1507         err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1508                         MRVL88X2011_PMA_PMD_STATUS_1);
1509         if (err < 0)
1510                 goto out;
1511
1512         pma_status = ((err & MRVL88X2011_LNK_STATUS_OK) ? 1 : 0);
1513
1514         /* Check PMC Register : 3.0001.2 == 1: read twice */
1515         err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,
1516                         MRVL88X2011_PMA_PMD_STATUS_1);
1517         if (err < 0)
1518                 goto out;
1519
1520         err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,
1521                         MRVL88X2011_PMA_PMD_STATUS_1);
1522         if (err < 0)
1523                 goto out;
1524
1525         pcs_status = ((err & MRVL88X2011_LNK_STATUS_OK) ? 1 : 0);
1526
1527         /* Check XGXS Register : 4.0018.[0-3,12] */
1528         err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV4_ADDR,
1529                         MRVL88X2011_10G_XGXS_LANE_STAT);
1530         if (err < 0)
1531                 goto out;
1532
1533         if (err == (PHYXS_XGXS_LANE_STAT_ALINGED | PHYXS_XGXS_LANE_STAT_LANE3 |
1534                     PHYXS_XGXS_LANE_STAT_LANE2 | PHYXS_XGXS_LANE_STAT_LANE1 |
1535                     PHYXS_XGXS_LANE_STAT_LANE0 | PHYXS_XGXS_LANE_STAT_MAGIC |
1536                     0x800))
1537                 link_up = (pma_status && pcs_status) ? 1 : 0;
1538
1539         np->link_config.active_speed = SPEED_10000;
1540         np->link_config.active_duplex = DUPLEX_FULL;
1541         err = 0;
1542 out:
1543         mrvl88x2011_act_led(np, (link_up ?
1544                                  MRVL88X2011_LED_CTL_PCS_ACT :
1545                                  MRVL88X2011_LED_CTL_OFF));
1546
1547         *link_up_p = link_up;
1548         return err;
1549 }
1550
1551 static int link_status_10g_bcom(struct niu *np, int *link_up_p)
1552 {
1553         int err, link_up;
1554
1555         link_up = 0;
1556
1557         err = mdio_read(np, np->phy_addr, BCM8704_PMA_PMD_DEV_ADDR,
1558                         BCM8704_PMD_RCV_SIGDET);
1559         if (err < 0)
1560                 goto out;
1561         if (!(err & PMD_RCV_SIGDET_GLOBAL)) {
1562                 err = 0;
1563                 goto out;
1564         }
1565
1566         err = mdio_read(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
1567                         BCM8704_PCS_10G_R_STATUS);
1568         if (err < 0)
1569                 goto out;
1570         if (!(err & PCS_10G_R_STATUS_BLK_LOCK)) {
1571                 err = 0;
1572                 goto out;
1573         }
1574
1575         err = mdio_read(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
1576                         BCM8704_PHYXS_XGXS_LANE_STAT);
1577         if (err < 0)
1578                 goto out;
1579
1580         if (err != (PHYXS_XGXS_LANE_STAT_ALINGED |
1581                     PHYXS_XGXS_LANE_STAT_MAGIC |
1582                     PHYXS_XGXS_LANE_STAT_LANE3 |
1583                     PHYXS_XGXS_LANE_STAT_LANE2 |
1584                     PHYXS_XGXS_LANE_STAT_LANE1 |
1585                     PHYXS_XGXS_LANE_STAT_LANE0)) {
1586                 err = 0;
1587                 goto out;
1588         }
1589
1590         link_up = 1;
1591         np->link_config.active_speed = SPEED_10000;
1592         np->link_config.active_duplex = DUPLEX_FULL;
1593         err = 0;
1594
1595 out:
1596         *link_up_p = link_up;
1597         return err;
1598 }
1599
1600 static int link_status_10g(struct niu *np, int *link_up_p)
1601 {
1602         unsigned long flags;
1603         int err = -EINVAL;
1604
1605         spin_lock_irqsave(&np->lock, flags);
1606
1607         if (np->link_config.loopback_mode == LOOPBACK_DISABLED) {
1608                 int phy_id;
1609
1610                 phy_id = phy_decode(np->parent->port_phy, np->port);
1611                 phy_id = np->parent->phy_probe_info.phy_id[phy_id][np->port];
1612
1613                 /* handle different phy types */
1614                 switch (phy_id & NIU_PHY_ID_MASK) {
1615                 case NIU_PHY_ID_MRVL88X2011:
1616                         err = link_status_10g_mrvl(np, link_up_p);
1617                         break;
1618
1619                 default: /* bcom 8704 */
1620                         err = link_status_10g_bcom(np, link_up_p);
1621                         break;
1622                 }
1623         }
1624
1625         spin_unlock_irqrestore(&np->lock, flags);
1626
1627         return err;
1628 }
1629
1630 static int link_status_1g(struct niu *np, int *link_up_p)
1631 {
1632         struct niu_link_config *lp = &np->link_config;
1633         u16 current_speed, bmsr;
1634         unsigned long flags;
1635         u8 current_duplex;
1636         int err, link_up;
1637
1638         link_up = 0;
1639         current_speed = SPEED_INVALID;
1640         current_duplex = DUPLEX_INVALID;
1641
1642         spin_lock_irqsave(&np->lock, flags);
1643
1644         err = -EINVAL;
1645         if (np->link_config.loopback_mode != LOOPBACK_DISABLED)
1646                 goto out;
1647
1648         err = mii_read(np, np->phy_addr, MII_BMSR);
1649         if (err < 0)
1650                 goto out;
1651
1652         bmsr = err;
1653         if (bmsr & BMSR_LSTATUS) {
1654                 u16 adv, lpa, common, estat;
1655
1656                 err = mii_read(np, np->phy_addr, MII_ADVERTISE);
1657                 if (err < 0)
1658                         goto out;
1659                 adv = err;
1660
1661                 err = mii_read(np, np->phy_addr, MII_LPA);
1662                 if (err < 0)
1663                         goto out;
1664                 lpa = err;
1665
1666                 common = adv & lpa;
1667
1668                 err = mii_read(np, np->phy_addr, MII_ESTATUS);
1669                 if (err < 0)
1670                         goto out;
1671                 estat = err;
1672
1673                 link_up = 1;
1674                 if (estat & (ESTATUS_1000_TFULL | ESTATUS_1000_THALF)) {
1675                         current_speed = SPEED_1000;
1676                         if (estat & ESTATUS_1000_TFULL)
1677                                 current_duplex = DUPLEX_FULL;
1678                         else
1679                                 current_duplex = DUPLEX_HALF;
1680                 } else {
1681                         if (common & ADVERTISE_100BASE4) {
1682                                 current_speed = SPEED_100;
1683                                 current_duplex = DUPLEX_HALF;
1684                         } else if (common & ADVERTISE_100FULL) {
1685                                 current_speed = SPEED_100;
1686                                 current_duplex = DUPLEX_FULL;
1687                         } else if (common & ADVERTISE_100HALF) {
1688                                 current_speed = SPEED_100;
1689                                 current_duplex = DUPLEX_HALF;
1690                         } else if (common & ADVERTISE_10FULL) {
1691                                 current_speed = SPEED_10;
1692                                 current_duplex = DUPLEX_FULL;
1693                         } else if (common & ADVERTISE_10HALF) {
1694                                 current_speed = SPEED_10;
1695                                 current_duplex = DUPLEX_HALF;
1696                         } else
1697                                 link_up = 0;
1698                 }
1699         }
1700         lp->active_speed = current_speed;
1701         lp->active_duplex = current_duplex;
1702         err = 0;
1703
1704 out:
1705         spin_unlock_irqrestore(&np->lock, flags);
1706
1707         *link_up_p = link_up;
1708         return err;
1709 }
1710
1711 static int niu_link_status(struct niu *np, int *link_up_p)
1712 {
1713         const struct niu_phy_ops *ops = np->phy_ops;
1714         int err;
1715
1716         err = 0;
1717         if (ops->link_status)
1718                 err = ops->link_status(np, link_up_p);
1719
1720         return err;
1721 }
1722
1723 static void niu_timer(unsigned long __opaque)
1724 {
1725         struct niu *np = (struct niu *) __opaque;
1726         unsigned long off;
1727         int err, link_up;
1728
1729         err = niu_link_status(np, &link_up);
1730         if (!err)
1731                 niu_link_status_common(np, link_up);
1732
1733         if (netif_carrier_ok(np->dev))
1734                 off = 5 * HZ;
1735         else
1736                 off = 1 * HZ;
1737         np->timer.expires = jiffies + off;
1738
1739         add_timer(&np->timer);
1740 }
1741
1742 static const struct niu_phy_ops phy_ops_10g_serdes = {
1743         .serdes_init            = serdes_init_10g_serdes,
1744         .link_status            = link_status_10g_serdes,
1745 };
1746
1747 static const struct niu_phy_ops phy_ops_1g_rgmii = {
1748         .xcvr_init              = xcvr_init_1g_rgmii,
1749         .link_status            = link_status_1g_rgmii,
1750 };
1751
1752 static const struct niu_phy_ops phy_ops_10g_fiber_niu = {
1753         .serdes_init            = serdes_init_niu,
1754         .xcvr_init              = xcvr_init_10g,
1755         .link_status            = link_status_10g,
1756 };
1757
1758 static const struct niu_phy_ops phy_ops_10g_fiber = {
1759         .serdes_init            = serdes_init_10g,
1760         .xcvr_init              = xcvr_init_10g,
1761         .link_status            = link_status_10g,
1762 };
1763
1764 static const struct niu_phy_ops phy_ops_10g_copper = {
1765         .serdes_init            = serdes_init_10g,
1766         .link_status            = link_status_10g, /* XXX */
1767 };
1768
1769 static const struct niu_phy_ops phy_ops_1g_fiber = {
1770         .serdes_init            = serdes_init_1g,
1771         .xcvr_init              = xcvr_init_1g,
1772         .link_status            = link_status_1g,
1773 };
1774
1775 static const struct niu_phy_ops phy_ops_1g_copper = {
1776         .xcvr_init              = xcvr_init_1g,
1777         .link_status            = link_status_1g,
1778 };
1779
1780 struct niu_phy_template {
1781         const struct niu_phy_ops        *ops;
1782         u32                             phy_addr_base;
1783 };
1784
1785 static const struct niu_phy_template phy_template_niu = {
1786         .ops            = &phy_ops_10g_fiber_niu,
1787         .phy_addr_base  = 16,
1788 };
1789
1790 static const struct niu_phy_template phy_template_10g_fiber = {
1791         .ops            = &phy_ops_10g_fiber,
1792         .phy_addr_base  = 8,
1793 };
1794
1795 static const struct niu_phy_template phy_template_10g_copper = {
1796         .ops            = &phy_ops_10g_copper,
1797         .phy_addr_base  = 10,
1798 };
1799
1800 static const struct niu_phy_template phy_template_1g_fiber = {
1801         .ops            = &phy_ops_1g_fiber,
1802         .phy_addr_base  = 0,
1803 };
1804
1805 static const struct niu_phy_template phy_template_1g_copper = {
1806         .ops            = &phy_ops_1g_copper,
1807         .phy_addr_base  = 0,
1808 };
1809
1810 static const struct niu_phy_template phy_template_1g_rgmii = {
1811         .ops            = &phy_ops_1g_rgmii,
1812         .phy_addr_base  = 0,
1813 };
1814
1815 static const struct niu_phy_template phy_template_10g_serdes = {
1816         .ops            = &phy_ops_10g_serdes,
1817         .phy_addr_base  = 0,
1818 };
1819
1820 static int niu_atca_port_num[4] = {
1821         0, 0,  11, 10
1822 };
1823
1824 static int serdes_init_10g_serdes(struct niu *np)
1825 {
1826         struct niu_link_config *lp = &np->link_config;
1827         unsigned long ctrl_reg, test_cfg_reg, pll_cfg, i;
1828         u64 ctrl_val, test_cfg_val, sig, mask, val;
1829         int err;
1830         u64 reset_val;
1831
1832         switch (np->port) {
1833         case 0:
1834                 reset_val =  ENET_SERDES_RESET_0;
1835                 ctrl_reg = ENET_SERDES_0_CTRL_CFG;
1836                 test_cfg_reg = ENET_SERDES_0_TEST_CFG;
1837                 pll_cfg = ENET_SERDES_0_PLL_CFG;
1838                 break;
1839         case 1:
1840                 reset_val =  ENET_SERDES_RESET_1;
1841                 ctrl_reg = ENET_SERDES_1_CTRL_CFG;
1842                 test_cfg_reg = ENET_SERDES_1_TEST_CFG;
1843                 pll_cfg = ENET_SERDES_1_PLL_CFG;
1844                 break;
1845
1846         default:
1847                 return -EINVAL;
1848         }
1849         ctrl_val = (ENET_SERDES_CTRL_SDET_0 |
1850                     ENET_SERDES_CTRL_SDET_1 |
1851                     ENET_SERDES_CTRL_SDET_2 |
1852                     ENET_SERDES_CTRL_SDET_3 |
1853                     (0x5 << ENET_SERDES_CTRL_EMPH_0_SHIFT) |
1854                     (0x5 << ENET_SERDES_CTRL_EMPH_1_SHIFT) |
1855                     (0x5 << ENET_SERDES_CTRL_EMPH_2_SHIFT) |
1856                     (0x5 << ENET_SERDES_CTRL_EMPH_3_SHIFT) |
1857                     (0x1 << ENET_SERDES_CTRL_LADJ_0_SHIFT) |
1858                     (0x1 << ENET_SERDES_CTRL_LADJ_1_SHIFT) |
1859                     (0x1 << ENET_SERDES_CTRL_LADJ_2_SHIFT) |
1860                     (0x1 << ENET_SERDES_CTRL_LADJ_3_SHIFT));
1861         test_cfg_val = 0;
1862
1863         if (lp->loopback_mode == LOOPBACK_PHY) {
1864                 test_cfg_val |= ((ENET_TEST_MD_PAD_LOOPBACK <<
1865                                   ENET_SERDES_TEST_MD_0_SHIFT) |
1866                                  (ENET_TEST_MD_PAD_LOOPBACK <<
1867                                   ENET_SERDES_TEST_MD_1_SHIFT) |
1868                                  (ENET_TEST_MD_PAD_LOOPBACK <<
1869                                   ENET_SERDES_TEST_MD_2_SHIFT) |
1870                                  (ENET_TEST_MD_PAD_LOOPBACK <<
1871                                   ENET_SERDES_TEST_MD_3_SHIFT));
1872         }
1873
1874         esr_reset(np);
1875         nw64(pll_cfg, ENET_SERDES_PLL_FBDIV2);
1876         nw64(ctrl_reg, ctrl_val);
1877         nw64(test_cfg_reg, test_cfg_val);
1878
1879         /* Initialize all 4 lanes of the SERDES.  */
1880         for (i = 0; i < 4; i++) {
1881                 u32 rxtx_ctrl, glue0;
1882
1883                 err = esr_read_rxtx_ctrl(np, i, &rxtx_ctrl);
1884                 if (err)
1885                         return err;
1886                 err = esr_read_glue0(np, i, &glue0);
1887                 if (err)
1888                         return err;
1889
1890                 rxtx_ctrl &= ~(ESR_RXTX_CTRL_VMUXLO);
1891                 rxtx_ctrl |= (ESR_RXTX_CTRL_ENSTRETCH |
1892                               (2 << ESR_RXTX_CTRL_VMUXLO_SHIFT));
1893
1894                 glue0 &= ~(ESR_GLUE_CTRL0_SRATE |
1895                            ESR_GLUE_CTRL0_THCNT |
1896                            ESR_GLUE_CTRL0_BLTIME);
1897                 glue0 |= (ESR_GLUE_CTRL0_RXLOSENAB |
1898                           (0xf << ESR_GLUE_CTRL0_SRATE_SHIFT) |
1899                           (0xff << ESR_GLUE_CTRL0_THCNT_SHIFT) |
1900                           (BLTIME_300_CYCLES <<
1901                            ESR_GLUE_CTRL0_BLTIME_SHIFT));
1902
1903                 err = esr_write_rxtx_ctrl(np, i, rxtx_ctrl);
1904                 if (err)
1905                         return err;
1906                 err = esr_write_glue0(np, i, glue0);
1907                 if (err)
1908                         return err;
1909         }
1910
1911
1912         sig = nr64(ESR_INT_SIGNALS);
1913         switch (np->port) {
1914         case 0:
1915                 mask = ESR_INT_SIGNALS_P0_BITS;
1916                 val = (ESR_INT_SRDY0_P0 |
1917                        ESR_INT_DET0_P0 |
1918                        ESR_INT_XSRDY_P0 |
1919                        ESR_INT_XDP_P0_CH3 |
1920                        ESR_INT_XDP_P0_CH2 |
1921                        ESR_INT_XDP_P0_CH1 |
1922                        ESR_INT_XDP_P0_CH0);
1923                 break;
1924
1925         case 1:
1926                 mask = ESR_INT_SIGNALS_P1_BITS;
1927                 val = (ESR_INT_SRDY0_P1 |
1928                        ESR_INT_DET0_P1 |
1929                        ESR_INT_XSRDY_P1 |
1930                        ESR_INT_XDP_P1_CH3 |
1931                        ESR_INT_XDP_P1_CH2 |
1932                        ESR_INT_XDP_P1_CH1 |
1933                        ESR_INT_XDP_P1_CH0);
1934                 break;
1935
1936         default:
1937                 return -EINVAL;
1938         }
1939
1940         if ((sig & mask) != val) {
1941                 int err;
1942                 err = serdes_init_1g_serdes(np);
1943                 if (!err) {
1944                         np->flags &= ~NIU_FLAGS_10G;
1945                         np->mac_xcvr = MAC_XCVR_PCS;
1946                 }  else {
1947                         dev_err(np->device, PFX "Port %u 10G/1G SERDES Link Failed \n",
1948                          np->port);
1949                         return -ENODEV;
1950                 }
1951         }
1952
1953         return 0;
1954 }
1955
1956 static int niu_determine_phy_disposition(struct niu *np)
1957 {
1958         struct niu_parent *parent = np->parent;
1959         u8 plat_type = parent->plat_type;
1960         const struct niu_phy_template *tp;
1961         u32 phy_addr_off = 0;
1962
1963         if (plat_type == PLAT_TYPE_NIU) {
1964                 tp = &phy_template_niu;
1965                 phy_addr_off += np->port;
1966         } else {
1967                 switch (np->flags &
1968                         (NIU_FLAGS_10G |
1969                          NIU_FLAGS_FIBER |
1970                          NIU_FLAGS_XCVR_SERDES)) {
1971                 case 0:
1972                         /* 1G copper */
1973                         tp = &phy_template_1g_copper;
1974                         if (plat_type == PLAT_TYPE_VF_P0)
1975                                 phy_addr_off = 10;
1976                         else if (plat_type == PLAT_TYPE_VF_P1)
1977                                 phy_addr_off = 26;
1978
1979                         phy_addr_off += (np->port ^ 0x3);
1980                         break;
1981
1982                 case NIU_FLAGS_10G:
1983                         /* 10G copper */
1984                         tp = &phy_template_1g_copper;
1985                         break;
1986
1987                 case NIU_FLAGS_FIBER:
1988                         /* 1G fiber */
1989                         tp = &phy_template_1g_fiber;
1990                         break;
1991
1992                 case NIU_FLAGS_10G | NIU_FLAGS_FIBER:
1993                         /* 10G fiber */
1994                         tp = &phy_template_10g_fiber;
1995                         if (plat_type == PLAT_TYPE_VF_P0 ||
1996                             plat_type == PLAT_TYPE_VF_P1)
1997                                 phy_addr_off = 8;
1998                         phy_addr_off += np->port;
1999                         break;
2000
2001                 case NIU_FLAGS_10G | NIU_FLAGS_XCVR_SERDES:
2002                 case NIU_FLAGS_XCVR_SERDES | NIU_FLAGS_FIBER:
2003                 case NIU_FLAGS_XCVR_SERDES:
2004                         switch(np->port) {
2005                         case 0:
2006                         case 1:
2007                                 tp = &phy_template_10g_serdes;
2008                                 break;
2009                         case 2:
2010                         case 3:
2011                                 tp = &phy_template_1g_rgmii;
2012                                 break;
2013                         default:
2014                                 return -EINVAL;
2015                                 break;
2016                         }
2017                         phy_addr_off = niu_atca_port_num[np->port];
2018                         break;
2019
2020                 default:
2021                         return -EINVAL;
2022                 }
2023         }
2024
2025         np->phy_ops = tp->ops;
2026         np->phy_addr = tp->phy_addr_base + phy_addr_off;
2027
2028         return 0;
2029 }
2030
2031 static int niu_init_link(struct niu *np)
2032 {
2033         struct niu_parent *parent = np->parent;
2034         int err, ignore;
2035
2036         if (parent->plat_type == PLAT_TYPE_NIU) {
2037                 err = niu_xcvr_init(np);
2038                 if (err)
2039                         return err;
2040                 msleep(200);
2041         }
2042         err = niu_serdes_init(np);
2043         if (err)
2044                 return err;
2045         msleep(200);
2046         err = niu_xcvr_init(np);
2047         if (!err)
2048                 niu_link_status(np, &ignore);
2049         return 0;
2050 }
2051
2052 static void niu_set_primary_mac(struct niu *np, unsigned char *addr)
2053 {
2054         u16 reg0 = addr[4] << 8 | addr[5];
2055         u16 reg1 = addr[2] << 8 | addr[3];
2056         u16 reg2 = addr[0] << 8 | addr[1];
2057
2058         if (np->flags & NIU_FLAGS_XMAC) {
2059                 nw64_mac(XMAC_ADDR0, reg0);
2060                 nw64_mac(XMAC_ADDR1, reg1);
2061                 nw64_mac(XMAC_ADDR2, reg2);
2062         } else {
2063                 nw64_mac(BMAC_ADDR0, reg0);
2064                 nw64_mac(BMAC_ADDR1, reg1);
2065                 nw64_mac(BMAC_ADDR2, reg2);
2066         }
2067 }
2068
2069 static int niu_num_alt_addr(struct niu *np)
2070 {
2071         if (np->flags & NIU_FLAGS_XMAC)
2072                 return XMAC_NUM_ALT_ADDR;
2073         else
2074                 return BMAC_NUM_ALT_ADDR;
2075 }
2076
2077 static int niu_set_alt_mac(struct niu *np, int index, unsigned char *addr)
2078 {
2079         u16 reg0 = addr[4] << 8 | addr[5];
2080         u16 reg1 = addr[2] << 8 | addr[3];
2081         u16 reg2 = addr[0] << 8 | addr[1];
2082
2083         if (index >= niu_num_alt_addr(np))
2084                 return -EINVAL;
2085
2086         if (np->flags & NIU_FLAGS_XMAC) {
2087                 nw64_mac(XMAC_ALT_ADDR0(index), reg0);
2088                 nw64_mac(XMAC_ALT_ADDR1(index), reg1);
2089                 nw64_mac(XMAC_ALT_ADDR2(index), reg2);
2090         } else {
2091                 nw64_mac(BMAC_ALT_ADDR0(index), reg0);
2092                 nw64_mac(BMAC_ALT_ADDR1(index), reg1);
2093                 nw64_mac(BMAC_ALT_ADDR2(index), reg2);
2094         }
2095
2096         return 0;
2097 }
2098
2099 static int niu_enable_alt_mac(struct niu *np, int index, int on)
2100 {
2101         unsigned long reg;
2102         u64 val, mask;
2103
2104         if (index >= niu_num_alt_addr(np))
2105                 return -EINVAL;
2106
2107         if (np->flags & NIU_FLAGS_XMAC) {
2108                 reg = XMAC_ADDR_CMPEN;
2109                 mask = 1 << index;
2110         } else {
2111                 reg = BMAC_ADDR_CMPEN;
2112                 mask = 1 << (index + 1);
2113         }
2114
2115         val = nr64_mac(reg);
2116         if (on)
2117                 val |= mask;
2118         else
2119                 val &= ~mask;
2120         nw64_mac(reg, val);
2121
2122         return 0;
2123 }
2124
2125 static void __set_rdc_table_num_hw(struct niu *np, unsigned long reg,
2126                                    int num, int mac_pref)
2127 {
2128         u64 val = nr64_mac(reg);
2129         val &= ~(HOST_INFO_MACRDCTBLN | HOST_INFO_MPR);
2130         val |= num;
2131         if (mac_pref)
2132                 val |= HOST_INFO_MPR;
2133         nw64_mac(reg, val);
2134 }
2135
2136 static int __set_rdc_table_num(struct niu *np,
2137                                int xmac_index, int bmac_index,
2138                                int rdc_table_num, int mac_pref)
2139 {
2140         unsigned long reg;
2141
2142         if (rdc_table_num & ~HOST_INFO_MACRDCTBLN)
2143                 return -EINVAL;
2144         if (np->flags & NIU_FLAGS_XMAC)
2145                 reg = XMAC_HOST_INFO(xmac_index);
2146         else
2147                 reg = BMAC_HOST_INFO(bmac_index);
2148         __set_rdc_table_num_hw(np, reg, rdc_table_num, mac_pref);
2149         return 0;
2150 }
2151
2152 static int niu_set_primary_mac_rdc_table(struct niu *np, int table_num,
2153                                          int mac_pref)
2154 {
2155         return __set_rdc_table_num(np, 17, 0, table_num, mac_pref);
2156 }
2157
2158 static int niu_set_multicast_mac_rdc_table(struct niu *np, int table_num,
2159                                            int mac_pref)
2160 {
2161         return __set_rdc_table_num(np, 16, 8, table_num, mac_pref);
2162 }
2163
2164 static int niu_set_alt_mac_rdc_table(struct niu *np, int idx,
2165                                      int table_num, int mac_pref)
2166 {
2167         if (idx >= niu_num_alt_addr(np))
2168                 return -EINVAL;
2169         return __set_rdc_table_num(np, idx, idx + 1, table_num, mac_pref);
2170 }
2171
2172 static u64 vlan_entry_set_parity(u64 reg_val)
2173 {
2174         u64 port01_mask;
2175         u64 port23_mask;
2176
2177         port01_mask = 0x00ff;
2178         port23_mask = 0xff00;
2179
2180         if (hweight64(reg_val & port01_mask) & 1)
2181                 reg_val |= ENET_VLAN_TBL_PARITY0;
2182         else
2183                 reg_val &= ~ENET_VLAN_TBL_PARITY0;
2184
2185         if (hweight64(reg_val & port23_mask) & 1)
2186                 reg_val |= ENET_VLAN_TBL_PARITY1;
2187         else
2188                 reg_val &= ~ENET_VLAN_TBL_PARITY1;
2189
2190         return reg_val;
2191 }
2192
2193 static void vlan_tbl_write(struct niu *np, unsigned long index,
2194                            int port, int vpr, int rdc_table)
2195 {
2196         u64 reg_val = nr64(ENET_VLAN_TBL(index));
2197
2198         reg_val &= ~((ENET_VLAN_TBL_VPR |
2199                       ENET_VLAN_TBL_VLANRDCTBLN) <<
2200                      ENET_VLAN_TBL_SHIFT(port));
2201         if (vpr)
2202                 reg_val |= (ENET_VLAN_TBL_VPR <<
2203                             ENET_VLAN_TBL_SHIFT(port));
2204         reg_val |= (rdc_table << ENET_VLAN_TBL_SHIFT(port));
2205
2206         reg_val = vlan_entry_set_parity(reg_val);
2207
2208         nw64(ENET_VLAN_TBL(index), reg_val);
2209 }
2210
2211 static void vlan_tbl_clear(struct niu *np)
2212 {
2213         int i;
2214
2215         for (i = 0; i < ENET_VLAN_TBL_NUM_ENTRIES; i++)
2216                 nw64(ENET_VLAN_TBL(i), 0);
2217 }
2218
2219 static int tcam_wait_bit(struct niu *np, u64 bit)
2220 {
2221         int limit = 1000;
2222
2223         while (--limit > 0) {
2224                 if (nr64(TCAM_CTL) & bit)
2225                         break;
2226                 udelay(1);
2227         }
2228         if (limit < 0)
2229                 return -ENODEV;
2230
2231         return 0;
2232 }
2233
2234 static int tcam_flush(struct niu *np, int index)
2235 {
2236         nw64(TCAM_KEY_0, 0x00);
2237         nw64(TCAM_KEY_MASK_0, 0xff);
2238         nw64(TCAM_CTL, (TCAM_CTL_RWC_TCAM_WRITE | index));
2239
2240         return tcam_wait_bit(np, TCAM_CTL_STAT);
2241 }
2242
2243 #if 0
2244 static int tcam_read(struct niu *np, int index,
2245                      u64 *key, u64 *mask)
2246 {
2247         int err;
2248
2249         nw64(TCAM_CTL, (TCAM_CTL_RWC_TCAM_READ | index));
2250         err = tcam_wait_bit(np, TCAM_CTL_STAT);
2251         if (!err) {
2252                 key[0] = nr64(TCAM_KEY_0);
2253                 key[1] = nr64(TCAM_KEY_1);
2254                 key[2] = nr64(TCAM_KEY_2);
2255                 key[3] = nr64(TCAM_KEY_3);
2256                 mask[0] = nr64(TCAM_KEY_MASK_0);
2257                 mask[1] = nr64(TCAM_KEY_MASK_1);
2258                 mask[2] = nr64(TCAM_KEY_MASK_2);
2259                 mask[3] = nr64(TCAM_KEY_MASK_3);
2260         }
2261         return err;
2262 }
2263 #endif
2264
2265 static int tcam_write(struct niu *np, int index,
2266                       u64 *key, u64 *mask)
2267 {
2268         nw64(TCAM_KEY_0, key[0]);
2269         nw64(TCAM_KEY_1, key[1]);
2270         nw64(TCAM_KEY_2, key[2]);
2271         nw64(TCAM_KEY_3, key[3]);
2272         nw64(TCAM_KEY_MASK_0, mask[0]);
2273         nw64(TCAM_KEY_MASK_1, mask[1]);
2274         nw64(TCAM_KEY_MASK_2, mask[2]);
2275         nw64(TCAM_KEY_MASK_3, mask[3]);
2276         nw64(TCAM_CTL, (TCAM_CTL_RWC_TCAM_WRITE | index));
2277
2278         return tcam_wait_bit(np, TCAM_CTL_STAT);
2279 }
2280
2281 #if 0
2282 static int tcam_assoc_read(struct niu *np, int index, u64 *data)
2283 {
2284         int err;
2285
2286         nw64(TCAM_CTL, (TCAM_CTL_RWC_RAM_READ | index));
2287         err = tcam_wait_bit(np, TCAM_CTL_STAT);
2288         if (!err)
2289                 *data = nr64(TCAM_KEY_1);
2290
2291         return err;
2292 }
2293 #endif
2294
2295 static int tcam_assoc_write(struct niu *np, int index, u64 assoc_data)
2296 {
2297         nw64(TCAM_KEY_1, assoc_data);
2298         nw64(TCAM_CTL, (TCAM_CTL_RWC_RAM_WRITE | index));
2299
2300         return tcam_wait_bit(np, TCAM_CTL_STAT);
2301 }
2302
2303 static void tcam_enable(struct niu *np, int on)
2304 {
2305         u64 val = nr64(FFLP_CFG_1);
2306
2307         if (on)
2308                 val &= ~FFLP_CFG_1_TCAM_DIS;
2309         else
2310                 val |= FFLP_CFG_1_TCAM_DIS;
2311         nw64(FFLP_CFG_1, val);
2312 }
2313
2314 static void tcam_set_lat_and_ratio(struct niu *np, u64 latency, u64 ratio)
2315 {
2316         u64 val = nr64(FFLP_CFG_1);
2317
2318         val &= ~(FFLP_CFG_1_FFLPINITDONE |
2319                  FFLP_CFG_1_CAMLAT |
2320                  FFLP_CFG_1_CAMRATIO);
2321         val |= (latency << FFLP_CFG_1_CAMLAT_SHIFT);
2322         val |= (ratio << FFLP_CFG_1_CAMRATIO_SHIFT);
2323         nw64(FFLP_CFG_1, val);
2324
2325         val = nr64(FFLP_CFG_1);
2326         val |= FFLP_CFG_1_FFLPINITDONE;
2327         nw64(FFLP_CFG_1, val);
2328 }
2329
2330 static int tcam_user_eth_class_enable(struct niu *np, unsigned long class,
2331                                       int on)
2332 {
2333         unsigned long reg;
2334         u64 val;
2335
2336         if (class < CLASS_CODE_ETHERTYPE1 ||
2337             class > CLASS_CODE_ETHERTYPE2)
2338                 return -EINVAL;
2339
2340         reg = L2_CLS(class - CLASS_CODE_ETHERTYPE1);
2341         val = nr64(reg);
2342         if (on)
2343                 val |= L2_CLS_VLD;
2344         else
2345                 val &= ~L2_CLS_VLD;
2346         nw64(reg, val);
2347
2348         return 0;
2349 }
2350
2351 #if 0
2352 static int tcam_user_eth_class_set(struct niu *np, unsigned long class,
2353                                    u64 ether_type)
2354 {
2355         unsigned long reg;
2356         u64 val;
2357
2358         if (class < CLASS_CODE_ETHERTYPE1 ||
2359             class > CLASS_CODE_ETHERTYPE2 ||
2360             (ether_type & ~(u64)0xffff) != 0)
2361                 return -EINVAL;
2362
2363         reg = L2_CLS(class - CLASS_CODE_ETHERTYPE1);
2364         val = nr64(reg);
2365         val &= ~L2_CLS_ETYPE;
2366         val |= (ether_type << L2_CLS_ETYPE_SHIFT);
2367         nw64(reg, val);
2368
2369         return 0;
2370 }
2371 #endif
2372
2373 static int tcam_user_ip_class_enable(struct niu *np, unsigned long class,
2374                                      int on)
2375 {
2376         unsigned long reg;
2377         u64 val;
2378
2379         if (class < CLASS_CODE_USER_PROG1 ||
2380             class > CLASS_CODE_USER_PROG4)
2381                 return -EINVAL;
2382
2383         reg = L3_CLS(class - CLASS_CODE_USER_PROG1);
2384         val = nr64(reg);
2385         if (on)
2386                 val |= L3_CLS_VALID;
2387         else
2388                 val &= ~L3_CLS_VALID;
2389         nw64(reg, val);
2390
2391         return 0;
2392 }
2393
2394 #if 0
2395 static int tcam_user_ip_class_set(struct niu *np, unsigned long class,
2396                                   int ipv6, u64 protocol_id,
2397                                   u64 tos_mask, u64 tos_val)
2398 {
2399         unsigned long reg;
2400         u64 val;
2401
2402         if (class < CLASS_CODE_USER_PROG1 ||
2403             class > CLASS_CODE_USER_PROG4 ||
2404             (protocol_id & ~(u64)0xff) != 0 ||
2405             (tos_mask & ~(u64)0xff) != 0 ||
2406             (tos_val & ~(u64)0xff) != 0)
2407                 return -EINVAL;
2408
2409         reg = L3_CLS(class - CLASS_CODE_USER_PROG1);
2410         val = nr64(reg);
2411         val &= ~(L3_CLS_IPVER | L3_CLS_PID |
2412                  L3_CLS_TOSMASK | L3_CLS_TOS);
2413         if (ipv6)
2414                 val |= L3_CLS_IPVER;
2415         val |= (protocol_id << L3_CLS_PID_SHIFT);
2416         val |= (tos_mask << L3_CLS_TOSMASK_SHIFT);
2417         val |= (tos_val << L3_CLS_TOS_SHIFT);
2418         nw64(reg, val);
2419
2420         return 0;
2421 }
2422 #endif
2423
2424 static int tcam_early_init(struct niu *np)
2425 {
2426         unsigned long i;
2427         int err;
2428
2429         tcam_enable(np, 0);
2430         tcam_set_lat_and_ratio(np,
2431                                DEFAULT_TCAM_LATENCY,
2432                                DEFAULT_TCAM_ACCESS_RATIO);
2433         for (i = CLASS_CODE_ETHERTYPE1; i <= CLASS_CODE_ETHERTYPE2; i++) {
2434                 err = tcam_user_eth_class_enable(np, i, 0);
2435                 if (err)
2436                         return err;
2437         }
2438         for (i = CLASS_CODE_USER_PROG1; i <= CLASS_CODE_USER_PROG4; i++) {
2439                 err = tcam_user_ip_class_enable(np, i, 0);
2440                 if (err)
2441                         return err;
2442         }
2443
2444         return 0;
2445 }
2446
2447 static int tcam_flush_all(struct niu *np)
2448 {
2449         unsigned long i;
2450
2451         for (i = 0; i < np->parent->tcam_num_entries; i++) {
2452                 int err = tcam_flush(np, i);
2453                 if (err)
2454                         return err;
2455         }
2456         return 0;
2457 }
2458
2459 static u64 hash_addr_regval(unsigned long index, unsigned long num_entries)
2460 {
2461         return ((u64)index | (num_entries == 1 ?
2462                               HASH_TBL_ADDR_AUTOINC : 0));
2463 }
2464
2465 #if 0
2466 static int hash_read(struct niu *np, unsigned long partition,
2467                      unsigned long index, unsigned long num_entries,
2468                      u64 *data)
2469 {
2470         u64 val = hash_addr_regval(index, num_entries);
2471         unsigned long i;
2472
2473         if (partition >= FCRAM_NUM_PARTITIONS ||
2474             index + num_entries > FCRAM_SIZE)
2475                 return -EINVAL;
2476
2477         nw64(HASH_TBL_ADDR(partition), val);
2478         for (i = 0; i < num_entries; i++)
2479                 data[i] = nr64(HASH_TBL_DATA(partition));
2480
2481         return 0;
2482 }
2483 #endif
2484
2485 static int hash_write(struct niu *np, unsigned long partition,
2486                       unsigned long index, unsigned long num_entries,
2487                       u64 *data)
2488 {
2489         u64 val = hash_addr_regval(index, num_entries);
2490         unsigned long i;
2491
2492         if (partition >= FCRAM_NUM_PARTITIONS ||
2493             index + (num_entries * 8) > FCRAM_SIZE)
2494                 return -EINVAL;
2495
2496         nw64(HASH_TBL_ADDR(partition), val);
2497         for (i = 0; i < num_entries; i++)
2498                 nw64(HASH_TBL_DATA(partition), data[i]);
2499
2500         return 0;
2501 }
2502
2503 static void fflp_reset(struct niu *np)
2504 {
2505         u64 val;
2506
2507         nw64(FFLP_CFG_1, FFLP_CFG_1_PIO_FIO_RST);
2508         udelay(10);
2509         nw64(FFLP_CFG_1, 0);
2510
2511         val = FFLP_CFG_1_FCRAMOUTDR_NORMAL | FFLP_CFG_1_FFLPINITDONE;
2512         nw64(FFLP_CFG_1, val);
2513 }
2514
2515 static void fflp_set_timings(struct niu *np)
2516 {
2517         u64 val = nr64(FFLP_CFG_1);
2518
2519         val &= ~FFLP_CFG_1_FFLPINITDONE;
2520         val |= (DEFAULT_FCRAMRATIO << FFLP_CFG_1_FCRAMRATIO_SHIFT);
2521         nw64(FFLP_CFG_1, val);
2522
2523         val = nr64(FFLP_CFG_1);
2524         val |= FFLP_CFG_1_FFLPINITDONE;
2525         nw64(FFLP_CFG_1, val);
2526
2527         val = nr64(FCRAM_REF_TMR);
2528         val &= ~(FCRAM_REF_TMR_MAX | FCRAM_REF_TMR_MIN);
2529         val |= (DEFAULT_FCRAM_REFRESH_MAX << FCRAM_REF_TMR_MAX_SHIFT);
2530         val |= (DEFAULT_FCRAM_REFRESH_MIN << FCRAM_REF_TMR_MIN_SHIFT);
2531         nw64(FCRAM_REF_TMR, val);
2532 }
2533
2534 static int fflp_set_partition(struct niu *np, u64 partition,
2535                               u64 mask, u64 base, int enable)
2536 {
2537         unsigned long reg;
2538         u64 val;
2539
2540         if (partition >= FCRAM_NUM_PARTITIONS ||
2541             (mask & ~(u64)0x1f) != 0 ||
2542             (base & ~(u64)0x1f) != 0)
2543                 return -EINVAL;
2544
2545         reg = FLW_PRT_SEL(partition);
2546
2547         val = nr64(reg);
2548         val &= ~(FLW_PRT_SEL_EXT | FLW_PRT_SEL_MASK | FLW_PRT_SEL_BASE);
2549         val |= (mask << FLW_PRT_SEL_MASK_SHIFT);
2550         val |= (base << FLW_PRT_SEL_BASE_SHIFT);
2551         if (enable)
2552                 val |= FLW_PRT_SEL_EXT;
2553         nw64(reg, val);
2554
2555         return 0;
2556 }
2557
2558 static int fflp_disable_all_partitions(struct niu *np)
2559 {
2560         unsigned long i;
2561
2562         for (i = 0; i < FCRAM_NUM_PARTITIONS; i++) {
2563                 int err = fflp_set_partition(np, 0, 0, 0, 0);
2564                 if (err)
2565                         return err;
2566         }
2567         return 0;
2568 }
2569
2570 static void fflp_llcsnap_enable(struct niu *np, int on)
2571 {
2572         u64 val = nr64(FFLP_CFG_1);
2573
2574         if (on)
2575                 val |= FFLP_CFG_1_LLCSNAP;
2576         else
2577                 val &= ~FFLP_CFG_1_LLCSNAP;
2578         nw64(FFLP_CFG_1, val);
2579 }
2580
2581 static void fflp_errors_enable(struct niu *np, int on)
2582 {
2583         u64 val = nr64(FFLP_CFG_1);
2584
2585         if (on)
2586                 val &= ~FFLP_CFG_1_ERRORDIS;
2587         else
2588                 val |= FFLP_CFG_1_ERRORDIS;
2589         nw64(FFLP_CFG_1, val);
2590 }
2591
2592 static int fflp_hash_clear(struct niu *np)
2593 {
2594         struct fcram_hash_ipv4 ent;
2595         unsigned long i;
2596
2597         /* IPV4 hash entry with valid bit clear, rest is don't care.  */
2598         memset(&ent, 0, sizeof(ent));
2599         ent.header = HASH_HEADER_EXT;
2600
2601         for (i = 0; i < FCRAM_SIZE; i += sizeof(ent)) {
2602                 int err = hash_write(np, 0, i, 1, (u64 *) &ent);
2603                 if (err)
2604                         return err;
2605         }
2606         return 0;
2607 }
2608
2609 static int fflp_early_init(struct niu *np)
2610 {
2611         struct niu_parent *parent;
2612         unsigned long flags;
2613         int err;
2614
2615         niu_lock_parent(np, flags);
2616
2617         parent = np->parent;
2618         err = 0;
2619         if (!(parent->flags & PARENT_FLGS_CLS_HWINIT)) {
2620                 niudbg(PROBE, "fflp_early_init: Initting hw on port %u\n",
2621                        np->port);
2622                 if (np->parent->plat_type != PLAT_TYPE_NIU) {
2623                         fflp_reset(np);
2624                         fflp_set_timings(np);
2625                         err = fflp_disable_all_partitions(np);
2626                         if (err) {
2627                                 niudbg(PROBE, "fflp_disable_all_partitions "
2628                                        "failed, err=%d\n", err);
2629                                 goto out;
2630                         }
2631                 }
2632
2633                 err = tcam_early_init(np);
2634                 if (err) {
2635                         niudbg(PROBE, "tcam_early_init failed, err=%d\n",
2636                                err);
2637                         goto out;
2638                 }
2639                 fflp_llcsnap_enable(np, 1);
2640                 fflp_errors_enable(np, 0);
2641                 nw64(H1POLY, 0);
2642                 nw64(H2POLY, 0);
2643
2644                 err = tcam_flush_all(np);
2645                 if (err) {
2646                         niudbg(PROBE, "tcam_flush_all failed, err=%d\n",
2647                                err);
2648                         goto out;
2649                 }
2650                 if (np->parent->plat_type != PLAT_TYPE_NIU) {
2651                         err = fflp_hash_clear(np);
2652                         if (err) {
2653                                 niudbg(PROBE, "fflp_hash_clear failed, "
2654                                        "err=%d\n", err);
2655                                 goto out;
2656                         }
2657                 }
2658
2659                 vlan_tbl_clear(np);
2660
2661                 niudbg(PROBE, "fflp_early_init: Success\n");
2662                 parent->flags |= PARENT_FLGS_CLS_HWINIT;
2663         }
2664 out:
2665         niu_unlock_parent(np, flags);
2666         return err;
2667 }
2668
2669 static int niu_set_flow_key(struct niu *np, unsigned long class_code, u64 key)
2670 {
2671         if (class_code < CLASS_CODE_USER_PROG1 ||
2672             class_code > CLASS_CODE_SCTP_IPV6)
2673                 return -EINVAL;
2674
2675         nw64(FLOW_KEY(class_code - CLASS_CODE_USER_PROG1), key);
2676         return 0;
2677 }
2678
2679 static int niu_set_tcam_key(struct niu *np, unsigned long class_code, u64 key)
2680 {
2681         if (class_code < CLASS_CODE_USER_PROG1 ||
2682             class_code > CLASS_CODE_SCTP_IPV6)
2683                 return -EINVAL;
2684
2685         nw64(TCAM_KEY(class_code - CLASS_CODE_USER_PROG1), key);
2686         return 0;
2687 }
2688
2689 static void niu_rx_skb_append(struct sk_buff *skb, struct page *page,
2690                               u32 offset, u32 size)
2691 {
2692         int i = skb_shinfo(skb)->nr_frags;
2693         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2694
2695         frag->page = page;
2696         frag->page_offset = offset;
2697         frag->size = size;
2698
2699         skb->len += size;
2700         skb->data_len += size;
2701         skb->truesize += size;
2702
2703         skb_shinfo(skb)->nr_frags = i + 1;
2704 }
2705
2706 static unsigned int niu_hash_rxaddr(struct rx_ring_info *rp, u64 a)
2707 {
2708         a >>= PAGE_SHIFT;
2709         a ^= (a >> ilog2(MAX_RBR_RING_SIZE));
2710
2711         return (a & (MAX_RBR_RING_SIZE - 1));
2712 }
2713
2714 static struct page *niu_find_rxpage(struct rx_ring_info *rp, u64 addr,
2715                                     struct page ***link)
2716 {
2717         unsigned int h = niu_hash_rxaddr(rp, addr);
2718         struct page *p, **pp;
2719
2720         addr &= PAGE_MASK;
2721         pp = &rp->rxhash[h];
2722         for (; (p = *pp) != NULL; pp = (struct page **) &p->mapping) {
2723                 if (p->index == addr) {
2724                         *link = pp;
2725                         break;
2726                 }
2727         }
2728
2729         return p;
2730 }
2731
2732 static void niu_hash_page(struct rx_ring_info *rp, struct page *page, u64 base)
2733 {
2734         unsigned int h = niu_hash_rxaddr(rp, base);
2735
2736         page->index = base;
2737         page->mapping = (struct address_space *) rp->rxhash[h];
2738         rp->rxhash[h] = page;
2739 }
2740
2741 static int niu_rbr_add_page(struct niu *np, struct rx_ring_info *rp,
2742                             gfp_t mask, int start_index)
2743 {
2744         struct page *page;
2745         u64 addr;
2746         int i;
2747
2748         page = alloc_page(mask);
2749         if (!page)
2750                 return -ENOMEM;
2751
2752         addr = np->ops->map_page(np->device, page, 0,
2753                                  PAGE_SIZE, DMA_FROM_DEVICE);
2754
2755         niu_hash_page(rp, page, addr);
2756         if (rp->rbr_blocks_per_page > 1)
2757                 atomic_add(rp->rbr_blocks_per_page - 1,
2758                            &compound_head(page)->_count);
2759
2760         for (i = 0; i < rp->rbr_blocks_per_page; i++) {
2761                 __le32 *rbr = &rp->rbr[start_index + i];
2762
2763                 *rbr = cpu_to_le32(addr >> RBR_DESCR_ADDR_SHIFT);
2764                 addr += rp->rbr_block_size;
2765         }
2766
2767         return 0;
2768 }
2769
2770 static void niu_rbr_refill(struct niu *np, struct rx_ring_info *rp, gfp_t mask)
2771 {
2772         int index = rp->rbr_index;
2773
2774         rp->rbr_pending++;
2775         if ((rp->rbr_pending % rp->rbr_blocks_per_page) == 0) {
2776                 int err = niu_rbr_add_page(np, rp, mask, index);
2777
2778                 if (unlikely(err)) {
2779                         rp->rbr_pending--;
2780                         return;
2781                 }
2782
2783                 rp->rbr_index += rp->rbr_blocks_per_page;
2784                 BUG_ON(rp->rbr_index > rp->rbr_table_size);
2785                 if (rp->rbr_index == rp->rbr_table_size)
2786                         rp->rbr_index = 0;
2787
2788                 if (rp->rbr_pending >= rp->rbr_kick_thresh) {
2789                         nw64(RBR_KICK(rp->rx_channel), rp->rbr_pending);
2790                         rp->rbr_pending = 0;
2791                 }
2792         }
2793 }
2794
2795 static int niu_rx_pkt_ignore(struct niu *np, struct rx_ring_info *rp)
2796 {
2797         unsigned int index = rp->rcr_index;
2798         int num_rcr = 0;
2799
2800         rp->rx_dropped++;
2801         while (1) {
2802                 struct page *page, **link;
2803                 u64 addr, val;
2804                 u32 rcr_size;
2805
2806                 num_rcr++;
2807
2808                 val = le64_to_cpup(&rp->rcr[index]);
2809                 addr = (val & RCR_ENTRY_PKT_BUF_ADDR) <<
2810                         RCR_ENTRY_PKT_BUF_ADDR_SHIFT;
2811                 page = niu_find_rxpage(rp, addr, &link);
2812
2813                 rcr_size = rp->rbr_sizes[(val & RCR_ENTRY_PKTBUFSZ) >>
2814                                          RCR_ENTRY_PKTBUFSZ_SHIFT];
2815                 if ((page->index + PAGE_SIZE) - rcr_size == addr) {
2816                         *link = (struct page *) page->mapping;
2817                         np->ops->unmap_page(np->device, page->index,
2818                                             PAGE_SIZE, DMA_FROM_DEVICE);
2819                         page->index = 0;
2820                         page->mapping = NULL;
2821                         __free_page(page);
2822                         rp->rbr_refill_pending++;
2823                 }
2824
2825                 index = NEXT_RCR(rp, index);
2826                 if (!(val & RCR_ENTRY_MULTI))
2827                         break;
2828
2829         }
2830         rp->rcr_index = index;
2831
2832         return num_rcr;
2833 }
2834
2835 static int niu_process_rx_pkt(struct niu *np, struct rx_ring_info *rp)
2836 {
2837         unsigned int index = rp->rcr_index;
2838         struct sk_buff *skb;
2839         int len, num_rcr;
2840
2841         skb = netdev_alloc_skb(np->dev, RX_SKB_ALLOC_SIZE);
2842         if (unlikely(!skb))
2843                 return niu_rx_pkt_ignore(np, rp);
2844
2845         num_rcr = 0;
2846         while (1) {
2847                 struct page *page, **link;
2848                 u32 rcr_size, append_size;
2849                 u64 addr, val, off;
2850
2851                 num_rcr++;
2852
2853                 val = le64_to_cpup(&rp->rcr[index]);
2854
2855                 len = (val & RCR_ENTRY_L2_LEN) >>
2856                         RCR_ENTRY_L2_LEN_SHIFT;
2857                 len -= ETH_FCS_LEN;
2858
2859                 addr = (val & RCR_ENTRY_PKT_BUF_ADDR) <<
2860                         RCR_ENTRY_PKT_BUF_ADDR_SHIFT;
2861                 page = niu_find_rxpage(rp, addr, &link);
2862
2863                 rcr_size = rp->rbr_sizes[(val & RCR_ENTRY_PKTBUFSZ) >>
2864                                          RCR_ENTRY_PKTBUFSZ_SHIFT];
2865
2866                 off = addr & ~PAGE_MASK;
2867                 append_size = rcr_size;
2868                 if (num_rcr == 1) {
2869                         int ptype;
2870
2871                         off += 2;
2872                         append_size -= 2;
2873
2874                         ptype = (val >> RCR_ENTRY_PKT_TYPE_SHIFT);
2875                         if ((ptype == RCR_PKT_TYPE_TCP ||
2876                              ptype == RCR_PKT_TYPE_UDP) &&
2877                             !(val & (RCR_ENTRY_NOPORT |
2878                                      RCR_ENTRY_ERROR)))
2879                                 skb->ip_summed = CHECKSUM_UNNECESSARY;
2880                         else
2881                                 skb->ip_summed = CHECKSUM_NONE;
2882                 }
2883                 if (!(val & RCR_ENTRY_MULTI))
2884                         append_size = len - skb->len;
2885
2886                 niu_rx_skb_append(skb, page, off, append_size);
2887                 if ((page->index + rp->rbr_block_size) - rcr_size == addr) {
2888                         *link = (struct page *) page->mapping;
2889                         np->ops->unmap_page(np->device, page->index,
2890                                             PAGE_SIZE, DMA_FROM_DEVICE);
2891                         page->index = 0;
2892                         page->mapping = NULL;
2893                         rp->rbr_refill_pending++;
2894                 } else
2895                         get_page(page);
2896
2897                 index = NEXT_RCR(rp, index);
2898                 if (!(val & RCR_ENTRY_MULTI))
2899                         break;
2900
2901         }
2902         rp->rcr_index = index;
2903
2904         skb_reserve(skb, NET_IP_ALIGN);
2905         __pskb_pull_tail(skb, min(len, NIU_RXPULL_MAX));
2906
2907         rp->rx_packets++;
2908         rp->rx_bytes += skb->len;
2909
2910         skb->protocol = eth_type_trans(skb, np->dev);
2911         netif_receive_skb(skb);
2912
2913         np->dev->last_rx = jiffies;
2914
2915         return num_rcr;
2916 }
2917
2918 static int niu_rbr_fill(struct niu *np, struct rx_ring_info *rp, gfp_t mask)
2919 {
2920         int blocks_per_page = rp->rbr_blocks_per_page;
2921         int err, index = rp->rbr_index;
2922
2923         err = 0;
2924         while (index < (rp->rbr_table_size - blocks_per_page)) {
2925                 err = niu_rbr_add_page(np, rp, mask, index);
2926                 if (err)
2927                         break;
2928
2929                 index += blocks_per_page;
2930         }
2931
2932         rp->rbr_index = index;
2933         return err;
2934 }
2935
2936 static void niu_rbr_free(struct niu *np, struct rx_ring_info *rp)
2937 {
2938         int i;
2939
2940         for (i = 0; i < MAX_RBR_RING_SIZE; i++) {
2941                 struct page *page;
2942
2943                 page = rp->rxhash[i];
2944                 while (page) {
2945                         struct page *next = (struct page *) page->mapping;
2946                         u64 base = page->index;
2947
2948                         np->ops->unmap_page(np->device, base, PAGE_SIZE,
2949                                             DMA_FROM_DEVICE);
2950                         page->index = 0;
2951                         page->mapping = NULL;
2952
2953                         __free_page(page);
2954
2955                         page = next;
2956                 }
2957         }
2958
2959         for (i = 0; i < rp->rbr_table_size; i++)
2960                 rp->rbr[i] = cpu_to_le32(0);
2961         rp->rbr_index = 0;
2962 }
2963
2964 static int release_tx_packet(struct niu *np, struct tx_ring_info *rp, int idx)
2965 {
2966         struct tx_buff_info *tb = &rp->tx_buffs[idx];
2967         struct sk_buff *skb = tb->skb;
2968         struct tx_pkt_hdr *tp;
2969         u64 tx_flags;
2970         int i, len;
2971
2972         tp = (struct tx_pkt_hdr *) skb->data;
2973         tx_flags = le64_to_cpup(&tp->flags);
2974
2975         rp->tx_packets++;
2976         rp->tx_bytes += (((tx_flags & TXHDR_LEN) >> TXHDR_LEN_SHIFT) -
2977                          ((tx_flags & TXHDR_PAD) / 2));
2978
2979         len = skb_headlen(skb);
2980         np->ops->unmap_single(np->device, tb->mapping,
2981                               len, DMA_TO_DEVICE);
2982
2983         if (le64_to_cpu(rp->descr[idx]) & TX_DESC_MARK)
2984                 rp->mark_pending--;
2985
2986         tb->skb = NULL;
2987         do {
2988                 idx = NEXT_TX(rp, idx);
2989                 len -= MAX_TX_DESC_LEN;
2990         } while (len > 0);
2991
2992         for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2993                 tb = &rp->tx_buffs[idx];
2994                 BUG_ON(tb->skb != NULL);
2995                 np->ops->unmap_page(np->device, tb->mapping,
2996                                     skb_shinfo(skb)->frags[i].size,
2997                                     DMA_TO_DEVICE);
2998                 idx = NEXT_TX(rp, idx);
2999         }
3000
3001         dev_kfree_skb(skb);
3002
3003         return idx;
3004 }
3005
3006 #define NIU_TX_WAKEUP_THRESH(rp)                ((rp)->pending / 4)
3007
3008 static void niu_tx_work(struct niu *np, struct tx_ring_info *rp)
3009 {
3010         u16 pkt_cnt, tmp;
3011         int cons;
3012         u64 cs;
3013
3014         cs = rp->tx_cs;
3015         if (unlikely(!(cs & (TX_CS_MK | TX_CS_MMK))))
3016                 goto out;
3017
3018         tmp = pkt_cnt = (cs & TX_CS_PKT_CNT) >> TX_CS_PKT_CNT_SHIFT;
3019         pkt_cnt = (pkt_cnt - rp->last_pkt_cnt) &
3020                 (TX_CS_PKT_CNT >> TX_CS_PKT_CNT_SHIFT);
3021
3022         rp->last_pkt_cnt = tmp;
3023
3024         cons = rp->cons;
3025
3026         niudbg(TX_DONE, "%s: niu_tx_work() pkt_cnt[%u] cons[%d]\n",
3027                np->dev->name, pkt_cnt, cons);
3028
3029         while (pkt_cnt--)
3030                 cons = release_tx_packet(np, rp, cons);
3031
3032         rp->cons = cons;
3033         smp_mb();
3034
3035 out:
3036         if (unlikely(netif_queue_stopped(np->dev) &&
3037                      (niu_tx_avail(rp) > NIU_TX_WAKEUP_THRESH(rp)))) {
3038                 netif_tx_lock(np->dev);
3039                 if (netif_queue_stopped(np->dev) &&
3040                     (niu_tx_avail(rp) > NIU_TX_WAKEUP_THRESH(rp)))
3041                         netif_wake_queue(np->dev);
3042                 netif_tx_unlock(np->dev);
3043         }
3044 }
3045
3046 static int niu_rx_work(struct niu *np, struct rx_ring_info *rp, int budget)
3047 {
3048         int qlen, rcr_done = 0, work_done = 0;
3049         struct rxdma_mailbox *mbox = rp->mbox;
3050         u64 stat;
3051
3052 #if 1
3053         stat = nr64(RX_DMA_CTL_STAT(rp->rx_channel));
3054         qlen = nr64(RCRSTAT_A(rp->rx_channel)) & RCRSTAT_A_QLEN;
3055 #else
3056         stat = le64_to_cpup(&mbox->rx_dma_ctl_stat);
3057         qlen = (le64_to_cpup(&mbox->rcrstat_a) & RCRSTAT_A_QLEN);
3058 #endif
3059         mbox->rx_dma_ctl_stat = 0;
3060         mbox->rcrstat_a = 0;
3061
3062         niudbg(RX_STATUS, "%s: niu_rx_work(chan[%d]), stat[%llx] qlen=%d\n",
3063                np->dev->name, rp->rx_channel, (unsigned long long) stat, qlen);
3064
3065         rcr_done = work_done = 0;
3066         qlen = min(qlen, budget);
3067         while (work_done < qlen) {
3068                 rcr_done += niu_process_rx_pkt(np, rp);
3069                 work_done++;
3070         }
3071
3072         if (rp->rbr_refill_pending >= rp->rbr_kick_thresh) {
3073                 unsigned int i;
3074
3075                 for (i = 0; i < rp->rbr_refill_pending; i++)
3076                         niu_rbr_refill(np, rp, GFP_ATOMIC);
3077                 rp->rbr_refill_pending = 0;
3078         }
3079
3080         stat = (RX_DMA_CTL_STAT_MEX |
3081                 ((u64)work_done << RX_DMA_CTL_STAT_PKTREAD_SHIFT) |
3082                 ((u64)rcr_done << RX_DMA_CTL_STAT_PTRREAD_SHIFT));
3083
3084         nw64(RX_DMA_CTL_STAT(rp->rx_channel), stat);
3085
3086         return work_done;
3087 }
3088
3089 static int niu_poll_core(struct niu *np, struct niu_ldg *lp, int budget)
3090 {
3091         u64 v0 = lp->v0;
3092         u32 tx_vec = (v0 >> 32);
3093         u32 rx_vec = (v0 & 0xffffffff);
3094         int i, work_done = 0;
3095
3096         niudbg(INTR, "%s: niu_poll_core() v0[%016llx]\n",
3097                np->dev->name, (unsigned long long) v0);
3098
3099         for (i = 0; i < np->num_tx_rings; i++) {
3100                 struct tx_ring_info *rp = &np->tx_rings[i];
3101                 if (tx_vec & (1 << rp->tx_channel))
3102                         niu_tx_work(np, rp);
3103                 nw64(LD_IM0(LDN_TXDMA(rp->tx_channel)), 0);
3104         }
3105
3106         for (i = 0; i < np->num_rx_rings; i++) {
3107                 struct rx_ring_info *rp = &np->rx_rings[i];
3108
3109                 if (rx_vec & (1 << rp->rx_channel)) {
3110                         int this_work_done;
3111
3112                         this_work_done = niu_rx_work(np, rp,
3113                                                      budget);
3114
3115                         budget -= this_work_done;
3116                         work_done += this_work_done;
3117                 }
3118                 nw64(LD_IM0(LDN_RXDMA(rp->rx_channel)), 0);
3119         }
3120
3121         return work_done;
3122 }
3123
3124 static int niu_poll(struct napi_struct *napi, int budget)
3125 {
3126         struct niu_ldg *lp = container_of(napi, struct niu_ldg, napi);
3127         struct niu *np = lp->np;
3128         int work_done;
3129
3130         work_done = niu_poll_core(np, lp, budget);
3131
3132         if (work_done < budget) {
3133                 netif_rx_complete(np->dev, napi);
3134                 niu_ldg_rearm(np, lp, 1);
3135         }
3136         return work_done;
3137 }
3138
3139 static void niu_log_rxchan_errors(struct niu *np, struct rx_ring_info *rp,
3140                                   u64 stat)
3141 {
3142         dev_err(np->device, PFX "%s: RX channel %u errors ( ",
3143                 np->dev->name, rp->rx_channel);
3144
3145         if (stat & RX_DMA_CTL_STAT_RBR_TMOUT)
3146                 printk("RBR_TMOUT ");
3147         if (stat & RX_DMA_CTL_STAT_RSP_CNT_ERR)
3148                 printk("RSP_CNT ");
3149         if (stat & RX_DMA_CTL_STAT_BYTE_EN_BUS)
3150                 printk("BYTE_EN_BUS ");
3151         if (stat & RX_DMA_CTL_STAT_RSP_DAT_ERR)
3152                 printk("RSP_DAT ");
3153         if (stat & RX_DMA_CTL_STAT_RCR_ACK_ERR)
3154                 printk("RCR_ACK ");
3155         if (stat & RX_DMA_CTL_STAT_RCR_SHA_PAR)
3156                 printk("RCR_SHA_PAR ");
3157         if (stat & RX_DMA_CTL_STAT_RBR_PRE_PAR)
3158                 printk("RBR_PRE_PAR ");
3159         if (stat & RX_DMA_CTL_STAT_CONFIG_ERR)
3160                 printk("CONFIG ");
3161         if (stat & RX_DMA_CTL_STAT_RCRINCON)
3162                 printk("RCRINCON ");
3163         if (stat & RX_DMA_CTL_STAT_RCRFULL)
3164                 printk("RCRFULL ");
3165         if (stat & RX_DMA_CTL_STAT_RBRFULL)
3166                 printk("RBRFULL ");
3167         if (stat & RX_DMA_CTL_STAT_RBRLOGPAGE)
3168                 printk("RBRLOGPAGE ");
3169         if (stat & RX_DMA_CTL_STAT_CFIGLOGPAGE)
3170                 printk("CFIGLOGPAGE ");
3171         if (stat & RX_DMA_CTL_STAT_DC_FIFO_ERR)
3172                 printk("DC_FIDO ");
3173
3174         printk(")\n");
3175 }
3176
3177 static int niu_rx_error(struct niu *np, struct rx_ring_info *rp)
3178 {
3179         u64 stat = nr64(RX_DMA_CTL_STAT(rp->rx_channel));
3180         int err = 0;
3181
3182
3183         if (stat & (RX_DMA_CTL_STAT_CHAN_FATAL |
3184                     RX_DMA_CTL_STAT_PORT_FATAL))
3185                 err = -EINVAL;
3186
3187         if (err) {
3188                 dev_err(np->device, PFX "%s: RX channel %u error, stat[%llx]\n",
3189                         np->dev->name, rp->rx_channel,
3190                         (unsigned long long) stat);
3191
3192                 niu_log_rxchan_errors(np, rp, stat);
3193         }
3194
3195         nw64(RX_DMA_CTL_STAT(rp->rx_channel),
3196              stat & RX_DMA_CTL_WRITE_CLEAR_ERRS);
3197
3198         return err;
3199 }
3200
3201 static void niu_log_txchan_errors(struct niu *np, struct tx_ring_info *rp,
3202                                   u64 cs)
3203 {
3204         dev_err(np->device, PFX "%s: TX channel %u errors ( ",
3205                 np->dev->name, rp->tx_channel);
3206
3207         if (cs & TX_CS_MBOX_ERR)
3208                 printk("MBOX ");
3209         if (cs & TX_CS_PKT_SIZE_ERR)
3210                 printk("PKT_SIZE ");
3211         if (cs & TX_CS_TX_RING_OFLOW)
3212                 printk("TX_RING_OFLOW ");
3213         if (cs & TX_CS_PREF_BUF_PAR_ERR)
3214                 printk("PREF_BUF_PAR ");
3215         if (cs & TX_CS_NACK_PREF)
3216                 printk("NACK_PREF ");
3217         if (cs & TX_CS_NACK_PKT_RD)
3218                 printk("NACK_PKT_RD ");
3219         if (cs & TX_CS_CONF_PART_ERR)
3220                 printk("CONF_PART ");
3221         if (cs & TX_CS_PKT_PRT_ERR)
3222                 printk("PKT_PTR ");
3223
3224         printk(")\n");
3225 }
3226
3227 static int niu_tx_error(struct niu *np, struct tx_ring_info *rp)
3228 {
3229         u64 cs, logh, logl;
3230
3231         cs = nr64(TX_CS(rp->tx_channel));
3232         logh = nr64(TX_RNG_ERR_LOGH(rp->tx_channel));
3233         logl = nr64(TX_RNG_ERR_LOGL(rp->tx_channel));
3234
3235         dev_err(np->device, PFX "%s: TX channel %u error, "
3236                 "cs[%llx] logh[%llx] logl[%llx]\n",
3237                 np->dev->name, rp->tx_channel,
3238                 (unsigned long long) cs,
3239                 (unsigned long long) logh,
3240                 (unsigned long long) logl);
3241
3242         niu_log_txchan_errors(np, rp, cs);
3243
3244         return -ENODEV;
3245 }
3246
3247 static int niu_mif_interrupt(struct niu *np)
3248 {
3249         u64 mif_status = nr64(MIF_STATUS);
3250         int phy_mdint = 0;
3251
3252         if (np->flags & NIU_FLAGS_XMAC) {
3253                 u64 xrxmac_stat = nr64_mac(XRXMAC_STATUS);
3254
3255                 if (xrxmac_stat & XRXMAC_STATUS_PHY_MDINT)
3256                         phy_mdint = 1;
3257         }
3258
3259         dev_err(np->device, PFX "%s: MIF interrupt, "
3260                 "stat[%llx] phy_mdint(%d)\n",
3261                 np->dev->name, (unsigned long long) mif_status, phy_mdint);
3262
3263         return -ENODEV;
3264 }
3265
3266 static void niu_xmac_interrupt(struct niu *np)
3267 {
3268         struct niu_xmac_stats *mp = &np->mac_stats.xmac;
3269         u64 val;
3270
3271         val = nr64_mac(XTXMAC_STATUS);
3272         if (val & XTXMAC_STATUS_FRAME_CNT_EXP)
3273                 mp->tx_frames += TXMAC_FRM_CNT_COUNT;
3274         if (val & XTXMAC_STATUS_BYTE_CNT_EXP)
3275                 mp->tx_bytes += TXMAC_BYTE_CNT_COUNT;
3276         if (val & XTXMAC_STATUS_TXFIFO_XFR_ERR)
3277                 mp->tx_fifo_errors++;
3278         if (val & XTXMAC_STATUS_TXMAC_OFLOW)
3279                 mp->tx_overflow_errors++;
3280         if (val & XTXMAC_STATUS_MAX_PSIZE_ERR)
3281                 mp->tx_max_pkt_size_errors++;
3282         if (val & XTXMAC_STATUS_TXMAC_UFLOW)
3283                 mp->tx_underflow_errors++;
3284
3285         val = nr64_mac(XRXMAC_STATUS);
3286         if (val & XRXMAC_STATUS_LCL_FLT_STATUS)
3287                 mp->rx_local_faults++;
3288         if (val & XRXMAC_STATUS_RFLT_DET)
3289                 mp->rx_remote_faults++;
3290         if (val & XRXMAC_STATUS_LFLT_CNT_EXP)
3291                 mp->rx_link_faults += LINK_FAULT_CNT_COUNT;
3292         if (val & XRXMAC_STATUS_ALIGNERR_CNT_EXP)
3293                 mp->rx_align_errors += RXMAC_ALIGN_ERR_CNT_COUNT;
3294         if (val & XRXMAC_STATUS_RXFRAG_CNT_EXP)
3295                 mp->rx_frags += RXMAC_FRAG_CNT_COUNT;
3296         if (val & XRXMAC_STATUS_RXMULTF_CNT_EXP)
3297                 mp->rx_mcasts += RXMAC_MC_FRM_CNT_COUNT;
3298         if (val & XRXMAC_STATUS_RXBCAST_CNT_EXP)
3299                 mp->rx_bcasts += RXMAC_BC_FRM_CNT_COUNT;
3300         if (val & XRXMAC_STATUS_RXBCAST_CNT_EXP)
3301                 mp->rx_bcasts += RXMAC_BC_FRM_CNT_COUNT;
3302         if (val & XRXMAC_STATUS_RXHIST1_CNT_EXP)
3303                 mp->rx_hist_cnt1 += RXMAC_HIST_CNT1_COUNT;
3304         if (val & XRXMAC_STATUS_RXHIST2_CNT_EXP)
3305                 mp->rx_hist_cnt2 += RXMAC_HIST_CNT2_COUNT;
3306         if (val & XRXMAC_STATUS_RXHIST3_CNT_EXP)
3307                 mp->rx_hist_cnt3 += RXMAC_HIST_CNT3_COUNT;
3308         if (val & XRXMAC_STATUS_RXHIST4_CNT_EXP)
3309                 mp->rx_hist_cnt4 += RXMAC_HIST_CNT4_COUNT;
3310         if (val & XRXMAC_STATUS_RXHIST5_CNT_EXP)
3311                 mp->rx_hist_cnt5 += RXMAC_HIST_CNT5_COUNT;
3312         if (val & XRXMAC_STATUS_RXHIST6_CNT_EXP)
3313                 mp->rx_hist_cnt6 += RXMAC_HIST_CNT6_COUNT;
3314         if (val & XRXMAC_STATUS_RXHIST7_CNT_EXP)
3315                 mp->rx_hist_cnt7 += RXMAC_HIST_CNT7_COUNT;
3316         if (val & XRXMAC_STAT_MSK_RXOCTET_CNT_EXP)
3317                 mp->rx_octets += RXMAC_BT_CNT_COUNT;
3318         if (val & XRXMAC_STATUS_CVIOLERR_CNT_EXP)
3319                 mp->rx_code_violations += RXMAC_CD_VIO_CNT_COUNT;
3320         if (val & XRXMAC_STATUS_LENERR_CNT_EXP)
3321                 mp->rx_len_errors += RXMAC_MPSZER_CNT_COUNT;
3322         if (val & XRXMAC_STATUS_CRCERR_CNT_EXP)
3323                 mp->rx_crc_errors += RXMAC_CRC_ER_CNT_COUNT;
3324         if (val & XRXMAC_STATUS_RXUFLOW)
3325                 mp->rx_underflows++;
3326         if (val & XRXMAC_STATUS_RXOFLOW)
3327                 mp->rx_overflows++;
3328
3329         val = nr64_mac(XMAC_FC_STAT);
3330         if (val & XMAC_FC_STAT_TX_MAC_NPAUSE)
3331                 mp->pause_off_state++;
3332         if (val & XMAC_FC_STAT_TX_MAC_PAUSE)
3333                 mp->pause_on_state++;
3334         if (val & XMAC_FC_STAT_RX_MAC_RPAUSE)
3335                 mp->pause_received++;
3336 }
3337
3338 static void niu_bmac_interrupt(struct niu *np)
3339 {
3340         struct niu_bmac_stats *mp = &np->mac_stats.bmac;
3341         u64 val;
3342
3343         val = nr64_mac(BTXMAC_STATUS);
3344         if (val & BTXMAC_STATUS_UNDERRUN)
3345                 mp->tx_underflow_errors++;
3346         if (val & BTXMAC_STATUS_MAX_PKT_ERR)
3347                 mp->tx_max_pkt_size_errors++;
3348         if (val & BTXMAC_STATUS_BYTE_CNT_EXP)
3349                 mp->tx_bytes += BTXMAC_BYTE_CNT_COUNT;
3350         if (val & BTXMAC_STATUS_FRAME_CNT_EXP)
3351                 mp->tx_frames += BTXMAC_FRM_CNT_COUNT;
3352
3353         val = nr64_mac(BRXMAC_STATUS);
3354         if (val & BRXMAC_STATUS_OVERFLOW)
3355                 mp->rx_overflows++;
3356         if (val & BRXMAC_STATUS_FRAME_CNT_EXP)
3357                 mp->rx_frames += BRXMAC_FRAME_CNT_COUNT;
3358         if (val & BRXMAC_STATUS_ALIGN_ERR_EXP)
3359                 mp->rx_align_errors += BRXMAC_ALIGN_ERR_CNT_COUNT;
3360         if (val & BRXMAC_STATUS_CRC_ERR_EXP)
3361                 mp->rx_crc_errors += BRXMAC_ALIGN_ERR_CNT_COUNT;
3362         if (val & BRXMAC_STATUS_LEN_ERR_EXP)
3363                 mp->rx_len_errors += BRXMAC_CODE_VIOL_ERR_CNT_COUNT;
3364
3365         val = nr64_mac(BMAC_CTRL_STATUS);
3366         if (val & BMAC_CTRL_STATUS_NOPAUSE)
3367                 mp->pause_off_state++;
3368         if (val & BMAC_CTRL_STATUS_PAUSE)
3369                 mp->pause_on_state++;
3370         if (val & BMAC_CTRL_STATUS_PAUSE_RECV)
3371                 mp->pause_received++;
3372 }
3373
3374 static int niu_mac_interrupt(struct niu *np)
3375 {
3376         if (np->flags & NIU_FLAGS_XMAC)
3377                 niu_xmac_interrupt(np);
3378         else
3379                 niu_bmac_interrupt(np);
3380
3381         return 0;
3382 }
3383
3384 static void niu_log_device_error(struct niu *np, u64 stat)
3385 {
3386         dev_err(np->device, PFX "%s: Core device errors ( ",
3387                 np->dev->name);
3388
3389         if (stat & SYS_ERR_MASK_META2)
3390                 printk("META2 ");
3391         if (stat & SYS_ERR_MASK_META1)
3392                 printk("META1 ");
3393         if (stat & SYS_ERR_MASK_PEU)
3394                 printk("PEU ");
3395         if (stat & SYS_ERR_MASK_TXC)
3396                 printk("TXC ");
3397         if (stat & SYS_ERR_MASK_RDMC)
3398                 printk("RDMC ");
3399         if (stat & SYS_ERR_MASK_TDMC)
3400                 printk("TDMC ");
3401         if (stat & SYS_ERR_MASK_ZCP)
3402                 printk("ZCP ");
3403         if (stat & SYS_ERR_MASK_FFLP)
3404                 printk("FFLP ");
3405         if (stat & SYS_ERR_MASK_IPP)
3406                 printk("IPP ");
3407         if (stat & SYS_ERR_MASK_MAC)
3408                 printk("MAC ");
3409         if (stat & SYS_ERR_MASK_SMX)
3410                 printk("SMX ");
3411
3412         printk(")\n");
3413 }
3414
3415 static int niu_device_error(struct niu *np)
3416 {
3417         u64 stat = nr64(SYS_ERR_STAT);
3418
3419         dev_err(np->device, PFX "%s: Core device error, stat[%llx]\n",
3420                 np->dev->name, (unsigned long long) stat);
3421
3422         niu_log_device_error(np, stat);
3423
3424         return -ENODEV;
3425 }
3426
3427 static int niu_slowpath_interrupt(struct niu *np, struct niu_ldg *lp,
3428                               u64 v0, u64 v1, u64 v2)
3429 {
3430
3431         int i, err = 0;
3432
3433         lp->v0 = v0;
3434         lp->v1 = v1;
3435         lp->v2 = v2;
3436
3437         if (v1 & 0x00000000ffffffffULL) {
3438                 u32 rx_vec = (v1 & 0xffffffff);
3439
3440                 for (i = 0; i < np->num_rx_rings; i++) {
3441                         struct rx_ring_info *rp = &np->rx_rings[i];
3442
3443                         if (rx_vec & (1 << rp->rx_channel)) {
3444                                 int r = niu_rx_error(np, rp);
3445                                 if (r) {
3446                                         err = r;
3447                                 } else {
3448                                         if (!v0)
3449                                                 nw64(RX_DMA_CTL_STAT(rp->rx_channel),
3450                                                      RX_DMA_CTL_STAT_MEX);
3451                                 }
3452                         }
3453                 }
3454         }
3455         if (v1 & 0x7fffffff00000000ULL) {
3456                 u32 tx_vec = (v1 >> 32) & 0x7fffffff;
3457
3458                 for (i = 0; i < np->num_tx_rings; i++) {
3459                         struct tx_ring_info *rp = &np->tx_rings[i];
3460
3461                         if (tx_vec & (1 << rp->tx_channel)) {
3462                                 int r = niu_tx_error(np, rp);
3463                                 if (r)
3464                                         err = r;
3465                         }
3466                 }
3467         }
3468         if ((v0 | v1) & 0x8000000000000000ULL) {
3469                 int r = niu_mif_interrupt(np);
3470                 if (r)
3471                         err = r;
3472         }
3473         if (v2) {
3474                 if (v2 & 0x01ef) {
3475                         int r = niu_mac_interrupt(np);
3476                         if (r)
3477                                 err = r;
3478                 }
3479                 if (v2 & 0x0210) {
3480                         int r = niu_device_error(np);
3481                         if (r)
3482                                 err = r;
3483                 }
3484         }
3485
3486         if (err)
3487                 niu_enable_interrupts(np, 0);
3488
3489         return err;
3490 }
3491
3492 static void niu_rxchan_intr(struct niu *np, struct rx_ring_info *rp,
3493                             int ldn)
3494 {
3495         struct rxdma_mailbox *mbox = rp->mbox;
3496         u64 stat_write, stat = le64_to_cpup(&mbox->rx_dma_ctl_stat);
3497
3498         stat_write = (RX_DMA_CTL_STAT_RCRTHRES |
3499                       RX_DMA_CTL_STAT_RCRTO);
3500         nw64(RX_DMA_CTL_STAT(rp->rx_channel), stat_write);
3501
3502         niudbg(INTR, "%s: rxchan_intr stat[%llx]\n",
3503                np->dev->name, (unsigned long long) stat);
3504 }
3505
3506 static void niu_txchan_intr(struct niu *np, struct tx_ring_info *rp,
3507                             int ldn)
3508 {
3509         rp->tx_cs = nr64(TX_CS(rp->tx_channel));
3510
3511         niudbg(INTR, "%s: txchan_intr cs[%llx]\n",
3512                np->dev->name, (unsigned long long) rp->tx_cs);
3513 }
3514
3515 static void __niu_fastpath_interrupt(struct niu *np, int ldg, u64 v0)
3516 {
3517         struct niu_parent *parent = np->parent;
3518         u32 rx_vec, tx_vec;
3519         int i;
3520
3521         tx_vec = (v0 >> 32);
3522         rx_vec = (v0 & 0xffffffff);
3523
3524         for (i = 0; i < np->num_rx_rings; i++) {
3525                 struct rx_ring_info *rp = &np->rx_rings[i];
3526                 int ldn = LDN_RXDMA(rp->rx_channel);
3527
3528                 if (parent->ldg_map[ldn] != ldg)
3529                         continue;
3530
3531                 nw64(LD_IM0(ldn), LD_IM0_MASK);
3532                 if (rx_vec & (1 << rp->rx_channel))
3533                         niu_rxchan_intr(np, rp, ldn);
3534         }
3535
3536         for (i = 0; i < np->num_tx_rings; i++) {
3537                 struct tx_ring_info *rp = &np->tx_rings[i];
3538                 int ldn = LDN_TXDMA(rp->tx_channel);
3539
3540                 if (parent->ldg_map[ldn] != ldg)
3541                         continue;
3542
3543                 nw64(LD_IM0(ldn), LD_IM0_MASK);
3544                 if (tx_vec & (1 << rp->tx_channel))
3545                         niu_txchan_intr(np, rp, ldn);
3546         }
3547 }
3548
3549 static void niu_schedule_napi(struct niu *np, struct niu_ldg *lp,
3550                               u64 v0, u64 v1, u64 v2)
3551 {
3552         if (likely(netif_rx_schedule_prep(np->dev, &lp->napi))) {
3553                 lp->v0 = v0;
3554                 lp->v1 = v1;
3555                 lp->v2 = v2;
3556                 __niu_fastpath_interrupt(np, lp->ldg_num, v0);
3557                 __netif_rx_schedule(np->dev, &lp->napi);
3558         }
3559 }
3560
3561 static irqreturn_t niu_interrupt(int irq, void *dev_id)
3562 {
3563         struct niu_ldg *lp = dev_id;
3564         struct niu *np = lp->np;
3565         int ldg = lp->ldg_num;
3566         unsigned long flags;
3567         u64 v0, v1, v2;
3568
3569         if (netif_msg_intr(np))
3570                 printk(KERN_DEBUG PFX "niu_interrupt() ldg[%p](%d) ",
3571                        lp, ldg);
3572
3573         spin_lock_irqsave(&np->lock, flags);
3574
3575         v0 = nr64(LDSV0(ldg));
3576         v1 = nr64(LDSV1(ldg));
3577         v2 = nr64(LDSV2(ldg));
3578
3579         if (netif_msg_intr(np))
3580                 printk("v0[%llx] v1[%llx] v2[%llx]\n",
3581                        (unsigned long long) v0,
3582                        (unsigned long long) v1,
3583                        (unsigned long long) v2);
3584
3585         if (unlikely(!v0 && !v1 && !v2)) {
3586                 spin_unlock_irqrestore(&np->lock, flags);
3587                 return IRQ_NONE;
3588         }
3589
3590         if (unlikely((v0 & ((u64)1 << LDN_MIF)) || v1 || v2)) {
3591                 int err = niu_slowpath_interrupt(np, lp, v0, v1, v2);
3592                 if (err)
3593                         goto out;
3594         }
3595         if (likely(v0 & ~((u64)1 << LDN_MIF)))
3596                 niu_schedule_napi(np, lp, v0, v1, v2);
3597         else
3598                 niu_ldg_rearm(np, lp, 1);
3599 out:
3600         spin_unlock_irqrestore(&np->lock, flags);
3601
3602         return IRQ_HANDLED;
3603 }
3604
3605 static void niu_free_rx_ring_info(struct niu *np, struct rx_ring_info *rp)
3606 {
3607         if (rp->mbox) {
3608                 np->ops->free_coherent(np->device,
3609                                        sizeof(struct rxdma_mailbox),
3610                                        rp->mbox, rp->mbox_dma);
3611                 rp->mbox = NULL;
3612         }
3613         if (rp->rcr) {
3614                 np->ops->free_coherent(np->device,
3615                                        MAX_RCR_RING_SIZE * sizeof(__le64),
3616                                        rp->rcr, rp->rcr_dma);
3617                 rp->rcr = NULL;
3618                 rp->rcr_table_size = 0;
3619                 rp->rcr_index = 0;
3620         }
3621         if (rp->rbr) {
3622                 niu_rbr_free(np, rp);
3623
3624                 np->ops->free_coherent(np->device,
3625                                        MAX_RBR_RING_SIZE * sizeof(__le32),
3626                                        rp->rbr, rp->rbr_dma);
3627                 rp->rbr = NULL;
3628                 rp->rbr_table_size = 0;
3629                 rp->rbr_index = 0;
3630         }
3631         kfree(rp->rxhash);
3632         rp->rxhash = NULL;
3633 }
3634
3635 static void niu_free_tx_ring_info(struct niu *np, struct tx_ring_info *rp)
3636 {
3637         if (rp->mbox) {
3638                 np->ops->free_coherent(np->device,
3639                                        sizeof(struct txdma_mailbox),
3640                                        rp->mbox, rp->mbox_dma);
3641                 rp->mbox = NULL;
3642         }
3643         if (rp->descr) {
3644                 int i;
3645
3646                 for (i = 0; i < MAX_TX_RING_SIZE; i++) {
3647                         if (rp->tx_buffs[i].skb)
3648                                 (void) release_tx_packet(np, rp, i);
3649                 }
3650
3651                 np->ops->free_coherent(np->device,
3652                                        MAX_TX_RING_SIZE * sizeof(__le64),
3653                                        rp->descr, rp->descr_dma);
3654                 rp->descr = NULL;
3655                 rp->pending = 0;
3656                 rp->prod = 0;
3657                 rp->cons = 0;
3658                 rp->wrap_bit = 0;
3659         }
3660 }
3661
3662 static void niu_free_channels(struct niu *np)
3663 {
3664         int i;
3665
3666         if (np->rx_rings) {
3667                 for (i = 0; i < np->num_rx_rings; i++) {
3668                         struct rx_ring_info *rp = &np->rx_rings[i];
3669
3670                         niu_free_rx_ring_info(np, rp);
3671                 }
3672                 kfree(np->rx_rings);
3673                 np->rx_rings = NULL;
3674                 np->num_rx_rings = 0;
3675         }
3676
3677         if (np->tx_rings) {
3678                 for (i = 0; i < np->num_tx_rings; i++) {
3679                         struct tx_ring_info *rp = &np->tx_rings[i];
3680
3681                         niu_free_tx_ring_info(np, rp);
3682                 }
3683                 kfree(np->tx_rings);
3684                 np->tx_rings = NULL;
3685                 np->num_tx_rings = 0;
3686         }
3687 }
3688
3689 static int niu_alloc_rx_ring_info(struct niu *np,
3690                                   struct rx_ring_info *rp)
3691 {
3692         BUILD_BUG_ON(sizeof(struct rxdma_mailbox) != 64);
3693
3694         rp->rxhash = kzalloc(MAX_RBR_RING_SIZE * sizeof(struct page *),
3695                              GFP_KERNEL);
3696         if (!rp->rxhash)
3697                 return -ENOMEM;
3698
3699         rp->mbox = np->ops->alloc_coherent(np->device,
3700                                            sizeof(struct rxdma_mailbox),
3701                                            &rp->mbox_dma, GFP_KERNEL);
3702         if (!rp->mbox)
3703                 return -ENOMEM;
3704         if ((unsigned long)rp->mbox & (64UL - 1)) {
3705                 dev_err(np->device, PFX "%s: Coherent alloc gives misaligned "
3706                         "RXDMA mailbox %p\n", np->dev->name, rp->mbox);
3707                 return -EINVAL;
3708         }
3709
3710         rp->rcr = np->ops->alloc_coherent(np->device,
3711                                           MAX_RCR_RING_SIZE * sizeof(__le64),
3712                                           &rp->rcr_dma, GFP_KERNEL);
3713         if (!rp->rcr)
3714                 return -ENOMEM;
3715         if ((unsigned long)rp->rcr & (64UL - 1)) {
3716                 dev_err(np->device, PFX "%s: Coherent alloc gives misaligned "
3717                         "RXDMA RCR table %p\n", np->dev->name, rp->rcr);
3718                 return -EINVAL;
3719         }
3720         rp->rcr_table_size = MAX_RCR_RING_SIZE;
3721         rp->rcr_index = 0;
3722
3723         rp->rbr = np->ops->alloc_coherent(np->device,
3724                                           MAX_RBR_RING_SIZE * sizeof(__le32),
3725                                           &rp->rbr_dma, GFP_KERNEL);
3726         if (!rp->rbr)
3727                 return -ENOMEM;
3728         if ((unsigned long)rp->rbr & (64UL - 1)) {
3729                 dev_err(np->device, PFX "%s: Coherent alloc gives misaligned "
3730                         "RXDMA RBR table %p\n", np->dev->name, rp->rbr);
3731                 return -EINVAL;
3732         }
3733         rp->rbr_table_size = MAX_RBR_RING_SIZE;
3734         rp->rbr_index = 0;
3735         rp->rbr_pending = 0;
3736
3737         return 0;
3738 }
3739
3740 static void niu_set_max_burst(struct niu *np, struct tx_ring_info *rp)
3741 {
3742         int mtu = np->dev->mtu;
3743
3744         /* These values are recommended by the HW designers for fair
3745          * utilization of DRR amongst the rings.
3746          */
3747         rp->max_burst = mtu + 32;
3748         if (rp->max_burst > 4096)
3749                 rp->max_burst = 4096;
3750 }
3751
3752 static int niu_alloc_tx_ring_info(struct niu *np,
3753                                   struct tx_ring_info *rp)
3754 {
3755         BUILD_BUG_ON(sizeof(struct txdma_mailbox) != 64);
3756
3757         rp->mbox = np->ops->alloc_coherent(np->device,
3758                                            sizeof(struct txdma_mailbox),
3759                                            &rp->mbox_dma, GFP_KERNEL);
3760         if (!rp->mbox)
3761                 return -ENOMEM;
3762         if ((unsigned long)rp->mbox & (64UL - 1)) {
3763                 dev_err(np->device, PFX "%s: Coherent alloc gives misaligned "
3764                         "TXDMA mailbox %p\n", np->dev->name, rp->mbox);
3765                 return -EINVAL;
3766         }
3767
3768         rp->descr = np->ops->alloc_coherent(np->device,
3769                                             MAX_TX_RING_SIZE * sizeof(__le64),
3770                                             &rp->descr_dma, GFP_KERNEL);
3771         if (!rp->descr)
3772                 return -ENOMEM;
3773         if ((unsigned long)rp->descr & (64UL - 1)) {
3774                 dev_err(np->device, PFX "%s: Coherent alloc gives misaligned "
3775                         "TXDMA descr table %p\n", np->dev->name, rp->descr);
3776                 return -EINVAL;
3777         }
3778
3779         rp->pending = MAX_TX_RING_SIZE;
3780         rp->prod = 0;
3781         rp->cons = 0;
3782         rp->wrap_bit = 0;
3783
3784         /* XXX make these configurable... XXX */
3785         rp->mark_freq = rp->pending / 4;
3786
3787         niu_set_max_burst(np, rp);
3788
3789         return 0;
3790 }
3791
3792 static void niu_size_rbr(struct niu *np, struct rx_ring_info *rp)
3793 {
3794         u16 bss;
3795
3796         bss = min(PAGE_SHIFT, 15);
3797
3798         rp->rbr_block_size = 1 << bss;
3799         rp->rbr_blocks_per_page = 1 << (PAGE_SHIFT-bss);
3800
3801         rp->rbr_sizes[0] = 256;
3802         rp->rbr_sizes[1] = 1024;
3803         if (np->dev->mtu > ETH_DATA_LEN) {
3804                 switch (PAGE_SIZE) {
3805                 case 4 * 1024:
3806                         rp->rbr_sizes[2] = 4096;
3807                         break;
3808
3809                 default:
3810                         rp->rbr_sizes[2] = 8192;
3811                         break;
3812                 }
3813         } else {
3814                 rp->rbr_sizes[2] = 2048;
3815         }
3816         rp->rbr_sizes[3] = rp->rbr_block_size;
3817 }
3818
3819 static int niu_alloc_channels(struct niu *np)
3820 {
3821         struct niu_parent *parent = np->parent;
3822         int first_rx_channel, first_tx_channel;
3823         int i, port, err;
3824
3825         port = np->port;
3826         first_rx_channel = first_tx_channel = 0;
3827         for (i = 0; i < port; i++) {
3828                 first_rx_channel += parent->rxchan_per_port[i];
3829                 first_tx_channel += parent->txchan_per_port[i];
3830         }
3831
3832         np->num_rx_rings = parent->rxchan_per_port[port];
3833         np->num_tx_rings = parent->txchan_per_port[port];
3834
3835         np->rx_rings = kzalloc(np->num_rx_rings * sizeof(struct rx_ring_info),
3836                                GFP_KERNEL);
3837         err = -ENOMEM;
3838         if (!np->rx_rings)
3839                 goto out_err;
3840
3841         for (i = 0; i < np->num_rx_rings; i++) {
3842                 struct rx_ring_info *rp = &np->rx_rings[i];
3843
3844                 rp->np = np;
3845                 rp->rx_channel = first_rx_channel + i;
3846
3847                 err = niu_alloc_rx_ring_info(np, rp);
3848                 if (err)
3849                         goto out_err;
3850
3851                 niu_size_rbr(np, rp);
3852
3853                 /* XXX better defaults, configurable, etc... XXX */
3854                 rp->nonsyn_window = 64;
3855                 rp->nonsyn_threshold = rp->rcr_table_size - 64;
3856                 rp->syn_window = 64;
3857                 rp->syn_threshold = rp->rcr_table_size - 64;
3858                 rp->rcr_pkt_threshold = 16;
3859                 rp->rcr_timeout = 8;
3860                 rp->rbr_kick_thresh = RBR_REFILL_MIN;
3861                 if (rp->rbr_kick_thresh < rp->rbr_blocks_per_page)
3862                         rp->rbr_kick_thresh = rp->rbr_blocks_per_page;
3863
3864                 err = niu_rbr_fill(np, rp, GFP_KERNEL);
3865                 if (err)
3866                         return err;
3867         }
3868
3869         np->tx_rings = kzalloc(np->num_tx_rings * sizeof(struct tx_ring_info),
3870                                GFP_KERNEL);
3871         err = -ENOMEM;
3872         if (!np->tx_rings)
3873                 goto out_err;
3874
3875         for (i = 0; i < np->num_tx_rings; i++) {
3876                 struct tx_ring_info *rp = &np->tx_rings[i];
3877
3878                 rp->np = np;
3879                 rp->tx_channel = first_tx_channel + i;
3880
3881                 err = niu_alloc_tx_ring_info(np, rp);
3882                 if (err)
3883                         goto out_err;
3884         }
3885
3886         return 0;
3887
3888 out_err:
3889         niu_free_channels(np);
3890         return err;
3891 }
3892
3893 static int niu_tx_cs_sng_poll(struct niu *np, int channel)
3894 {
3895         int limit = 1000;
3896
3897         while (--limit > 0) {
3898                 u64 val = nr64(TX_CS(channel));
3899                 if (val & TX_CS_SNG_STATE)
3900                         return 0;
3901         }
3902         return -ENODEV;
3903 }
3904
3905 static int niu_tx_channel_stop(struct niu *np, int channel)
3906 {
3907         u64 val = nr64(TX_CS(channel));
3908
3909         val |= TX_CS_STOP_N_GO;
3910         nw64(TX_CS(channel), val);
3911
3912         return niu_tx_cs_sng_poll(np, channel);
3913 }
3914
3915 static int niu_tx_cs_reset_poll(struct niu *np, int channel)
3916 {
3917         int limit = 1000;
3918
3919         while (--limit > 0) {
3920                 u64 val = nr64(TX_CS(channel));
3921                 if (!(val & TX_CS_RST))
3922                         return 0;
3923         }
3924         return -ENODEV;
3925 }
3926
3927 static int niu_tx_channel_reset(struct niu *np, int channel)
3928 {
3929         u64 val = nr64(TX_CS(channel));
3930         int err;
3931
3932         val |= TX_CS_RST;
3933         nw64(TX_CS(channel), val);
3934
3935         err = niu_tx_cs_reset_poll(np, channel);
3936         if (!err)
3937                 nw64(TX_RING_KICK(channel), 0);
3938
3939         return err;
3940 }
3941
3942 static int niu_tx_channel_lpage_init(struct niu *np, int channel)
3943 {
3944         u64 val;
3945
3946         nw64(TX_LOG_MASK1(channel), 0);
3947         nw64(TX_LOG_VAL1(channel), 0);
3948         nw64(TX_LOG_MASK2(channel), 0);
3949         nw64(TX_LOG_VAL2(channel), 0);
3950         nw64(TX_LOG_PAGE_RELO1(channel), 0);
3951         nw64(TX_LOG_PAGE_RELO2(channel), 0);
3952         nw64(TX_LOG_PAGE_HDL(channel), 0);
3953
3954         val  = (u64)np->port << TX_LOG_PAGE_VLD_FUNC_SHIFT;
3955         val |= (TX_LOG_PAGE_VLD_PAGE0 | TX_LOG_PAGE_VLD_PAGE1);
3956         nw64(TX_LOG_PAGE_VLD(channel), val);
3957
3958         /* XXX TXDMA 32bit mode? XXX */
3959
3960         return 0;
3961 }
3962
3963 static void niu_txc_enable_port(struct niu *np, int on)
3964 {
3965         unsigned long flags;
3966         u64 val, mask;
3967
3968         niu_lock_parent(np, flags);
3969         val = nr64(TXC_CONTROL);
3970         mask = (u64)1 << np->port;
3971         if (on) {
3972                 val |= TXC_CONTROL_ENABLE | mask;
3973         } else {
3974                 val &= ~mask;
3975                 if ((val & ~TXC_CONTROL_ENABLE) == 0)
3976                         val &= ~TXC_CONTROL_ENABLE;
3977         }
3978         nw64(TXC_CONTROL, val);
3979         niu_unlock_parent(np, flags);
3980 }
3981
3982 static void niu_txc_set_imask(struct niu *np, u64 imask)
3983 {
3984         unsigned long flags;
3985         u64 val;
3986
3987         niu_lock_parent(np, flags);
3988         val = nr64(TXC_INT_MASK);
3989         val &= ~TXC_INT_MASK_VAL(np->port);
3990         val |= (imask << TXC_INT_MASK_VAL_SHIFT(np->port));
3991         niu_unlock_parent(np, flags);
3992 }
3993
3994 static void niu_txc_port_dma_enable(struct niu *np, int on)
3995 {
3996         u64 val = 0;
3997
3998         if (on) {
3999                 int i;
4000
4001                 for (i = 0; i < np->num_tx_rings; i++)
4002                         val |= (1 << np->tx_rings[i].tx_channel);
4003         }
4004         nw64(TXC_PORT_DMA(np->port), val);
4005 }
4006
4007 static int niu_init_one_tx_channel(struct niu *np, struct tx_ring_info *rp)
4008 {
4009         int err, channel = rp->tx_channel;
4010         u64 val, ring_len;
4011
4012         err = niu_tx_channel_stop(np, channel);
4013         if (err)
4014                 return err;
4015
4016         err = niu_tx_channel_reset(np, channel);
4017         if (err)
4018                 return err;
4019
4020         err = niu_tx_channel_lpage_init(np, channel);
4021         if (err)
4022                 return err;
4023
4024         nw64(TXC_DMA_MAX(channel), rp->max_burst);
4025         nw64(TX_ENT_MSK(channel), 0);
4026
4027         if (rp->descr_dma & ~(TX_RNG_CFIG_STADDR_BASE |
4028                               TX_RNG_CFIG_STADDR)) {
4029                 dev_err(np->device, PFX "%s: TX ring channel %d "
4030                         "DMA addr (%llx) is not aligned.\n",
4031                         np->dev->name, channel,
4032                         (unsigned long long) rp->descr_dma);
4033                 return -EINVAL;
4034         }
4035
4036         /* The length field in TX_RNG_CFIG is measured in 64-byte
4037          * blocks.  rp->pending is the number of TX descriptors in
4038          * our ring, 8 bytes each, thus we divide by 8 bytes more
4039          * to get the proper value the chip wants.
4040          */
4041         ring_len = (rp->pending / 8);
4042
4043         val = ((ring_len << TX_RNG_CFIG_LEN_SHIFT) |
4044                rp->descr_dma);
4045         nw64(TX_RNG_CFIG(channel), val);
4046
4047         if (((rp->mbox_dma >> 32) & ~TXDMA_MBH_MBADDR) ||
4048             ((u32)rp->mbox_dma & ~TXDMA_MBL_MBADDR)) {
4049                 dev_err(np->device, PFX "%s: TX ring channel %d "
4050                         "MBOX addr (%llx) is has illegal bits.\n",
4051                         np->dev->name, channel,
4052                         (unsigned long long) rp->mbox_dma);
4053                 return -EINVAL;
4054         }
4055         nw64(TXDMA_MBH(channel), rp->mbox_dma >> 32);
4056         nw64(TXDMA_MBL(channel), rp->mbox_dma & TXDMA_MBL_MBADDR);
4057
4058         nw64(TX_CS(channel), 0);
4059
4060         rp->last_pkt_cnt = 0;
4061
4062         return 0;
4063 }
4064
4065 static void niu_init_rdc_groups(struct niu *np)
4066 {
4067         struct niu_rdc_tables *tp = &np->parent->rdc_group_cfg[np->port];
4068         int i, first_table_num = tp->first_table_num;
4069
4070         for (i = 0; i < tp->num_tables; i++) {
4071                 struct rdc_table *tbl = &tp->tables[i];
4072                 int this_table = first_table_num + i;
4073                 int slot;
4074
4075                 for (slot = 0; slot < NIU_RDC_TABLE_SLOTS; slot++)
4076                         nw64(RDC_TBL(this_table, slot),
4077                              tbl->rxdma_channel[slot]);
4078         }
4079
4080         nw64(DEF_RDC(np->port), np->parent->rdc_default[np->port]);
4081 }
4082
4083 static void niu_init_drr_weight(struct niu *np)
4084 {
4085         int type = phy_decode(np->parent->port_phy, np->port);
4086         u64 val;
4087
4088         switch (type) {
4089         case PORT_TYPE_10G:
4090                 val = PT_DRR_WEIGHT_DEFAULT_10G;
4091                 break;
4092
4093         case PORT_TYPE_1G:
4094         default:
4095                 val = PT_DRR_WEIGHT_DEFAULT_1G;
4096                 break;
4097         }
4098         nw64(PT_DRR_WT(np->port), val);
4099 }
4100
4101 static int niu_init_hostinfo(struct niu *np)
4102 {
4103         struct niu_parent *parent = np->parent;
4104         struct niu_rdc_tables *tp = &parent->rdc_group_cfg[np->port];
4105         int i, err, num_alt = niu_num_alt_addr(np);
4106         int first_rdc_table = tp->first_table_num;
4107
4108         err = niu_set_primary_mac_rdc_table(np, first_rdc_table, 1);
4109         if (err)
4110                 return err;
4111
4112         err = niu_set_multicast_mac_rdc_table(np, first_rdc_table, 1);
4113         if (err)
4114                 return err;
4115
4116         for (i = 0; i < num_alt; i++) {
4117                 err = niu_set_alt_mac_rdc_table(np, i, first_rdc_table, 1);
4118                 if (err)
4119                         return err;
4120         }
4121
4122         return 0;
4123 }
4124
4125 static int niu_rx_channel_reset(struct niu *np, int channel)
4126 {
4127         return niu_set_and_wait_clear(np, RXDMA_CFIG1(channel),
4128                                       RXDMA_CFIG1_RST, 1000, 10,
4129                                       "RXDMA_CFIG1");
4130 }
4131
4132 static int niu_rx_channel_lpage_init(struct niu *np, int channel)
4133 {
4134         u64 val;
4135
4136         nw64(RX_LOG_MASK1(channel), 0);
4137         nw64(RX_LOG_VAL1(channel), 0);
4138         nw64(RX_LOG_MASK2(channel), 0);
4139         nw64(RX_LOG_VAL2(channel), 0);
4140         nw64(RX_LOG_PAGE_RELO1(channel), 0);
4141         nw64(RX_LOG_PAGE_RELO2(channel), 0);
4142         nw64(RX_LOG_PAGE_HDL(channel), 0);
4143
4144         val  = (u64)np->port << RX_LOG_PAGE_VLD_FUNC_SHIFT;
4145         val |= (RX_LOG_PAGE_VLD_PAGE0 | RX_LOG_PAGE_VLD_PAGE1);
4146         nw64(RX_LOG_PAGE_VLD(channel), val);
4147
4148         return 0;
4149 }
4150
4151 static void niu_rx_channel_wred_init(struct niu *np, struct rx_ring_info *rp)
4152 {
4153         u64 val;
4154
4155         val = (((u64)rp->nonsyn_window << RDC_RED_PARA_WIN_SHIFT) |
4156                ((u64)rp->nonsyn_threshold << RDC_RED_PARA_THRE_SHIFT) |
4157                ((u64)rp->syn_window << RDC_RED_PARA_WIN_SYN_SHIFT) |
4158                ((u64)rp->syn_threshold << RDC_RED_PARA_THRE_SYN_SHIFT));
4159         nw64(RDC_RED_PARA(rp->rx_channel), val);
4160 }
4161
4162 static int niu_compute_rbr_cfig_b(struct rx_ring_info *rp, u64 *ret)
4163 {
4164         u64 val = 0;
4165
4166         switch (rp->rbr_block_size) {
4167         case 4 * 1024:
4168                 val |= (RBR_BLKSIZE_4K << RBR_CFIG_B_BLKSIZE_SHIFT);
4169                 break;
4170         case 8 * 1024:
4171                 val |= (RBR_BLKSIZE_8K << RBR_CFIG_B_BLKSIZE_SHIFT);
4172                 break;
4173         case 16 * 1024:
4174                 val |= (RBR_BLKSIZE_16K << RBR_CFIG_B_BLKSIZE_SHIFT);
4175                 break;
4176         case 32 * 1024:
4177                 val |= (RBR_BLKSIZE_32K << RBR_CFIG_B_BLKSIZE_SHIFT);
4178                 break;
4179         default:
4180                 return -EINVAL;
4181         }
4182         val |= RBR_CFIG_B_VLD2;
4183         switch (rp->rbr_sizes[2]) {
4184         case 2 * 1024:
4185                 val |= (RBR_BUFSZ2_2K << RBR_CFIG_B_BUFSZ2_SHIFT);
4186                 break;
4187         case 4 * 1024:
4188                 val |= (RBR_BUFSZ2_4K << RBR_CFIG_B_BUFSZ2_SHIFT);
4189                 break;
4190         case 8 * 1024:
4191                 val |= (RBR_BUFSZ2_8K << RBR_CFIG_B_BUFSZ2_SHIFT);
4192                 break;
4193         case 16 * 1024:
4194                 val |= (RBR_BUFSZ2_16K << RBR_CFIG_B_BUFSZ2_SHIFT);
4195                 break;
4196
4197         default:
4198                 return -EINVAL;
4199         }
4200         val |= RBR_CFIG_B_VLD1;
4201         switch (rp->rbr_sizes[1]) {
4202         case 1 * 1024:
4203                 val |= (RBR_BUFSZ1_1K << RBR_CFIG_B_BUFSZ1_SHIFT);
4204                 break;
4205         case 2 * 1024:
4206                 val |= (RBR_BUFSZ1_2K << RBR_CFIG_B_BUFSZ1_SHIFT);
4207                 break;
4208         case 4 * 1024:
4209                 val |= (RBR_BUFSZ1_4K << RBR_CFIG_B_BUFSZ1_SHIFT);
4210                 break;
4211         case 8 * 1024:
4212                 val |= (RBR_BUFSZ1_8K << RBR_CFIG_B_BUFSZ1_SHIFT);
4213                 break;
4214
4215         default:
4216                 return -EINVAL;
4217         }
4218         val |= RBR_CFIG_B_VLD0;
4219         switch (rp->rbr_sizes[0]) {
4220         case 256:
4221                 val |= (RBR_BUFSZ0_256 << RBR_CFIG_B_BUFSZ0_SHIFT);
4222                 break;
4223         case 512:
4224                 val |= (RBR_BUFSZ0_512 << RBR_CFIG_B_BUFSZ0_SHIFT);
4225                 break;
4226         case 1 * 1024:
4227                 val |= (RBR_BUFSZ0_1K << RBR_CFIG_B_BUFSZ0_SHIFT);
4228                 break;
4229         case 2 * 1024:
4230                 val |= (RBR_BUFSZ0_2K << RBR_CFIG_B_BUFSZ0_SHIFT);
4231                 break;
4232
4233         default:
4234                 return -EINVAL;
4235         }
4236
4237         *ret = val;
4238         return 0;
4239 }
4240
4241 static int niu_enable_rx_channel(struct niu *np, int channel, int on)
4242 {
4243         u64 val = nr64(RXDMA_CFIG1(channel));
4244         int limit;
4245
4246         if (on)
4247                 val |= RXDMA_CFIG1_EN;
4248         else
4249                 val &= ~RXDMA_CFIG1_EN;
4250         nw64(RXDMA_CFIG1(channel), val);
4251
4252         limit = 1000;
4253         while (--limit > 0) {
4254                 if (nr64(RXDMA_CFIG1(channel)) & RXDMA_CFIG1_QST)
4255                         break;
4256                 udelay(10);
4257         }
4258         if (limit <= 0)
4259                 return -ENODEV;
4260         return 0;
4261 }
4262
4263 static int niu_init_one_rx_channel(struct niu *np, struct rx_ring_info *rp)
4264 {
4265         int err, channel = rp->rx_channel;
4266         u64 val;
4267
4268         err = niu_rx_channel_reset(np, channel);
4269         if (err)
4270                 return err;
4271
4272         err = niu_rx_channel_lpage_init(np, channel);
4273         if (err)
4274                 return err;
4275
4276         niu_rx_channel_wred_init(np, rp);
4277
4278         nw64(RX_DMA_ENT_MSK(channel), RX_DMA_ENT_MSK_RBR_EMPTY);
4279         nw64(RX_DMA_CTL_STAT(channel),
4280              (RX_DMA_CTL_STAT_MEX |
4281               RX_DMA_CTL_STAT_RCRTHRES |
4282               RX_DMA_CTL_STAT_RCRTO |
4283               RX_DMA_CTL_STAT_RBR_EMPTY));
4284         nw64(RXDMA_CFIG1(channel), rp->mbox_dma >> 32);
4285         nw64(RXDMA_CFIG2(channel), (rp->mbox_dma & 0x00000000ffffffc0));
4286         nw64(RBR_CFIG_A(channel),
4287              ((u64)rp->rbr_table_size << RBR_CFIG_A_LEN_SHIFT) |
4288              (rp->rbr_dma & (RBR_CFIG_A_STADDR_BASE | RBR_CFIG_A_STADDR)));
4289         err = niu_compute_rbr_cfig_b(rp, &val);
4290         if (err)
4291                 return err;
4292         nw64(RBR_CFIG_B(channel), val);
4293         nw64(RCRCFIG_A(channel),
4294              ((u64)rp->rcr_table_size << RCRCFIG_A_LEN_SHIFT) |
4295              (rp->rcr_dma & (RCRCFIG_A_STADDR_BASE | RCRCFIG_A_STADDR)));
4296         nw64(RCRCFIG_B(channel),
4297              ((u64)rp->rcr_pkt_threshold << RCRCFIG_B_PTHRES_SHIFT) |
4298              RCRCFIG_B_ENTOUT |
4299              ((u64)rp->rcr_timeout << RCRCFIG_B_TIMEOUT_SHIFT));
4300
4301         err = niu_enable_rx_channel(np, channel, 1);
4302         if (err)
4303                 return err;
4304
4305         nw64(RBR_KICK(channel), rp->rbr_index);
4306
4307         val = nr64(RX_DMA_CTL_STAT(channel));
4308         val |= RX_DMA_CTL_STAT_RBR_EMPTY;
4309         nw64(RX_DMA_CTL_STAT(channel), val);
4310
4311         return 0;
4312 }
4313
4314 static int niu_init_rx_channels(struct niu *np)
4315 {
4316         unsigned long flags;
4317         u64 seed = jiffies_64;
4318         int err, i;
4319
4320         niu_lock_parent(np, flags);
4321         nw64(RX_DMA_CK_DIV, np->parent->rxdma_clock_divider);
4322         nw64(RED_RAN_INIT, RED_RAN_INIT_OPMODE | (seed & RED_RAN_INIT_VAL));
4323         niu_unlock_parent(np, flags);
4324
4325         /* XXX RXDMA 32bit mode? XXX */
4326
4327         niu_init_rdc_groups(np);
4328         niu_init_drr_weight(np);
4329
4330         err = niu_init_hostinfo(np);
4331         if (err)
4332                 return err;
4333
4334         for (i = 0; i < np->num_rx_rings; i++) {
4335                 struct rx_ring_info *rp = &np->rx_rings[i];
4336
4337                 err = niu_init_one_rx_channel(np, rp);
4338                 if (err)
4339                         return err;
4340         }
4341
4342         return 0;
4343 }
4344
4345 static int niu_set_ip_frag_rule(struct niu *np)
4346 {
4347         struct niu_parent *parent = np->parent;
4348         struct niu_classifier *cp = &np->clas;
4349         struct niu_tcam_entry *tp;
4350         int index, err;
4351
4352         /* XXX fix this allocation scheme XXX */
4353         index = cp->tcam_index;
4354         tp = &parent->tcam[index];
4355
4356         /* Note that the noport bit is the same in both ipv4 and
4357          * ipv6 format TCAM entries.
4358          */
4359         memset(tp, 0, sizeof(*tp));
4360         tp->key[1] = TCAM_V4KEY1_NOPORT;
4361         tp->key_mask[1] = TCAM_V4KEY1_NOPORT;
4362         tp->assoc_data = (TCAM_ASSOCDATA_TRES_USE_OFFSET |
4363                           ((u64)0 << TCAM_ASSOCDATA_OFFSET_SHIFT));
4364         err = tcam_write(np, index, tp->key, tp->key_mask);
4365         if (err)
4366                 return err;
4367         err = tcam_assoc_write(np, index, tp->assoc_data);
4368         if (err)
4369                 return err;
4370
4371         return 0;
4372 }
4373
4374 static int niu_init_classifier_hw(struct niu *np)
4375 {
4376         struct niu_parent *parent = np->parent;
4377         struct niu_classifier *cp = &np->clas;
4378         int i, err;
4379
4380         nw64(H1POLY, cp->h1_init);
4381         nw64(H2POLY, cp->h2_init);
4382
4383         err = niu_init_hostinfo(np);
4384         if (err)
4385                 return err;
4386
4387         for (i = 0; i < ENET_VLAN_TBL_NUM_ENTRIES; i++) {
4388                 struct niu_vlan_rdc *vp = &cp->vlan_mappings[i];
4389
4390                 vlan_tbl_write(np, i, np->port,
4391                                vp->vlan_pref, vp->rdc_num);
4392         }
4393
4394         for (i = 0; i < cp->num_alt_mac_mappings; i++) {
4395                 struct niu_altmac_rdc *ap = &cp->alt_mac_mappings[i];
4396
4397                 err = niu_set_alt_mac_rdc_table(np, ap->alt_mac_num,
4398                                                 ap->rdc_num, ap->mac_pref);
4399                 if (err)
4400                         return err;
4401         }
4402
4403         for (i = CLASS_CODE_USER_PROG1; i <= CLASS_CODE_SCTP_IPV6; i++) {
4404                 int index = i - CLASS_CODE_USER_PROG1;
4405
4406                 err = niu_set_tcam_key(np, i, parent->tcam_key[index]);
4407                 if (err)
4408                         return err;
4409                 err = niu_set_flow_key(np, i, parent->flow_key[index]);
4410                 if (err)
4411                         return err;
4412         }
4413
4414         err = niu_set_ip_frag_rule(np);
4415         if (err)
4416                 return err;
4417
4418         tcam_enable(np, 1);
4419
4420         return 0;
4421 }
4422
4423 static int niu_zcp_write(struct niu *np, int index, u64 *data)
4424 {
4425         nw64(ZCP_RAM_DATA0, data[0]);
4426         nw64(ZCP_RAM_DATA1, data[1]);
4427         nw64(ZCP_RAM_DATA2, data[2]);
4428         nw64(ZCP_RAM_DATA3, data[3]);
4429         nw64(ZCP_RAM_DATA4, data[4]);
4430         nw64(ZCP_RAM_BE, ZCP_RAM_BE_VAL);
4431         nw64(ZCP_RAM_ACC,
4432              (ZCP_RAM_ACC_WRITE |
4433               (0 << ZCP_RAM_ACC_ZFCID_SHIFT) |
4434               (ZCP_RAM_SEL_CFIFO(np->port) << ZCP_RAM_ACC_RAM_SEL_SHIFT)));
4435
4436         return niu_wait_bits_clear(np, ZCP_RAM_ACC, ZCP_RAM_ACC_BUSY,
4437                                    1000, 100);
4438 }
4439
4440 static int niu_zcp_read(struct niu *np, int index, u64 *data)
4441 {
4442         int err;
4443
4444         err = niu_wait_bits_clear(np, ZCP_RAM_ACC, ZCP_RAM_ACC_BUSY,
4445                                   1000, 100);
4446         if (err) {
4447                 dev_err(np->device, PFX "%s: ZCP read busy won't clear, "
4448                         "ZCP_RAM_ACC[%llx]\n", np->dev->name,
4449                         (unsigned long long) nr64(ZCP_RAM_ACC));
4450                 return err;
4451         }
4452
4453         nw64(ZCP_RAM_ACC,
4454              (ZCP_RAM_ACC_READ |
4455               (0 << ZCP_RAM_ACC_ZFCID_SHIFT) |
4456               (ZCP_RAM_SEL_CFIFO(np->port) << ZCP_RAM_ACC_RAM_SEL_SHIFT)));
4457
4458         err = niu_wait_bits_clear(np, ZCP_RAM_ACC, ZCP_RAM_ACC_BUSY,
4459                                   1000, 100);
4460         if (err) {
4461                 dev_err(np->device, PFX "%s: ZCP read busy2 won't clear, "
4462                         "ZCP_RAM_ACC[%llx]\n", np->dev->name,
4463                         (unsigned long long) nr64(ZCP_RAM_ACC));
4464                 return err;
4465         }
4466
4467         data[0] = nr64(ZCP_RAM_DATA0);
4468         data[1] = nr64(ZCP_RAM_DATA1);
4469         data[2] = nr64(ZCP_RAM_DATA2);
4470         data[3] = nr64(ZCP_RAM_DATA3);
4471         data[4] = nr64(ZCP_RAM_DATA4);
4472
4473         return 0;
4474 }
4475
4476 static void niu_zcp_cfifo_reset(struct niu *np)
4477 {
4478         u64 val = nr64(RESET_CFIFO);
4479
4480         val |= RESET_CFIFO_RST(np->port);
4481         nw64(RESET_CFIFO, val);
4482         udelay(10);
4483
4484         val &= ~RESET_CFIFO_RST(np->port);
4485         nw64(RESET_CFIFO, val);
4486 }
4487
4488 static int niu_init_zcp(struct niu *np)
4489 {
4490         u64 data[5], rbuf[5];
4491         int i, max, err;
4492
4493         if (np->parent->plat_type != PLAT_TYPE_NIU) {
4494                 if (np->port == 0 || np->port == 1)
4495                         max = ATLAS_P0_P1_CFIFO_ENTRIES;
4496                 else
4497                         max = ATLAS_P2_P3_CFIFO_ENTRIES;
4498         } else
4499                 max = NIU_CFIFO_ENTRIES;
4500
4501         data[0] = 0;
4502         data[1] = 0;
4503         data[2] = 0;
4504         data[3] = 0;
4505         data[4] = 0;
4506
4507         for (i = 0; i < max; i++) {
4508                 err = niu_zcp_write(np, i, data);
4509                 if (err)
4510                         return err;
4511                 err = niu_zcp_read(np, i, rbuf);
4512                 if (err)
4513                         return err;
4514         }
4515
4516         niu_zcp_cfifo_reset(np);
4517         nw64(CFIFO_ECC(np->port), 0);
4518         nw64(ZCP_INT_STAT, ZCP_INT_STAT_ALL);
4519         (void) nr64(ZCP_INT_STAT);
4520         nw64(ZCP_INT_MASK, ZCP_INT_MASK_ALL);
4521
4522         return 0;
4523 }
4524
4525 static void niu_ipp_write(struct niu *np, int index, u64 *data)
4526 {
4527         u64 val = nr64_ipp(IPP_CFIG);
4528
4529         nw64_ipp(IPP_CFIG, val | IPP_CFIG_DFIFO_PIO_W);
4530         nw64_ipp(IPP_DFIFO_WR_PTR, index);
4531         nw64_ipp(IPP_DFIFO_WR0, data[0]);
4532         nw64_ipp(IPP_DFIFO_WR1, data[1]);
4533         nw64_ipp(IPP_DFIFO_WR2, data[2]);
4534         nw64_ipp(IPP_DFIFO_WR3, data[3]);
4535         nw64_ipp(IPP_DFIFO_WR4, data[4]);
4536         nw64_ipp(IPP_CFIG, val & ~IPP_CFIG_DFIFO_PIO_W);
4537 }
4538
4539 static void niu_ipp_read(struct niu *np, int index, u64 *data)
4540 {
4541         nw64_ipp(IPP_DFIFO_RD_PTR, index);
4542         data[0] = nr64_ipp(IPP_DFIFO_RD0);
4543         data[1] = nr64_ipp(IPP_DFIFO_RD1);
4544         data[2] = nr64_ipp(IPP_DFIFO_RD2);
4545         data[3] = nr64_ipp(IPP_DFIFO_RD3);
4546         data[4] = nr64_ipp(IPP_DFIFO_RD4);
4547 }
4548
4549 static int niu_ipp_reset(struct niu *np)
4550 {
4551         return niu_set_and_wait_clear_ipp(np, IPP_CFIG, IPP_CFIG_SOFT_RST,
4552                                           1000, 100, "IPP_CFIG");
4553 }
4554
4555 static int niu_init_ipp(struct niu *np)
4556 {
4557         u64 data[5], rbuf[5], val;
4558         int i, max, err;
4559
4560         if (np->parent->plat_type != PLAT_TYPE_NIU) {
4561                 if (np->port == 0 || np->port == 1)
4562                         max = ATLAS_P0_P1_DFIFO_ENTRIES;
4563                 else
4564                         max = ATLAS_P2_P3_DFIFO_ENTRIES;
4565         } else
4566                 max = NIU_DFIFO_ENTRIES;
4567
4568         data[0] = 0;
4569         data[1] = 0;
4570         data[2] = 0;
4571         data[3] = 0;
4572         data[4] = 0;
4573
4574         for (i = 0; i < max; i++) {
4575                 niu_ipp_write(np, i, data);
4576                 niu_ipp_read(np, i, rbuf);
4577         }
4578
4579         (void) nr64_ipp(IPP_INT_STAT);
4580         (void) nr64_ipp(IPP_INT_STAT);
4581
4582         err = niu_ipp_reset(np);
4583         if (err)
4584                 return err;
4585
4586         (void) nr64_ipp(IPP_PKT_DIS);
4587         (void) nr64_ipp(IPP_BAD_CS_CNT);
4588         (void) nr64_ipp(IPP_ECC);
4589
4590         (void) nr64_ipp(IPP_INT_STAT);
4591
4592         nw64_ipp(IPP_MSK, ~IPP_MSK_ALL);
4593
4594         val = nr64_ipp(IPP_CFIG);
4595         val &= ~IPP_CFIG_IP_MAX_PKT;
4596         val |= (IPP_CFIG_IPP_ENABLE |
4597                 IPP_CFIG_DFIFO_ECC_EN |
4598                 IPP_CFIG_DROP_BAD_CRC |
4599                 IPP_CFIG_CKSUM_EN |
4600                 (0x1ffff << IPP_CFIG_IP_MAX_PKT_SHIFT));
4601         nw64_ipp(IPP_CFIG, val);
4602
4603         return 0;
4604 }
4605
4606 static void niu_handle_led(struct niu *np, int status)
4607 {
4608         u64 val;
4609         val = nr64_mac(XMAC_CONFIG);
4610
4611         if ((np->flags & NIU_FLAGS_10G) != 0 &&
4612             (np->flags & NIU_FLAGS_FIBER) != 0) {
4613                 if (status) {
4614                         val |= XMAC_CONFIG_LED_POLARITY;
4615                         val &= ~XMAC_CONFIG_FORCE_LED_ON;
4616                 } else {
4617                         val |= XMAC_CONFIG_FORCE_LED_ON;
4618                         val &= ~XMAC_CONFIG_LED_POLARITY;
4619                 }
4620         }
4621
4622         nw64_mac(XMAC_CONFIG, val);
4623 }
4624
4625 static void niu_init_xif_xmac(struct niu *np)
4626 {
4627         struct niu_link_config *lp = &np->link_config;
4628         u64 val;
4629
4630         if (np->flags & NIU_FLAGS_XCVR_SERDES) {
4631                 val = nr64(MIF_CONFIG);
4632                 val |= MIF_CONFIG_ATCA_GE;
4633                 nw64(MIF_CONFIG, val);
4634         }
4635
4636         val = nr64_mac(XMAC_CONFIG);
4637         val &= ~XMAC_CONFIG_SEL_POR_CLK_SRC;
4638
4639         val |= XMAC_CONFIG_TX_OUTPUT_EN;
4640
4641         if (lp->loopback_mode == LOOPBACK_MAC) {
4642                 val &= ~XMAC_CONFIG_SEL_POR_CLK_SRC;
4643                 val |= XMAC_CONFIG_LOOPBACK;
4644         } else {
4645                 val &= ~XMAC_CONFIG_LOOPBACK;
4646         }
4647
4648         if (np->flags & NIU_FLAGS_10G) {
4649                 val &= ~XMAC_CONFIG_LFS_DISABLE;
4650         } else {
4651                 val |= XMAC_CONFIG_LFS_DISABLE;
4652                 if (!(np->flags & NIU_FLAGS_FIBER) &&
4653                     !(np->flags & NIU_FLAGS_XCVR_SERDES))
4654                         val |= XMAC_CONFIG_1G_PCS_BYPASS;
4655                 else
4656                         val &= ~XMAC_CONFIG_1G_PCS_BYPASS;
4657         }
4658
4659         val &= ~XMAC_CONFIG_10G_XPCS_BYPASS;
4660
4661         if (lp->active_speed == SPEED_100)
4662                 val |= XMAC_CONFIG_SEL_CLK_25MHZ;
4663         else
4664                 val &= ~XMAC_CONFIG_SEL_CLK_25MHZ;
4665
4666         nw64_mac(XMAC_CONFIG, val);
4667
4668         val = nr64_mac(XMAC_CONFIG);
4669         val &= ~XMAC_CONFIG_MODE_MASK;
4670         if (np->flags & NIU_FLAGS_10G) {
4671                 val |= XMAC_CONFIG_MODE_XGMII;
4672         } else {
4673                 if (lp->active_speed == SPEED_100)
4674                         val |= XMAC_CONFIG_MODE_MII;
4675                 else
4676                         val |= XMAC_CONFIG_MODE_GMII;
4677         }
4678
4679         nw64_mac(XMAC_CONFIG, val);
4680 }
4681
4682 static void niu_init_xif_bmac(struct niu *np)
4683 {
4684         struct niu_link_config *lp = &np->link_config;
4685         u64 val;
4686
4687         val = BMAC_XIF_CONFIG_TX_OUTPUT_EN;
4688
4689         if (lp->loopback_mode == LOOPBACK_MAC)
4690                 val |= BMAC_XIF_CONFIG_MII_LOOPBACK;
4691         else
4692                 val &= ~BMAC_XIF_CONFIG_MII_LOOPBACK;
4693
4694         if (lp->active_speed == SPEED_1000)
4695                 val |= BMAC_XIF_CONFIG_GMII_MODE;
4696         else
4697                 val &= ~BMAC_XIF_CONFIG_GMII_MODE;
4698
4699         val &= ~(BMAC_XIF_CONFIG_LINK_LED |
4700                  BMAC_XIF_CONFIG_LED_POLARITY);
4701
4702         if (!(np->flags & NIU_FLAGS_10G) &&
4703             !(np->flags & NIU_FLAGS_FIBER) &&
4704             lp->active_speed == SPEED_100)
4705                 val |= BMAC_XIF_CONFIG_25MHZ_CLOCK;
4706         else
4707                 val &= ~BMAC_XIF_CONFIG_25MHZ_CLOCK;
4708
4709         nw64_mac(BMAC_XIF_CONFIG, val);
4710 }
4711
4712 static void niu_init_xif(struct niu *np)
4713 {
4714         if (np->flags & NIU_FLAGS_XMAC)
4715                 niu_init_xif_xmac(np);
4716         else
4717                 niu_init_xif_bmac(np);
4718 }
4719
4720 static void niu_pcs_mii_reset(struct niu *np)
4721 {
4722         int limit = 1000;
4723         u64 val = nr64_pcs(PCS_MII_CTL);
4724         val |= PCS_MII_CTL_RST;
4725         nw64_pcs(PCS_MII_CTL, val);
4726         while ((--limit >= 0) && (val & PCS_MII_CTL_RST)) {
4727                 udelay(100);
4728                 val = nr64_pcs(PCS_MII_CTL);
4729         }
4730 }
4731
4732 static void niu_xpcs_reset(struct niu *np)
4733 {
4734         int limit = 1000;
4735         u64 val = nr64_xpcs(XPCS_CONTROL1);
4736         val |= XPCS_CONTROL1_RESET;
4737         nw64_xpcs(XPCS_CONTROL1, val);
4738         while ((--limit >= 0) && (val & XPCS_CONTROL1_RESET)) {
4739                 udelay(100);
4740                 val = nr64_xpcs(XPCS_CONTROL1);
4741         }
4742 }
4743
4744 static int niu_init_pcs(struct niu *np)
4745 {
4746         struct niu_link_config *lp = &np->link_config;
4747         u64 val;
4748
4749         switch (np->flags & (NIU_FLAGS_10G |
4750                              NIU_FLAGS_FIBER |
4751                              NIU_FLAGS_XCVR_SERDES)) {
4752         case NIU_FLAGS_FIBER:
4753                 /* 1G fiber */
4754                 nw64_pcs(PCS_CONF, PCS_CONF_MASK | PCS_CONF_ENABLE);
4755                 nw64_pcs(PCS_DPATH_MODE, 0);
4756                 niu_pcs_mii_reset(np);
4757                 break;
4758
4759         case NIU_FLAGS_10G:
4760         case NIU_FLAGS_10G | NIU_FLAGS_FIBER:
4761         case NIU_FLAGS_10G | NIU_FLAGS_XCVR_SERDES:
4762                 /* 10G SERDES */
4763                 if (!(np->flags & NIU_FLAGS_XMAC))
4764                         return -EINVAL;
4765
4766                 /* 10G copper or fiber */
4767                 val = nr64_mac(XMAC_CONFIG);
4768                 val &= ~XMAC_CONFIG_10G_XPCS_BYPASS;
4769                 nw64_mac(XMAC_CONFIG, val);
4770
4771                 niu_xpcs_reset(np);
4772
4773                 val = nr64_xpcs(XPCS_CONTROL1);
4774                 if (lp->loopback_mode == LOOPBACK_PHY)
4775                         val |= XPCS_CONTROL1_LOOPBACK;
4776                 else
4777                         val &= ~XPCS_CONTROL1_LOOPBACK;
4778                 nw64_xpcs(XPCS_CONTROL1, val);
4779
4780                 nw64_xpcs(XPCS_DESKEW_ERR_CNT, 0);
4781                 (void) nr64_xpcs(XPCS_SYMERR_CNT01);
4782                 (void) nr64_xpcs(XPCS_SYMERR_CNT23);
4783                 break;
4784
4785
4786         case NIU_FLAGS_XCVR_SERDES:
4787                 /* 1G SERDES */
4788                 niu_pcs_mii_reset(np);
4789                 nw64_pcs(PCS_CONF, PCS_CONF_MASK | PCS_CONF_ENABLE);
4790                 nw64_pcs(PCS_DPATH_MODE, 0);
4791                 break;
4792
4793         case 0:
4794                 /* 1G copper */
4795         case NIU_FLAGS_XCVR_SERDES | NIU_FLAGS_FIBER:
4796                 /* 1G RGMII FIBER */
4797                 nw64_pcs(PCS_DPATH_MODE, PCS_DPATH_MODE_MII);
4798                 niu_pcs_mii_reset(np);
4799                 break;
4800
4801         default:
4802                 return -EINVAL;
4803         }
4804
4805         return 0;
4806 }
4807
4808 static int niu_reset_tx_xmac(struct niu *np)
4809 {
4810         return niu_set_and_wait_clear_mac(np, XTXMAC_SW_RST,
4811                                           (XTXMAC_SW_RST_REG_RS |
4812                                            XTXMAC_SW_RST_SOFT_RST),
4813                                           1000, 100, "XTXMAC_SW_RST");
4814 }
4815
4816 static int niu_reset_tx_bmac(struct niu *np)
4817 {
4818         int limit;
4819
4820         nw64_mac(BTXMAC_SW_RST, BTXMAC_SW_RST_RESET);
4821         limit = 1000;
4822         while (--limit >= 0) {
4823                 if (!(nr64_mac(BTXMAC_SW_RST) & BTXMAC_SW_RST_RESET))
4824                         break;
4825                 udelay(100);
4826         }
4827         if (limit < 0) {
4828                 dev_err(np->device, PFX "Port %u TX BMAC would not reset, "
4829                         "BTXMAC_SW_RST[%llx]\n",
4830                         np->port,
4831                         (unsigned long long) nr64_mac(BTXMAC_SW_RST));
4832                 return -ENODEV;
4833         }
4834
4835         return 0;
4836 }
4837
4838 static int niu_reset_tx_mac(struct niu *np)
4839 {
4840         if (np->flags & NIU_FLAGS_XMAC)
4841                 return niu_reset_tx_xmac(np);
4842         else
4843                 return niu_reset_tx_bmac(np);
4844 }
4845
4846 static void niu_init_tx_xmac(struct niu *np, u64 min, u64 max)
4847 {
4848         u64 val;
4849
4850         val = nr64_mac(XMAC_MIN);
4851         val &= ~(XMAC_MIN_TX_MIN_PKT_SIZE |
4852                  XMAC_MIN_RX_MIN_PKT_SIZE);
4853         val |= (min << XMAC_MIN_RX_MIN_PKT_SIZE_SHFT);
4854         val |= (min << XMAC_MIN_TX_MIN_PKT_SIZE_SHFT);
4855         nw64_mac(XMAC_MIN, val);
4856
4857         nw64_mac(XMAC_MAX, max);
4858
4859         nw64_mac(XTXMAC_STAT_MSK, ~(u64)0);
4860
4861         val = nr64_mac(XMAC_IPG);
4862         if (np->flags & NIU_FLAGS_10G) {
4863                 val &= ~XMAC_IPG_IPG_XGMII;
4864                 val |= (IPG_12_15_XGMII << XMAC_IPG_IPG_XGMII_SHIFT);
4865         } else {
4866                 val &= ~XMAC_IPG_IPG_MII_GMII;
4867                 val |= (IPG_12_MII_GMII << XMAC_IPG_IPG_MII_GMII_SHIFT);
4868         }
4869         nw64_mac(XMAC_IPG, val);
4870
4871         val = nr64_mac(XMAC_CONFIG);
4872         val &= ~(XMAC_CONFIG_ALWAYS_NO_CRC |
4873                  XMAC_CONFIG_STRETCH_MODE |
4874                  XMAC_CONFIG_VAR_MIN_IPG_EN |
4875                  XMAC_CONFIG_TX_ENABLE);
4876         nw64_mac(XMAC_CONFIG, val);
4877
4878         nw64_mac(TXMAC_FRM_CNT, 0);
4879         nw64_mac(TXMAC_BYTE_CNT, 0);
4880 }
4881
4882 static void niu_init_tx_bmac(struct niu *np, u64 min, u64 max)
4883 {
4884         u64 val;
4885
4886         nw64_mac(BMAC_MIN_FRAME, min);
4887         nw64_mac(BMAC_MAX_FRAME, max);
4888
4889         nw64_mac(BTXMAC_STATUS_MASK, ~(u64)0);
4890         nw64_mac(BMAC_CTRL_TYPE, 0x8808);
4891         nw64_mac(BMAC_PREAMBLE_SIZE, 7);
4892
4893         val = nr64_mac(BTXMAC_CONFIG);
4894         val &= ~(BTXMAC_CONFIG_FCS_DISABLE |
4895                  BTXMAC_CONFIG_ENABLE);
4896         nw64_mac(BTXMAC_CONFIG, val);
4897 }
4898
4899 static void niu_init_tx_mac(struct niu *np)
4900 {
4901         u64 min, max;
4902
4903         min = 64;
4904         if (np->dev->mtu > ETH_DATA_LEN)
4905                 max = 9216;
4906         else
4907                 max = 1522;
4908
4909         /* The XMAC_MIN register only accepts values for TX min which
4910          * have the low 3 bits cleared.
4911          */
4912         BUILD_BUG_ON(min & 0x7);
4913
4914         if (np->flags & NIU_FLAGS_XMAC)
4915                 niu_init_tx_xmac(np, min, max);
4916         else
4917                 niu_init_tx_bmac(np, min, max);
4918 }
4919
4920 static int niu_reset_rx_xmac(struct niu *np)
4921 {
4922         int limit;
4923
4924         nw64_mac(XRXMAC_SW_RST,
4925                  XRXMAC_SW_RST_REG_RS | XRXMAC_SW_RST_SOFT_RST);
4926         limit = 1000;
4927         while (--limit >= 0) {
4928                 if (!(nr64_mac(XRXMAC_SW_RST) & (XRXMAC_SW_RST_REG_RS |
4929                                                  XRXMAC_SW_RST_SOFT_RST)))
4930                     break;
4931                 udelay(100);
4932         }
4933         if (limit < 0) {
4934                 dev_err(np->device, PFX "Port %u RX XMAC would not reset, "
4935                         "XRXMAC_SW_RST[%llx]\n",
4936                         np->port,
4937                         (unsigned long long) nr64_mac(XRXMAC_SW_RST));
4938                 return -ENODEV;
4939         }
4940
4941         return 0;
4942 }
4943
4944 static int niu_reset_rx_bmac(struct niu *np)
4945 {
4946         int limit;
4947
4948         nw64_mac(BRXMAC_SW_RST, BRXMAC_SW_RST_RESET);
4949         limit = 1000;
4950         while (--limit >= 0) {
4951                 if (!(nr64_mac(BRXMAC_SW_RST) & BRXMAC_SW_RST_RESET))
4952                         break;
4953                 udelay(100);
4954         }
4955         if (limit < 0) {
4956                 dev_err(np->device, PFX "Port %u RX BMAC would not reset, "
4957                         "BRXMAC_SW_RST[%llx]\n",
4958                         np->port,
4959                         (unsigned long long) nr64_mac(BRXMAC_SW_RST));
4960                 return -ENODEV;
4961         }
4962
4963         return 0;
4964 }
4965
4966 static int niu_reset_rx_mac(struct niu *np)
4967 {
4968         if (np->flags & NIU_FLAGS_XMAC)
4969                 return niu_reset_rx_xmac(np);
4970         else
4971                 return niu_reset_rx_bmac(np);
4972 }
4973
4974 static void niu_init_rx_xmac(struct niu *np)
4975 {
4976         struct niu_parent *parent = np->parent;
4977         struct niu_rdc_tables *tp = &parent->rdc_group_cfg[np->port];
4978         int first_rdc_table = tp->first_table_num;
4979         unsigned long i;
4980         u64 val;
4981
4982         nw64_mac(XMAC_ADD_FILT0, 0);
4983         nw64_mac(XMAC_ADD_FILT1, 0);
4984         nw64_mac(XMAC_ADD_FILT2, 0);
4985         nw64_mac(XMAC_ADD_FILT12_MASK, 0);
4986         nw64_mac(XMAC_ADD_FILT00_MASK, 0);
4987         for (i = 0; i < MAC_NUM_HASH; i++)
4988                 nw64_mac(XMAC_HASH_TBL(i), 0);
4989         nw64_mac(XRXMAC_STAT_MSK, ~(u64)0);
4990         niu_set_primary_mac_rdc_table(np, first_rdc_table, 1);
4991         niu_set_multicast_mac_rdc_table(np, first_rdc_table, 1);
4992
4993         val = nr64_mac(XMAC_CONFIG);
4994         val &= ~(XMAC_CONFIG_RX_MAC_ENABLE |
4995                  XMAC_CONFIG_PROMISCUOUS |
4996                  XMAC_CONFIG_PROMISC_GROUP |
4997                  XMAC_CONFIG_ERR_CHK_DIS |
4998                  XMAC_CONFIG_RX_CRC_CHK_DIS |
4999                  XMAC_CONFIG_RESERVED_MULTICAST |
5000                  XMAC_CONFIG_RX_CODEV_CHK_DIS |
5001                  XMAC_CONFIG_ADDR_FILTER_EN |
5002                  XMAC_CONFIG_RCV_PAUSE_ENABLE |
5003                  XMAC_CONFIG_STRIP_CRC |
5004                  XMAC_CONFIG_PASS_FLOW_CTRL |
5005                  XMAC_CONFIG_MAC2IPP_PKT_CNT_EN);
5006         val |= (XMAC_CONFIG_HASH_FILTER_EN);
5007         nw64_mac(XMAC_CONFIG, val);
5008
5009         nw64_mac(RXMAC_BT_CNT, 0);
5010         nw64_mac(RXMAC_BC_FRM_CNT, 0);
5011         nw64_mac(RXMAC_MC_FRM_CNT, 0);
5012         nw64_mac(RXMAC_FRAG_CNT, 0);
5013         nw64_mac(RXMAC_HIST_CNT1, 0);
5014         nw64_mac(RXMAC_HIST_CNT2, 0);
5015         nw64_mac(RXMAC_HIST_CNT3, 0);
5016         nw64_mac(RXMAC_HIST_CNT4, 0);
5017         nw64_mac(RXMAC_HIST_CNT5, 0);
5018         nw64_mac(RXMAC_HIST_CNT6, 0);
5019         nw64_mac(RXMAC_HIST_CNT7, 0);
5020         nw64_mac(RXMAC_MPSZER_CNT, 0);
5021         nw64_mac(RXMAC_CRC_ER_CNT, 0);
5022         nw64_mac(RXMAC_CD_VIO_CNT, 0);
5023         nw64_mac(LINK_FAULT_CNT, 0);
5024 }
5025
5026 static void niu_init_rx_bmac(struct niu *np)
5027 {
5028         struct niu_parent *parent = np->parent;
5029         struct niu_rdc_tables *tp = &parent->rdc_group_cfg[np->port];
5030         int first_rdc_table = tp->first_table_num;
5031         unsigned long i;
5032         u64 val;
5033
5034         nw64_mac(BMAC_ADD_FILT0, 0);
5035         nw64_mac(BMAC_ADD_FILT1, 0);
5036         nw64_mac(BMAC_ADD_FILT2, 0);
5037         nw64_mac(BMAC_ADD_FILT12_MASK, 0);
5038         nw64_mac(BMAC_ADD_FILT00_MASK, 0);
5039         for (i = 0; i < MAC_NUM_HASH; i++)
5040                 nw64_mac(BMAC_HASH_TBL(i), 0);
5041         niu_set_primary_mac_rdc_table(np, first_rdc_table, 1);
5042         niu_set_multicast_mac_rdc_table(np, first_rdc_table, 1);
5043         nw64_mac(BRXMAC_STATUS_MASK, ~(u64)0);
5044
5045         val = nr64_mac(BRXMAC_CONFIG);
5046         val &= ~(BRXMAC_CONFIG_ENABLE |
5047                  BRXMAC_CONFIG_STRIP_PAD |
5048                  BRXMAC_CONFIG_STRIP_FCS |
5049                  BRXMAC_CONFIG_PROMISC |
5050                  BRXMAC_CONFIG_PROMISC_GRP |
5051                  BRXMAC_CONFIG_ADDR_FILT_EN |
5052                  BRXMAC_CONFIG_DISCARD_DIS);
5053         val |= (BRXMAC_CONFIG_HASH_FILT_EN);
5054         nw64_mac(BRXMAC_CONFIG, val);
5055
5056         val = nr64_mac(BMAC_ADDR_CMPEN);
5057         val |= BMAC_ADDR_CMPEN_EN0;
5058         nw64_mac(BMAC_ADDR_CMPEN, val);
5059 }
5060
5061 static void niu_init_rx_mac(struct niu *np)
5062 {
5063         niu_set_primary_mac(np, np->dev->dev_addr);
5064
5065         if (np->flags & NIU_FLAGS_XMAC)
5066                 niu_init_rx_xmac(np);
5067         else
5068                 niu_init_rx_bmac(np);
5069 }
5070
5071 static void niu_enable_tx_xmac(struct niu *np, int on)
5072 {
5073         u64 val = nr64_mac(XMAC_CONFIG);
5074
5075         if (on)
5076                 val |= XMAC_CONFIG_TX_ENABLE;
5077         else
5078                 val &= ~XMAC_CONFIG_TX_ENABLE;
5079         nw64_mac(XMAC_CONFIG, val);
5080 }
5081
5082 static void niu_enable_tx_bmac(struct niu *np, int on)
5083 {
5084         u64 val = nr64_mac(BTXMAC_CONFIG);
5085
5086         if (on)
5087                 val |= BTXMAC_CONFIG_ENABLE;
5088         else
5089                 val &= ~BTXMAC_CONFIG_ENABLE;
5090         nw64_mac(BTXMAC_CONFIG, val);
5091 }
5092
5093 static void niu_enable_tx_mac(struct niu *np, int on)
5094 {
5095         if (np->flags & NIU_FLAGS_XMAC)
5096                 niu_enable_tx_xmac(np, on);
5097         else
5098                 niu_enable_tx_bmac(np, on);
5099 }
5100
5101 static void niu_enable_rx_xmac(struct niu *np, int on)
5102 {
5103         u64 val = nr64_mac(XMAC_CONFIG);
5104
5105         val &= ~(XMAC_CONFIG_HASH_FILTER_EN |
5106                  XMAC_CONFIG_PROMISCUOUS);
5107
5108         if (np->flags & NIU_FLAGS_MCAST)
5109                 val |= XMAC_CONFIG_HASH_FILTER_EN;
5110         if (np->flags & NIU_FLAGS_PROMISC)
5111                 val |= XMAC_CONFIG_PROMISCUOUS;
5112
5113         if (on)
5114                 val |= XMAC_CONFIG_RX_MAC_ENABLE;
5115         else
5116                 val &= ~XMAC_CONFIG_RX_MAC_ENABLE;
5117         nw64_mac(XMAC_CONFIG, val);
5118 }
5119
5120 static void niu_enable_rx_bmac(struct niu *np, int on)
5121 {
5122         u64 val = nr64_mac(BRXMAC_CONFIG);
5123
5124         val &= ~(BRXMAC_CONFIG_HASH_FILT_EN |
5125                  BRXMAC_CONFIG_PROMISC);
5126
5127         if (np->flags & NIU_FLAGS_MCAST)
5128                 val |= BRXMAC_CONFIG_HASH_FILT_EN;
5129         if (np->flags & NIU_FLAGS_PROMISC)
5130                 val |= BRXMAC_CONFIG_PROMISC;
5131
5132         if (on)
5133                 val |= BRXMAC_CONFIG_ENABLE;
5134         else
5135                 val &= ~BRXMAC_CONFIG_ENABLE;
5136         nw64_mac(BRXMAC_CONFIG, val);
5137 }
5138
5139 static void niu_enable_rx_mac(struct niu *np, int on)
5140 {
5141         if (np->flags & NIU_FLAGS_XMAC)
5142                 niu_enable_rx_xmac(np, on);
5143         else
5144                 niu_enable_rx_bmac(np, on);
5145 }
5146
5147 static int niu_init_mac(struct niu *np)
5148 {
5149         int err;
5150
5151         niu_init_xif(np);
5152         err = niu_init_pcs(np);
5153         if (err)
5154                 return err;
5155
5156         err = niu_reset_tx_mac(np);
5157         if (err)
5158                 return err;
5159         niu_init_tx_mac(np);
5160         err = niu_reset_rx_mac(np);
5161         if (err)
5162                 return err;
5163         niu_init_rx_mac(np);
5164
5165         /* This looks hookey but the RX MAC reset we just did will
5166          * undo some of the state we setup in niu_init_tx_mac() so we
5167          * have to call it again.  In particular, the RX MAC reset will
5168          * set the XMAC_MAX register back to it's default value.
5169          */
5170         niu_init_tx_mac(np);
5171         niu_enable_tx_mac(np, 1);
5172
5173         niu_enable_rx_mac(np, 1);
5174
5175         return 0;
5176 }
5177
5178 static void niu_stop_one_tx_channel(struct niu *np, struct tx_ring_info *rp)
5179 {
5180         (void) niu_tx_channel_stop(np, rp->tx_channel);
5181 }
5182
5183 static void niu_stop_tx_channels(struct niu *np)
5184 {
5185         int i;
5186
5187         for (i = 0; i < np->num_tx_rings; i++) {
5188                 struct tx_ring_info *rp = &np->tx_rings[i];
5189
5190                 niu_stop_one_tx_channel(np, rp);
5191         }
5192 }
5193
5194 static void niu_reset_one_tx_channel(struct niu *np, struct tx_ring_info *rp)
5195 {
5196         (void) niu_tx_channel_reset(np, rp->tx_channel);
5197 }
5198
5199 static void niu_reset_tx_channels(struct niu *np)
5200 {
5201         int i;
5202
5203         for (i = 0; i < np->num_tx_rings; i++) {
5204                 struct tx_ring_info *rp = &np->tx_rings[i];
5205
5206                 niu_reset_one_tx_channel(np, rp);
5207         }
5208 }
5209
5210 static void niu_stop_one_rx_channel(struct niu *np, struct rx_ring_info *rp)
5211 {
5212         (void) niu_enable_rx_channel(np, rp->rx_channel, 0);
5213 }
5214
5215 static void niu_stop_rx_channels(struct niu *np)
5216 {
5217         int i;
5218
5219         for (i = 0; i < np->num_rx_rings; i++) {
5220                 struct rx_ring_info *rp = &np->rx_rings[i];
5221
5222                 niu_stop_one_rx_channel(np, rp);
5223         }
5224 }
5225
5226 static void niu_reset_one_rx_channel(struct niu *np, struct rx_ring_info *rp)
5227 {
5228         int channel = rp->rx_channel;
5229
5230         (void) niu_rx_channel_reset(np, channel);
5231         nw64(RX_DMA_ENT_MSK(channel), RX_DMA_ENT_MSK_ALL);
5232         nw64(RX_DMA_CTL_STAT(channel), 0);
5233         (void) niu_enable_rx_channel(np, channel, 0);
5234 }
5235
5236 static void niu_reset_rx_channels(struct niu *np)
5237 {
5238         int i;
5239
5240         for (i = 0; i < np->num_rx_rings; i++) {
5241                 struct rx_ring_info *rp = &np->rx_rings[i];
5242
5243                 niu_reset_one_rx_channel(np, rp);
5244         }
5245 }
5246
5247 static void niu_disable_ipp(struct niu *np)
5248 {
5249         u64 rd, wr, val;
5250         int limit;
5251
5252         rd = nr64_ipp(IPP_DFIFO_RD_PTR);
5253         wr = nr64_ipp(IPP_DFIFO_WR_PTR);
5254         limit = 100;
5255         while (--limit >= 0 && (rd != wr)) {
5256                 rd = nr64_ipp(IPP_DFIFO_RD_PTR);
5257                 wr = nr64_ipp(IPP_DFIFO_WR_PTR);
5258         }
5259         if (limit < 0 &&
5260             (rd != 0 && wr != 1)) {
5261                 dev_err(np->device, PFX "%s: IPP would not quiesce, "
5262                         "rd_ptr[%llx] wr_ptr[%llx]\n",
5263                         np->dev->name,
5264                         (unsigned long long) nr64_ipp(IPP_DFIFO_RD_PTR),
5265                         (unsigned long long) nr64_ipp(IPP_DFIFO_WR_PTR));
5266         }
5267
5268         val = nr64_ipp(IPP_CFIG);
5269         val &= ~(IPP_CFIG_IPP_ENABLE |
5270                  IPP_CFIG_DFIFO_ECC_EN |
5271                  IPP_CFIG_DROP_BAD_CRC |
5272                  IPP_CFIG_CKSUM_EN);
5273         nw64_ipp(IPP_CFIG, val);
5274
5275         (void) niu_ipp_reset(np);
5276 }
5277
5278 static int niu_init_hw(struct niu *np)
5279 {
5280         int i, err;
5281
5282         niudbg(IFUP, "%s: Initialize TXC\n", np->dev->name);
5283         niu_txc_enable_port(np, 1);
5284         niu_txc_port_dma_enable(np, 1);
5285         niu_txc_set_imask(np, 0);
5286
5287         niudbg(IFUP, "%s: Initialize TX channels\n", np->dev->name);
5288         for (i = 0; i < np->num_tx_rings; i++) {
5289                 struct tx_ring_info *rp = &np->tx_rings[i];
5290
5291                 err = niu_init_one_tx_channel(np, rp);
5292                 if (err)
5293                         return err;
5294         }
5295
5296         niudbg(IFUP, "%s: Initialize RX channels\n", np->dev->name);
5297         err = niu_init_rx_channels(np);
5298         if (err)
5299                 goto out_uninit_tx_channels;
5300
5301         niudbg(IFUP, "%s: Initialize classifier\n", np->dev->name);
5302         err = niu_init_classifier_hw(np);
5303         if (err)
5304                 goto out_uninit_rx_channels;
5305
5306         niudbg(IFUP, "%s: Initialize ZCP\n", np->dev->name);
5307         err = niu_init_zcp(np);
5308         if (err)
5309                 goto out_uninit_rx_channels;
5310
5311         niudbg(IFUP, "%s: Initialize IPP\n", np->dev->name);
5312         err = niu_init_ipp(np);
5313         if (err)
5314                 goto out_uninit_rx_channels;
5315
5316         niudbg(IFUP, "%s: Initialize MAC\n", np->dev->name);
5317         err = niu_init_mac(np);
5318         if (err)
5319                 goto out_uninit_ipp;
5320
5321         return 0;
5322
5323 out_uninit_ipp:
5324         niudbg(IFUP, "%s: Uninit IPP\n", np->dev->name);
5325         niu_disable_ipp(np);
5326
5327 out_uninit_rx_channels:
5328         niudbg(IFUP, "%s: Uninit RX channels\n", np->dev->name);
5329         niu_stop_rx_channels(np);
5330         niu_reset_rx_channels(np);
5331
5332 out_uninit_tx_channels:
5333         niudbg(IFUP, "%s: Uninit TX channels\n", np->dev->name);
5334         niu_stop_tx_channels(np);
5335         niu_reset_tx_channels(np);
5336
5337         return err;
5338 }
5339
5340 static void niu_stop_hw(struct niu *np)
5341 {
5342         niudbg(IFDOWN, "%s: Disable interrupts\n", np->dev->name);
5343         niu_enable_interrupts(np, 0);
5344
5345         niudbg(IFDOWN, "%s: Disable RX MAC\n", np->dev->name);
5346         niu_enable_rx_mac(np, 0);
5347
5348         niudbg(IFDOWN, "%s: Disable IPP\n", np->dev->name);
5349         niu_disable_ipp(np);
5350
5351         niudbg(IFDOWN, "%s: Stop TX channels\n", np->dev->name);
5352         niu_stop_tx_channels(np);
5353
5354         niudbg(IFDOWN, "%s: Stop RX channels\n", np->dev->name);
5355         niu_stop_rx_channels(np);
5356
5357         niudbg(IFDOWN, "%s: Reset TX channels\n", np->dev->name);
5358         niu_reset_tx_channels(np);
5359
5360         niudbg(IFDOWN, "%s: Reset RX channels\n", np->dev->name);
5361         niu_reset_rx_channels(np);
5362 }
5363
5364 static int niu_request_irq(struct niu *np)
5365 {
5366         int i, j, err;
5367
5368         err = 0;
5369         for (i = 0; i < np->num_ldg; i++) {
5370                 struct niu_ldg *lp = &np->ldg[i];
5371
5372                 err = request_irq(lp->irq, niu_interrupt,
5373                                   IRQF_SHARED | IRQF_SAMPLE_RANDOM,
5374                                   np->dev->name, lp);
5375                 if (err)
5376                         goto out_free_irqs;
5377
5378         }
5379
5380         return 0;
5381
5382 out_free_irqs:
5383         for (j = 0; j < i; j++) {
5384                 struct niu_ldg *lp = &np->ldg[j];
5385
5386                 free_irq(lp->irq, lp);
5387         }
5388         return err;
5389 }
5390
5391 static void niu_free_irq(struct niu *np)
5392 {
5393         int i;
5394
5395         for (i = 0; i < np->num_ldg; i++) {
5396                 struct niu_ldg *lp = &np->ldg[i];
5397
5398                 free_irq(lp->irq, lp);
5399         }
5400 }
5401
5402 static void niu_enable_napi(struct niu *np)
5403 {
5404         int i;
5405
5406         for (i = 0; i < np->num_ldg; i++)
5407                 napi_enable(&np->ldg[i].napi);
5408 }
5409
5410 static void niu_disable_napi(struct niu *np)
5411 {
5412         int i;
5413
5414         for (i = 0; i < np->num_ldg; i++)
5415                 napi_disable(&np->ldg[i].napi);
5416 }
5417
5418 static int niu_open(struct net_device *dev)
5419 {
5420         struct niu *np = netdev_priv(dev);
5421         int err;
5422
5423         netif_carrier_off(dev);
5424
5425         err = niu_alloc_channels(np);
5426         if (err)
5427                 goto out_err;
5428
5429         err = niu_enable_interrupts(np, 0);
5430         if (err)
5431                 goto out_free_channels;
5432
5433         err = niu_request_irq(np);
5434         if (err)
5435                 goto out_free_channels;
5436
5437         niu_enable_napi(np);
5438
5439         spin_lock_irq(&np->lock);
5440
5441         err = niu_init_hw(np);
5442         if (!err) {
5443                 init_timer(&np->timer);
5444                 np->timer.expires = jiffies + HZ;
5445                 np->timer.data = (unsigned long) np;
5446                 np->timer.function = niu_timer;
5447
5448                 err = niu_enable_interrupts(np, 1);
5449                 if (err)
5450                         niu_stop_hw(np);
5451         }
5452
5453         spin_unlock_irq(&np->lock);
5454
5455         if (err) {
5456                 niu_disable_napi(np);
5457                 goto out_free_irq;
5458         }
5459
5460         netif_start_queue(dev);
5461
5462         if (np->link_config.loopback_mode != LOOPBACK_DISABLED)
5463                 netif_carrier_on(dev);
5464
5465         add_timer(&np->timer);
5466
5467         return 0;
5468
5469 out_free_irq:
5470         niu_free_irq(np);
5471
5472 out_free_channels:
5473         niu_free_channels(np);
5474
5475 out_err:
5476         return err;
5477 }
5478
5479 static void niu_full_shutdown(struct niu *np, struct net_device *dev)
5480 {
5481         cancel_work_sync(&np->reset_task);
5482
5483         niu_disable_napi(np);
5484         netif_stop_queue(dev);
5485
5486         del_timer_sync(&np->timer);
5487
5488         spin_lock_irq(&np->lock);
5489
5490         niu_stop_hw(np);
5491
5492         spin_unlock_irq(&np->lock);
5493 }
5494
5495 static int niu_close(struct net_device *dev)
5496 {
5497         struct niu *np = netdev_priv(dev);
5498
5499         niu_full_shutdown(np, dev);
5500
5501         niu_free_irq(np);
5502
5503         niu_free_channels(np);
5504
5505         niu_handle_led(np, 0);
5506
5507         return 0;
5508 }
5509
5510 static void niu_sync_xmac_stats(struct niu *np)
5511 {
5512         struct niu_xmac_stats *mp = &np->mac_stats.xmac;
5513
5514         mp->tx_frames += nr64_mac(TXMAC_FRM_CNT);
5515         mp->tx_bytes += nr64_mac(TXMAC_BYTE_CNT);
5516
5517         mp->rx_link_faults += nr64_mac(LINK_FAULT_CNT);
5518         mp->rx_align_errors += nr64_mac(RXMAC_ALIGN_ERR_CNT);
5519         mp->rx_frags += nr64_mac(RXMAC_FRAG_CNT);
5520         mp->rx_mcasts += nr64_mac(RXMAC_MC_FRM_CNT);
5521         mp->rx_bcasts += nr64_mac(RXMAC_BC_FRM_CNT);
5522         mp->rx_hist_cnt1 += nr64_mac(RXMAC_HIST_CNT1);
5523         mp->rx_hist_cnt2 += nr64_mac(RXMAC_HIST_CNT2);
5524         mp->rx_hist_cnt3 += nr64_mac(RXMAC_HIST_CNT3);
5525         mp->rx_hist_cnt4 += nr64_mac(RXMAC_HIST_CNT4);
5526         mp->rx_hist_cnt5 += nr64_mac(RXMAC_HIST_CNT5);
5527         mp->rx_hist_cnt6 += nr64_mac(RXMAC_HIST_CNT6);
5528         mp->rx_hist_cnt7 += nr64_mac(RXMAC_HIST_CNT7);
5529         mp->rx_octets += nr64_mac(RXMAC_BT_CNT);
5530         mp->rx_code_violations += nr64_mac(RXMAC_CD_VIO_CNT);
5531         mp->rx_len_errors += nr64_mac(RXMAC_MPSZER_CNT);
5532         mp->rx_crc_errors += nr64_mac(RXMAC_CRC_ER_CNT);
5533 }
5534
5535 static void niu_sync_bmac_stats(struct niu *np)
5536 {
5537         struct niu_bmac_stats *mp = &np->mac_stats.bmac;
5538
5539         mp->tx_bytes += nr64_mac(BTXMAC_BYTE_CNT);
5540         mp->tx_frames += nr64_mac(BTXMAC_FRM_CNT);
5541
5542         mp->rx_frames += nr64_mac(BRXMAC_FRAME_CNT);
5543         mp->rx_align_errors += nr64_mac(BRXMAC_ALIGN_ERR_CNT);
5544         mp->rx_crc_errors += nr64_mac(BRXMAC_ALIGN_ERR_CNT);
5545         mp->rx_len_errors += nr64_mac(BRXMAC_CODE_VIOL_ERR_CNT);
5546 }
5547
5548 static void niu_sync_mac_stats(struct niu *np)
5549 {
5550         if (np->flags & NIU_FLAGS_XMAC)
5551                 niu_sync_xmac_stats(np);
5552         else
5553                 niu_sync_bmac_stats(np);
5554 }
5555
5556 static void niu_get_rx_stats(struct niu *np)
5557 {
5558         unsigned long pkts, dropped, errors, bytes;
5559         int i;
5560
5561         pkts = dropped = errors = bytes = 0;
5562         for (i = 0; i < np->num_rx_rings; i++) {
5563                 struct rx_ring_info *rp = &np->rx_rings[i];
5564
5565                 pkts += rp->rx_packets;
5566                 bytes += rp->rx_bytes;
5567                 dropped += rp->rx_dropped;
5568                 errors += rp->rx_errors;
5569         }
5570         np->net_stats.rx_packets = pkts;
5571         np->net_stats.rx_bytes = bytes;
5572         np->net_stats.rx_dropped = dropped;
5573         np->net_stats.rx_errors = errors;
5574 }
5575
5576 static void niu_get_tx_stats(struct niu *np)
5577 {
5578         unsigned long pkts, errors, bytes;
5579         int i;
5580
5581         pkts = errors = bytes = 0;
5582         for (i = 0; i < np->num_tx_rings; i++) {
5583                 struct tx_ring_info *rp = &np->tx_rings[i];
5584
5585                 pkts += rp->tx_packets;
5586                 bytes += rp->tx_bytes;
5587                 errors += rp->tx_errors;
5588         }
5589         np->net_stats.tx_packets = pkts;
5590         np->net_stats.tx_bytes = bytes;
5591         np->net_stats.tx_errors = errors;
5592 }
5593
5594 static struct net_device_stats *niu_get_stats(struct net_device *dev)
5595 {
5596         struct niu *np = netdev_priv(dev);
5597
5598         niu_get_rx_stats(np);
5599         niu_get_tx_stats(np);
5600
5601         return &np->net_stats;
5602 }
5603
5604 static void niu_load_hash_xmac(struct niu *np, u16 *hash)
5605 {
5606         int i;
5607
5608         for (i = 0; i < 16; i++)
5609                 nw64_mac(XMAC_HASH_TBL(i), hash[i]);
5610 }
5611
5612 static void niu_load_hash_bmac(struct niu *np, u16 *hash)
5613 {
5614         int i;
5615
5616         for (i = 0; i < 16; i++)
5617                 nw64_mac(BMAC_HASH_TBL(i), hash[i]);
5618 }
5619
5620 static void niu_load_hash(struct niu *np, u16 *hash)
5621 {
5622         if (np->flags & NIU_FLAGS_XMAC)
5623                 niu_load_hash_xmac(np, hash);
5624         else
5625                 niu_load_hash_bmac(np, hash);
5626 }
5627
5628 static void niu_set_rx_mode(struct net_device *dev)
5629 {
5630         struct niu *np = netdev_priv(dev);
5631         int i, alt_cnt, err;
5632         struct dev_addr_list *addr;
5633         unsigned long flags;
5634         u16 hash[16] = { 0, };
5635
5636         spin_lock_irqsave(&np->lock, flags);
5637         niu_enable_rx_mac(np, 0);
5638
5639         np->flags &= ~(NIU_FLAGS_MCAST | NIU_FLAGS_PROMISC);
5640         if (dev->flags & IFF_PROMISC)
5641                 np->flags |= NIU_FLAGS_PROMISC;
5642         if ((dev->flags & IFF_ALLMULTI) || (dev->mc_count > 0))
5643                 np->flags |= NIU_FLAGS_MCAST;
5644
5645         alt_cnt = dev->uc_count;
5646         if (alt_cnt > niu_num_alt_addr(np)) {
5647                 alt_cnt = 0;
5648                 np->flags |= NIU_FLAGS_PROMISC;
5649         }
5650
5651         if (alt_cnt) {
5652                 int index = 0;
5653
5654                 for (addr = dev->uc_list; addr; addr = addr->next) {
5655                         err = niu_set_alt_mac(np, index,
5656                                               addr->da_addr);
5657                         if (err)
5658                                 printk(KERN_WARNING PFX "%s: Error %d "
5659                                        "adding alt mac %d\n",
5660                                        dev->name, err, index);
5661                         err = niu_enable_alt_mac(np, index, 1);
5662                         if (err)
5663                                 printk(KERN_WARNING PFX "%s: Error %d "
5664                                        "enabling alt mac %d\n",
5665                                        dev->name, err, index);
5666
5667                         index++;
5668                 }
5669         } else {
5670                 int alt_start;
5671                 if (np->flags & NIU_FLAGS_XMAC)
5672                         alt_start = 0;
5673                 else
5674                         alt_start = 1;
5675                 for (i = alt_start; i < niu_num_alt_addr(np); i++) {
5676                         err = niu_enable_alt_mac(np, i, 0);
5677                         if (err)
5678                                 printk(KERN_WARNING PFX "%s: Error %d "
5679                                        "disabling alt mac %d\n",
5680                                        dev->name, err, i);
5681                 }
5682         }
5683         if (dev->flags & IFF_ALLMULTI) {
5684                 for (i = 0; i < 16; i++)
5685                         hash[i] = 0xffff;
5686         } else if (dev->mc_count > 0) {
5687                 for (addr = dev->mc_list; addr; addr = addr->next) {
5688                         u32 crc = ether_crc_le(ETH_ALEN, addr->da_addr);
5689
5690                         crc >>= 24;
5691                         hash[crc >> 4] |= (1 << (15 - (crc & 0xf)));
5692                 }
5693         }
5694
5695         if (np->flags & NIU_FLAGS_MCAST)
5696                 niu_load_hash(np, hash);
5697
5698         niu_enable_rx_mac(np, 1);
5699         spin_unlock_irqrestore(&np->lock, flags);
5700 }
5701
5702 static int niu_set_mac_addr(struct net_device *dev, void *p)
5703 {
5704         struct niu *np = netdev_priv(dev);
5705         struct sockaddr *addr = p;
5706         unsigned long flags;
5707
5708         if (!is_valid_ether_addr(addr->sa_data))
5709                 return -EINVAL;
5710
5711         memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
5712
5713         if (!netif_running(dev))
5714                 return 0;
5715
5716         spin_lock_irqsave(&np->lock, flags);
5717         niu_enable_rx_mac(np, 0);
5718         niu_set_primary_mac(np, dev->dev_addr);
5719         niu_enable_rx_mac(np, 1);
5720         spin_unlock_irqrestore(&np->lock, flags);
5721
5722         return 0;
5723 }
5724
5725 static int niu_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
5726 {
5727         return -EOPNOTSUPP;
5728 }
5729
5730 static void niu_netif_stop(struct niu *np)
5731 {
5732         np->dev->trans_start = jiffies; /* prevent tx timeout */
5733
5734         niu_disable_napi(np);
5735
5736         netif_tx_disable(np->dev);
5737 }
5738
5739 static void niu_netif_start(struct niu *np)
5740 {
5741         /* NOTE: unconditional netif_wake_queue is only appropriate
5742          * so long as all callers are assured to have free tx slots
5743          * (such as after niu_init_hw).
5744          */
5745         netif_wake_queue(np->dev);
5746
5747         niu_enable_napi(np);
5748
5749         niu_enable_interrupts(np, 1);
5750 }
5751
5752 static void niu_reset_task(struct work_struct *work)
5753 {
5754         struct niu *np = container_of(work, struct niu, reset_task);
5755         unsigned long flags;
5756         int err;
5757
5758         spin_lock_irqsave(&np->lock, flags);
5759         if (!netif_running(np->dev)) {
5760                 spin_unlock_irqrestore(&np->lock, flags);
5761                 return;
5762         }
5763
5764         spin_unlock_irqrestore(&np->lock, flags);
5765
5766         del_timer_sync(&np->timer);
5767
5768         niu_netif_stop(np);
5769
5770         spin_lock_irqsave(&np->lock, flags);
5771
5772         niu_stop_hw(np);
5773
5774         err = niu_init_hw(np);
5775         if (!err) {
5776                 np->timer.expires = jiffies + HZ;
5777                 add_timer(&np->timer);
5778                 niu_netif_start(np);
5779         }
5780
5781         spin_unlock_irqrestore(&np->lock, flags);
5782 }
5783
5784 static void niu_tx_timeout(struct net_device *dev)
5785 {
5786         struct niu *np = netdev_priv(dev);
5787
5788         dev_err(np->device, PFX "%s: Transmit timed out, resetting\n",
5789                 dev->name);
5790
5791         schedule_work(&np->reset_task);
5792 }
5793
5794 static void niu_set_txd(struct tx_ring_info *rp, int index,
5795                         u64 mapping, u64 len, u64 mark,
5796                         u64 n_frags)
5797 {
5798         __le64 *desc = &rp->descr[index];
5799
5800         *desc = cpu_to_le64(mark |
5801                             (n_frags << TX_DESC_NUM_PTR_SHIFT) |
5802                             (len << TX_DESC_TR_LEN_SHIFT) |
5803                             (mapping & TX_DESC_SAD));
5804 }
5805
5806 static u64 niu_compute_tx_flags(struct sk_buff *skb, struct ethhdr *ehdr,
5807                                 u64 pad_bytes, u64 len)
5808 {
5809         u16 eth_proto, eth_proto_inner;
5810         u64 csum_bits, l3off, ihl, ret;
5811         u8 ip_proto;
5812         int ipv6;
5813
5814         eth_proto = be16_to_cpu(ehdr->h_proto);
5815         eth_proto_inner = eth_proto;
5816         if (eth_proto == ETH_P_8021Q) {
5817                 struct vlan_ethhdr *vp = (struct vlan_ethhdr *) ehdr;
5818                 __be16 val = vp->h_vlan_encapsulated_proto;
5819
5820                 eth_proto_inner = be16_to_cpu(val);
5821         }
5822
5823         ipv6 = ihl = 0;
5824         switch (skb->protocol) {
5825         case __constant_htons(ETH_P_IP):
5826                 ip_proto = ip_hdr(skb)->protocol;
5827                 ihl = ip_hdr(skb)->ihl;
5828                 break;
5829         case __constant_htons(ETH_P_IPV6):
5830                 ip_proto = ipv6_hdr(skb)->nexthdr;
5831                 ihl = (40 >> 2);
5832                 ipv6 = 1;
5833                 break;
5834         default:
5835                 ip_proto = ihl = 0;
5836                 break;
5837         }
5838
5839         csum_bits = TXHDR_CSUM_NONE;
5840         if (skb->ip_summed == CHECKSUM_PARTIAL) {
5841                 u64 start, stuff;
5842
5843                 csum_bits = (ip_proto == IPPROTO_TCP ?
5844                              TXHDR_CSUM_TCP :
5845                              (ip_proto == IPPROTO_UDP ?
5846                               TXHDR_CSUM_UDP : TXHDR_CSUM_SCTP));
5847
5848                 start = skb_transport_offset(skb) -
5849                         (pad_bytes + sizeof(struct tx_pkt_hdr));
5850                 stuff = start + skb->csum_offset;
5851
5852                 csum_bits |= (start / 2) << TXHDR_L4START_SHIFT;
5853                 csum_bits |= (stuff / 2) << TXHDR_L4STUFF_SHIFT;
5854         }
5855
5856         l3off = skb_network_offset(skb) -
5857                 (pad_bytes + sizeof(struct tx_pkt_hdr));
5858
5859         ret = (((pad_bytes / 2) << TXHDR_PAD_SHIFT) |
5860                (len << TXHDR_LEN_SHIFT) |
5861                ((l3off / 2) << TXHDR_L3START_SHIFT) |
5862                (ihl << TXHDR_IHL_SHIFT) |
5863                ((eth_proto_inner < 1536) ? TXHDR_LLC : 0) |
5864                ((eth_proto == ETH_P_8021Q) ? TXHDR_VLAN : 0) |
5865                (ipv6 ? TXHDR_IP_VER : 0) |
5866                csum_bits);
5867
5868         return ret;
5869 }
5870
5871 static struct tx_ring_info *tx_ring_select(struct niu *np, struct sk_buff *skb)
5872 {
5873         return &np->tx_rings[0];
5874 }
5875
5876 static int niu_start_xmit(struct sk_buff *skb, struct net_device *dev)
5877 {
5878         struct niu *np = netdev_priv(dev);
5879         unsigned long align, headroom;
5880         struct tx_ring_info *rp;
5881         struct tx_pkt_hdr *tp;
5882         unsigned int len, nfg;
5883         struct ethhdr *ehdr;
5884         int prod, i, tlen;
5885         u64 mapping, mrk;
5886
5887         rp = tx_ring_select(np, skb);
5888
5889         if (niu_tx_avail(rp) <= (skb_shinfo(skb)->nr_frags + 1)) {
5890                 netif_stop_queue(dev);
5891                 dev_err(np->device, PFX "%s: BUG! Tx ring full when "
5892                         "queue awake!\n", dev->name);
5893                 rp->tx_errors++;
5894                 return NETDEV_TX_BUSY;
5895         }
5896
5897         if (skb->len < ETH_ZLEN) {
5898                 unsigned int pad_bytes = ETH_ZLEN - skb->len;
5899
5900                 if (skb_pad(skb, pad_bytes))
5901                         goto out;
5902                 skb_put(skb, pad_bytes);
5903         }
5904
5905         len = sizeof(struct tx_pkt_hdr) + 15;
5906         if (skb_headroom(skb) < len) {
5907                 struct sk_buff *skb_new;
5908
5909                 skb_new = skb_realloc_headroom(skb, len);
5910                 if (!skb_new) {
5911                         rp->tx_errors++;
5912                         goto out_drop;
5913                 }
5914                 kfree_skb(skb);
5915                 skb = skb_new;
5916         } else
5917                 skb_orphan(skb);
5918
5919         align = ((unsigned long) skb->data & (16 - 1));
5920         headroom = align + sizeof(struct tx_pkt_hdr);
5921
5922         ehdr = (struct ethhdr *) skb->data;
5923         tp = (struct tx_pkt_hdr *) skb_push(skb, headroom);
5924
5925         len = skb->len - sizeof(struct tx_pkt_hdr);
5926         tp->flags = cpu_to_le64(niu_compute_tx_flags(skb, ehdr, align, len));
5927         tp->resv = 0;
5928
5929         len = skb_headlen(skb);
5930         mapping = np->ops->map_single(np->device, skb->data,
5931                                       len, DMA_TO_DEVICE);
5932
5933         prod = rp->prod;
5934
5935         rp->tx_buffs[prod].skb = skb;
5936         rp->tx_buffs[prod].mapping = mapping;
5937
5938         mrk = TX_DESC_SOP;
5939         if (++rp->mark_counter == rp->mark_freq) {
5940                 rp->mark_counter = 0;
5941                 mrk |= TX_DESC_MARK;
5942                 rp->mark_pending++;
5943         }
5944
5945         tlen = len;
5946         nfg = skb_shinfo(skb)->nr_frags;
5947         while (tlen > 0) {
5948                 tlen -= MAX_TX_DESC_LEN;
5949                 nfg++;
5950         }
5951
5952         while (len > 0) {
5953                 unsigned int this_len = len;
5954
5955                 if (this_len > MAX_TX_DESC_LEN)
5956                         this_len = MAX_TX_DESC_LEN;
5957
5958                 niu_set_txd(rp, prod, mapping, this_len, mrk, nfg);
5959                 mrk = nfg = 0;
5960
5961                 prod = NEXT_TX(rp, prod);
5962                 mapping += this_len;
5963                 len -= this_len;
5964         }
5965
5966         for (i = 0; i <  skb_shinfo(skb)->nr_frags; i++) {
5967                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5968
5969                 len = frag->size;
5970                 mapping = np->ops->map_page(np->device, frag->page,
5971                                             frag->page_offset, len,
5972                                             DMA_TO_DEVICE);
5973
5974                 rp->tx_buffs[prod].skb = NULL;
5975                 rp->tx_buffs[prod].mapping = mapping;
5976
5977                 niu_set_txd(rp, prod, mapping, len, 0, 0);
5978
5979                 prod = NEXT_TX(rp, prod);
5980         }
5981
5982         if (prod < rp->prod)
5983                 rp->wrap_bit ^= TX_RING_KICK_WRAP;
5984         rp->prod = prod;
5985
5986         nw64(TX_RING_KICK(rp->tx_channel), rp->wrap_bit | (prod << 3));
5987
5988         if (unlikely(niu_tx_avail(rp) <= (MAX_SKB_FRAGS + 1))) {
5989                 netif_stop_queue(dev);
5990                 if (niu_tx_avail(rp) > NIU_TX_WAKEUP_THRESH(rp))
5991                         netif_wake_queue(dev);
5992         }
5993
5994         dev->trans_start = jiffies;
5995
5996 out:
5997         return NETDEV_TX_OK;
5998
5999 out_drop:
6000         rp->tx_errors++;
6001         kfree_skb(skb);
6002         goto out;
6003 }
6004
6005 static int niu_change_mtu(struct net_device *dev, int new_mtu)
6006 {
6007         struct niu *np = netdev_priv(dev);
6008         int err, orig_jumbo, new_jumbo;
6009
6010         if (new_mtu < 68 || new_mtu > NIU_MAX_MTU)
6011                 return -EINVAL;
6012
6013         orig_jumbo = (dev->mtu > ETH_DATA_LEN);
6014         new_jumbo = (new_mtu > ETH_DATA_LEN);
6015
6016         dev->mtu = new_mtu;
6017
6018         if (!netif_running(dev) ||
6019             (orig_jumbo == new_jumbo))
6020                 return 0;
6021
6022         niu_full_shutdown(np, dev);
6023
6024         niu_free_channels(np);
6025
6026         niu_enable_napi(np);
6027
6028         err = niu_alloc_channels(np);
6029         if (err)
6030                 return err;
6031
6032         spin_lock_irq(&np->lock);
6033
6034         err = niu_init_hw(np);
6035         if (!err) {
6036                 init_timer(&np->timer);
6037                 np->timer.expires = jiffies + HZ;
6038                 np->timer.data = (unsigned long) np;
6039                 np->timer.function = niu_timer;
6040
6041                 err = niu_enable_interrupts(np, 1);
6042                 if (err)
6043                         niu_stop_hw(np);
6044         }
6045
6046         spin_unlock_irq(&np->lock);
6047
6048         if (!err) {
6049                 netif_start_queue(dev);
6050                 if (np->link_config.loopback_mode != LOOPBACK_DISABLED)
6051                         netif_carrier_on(dev);
6052
6053                 add_timer(&np->timer);
6054         }
6055
6056         return err;
6057 }
6058
6059 static void niu_get_drvinfo(struct net_device *dev,
6060                             struct ethtool_drvinfo *info)
6061 {
6062         struct niu *np = netdev_priv(dev);
6063         struct niu_vpd *vpd = &np->vpd;
6064
6065         strcpy(info->driver, DRV_MODULE_NAME);
6066         strcpy(info->version, DRV_MODULE_VERSION);
6067         sprintf(info->fw_version, "%d.%d",
6068                 vpd->fcode_major, vpd->fcode_minor);
6069         if (np->parent->plat_type != PLAT_TYPE_NIU)
6070                 strcpy(info->bus_info, pci_name(np->pdev));
6071 }
6072
6073 static int niu_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6074 {
6075         struct niu *np = netdev_priv(dev);
6076         struct niu_link_config *lp;
6077
6078         lp = &np->link_config;
6079
6080         memset(cmd, 0, sizeof(*cmd));
6081         cmd->phy_address = np->phy_addr;
6082         cmd->supported = lp->supported;
6083         cmd->advertising = lp->advertising;
6084         cmd->autoneg = lp->autoneg;
6085         cmd->speed = lp->active_speed;
6086         cmd->duplex = lp->active_duplex;
6087
6088         return 0;
6089 }
6090
6091 static int niu_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6092 {
6093         return -EINVAL;
6094 }
6095
6096 static u32 niu_get_msglevel(struct net_device *dev)
6097 {
6098         struct niu *np = netdev_priv(dev);
6099         return np->msg_enable;
6100 }
6101
6102 static void niu_set_msglevel(struct net_device *dev, u32 value)
6103 {
6104         struct niu *np = netdev_priv(dev);
6105         np->msg_enable = value;
6106 }
6107
6108 static int niu_get_eeprom_len(struct net_device *dev)
6109 {
6110         struct niu *np = netdev_priv(dev);
6111
6112         return np->eeprom_len;
6113 }
6114
6115 static int niu_get_eeprom(struct net_device *dev,
6116                           struct ethtool_eeprom *eeprom, u8 *data)
6117 {
6118         struct niu *np = netdev_priv(dev);
6119         u32 offset, len, val;
6120
6121         offset = eeprom->offset;
6122         len = eeprom->len;
6123
6124         if (offset + len < offset)
6125                 return -EINVAL;
6126         if (offset >= np->eeprom_len)
6127                 return -EINVAL;
6128         if (offset + len > np->eeprom_len)
6129                 len = eeprom->len = np->eeprom_len - offset;
6130
6131         if (offset & 3) {
6132                 u32 b_offset, b_count;
6133
6134                 b_offset = offset & 3;
6135                 b_count = 4 - b_offset;
6136                 if (b_count > len)
6137                         b_count = len;
6138
6139                 val = nr64(ESPC_NCR((offset - b_offset) / 4));
6140                 memcpy(data, ((char *)&val) + b_offset, b_count);
6141                 data += b_count;
6142                 len -= b_count;
6143                 offset += b_count;
6144         }
6145         while (len >= 4) {
6146                 val = nr64(ESPC_NCR(offset / 4));
6147                 memcpy(data, &val, 4);
6148                 data += 4;
6149                 len -= 4;
6150                 offset += 4;
6151         }
6152         if (len) {
6153                 val = nr64(ESPC_NCR(offset / 4));
6154                 memcpy(data, &val, len);
6155         }
6156         return 0;
6157 }
6158
6159 static const struct {
6160         const char string[ETH_GSTRING_LEN];
6161 } niu_xmac_stat_keys[] = {
6162         { "tx_frames" },
6163         { "tx_bytes" },
6164         { "tx_fifo_errors" },
6165         { "tx_overflow_errors" },
6166         { "tx_max_pkt_size_errors" },
6167         { "tx_underflow_errors" },
6168         { "rx_local_faults" },
6169         { "rx_remote_faults" },
6170         { "rx_link_faults" },
6171         { "rx_align_errors" },
6172         { "rx_frags" },
6173         { "rx_mcasts" },
6174         { "rx_bcasts" },
6175         { "rx_hist_cnt1" },
6176         { "rx_hist_cnt2" },
6177         { "rx_hist_cnt3" },
6178         { "rx_hist_cnt4" },
6179         { "rx_hist_cnt5" },
6180         { "rx_hist_cnt6" },
6181         { "rx_hist_cnt7" },
6182         { "rx_octets" },
6183         { "rx_code_violations" },
6184         { "rx_len_errors" },
6185         { "rx_crc_errors" },
6186         { "rx_underflows" },
6187         { "rx_overflows" },
6188         { "pause_off_state" },
6189         { "pause_on_state" },
6190         { "pause_received" },
6191 };
6192
6193 #define NUM_XMAC_STAT_KEYS      ARRAY_SIZE(niu_xmac_stat_keys)
6194
6195 static const struct {
6196         const char string[ETH_GSTRING_LEN];
6197 } niu_bmac_stat_keys[] = {
6198         { "tx_underflow_errors" },
6199         { "tx_max_pkt_size_errors" },
6200         { "tx_bytes" },
6201         { "tx_frames" },
6202         { "rx_overflows" },
6203         { "rx_frames" },
6204         { "rx_align_errors" },
6205         { "rx_crc_errors" },
6206         { "rx_len_errors" },
6207         { "pause_off_state" },
6208         { "pause_on_state" },
6209         { "pause_received" },
6210 };
6211
6212 #define NUM_BMAC_STAT_KEYS      ARRAY_SIZE(niu_bmac_stat_keys)
6213
6214 static const struct {
6215         const char string[ETH_GSTRING_LEN];
6216 } niu_rxchan_stat_keys[] = {
6217         { "rx_channel" },
6218         { "rx_packets" },
6219         { "rx_bytes" },
6220         { "rx_dropped" },
6221         { "rx_errors" },
6222 };
6223
6224 #define NUM_RXCHAN_STAT_KEYS    ARRAY_SIZE(niu_rxchan_stat_keys)
6225
6226 static const struct {
6227         const char string[ETH_GSTRING_LEN];
6228 } niu_txchan_stat_keys[] = {
6229         { "tx_channel" },
6230         { "tx_packets" },
6231         { "tx_bytes" },
6232         { "tx_errors" },
6233 };
6234
6235 #define NUM_TXCHAN_STAT_KEYS    ARRAY_SIZE(niu_txchan_stat_keys)
6236
6237 static void niu_get_strings(struct net_device *dev, u32 stringset, u8 *data)
6238 {
6239         struct niu *np = netdev_priv(dev);
6240         int i;
6241
6242         if (stringset != ETH_SS_STATS)
6243                 return;
6244
6245         if (np->flags & NIU_FLAGS_XMAC) {
6246                 memcpy(data, niu_xmac_stat_keys,
6247                        sizeof(niu_xmac_stat_keys));
6248                 data += sizeof(niu_xmac_stat_keys);
6249         } else {
6250                 memcpy(data, niu_bmac_stat_keys,
6251                        sizeof(niu_bmac_stat_keys));
6252                 data += sizeof(niu_bmac_stat_keys);
6253         }
6254         for (i = 0; i < np->num_rx_rings; i++) {
6255                 memcpy(data, niu_rxchan_stat_keys,
6256                        sizeof(niu_rxchan_stat_keys));
6257                 data += sizeof(niu_rxchan_stat_keys);
6258         }
6259         for (i = 0; i < np->num_tx_rings; i++) {
6260                 memcpy(data, niu_txchan_stat_keys,
6261                        sizeof(niu_txchan_stat_keys));
6262                 data += sizeof(niu_txchan_stat_keys);
6263         }
6264 }
6265
6266 static int niu_get_stats_count(struct net_device *dev)
6267 {
6268         struct niu *np = netdev_priv(dev);
6269
6270         return ((np->flags & NIU_FLAGS_XMAC ?
6271                  NUM_XMAC_STAT_KEYS :
6272                  NUM_BMAC_STAT_KEYS) +
6273                 (np->num_rx_rings * NUM_RXCHAN_STAT_KEYS) +
6274                 (np->num_tx_rings * NUM_TXCHAN_STAT_KEYS));
6275 }
6276
6277 static void niu_get_ethtool_stats(struct net_device *dev,
6278                                   struct ethtool_stats *stats, u64 *data)
6279 {
6280         struct niu *np = netdev_priv(dev);
6281         int i;
6282
6283         niu_sync_mac_stats(np);
6284         if (np->flags & NIU_FLAGS_XMAC) {
6285                 memcpy(data, &np->mac_stats.xmac,
6286                        sizeof(struct niu_xmac_stats));
6287                 data += (sizeof(struct niu_xmac_stats) / sizeof(u64));
6288         } else {
6289                 memcpy(data, &np->mac_stats.bmac,
6290                        sizeof(struct niu_bmac_stats));
6291                 data += (sizeof(struct niu_bmac_stats) / sizeof(u64));
6292         }
6293         for (i = 0; i < np->num_rx_rings; i++) {
6294                 struct rx_ring_info *rp = &np->rx_rings[i];
6295
6296                 data[0] = rp->rx_channel;
6297                 data[1] = rp->rx_packets;
6298                 data[2] = rp->rx_bytes;
6299                 data[3] = rp->rx_dropped;
6300                 data[4] = rp->rx_errors;
6301                 data += 5;
6302         }
6303         for (i = 0; i < np->num_tx_rings; i++) {
6304                 struct tx_ring_info *rp = &np->tx_rings[i];
6305
6306                 data[0] = rp->tx_channel;
6307                 data[1] = rp->tx_packets;
6308                 data[2] = rp->tx_bytes;
6309                 data[3] = rp->tx_errors;
6310                 data += 4;
6311         }
6312 }
6313
6314 static u64 niu_led_state_save(struct niu *np)
6315 {
6316         if (np->flags & NIU_FLAGS_XMAC)
6317                 return nr64_mac(XMAC_CONFIG);
6318         else
6319                 return nr64_mac(BMAC_XIF_CONFIG);
6320 }
6321
6322 static void niu_led_state_restore(struct niu *np, u64 val)
6323 {
6324         if (np->flags & NIU_FLAGS_XMAC)
6325                 nw64_mac(XMAC_CONFIG, val);
6326         else
6327                 nw64_mac(BMAC_XIF_CONFIG, val);
6328 }
6329
6330 static void niu_force_led(struct niu *np, int on)
6331 {
6332         u64 val, reg, bit;
6333
6334         if (np->flags & NIU_FLAGS_XMAC) {
6335                 reg = XMAC_CONFIG;
6336                 bit = XMAC_CONFIG_FORCE_LED_ON;
6337         } else {
6338                 reg = BMAC_XIF_CONFIG;
6339                 bit = BMAC_XIF_CONFIG_LINK_LED;
6340         }
6341
6342         val = nr64_mac(reg);
6343         if (on)
6344                 val |= bit;
6345         else
6346                 val &= ~bit;
6347         nw64_mac(reg, val);
6348 }
6349
6350 static int niu_phys_id(struct net_device *dev, u32 data)
6351 {
6352         struct niu *np = netdev_priv(dev);
6353         u64 orig_led_state;
6354         int i;
6355
6356         if (!netif_running(dev))
6357                 return -EAGAIN;
6358
6359         if (data == 0)
6360                 data = 2;
6361
6362         orig_led_state = niu_led_state_save(np);
6363         for (i = 0; i < (data * 2); i++) {
6364                 int on = ((i % 2) == 0);
6365
6366                 niu_force_led(np, on);
6367
6368                 if (msleep_interruptible(500))
6369                         break;
6370         }
6371         niu_led_state_restore(np, orig_led_state);
6372
6373         return 0;
6374 }
6375
6376 static const struct ethtool_ops niu_ethtool_ops = {
6377         .get_drvinfo            = niu_get_drvinfo,
6378         .get_link               = ethtool_op_get_link,
6379         .get_msglevel           = niu_get_msglevel,
6380         .set_msglevel           = niu_set_msglevel,
6381         .get_eeprom_len         = niu_get_eeprom_len,
6382         .get_eeprom             = niu_get_eeprom,
6383         .get_settings           = niu_get_settings,
6384         .set_settings           = niu_set_settings,
6385         .get_strings            = niu_get_strings,
6386         .get_stats_count        = niu_get_stats_count,
6387         .get_ethtool_stats      = niu_get_ethtool_stats,
6388         .phys_id                = niu_phys_id,
6389 };
6390
6391 static int niu_ldg_assign_ldn(struct niu *np, struct niu_parent *parent,
6392                               int ldg, int ldn)
6393 {
6394         if (ldg < NIU_LDG_MIN || ldg > NIU_LDG_MAX)
6395                 return -EINVAL;
6396         if (ldn < 0 || ldn > LDN_MAX)
6397                 return -EINVAL;
6398
6399         parent->ldg_map[ldn] = ldg;
6400
6401         if (np->parent->plat_type == PLAT_TYPE_NIU) {
6402                 /* On N2 NIU, the ldn-->ldg assignments are setup and fixed by
6403                  * the firmware, and we're not supposed to change them.
6404                  * Validate the mapping, because if it's wrong we probably
6405                  * won't get any interrupts and that's painful to debug.
6406                  */
6407                 if (nr64(LDG_NUM(ldn)) != ldg) {
6408                         dev_err(np->device, PFX "Port %u, mis-matched "
6409                                 "LDG assignment "
6410                                 "for ldn %d, should be %d is %llu\n",
6411                                 np->port, ldn, ldg,
6412                                 (unsigned long long) nr64(LDG_NUM(ldn)));
6413                         return -EINVAL;
6414                 }
6415         } else
6416                 nw64(LDG_NUM(ldn), ldg);
6417
6418         return 0;
6419 }
6420
6421 static int niu_set_ldg_timer_res(struct niu *np, int res)
6422 {
6423         if (res < 0 || res > LDG_TIMER_RES_VAL)
6424                 return -EINVAL;
6425
6426
6427         nw64(LDG_TIMER_RES, res);
6428
6429         return 0;
6430 }
6431
6432 static int niu_set_ldg_sid(struct niu *np, int ldg, int func, int vector)
6433 {
6434         if ((ldg < NIU_LDG_MIN || ldg > NIU_LDG_MAX) ||
6435             (func < 0 || func > 3) ||
6436             (vector < 0 || vector > 0x1f))
6437                 return -EINVAL;
6438
6439         nw64(SID(ldg), (func << SID_FUNC_SHIFT) | vector);
6440
6441         return 0;
6442 }
6443
6444 static int __devinit niu_pci_eeprom_read(struct niu *np, u32 addr)
6445 {
6446         u64 frame, frame_base = (ESPC_PIO_STAT_READ_START |
6447                                  (addr << ESPC_PIO_STAT_ADDR_SHIFT));
6448         int limit;
6449
6450         if (addr > (ESPC_PIO_STAT_ADDR >> ESPC_PIO_STAT_ADDR_SHIFT))
6451                 return -EINVAL;
6452
6453         frame = frame_base;
6454         nw64(ESPC_PIO_STAT, frame);
6455         limit = 64;
6456         do {
6457                 udelay(5);
6458                 frame = nr64(ESPC_PIO_STAT);
6459                 if (frame & ESPC_PIO_STAT_READ_END)
6460                         break;
6461         } while (limit--);
6462         if (!(frame & ESPC_PIO_STAT_READ_END)) {
6463                 dev_err(np->device, PFX "EEPROM read timeout frame[%llx]\n",
6464                         (unsigned long long) frame);
6465                 return -ENODEV;
6466         }
6467
6468         frame = frame_base;
6469         nw64(ESPC_PIO_STAT, frame);
6470         limit = 64;
6471         do {
6472                 udelay(5);
6473                 frame = nr64(ESPC_PIO_STAT);
6474                 if (frame & ESPC_PIO_STAT_READ_END)
6475                         break;
6476         } while (limit--);
6477         if (!(frame & ESPC_PIO_STAT_READ_END)) {
6478                 dev_err(np->device, PFX "EEPROM read timeout frame[%llx]\n",
6479                         (unsigned long long) frame);
6480                 return -ENODEV;
6481         }
6482
6483         frame = nr64(ESPC_PIO_STAT);
6484         return (frame & ESPC_PIO_STAT_DATA) >> ESPC_PIO_STAT_DATA_SHIFT;
6485 }
6486
6487 static int __devinit niu_pci_eeprom_read16(struct niu *np, u32 off)
6488 {
6489         int err = niu_pci_eeprom_read(np, off);
6490         u16 val;
6491
6492         if (err < 0)
6493                 return err;
6494         val = (err << 8);
6495         err = niu_pci_eeprom_read(np, off + 1);
6496         if (err < 0)
6497                 return err;
6498         val |= (err & 0xff);
6499
6500         return val;
6501 }
6502
6503 static int __devinit niu_pci_eeprom_read16_swp(struct niu *np, u32 off)
6504 {
6505         int err = niu_pci_eeprom_read(np, off);
6506         u16 val;
6507
6508         if (err < 0)
6509                 return err;
6510
6511         val = (err & 0xff);
6512         err = niu_pci_eeprom_read(np, off + 1);
6513         if (err < 0)
6514                 return err;
6515
6516         val |= (err & 0xff) << 8;
6517
6518         return val;
6519 }
6520
6521 static int __devinit niu_pci_vpd_get_propname(struct niu *np,
6522                                               u32 off,
6523                                               char *namebuf,
6524                                               int namebuf_len)
6525 {
6526         int i;
6527
6528         for (i = 0; i < namebuf_len; i++) {
6529                 int err = niu_pci_eeprom_read(np, off + i);
6530                 if (err < 0)
6531                         return err;
6532                 *namebuf++ = err;
6533                 if (!err)
6534                         break;
6535         }
6536         if (i >= namebuf_len)
6537                 return -EINVAL;
6538
6539         return i + 1;
6540 }
6541
6542 static void __devinit niu_vpd_parse_version(struct niu *np)
6543 {
6544         struct niu_vpd *vpd = &np->vpd;
6545         int len = strlen(vpd->version) + 1;
6546         const char *s = vpd->version;
6547         int i;
6548
6549         for (i = 0; i < len - 5; i++) {
6550                 if (!strncmp(s + i, "FCode ", 5))
6551                         break;
6552         }
6553         if (i >= len - 5)
6554                 return;
6555
6556         s += i + 5;
6557         sscanf(s, "%d.%d", &vpd->fcode_major, &vpd->fcode_minor);
6558
6559         niudbg(PROBE, "VPD_SCAN: FCODE major(%d) minor(%d)\n",
6560                vpd->fcode_major, vpd->fcode_minor);
6561         if (vpd->fcode_major > NIU_VPD_MIN_MAJOR ||
6562             (vpd->fcode_major == NIU_VPD_MIN_MAJOR &&
6563              vpd->fcode_minor >= NIU_VPD_MIN_MINOR))
6564                 np->flags |= NIU_FLAGS_VPD_VALID;
6565 }
6566
6567 /* ESPC_PIO_EN_ENABLE must be set */
6568 static int __devinit niu_pci_vpd_scan_props(struct niu *np,
6569                                             u32 start, u32 end)
6570 {
6571         unsigned int found_mask = 0;
6572 #define FOUND_MASK_MODEL        0x00000001
6573 #define FOUND_MASK_BMODEL       0x00000002
6574 #define FOUND_MASK_VERS         0x00000004
6575 #define FOUND_MASK_MAC          0x00000008
6576 #define FOUND_MASK_NMAC         0x00000010
6577 #define FOUND_MASK_PHY          0x00000020
6578 #define FOUND_MASK_ALL          0x0000003f
6579
6580         niudbg(PROBE, "VPD_SCAN: start[%x] end[%x]\n",
6581                start, end);
6582         while (start < end) {
6583                 int len, err, instance, type, prop_len;
6584                 char namebuf[64];
6585                 u8 *prop_buf;
6586                 int max_len;
6587
6588                 if (found_mask == FOUND_MASK_ALL) {
6589                         niu_vpd_parse_version(np);
6590                         return 1;
6591                 }
6592
6593                 err = niu_pci_eeprom_read(np, start + 2);
6594                 if (err < 0)
6595                         return err;
6596                 len = err;
6597                 start += 3;
6598
6599                 instance = niu_pci_eeprom_read(np, start);
6600                 type = niu_pci_eeprom_read(np, start + 3);
6601                 prop_len = niu_pci_eeprom_read(np, start + 4);
6602                 err = niu_pci_vpd_get_propname(np, start + 5, namebuf, 64);
6603                 if (err < 0)
6604                         return err;
6605
6606                 prop_buf = NULL;
6607                 max_len = 0;
6608                 if (!strcmp(namebuf, "model")) {
6609                         prop_buf = np->vpd.model;
6610                         max_len = NIU_VPD_MODEL_MAX;
6611                         found_mask |= FOUND_MASK_MODEL;
6612                 } else if (!strcmp(namebuf, "board-model")) {
6613                         prop_buf = np->vpd.board_model;
6614                         max_len = NIU_VPD_BD_MODEL_MAX;
6615                         found_mask |= FOUND_MASK_BMODEL;
6616                 } else if (!strcmp(namebuf, "version")) {
6617                         prop_buf = np->vpd.version;
6618                         max_len = NIU_VPD_VERSION_MAX;
6619                         found_mask |= FOUND_MASK_VERS;
6620                 } else if (!strcmp(namebuf, "local-mac-address")) {
6621                         prop_buf = np->vpd.local_mac;
6622                         max_len = ETH_ALEN;
6623                         found_mask |= FOUND_MASK_MAC;
6624                 } else if (!strcmp(namebuf, "num-mac-addresses")) {
6625                         prop_buf = &np->vpd.mac_num;
6626                         max_len = 1;
6627                         found_mask |= FOUND_MASK_NMAC;
6628                 } else if (!strcmp(namebuf, "phy-type")) {
6629                         prop_buf = np->vpd.phy_type;
6630                         max_len = NIU_VPD_PHY_TYPE_MAX;
6631                         found_mask |= FOUND_MASK_PHY;
6632                 }
6633
6634                 if (max_len && prop_len > max_len) {
6635                         dev_err(np->device, PFX "Property '%s' length (%d) is "
6636                                 "too long.\n", namebuf, prop_len);
6637                         return -EINVAL;
6638                 }
6639
6640                 if (prop_buf) {
6641                         u32 off = start + 5 + err;
6642                         int i;
6643
6644                         niudbg(PROBE, "VPD_SCAN: Reading in property [%s] "
6645                                "len[%d]\n", namebuf, prop_len);
6646                         for (i = 0; i < prop_len; i++)
6647                                 *prop_buf++ = niu_pci_eeprom_read(np, off + i);
6648                 }
6649
6650                 start += len;
6651         }
6652
6653         return 0;
6654 }
6655
6656 /* ESPC_PIO_EN_ENABLE must be set */
6657 static void __devinit niu_pci_vpd_fetch(struct niu *np, u32 start)
6658 {
6659         u32 offset;
6660         int err;
6661
6662         err = niu_pci_eeprom_read16_swp(np, start + 1);
6663         if (err < 0)
6664                 return;
6665
6666         offset = err + 3;
6667
6668         while (start + offset < ESPC_EEPROM_SIZE) {
6669                 u32 here = start + offset;
6670                 u32 end;
6671
6672                 err = niu_pci_eeprom_read(np, here);
6673                 if (err != 0x90)
6674                         return;
6675
6676                 err = niu_pci_eeprom_read16_swp(np, here + 1);
6677                 if (err < 0)
6678                         return;
6679
6680                 here = start + offset + 3;
6681                 end = start + offset + err;
6682
6683                 offset += err;
6684
6685                 err = niu_pci_vpd_scan_props(np, here, end);
6686                 if (err < 0 || err == 1)
6687                         return;
6688         }
6689 }
6690
6691 /* ESPC_PIO_EN_ENABLE must be set */
6692 static u32 __devinit niu_pci_vpd_offset(struct niu *np)
6693 {
6694         u32 start = 0, end = ESPC_EEPROM_SIZE, ret;
6695         int err;
6696
6697         while (start < end) {
6698                 ret = start;
6699
6700                 /* ROM header signature?  */
6701                 err = niu_pci_eeprom_read16(np, start +  0);
6702                 if (err != 0x55aa)
6703                         return 0;
6704
6705                 /* Apply offset to PCI data structure.  */
6706                 err = niu_pci_eeprom_read16(np, start + 23);
6707                 if (err < 0)
6708                         return 0;
6709                 start += err;
6710
6711                 /* Check for "PCIR" signature.  */
6712                 err = niu_pci_eeprom_read16(np, start +  0);
6713                 if (err != 0x5043)
6714                         return 0;
6715                 err = niu_pci_eeprom_read16(np, start +  2);
6716                 if (err != 0x4952)
6717                         return 0;
6718
6719                 /* Check for OBP image type.  */
6720                 err = niu_pci_eeprom_read(np, start + 20);
6721                 if (err < 0)
6722                         return 0;
6723                 if (err != 0x01) {
6724                         err = niu_pci_eeprom_read(np, ret + 2);
6725                         if (err < 0)
6726                                 return 0;
6727
6728                         start = ret + (err * 512);
6729                         continue;
6730                 }
6731
6732                 err = niu_pci_eeprom_read16_swp(np, start + 8);
6733                 if (err < 0)
6734                         return err;
6735                 ret += err;
6736
6737                 err = niu_pci_eeprom_read(np, ret + 0);
6738                 if (err != 0x82)
6739                         return 0;
6740
6741                 return ret;
6742         }
6743
6744         return 0;
6745 }
6746
6747 static int __devinit niu_phy_type_prop_decode(struct niu *np,
6748                                               const char *phy_prop)
6749 {
6750         if (!strcmp(phy_prop, "mif")) {
6751                 /* 1G copper, MII */
6752                 np->flags &= ~(NIU_FLAGS_FIBER |
6753                                NIU_FLAGS_10G);
6754                 np->mac_xcvr = MAC_XCVR_MII;
6755         } else if (!strcmp(phy_prop, "xgf")) {
6756                 /* 10G fiber, XPCS */
6757                 np->flags |= (NIU_FLAGS_10G |
6758                               NIU_FLAGS_FIBER);
6759                 np->mac_xcvr = MAC_XCVR_XPCS;
6760         } else if (!strcmp(phy_prop, "pcs")) {
6761                 /* 1G fiber, PCS */
6762                 np->flags &= ~NIU_FLAGS_10G;
6763                 np->flags |= NIU_FLAGS_FIBER;
6764                 np->mac_xcvr = MAC_XCVR_PCS;
6765         } else if (!strcmp(phy_prop, "xgc")) {
6766                 /* 10G copper, XPCS */
6767                 np->flags |= NIU_FLAGS_10G;
6768                 np->flags &= ~NIU_FLAGS_FIBER;
6769                 np->mac_xcvr = MAC_XCVR_XPCS;
6770         } else {
6771                 return -EINVAL;
6772         }
6773         return 0;
6774 }
6775
6776 static void __devinit niu_pci_vpd_validate(struct niu *np)
6777 {
6778         struct net_device *dev = np->dev;
6779         struct niu_vpd *vpd = &np->vpd;
6780         u8 val8;
6781
6782         if (!is_valid_ether_addr(&vpd->local_mac[0])) {
6783                 dev_err(np->device, PFX "VPD MAC invalid, "
6784                         "falling back to SPROM.\n");
6785
6786                 np->flags &= ~NIU_FLAGS_VPD_VALID;
6787                 return;
6788         }
6789
6790         if (!strcmp(np->vpd.model, "SUNW,CP3220") ||
6791             !strcmp(np->vpd.model, "SUNW,CP3260")) {
6792                 np->flags |= NIU_FLAGS_10G;
6793                 np->flags &= ~NIU_FLAGS_FIBER;
6794                 np->flags |= NIU_FLAGS_XCVR_SERDES;
6795                 np->mac_xcvr = MAC_XCVR_PCS;
6796                 if (np->port > 1) {
6797                         np->flags |= NIU_FLAGS_FIBER;
6798                         np->flags &= ~NIU_FLAGS_10G;
6799                 }
6800                 if (np->flags & NIU_FLAGS_10G)
6801                          np->mac_xcvr = MAC_XCVR_XPCS;
6802         } else if (niu_phy_type_prop_decode(np, np->vpd.phy_type)) {
6803                 dev_err(np->device, PFX "Illegal phy string [%s].\n",
6804                         np->vpd.phy_type);
6805                 dev_err(np->device, PFX "Falling back to SPROM.\n");
6806                 np->flags &= ~NIU_FLAGS_VPD_VALID;
6807                 return;
6808         }
6809
6810         memcpy(dev->perm_addr, vpd->local_mac, ETH_ALEN);
6811
6812         val8 = dev->perm_addr[5];
6813         dev->perm_addr[5] += np->port;
6814         if (dev->perm_addr[5] < val8)
6815                 dev->perm_addr[4]++;
6816
6817         memcpy(dev->dev_addr, dev->perm_addr, dev->addr_len);
6818 }
6819
6820 static int __devinit niu_pci_probe_sprom(struct niu *np)
6821 {
6822         struct net_device *dev = np->dev;
6823         int len, i;
6824         u64 val, sum;
6825         u8 val8;
6826
6827         val = (nr64(ESPC_VER_IMGSZ) & ESPC_VER_IMGSZ_IMGSZ);
6828         val >>= ESPC_VER_IMGSZ_IMGSZ_SHIFT;
6829         len = val / 4;
6830
6831         np->eeprom_len = len;
6832
6833         niudbg(PROBE, "SPROM: Image size %llu\n", (unsigned long long) val);
6834
6835         sum = 0;
6836         for (i = 0; i < len; i++) {
6837                 val = nr64(ESPC_NCR(i));
6838                 sum += (val >>  0) & 0xff;
6839                 sum += (val >>  8) & 0xff;
6840                 sum += (val >> 16) & 0xff;
6841                 sum += (val >> 24) & 0xff;
6842         }
6843         niudbg(PROBE, "SPROM: Checksum %x\n", (int)(sum & 0xff));
6844         if ((sum & 0xff) != 0xab) {
6845                 dev_err(np->device, PFX "Bad SPROM checksum "
6846                         "(%x, should be 0xab)\n", (int) (sum & 0xff));
6847                 return -EINVAL;
6848         }
6849
6850         val = nr64(ESPC_PHY_TYPE);
6851         switch (np->port) {
6852         case 0:
6853                 val8 = (val & ESPC_PHY_TYPE_PORT0) >>
6854                         ESPC_PHY_TYPE_PORT0_SHIFT;
6855                 break;
6856         case 1:
6857                 val8 = (val & ESPC_PHY_TYPE_PORT1) >>
6858                         ESPC_PHY_TYPE_PORT1_SHIFT;
6859                 break;
6860         case 2:
6861                 val8 = (val & ESPC_PHY_TYPE_PORT2) >>
6862                         ESPC_PHY_TYPE_PORT2_SHIFT;
6863                 break;
6864         case 3:
6865                 val8 = (val & ESPC_PHY_TYPE_PORT3) >>
6866                         ESPC_PHY_TYPE_PORT3_SHIFT;
6867                 break;
6868         default:
6869                 dev_err(np->device, PFX "Bogus port number %u\n",
6870                         np->port);
6871                 return -EINVAL;
6872         }
6873         niudbg(PROBE, "SPROM: PHY type %x\n", val8);
6874
6875         switch (val8) {
6876         case ESPC_PHY_TYPE_1G_COPPER:
6877                 /* 1G copper, MII */
6878                 np->flags &= ~(NIU_FLAGS_FIBER |
6879                                NIU_FLAGS_10G);
6880                 np->mac_xcvr = MAC_XCVR_MII;
6881                 break;
6882
6883         case ESPC_PHY_TYPE_1G_FIBER:
6884                 /* 1G fiber, PCS */
6885                 np->flags &= ~NIU_FLAGS_10G;
6886                 np->flags |= NIU_FLAGS_FIBER;
6887                 np->mac_xcvr = MAC_XCVR_PCS;
6888                 break;
6889
6890         case ESPC_PHY_TYPE_10G_COPPER:
6891                 /* 10G copper, XPCS */
6892                 np->flags |= NIU_FLAGS_10G;
6893                 np->flags &= ~NIU_FLAGS_FIBER;
6894                 np->mac_xcvr = MAC_XCVR_XPCS;
6895                 break;
6896
6897         case ESPC_PHY_TYPE_10G_FIBER:
6898                 /* 10G fiber, XPCS */
6899                 np->flags |= (NIU_FLAGS_10G |
6900                               NIU_FLAGS_FIBER);
6901                 np->mac_xcvr = MAC_XCVR_XPCS;
6902                 break;
6903
6904         default:
6905                 dev_err(np->device, PFX "Bogus SPROM phy type %u\n", val8);
6906                 return -EINVAL;
6907         }
6908
6909         val = nr64(ESPC_MAC_ADDR0);
6910         niudbg(PROBE, "SPROM: MAC_ADDR0[%08llx]\n",
6911                (unsigned long long) val);
6912         dev->perm_addr[0] = (val >>  0) & 0xff;
6913         dev->perm_addr[1] = (val >>  8) & 0xff;
6914         dev->perm_addr[2] = (val >> 16) & 0xff;
6915         dev->perm_addr[3] = (val >> 24) & 0xff;
6916
6917         val = nr64(ESPC_MAC_ADDR1);
6918         niudbg(PROBE, "SPROM: MAC_ADDR1[%08llx]\n",
6919                (unsigned long long) val);
6920         dev->perm_addr[4] = (val >>  0) & 0xff;
6921         dev->perm_addr[5] = (val >>  8) & 0xff;
6922
6923         if (!is_valid_ether_addr(&dev->perm_addr[0])) {
6924                 dev_err(np->device, PFX "SPROM MAC address invalid\n");
6925                 dev_err(np->device, PFX "[ \n");
6926                 for (i = 0; i < 6; i++)
6927                         printk("%02x ", dev->perm_addr[i]);
6928                 printk("]\n");
6929                 return -EINVAL;
6930         }
6931
6932         val8 = dev->perm_addr[5];
6933         dev->perm_addr[5] += np->port;
6934         if (dev->perm_addr[5] < val8)
6935                 dev->perm_addr[4]++;
6936
6937         memcpy(dev->dev_addr, dev->perm_addr, dev->addr_len);
6938
6939         val = nr64(ESPC_MOD_STR_LEN);
6940         niudbg(PROBE, "SPROM: MOD_STR_LEN[%llu]\n",
6941                (unsigned long long) val);
6942         if (val >= 8 * 4)
6943                 return -EINVAL;
6944
6945         for (i = 0; i < val; i += 4) {
6946                 u64 tmp = nr64(ESPC_NCR(5 + (i / 4)));
6947
6948                 np->vpd.model[i + 3] = (tmp >>  0) & 0xff;
6949                 np->vpd.model[i + 2] = (tmp >>  8) & 0xff;
6950                 np->vpd.model[i + 1] = (tmp >> 16) & 0xff;
6951                 np->vpd.model[i + 0] = (tmp >> 24) & 0xff;
6952         }
6953         np->vpd.model[val] = '\0';
6954
6955         val = nr64(ESPC_BD_MOD_STR_LEN);
6956         niudbg(PROBE, "SPROM: BD_MOD_STR_LEN[%llu]\n",
6957                (unsigned long long) val);
6958         if (val >= 4 * 4)
6959                 return -EINVAL;
6960
6961         for (i = 0; i < val; i += 4) {
6962                 u64 tmp = nr64(ESPC_NCR(14 + (i / 4)));
6963
6964                 np->vpd.board_model[i + 3] = (tmp >>  0) & 0xff;
6965                 np->vpd.board_model[i + 2] = (tmp >>  8) & 0xff;
6966                 np->vpd.board_model[i + 1] = (tmp >> 16) & 0xff;
6967                 np->vpd.board_model[i + 0] = (tmp >> 24) & 0xff;
6968         }
6969         np->vpd.board_model[val] = '\0';
6970
6971         np->vpd.mac_num =
6972                 nr64(ESPC_NUM_PORTS_MACS) & ESPC_NUM_PORTS_MACS_VAL;
6973         niudbg(PROBE, "SPROM: NUM_PORTS_MACS[%d]\n",
6974                np->vpd.mac_num);
6975
6976         return 0;
6977 }
6978
6979 static int __devinit niu_get_and_validate_port(struct niu *np)
6980 {
6981         struct niu_parent *parent = np->parent;
6982
6983         if (np->port <= 1)
6984                 np->flags |= NIU_FLAGS_XMAC;
6985
6986         if (!parent->num_ports) {
6987                 if (parent->plat_type == PLAT_TYPE_NIU) {
6988                         parent->num_ports = 2;
6989                 } else {
6990                         parent->num_ports = nr64(ESPC_NUM_PORTS_MACS) &
6991                                 ESPC_NUM_PORTS_MACS_VAL;
6992
6993                         if (!parent->num_ports)
6994                                 parent->num_ports = 4;
6995                 }
6996         }
6997
6998         niudbg(PROBE, "niu_get_and_validate_port: port[%d] num_ports[%d]\n",
6999                np->port, parent->num_ports);
7000         if (np->port >= parent->num_ports)
7001                 return -ENODEV;
7002
7003         return 0;
7004 }
7005
7006 static int __devinit phy_record(struct niu_parent *parent,
7007                                 struct phy_probe_info *p,
7008                                 int dev_id_1, int dev_id_2, u8 phy_port,
7009                                 int type)
7010 {
7011         u32 id = (dev_id_1 << 16) | dev_id_2;
7012         u8 idx;
7013
7014         if (dev_id_1 < 0 || dev_id_2 < 0)
7015                 return 0;
7016         if (type == PHY_TYPE_PMA_PMD || type == PHY_TYPE_PCS) {
7017                 if (((id & NIU_PHY_ID_MASK) != NIU_PHY_ID_BCM8704) &&
7018                     ((id & NIU_PHY_ID_MASK) != NIU_PHY_ID_MRVL88X2011))
7019                         return 0;
7020         } else {
7021                 if ((id & NIU_PHY_ID_MASK) != NIU_PHY_ID_BCM5464R)
7022                         return 0;
7023         }
7024
7025         pr_info("niu%d: Found PHY %08x type %s at phy_port %u\n",
7026                 parent->index, id,
7027                 (type == PHY_TYPE_PMA_PMD ?
7028                  "PMA/PMD" :
7029                  (type == PHY_TYPE_PCS ?
7030                   "PCS" : "MII")),
7031                 phy_port);
7032
7033         if (p->cur[type] >= NIU_MAX_PORTS) {
7034                 printk(KERN_ERR PFX "Too many PHY ports.\n");
7035                 return -EINVAL;
7036         }
7037         idx = p->cur[type];
7038         p->phy_id[type][idx] = id;
7039         p->phy_port[type][idx] = phy_port;
7040         p->cur[type] = idx + 1;
7041         return 0;
7042 }
7043
7044 static int __devinit port_has_10g(struct phy_probe_info *p, int port)
7045 {
7046         int i;
7047
7048         for (i = 0; i < p->cur[PHY_TYPE_PMA_PMD]; i++) {
7049                 if (p->phy_port[PHY_TYPE_PMA_PMD][i] == port)
7050                         return 1;
7051         }
7052         for (i = 0; i < p->cur[PHY_TYPE_PCS]; i++) {
7053                 if (p->phy_port[PHY_TYPE_PCS][i] == port)
7054                         return 1;
7055         }
7056
7057         return 0;
7058 }
7059
7060 static int __devinit count_10g_ports(struct phy_probe_info *p, int *lowest)
7061 {
7062         int port, cnt;
7063
7064         cnt = 0;
7065         *lowest = 32;
7066         for (port = 8; port < 32; port++) {
7067                 if (port_has_10g(p, port)) {
7068                         if (!cnt)
7069                                 *lowest = port;
7070                         cnt++;
7071                 }
7072         }
7073
7074         return cnt;
7075 }
7076
7077 static int __devinit count_1g_ports(struct phy_probe_info *p, int *lowest)
7078 {
7079         *lowest = 32;
7080         if (p->cur[PHY_TYPE_MII])
7081                 *lowest = p->phy_port[PHY_TYPE_MII][0];
7082
7083         return p->cur[PHY_TYPE_MII];
7084 }
7085
7086 static void __devinit niu_n2_divide_channels(struct niu_parent *parent)
7087 {
7088         int num_ports = parent->num_ports;
7089         int i;
7090
7091         for (i = 0; i < num_ports; i++) {
7092                 parent->rxchan_per_port[i] = (16 / num_ports);
7093                 parent->txchan_per_port[i] = (16 / num_ports);
7094
7095                 pr_info(PFX "niu%d: Port %u [%u RX chans] "
7096                         "[%u TX chans]\n",
7097                         parent->index, i,
7098                         parent->rxchan_per_port[i],
7099                         parent->txchan_per_port[i]);
7100         }
7101 }
7102
7103 static void __devinit niu_divide_channels(struct niu_parent *parent,
7104                                           int num_10g, int num_1g)
7105 {
7106         int num_ports = parent->num_ports;
7107         int rx_chans_per_10g, rx_chans_per_1g;
7108         int tx_chans_per_10g, tx_chans_per_1g;
7109         int i, tot_rx, tot_tx;
7110
7111         if (!num_10g || !num_1g) {
7112                 rx_chans_per_10g = rx_chans_per_1g =
7113                         (NIU_NUM_RXCHAN / num_ports);
7114                 tx_chans_per_10g = tx_chans_per_1g =
7115                         (NIU_NUM_TXCHAN / num_ports);
7116         } else {
7117                 rx_chans_per_1g = NIU_NUM_RXCHAN / 8;
7118                 rx_chans_per_10g = (NIU_NUM_RXCHAN -
7119                                     (rx_chans_per_1g * num_1g)) /
7120                         num_10g;
7121
7122                 tx_chans_per_1g = NIU_NUM_TXCHAN / 6;
7123                 tx_chans_per_10g = (NIU_NUM_TXCHAN -
7124                                     (tx_chans_per_1g * num_1g)) /
7125                         num_10g;
7126         }
7127
7128         tot_rx = tot_tx = 0;
7129         for (i = 0; i < num_ports; i++) {
7130                 int type = phy_decode(parent->port_phy, i);
7131
7132                 if (type == PORT_TYPE_10G) {
7133                         parent->rxchan_per_port[i] = rx_chans_per_10g;
7134                         parent->txchan_per_port[i] = tx_chans_per_10g;
7135                 } else {
7136                         parent->rxchan_per_port[i] = rx_chans_per_1g;
7137                         parent->txchan_per_port[i] = tx_chans_per_1g;
7138                 }
7139                 pr_info(PFX "niu%d: Port %u [%u RX chans] "
7140                         "[%u TX chans]\n",
7141                         parent->index, i,
7142                         parent->rxchan_per_port[i],
7143                         parent->txchan_per_port[i]);
7144                 tot_rx += parent->rxchan_per_port[i];
7145                 tot_tx += parent->txchan_per_port[i];
7146         }
7147
7148         if (tot_rx > NIU_NUM_RXCHAN) {
7149                 printk(KERN_ERR PFX "niu%d: Too many RX channels (%d), "
7150                        "resetting to one per port.\n",
7151                        parent->index, tot_rx);
7152                 for (i = 0; i < num_ports; i++)
7153                         parent->rxchan_per_port[i] = 1;
7154         }
7155         if (tot_tx > NIU_NUM_TXCHAN) {
7156                 printk(KERN_ERR PFX "niu%d: Too many TX channels (%d), "
7157                        "resetting to one per port.\n",
7158                        parent->index, tot_tx);
7159                 for (i = 0; i < num_ports; i++)
7160                         parent->txchan_per_port[i] = 1;
7161         }
7162         if (tot_rx < NIU_NUM_RXCHAN || tot_tx < NIU_NUM_TXCHAN) {
7163                 printk(KERN_WARNING PFX "niu%d: Driver bug, wasted channels, "
7164                        "RX[%d] TX[%d]\n",
7165                        parent->index, tot_rx, tot_tx);
7166         }
7167 }
7168
7169 static void __devinit niu_divide_rdc_groups(struct niu_parent *parent,
7170                                             int num_10g, int num_1g)
7171 {
7172         int i, num_ports = parent->num_ports;
7173         int rdc_group, rdc_groups_per_port;
7174         int rdc_channel_base;
7175
7176         rdc_group = 0;
7177         rdc_groups_per_port = NIU_NUM_RDC_TABLES / num_ports;
7178
7179         rdc_channel_base = 0;
7180
7181         for (i = 0; i < num_ports; i++) {
7182                 struct niu_rdc_tables *tp = &parent->rdc_group_cfg[i];
7183                 int grp, num_channels = parent->rxchan_per_port[i];
7184                 int this_channel_offset;
7185
7186                 tp->first_table_num = rdc_group;
7187                 tp->num_tables = rdc_groups_per_port;
7188                 this_channel_offset = 0;
7189                 for (grp = 0; grp < tp->num_tables; grp++) {
7190                         struct rdc_table *rt = &tp->tables[grp];
7191                         int slot;
7192
7193                         pr_info(PFX "niu%d: Port %d RDC tbl(%d) [ ",
7194                                 parent->index, i, tp->first_table_num + grp);
7195                         for (slot = 0; slot < NIU_RDC_TABLE_SLOTS; slot++) {
7196                                 rt->rxdma_channel[slot] =
7197                                         rdc_channel_base + this_channel_offset;
7198
7199                                 printk("%d ", rt->rxdma_channel[slot]);
7200
7201                                 if (++this_channel_offset == num_channels)
7202                                         this_channel_offset = 0;
7203                         }
7204                         printk("]\n");
7205                 }
7206
7207                 parent->rdc_default[i] = rdc_channel_base;
7208
7209                 rdc_channel_base += num_channels;
7210                 rdc_group += rdc_groups_per_port;
7211         }
7212 }
7213
7214 static int __devinit fill_phy_probe_info(struct niu *np,
7215                                          struct niu_parent *parent,
7216                                          struct phy_probe_info *info)
7217 {
7218         unsigned long flags;
7219         int port, err;
7220
7221         memset(info, 0, sizeof(*info));
7222
7223         /* Port 0 to 7 are reserved for onboard Serdes, probe the rest.  */
7224         niu_lock_parent(np, flags);
7225         err = 0;
7226         for (port = 8; port < 32; port++) {
7227                 int dev_id_1, dev_id_2;
7228
7229                 dev_id_1 = mdio_read(np, port,
7230                                      NIU_PMA_PMD_DEV_ADDR, MII_PHYSID1);
7231                 dev_id_2 = mdio_read(np, port,
7232                                      NIU_PMA_PMD_DEV_ADDR, MII_PHYSID2);
7233                 err = phy_record(parent, info, dev_id_1, dev_id_2, port,
7234                                  PHY_TYPE_PMA_PMD);
7235                 if (err)
7236                         break;
7237                 dev_id_1 = mdio_read(np, port,
7238                                      NIU_PCS_DEV_ADDR, MII_PHYSID1);
7239                 dev_id_2 = mdio_read(np, port,
7240                                      NIU_PCS_DEV_ADDR, MII_PHYSID2);
7241                 err = phy_record(parent, info, dev_id_1, dev_id_2, port,
7242                                  PHY_TYPE_PCS);
7243                 if (err)
7244                         break;
7245                 dev_id_1 = mii_read(np, port, MII_PHYSID1);
7246                 dev_id_2 = mii_read(np, port, MII_PHYSID2);
7247                 err = phy_record(parent, info, dev_id_1, dev_id_2, port,
7248                                  PHY_TYPE_MII);
7249                 if (err)
7250                         break;
7251         }
7252         niu_unlock_parent(np, flags);
7253
7254         return err;
7255 }
7256
7257 static int __devinit walk_phys(struct niu *np, struct niu_parent *parent)
7258 {
7259         struct phy_probe_info *info = &parent->phy_probe_info;
7260         int lowest_10g, lowest_1g;
7261         int num_10g, num_1g;
7262         u32 val;
7263         int err;
7264
7265
7266         if (!strcmp(np->vpd.model, "SUNW,CP3220") ||
7267             !strcmp(np->vpd.model, "SUNW,CP3260")) {
7268                 num_10g = 0;
7269                 num_1g = 2;
7270                 parent->plat_type = PLAT_TYPE_ATCA_CP3220;
7271                 parent->num_ports = 4;
7272                 val = (phy_encode(PORT_TYPE_1G, 0) |
7273                        phy_encode(PORT_TYPE_1G, 1) |
7274                        phy_encode(PORT_TYPE_1G, 2) |
7275                        phy_encode(PORT_TYPE_1G, 3));
7276         } else {
7277                 err = fill_phy_probe_info(np, parent, info);
7278                 if (err)
7279                         return err;
7280
7281                 num_10g = count_10g_ports(info, &lowest_10g);
7282                 num_1g = count_1g_ports(info, &lowest_1g);
7283
7284                 switch ((num_10g << 4) | num_1g) {
7285                 case 0x24:
7286                         if (lowest_1g == 10)
7287                                 parent->plat_type = PLAT_TYPE_VF_P0;
7288                         else if (lowest_1g == 26)
7289                                 parent->plat_type = PLAT_TYPE_VF_P1;
7290                         else
7291                                 goto unknown_vg_1g_port;
7292
7293                         /* fallthru */
7294                 case 0x22:
7295                         val = (phy_encode(PORT_TYPE_10G, 0) |
7296                                phy_encode(PORT_TYPE_10G, 1) |
7297                                phy_encode(PORT_TYPE_1G, 2) |
7298                                phy_encode(PORT_TYPE_1G, 3));
7299                         break;
7300
7301                 case 0x20:
7302                         val = (phy_encode(PORT_TYPE_10G, 0) |
7303                                phy_encode(PORT_TYPE_10G, 1));
7304                         break;
7305
7306                 case 0x10:
7307                         val = phy_encode(PORT_TYPE_10G, np->port);
7308                         break;
7309
7310                 case 0x14:
7311                         if (lowest_1g == 10)
7312                                 parent->plat_type = PLAT_TYPE_VF_P0;
7313                         else if (lowest_1g == 26)
7314                                 parent->plat_type = PLAT_TYPE_VF_P1;
7315                         else
7316                                 goto unknown_vg_1g_port;
7317
7318                         /* fallthru */
7319                 case 0x13:
7320                         if ((lowest_10g & 0x7) == 0)
7321                                 val = (phy_encode(PORT_TYPE_10G, 0) |
7322                                        phy_encode(PORT_TYPE_1G, 1) |
7323                                        phy_encode(PORT_TYPE_1G, 2) |
7324                                        phy_encode(PORT_TYPE_1G, 3));
7325                         else
7326                                 val = (phy_encode(PORT_TYPE_1G, 0) |
7327                                        phy_encode(PORT_TYPE_10G, 1) |
7328                                        phy_encode(PORT_TYPE_1G, 2) |
7329                                        phy_encode(PORT_TYPE_1G, 3));
7330                         break;
7331
7332                 case 0x04:
7333                         if (lowest_1g == 10)
7334                                 parent->plat_type = PLAT_TYPE_VF_P0;
7335                         else if (lowest_1g == 26)
7336                                 parent->plat_type = PLAT_TYPE_VF_P1;
7337                         else
7338                                 goto unknown_vg_1g_port;
7339
7340                         val = (phy_encode(PORT_TYPE_1G, 0) |
7341                                phy_encode(PORT_TYPE_1G, 1) |
7342                                phy_encode(PORT_TYPE_1G, 2) |
7343                                phy_encode(PORT_TYPE_1G, 3));
7344                         break;
7345
7346                 default:
7347                         printk(KERN_ERR PFX "Unsupported port config "
7348                                "10G[%d] 1G[%d]\n",
7349                                num_10g, num_1g);
7350                         return -EINVAL;
7351                 }
7352         }
7353
7354         parent->port_phy = val;
7355
7356         if (parent->plat_type == PLAT_TYPE_NIU)
7357                 niu_n2_divide_channels(parent);
7358         else
7359                 niu_divide_channels(parent, num_10g, num_1g);
7360
7361         niu_divide_rdc_groups(parent, num_10g, num_1g);
7362
7363         return 0;
7364
7365 unknown_vg_1g_port:
7366         printk(KERN_ERR PFX "Cannot identify platform type, 1gport=%d\n",
7367                lowest_1g);
7368         return -EINVAL;
7369 }
7370
7371 static int __devinit niu_probe_ports(struct niu *np)
7372 {
7373         struct niu_parent *parent = np->parent;
7374         int err, i;
7375
7376         niudbg(PROBE, "niu_probe_ports(): port_phy[%08x]\n",
7377                parent->port_phy);
7378
7379         if (parent->port_phy == PORT_PHY_UNKNOWN) {
7380                 err = walk_phys(np, parent);
7381                 if (err)
7382                         return err;
7383
7384                 niu_set_ldg_timer_res(np, 2);
7385                 for (i = 0; i <= LDN_MAX; i++)
7386                         niu_ldn_irq_enable(np, i, 0);
7387         }
7388
7389         if (parent->port_phy == PORT_PHY_INVALID)
7390                 return -EINVAL;
7391
7392         return 0;
7393 }
7394
7395 static int __devinit niu_classifier_swstate_init(struct niu *np)
7396 {
7397         struct niu_classifier *cp = &np->clas;
7398
7399         niudbg(PROBE, "niu_classifier_swstate_init: num_tcam(%d)\n",
7400                np->parent->tcam_num_entries);
7401
7402         cp->tcam_index = (u16) np->port;
7403         cp->h1_init = 0xffffffff;
7404         cp->h2_init = 0xffff;
7405
7406         return fflp_early_init(np);
7407 }
7408
7409 static void __devinit niu_link_config_init(struct niu *np)
7410 {
7411         struct niu_link_config *lp = &np->link_config;
7412
7413         lp->advertising = (ADVERTISED_10baseT_Half |
7414                            ADVERTISED_10baseT_Full |
7415                            ADVERTISED_100baseT_Half |
7416                            ADVERTISED_100baseT_Full |
7417                            ADVERTISED_1000baseT_Half |
7418                            ADVERTISED_1000baseT_Full |
7419                            ADVERTISED_10000baseT_Full |
7420                            ADVERTISED_Autoneg);
7421         lp->speed = lp->active_speed = SPEED_INVALID;
7422         lp->duplex = lp->active_duplex = DUPLEX_INVALID;
7423 #if 0
7424         lp->loopback_mode = LOOPBACK_MAC;
7425         lp->active_speed = SPEED_10000;
7426         lp->active_duplex = DUPLEX_FULL;
7427 #else
7428         lp->loopback_mode = LOOPBACK_DISABLED;
7429 #endif
7430 }
7431
7432 static int __devinit niu_init_mac_ipp_pcs_base(struct niu *np)
7433 {
7434         switch (np->port) {
7435         case 0:
7436                 np->mac_regs = np->regs + XMAC_PORT0_OFF;
7437                 np->ipp_off  = 0x00000;
7438                 np->pcs_off  = 0x04000;
7439                 np->xpcs_off = 0x02000;
7440                 break;
7441
7442         case 1:
7443                 np->mac_regs = np->regs + XMAC_PORT1_OFF;
7444                 np->ipp_off  = 0x08000;
7445                 np->pcs_off  = 0x0a000;
7446                 np->xpcs_off = 0x08000;
7447                 break;
7448
7449         case 2:
7450                 np->mac_regs = np->regs + BMAC_PORT2_OFF;
7451                 np->ipp_off  = 0x04000;
7452                 np->pcs_off  = 0x0e000;
7453                 np->xpcs_off = ~0UL;
7454                 break;
7455
7456         case 3:
7457                 np->mac_regs = np->regs + BMAC_PORT3_OFF;
7458                 np->ipp_off  = 0x0c000;
7459                 np->pcs_off  = 0x12000;
7460                 np->xpcs_off = ~0UL;
7461                 break;
7462
7463         default:
7464                 dev_err(np->device, PFX "Port %u is invalid, cannot "
7465                         "compute MAC block offset.\n", np->port);
7466                 return -EINVAL;
7467         }
7468
7469         return 0;
7470 }
7471
7472 static void __devinit niu_try_msix(struct niu *np, u8 *ldg_num_map)
7473 {
7474         struct msix_entry msi_vec[NIU_NUM_LDG];
7475         struct niu_parent *parent = np->parent;
7476         struct pci_dev *pdev = np->pdev;
7477         int i, num_irqs, err;
7478         u8 first_ldg;
7479
7480         first_ldg = (NIU_NUM_LDG / parent->num_ports) * np->port;
7481         for (i = 0; i < (NIU_NUM_LDG / parent->num_ports); i++)
7482                 ldg_num_map[i] = first_ldg + i;
7483
7484         num_irqs = (parent->rxchan_per_port[np->port] +
7485                     parent->txchan_per_port[np->port] +
7486                     (np->port == 0 ? 3 : 1));
7487         BUG_ON(num_irqs > (NIU_NUM_LDG / parent->num_ports));
7488
7489 retry:
7490         for (i = 0; i < num_irqs; i++) {
7491                 msi_vec[i].vector = 0;
7492                 msi_vec[i].entry = i;
7493         }
7494
7495         err = pci_enable_msix(pdev, msi_vec, num_irqs);
7496         if (err < 0) {
7497                 np->flags &= ~NIU_FLAGS_MSIX;
7498                 return;
7499         }
7500         if (err > 0) {
7501                 num_irqs = err;
7502                 goto retry;
7503         }
7504
7505         np->flags |= NIU_FLAGS_MSIX;
7506         for (i = 0; i < num_irqs; i++)
7507                 np->ldg[i].irq = msi_vec[i].vector;
7508         np->num_ldg = num_irqs;
7509 }
7510
7511 static int __devinit niu_n2_irq_init(struct niu *np, u8 *ldg_num_map)
7512 {
7513 #ifdef CONFIG_SPARC64
7514         struct of_device *op = np->op;
7515         const u32 *int_prop;
7516         int i;
7517
7518         int_prop = of_get_property(op->node, "interrupts", NULL);
7519         if (!int_prop)
7520                 return -ENODEV;
7521
7522         for (i = 0; i < op->num_irqs; i++) {
7523                 ldg_num_map[i] = int_prop[i];
7524                 np->ldg[i].irq = op->irqs[i];
7525         }
7526
7527         np->num_ldg = op->num_irqs;
7528
7529         return 0;
7530 #else
7531         return -EINVAL;
7532 #endif
7533 }
7534
7535 static int __devinit niu_ldg_init(struct niu *np)
7536 {
7537         struct niu_parent *parent = np->parent;
7538         u8 ldg_num_map[NIU_NUM_LDG];
7539         int first_chan, num_chan;
7540         int i, err, ldg_rotor;
7541         u8 port;
7542
7543         np->num_ldg = 1;
7544         np->ldg[0].irq = np->dev->irq;
7545         if (parent->plat_type == PLAT_TYPE_NIU) {
7546                 err = niu_n2_irq_init(np, ldg_num_map);
7547                 if (err)
7548                         return err;
7549         } else
7550                 niu_try_msix(np, ldg_num_map);
7551
7552         port = np->port;
7553         for (i = 0; i < np->num_ldg; i++) {
7554                 struct niu_ldg *lp = &np->ldg[i];
7555
7556                 netif_napi_add(np->dev, &lp->napi, niu_poll, 64);
7557
7558                 lp->np = np;
7559                 lp->ldg_num = ldg_num_map[i];
7560                 lp->timer = 2; /* XXX */
7561
7562                 /* On N2 NIU the firmware has setup the SID mappings so they go
7563                  * to the correct values that will route the LDG to the proper
7564                  * interrupt in the NCU interrupt table.
7565                  */
7566                 if (np->parent->plat_type != PLAT_TYPE_NIU) {
7567                         err = niu_set_ldg_sid(np, lp->ldg_num, port, i);
7568                         if (err)
7569                                 return err;
7570                 }
7571         }
7572
7573         /* We adopt the LDG assignment ordering used by the N2 NIU
7574          * 'interrupt' properties because that simplifies a lot of
7575          * things.  This ordering is:
7576          *
7577          *      MAC
7578          *      MIF     (if port zero)
7579          *      SYSERR  (if port zero)
7580          *      RX channels
7581          *      TX channels
7582          */
7583
7584         ldg_rotor = 0;
7585
7586         err = niu_ldg_assign_ldn(np, parent, ldg_num_map[ldg_rotor],
7587                                   LDN_MAC(port));
7588         if (err)
7589                 return err;
7590
7591         ldg_rotor++;
7592         if (ldg_rotor == np->num_ldg)
7593                 ldg_rotor = 0;
7594
7595         if (port == 0) {
7596                 err = niu_ldg_assign_ldn(np, parent,
7597                                          ldg_num_map[ldg_rotor],
7598                                          LDN_MIF);
7599                 if (err)
7600                         return err;
7601
7602                 ldg_rotor++;
7603                 if (ldg_rotor == np->num_ldg)
7604                         ldg_rotor = 0;
7605
7606                 err = niu_ldg_assign_ldn(np, parent,
7607                                          ldg_num_map[ldg_rotor],
7608                                          LDN_DEVICE_ERROR);
7609                 if (err)
7610                         return err;
7611
7612                 ldg_rotor++;
7613                 if (ldg_rotor == np->num_ldg)
7614                         ldg_rotor = 0;
7615
7616         }
7617
7618         first_chan = 0;
7619         for (i = 0; i < port; i++)
7620                 first_chan += parent->rxchan_per_port[port];
7621         num_chan = parent->rxchan_per_port[port];
7622
7623         for (i = first_chan; i < (first_chan + num_chan); i++) {
7624                 err = niu_ldg_assign_ldn(np, parent,
7625                                          ldg_num_map[ldg_rotor],
7626                                          LDN_RXDMA(i));
7627                 if (err)
7628                         return err;
7629                 ldg_rotor++;
7630                 if (ldg_rotor == np->num_ldg)
7631                         ldg_rotor = 0;
7632         }
7633
7634         first_chan = 0;
7635         for (i = 0; i < port; i++)
7636                 first_chan += parent->txchan_per_port[port];
7637         num_chan = parent->txchan_per_port[port];
7638         for (i = first_chan; i < (first_chan + num_chan); i++) {
7639                 err = niu_ldg_assign_ldn(np, parent,
7640                                          ldg_num_map[ldg_rotor],
7641                                          LDN_TXDMA(i));
7642                 if (err)
7643                         return err;
7644                 ldg_rotor++;
7645                 if (ldg_rotor == np->num_ldg)
7646                         ldg_rotor = 0;
7647         }
7648
7649         return 0;
7650 }
7651
7652 static void __devexit niu_ldg_free(struct niu *np)
7653 {
7654         if (np->flags & NIU_FLAGS_MSIX)
7655                 pci_disable_msix(np->pdev);
7656 }
7657
7658 static int __devinit niu_get_of_props(struct niu *np)
7659 {
7660 #ifdef CONFIG_SPARC64
7661         struct net_device *dev = np->dev;
7662         struct device_node *dp;
7663         const char *phy_type;
7664         const u8 *mac_addr;
7665         int prop_len;
7666
7667         if (np->parent->plat_type == PLAT_TYPE_NIU)
7668                 dp = np->op->node;
7669         else
7670                 dp = pci_device_to_OF_node(np->pdev);
7671
7672         phy_type = of_get_property(dp, "phy-type", &prop_len);
7673         if (!phy_type) {
7674                 dev_err(np->device, PFX "%s: OF node lacks "
7675                         "phy-type property\n",
7676                         dp->full_name);
7677                 return -EINVAL;
7678         }
7679
7680         if (!strcmp(phy_type, "none"))
7681                 return -ENODEV;
7682
7683         strcpy(np->vpd.phy_type, phy_type);
7684
7685         if (niu_phy_type_prop_decode(np, np->vpd.phy_type)) {
7686                 dev_err(np->device, PFX "%s: Illegal phy string [%s].\n",
7687                         dp->full_name, np->vpd.phy_type);
7688                 return -EINVAL;
7689         }
7690
7691         mac_addr = of_get_property(dp, "local-mac-address", &prop_len);
7692         if (!mac_addr) {
7693                 dev_err(np->device, PFX "%s: OF node lacks "
7694                         "local-mac-address property\n",
7695                         dp->full_name);
7696                 return -EINVAL;
7697         }
7698         if (prop_len != dev->addr_len) {
7699                 dev_err(np->device, PFX "%s: OF MAC address prop len (%d) "
7700                         "is wrong.\n",
7701                         dp->full_name, prop_len);
7702         }
7703         memcpy(dev->perm_addr, mac_addr, dev->addr_len);
7704         if (!is_valid_ether_addr(&dev->perm_addr[0])) {
7705                 int i;
7706
7707                 dev_err(np->device, PFX "%s: OF MAC address is invalid\n",
7708                         dp->full_name);
7709                 dev_err(np->device, PFX "%s: [ \n",
7710                         dp->full_name);
7711                 for (i = 0; i < 6; i++)
7712                         printk("%02x ", dev->perm_addr[i]);
7713                 printk("]\n");
7714                 return -EINVAL;
7715         }
7716
7717         memcpy(dev->dev_addr, dev->perm_addr, dev->addr_len);
7718
7719         return 0;
7720 #else
7721         return -EINVAL;
7722 #endif
7723 }
7724
7725 static int __devinit niu_get_invariants(struct niu *np)
7726 {
7727         int err, have_props;
7728         u32 offset;
7729
7730         err = niu_get_of_props(np);
7731         if (err == -ENODEV)
7732                 return err;
7733
7734         have_props = !err;
7735
7736         err = niu_get_and_validate_port(np);
7737         if (err)
7738                 return err;
7739
7740         err = niu_init_mac_ipp_pcs_base(np);
7741         if (err)
7742                 return err;
7743
7744         if (!have_props) {
7745                 if (np->parent->plat_type == PLAT_TYPE_NIU)
7746                         return -EINVAL;
7747
7748                 nw64(ESPC_PIO_EN, ESPC_PIO_EN_ENABLE);
7749                 offset = niu_pci_vpd_offset(np);
7750                 niudbg(PROBE, "niu_get_invariants: VPD offset [%08x]\n",
7751                        offset);
7752                 if (offset)
7753                         niu_pci_vpd_fetch(np, offset);
7754                 nw64(ESPC_PIO_EN, 0);
7755
7756                 if (np->flags & NIU_FLAGS_VPD_VALID)
7757                         niu_pci_vpd_validate(np);
7758
7759                 if (!(np->flags & NIU_FLAGS_VPD_VALID)) {
7760                         err = niu_pci_probe_sprom(np);
7761                         if (err)
7762                                 return err;
7763                 }
7764         }
7765
7766         err = niu_probe_ports(np);
7767         if (err)
7768                 return err;
7769
7770         niu_ldg_init(np);
7771
7772         niu_classifier_swstate_init(np);
7773         niu_link_config_init(np);
7774
7775         err = niu_determine_phy_disposition(np);
7776         if (!err)
7777                 err = niu_init_link(np);
7778
7779         return err;
7780 }
7781
7782 static LIST_HEAD(niu_parent_list);
7783 static DEFINE_MUTEX(niu_parent_lock);
7784 static int niu_parent_index;
7785
7786 static ssize_t show_port_phy(struct device *dev,
7787                              struct device_attribute *attr, char *buf)
7788 {
7789         struct platform_device *plat_dev = to_platform_device(dev);
7790         struct niu_parent *p = plat_dev->dev.platform_data;
7791         u32 port_phy = p->port_phy;
7792         char *orig_buf = buf;
7793         int i;
7794
7795         if (port_phy == PORT_PHY_UNKNOWN ||
7796             port_phy == PORT_PHY_INVALID)
7797                 return 0;
7798
7799         for (i = 0; i < p->num_ports; i++) {
7800                 const char *type_str;
7801                 int type;
7802
7803                 type = phy_decode(port_phy, i);
7804                 if (type == PORT_TYPE_10G)
7805                         type_str = "10G";
7806                 else
7807                         type_str = "1G";
7808                 buf += sprintf(buf,
7809                                (i == 0) ? "%s" : " %s",
7810                                type_str);
7811         }
7812         buf += sprintf(buf, "\n");
7813         return buf - orig_buf;
7814 }
7815
7816 static ssize_t show_plat_type(struct device *dev,
7817                               struct device_attribute *attr, char *buf)
7818 {
7819         struct platform_device *plat_dev = to_platform_device(dev);
7820         struct niu_parent *p = plat_dev->dev.platform_data;
7821         const char *type_str;
7822
7823         switch (p->plat_type) {
7824         case PLAT_TYPE_ATLAS:
7825                 type_str = "atlas";
7826                 break;
7827         case PLAT_TYPE_NIU:
7828                 type_str = "niu";
7829                 break;
7830         case PLAT_TYPE_VF_P0:
7831                 type_str = "vf_p0";
7832                 break;
7833         case PLAT_TYPE_VF_P1:
7834                 type_str = "vf_p1";
7835                 break;
7836         default:
7837                 type_str = "unknown";
7838                 break;
7839         }
7840
7841         return sprintf(buf, "%s\n", type_str);
7842 }
7843
7844 static ssize_t __show_chan_per_port(struct device *dev,
7845                                     struct device_attribute *attr, char *buf,
7846                                     int rx)
7847 {
7848         struct platform_device *plat_dev = to_platform_device(dev);
7849         struct niu_parent *p = plat_dev->dev.platform_data;
7850         char *orig_buf = buf;
7851         u8 *arr;
7852         int i;
7853
7854         arr = (rx ? p->rxchan_per_port : p->txchan_per_port);
7855
7856         for (i = 0; i < p->num_ports; i++) {
7857                 buf += sprintf(buf,
7858                                (i == 0) ? "%d" : " %d",
7859                                arr[i]);
7860         }
7861         buf += sprintf(buf, "\n");
7862
7863         return buf - orig_buf;
7864 }
7865
7866 static ssize_t show_rxchan_per_port(struct device *dev,
7867                                     struct device_attribute *attr, char *buf)
7868 {
7869         return __show_chan_per_port(dev, attr, buf, 1);
7870 }
7871
7872 static ssize_t show_txchan_per_port(struct device *dev,
7873                                     struct device_attribute *attr, char *buf)
7874 {
7875         return __show_chan_per_port(dev, attr, buf, 1);
7876 }
7877
7878 static ssize_t show_num_ports(struct device *dev,
7879                               struct device_attribute *attr, char *buf)
7880 {
7881         struct platform_device *plat_dev = to_platform_device(dev);
7882         struct niu_parent *p = plat_dev->dev.platform_data;
7883
7884         return sprintf(buf, "%d\n", p->num_ports);
7885 }
7886
7887 static struct device_attribute niu_parent_attributes[] = {
7888         __ATTR(port_phy, S_IRUGO, show_port_phy, NULL),
7889         __ATTR(plat_type, S_IRUGO, show_plat_type, NULL),
7890         __ATTR(rxchan_per_port, S_IRUGO, show_rxchan_per_port, NULL),
7891         __ATTR(txchan_per_port, S_IRUGO, show_txchan_per_port, NULL),
7892         __ATTR(num_ports, S_IRUGO, show_num_ports, NULL),
7893         {}
7894 };
7895
7896 static struct niu_parent * __devinit niu_new_parent(struct niu *np,
7897                                                     union niu_parent_id *id,
7898                                                     u8 ptype)
7899 {
7900         struct platform_device *plat_dev;
7901         struct niu_parent *p;
7902         int i;
7903
7904         niudbg(PROBE, "niu_new_parent: Creating new parent.\n");
7905
7906         plat_dev = platform_device_register_simple("niu", niu_parent_index,
7907                                                    NULL, 0);
7908         if (!plat_dev)
7909                 return NULL;
7910
7911         for (i = 0; attr_name(niu_parent_attributes[i]); i++) {
7912                 int err = device_create_file(&plat_dev->dev,
7913                                              &niu_parent_attributes[i]);
7914                 if (err)
7915                         goto fail_unregister;
7916         }
7917
7918         p = kzalloc(sizeof(*p), GFP_KERNEL);
7919         if (!p)
7920                 goto fail_unregister;
7921
7922         p->index = niu_parent_index++;
7923
7924         plat_dev->dev.platform_data = p;
7925         p->plat_dev = plat_dev;
7926
7927         memcpy(&p->id, id, sizeof(*id));
7928         p->plat_type = ptype;
7929         INIT_LIST_HEAD(&p->list);
7930         atomic_set(&p->refcnt, 0);
7931         list_add(&p->list, &niu_parent_list);
7932         spin_lock_init(&p->lock);
7933
7934         p->rxdma_clock_divider = 7500;
7935
7936         p->tcam_num_entries = NIU_PCI_TCAM_ENTRIES;
7937         if (p->plat_type == PLAT_TYPE_NIU)
7938                 p->tcam_num_entries = NIU_NONPCI_TCAM_ENTRIES;
7939
7940         for (i = CLASS_CODE_USER_PROG1; i <= CLASS_CODE_SCTP_IPV6; i++) {
7941                 int index = i - CLASS_CODE_USER_PROG1;
7942
7943                 p->tcam_key[index] = TCAM_KEY_TSEL;
7944                 p->flow_key[index] = (FLOW_KEY_IPSA |
7945                                       FLOW_KEY_IPDA |
7946                                       FLOW_KEY_PROTO |
7947                                       (FLOW_KEY_L4_BYTE12 <<
7948                                        FLOW_KEY_L4_0_SHIFT) |
7949                                       (FLOW_KEY_L4_BYTE12 <<
7950                                        FLOW_KEY_L4_1_SHIFT));
7951         }
7952
7953         for (i = 0; i < LDN_MAX + 1; i++)
7954                 p->ldg_map[i] = LDG_INVALID;
7955
7956         return p;
7957
7958 fail_unregister:
7959         platform_device_unregister(plat_dev);
7960         return NULL;
7961 }
7962
7963 static struct niu_parent * __devinit niu_get_parent(struct niu *np,
7964                                                     union niu_parent_id *id,
7965                                                     u8 ptype)
7966 {
7967         struct niu_parent *p, *tmp;
7968         int port = np->port;
7969
7970         niudbg(PROBE, "niu_get_parent: platform_type[%u] port[%u]\n",
7971                ptype, port);
7972
7973         mutex_lock(&niu_parent_lock);
7974         p = NULL;
7975         list_for_each_entry(tmp, &niu_parent_list, list) {
7976                 if (!memcmp(id, &tmp->id, sizeof(*id))) {
7977                         p = tmp;
7978                         break;
7979                 }
7980         }
7981         if (!p)
7982                 p = niu_new_parent(np, id, ptype);
7983
7984         if (p) {
7985                 char port_name[6];
7986                 int err;
7987
7988                 sprintf(port_name, "port%d", port);
7989                 err = sysfs_create_link(&p->plat_dev->dev.kobj,
7990                                         &np->device->kobj,
7991                                         port_name);
7992                 if (!err) {
7993                         p->ports[port] = np;
7994                         atomic_inc(&p->refcnt);
7995                 }
7996         }
7997         mutex_unlock(&niu_parent_lock);
7998
7999         return p;
8000 }
8001
8002 static void niu_put_parent(struct niu *np)
8003 {
8004         struct niu_parent *p = np->parent;
8005         u8 port = np->port;
8006         char port_name[6];
8007
8008         BUG_ON(!p || p->ports[port] != np);
8009
8010         niudbg(PROBE, "niu_put_parent: port[%u]\n", port);
8011
8012         sprintf(port_name, "port%d", port);
8013
8014         mutex_lock(&niu_parent_lock);
8015
8016         sysfs_remove_link(&p->plat_dev->dev.kobj, port_name);
8017
8018         p->ports[port] = NULL;
8019         np->parent = NULL;
8020
8021         if (atomic_dec_and_test(&p->refcnt)) {
8022                 list_del(&p->list);
8023                 platform_device_unregister(p->plat_dev);
8024         }
8025
8026         mutex_unlock(&niu_parent_lock);
8027 }
8028
8029 static void *niu_pci_alloc_coherent(struct device *dev, size_t size,
8030                                     u64 *handle, gfp_t flag)
8031 {
8032         dma_addr_t dh;
8033         void *ret;
8034
8035         ret = dma_alloc_coherent(dev, size, &dh, flag);
8036         if (ret)
8037                 *handle = dh;
8038         return ret;
8039 }
8040
8041 static void niu_pci_free_coherent(struct device *dev, size_t size,
8042                                   void *cpu_addr, u64 handle)
8043 {
8044         dma_free_coherent(dev, size, cpu_addr, handle);
8045 }
8046
8047 static u64 niu_pci_map_page(struct device *dev, struct page *page,
8048                             unsigned long offset, size_t size,
8049                             enum dma_data_direction direction)
8050 {
8051         return dma_map_page(dev, page, offset, size, direction);
8052 }
8053
8054 static void niu_pci_unmap_page(struct device *dev, u64 dma_address,
8055                                size_t size, enum dma_data_direction direction)
8056 {
8057         return dma_unmap_page(dev, dma_address, size, direction);
8058 }
8059
8060 static u64 niu_pci_map_single(struct device *dev, void *cpu_addr,
8061                               size_t size,
8062                               enum dma_data_direction direction)
8063 {
8064         return dma_map_single(dev, cpu_addr, size, direction);
8065 }
8066
8067 static void niu_pci_unmap_single(struct device *dev, u64 dma_address,
8068                                  size_t size,
8069                                  enum dma_data_direction direction)
8070 {
8071         dma_unmap_single(dev, dma_address, size, direction);
8072 }
8073
8074 static const struct niu_ops niu_pci_ops = {
8075         .alloc_coherent = niu_pci_alloc_coherent,
8076         .free_coherent  = niu_pci_free_coherent,
8077         .map_page       = niu_pci_map_page,
8078         .unmap_page     = niu_pci_unmap_page,
8079         .map_single     = niu_pci_map_single,
8080         .unmap_single   = niu_pci_unmap_single,
8081 };
8082
8083 static void __devinit niu_driver_version(void)
8084 {
8085         static int niu_version_printed;
8086
8087         if (niu_version_printed++ == 0)
8088                 pr_info("%s", version);
8089 }
8090
8091 static struct net_device * __devinit niu_alloc_and_init(
8092         struct device *gen_dev, struct pci_dev *pdev,
8093         struct of_device *op, const struct niu_ops *ops,
8094         u8 port)
8095 {
8096         struct net_device *dev = alloc_etherdev(sizeof(struct niu));
8097         struct niu *np;
8098
8099         if (!dev) {
8100                 dev_err(gen_dev, PFX "Etherdev alloc failed, aborting.\n");
8101                 return NULL;
8102         }
8103
8104         SET_NETDEV_DEV(dev, gen_dev);
8105
8106         np = netdev_priv(dev);
8107         np->dev = dev;
8108         np->pdev = pdev;
8109         np->op = op;
8110         np->device = gen_dev;
8111         np->ops = ops;
8112
8113         np->msg_enable = niu_debug;
8114
8115         spin_lock_init(&np->lock);
8116         INIT_WORK(&np->reset_task, niu_reset_task);
8117
8118         np->port = port;
8119
8120         return dev;
8121 }
8122
8123 static void __devinit niu_assign_netdev_ops(struct net_device *dev)
8124 {
8125         dev->open = niu_open;
8126         dev->stop = niu_close;
8127         dev->get_stats = niu_get_stats;
8128         dev->set_multicast_list = niu_set_rx_mode;
8129         dev->set_mac_address = niu_set_mac_addr;
8130         dev->do_ioctl = niu_ioctl;
8131         dev->tx_timeout = niu_tx_timeout;
8132         dev->hard_start_xmit = niu_start_xmit;
8133         dev->ethtool_ops = &niu_ethtool_ops;
8134         dev->watchdog_timeo = NIU_TX_TIMEOUT;
8135         dev->change_mtu = niu_change_mtu;
8136 }
8137
8138 static void __devinit niu_device_announce(struct niu *np)
8139 {
8140         struct net_device *dev = np->dev;
8141         DECLARE_MAC_BUF(mac);
8142
8143         pr_info("%s: NIU Ethernet %s\n",
8144                 dev->name, print_mac(mac, dev->dev_addr));
8145
8146         if (np->parent->plat_type == PLAT_TYPE_ATCA_CP3220) {
8147                 pr_info("%s: Port type[%s] mode[%s:%s] XCVR[%s] phy[%s]\n",
8148                                 dev->name,
8149                                 (np->flags & NIU_FLAGS_XMAC ? "XMAC" : "BMAC"),
8150                                 (np->flags & NIU_FLAGS_10G ? "10G" : "1G"),
8151                                 (np->flags & NIU_FLAGS_FIBER ? "RGMII FIBER" : "SERDES"),
8152                                 (np->mac_xcvr == MAC_XCVR_MII ? "MII" :
8153                                  (np->mac_xcvr == MAC_XCVR_PCS ? "PCS" : "XPCS")),
8154                                 np->vpd.phy_type);
8155         } else {
8156                 pr_info("%s: Port type[%s] mode[%s:%s] XCVR[%s] phy[%s]\n",
8157                                 dev->name,
8158                                 (np->flags & NIU_FLAGS_XMAC ? "XMAC" : "BMAC"),
8159                                 (np->flags & NIU_FLAGS_10G ? "10G" : "1G"),
8160                                 (np->flags & NIU_FLAGS_FIBER ? "FIBER" : "COPPER"),
8161                                 (np->mac_xcvr == MAC_XCVR_MII ? "MII" :
8162                                  (np->mac_xcvr == MAC_XCVR_PCS ? "PCS" : "XPCS")),
8163                                 np->vpd.phy_type);
8164         }
8165 }
8166
8167 static int __devinit niu_pci_init_one(struct pci_dev *pdev,
8168                                       const struct pci_device_id *ent)
8169 {
8170         unsigned long niureg_base, niureg_len;
8171         union niu_parent_id parent_id;
8172         struct net_device *dev;
8173         struct niu *np;
8174         int err, pos;
8175         u64 dma_mask;
8176         u16 val16;
8177
8178         niu_driver_version();
8179
8180         err = pci_enable_device(pdev);
8181         if (err) {
8182                 dev_err(&pdev->dev, PFX "Cannot enable PCI device, "
8183                         "aborting.\n");
8184                 return err;
8185         }
8186
8187         if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM) ||
8188             !(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
8189                 dev_err(&pdev->dev, PFX "Cannot find proper PCI device "
8190                         "base addresses, aborting.\n");
8191                 err = -ENODEV;
8192                 goto err_out_disable_pdev;
8193         }
8194
8195         err = pci_request_regions(pdev, DRV_MODULE_NAME);
8196         if (err) {
8197                 dev_err(&pdev->dev, PFX "Cannot obtain PCI resources, "
8198                         "aborting.\n");
8199                 goto err_out_disable_pdev;
8200         }
8201
8202         pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
8203         if (pos <= 0) {
8204                 dev_err(&pdev->dev, PFX "Cannot find PCI Express capability, "
8205                         "aborting.\n");
8206                 goto err_out_free_res;
8207         }
8208
8209         dev = niu_alloc_and_init(&pdev->dev, pdev, NULL,
8210                                  &niu_pci_ops, PCI_FUNC(pdev->devfn));
8211         if (!dev) {
8212                 err = -ENOMEM;
8213                 goto err_out_free_res;
8214         }
8215         np = netdev_priv(dev);
8216
8217         memset(&parent_id, 0, sizeof(parent_id));
8218         parent_id.pci.domain = pci_domain_nr(pdev->bus);
8219         parent_id.pci.bus = pdev->bus->number;
8220         parent_id.pci.device = PCI_SLOT(pdev->devfn);
8221
8222         np->parent = niu_get_parent(np, &parent_id,
8223                                     PLAT_TYPE_ATLAS);
8224         if (!np->parent) {
8225                 err = -ENOMEM;
8226                 goto err_out_free_dev;
8227         }
8228
8229         pci_read_config_word(pdev, pos + PCI_EXP_DEVCTL, &val16);
8230         val16 &= ~PCI_EXP_DEVCTL_NOSNOOP_EN;
8231         val16 |= (PCI_EXP_DEVCTL_CERE |
8232                   PCI_EXP_DEVCTL_NFERE |
8233                   PCI_EXP_DEVCTL_FERE |
8234                   PCI_EXP_DEVCTL_URRE |
8235                   PCI_EXP_DEVCTL_RELAX_EN);
8236         pci_write_config_word(pdev, pos + PCI_EXP_DEVCTL, val16);
8237
8238         dma_mask = DMA_44BIT_MASK;
8239         err = pci_set_dma_mask(pdev, dma_mask);
8240         if (!err) {
8241                 dev->features |= NETIF_F_HIGHDMA;
8242                 err = pci_set_consistent_dma_mask(pdev, dma_mask);
8243                 if (err) {
8244                         dev_err(&pdev->dev, PFX "Unable to obtain 44 bit "
8245                                 "DMA for consistent allocations, "
8246                                 "aborting.\n");
8247                         goto err_out_release_parent;
8248                 }
8249         }
8250         if (err || dma_mask == DMA_32BIT_MASK) {
8251                 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
8252                 if (err) {
8253                         dev_err(&pdev->dev, PFX "No usable DMA configuration, "
8254                                 "aborting.\n");
8255                         goto err_out_release_parent;
8256                 }
8257         }
8258
8259         dev->features |= (NETIF_F_SG | NETIF_F_HW_CSUM);
8260
8261         niureg_base = pci_resource_start(pdev, 0);
8262         niureg_len = pci_resource_len(pdev, 0);
8263
8264         np->regs = ioremap_nocache(niureg_base, niureg_len);
8265         if (!np->regs) {
8266                 dev_err(&pdev->dev, PFX "Cannot map device registers, "
8267                         "aborting.\n");
8268                 err = -ENOMEM;
8269                 goto err_out_release_parent;
8270         }
8271
8272         pci_set_master(pdev);
8273         pci_save_state(pdev);
8274
8275         dev->irq = pdev->irq;
8276
8277         niu_assign_netdev_ops(dev);
8278
8279         err = niu_get_invariants(np);
8280         if (err) {
8281                 if (err != -ENODEV)
8282                         dev_err(&pdev->dev, PFX "Problem fetching invariants "
8283                                 "of chip, aborting.\n");
8284                 goto err_out_iounmap;
8285         }
8286
8287         err = register_netdev(dev);
8288         if (err) {
8289                 dev_err(&pdev->dev, PFX "Cannot register net device, "
8290                         "aborting.\n");
8291                 goto err_out_iounmap;
8292         }
8293
8294         pci_set_drvdata(pdev, dev);
8295
8296         niu_device_announce(np);
8297
8298         return 0;
8299
8300 err_out_iounmap:
8301         if (np->regs) {
8302                 iounmap(np->regs);
8303                 np->regs = NULL;
8304         }
8305
8306 err_out_release_parent:
8307         niu_put_parent(np);
8308
8309 err_out_free_dev:
8310         free_netdev(dev);
8311
8312 err_out_free_res:
8313         pci_release_regions(pdev);
8314
8315 err_out_disable_pdev:
8316         pci_disable_device(pdev);
8317         pci_set_drvdata(pdev, NULL);
8318
8319         return err;
8320 }
8321
8322 static void __devexit niu_pci_remove_one(struct pci_dev *pdev)
8323 {
8324         struct net_device *dev = pci_get_drvdata(pdev);
8325
8326         if (dev) {
8327                 struct niu *np = netdev_priv(dev);
8328
8329                 unregister_netdev(dev);
8330                 if (np->regs) {
8331                         iounmap(np->regs);
8332                         np->regs = NULL;
8333                 }
8334
8335                 niu_ldg_free(np);
8336
8337                 niu_put_parent(np);
8338
8339                 free_netdev(dev);
8340                 pci_release_regions(pdev);
8341                 pci_disable_device(pdev);
8342                 pci_set_drvdata(pdev, NULL);
8343         }
8344 }
8345
8346 static int niu_suspend(struct pci_dev *pdev, pm_message_t state)
8347 {
8348         struct net_device *dev = pci_get_drvdata(pdev);
8349         struct niu *np = netdev_priv(dev);
8350         unsigned long flags;
8351
8352         if (!netif_running(dev))
8353                 return 0;
8354
8355         flush_scheduled_work();
8356         niu_netif_stop(np);
8357
8358         del_timer_sync(&np->timer);
8359
8360         spin_lock_irqsave(&np->lock, flags);
8361         niu_enable_interrupts(np, 0);
8362         spin_unlock_irqrestore(&np->lock, flags);
8363
8364         netif_device_detach(dev);
8365
8366         spin_lock_irqsave(&np->lock, flags);
8367         niu_stop_hw(np);
8368         spin_unlock_irqrestore(&np->lock, flags);
8369
8370         pci_save_state(pdev);
8371
8372         return 0;
8373 }
8374
8375 static int niu_resume(struct pci_dev *pdev)
8376 {
8377         struct net_device *dev = pci_get_drvdata(pdev);
8378         struct niu *np = netdev_priv(dev);
8379         unsigned long flags;
8380         int err;
8381
8382         if (!netif_running(dev))
8383                 return 0;
8384
8385         pci_restore_state(pdev);
8386
8387         netif_device_attach(dev);
8388
8389         spin_lock_irqsave(&np->lock, flags);
8390
8391         err = niu_init_hw(np);
8392         if (!err) {
8393                 np->timer.expires = jiffies + HZ;
8394                 add_timer(&np->timer);
8395                 niu_netif_start(np);
8396         }
8397
8398         spin_unlock_irqrestore(&np->lock, flags);
8399
8400         return err;
8401 }
8402
8403 static struct pci_driver niu_pci_driver = {
8404         .name           = DRV_MODULE_NAME,
8405         .id_table       = niu_pci_tbl,
8406         .probe          = niu_pci_init_one,
8407         .remove         = __devexit_p(niu_pci_remove_one),
8408         .suspend        = niu_suspend,
8409         .resume         = niu_resume,
8410 };
8411
8412 #ifdef CONFIG_SPARC64
8413 static void *niu_phys_alloc_coherent(struct device *dev, size_t size,
8414                                      u64 *dma_addr, gfp_t flag)
8415 {
8416         unsigned long order = get_order(size);
8417         unsigned long page = __get_free_pages(flag, order);
8418
8419         if (page == 0UL)
8420                 return NULL;
8421         memset((char *)page, 0, PAGE_SIZE << order);
8422         *dma_addr = __pa(page);
8423
8424         return (void *) page;
8425 }
8426
8427 static void niu_phys_free_coherent(struct device *dev, size_t size,
8428                                    void *cpu_addr, u64 handle)
8429 {
8430         unsigned long order = get_order(size);
8431
8432         free_pages((unsigned long) cpu_addr, order);
8433 }
8434
8435 static u64 niu_phys_map_page(struct device *dev, struct page *page,
8436                              unsigned long offset, size_t size,
8437                              enum dma_data_direction direction)
8438 {
8439         return page_to_phys(page) + offset;
8440 }
8441
8442 static void niu_phys_unmap_page(struct device *dev, u64 dma_address,
8443                                 size_t size, enum dma_data_direction direction)
8444 {
8445         /* Nothing to do.  */
8446 }
8447
8448 static u64 niu_phys_map_single(struct device *dev, void *cpu_addr,
8449                                size_t size,
8450                                enum dma_data_direction direction)
8451 {
8452         return __pa(cpu_addr);
8453 }
8454
8455 static void niu_phys_unmap_single(struct device *dev, u64 dma_address,
8456                                   size_t size,
8457                                   enum dma_data_direction direction)
8458 {
8459         /* Nothing to do.  */
8460 }
8461
8462 static const struct niu_ops niu_phys_ops = {
8463         .alloc_coherent = niu_phys_alloc_coherent,
8464         .free_coherent  = niu_phys_free_coherent,
8465         .map_page       = niu_phys_map_page,
8466         .unmap_page     = niu_phys_unmap_page,
8467         .map_single     = niu_phys_map_single,
8468         .unmap_single   = niu_phys_unmap_single,
8469 };
8470
8471 static unsigned long res_size(struct resource *r)
8472 {
8473         return r->end - r->start + 1UL;
8474 }
8475
8476 static int __devinit niu_of_probe(struct of_device *op,
8477                                   const struct of_device_id *match)
8478 {
8479         union niu_parent_id parent_id;
8480         struct net_device *dev;
8481         struct niu *np;
8482         const u32 *reg;
8483         int err;
8484
8485         niu_driver_version();
8486
8487         reg = of_get_property(op->node, "reg", NULL);
8488         if (!reg) {
8489                 dev_err(&op->dev, PFX "%s: No 'reg' property, aborting.\n",
8490                         op->node->full_name);
8491                 return -ENODEV;
8492         }
8493
8494         dev = niu_alloc_and_init(&op->dev, NULL, op,
8495                                  &niu_phys_ops, reg[0] & 0x1);
8496         if (!dev) {
8497                 err = -ENOMEM;
8498                 goto err_out;
8499         }
8500         np = netdev_priv(dev);
8501
8502         memset(&parent_id, 0, sizeof(parent_id));
8503         parent_id.of = of_get_parent(op->node);
8504
8505         np->parent = niu_get_parent(np, &parent_id,
8506                                     PLAT_TYPE_NIU);
8507         if (!np->parent) {
8508                 err = -ENOMEM;
8509                 goto err_out_free_dev;
8510         }
8511
8512         dev->features |= (NETIF_F_SG | NETIF_F_HW_CSUM);
8513
8514         np->regs = of_ioremap(&op->resource[1], 0,
8515                               res_size(&op->resource[1]),
8516                               "niu regs");
8517         if (!np->regs) {
8518                 dev_err(&op->dev, PFX "Cannot map device registers, "
8519                         "aborting.\n");
8520                 err = -ENOMEM;
8521                 goto err_out_release_parent;
8522         }
8523
8524         np->vir_regs_1 = of_ioremap(&op->resource[2], 0,
8525                                     res_size(&op->resource[2]),
8526                                     "niu vregs-1");
8527         if (!np->vir_regs_1) {
8528                 dev_err(&op->dev, PFX "Cannot map device vir registers 1, "
8529                         "aborting.\n");
8530                 err = -ENOMEM;
8531                 goto err_out_iounmap;
8532         }
8533
8534         np->vir_regs_2 = of_ioremap(&op->resource[3], 0,
8535                                     res_size(&op->resource[3]),
8536                                     "niu vregs-2");
8537         if (!np->vir_regs_2) {
8538                 dev_err(&op->dev, PFX "Cannot map device vir registers 2, "
8539                         "aborting.\n");
8540                 err = -ENOMEM;
8541                 goto err_out_iounmap;
8542         }
8543
8544         niu_assign_netdev_ops(dev);
8545
8546         err = niu_get_invariants(np);
8547         if (err) {
8548                 if (err != -ENODEV)
8549                         dev_err(&op->dev, PFX "Problem fetching invariants "
8550                                 "of chip, aborting.\n");
8551                 goto err_out_iounmap;
8552         }
8553
8554         err = register_netdev(dev);
8555         if (err) {
8556                 dev_err(&op->dev, PFX "Cannot register net device, "
8557                         "aborting.\n");
8558                 goto err_out_iounmap;
8559         }
8560
8561         dev_set_drvdata(&op->dev, dev);
8562
8563         niu_device_announce(np);
8564
8565         return 0;
8566
8567 err_out_iounmap:
8568         if (np->vir_regs_1) {
8569                 of_iounmap(&op->resource[2], np->vir_regs_1,
8570                            res_size(&op->resource[2]));
8571                 np->vir_regs_1 = NULL;
8572         }
8573
8574         if (np->vir_regs_2) {
8575                 of_iounmap(&op->resource[3], np->vir_regs_2,
8576                            res_size(&op->resource[3]));
8577                 np->vir_regs_2 = NULL;
8578         }
8579
8580         if (np->regs) {
8581                 of_iounmap(&op->resource[1], np->regs,
8582                            res_size(&op->resource[1]));
8583                 np->regs = NULL;
8584         }
8585
8586 err_out_release_parent:
8587         niu_put_parent(np);
8588
8589 err_out_free_dev:
8590         free_netdev(dev);
8591
8592 err_out:
8593         return err;
8594 }
8595
8596 static int __devexit niu_of_remove(struct of_device *op)
8597 {
8598         struct net_device *dev = dev_get_drvdata(&op->dev);
8599
8600         if (dev) {
8601                 struct niu *np = netdev_priv(dev);
8602
8603                 unregister_netdev(dev);
8604
8605                 if (np->vir_regs_1) {
8606                         of_iounmap(&op->resource[2], np->vir_regs_1,
8607                                    res_size(&op->resource[2]));
8608                         np->vir_regs_1 = NULL;
8609                 }
8610
8611                 if (np->vir_regs_2) {
8612                         of_iounmap(&op->resource[3], np->vir_regs_2,
8613                                    res_size(&op->resource[3]));
8614                         np->vir_regs_2 = NULL;
8615                 }
8616
8617                 if (np->regs) {
8618                         of_iounmap(&op->resource[1], np->regs,
8619                                    res_size(&op->resource[1]));
8620                         np->regs = NULL;
8621                 }
8622
8623                 niu_ldg_free(np);
8624
8625                 niu_put_parent(np);
8626
8627                 free_netdev(dev);
8628                 dev_set_drvdata(&op->dev, NULL);
8629         }
8630         return 0;
8631 }
8632
8633 static struct of_device_id niu_match[] = {
8634         {
8635                 .name = "network",
8636                 .compatible = "SUNW,niusl",
8637         },
8638         {},
8639 };
8640 MODULE_DEVICE_TABLE(of, niu_match);
8641
8642 static struct of_platform_driver niu_of_driver = {
8643         .name           = "niu",
8644         .match_table    = niu_match,
8645         .probe          = niu_of_probe,
8646         .remove         = __devexit_p(niu_of_remove),
8647 };
8648
8649 #endif /* CONFIG_SPARC64 */
8650
8651 static int __init niu_init(void)
8652 {
8653         int err = 0;
8654
8655         BUILD_BUG_ON(PAGE_SIZE < 4 * 1024);
8656
8657         niu_debug = netif_msg_init(debug, NIU_MSG_DEFAULT);
8658
8659 #ifdef CONFIG_SPARC64
8660         err = of_register_driver(&niu_of_driver, &of_bus_type);
8661 #endif
8662
8663         if (!err) {
8664                 err = pci_register_driver(&niu_pci_driver);
8665 #ifdef CONFIG_SPARC64
8666                 if (err)
8667                         of_unregister_driver(&niu_of_driver);
8668 #endif
8669         }
8670
8671         return err;
8672 }
8673
8674 static void __exit niu_exit(void)
8675 {
8676         pci_unregister_driver(&niu_pci_driver);
8677 #ifdef CONFIG_SPARC64
8678         of_unregister_driver(&niu_of_driver);
8679 #endif
8680 }
8681
8682 module_init(niu_init);
8683 module_exit(niu_exit);