drivers/net/qlge/qlge_main.c

   1 /*
   2  * QLogic qlge NIC HBA Driver
   3  * Copyright (c)  2003-2008 QLogic Corporation
   4  * See LICENSE.qlge for copyright and licensing details.
   5  * Author:     Linux qlge network device driver by
   6  *                      Ron Mercer <ron.mercer@qlogic.com>
   7  */
   8 #include <linux/kernel.h>
   9 #include <linux/init.h>
  10 #include <linux/types.h>
  11 #include <linux/module.h>
  12 #include <linux/list.h>
  13 #include <linux/pci.h>
  14 #include <linux/dma-mapping.h>
  15 #include <linux/pagemap.h>
  16 #include <linux/sched.h>
  17 #include <linux/slab.h>
  18 #include <linux/dmapool.h>
  19 #include <linux/mempool.h>
  20 #include <linux/spinlock.h>
  21 #include <linux/kthread.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/errno.h>
  24 #include <linux/ioport.h>
  25 #include <linux/in.h>
  26 #include <linux/ip.h>
  27 #include <linux/ipv6.h>
  28 #include <net/ipv6.h>
  29 #include <linux/tcp.h>
  30 #include <linux/udp.h>
  31 #include <linux/if_arp.h>
  32 #include <linux/if_ether.h>
  33 #include <linux/netdevice.h>
  34 #include <linux/etherdevice.h>
  35 #include <linux/ethtool.h>
  36 #include <linux/skbuff.h>
  37 #include <linux/rtnetlink.h>
  38 #include <linux/if_vlan.h>
  39 #include <linux/delay.h>
  40 #include <linux/mm.h>
  41 #include <linux/vmalloc.h>
  42 #include <net/ip6_checksum.h>
  43
  44 #include "qlge.h"
  45
  46 char qlge_driver_name[] = DRV_NAME;
  47 const char qlge_driver_version[] = DRV_VERSION;
  48
  49 MODULE_AUTHOR("Ron Mercer <ron.mercer@qlogic.com>");
  50 MODULE_DESCRIPTION(DRV_STRING " ");
  51 MODULE_LICENSE("GPL");
  52 MODULE_VERSION(DRV_VERSION);
  53
  54 static const u32 default_msg =
  55     NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK |
  56 /* NETIF_MSG_TIMER |    */
  57     NETIF_MSG_IFDOWN |
  58     NETIF_MSG_IFUP |
  59     NETIF_MSG_RX_ERR |
  60     NETIF_MSG_TX_ERR |
  61     NETIF_MSG_TX_QUEUED |
  62     NETIF_MSG_INTR | NETIF_MSG_TX_DONE | NETIF_MSG_RX_STATUS |
  63 /* NETIF_MSG_PKTDATA | */
  64     NETIF_MSG_HW | NETIF_MSG_WOL | 0;
  65
  66 static int debug = 0x00007fff;  /* defaults above */
  67 module_param(debug, int, 0);
  68 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
  69
  70 #define MSIX_IRQ 0
  71 #define MSI_IRQ 1
  72 #define LEG_IRQ 2
  73 static int irq_type = MSIX_IRQ;
  74 module_param(irq_type, int, MSIX_IRQ);
  75 MODULE_PARM_DESC(irq_type, "0 = MSI-X, 1 = MSI, 2 = Legacy.");
  76
  77 static struct pci_device_id qlge_pci_tbl[] __devinitdata = {
  78         {PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, QLGE_DEVICE_ID)},
  79         /* required last entry */
  80         {0,}
  81 };
  82
  83 MODULE_DEVICE_TABLE(pci, qlge_pci_tbl);
  84
  85 /* This hardware semaphore causes exclusive access to
  86  * resources shared between the NIC driver, MPI firmware,
  87  * FCOE firmware and the FC driver.
  88  */
  89 static int ql_sem_trylock(struct ql_adapter *qdev, u32 sem_mask)
  90 {
  91         u32 sem_bits = 0;
  92
  93         switch (sem_mask) {
  94         case SEM_XGMAC0_MASK:
  95                 sem_bits = SEM_SET << SEM_XGMAC0_SHIFT;
  96                 break;
  97         case SEM_XGMAC1_MASK:
  98                 sem_bits = SEM_SET << SEM_XGMAC1_SHIFT;
  99                 break;
 100         case SEM_ICB_MASK:
 101                 sem_bits = SEM_SET << SEM_ICB_SHIFT;
 102                 break;
 103         case SEM_MAC_ADDR_MASK:
 104                 sem_bits = SEM_SET << SEM_MAC_ADDR_SHIFT;
 105                 break;
 106         case SEM_FLASH_MASK:
 107                 sem_bits = SEM_SET << SEM_FLASH_SHIFT;
 108                 break;
 109         case SEM_PROBE_MASK:
 110                 sem_bits = SEM_SET << SEM_PROBE_SHIFT;
 111                 break;
 112         case SEM_RT_IDX_MASK:
 113                 sem_bits = SEM_SET << SEM_RT_IDX_SHIFT;
 114                 break;
 115         case SEM_PROC_REG_MASK:
 116                 sem_bits = SEM_SET << SEM_PROC_REG_SHIFT;
 117                 break;
 118         default:
 119                 QPRINTK(qdev, PROBE, ALERT, "Bad Semaphore mask!.\n");
 120                 return -EINVAL;
 121         }
 122
 123         ql_write32(qdev, SEM, sem_bits | sem_mask);
 124         return !(ql_read32(qdev, SEM) & sem_bits);
 125 }
 126
 127 int ql_sem_spinlock(struct ql_adapter *qdev, u32 sem_mask)
 128 {
 129         unsigned int wait_count = 30;
 130         do {
 131                 if (!ql_sem_trylock(qdev, sem_mask))
 132                         return 0;
 133                 udelay(100);
 134         } while (--wait_count);
 135         return -ETIMEDOUT;
 136 }
 137
 138 void ql_sem_unlock(struct ql_adapter *qdev, u32 sem_mask)
 139 {
 140         ql_write32(qdev, SEM, sem_mask);
 141         ql_read32(qdev, SEM);   /* flush */
 142 }
 143
 144 /* This function waits for a specific bit to come ready
 145  * in a given register.  It is used mostly by the initialize
 146  * process, but is also used in kernel thread API such as
 147  * netdev->set_multi, netdev->set_mac_address, netdev->vlan_rx_add_vid.
 148  */
 149 int ql_wait_reg_rdy(struct ql_adapter *qdev, u32 reg, u32 bit, u32 err_bit)
 150 {
 151         u32 temp;
 152         int count = UDELAY_COUNT;
 153
 154         while (count) {
 155                 temp = ql_read32(qdev, reg);
 156
 157                 /* check for errors */
 158                 if (temp & err_bit) {
 159                         QPRINTK(qdev, PROBE, ALERT,
 160                                 "register 0x%.08x access error, value = 0x%.08x!.\n",
 161                                 reg, temp);
 162                         return -EIO;
 163                 } else if (temp & bit)
 164                         return 0;
 165                 udelay(UDELAY_DELAY);
 166                 count--;
 167         }
 168         QPRINTK(qdev, PROBE, ALERT,
 169                 "Timed out waiting for reg %x to come ready.\n", reg);
 170         return -ETIMEDOUT;
 171 }
 172
 173 /* The CFG register is used to download TX and RX control blocks
 174  * to the chip. This function waits for an operation to complete.
 175  */
 176 static int ql_wait_cfg(struct ql_adapter *qdev, u32 bit)
 177 {
 178         int count = UDELAY_COUNT;
 179         u32 temp;
 180
 181         while (count) {
 182                 temp = ql_read32(qdev, CFG);
 183                 if (temp & CFG_LE)
 184                         return -EIO;
 185                 if (!(temp & bit))
 186                         return 0;
 187                 udelay(UDELAY_DELAY);
 188                 count--;
 189         }
 190         return -ETIMEDOUT;
 191 }
 192
 193
 194 /* Used to issue init control blocks to hw. Maps control block,
 195  * sets address, triggers download, waits for completion.
 196  */
 197 int ql_write_cfg(struct ql_adapter *qdev, void *ptr, int size, u32 bit,
 198                  u16 q_id)
 199 {
 200         u64 map;
 201         int status = 0;
 202         int direction;
 203         u32 mask;
 204         u32 value;
 205
 206         direction =
 207             (bit & (CFG_LRQ | CFG_LR | CFG_LCQ)) ? PCI_DMA_TODEVICE :
 208             PCI_DMA_FROMDEVICE;
 209
 210         map = pci_map_single(qdev->pdev, ptr, size, direction);
 211         if (pci_dma_mapping_error(qdev->pdev, map)) {
 212                 QPRINTK(qdev, IFUP, ERR, "Couldn't map DMA area.\n");
 213                 return -ENOMEM;
 214         }
 215
 216         status = ql_wait_cfg(qdev, bit);
 217         if (status) {
 218                 QPRINTK(qdev, IFUP, ERR,
 219                         "Timed out waiting for CFG to come ready.\n");
 220                 goto exit;
 221         }
 222
 223         status = ql_sem_spinlock(qdev, SEM_ICB_MASK);
 224         if (status)
 225                 goto exit;
 226         ql_write32(qdev, ICB_L, (u32) map);
 227         ql_write32(qdev, ICB_H, (u32) (map >> 32));
 228         ql_sem_unlock(qdev, SEM_ICB_MASK);      /* does flush too */
 229
 230         mask = CFG_Q_MASK | (bit << 16);
 231         value = bit | (q_id << CFG_Q_SHIFT);
 232         ql_write32(qdev, CFG, (mask | value));
 233
 234         /*
 235          * Wait for the bit to clear after signaling hw.
 236          */
 237         status = ql_wait_cfg(qdev, bit);
 238 exit:
 239         pci_unmap_single(qdev->pdev, map, size, direction);
 240         return status;
 241 }
 242
 243 /* Get a specific MAC address from the CAM.  Used for debug and reg dump. */
 244 int ql_get_mac_addr_reg(struct ql_adapter *qdev, u32 type, u16 index,
 245                         u32 *value)
 246 {
 247         u32 offset = 0;
 248         int status;
 249
 250         status = ql_sem_spinlock(qdev, SEM_MAC_ADDR_MASK);
 251         if (status)
 252                 return status;
 253         switch (type) {
 254         case MAC_ADDR_TYPE_MULTI_MAC:
 255         case MAC_ADDR_TYPE_CAM_MAC:
 256                 {
 257                         status =
 258                             ql_wait_reg_rdy(qdev,
 259                                 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
 260                         if (status)
 261                                 goto exit;
 262                         ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */
 263                                    (index << MAC_ADDR_IDX_SHIFT) | /* index */
 264                                    MAC_ADDR_ADR | MAC_ADDR_RS | type); /* type */
 265                         status =
 266                             ql_wait_reg_rdy(qdev,
 267                                 MAC_ADDR_IDX, MAC_ADDR_MR, 0);
 268                         if (status)
 269                                 goto exit;
 270                         *value++ = ql_read32(qdev, MAC_ADDR_DATA);
 271                         status =
 272                             ql_wait_reg_rdy(qdev,
 273                                 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
 274                         if (status)
 275                                 goto exit;
 276                         ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */
 277                                    (index << MAC_ADDR_IDX_SHIFT) | /* index */
 278                                    MAC_ADDR_ADR | MAC_ADDR_RS | type); /* type */
 279                         status =
 280                             ql_wait_reg_rdy(qdev,
 281                                 MAC_ADDR_IDX, MAC_ADDR_MR, 0);
 282                         if (status)
 283                                 goto exit;
 284                         *value++ = ql_read32(qdev, MAC_ADDR_DATA);
 285                         if (type == MAC_ADDR_TYPE_CAM_MAC) {
 286                                 status =
 287                                     ql_wait_reg_rdy(qdev,
 288                                         MAC_ADDR_IDX, MAC_ADDR_MW, 0);
 289                                 if (status)
 290                                         goto exit;
 291                                 ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */
 292                                            (index << MAC_ADDR_IDX_SHIFT) | /* index */
 293                                            MAC_ADDR_ADR | MAC_ADDR_RS | type); /* type */
 294                                 status =
 295                                     ql_wait_reg_rdy(qdev, MAC_ADDR_IDX,
 296                                                     MAC_ADDR_MR, 0);
 297                                 if (status)
 298                                         goto exit;
 299                                 *value++ = ql_read32(qdev, MAC_ADDR_DATA);
 300                         }
 301                         break;
 302                 }
 303         case MAC_ADDR_TYPE_VLAN:
 304         case MAC_ADDR_TYPE_MULTI_FLTR:
 305         default:
 306                 QPRINTK(qdev, IFUP, CRIT,
 307                         "Address type %d not yet supported.\n", type);
 308                 status = -EPERM;
 309         }
 310 exit:
 311         ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK);
 312         return status;
 313 }
 314
 315 /* Set up a MAC, multicast or VLAN address for the
 316  * inbound frame matching.
 317  */
 318 static int ql_set_mac_addr_reg(struct ql_adapter *qdev, u8 *addr, u32 type,
 319                                u16 index)
 320 {
 321         u32 offset = 0;
 322         int status = 0;
 323
 324         status = ql_sem_spinlock(qdev, SEM_MAC_ADDR_MASK);
 325         if (status)
 326                 return status;
 327         switch (type) {
 328         case MAC_ADDR_TYPE_MULTI_MAC:
 329         case MAC_ADDR_TYPE_CAM_MAC:
 330                 {
 331                         u32 cam_output;
 332                         u32 upper = (addr[0] << 8) | addr[1];
 333                         u32 lower =
 334                             (addr[2] << 24) | (addr[3] << 16) | (addr[4] << 8) |
 335                             (addr[5]);
 336
 337                         QPRINTK(qdev, IFUP, INFO,
 338                                 "Adding %s address %pM"
 339                                 " at index %d in the CAM.\n",
 340                                 ((type ==
 341                                   MAC_ADDR_TYPE_MULTI_MAC) ? "MULTICAST" :
 342                                  "UNICAST"), addr, index);
 343
 344                         status =
 345                             ql_wait_reg_rdy(qdev,
 346                                 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
 347                         if (status)
 348                                 goto exit;
 349                         ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */
 350                                    (index << MAC_ADDR_IDX_SHIFT) | /* index */
 351                                    type);       /* type */
 352                         ql_write32(qdev, MAC_ADDR_DATA, lower);
 353                         status =
 354                             ql_wait_reg_rdy(qdev,
 355                                 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
 356                         if (status)
 357                                 goto exit;
 358                         ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */
 359                                    (index << MAC_ADDR_IDX_SHIFT) | /* index */
 360                                    type);       /* type */
 361                         ql_write32(qdev, MAC_ADDR_DATA, upper);
 362                         status =
 363                             ql_wait_reg_rdy(qdev,
 364                                 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
 365                         if (status)
 366                                 goto exit;
 367                         ql_write32(qdev, MAC_ADDR_IDX, (offset) |       /* offset */
 368                                    (index << MAC_ADDR_IDX_SHIFT) |      /* index */
 369                                    type);       /* type */
 370                         /* This field should also include the queue id
 371                            and possibly the function id.  Right now we hardcode
 372                            the route field to NIC core.
 373                          */
 374                         if (type == MAC_ADDR_TYPE_CAM_MAC) {
 375                                 cam_output = (CAM_OUT_ROUTE_NIC |
 376                                               (qdev->
 377                                                func << CAM_OUT_FUNC_SHIFT) |
 378                                               (qdev->
 379                                                rss_ring_first_cq_id <<
 380                                                CAM_OUT_CQ_ID_SHIFT));
 381                                 if (qdev->vlgrp)
 382                                         cam_output |= CAM_OUT_RV;
 383                                 /* route to NIC core */
 384                                 ql_write32(qdev, MAC_ADDR_DATA, cam_output);
 385                         }
 386                         break;
 387                 }
 388         case MAC_ADDR_TYPE_VLAN:
 389                 {
 390                         u32 enable_bit = *((u32 *) &addr[0]);
 391                         /* For VLAN, the addr actually holds a bit that
 392                          * either enables or disables the vlan id we are
 393                          * addressing. It's either MAC_ADDR_E on or off.
 394                          * That's bit-27 we're talking about.
 395                          */
 396                         QPRINTK(qdev, IFUP, INFO, "%s VLAN ID %d %s the CAM.\n",
 397                                 (enable_bit ? "Adding" : "Removing"),
 398                                 index, (enable_bit ? "to" : "from"));
 399
 400                         status =
 401                             ql_wait_reg_rdy(qdev,
 402                                 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
 403                         if (status)
 404                                 goto exit;
 405                         ql_write32(qdev, MAC_ADDR_IDX, offset | /* offset */
 406                                    (index << MAC_ADDR_IDX_SHIFT) |      /* index */
 407                                    type |       /* type */
 408                                    enable_bit); /* enable/disable */
 409                         break;
 410                 }
 411         case MAC_ADDR_TYPE_MULTI_FLTR:
 412         default:
 413                 QPRINTK(qdev, IFUP, CRIT,
 414                         "Address type %d not yet supported.\n", type);
 415                 status = -EPERM;
 416         }
 417 exit:
 418         ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK);
 419         return status;
 420 }
 421
 422 /* Get a specific frame routing value from the CAM.
 423  * Used for debug and reg dump.
 424  */
 425 int ql_get_routing_reg(struct ql_adapter *qdev, u32 index, u32 *value)
 426 {
 427         int status = 0;
 428
 429         status = ql_sem_spinlock(qdev, SEM_RT_IDX_MASK);
 430         if (status)
 431                 goto exit;
 432
 433         status = ql_wait_reg_rdy(qdev, RT_IDX, RT_IDX_MW, 0);
 434         if (status)
 435                 goto exit;
 436
 437         ql_write32(qdev, RT_IDX,
 438                    RT_IDX_TYPE_NICQ | RT_IDX_RS | (index << RT_IDX_IDX_SHIFT));
 439         status = ql_wait_reg_rdy(qdev, RT_IDX, RT_IDX_MR, 0);
 440         if (status)
 441                 goto exit;
 442         *value = ql_read32(qdev, RT_DATA);
 443 exit:
 444         ql_sem_unlock(qdev, SEM_RT_IDX_MASK);
 445         return status;
 446 }
 447
 448 /* The NIC function for this chip has 16 routing indexes.  Each one can be used
 449  * to route different frame types to various inbound queues.  We send broadcast/
 450  * multicast/error frames to the default queue for slow handling,
 451  * and CAM hit/RSS frames to the fast handling queues.
 452  */
 453 static int ql_set_routing_reg(struct ql_adapter *qdev, u32 index, u32 mask,
 454                               int enable)
 455 {
 456         int status;
 457         u32 value = 0;
 458
 459         status = ql_sem_spinlock(qdev, SEM_RT_IDX_MASK);
 460         if (status)
 461                 return status;
 462
 463         QPRINTK(qdev, IFUP, DEBUG,
 464                 "%s %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s mask %s the routing reg.\n",
 465                 (enable ? "Adding" : "Removing"),
 466                 ((index == RT_IDX_ALL_ERR_SLOT) ? "MAC ERROR/ALL ERROR" : ""),
 467                 ((index == RT_IDX_IP_CSUM_ERR_SLOT) ? "IP CSUM ERROR" : ""),
 468                 ((index ==
 469                   RT_IDX_TCP_UDP_CSUM_ERR_SLOT) ? "TCP/UDP CSUM ERROR" : ""),
 470                 ((index == RT_IDX_BCAST_SLOT) ? "BROADCAST" : ""),
 471                 ((index == RT_IDX_MCAST_MATCH_SLOT) ? "MULTICAST MATCH" : ""),
 472                 ((index == RT_IDX_ALLMULTI_SLOT) ? "ALL MULTICAST MATCH" : ""),
 473                 ((index == RT_IDX_UNUSED6_SLOT) ? "UNUSED6" : ""),
 474                 ((index == RT_IDX_UNUSED7_SLOT) ? "UNUSED7" : ""),
 475                 ((index == RT_IDX_RSS_MATCH_SLOT) ? "RSS ALL/IPV4 MATCH" : ""),
 476                 ((index == RT_IDX_RSS_IPV6_SLOT) ? "RSS IPV6" : ""),
 477                 ((index == RT_IDX_RSS_TCP4_SLOT) ? "RSS TCP4" : ""),
 478                 ((index == RT_IDX_RSS_TCP6_SLOT) ? "RSS TCP6" : ""),
 479                 ((index == RT_IDX_CAM_HIT_SLOT) ? "CAM HIT" : ""),
 480                 ((index == RT_IDX_UNUSED013) ? "UNUSED13" : ""),
 481                 ((index == RT_IDX_UNUSED014) ? "UNUSED14" : ""),
 482                 ((index == RT_IDX_PROMISCUOUS_SLOT) ? "PROMISCUOUS" : ""),
 483                 (enable ? "to" : "from"));
 484
 485         switch (mask) {
 486         case RT_IDX_CAM_HIT:
 487                 {
 488                         value = RT_IDX_DST_CAM_Q |      /* dest */
 489                             RT_IDX_TYPE_NICQ |  /* type */
 490                             (RT_IDX_CAM_HIT_SLOT << RT_IDX_IDX_SHIFT);/* index */
 491                         break;
 492                 }
 493         case RT_IDX_VALID:      /* Promiscuous Mode frames. */
 494                 {
 495                         value = RT_IDX_DST_DFLT_Q |     /* dest */
 496                             RT_IDX_TYPE_NICQ |  /* type */
 497                             (RT_IDX_PROMISCUOUS_SLOT << RT_IDX_IDX_SHIFT);/* index */
 498                         break;
 499                 }
 500         case RT_IDX_ERR:        /* Pass up MAC,IP,TCP/UDP error frames. */
 501                 {
 502                         value = RT_IDX_DST_DFLT_Q |     /* dest */
 503                             RT_IDX_TYPE_NICQ |  /* type */
 504                             (RT_IDX_ALL_ERR_SLOT << RT_IDX_IDX_SHIFT);/* index */
 505                         break;
 506                 }
 507         case RT_IDX_BCAST:      /* Pass up Broadcast frames to default Q. */
 508                 {
 509                         value = RT_IDX_DST_DFLT_Q |     /* dest */
 510                             RT_IDX_TYPE_NICQ |  /* type */
 511                             (RT_IDX_BCAST_SLOT << RT_IDX_IDX_SHIFT);/* index */
 512                         break;
 513                 }
 514         case RT_IDX_MCAST:      /* Pass up All Multicast frames. */
 515                 {
 516                         value = RT_IDX_DST_CAM_Q |      /* dest */
 517                             RT_IDX_TYPE_NICQ |  /* type */
 518                             (RT_IDX_ALLMULTI_SLOT << RT_IDX_IDX_SHIFT);/* index */
 519                         break;
 520                 }
 521         case RT_IDX_MCAST_MATCH:        /* Pass up matched Multicast frames. */
 522                 {
 523                         value = RT_IDX_DST_CAM_Q |      /* dest */
 524                             RT_IDX_TYPE_NICQ |  /* type */
 525                             (RT_IDX_MCAST_MATCH_SLOT << RT_IDX_IDX_SHIFT);/* index */
 526                         break;
 527                 }
 528         case RT_IDX_RSS_MATCH:  /* Pass up matched RSS frames. */
 529                 {
 530                         value = RT_IDX_DST_RSS |        /* dest */
 531                             RT_IDX_TYPE_NICQ |  /* type */
 532                             (RT_IDX_RSS_MATCH_SLOT << RT_IDX_IDX_SHIFT);/* index */
 533                         break;
 534                 }
 535         case 0:         /* Clear the E-bit on an entry. */
 536                 {
 537                         value = RT_IDX_DST_DFLT_Q |     /* dest */
 538                             RT_IDX_TYPE_NICQ |  /* type */
 539                             (index << RT_IDX_IDX_SHIFT);/* index */
 540                         break;
 541                 }
 542         default:
 543                 QPRINTK(qdev, IFUP, ERR, "Mask type %d not yet supported.\n",
 544                         mask);
 545                 status = -EPERM;
 546                 goto exit;
 547         }
 548
 549         if (value) {
 550                 status = ql_wait_reg_rdy(qdev, RT_IDX, RT_IDX_MW, 0);
 551                 if (status)
 552                         goto exit;
 553                 value |= (enable ? RT_IDX_E : 0);
 554                 ql_write32(qdev, RT_IDX, value);
 555                 ql_write32(qdev, RT_DATA, enable ? mask : 0);
 556         }
 557 exit:
 558         ql_sem_unlock(qdev, SEM_RT_IDX_MASK);
 559         return status;
 560 }
 561
 562 static void ql_enable_interrupts(struct ql_adapter *qdev)
 563 {
 564         ql_write32(qdev, INTR_EN, (INTR_EN_EI << 16) | INTR_EN_EI);
 565 }
 566
 567 static void ql_disable_interrupts(struct ql_adapter *qdev)
 568 {
 569         ql_write32(qdev, INTR_EN, (INTR_EN_EI << 16));
 570 }
 571
 572 /* If we're running with multiple MSI-X vectors then we enable on the fly.
 573  * Otherwise, we may have multiple outstanding workers and don't want to
 574  * enable until the last one finishes. In this case, the irq_cnt gets
 575  * incremented everytime we queue a worker and decremented everytime
 576  * a worker finishes.  Once it hits zero we enable the interrupt.
 577  */
 578 u32 ql_enable_completion_interrupt(struct ql_adapter *qdev, u32 intr)
 579 {
 580         u32 var = 0;
 581         unsigned long hw_flags = 0;
 582         struct intr_context *ctx = qdev->intr_context + intr;
 583
 584         if (likely(test_bit(QL_MSIX_ENABLED, &qdev->flags) && intr)) {
 585                 /* Always enable if we're MSIX multi interrupts and
 586                  * it's not the default (zeroeth) interrupt.
 587                  */
 588                 ql_write32(qdev, INTR_EN,
 589                            ctx->intr_en_mask);
 590                 var = ql_read32(qdev, STS);
 591                 return var;
 592         }
 593
 594         spin_lock_irqsave(&qdev->hw_lock, hw_flags);
 595         if (atomic_dec_and_test(&ctx->irq_cnt)) {
 596                 ql_write32(qdev, INTR_EN,
 597                            ctx->intr_en_mask);
 598                 var = ql_read32(qdev, STS);
 599         }
 600         spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
 601         return var;
 602 }
 603
 604 static u32 ql_disable_completion_interrupt(struct ql_adapter *qdev, u32 intr)
 605 {
 606         u32 var = 0;
 607         unsigned long hw_flags;
 608         struct intr_context *ctx;
 609
 610         /* HW disables for us if we're MSIX multi interrupts and
 611          * it's not the default (zeroeth) interrupt.
 612          */
 613         if (likely(test_bit(QL_MSIX_ENABLED, &qdev->flags) && intr))
 614                 return 0;
 615
 616         ctx = qdev->intr_context + intr;
 617         spin_lock_irqsave(&qdev->hw_lock, hw_flags);
 618         if (!atomic_read(&ctx->irq_cnt)) {
 619                 ql_write32(qdev, INTR_EN,
 620                 ctx->intr_dis_mask);
 621                 var = ql_read32(qdev, STS);
 622         }
 623         atomic_inc(&ctx->irq_cnt);
 624         spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
 625         return var;
 626 }
 627
 628 static void ql_enable_all_completion_interrupts(struct ql_adapter *qdev)
 629 {
 630         int i;
 631         for (i = 0; i < qdev->intr_count; i++) {
 632                 /* The enable call does a atomic_dec_and_test
 633                  * and enables only if the result is zero.
 634                  * So we precharge it here.
 635                  */
 636                 if (unlikely(!test_bit(QL_MSIX_ENABLED, &qdev->flags) ||
 637                         i == 0))
 638                         atomic_set(&qdev->intr_context[i].irq_cnt, 1);
 639                 ql_enable_completion_interrupt(qdev, i);
 640         }
 641
 642 }
 643
 644 static int ql_read_flash_word(struct ql_adapter *qdev, int offset, __le32 *data)
 645 {
 646         int status = 0;
 647         /* wait for reg to come ready */
 648         status = ql_wait_reg_rdy(qdev,
 649                         FLASH_ADDR, FLASH_ADDR_RDY, FLASH_ADDR_ERR);
 650         if (status)
 651                 goto exit;
 652         /* set up for reg read */
 653         ql_write32(qdev, FLASH_ADDR, FLASH_ADDR_R | offset);
 654         /* wait for reg to come ready */
 655         status = ql_wait_reg_rdy(qdev,
 656                         FLASH_ADDR, FLASH_ADDR_RDY, FLASH_ADDR_ERR);
 657         if (status)
 658                 goto exit;
 659          /* This data is stored on flash as an array of
 660          * __le32.  Since ql_read32() returns cpu endian
 661          * we need to swap it back.
 662          */
 663         *data = cpu_to_le32(ql_read32(qdev, FLASH_DATA));
 664 exit:
 665         return status;
 666 }
 667
 668 static int ql_get_flash_params(struct ql_adapter *qdev)
 669 {
 670         int i;
 671         int status;
 672         __le32 *p = (__le32 *)&qdev->flash;
 673         u32 offset = 0;
 674
 675         /* Second function's parameters follow the first
 676          * function's.
 677          */
 678         if (qdev->func)
 679                 offset = sizeof(qdev->flash) / sizeof(u32);
 680
 681         if (ql_sem_spinlock(qdev, SEM_FLASH_MASK))
 682                 return -ETIMEDOUT;
 683
 684         for (i = 0; i < sizeof(qdev->flash) / sizeof(u32); i++, p++) {
 685                 status = ql_read_flash_word(qdev, i+offset, p);
 686                 if (status) {
 687                         QPRINTK(qdev, IFUP, ERR, "Error reading flash.\n");
 688                         goto exit;
 689                 }
 690
 691         }
 692 exit:
 693         ql_sem_unlock(qdev, SEM_FLASH_MASK);
 694         return status;
 695 }
 696
 697 /* xgmac register are located behind the xgmac_addr and xgmac_data
 698  * register pair.  Each read/write requires us to wait for the ready
 699  * bit before reading/writing the data.
 700  */
 701 static int ql_write_xgmac_reg(struct ql_adapter *qdev, u32 reg, u32 data)
 702 {
 703         int status;
 704         /* wait for reg to come ready */
 705         status = ql_wait_reg_rdy(qdev,
 706                         XGMAC_ADDR, XGMAC_ADDR_RDY, XGMAC_ADDR_XME);
 707         if (status)
 708                 return status;
 709         /* write the data to the data reg */
 710         ql_write32(qdev, XGMAC_DATA, data);
 711         /* trigger the write */
 712         ql_write32(qdev, XGMAC_ADDR, reg);
 713         return status;
 714 }
 715
 716 /* xgmac register are located behind the xgmac_addr and xgmac_data
 717  * register pair.  Each read/write requires us to wait for the ready
 718  * bit before reading/writing the data.
 719  */
 720 int ql_read_xgmac_reg(struct ql_adapter *qdev, u32 reg, u32 *data)
 721 {
 722         int status = 0;
 723         /* wait for reg to come ready */
 724         status = ql_wait_reg_rdy(qdev,
 725                         XGMAC_ADDR, XGMAC_ADDR_RDY, XGMAC_ADDR_XME);
 726         if (status)
 727                 goto exit;
 728         /* set up for reg read */
 729         ql_write32(qdev, XGMAC_ADDR, reg | XGMAC_ADDR_R);
 730         /* wait for reg to come ready */
 731         status = ql_wait_reg_rdy(qdev,
 732                         XGMAC_ADDR, XGMAC_ADDR_RDY, XGMAC_ADDR_XME);
 733         if (status)
 734                 goto exit;
 735         /* get the data */
 736         *data = ql_read32(qdev, XGMAC_DATA);
 737 exit:
 738         return status;
 739 }
 740
 741 /* This is used for reading the 64-bit statistics regs. */
 742 int ql_read_xgmac_reg64(struct ql_adapter *qdev, u32 reg, u64 *data)
 743 {
 744         int status = 0;
 745         u32 hi = 0;
 746         u32 lo = 0;
 747
 748         status = ql_read_xgmac_reg(qdev, reg, &lo);
 749         if (status)
 750                 goto exit;
 751
 752         status = ql_read_xgmac_reg(qdev, reg + 4, &hi);
 753         if (status)
 754                 goto exit;
 755
 756         *data = (u64) lo | ((u64) hi << 32);
 757
 758 exit:
 759         return status;
 760 }
 761
 762 /* Take the MAC Core out of reset.
 763  * Enable statistics counting.
 764  * Take the transmitter/receiver out of reset.
 765  * This functionality may be done in the MPI firmware at a
 766  * later date.
 767  */
 768 static int ql_port_initialize(struct ql_adapter *qdev)
 769 {
 770         int status = 0;
 771         u32 data;
 772
 773         if (ql_sem_trylock(qdev, qdev->xg_sem_mask)) {
 774                 /* Another function has the semaphore, so
 775                  * wait for the port init bit to come ready.
 776                  */
 777                 QPRINTK(qdev, LINK, INFO,
 778                         "Another function has the semaphore, so wait for the port init bit to come ready.\n");
 779                 status = ql_wait_reg_rdy(qdev, STS, qdev->port_init, 0);
 780                 if (status) {
 781                         QPRINTK(qdev, LINK, CRIT,
 782                                 "Port initialize timed out.\n");
 783                 }
 784                 return status;
 785         }
 786
 787         QPRINTK(qdev, LINK, INFO, "Got xgmac semaphore!.\n");
 788         /* Set the core reset. */
 789         status = ql_read_xgmac_reg(qdev, GLOBAL_CFG, &data);
 790         if (status)
 791                 goto end;
 792         data |= GLOBAL_CFG_RESET;
 793         status = ql_write_xgmac_reg(qdev, GLOBAL_CFG, data);
 794         if (status)
 795                 goto end;
 796
 797         /* Clear the core reset and turn on jumbo for receiver. */
 798         data &= ~GLOBAL_CFG_RESET;      /* Clear core reset. */
 799         data |= GLOBAL_CFG_JUMBO;       /* Turn on jumbo. */
 800         data |= GLOBAL_CFG_TX_STAT_EN;
 801         data |= GLOBAL_CFG_RX_STAT_EN;
 802         status = ql_write_xgmac_reg(qdev, GLOBAL_CFG, data);
 803         if (status)
 804                 goto end;
 805
 806         /* Enable transmitter, and clear it's reset. */
 807         status = ql_read_xgmac_reg(qdev, TX_CFG, &data);
 808         if (status)
 809                 goto end;
 810         data &= ~TX_CFG_RESET;  /* Clear the TX MAC reset. */
 811         data |= TX_CFG_EN;      /* Enable the transmitter. */
 812         status = ql_write_xgmac_reg(qdev, TX_CFG, data);
 813         if (status)
 814                 goto end;
 815
 816         /* Enable receiver and clear it's reset. */
 817         status = ql_read_xgmac_reg(qdev, RX_CFG, &data);
 818         if (status)
 819                 goto end;
 820         data &= ~RX_CFG_RESET;  /* Clear the RX MAC reset. */
 821         data |= RX_CFG_EN;      /* Enable the receiver. */
 822         status = ql_write_xgmac_reg(qdev, RX_CFG, data);
 823         if (status)
 824                 goto end;
 825
 826         /* Turn on jumbo. */
 827         status =
 828             ql_write_xgmac_reg(qdev, MAC_TX_PARAMS, MAC_TX_PARAMS_JUMBO | (0x2580 << 16));
 829         if (status)
 830                 goto end;
 831         status =
 832             ql_write_xgmac_reg(qdev, MAC_RX_PARAMS, 0x2580);
 833         if (status)
 834                 goto end;
 835
 836         /* Signal to the world that the port is enabled.        */
 837         ql_write32(qdev, STS, ((qdev->port_init << 16) | qdev->port_init));
 838 end:
 839         ql_sem_unlock(qdev, qdev->xg_sem_mask);
 840         return status;
 841 }
 842
 843 /* Get the next large buffer. */
 844 static struct bq_desc *ql_get_curr_lbuf(struct rx_ring *rx_ring)
 845 {
 846         struct bq_desc *lbq_desc = &rx_ring->lbq[rx_ring->lbq_curr_idx];
 847         rx_ring->lbq_curr_idx++;
 848         if (rx_ring->lbq_curr_idx == rx_ring->lbq_len)
 849                 rx_ring->lbq_curr_idx = 0;
 850         rx_ring->lbq_free_cnt++;
 851         return lbq_desc;
 852 }
 853
 854 /* Get the next small buffer. */
 855 static struct bq_desc *ql_get_curr_sbuf(struct rx_ring *rx_ring)
 856 {
 857         struct bq_desc *sbq_desc = &rx_ring->sbq[rx_ring->sbq_curr_idx];
 858         rx_ring->sbq_curr_idx++;
 859         if (rx_ring->sbq_curr_idx == rx_ring->sbq_len)
 860                 rx_ring->sbq_curr_idx = 0;
 861         rx_ring->sbq_free_cnt++;
 862         return sbq_desc;
 863 }
 864
 865 /* Update an rx ring index. */
 866 static void ql_update_cq(struct rx_ring *rx_ring)
 867 {
 868         rx_ring->cnsmr_idx++;
 869         rx_ring->curr_entry++;
 870         if (unlikely(rx_ring->cnsmr_idx == rx_ring->cq_len)) {
 871                 rx_ring->cnsmr_idx = 0;
 872                 rx_ring->curr_entry = rx_ring->cq_base;
 873         }
 874 }
 875
 876 static void ql_write_cq_idx(struct rx_ring *rx_ring)
 877 {
 878         ql_write_db_reg(rx_ring->cnsmr_idx, rx_ring->cnsmr_idx_db_reg);
 879 }
 880
 881 /* Process (refill) a large buffer queue. */
 882 static void ql_update_lbq(struct ql_adapter *qdev, struct rx_ring *rx_ring)
 883 {
 884         int clean_idx = rx_ring->lbq_clean_idx;
 885         struct bq_desc *lbq_desc;
 886         u64 map;
 887         int i;
 888
 889         while (rx_ring->lbq_free_cnt > 16) {
 890                 for (i = 0; i < 16; i++) {
 891                         QPRINTK(qdev, RX_STATUS, DEBUG,
 892                                 "lbq: try cleaning clean_idx = %d.\n",
 893                                 clean_idx);
 894                         lbq_desc = &rx_ring->lbq[clean_idx];
 895                         if (lbq_desc->p.lbq_page == NULL) {
 896                                 QPRINTK(qdev, RX_STATUS, DEBUG,
 897                                         "lbq: getting new page for index %d.\n",
 898                                         lbq_desc->index);
 899                                 lbq_desc->p.lbq_page = alloc_page(GFP_ATOMIC);
 900                                 if (lbq_desc->p.lbq_page == NULL) {
 901                                         QPRINTK(qdev, RX_STATUS, ERR,
 902                                                 "Couldn't get a page.\n");
 903                                         return;
 904                                 }
 905                                 map = pci_map_page(qdev->pdev,
 906                                                    lbq_desc->p.lbq_page,
 907                                                    0, PAGE_SIZE,
 908                                                    PCI_DMA_FROMDEVICE);
 909                                 if (pci_dma_mapping_error(qdev->pdev, map)) {
 910                                         put_page(lbq_desc->p.lbq_page);
 911                                         lbq_desc->p.lbq_page = NULL;
 912                                         QPRINTK(qdev, RX_STATUS, ERR,
 913                                                 "PCI mapping failed.\n");
 914                                         return;
 915                                 }
 916                                 pci_unmap_addr_set(lbq_desc, mapaddr, map);
 917                                 pci_unmap_len_set(lbq_desc, maplen, PAGE_SIZE);
 918                                 *lbq_desc->addr = cpu_to_le64(map);
 919                         }
 920                         clean_idx++;
 921                         if (clean_idx == rx_ring->lbq_len)
 922                                 clean_idx = 0;
 923                 }
 924
 925                 rx_ring->lbq_clean_idx = clean_idx;
 926                 rx_ring->lbq_prod_idx += 16;
 927                 if (rx_ring->lbq_prod_idx == rx_ring->lbq_len)
 928                         rx_ring->lbq_prod_idx = 0;
 929                 QPRINTK(qdev, RX_STATUS, DEBUG,
 930                         "lbq: updating prod idx = %d.\n",
 931                         rx_ring->lbq_prod_idx);
 932                 ql_write_db_reg(rx_ring->lbq_prod_idx,
 933                                 rx_ring->lbq_prod_idx_db_reg);
 934                 rx_ring->lbq_free_cnt -= 16;
 935         }
 936 }
 937
 938 /* Process (refill) a small buffer queue. */
 939 static void ql_update_sbq(struct ql_adapter *qdev, struct rx_ring *rx_ring)
 940 {
 941         int clean_idx = rx_ring->sbq_clean_idx;
 942         struct bq_desc *sbq_desc;
 943         u64 map;
 944         int i;
 945
 946         while (rx_ring->sbq_free_cnt > 16) {
 947                 for (i = 0; i < 16; i++) {
 948                         sbq_desc = &rx_ring->sbq[clean_idx];
 949                         QPRINTK(qdev, RX_STATUS, DEBUG,
 950                                 "sbq: try cleaning clean_idx = %d.\n",
 951                                 clean_idx);
 952                         if (sbq_desc->p.skb == NULL) {
 953                                 QPRINTK(qdev, RX_STATUS, DEBUG,
 954                                         "sbq: getting new skb for index %d.\n",
 955                                         sbq_desc->index);
 956                                 sbq_desc->p.skb =
 957                                     netdev_alloc_skb(qdev->ndev,
 958                                                      rx_ring->sbq_buf_size);
 959                                 if (sbq_desc->p.skb == NULL) {
 960                                         QPRINTK(qdev, PROBE, ERR,
 961                                                 "Couldn't get an skb.\n");
 962                                         rx_ring->sbq_clean_idx = clean_idx;
 963                                         return;
 964                                 }
 965                                 skb_reserve(sbq_desc->p.skb, QLGE_SB_PAD);
 966                                 map = pci_map_single(qdev->pdev,
 967                                                      sbq_desc->p.skb->data,
 968                                                      rx_ring->sbq_buf_size /
 969                                                      2, PCI_DMA_FROMDEVICE);
 970                                 if (pci_dma_mapping_error(qdev->pdev, map)) {
 971                                         QPRINTK(qdev, IFUP, ERR, "PCI mapping failed.\n");
 972                                         rx_ring->sbq_clean_idx = clean_idx;
 973                                         dev_kfree_skb_any(sbq_desc->p.skb);
 974                                         sbq_desc->p.skb = NULL;
 975                                         return;
 976                                 }
 977                                 pci_unmap_addr_set(sbq_desc, mapaddr, map);
 978                                 pci_unmap_len_set(sbq_desc, maplen,
 979                                                   rx_ring->sbq_buf_size / 2);
 980                                 *sbq_desc->addr = cpu_to_le64(map);
 981                         }
 982
 983                         clean_idx++;
 984                         if (clean_idx == rx_ring->sbq_len)
 985                                 clean_idx = 0;
 986                 }
 987                 rx_ring->sbq_clean_idx = clean_idx;
 988                 rx_ring->sbq_prod_idx += 16;
 989                 if (rx_ring->sbq_prod_idx == rx_ring->sbq_len)
 990                         rx_ring->sbq_prod_idx = 0;
 991                 QPRINTK(qdev, RX_STATUS, DEBUG,
 992                         "sbq: updating prod idx = %d.\n",
 993                         rx_ring->sbq_prod_idx);
 994                 ql_write_db_reg(rx_ring->sbq_prod_idx,
 995                                 rx_ring->sbq_prod_idx_db_reg);
 996
 997                 rx_ring->sbq_free_cnt -= 16;
 998         }
 999 }
1000
1001 static void ql_update_buffer_queues(struct ql_adapter *qdev,
1002                                     struct rx_ring *rx_ring)
1003 {
1004         ql_update_sbq(qdev, rx_ring);
1005         ql_update_lbq(qdev, rx_ring);
1006 }
1007
1008 /* Unmaps tx buffers.  Can be called from send() if a pci mapping
1009  * fails at some stage, or from the interrupt when a tx completes.
1010  */
1011 static void ql_unmap_send(struct ql_adapter *qdev,
1012                           struct tx_ring_desc *tx_ring_desc, int mapped)
1013 {
1014         int i;
1015         for (i = 0; i < mapped; i++) {
1016                 if (i == 0 || (i == 7 && mapped > 7)) {
1017                         /*
1018                          * Unmap the skb->data area, or the
1019                          * external sglist (AKA the Outbound
1020                          * Address List (OAL)).
1021                          * If its the zeroeth element, then it's
1022                          * the skb->data area.  If it's the 7th
1023                          * element and there is more than 6 frags,
1024                          * then its an OAL.
1025                          */
1026                         if (i == 7) {
1027                                 QPRINTK(qdev, TX_DONE, DEBUG,
1028                                         "unmapping OAL area.\n");
1029                         }
1030                         pci_unmap_single(qdev->pdev,
1031                                          pci_unmap_addr(&tx_ring_desc->map[i],
1032                                                         mapaddr),
1033                                          pci_unmap_len(&tx_ring_desc->map[i],
1034                                                        maplen),
1035                                          PCI_DMA_TODEVICE);
1036                 } else {
1037                         QPRINTK(qdev, TX_DONE, DEBUG, "unmapping frag %d.\n",
1038                                 i);
1039                         pci_unmap_page(qdev->pdev,
1040                                        pci_unmap_addr(&tx_ring_desc->map[i],
1041                                                       mapaddr),
1042                                        pci_unmap_len(&tx_ring_desc->map[i],
1043                                                      maplen), PCI_DMA_TODEVICE);
1044                 }
1045         }
1046
1047 }
1048
1049 /* Map the buffers for this transmit.  This will return
1050  * NETDEV_TX_BUSY or NETDEV_TX_OK based on success.
1051  */
1052 static int ql_map_send(struct ql_adapter *qdev,
1053                        struct ob_mac_iocb_req *mac_iocb_ptr,
1054                        struct sk_buff *skb, struct tx_ring_desc *tx_ring_desc)
1055 {
1056         int len = skb_headlen(skb);
1057         dma_addr_t map;
1058         int frag_idx, err, map_idx = 0;
1059         struct tx_buf_desc *tbd = mac_iocb_ptr->tbd;
1060         int frag_cnt = skb_shinfo(skb)->nr_frags;
1061
1062         if (frag_cnt) {
1063                 QPRINTK(qdev, TX_QUEUED, DEBUG, "frag_cnt = %d.\n", frag_cnt);
1064         }
1065         /*
1066          * Map the skb buffer first.
1067          */
1068         map = pci_map_single(qdev->pdev, skb->data, len, PCI_DMA_TODEVICE);
1069
1070         err = pci_dma_mapping_error(qdev->pdev, map);
1071         if (err) {
1072                 QPRINTK(qdev, TX_QUEUED, ERR,
1073                         "PCI mapping failed with error: %d\n", err);
1074
1075                 return NETDEV_TX_BUSY;
1076         }
1077
1078         tbd->len = cpu_to_le32(len);
1079         tbd->addr = cpu_to_le64(map);
1080         pci_unmap_addr_set(&tx_ring_desc->map[map_idx], mapaddr, map);
1081         pci_unmap_len_set(&tx_ring_desc->map[map_idx], maplen, len);
1082         map_idx++;
1083
1084         /*
1085          * This loop fills the remainder of the 8 address descriptors
1086          * in the IOCB.  If there are more than 7 fragments, then the
1087          * eighth address desc will point to an external list (OAL).
1088          * When this happens, the remainder of the frags will be stored
1089          * in this list.
1090          */
1091         for (frag_idx = 0; frag_idx < frag_cnt; frag_idx++, map_idx++) {
1092                 skb_frag_t *frag = &skb_shinfo(skb)->frags[frag_idx];
1093                 tbd++;
1094                 if (frag_idx == 6 && frag_cnt > 7) {
1095                         /* Let's tack on an sglist.
1096                          * Our control block will now
1097                          * look like this:
1098                          * iocb->seg[0] = skb->data
1099                          * iocb->seg[1] = frag[0]
1100                          * iocb->seg[2] = frag[1]
1101                          * iocb->seg[3] = frag[2]
1102                          * iocb->seg[4] = frag[3]
1103                          * iocb->seg[5] = frag[4]
1104                          * iocb->seg[6] = frag[5]
1105                          * iocb->seg[7] = ptr to OAL (external sglist)
1106                          * oal->seg[0] = frag[6]
1107                          * oal->seg[1] = frag[7]
1108                          * oal->seg[2] = frag[8]
1109                          * oal->seg[3] = frag[9]
1110                          * oal->seg[4] = frag[10]
1111                          *      etc...
1112                          */
1113                         /* Tack on the OAL in the eighth segment of IOCB. */
1114                         map = pci_map_single(qdev->pdev, &tx_ring_desc->oal,
1115                                              sizeof(struct oal),
1116                                              PCI_DMA_TODEVICE);
1117                         err = pci_dma_mapping_error(qdev->pdev, map);
1118                         if (err) {
1119                                 QPRINTK(qdev, TX_QUEUED, ERR,
1120                                         "PCI mapping outbound address list with error: %d\n",
1121                                         err);
1122                                 goto map_error;
1123                         }
1124
1125                         tbd->addr = cpu_to_le64(map);
1126                         /*
1127                          * The length is the number of fragments
1128                          * that remain to be mapped times the length
1129                          * of our sglist (OAL).
1130                          */
1131                         tbd->len =
1132                             cpu_to_le32((sizeof(struct tx_buf_desc) *
1133                                          (frag_cnt - frag_idx)) | TX_DESC_C);
1134                         pci_unmap_addr_set(&tx_ring_desc->map[map_idx], mapaddr,
1135                                            map);
1136                         pci_unmap_len_set(&tx_ring_desc->map[map_idx], maplen,
1137                                           sizeof(struct oal));
1138                         tbd = (struct tx_buf_desc *)&tx_ring_desc->oal;
1139                         map_idx++;
1140                 }
1141
1142                 map =
1143                     pci_map_page(qdev->pdev, frag->page,
1144                                  frag->page_offset, frag->size,
1145                                  PCI_DMA_TODEVICE);
1146
1147                 err = pci_dma_mapping_error(qdev->pdev, map);
1148                 if (err) {
1149                         QPRINTK(qdev, TX_QUEUED, ERR,
1150                                 "PCI mapping frags failed with error: %d.\n",
1151                                 err);
1152                         goto map_error;
1153                 }
1154
1155                 tbd->addr = cpu_to_le64(map);
1156                 tbd->len = cpu_to_le32(frag->size);
1157                 pci_unmap_addr_set(&tx_ring_desc->map[map_idx], mapaddr, map);
1158                 pci_unmap_len_set(&tx_ring_desc->map[map_idx], maplen,
1159                                   frag->size);
1160
1161         }
1162         /* Save the number of segments we've mapped. */
1163         tx_ring_desc->map_cnt = map_idx;
1164         /* Terminate the last segment. */
1165         tbd->len = cpu_to_le32(le32_to_cpu(tbd->len) | TX_DESC_E);
1166         return NETDEV_TX_OK;
1167
1168 map_error:
1169         /*
1170          * If the first frag mapping failed, then i will be zero.
1171          * This causes the unmap of the skb->data area.  Otherwise
1172          * we pass in the number of frags that mapped successfully
1173          * so they can be umapped.
1174          */
1175         ql_unmap_send(qdev, tx_ring_desc, map_idx);
1176         return NETDEV_TX_BUSY;
1177 }
1178
1179 static void ql_realign_skb(struct sk_buff *skb, int len)
1180 {
1181         void *temp_addr = skb->data;
1182
1183         /* Undo the skb_reserve(skb,32) we did before
1184          * giving to hardware, and realign data on
1185          * a 2-byte boundary.
1186          */
1187         skb->data -= QLGE_SB_PAD - NET_IP_ALIGN;
1188         skb->tail -= QLGE_SB_PAD - NET_IP_ALIGN;
1189         skb_copy_to_linear_data(skb, temp_addr,
1190                 (unsigned int)len);
1191 }
1192
1193 /*
1194  * This function builds an skb for the given inbound
1195  * completion.  It will be rewritten for readability in the near
1196  * future, but for not it works well.
1197  */
1198 static struct sk_buff *ql_build_rx_skb(struct ql_adapter *qdev,
1199                                        struct rx_ring *rx_ring,
1200                                        struct ib_mac_iocb_rsp *ib_mac_rsp)
1201 {
1202         struct bq_desc *lbq_desc;
1203         struct bq_desc *sbq_desc;
1204         struct sk_buff *skb = NULL;
1205         u32 length = le32_to_cpu(ib_mac_rsp->data_len);
1206        u32 hdr_len = le32_to_cpu(ib_mac_rsp->hdr_len);
1207
1208         /*
1209          * Handle the header buffer if present.
1210          */
1211         if (ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HV &&
1212             ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HS) {
1213                 QPRINTK(qdev, RX_STATUS, DEBUG, "Header of %d bytes in small buffer.\n", hdr_len);
1214                 /*
1215                  * Headers fit nicely into a small buffer.
1216                  */
1217                 sbq_desc = ql_get_curr_sbuf(rx_ring);
1218                 pci_unmap_single(qdev->pdev,
1219                                 pci_unmap_addr(sbq_desc, mapaddr),
1220                                 pci_unmap_len(sbq_desc, maplen),
1221                                 PCI_DMA_FROMDEVICE);
1222                 skb = sbq_desc->p.skb;
1223                 ql_realign_skb(skb, hdr_len);
1224                 skb_put(skb, hdr_len);
1225                 sbq_desc->p.skb = NULL;
1226         }
1227
1228         /*
1229          * Handle the data buffer(s).
1230          */
1231         if (unlikely(!length)) {        /* Is there data too? */
1232                 QPRINTK(qdev, RX_STATUS, DEBUG,
1233                         "No Data buffer in this packet.\n");
1234                 return skb;
1235         }
1236
1237         if (ib_mac_rsp->flags3 & IB_MAC_IOCB_RSP_DS) {
1238                 if (ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HS) {
1239                         QPRINTK(qdev, RX_STATUS, DEBUG,
1240                                 "Headers in small, data of %d bytes in small, combine them.\n", length);
1241                         /*
1242                          * Data is less than small buffer size so it's
1243                          * stuffed in a small buffer.
1244                          * For this case we append the data
1245                          * from the "data" small buffer to the "header" small
1246                          * buffer.
1247                          */
1248                         sbq_desc = ql_get_curr_sbuf(rx_ring);
1249                         pci_dma_sync_single_for_cpu(qdev->pdev,
1250                                                     pci_unmap_addr
1251                                                     (sbq_desc, mapaddr),
1252                                                     pci_unmap_len
1253                                                     (sbq_desc, maplen),
1254                                                     PCI_DMA_FROMDEVICE);
1255                         memcpy(skb_put(skb, length),
1256                                sbq_desc->p.skb->data, length);
1257                         pci_dma_sync_single_for_device(qdev->pdev,
1258                                                        pci_unmap_addr
1259                                                        (sbq_desc,
1260                                                         mapaddr),
1261                                                        pci_unmap_len
1262                                                        (sbq_desc,
1263                                                         maplen),
1264                                                        PCI_DMA_FROMDEVICE);
1265                 } else {
1266                         QPRINTK(qdev, RX_STATUS, DEBUG,
1267                                 "%d bytes in a single small buffer.\n", length);
1268                         sbq_desc = ql_get_curr_sbuf(rx_ring);
1269                         skb = sbq_desc->p.skb;
1270                         ql_realign_skb(skb, length);
1271                         skb_put(skb, length);
1272                         pci_unmap_single(qdev->pdev,
1273                                          pci_unmap_addr(sbq_desc,
1274                                                         mapaddr),
1275                                          pci_unmap_len(sbq_desc,
1276                                                        maplen),
1277                                          PCI_DMA_FROMDEVICE);
1278                         sbq_desc->p.skb = NULL;
1279                 }
1280         } else if (ib_mac_rsp->flags3 & IB_MAC_IOCB_RSP_DL) {
1281                 if (ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HS) {
1282                         QPRINTK(qdev, RX_STATUS, DEBUG,
1283                                 "Header in small, %d bytes in large. Chain large to small!\n", length);
1284                         /*
1285                          * The data is in a single large buffer.  We
1286                          * chain it to the header buffer's skb and let
1287                          * it rip.
1288                          */
1289                         lbq_desc = ql_get_curr_lbuf(rx_ring);
1290                         pci_unmap_page(qdev->pdev,
1291                                        pci_unmap_addr(lbq_desc,
1292                                                       mapaddr),
1293                                        pci_unmap_len(lbq_desc, maplen),
1294                                        PCI_DMA_FROMDEVICE);
1295                         QPRINTK(qdev, RX_STATUS, DEBUG,
1296                                 "Chaining page to skb.\n");
1297                         skb_fill_page_desc(skb, 0, lbq_desc->p.lbq_page,
1298                                            0, length);
1299                         skb->len += length;
1300                         skb->data_len += length;
1301                         skb->truesize += length;
1302                         lbq_desc->p.lbq_page = NULL;
1303                 } else {
1304                         /*
1305                          * The headers and data are in a single large buffer. We
1306                          * copy it to a new skb and let it go. This can happen with
1307                          * jumbo mtu on a non-TCP/UDP frame.
1308                          */
1309                         lbq_desc = ql_get_curr_lbuf(rx_ring);
1310                         skb = netdev_alloc_skb(qdev->ndev, length);
1311                         if (skb == NULL) {
1312                                 QPRINTK(qdev, PROBE, DEBUG,
1313                                         "No skb available, drop the packet.\n");
1314                                 return NULL;
1315                         }
1316                         pci_unmap_page(qdev->pdev,
1317                                        pci_unmap_addr(lbq_desc,
1318                                                       mapaddr),
1319                                        pci_unmap_len(lbq_desc, maplen),
1320                                        PCI_DMA_FROMDEVICE);
1321                         skb_reserve(skb, NET_IP_ALIGN);
1322                         QPRINTK(qdev, RX_STATUS, DEBUG,
1323                                 "%d bytes of headers and data in large. Chain page to new skb and pull tail.\n", length);
1324                         skb_fill_page_desc(skb, 0, lbq_desc->p.lbq_page,
1325                                            0, length);
1326                         skb->len += length;
1327                         skb->data_len += length;
1328                         skb->truesize += length;
1329                         length -= length;
1330                         lbq_desc->p.lbq_page = NULL;
1331                         __pskb_pull_tail(skb,
1332                                 (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_V) ?
1333                                 VLAN_ETH_HLEN : ETH_HLEN);
1334                 }
1335         } else {
1336                 /*
1337                  * The data is in a chain of large buffers
1338                  * pointed to by a small buffer.  We loop
1339                  * thru and chain them to the our small header
1340                  * buffer's skb.
1341                  * frags:  There are 18 max frags and our small
1342                  *         buffer will hold 32 of them. The thing is,
1343                  *         we'll use 3 max for our 9000 byte jumbo
1344                  *         frames.  If the MTU goes up we could
1345                  *          eventually be in trouble.
1346                  */
1347                 int size, offset, i = 0;
1348                 __le64 *bq, bq_array[8];
1349                 sbq_desc = ql_get_curr_sbuf(rx_ring);
1350                 pci_unmap_single(qdev->pdev,
1351                                  pci_unmap_addr(sbq_desc, mapaddr),
1352                                  pci_unmap_len(sbq_desc, maplen),
1353                                  PCI_DMA_FROMDEVICE);
1354                 if (!(ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HS)) {
1355                         /*
1356                          * This is an non TCP/UDP IP frame, so
1357                          * the headers aren't split into a small
1358                          * buffer.  We have to use the small buffer
1359                          * that contains our sg list as our skb to
1360                          * send upstairs. Copy the sg list here to
1361                          * a local buffer and use it to find the
1362                          * pages to chain.
1363                          */
1364                         QPRINTK(qdev, RX_STATUS, DEBUG,
1365                                 "%d bytes of headers & data in chain of large.\n", length);
1366                         skb = sbq_desc->p.skb;
1367                         bq = &bq_array[0];
1368                         memcpy(bq, skb->data, sizeof(bq_array));
1369                         sbq_desc->p.skb = NULL;
1370                         skb_reserve(skb, NET_IP_ALIGN);
1371                 } else {
1372                         QPRINTK(qdev, RX_STATUS, DEBUG,
1373                                 "Headers in small, %d bytes of data in chain of large.\n", length);
1374                         bq = (__le64 *)sbq_desc->p.skb->data;
1375                 }
1376                 while (length > 0) {
1377                         lbq_desc = ql_get_curr_lbuf(rx_ring);
1378                         pci_unmap_page(qdev->pdev,
1379                                        pci_unmap_addr(lbq_desc,
1380                                                       mapaddr),
1381                                        pci_unmap_len(lbq_desc,
1382                                                      maplen),
1383                                        PCI_DMA_FROMDEVICE);
1384                         size = (length < PAGE_SIZE) ? length : PAGE_SIZE;
1385                         offset = 0;
1386
1387                         QPRINTK(qdev, RX_STATUS, DEBUG,
1388                                 "Adding page %d to skb for %d bytes.\n",
1389                                 i, size);
1390                         skb_fill_page_desc(skb, i, lbq_desc->p.lbq_page,
1391                                            offset, size);
1392                         skb->len += size;
1393                         skb->data_len += size;
1394                         skb->truesize += size;
1395                         length -= size;
1396                         lbq_desc->p.lbq_page = NULL;
1397                         bq++;
1398                         i++;
1399                 }
1400                 __pskb_pull_tail(skb, (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_V) ?
1401                                 VLAN_ETH_HLEN : ETH_HLEN);
1402         }
1403         return skb;
1404 }
1405
1406 /* Process an inbound completion from an rx ring. */
1407 static void ql_process_mac_rx_intr(struct ql_adapter *qdev,
1408                                    struct rx_ring *rx_ring,
1409                                    struct ib_mac_iocb_rsp *ib_mac_rsp)
1410 {
1411         struct net_device *ndev = qdev->ndev;
1412         struct sk_buff *skb = NULL;
1413
1414         QL_DUMP_IB_MAC_RSP(ib_mac_rsp);
1415
1416         skb = ql_build_rx_skb(qdev, rx_ring, ib_mac_rsp);
1417         if (unlikely(!skb)) {
1418                 QPRINTK(qdev, RX_STATUS, DEBUG,
1419                         "No skb available, drop packet.\n");
1420                 return;
1421         }
1422
1423         prefetch(skb->data);
1424         skb->dev = ndev;
1425         if (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) {
1426                 QPRINTK(qdev, RX_STATUS, DEBUG, "%s%s%s Multicast.\n",
1427                         (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) ==
1428                         IB_MAC_IOCB_RSP_M_HASH ? "Hash" : "",
1429                         (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) ==
1430                         IB_MAC_IOCB_RSP_M_REG ? "Registered" : "",
1431                         (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) ==
1432                         IB_MAC_IOCB_RSP_M_PROM ? "Promiscuous" : "");
1433         }
1434         if (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_P) {
1435                 QPRINTK(qdev, RX_STATUS, DEBUG, "Promiscuous Packet.\n");
1436         }
1437         if (ib_mac_rsp->flags1 & (IB_MAC_IOCB_RSP_IE | IB_MAC_IOCB_RSP_TE)) {
1438                 QPRINTK(qdev, RX_STATUS, ERR,
1439                         "Bad checksum for this %s packet.\n",
1440                         ((ib_mac_rsp->
1441                           flags2 & IB_MAC_IOCB_RSP_T) ? "TCP" : "UDP"));
1442                 skb->ip_summed = CHECKSUM_NONE;
1443         } else if (qdev->rx_csum &&
1444                    ((ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_T) ||
1445                     ((ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_U) &&
1446                      !(ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_NU)))) {
1447                 QPRINTK(qdev, RX_STATUS, DEBUG, "RX checksum done!\n");
1448                 skb->ip_summed = CHECKSUM_UNNECESSARY;
1449         }
1450         qdev->stats.rx_packets++;
1451         qdev->stats.rx_bytes += skb->len;
1452         skb->protocol = eth_type_trans(skb, ndev);
1453         if (qdev->vlgrp && (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_V)) {
1454                 QPRINTK(qdev, RX_STATUS, DEBUG,
1455                         "Passing a VLAN packet upstream.\n");
1456                 vlan_hwaccel_receive_skb(skb, qdev->vlgrp,
1457                                 le16_to_cpu(ib_mac_rsp->vlan_id));
1458         } else {
1459                 QPRINTK(qdev, RX_STATUS, DEBUG,
1460                         "Passing a normal packet upstream.\n");
1461                 netif_receive_skb(skb);
1462         }
1463 }
1464
1465 /* Process an outbound completion from an rx ring. */
1466 static void ql_process_mac_tx_intr(struct ql_adapter *qdev,
1467                                    struct ob_mac_iocb_rsp *mac_rsp)
1468 {
1469         struct tx_ring *tx_ring;
1470         struct tx_ring_desc *tx_ring_desc;
1471
1472         QL_DUMP_OB_MAC_RSP(mac_rsp);
1473         tx_ring = &qdev->tx_ring[mac_rsp->txq_idx];
1474         tx_ring_desc = &tx_ring->q[mac_rsp->tid];
1475         ql_unmap_send(qdev, tx_ring_desc, tx_ring_desc->map_cnt);
1476         qdev->stats.tx_bytes += tx_ring_desc->map_cnt;
1477         qdev->stats.tx_packets++;
1478         dev_kfree_skb(tx_ring_desc->skb);
1479         tx_ring_desc->skb = NULL;
1480
1481         if (unlikely(mac_rsp->flags1 & (OB_MAC_IOCB_RSP_E |
1482                                         OB_MAC_IOCB_RSP_S |
1483                                         OB_MAC_IOCB_RSP_L |
1484                                         OB_MAC_IOCB_RSP_P | OB_MAC_IOCB_RSP_B))) {
1485                 if (mac_rsp->flags1 & OB_MAC_IOCB_RSP_E) {
1486                         QPRINTK(qdev, TX_DONE, WARNING,
1487                                 "Total descriptor length did not match transfer length.\n");
1488                 }
1489                 if (mac_rsp->flags1 & OB_MAC_IOCB_RSP_S) {
1490                         QPRINTK(qdev, TX_DONE, WARNING,
1491                                 "Frame too short to be legal, not sent.\n");
1492                 }
1493                 if (mac_rsp->flags1 & OB_MAC_IOCB_RSP_L) {
1494                         QPRINTK(qdev, TX_DONE, WARNING,
1495                                 "Frame too long, but sent anyway.\n");
1496                 }
1497                 if (mac_rsp->flags1 & OB_MAC_IOCB_RSP_B) {
1498                         QPRINTK(qdev, TX_DONE, WARNING,
1499                                 "PCI backplane error. Frame not sent.\n");
1500                 }
1501         }
1502         atomic_inc(&tx_ring->tx_count);
1503 }
1504
1505 /* Fire up a handler to reset the MPI processor. */
1506 void ql_queue_fw_error(struct ql_adapter *qdev)
1507 {
1508         netif_stop_queue(qdev->ndev);
1509         netif_carrier_off(qdev->ndev);
1510         queue_delayed_work(qdev->workqueue, &qdev->mpi_reset_work, 0);
1511 }
1512
1513 void ql_queue_asic_error(struct ql_adapter *qdev)
1514 {
1515         netif_stop_queue(qdev->ndev);
1516         netif_carrier_off(qdev->ndev);
1517         ql_disable_interrupts(qdev);
1518         /* Clear adapter up bit to signal the recovery
1519          * process that it shouldn't kill the reset worker
1520          * thread
1521          */
1522         clear_bit(QL_ADAPTER_UP, &qdev->flags);
1523         queue_delayed_work(qdev->workqueue, &qdev->asic_reset_work, 0);
1524 }
1525
1526 static void ql_process_chip_ae_intr(struct ql_adapter *qdev,
1527                                     struct ib_ae_iocb_rsp *ib_ae_rsp)
1528 {
1529         switch (ib_ae_rsp->event) {
1530         case MGMT_ERR_EVENT:
1531                 QPRINTK(qdev, RX_ERR, ERR,
1532                         "Management Processor Fatal Error.\n");
1533                 ql_queue_fw_error(qdev);
1534                 return;
1535
1536         case CAM_LOOKUP_ERR_EVENT:
1537                 QPRINTK(qdev, LINK, ERR,
1538                         "Multiple CAM hits lookup occurred.\n");
1539                 QPRINTK(qdev, DRV, ERR, "This event shouldn't occur.\n");
1540                 ql_queue_asic_error(qdev);
1541                 return;
1542
1543         case SOFT_ECC_ERROR_EVENT:
1544                 QPRINTK(qdev, RX_ERR, ERR, "Soft ECC error detected.\n");
1545                 ql_queue_asic_error(qdev);
1546                 break;
1547
1548         case PCI_ERR_ANON_BUF_RD:
1549                 QPRINTK(qdev, RX_ERR, ERR,
1550                         "PCI error occurred when reading anonymous buffers from rx_ring %d.\n",
1551                         ib_ae_rsp->q_id);
1552                 ql_queue_asic_error(qdev);
1553                 break;
1554
1555         default:
1556                 QPRINTK(qdev, DRV, ERR, "Unexpected event %d.\n",
1557                         ib_ae_rsp->event);
1558                 ql_queue_asic_error(qdev);
1559                 break;
1560         }
1561 }
1562
1563 static int ql_clean_outbound_rx_ring(struct rx_ring *rx_ring)
1564 {
1565         struct ql_adapter *qdev = rx_ring->qdev;
1566         u32 prod = ql_read_sh_reg(rx_ring->prod_idx_sh_reg);
1567         struct ob_mac_iocb_rsp *net_rsp = NULL;
1568         int count = 0;
1569
1570         /* While there are entries in the completion queue. */
1571         while (prod != rx_ring->cnsmr_idx) {
1572
1573                 QPRINTK(qdev, RX_STATUS, DEBUG,
1574                         "cq_id = %d, prod = %d, cnsmr = %d.\n.", rx_ring->cq_id,
1575                         prod, rx_ring->cnsmr_idx);
1576
1577                 net_rsp = (struct ob_mac_iocb_rsp *)rx_ring->curr_entry;
1578                 rmb();
1579                 switch (net_rsp->opcode) {
1580
1581                 case OPCODE_OB_MAC_TSO_IOCB:
1582                 case OPCODE_OB_MAC_IOCB:
1583                         ql_process_mac_tx_intr(qdev, net_rsp);
1584                         break;
1585                 default:
1586                         QPRINTK(qdev, RX_STATUS, DEBUG,
1587                                 "Hit default case, not handled! dropping the packet, opcode = %x.\n",
1588                                 net_rsp->opcode);
1589                 }
1590                 count++;
1591                 ql_update_cq(rx_ring);
1592                 prod = ql_read_sh_reg(rx_ring->prod_idx_sh_reg);
1593         }
1594         ql_write_cq_idx(rx_ring);
1595         if (netif_queue_stopped(qdev->ndev) && net_rsp != NULL) {
1596                 struct tx_ring *tx_ring = &qdev->tx_ring[net_rsp->txq_idx];
1597                 if (atomic_read(&tx_ring->queue_stopped) &&
1598                     (atomic_read(&tx_ring->tx_count) > (tx_ring->wq_len / 4)))
1599                         /*
1600                          * The queue got stopped because the tx_ring was full.
1601                          * Wake it up, because it's now at least 25% empty.
1602                          */
1603                         netif_wake_queue(qdev->ndev);
1604         }
1605
1606         return count;
1607 }
1608
1609 static int ql_clean_inbound_rx_ring(struct rx_ring *rx_ring, int budget)
1610 {
1611         struct ql_adapter *qdev = rx_ring->qdev;
1612         u32 prod = ql_read_sh_reg(rx_ring->prod_idx_sh_reg);
1613         struct ql_net_rsp_iocb *net_rsp;
1614         int count = 0;
1615
1616         /* While there are entries in the completion queue. */
1617         while (prod != rx_ring->cnsmr_idx) {
1618
1619                 QPRINTK(qdev, RX_STATUS, DEBUG,
1620                         "cq_id = %d, prod = %d, cnsmr = %d.\n.", rx_ring->cq_id,
1621                         prod, rx_ring->cnsmr_idx);
1622
1623                 net_rsp = rx_ring->curr_entry;
1624                 rmb();
1625                 switch (net_rsp->opcode) {
1626                 case OPCODE_IB_MAC_IOCB:
1627                         ql_process_mac_rx_intr(qdev, rx_ring,
1628                                                (struct ib_mac_iocb_rsp *)
1629                                                net_rsp);
1630                         break;
1631
1632                 case OPCODE_IB_AE_IOCB:
1633                         ql_process_chip_ae_intr(qdev, (struct ib_ae_iocb_rsp *)
1634                                                 net_rsp);
1635                         break;
1636                 default:
1637                         {
1638                                 QPRINTK(qdev, RX_STATUS, DEBUG,
1639                                         "Hit default case, not handled! dropping the packet, opcode = %x.\n",
1640                                         net_rsp->opcode);
1641                         }
1642                 }
1643                 count++;
1644                 ql_update_cq(rx_ring);
1645                 prod = ql_read_sh_reg(rx_ring->prod_idx_sh_reg);
1646                 if (count == budget)
1647                         break;
1648         }
1649         ql_update_buffer_queues(qdev, rx_ring);
1650         ql_write_cq_idx(rx_ring);
1651         return count;
1652 }
1653
1654 static int ql_napi_poll_msix(struct napi_struct *napi, int budget)
1655 {
1656         struct rx_ring *rx_ring = container_of(napi, struct rx_ring, napi);
1657         struct ql_adapter *qdev = rx_ring->qdev;
1658         int work_done = ql_clean_inbound_rx_ring(rx_ring, budget);
1659
1660         QPRINTK(qdev, RX_STATUS, DEBUG, "Enter, NAPI POLL cq_id = %d.\n",
1661                 rx_ring->cq_id);
1662
1663         if (work_done < budget) {
1664                 __netif_rx_complete(napi);
1665                 ql_enable_completion_interrupt(qdev, rx_ring->irq);
1666         }
1667         return work_done;
1668 }
1669
1670 static void ql_vlan_rx_register(struct net_device *ndev, struct vlan_group *grp)
1671 {
1672         struct ql_adapter *qdev = netdev_priv(ndev);
1673
1674         qdev->vlgrp = grp;
1675         if (grp) {
1676                 QPRINTK(qdev, IFUP, DEBUG, "Turning on VLAN in NIC_RCV_CFG.\n");
1677                 ql_write32(qdev, NIC_RCV_CFG, NIC_RCV_CFG_VLAN_MASK |
1678                            NIC_RCV_CFG_VLAN_MATCH_AND_NON);
1679         } else {
1680                 QPRINTK(qdev, IFUP, DEBUG,
1681                         "Turning off VLAN in NIC_RCV_CFG.\n");
1682                 ql_write32(qdev, NIC_RCV_CFG, NIC_RCV_CFG_VLAN_MASK);
1683         }
1684 }
1685
1686 static void ql_vlan_rx_add_vid(struct net_device *ndev, u16 vid)
1687 {
1688         struct ql_adapter *qdev = netdev_priv(ndev);
1689         u32 enable_bit = MAC_ADDR_E;
1690
1691         spin_lock(&qdev->hw_lock);
1692         if (ql_set_mac_addr_reg
1693             (qdev, (u8 *) &enable_bit, MAC_ADDR_TYPE_VLAN, vid)) {
1694                 QPRINTK(qdev, IFUP, ERR, "Failed to init vlan address.\n");
1695         }
1696         spin_unlock(&qdev->hw_lock);
1697 }
1698
1699 static void ql_vlan_rx_kill_vid(struct net_device *ndev, u16 vid)
1700 {
1701         struct ql_adapter *qdev = netdev_priv(ndev);
1702         u32 enable_bit = 0;
1703
1704         spin_lock(&qdev->hw_lock);
1705         if (ql_set_mac_addr_reg
1706             (qdev, (u8 *) &enable_bit, MAC_ADDR_TYPE_VLAN, vid)) {
1707                 QPRINTK(qdev, IFUP, ERR, "Failed to clear vlan address.\n");
1708         }
1709         spin_unlock(&qdev->hw_lock);
1710
1711 }
1712
1713 /* Worker thread to process a given rx_ring that is dedicated
1714  * to outbound completions.
1715  */
1716 static void ql_tx_clean(struct work_struct *work)
1717 {
1718         struct rx_ring *rx_ring =
1719             container_of(work, struct rx_ring, rx_work.work);
1720         ql_clean_outbound_rx_ring(rx_ring);
1721         ql_enable_completion_interrupt(rx_ring->qdev, rx_ring->irq);
1722
1723 }
1724
1725 /* Worker thread to process a given rx_ring that is dedicated
1726  * to inbound completions.
1727  */
1728 static void ql_rx_clean(struct work_struct *work)
1729 {
1730         struct rx_ring *rx_ring =
1731             container_of(work, struct rx_ring, rx_work.work);
1732         ql_clean_inbound_rx_ring(rx_ring, 64);
1733         ql_enable_completion_interrupt(rx_ring->qdev, rx_ring->irq);
1734 }
1735
1736 /* MSI-X Multiple Vector Interrupt Handler for outbound completions. */
1737 static irqreturn_t qlge_msix_tx_isr(int irq, void *dev_id)
1738 {
1739         struct rx_ring *rx_ring = dev_id;
1740         queue_delayed_work_on(rx_ring->cpu, rx_ring->qdev->q_workqueue,
1741                               &rx_ring->rx_work, 0);
1742         return IRQ_HANDLED;
1743 }
1744
1745 /* MSI-X Multiple Vector Interrupt Handler for inbound completions. */
1746 static irqreturn_t qlge_msix_rx_isr(int irq, void *dev_id)
1747 {
1748         struct rx_ring *rx_ring = dev_id;
1749         netif_rx_schedule(&rx_ring->napi);
1750         return IRQ_HANDLED;
1751 }
1752
1753 /* This handles a fatal error, MPI activity, and the default
1754  * rx_ring in an MSI-X multiple vector environment.
1755  * In MSI/Legacy environment it also process the rest of
1756  * the rx_rings.
1757  */
1758 static irqreturn_t qlge_isr(int irq, void *dev_id)
1759 {
1760         struct rx_ring *rx_ring = dev_id;
1761         struct ql_adapter *qdev = rx_ring->qdev;
1762         struct intr_context *intr_context = &qdev->intr_context[0];
1763         u32 var;
1764         int i;
1765         int work_done = 0;
1766
1767         spin_lock(&qdev->hw_lock);
1768         if (atomic_read(&qdev->intr_context[0].irq_cnt)) {
1769                 QPRINTK(qdev, INTR, DEBUG, "Shared Interrupt, Not ours!\n");
1770                 spin_unlock(&qdev->hw_lock);
1771                 return IRQ_NONE;
1772         }
1773         spin_unlock(&qdev->hw_lock);
1774
1775         var = ql_disable_completion_interrupt(qdev, intr_context->intr);
1776
1777         /*
1778          * Check for fatal error.
1779          */
1780         if (var & STS_FE) {
1781                 ql_queue_asic_error(qdev);
1782                 QPRINTK(qdev, INTR, ERR, "Got fatal error, STS = %x.\n", var);
1783                 var = ql_read32(qdev, ERR_STS);
1784                 QPRINTK(qdev, INTR, ERR,
1785                         "Resetting chip. Error Status Register = 0x%x\n", var);
1786                 return IRQ_HANDLED;
1787         }
1788
1789         /*
1790          * Check MPI processor activity.
1791          */
1792         if (var & STS_PI) {
1793                 /*
1794                  * We've got an async event or mailbox completion.
1795                  * Handle it and clear the source of the interrupt.
1796                  */
1797                 QPRINTK(qdev, INTR, ERR, "Got MPI processor interrupt.\n");
1798                 ql_disable_completion_interrupt(qdev, intr_context->intr);
1799                 queue_delayed_work_on(smp_processor_id(), qdev->workqueue,
1800                                       &qdev->mpi_work, 0);
1801                 work_done++;
1802         }
1803
1804         /*
1805          * Check the default queue and wake handler if active.
1806          */
1807         rx_ring = &qdev->rx_ring[0];
1808         if (ql_read_sh_reg(rx_ring->prod_idx_sh_reg) != rx_ring->cnsmr_idx) {
1809                 QPRINTK(qdev, INTR, INFO, "Waking handler for rx_ring[0].\n");
1810                 ql_disable_completion_interrupt(qdev, intr_context->intr);
1811                 queue_delayed_work_on(smp_processor_id(), qdev->q_workqueue,
1812                                       &rx_ring->rx_work, 0);
1813                 work_done++;
1814         }
1815
1816         if (!test_bit(QL_MSIX_ENABLED, &qdev->flags)) {
1817                 /*
1818                  * Start the DPC for each active queue.
1819                  */
1820                 for (i = 1; i < qdev->rx_ring_count; i++) {
1821                         rx_ring = &qdev->rx_ring[i];
1822                         if (ql_read_sh_reg(rx_ring->prod_idx_sh_reg) !=
1823                             rx_ring->cnsmr_idx) {
1824                                 QPRINTK(qdev, INTR, INFO,
1825                                         "Waking handler for rx_ring[%d].\n", i);
1826                                 ql_disable_completion_interrupt(qdev,
1827                                                                 intr_context->
1828                                                                 intr);
1829                                 if (i < qdev->rss_ring_first_cq_id)
1830                                         queue_delayed_work_on(rx_ring->cpu,
1831                                                               qdev->q_workqueue,
1832                                                               &rx_ring->rx_work,
1833                                                               0);
1834                                 else
1835                                         netif_rx_schedule(&rx_ring->napi);
1836                                 work_done++;
1837                         }
1838                 }
1839         }
1840         ql_enable_completion_interrupt(qdev, intr_context->intr);
1841         return work_done ? IRQ_HANDLED : IRQ_NONE;
1842 }
1843
1844 static int ql_tso(struct sk_buff *skb, struct ob_mac_tso_iocb_req *mac_iocb_ptr)
1845 {
1846
1847         if (skb_is_gso(skb)) {
1848                 int err;
1849                 if (skb_header_cloned(skb)) {
1850                         err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
1851                         if (err)
1852                                 return err;
1853                 }
1854
1855                 mac_iocb_ptr->opcode = OPCODE_OB_MAC_TSO_IOCB;
1856                 mac_iocb_ptr->flags3 |= OB_MAC_TSO_IOCB_IC;
1857                 mac_iocb_ptr->frame_len = cpu_to_le32((u32) skb->len);
1858                 mac_iocb_ptr->total_hdrs_len =
1859                     cpu_to_le16(skb_transport_offset(skb) + tcp_hdrlen(skb));
1860                 mac_iocb_ptr->net_trans_offset =
1861                     cpu_to_le16(skb_network_offset(skb) |
1862                                 skb_transport_offset(skb)
1863                                 << OB_MAC_TRANSPORT_HDR_SHIFT);
1864                 mac_iocb_ptr->mss = cpu_to_le16(skb_shinfo(skb)->gso_size);
1865                 mac_iocb_ptr->flags2 |= OB_MAC_TSO_IOCB_LSO;
1866                 if (likely(skb->protocol == htons(ETH_P_IP))) {
1867                         struct iphdr *iph = ip_hdr(skb);
1868                         iph->check = 0;
1869                         mac_iocb_ptr->flags1 |= OB_MAC_TSO_IOCB_IP4;
1870                         tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
1871                                                                  iph->daddr, 0,
1872                                                                  IPPROTO_TCP,
1873                                                                  0);
1874                 } else if (skb->protocol == htons(ETH_P_IPV6)) {
1875                         mac_iocb_ptr->flags1 |= OB_MAC_TSO_IOCB_IP6;
1876                         tcp_hdr(skb)->check =
1877                             ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
1878                                              &ipv6_hdr(skb)->daddr,
1879                                              0, IPPROTO_TCP, 0);
1880                 }
1881                 return 1;
1882         }
1883         return 0;
1884 }
1885
1886 static void ql_hw_csum_setup(struct sk_buff *skb,
1887                              struct ob_mac_tso_iocb_req *mac_iocb_ptr)
1888 {
1889         int len;
1890         struct iphdr *iph = ip_hdr(skb);
1891         __sum16 *check;
1892         mac_iocb_ptr->opcode = OPCODE_OB_MAC_TSO_IOCB;
1893         mac_iocb_ptr->frame_len = cpu_to_le32((u32) skb->len);
1894         mac_iocb_ptr->net_trans_offset =
1895                 cpu_to_le16(skb_network_offset(skb) |
1896                 skb_transport_offset(skb) << OB_MAC_TRANSPORT_HDR_SHIFT);
1897
1898         mac_iocb_ptr->flags1 |= OB_MAC_TSO_IOCB_IP4;
1899         len = (ntohs(iph->tot_len) - (iph->ihl << 2));
1900         if (likely(iph->protocol == IPPROTO_TCP)) {
1901                 check = &(tcp_hdr(skb)->check);
1902                 mac_iocb_ptr->flags2 |= OB_MAC_TSO_IOCB_TC;
1903                 mac_iocb_ptr->total_hdrs_len =
1904                     cpu_to_le16(skb_transport_offset(skb) +
1905                                 (tcp_hdr(skb)->doff << 2));
1906         } else {
1907                 check = &(udp_hdr(skb)->check);
1908                 mac_iocb_ptr->flags2 |= OB_MAC_TSO_IOCB_UC;
1909                 mac_iocb_ptr->total_hdrs_len =
1910                     cpu_to_le16(skb_transport_offset(skb) +
1911                                 sizeof(struct udphdr));
1912         }
1913         *check = ~csum_tcpudp_magic(iph->saddr,
1914                                     iph->daddr, len, iph->protocol, 0);
1915 }
1916
1917 static int qlge_send(struct sk_buff *skb, struct net_device *ndev)
1918 {
1919         struct tx_ring_desc *tx_ring_desc;
1920         struct ob_mac_iocb_req *mac_iocb_ptr;
1921         struct ql_adapter *qdev = netdev_priv(ndev);
1922         int tso;
1923         struct tx_ring *tx_ring;
1924         u32 tx_ring_idx = (u32) QL_TXQ_IDX(qdev, skb);
1925
1926         tx_ring = &qdev->tx_ring[tx_ring_idx];
1927
1928         if (unlikely(atomic_read(&tx_ring->tx_count) < 2)) {
1929                 QPRINTK(qdev, TX_QUEUED, INFO,
1930                         "%s: shutting down tx queue %d du to lack of resources.\n",
1931                         __func__, tx_ring_idx);
1932                 netif_stop_queue(ndev);
1933                 atomic_inc(&tx_ring->queue_stopped);
1934                 return NETDEV_TX_BUSY;
1935         }
1936         tx_ring_desc = &tx_ring->q[tx_ring->prod_idx];
1937         mac_iocb_ptr = tx_ring_desc->queue_entry;
1938         memset((void *)mac_iocb_ptr, 0, sizeof(mac_iocb_ptr));
1939
1940         mac_iocb_ptr->opcode = OPCODE_OB_MAC_IOCB;
1941         mac_iocb_ptr->tid = tx_ring_desc->index;
1942         /* We use the upper 32-bits to store the tx queue for this IO.
1943          * When we get the completion we can use it to establish the context.
1944          */
1945         mac_iocb_ptr->txq_idx = tx_ring_idx;
1946         tx_ring_desc->skb = skb;
1947
1948         mac_iocb_ptr->frame_len = cpu_to_le16((u16) skb->len);
1949
1950         if (qdev->vlgrp && vlan_tx_tag_present(skb)) {
1951                 QPRINTK(qdev, TX_QUEUED, DEBUG, "Adding a vlan tag %d.\n",
1952                         vlan_tx_tag_get(skb));
1953                 mac_iocb_ptr->flags3 |= OB_MAC_IOCB_V;
1954                 mac_iocb_ptr->vlan_tci = cpu_to_le16(vlan_tx_tag_get(skb));
1955         }
1956         tso = ql_tso(skb, (struct ob_mac_tso_iocb_req *)mac_iocb_ptr);
1957         if (tso < 0) {
1958                 dev_kfree_skb_any(skb);
1959                 return NETDEV_TX_OK;
1960         } else if (unlikely(!tso) && (skb->ip_summed == CHECKSUM_PARTIAL)) {
1961                 ql_hw_csum_setup(skb,
1962                                  (struct ob_mac_tso_iocb_req *)mac_iocb_ptr);
1963         }
1964         if (ql_map_send(qdev, mac_iocb_ptr, skb, tx_ring_desc) !=
1965                         NETDEV_TX_OK) {
1966                 QPRINTK(qdev, TX_QUEUED, ERR,
1967                                 "Could not map the segments.\n");
1968                 return NETDEV_TX_BUSY;
1969         }
1970         QL_DUMP_OB_MAC_IOCB(mac_iocb_ptr);
1971         tx_ring->prod_idx++;
1972         if (tx_ring->prod_idx == tx_ring->wq_len)
1973                 tx_ring->prod_idx = 0;
1974         wmb();
1975
1976         ql_write_db_reg(tx_ring->prod_idx, tx_ring->prod_idx_db_reg);
1977         ndev->trans_start = jiffies;
1978         QPRINTK(qdev, TX_QUEUED, DEBUG, "tx queued, slot %d, len %d\n",
1979                 tx_ring->prod_idx, skb->len);
1980
1981         atomic_dec(&tx_ring->tx_count);
1982         return NETDEV_TX_OK;
1983 }
1984
1985 static void ql_free_shadow_space(struct ql_adapter *qdev)
1986 {
1987         if (qdev->rx_ring_shadow_reg_area) {
1988                 pci_free_consistent(qdev->pdev,
1989                                     PAGE_SIZE,
1990                                     qdev->rx_ring_shadow_reg_area,
1991                                     qdev->rx_ring_shadow_reg_dma);
1992                 qdev->rx_ring_shadow_reg_area = NULL;
1993         }
1994         if (qdev->tx_ring_shadow_reg_area) {
1995                 pci_free_consistent(qdev->pdev,
1996                                     PAGE_SIZE,
1997                                     qdev->tx_ring_shadow_reg_area,
1998                                     qdev->tx_ring_shadow_reg_dma);
1999                 qdev->tx_ring_shadow_reg_area = NULL;
2000         }
2001 }
2002
2003 static int ql_alloc_shadow_space(struct ql_adapter *qdev)
2004 {
2005         qdev->rx_ring_shadow_reg_area =
2006             pci_alloc_consistent(qdev->pdev,
2007                                  PAGE_SIZE, &qdev->rx_ring_shadow_reg_dma);
2008         if (qdev->rx_ring_shadow_reg_area == NULL) {
2009                 QPRINTK(qdev, IFUP, ERR,
2010                         "Allocation of RX shadow space failed.\n");
2011                 return -ENOMEM;
2012         }
2013         qdev->tx_ring_shadow_reg_area =
2014             pci_alloc_consistent(qdev->pdev, PAGE_SIZE,
2015                                  &qdev->tx_ring_shadow_reg_dma);
2016         if (qdev->tx_ring_shadow_reg_area == NULL) {
2017                 QPRINTK(qdev, IFUP, ERR,
2018                         "Allocation of TX shadow space failed.\n");
2019                 goto err_wqp_sh_area;
2020         }
2021         return 0;
2022
2023 err_wqp_sh_area:
2024         pci_free_consistent(qdev->pdev,
2025                             PAGE_SIZE,
2026                             qdev->rx_ring_shadow_reg_area,
2027                             qdev->rx_ring_shadow_reg_dma);
2028         return -ENOMEM;
2029 }
2030
2031 static void ql_init_tx_ring(struct ql_adapter *qdev, struct tx_ring *tx_ring)
2032 {
2033         struct tx_ring_desc *tx_ring_desc;
2034         int i;
2035         struct ob_mac_iocb_req *mac_iocb_ptr;
2036
2037         mac_iocb_ptr = tx_ring->wq_base;
2038         tx_ring_desc = tx_ring->q;
2039         for (i = 0; i < tx_ring->wq_len; i++) {
2040                 tx_ring_desc->index = i;
2041                 tx_ring_desc->skb = NULL;
2042                 tx_ring_desc->queue_entry = mac_iocb_ptr;
2043                 mac_iocb_ptr++;
2044                 tx_ring_desc++;
2045         }
2046         atomic_set(&tx_ring->tx_count, tx_ring->wq_len);
2047         atomic_set(&tx_ring->queue_stopped, 0);
2048 }
2049
2050 static void ql_free_tx_resources(struct ql_adapter *qdev,
2051                                  struct tx_ring *tx_ring)
2052 {
2053         if (tx_ring->wq_base) {
2054                 pci_free_consistent(qdev->pdev, tx_ring->wq_size,
2055                                     tx_ring->wq_base, tx_ring->wq_base_dma);
2056                 tx_ring->wq_base = NULL;
2057         }
2058         kfree(tx_ring->q);
2059         tx_ring->q = NULL;
2060 }
2061
2062 static int ql_alloc_tx_resources(struct ql_adapter *qdev,
2063                                  struct tx_ring *tx_ring)
2064 {
2065         tx_ring->wq_base =
2066             pci_alloc_consistent(qdev->pdev, tx_ring->wq_size,
2067                                  &tx_ring->wq_base_dma);
2068
2069         if ((tx_ring->wq_base == NULL)
2070             || tx_ring->wq_base_dma & (tx_ring->wq_size - 1)) {
2071                 QPRINTK(qdev, IFUP, ERR, "tx_ring alloc failed.\n");
2072                 return -ENOMEM;
2073         }
2074         tx_ring->q =
2075             kmalloc(tx_ring->wq_len * sizeof(struct tx_ring_desc), GFP_KERNEL);
2076         if (tx_ring->q == NULL)
2077                 goto err;
2078
2079         return 0;
2080 err:
2081         pci_free_consistent(qdev->pdev, tx_ring->wq_size,
2082                             tx_ring->wq_base, tx_ring->wq_base_dma);
2083         return -ENOMEM;
2084 }
2085
2086 static void ql_free_lbq_buffers(struct ql_adapter *qdev, struct rx_ring *rx_ring)
2087 {
2088         int i;
2089         struct bq_desc *lbq_desc;
2090
2091         for (i = 0; i < rx_ring->lbq_len; i++) {
2092                 lbq_desc = &rx_ring->lbq[i];
2093                 if (lbq_desc->p.lbq_page) {
2094                         pci_unmap_page(qdev->pdev,
2095                                        pci_unmap_addr(lbq_desc, mapaddr),
2096                                        pci_unmap_len(lbq_desc, maplen),
2097                                        PCI_DMA_FROMDEVICE);
2098
2099                         put_page(lbq_desc->p.lbq_page);
2100                         lbq_desc->p.lbq_page = NULL;
2101                 }
2102         }
2103 }
2104
2105 /*
2106  * Allocate and map a page for each element of the lbq.
2107  */
2108 static int ql_alloc_lbq_buffers(struct ql_adapter *qdev,
2109                                 struct rx_ring *rx_ring)
2110 {
2111         int i;
2112         struct bq_desc *lbq_desc;
2113         u64 map;
2114         __le64 *bq = rx_ring->lbq_base;
2115
2116         for (i = 0; i < rx_ring->lbq_len; i++) {
2117                 lbq_desc = &rx_ring->lbq[i];
2118                 memset(lbq_desc, 0, sizeof(lbq_desc));
2119                 lbq_desc->addr = bq;
2120                 lbq_desc->index = i;
2121                 lbq_desc->p.lbq_page = alloc_page(GFP_ATOMIC);
2122                 if (unlikely(!lbq_desc->p.lbq_page)) {
2123                         QPRINTK(qdev, IFUP, ERR, "failed alloc_page().\n");
2124                         goto mem_error;
2125                 } else {
2126                         map = pci_map_page(qdev->pdev,
2127                                            lbq_desc->p.lbq_page,
2128                                            0, PAGE_SIZE, PCI_DMA_FROMDEVICE);
2129                         if (pci_dma_mapping_error(qdev->pdev, map)) {
2130                                 QPRINTK(qdev, IFUP, ERR,
2131                                         "PCI mapping failed.\n");
2132                                 goto mem_error;
2133                         }
2134                         pci_unmap_addr_set(lbq_desc, mapaddr, map);
2135                         pci_unmap_len_set(lbq_desc, maplen, PAGE_SIZE);
2136                         *lbq_desc->addr = cpu_to_le64(map);
2137                 }
2138                 bq++;
2139         }
2140         return 0;
2141 mem_error:
2142         ql_free_lbq_buffers(qdev, rx_ring);
2143         return -ENOMEM;
2144 }
2145
2146 static void ql_free_sbq_buffers(struct ql_adapter *qdev, struct rx_ring *rx_ring)
2147 {
2148         int i;
2149         struct bq_desc *sbq_desc;
2150
2151         for (i = 0; i < rx_ring->sbq_len; i++) {
2152                 sbq_desc = &rx_ring->sbq[i];
2153                 if (sbq_desc == NULL) {
2154                         QPRINTK(qdev, IFUP, ERR, "sbq_desc %d is NULL.\n", i);
2155                         return;
2156                 }
2157                 if (sbq_desc->p.skb) {
2158                         pci_unmap_single(qdev->pdev,
2159                                          pci_unmap_addr(sbq_desc, mapaddr),
2160                                          pci_unmap_len(sbq_desc, maplen),
2161                                          PCI_DMA_FROMDEVICE);
2162                         dev_kfree_skb(sbq_desc->p.skb);
2163                         sbq_desc->p.skb = NULL;
2164                 }
2165         }
2166 }
2167
2168 /* Allocate and map an skb for each element of the sbq. */
2169 static int ql_alloc_sbq_buffers(struct ql_adapter *qdev,
2170                                 struct rx_ring *rx_ring)
2171 {
2172         int i;
2173         struct bq_desc *sbq_desc;
2174         struct sk_buff *skb;
2175         u64 map;
2176         __le64 *bq = rx_ring->sbq_base;
2177
2178         for (i = 0; i < rx_ring->sbq_len; i++) {
2179                 sbq_desc = &rx_ring->sbq[i];
2180                 memset(sbq_desc, 0, sizeof(sbq_desc));
2181                 sbq_desc->index = i;
2182                 sbq_desc->addr = bq;
2183                 skb = netdev_alloc_skb(qdev->ndev, rx_ring->sbq_buf_size);
2184                 if (unlikely(!skb)) {
2185                         /* Better luck next round */
2186                         QPRINTK(qdev, IFUP, ERR,
2187                                 "small buff alloc failed for %d bytes at index %d.\n",
2188                                 rx_ring->sbq_buf_size, i);
2189                         goto mem_err;
2190                 }
2191                 skb_reserve(skb, QLGE_SB_PAD);
2192                 sbq_desc->p.skb = skb;
2193                 /*
2194                  * Map only half the buffer. Because the
2195                  * other half may get some data copied to it
2196                  * when the completion arrives.
2197                  */
2198                 map = pci_map_single(qdev->pdev,
2199                                      skb->data,
2200                                      rx_ring->sbq_buf_size / 2,
2201                                      PCI_DMA_FROMDEVICE);
2202                 if (pci_dma_mapping_error(qdev->pdev, map)) {
2203                         QPRINTK(qdev, IFUP, ERR, "PCI mapping failed.\n");
2204                         goto mem_err;
2205                 }
2206                 pci_unmap_addr_set(sbq_desc, mapaddr, map);
2207                 pci_unmap_len_set(sbq_desc, maplen, rx_ring->sbq_buf_size / 2);
2208                 *sbq_desc->addr = cpu_to_le64(map);
2209                 bq++;
2210         }
2211         return 0;
2212 mem_err:
2213         ql_free_sbq_buffers(qdev, rx_ring);
2214         return -ENOMEM;
2215 }
2216
2217 static void ql_free_rx_resources(struct ql_adapter *qdev,
2218                                  struct rx_ring *rx_ring)
2219 {
2220         if (rx_ring->sbq_len)
2221                 ql_free_sbq_buffers(qdev, rx_ring);
2222         if (rx_ring->lbq_len)
2223                 ql_free_lbq_buffers(qdev, rx_ring);
2224
2225         /* Free the small buffer queue. */
2226         if (rx_ring->sbq_base) {
2227                 pci_free_consistent(qdev->pdev,
2228                                     rx_ring->sbq_size,
2229                                     rx_ring->sbq_base, rx_ring->sbq_base_dma);
2230                 rx_ring->sbq_base = NULL;
2231         }
2232
2233         /* Free the small buffer queue control blocks. */
2234         kfree(rx_ring->sbq);
2235         rx_ring->sbq = NULL;
2236
2237         /* Free the large buffer queue. */
2238         if (rx_ring->lbq_base) {
2239                 pci_free_consistent(qdev->pdev,
2240                                     rx_ring->lbq_size,
2241                                     rx_ring->lbq_base, rx_ring->lbq_base_dma);
2242                 rx_ring->lbq_base = NULL;
2243         }
2244
2245         /* Free the large buffer queue control blocks. */
2246         kfree(rx_ring->lbq);
2247         rx_ring->lbq = NULL;
2248
2249         /* Free the rx queue. */
2250         if (rx_ring->cq_base) {
2251                 pci_free_consistent(qdev->pdev,
2252                                     rx_ring->cq_size,
2253                                     rx_ring->cq_base, rx_ring->cq_base_dma);
2254                 rx_ring->cq_base = NULL;
2255         }
2256 }
2257
2258 /* Allocate queues and buffers for this completions queue based
2259  * on the values in the parameter structure. */
2260 static int ql_alloc_rx_resources(struct ql_adapter *qdev,
2261                                  struct rx_ring *rx_ring)
2262 {
2263
2264         /*
2265          * Allocate the completion queue for this rx_ring.
2266          */
2267         rx_ring->cq_base =
2268             pci_alloc_consistent(qdev->pdev, rx_ring->cq_size,
2269                                  &rx_ring->cq_base_dma);
2270
2271         if (rx_ring->cq_base == NULL) {
2272                 QPRINTK(qdev, IFUP, ERR, "rx_ring alloc failed.\n");
2273                 return -ENOMEM;
2274         }
2275
2276         if (rx_ring->sbq_len) {
2277                 /*
2278                  * Allocate small buffer queue.
2279                  */
2280                 rx_ring->sbq_base =
2281                     pci_alloc_consistent(qdev->pdev, rx_ring->sbq_size,
2282                                          &rx_ring->sbq_base_dma);
2283
2284                 if (rx_ring->sbq_base == NULL) {
2285                         QPRINTK(qdev, IFUP, ERR,
2286                                 "Small buffer queue allocation failed.\n");
2287                         goto err_mem;
2288                 }
2289
2290                 /*
2291                  * Allocate small buffer queue control blocks.
2292                  */
2293                 rx_ring->sbq =
2294                     kmalloc(rx_ring->sbq_len * sizeof(struct bq_desc),
2295                             GFP_KERNEL);
2296                 if (rx_ring->sbq == NULL) {
2297                         QPRINTK(qdev, IFUP, ERR,
2298                                 "Small buffer queue control block allocation failed.\n");
2299                         goto err_mem;
2300                 }
2301
2302                 if (ql_alloc_sbq_buffers(qdev, rx_ring)) {
2303                         QPRINTK(qdev, IFUP, ERR,
2304                                 "Small buffer allocation failed.\n");
2305                         goto err_mem;
2306                 }
2307         }
2308
2309         if (rx_ring->lbq_len) {
2310                 /*
2311                  * Allocate large buffer queue.
2312                  */
2313                 rx_ring->lbq_base =
2314                     pci_alloc_consistent(qdev->pdev, rx_ring->lbq_size,
2315                                          &rx_ring->lbq_base_dma);
2316
2317                 if (rx_ring->lbq_base == NULL) {
2318                         QPRINTK(qdev, IFUP, ERR,
2319                                 "Large buffer queue allocation failed.\n");
2320                         goto err_mem;
2321                 }
2322                 /*
2323                  * Allocate large buffer queue control blocks.
2324                  */
2325                 rx_ring->lbq =
2326                     kmalloc(rx_ring->lbq_len * sizeof(struct bq_desc),
2327                             GFP_KERNEL);
2328                 if (rx_ring->lbq == NULL) {
2329                         QPRINTK(qdev, IFUP, ERR,
2330                                 "Large buffer queue control block allocation failed.\n");
2331                         goto err_mem;
2332                 }
2333
2334                 /*
2335                  * Allocate the buffers.
2336                  */
2337                 if (ql_alloc_lbq_buffers(qdev, rx_ring)) {
2338                         QPRINTK(qdev, IFUP, ERR,
2339                                 "Large buffer allocation failed.\n");
2340                         goto err_mem;
2341                 }
2342         }
2343
2344         return 0;
2345
2346 err_mem:
2347         ql_free_rx_resources(qdev, rx_ring);
2348         return -ENOMEM;
2349 }
2350
2351 static void ql_tx_ring_clean(struct ql_adapter *qdev)
2352 {
2353         struct tx_ring *tx_ring;
2354         struct tx_ring_desc *tx_ring_desc;
2355         int i, j;
2356
2357         /*
2358          * Loop through all queues and free
2359          * any resources.
2360          */
2361         for (j = 0; j < qdev->tx_ring_count; j++) {
2362                 tx_ring = &qdev->tx_ring[j];
2363                 for (i = 0; i < tx_ring->wq_len; i++) {
2364                         tx_ring_desc = &tx_ring->q[i];
2365                         if (tx_ring_desc && tx_ring_desc->skb) {
2366                                 QPRINTK(qdev, IFDOWN, ERR,
2367                                 "Freeing lost SKB %p, from queue %d, index %d.\n",
2368                                         tx_ring_desc->skb, j,
2369                                         tx_ring_desc->index);
2370                                 ql_unmap_send(qdev, tx_ring_desc,
2371                                               tx_ring_desc->map_cnt);
2372                                 dev_kfree_skb(tx_ring_desc->skb);
2373                                 tx_ring_desc->skb = NULL;
2374                         }
2375                 }
2376         }
2377 }
2378
2379 static void ql_free_mem_resources(struct ql_adapter *qdev)
2380 {
2381         int i;
2382
2383         for (i = 0; i < qdev->tx_ring_count; i++)
2384                 ql_free_tx_resources(qdev, &qdev->tx_ring[i]);
2385         for (i = 0; i < qdev->rx_ring_count; i++)
2386                 ql_free_rx_resources(qdev, &qdev->rx_ring[i]);
2387         ql_free_shadow_space(qdev);
2388 }
2389
2390 static int ql_alloc_mem_resources(struct ql_adapter *qdev)
2391 {
2392         int i;
2393
2394         /* Allocate space for our shadow registers and such. */
2395         if (ql_alloc_shadow_space(qdev))
2396                 return -ENOMEM;
2397
2398         for (i = 0; i < qdev->rx_ring_count; i++) {
2399                 if (ql_alloc_rx_resources(qdev, &qdev->rx_ring[i]) != 0) {
2400                         QPRINTK(qdev, IFUP, ERR,
2401                                 "RX resource allocation failed.\n");
2402                         goto err_mem;
2403                 }
2404         }
2405         /* Allocate tx queue resources */
2406         for (i = 0; i < qdev->tx_ring_count; i++) {
2407                 if (ql_alloc_tx_resources(qdev, &qdev->tx_ring[i]) != 0) {
2408                         QPRINTK(qdev, IFUP, ERR,
2409                                 "TX resource allocation failed.\n");
2410                         goto err_mem;
2411                 }
2412         }
2413         return 0;
2414
2415 err_mem:
2416         ql_free_mem_resources(qdev);
2417         return -ENOMEM;
2418 }
2419
2420 /* Set up the rx ring control block and pass it to the chip.
2421  * The control block is defined as
2422  * "Completion Queue Initialization Control Block", or cqicb.
2423  */
2424 static int ql_start_rx_ring(struct ql_adapter *qdev, struct rx_ring *rx_ring)
2425 {
2426         struct cqicb *cqicb = &rx_ring->cqicb;
2427         void *shadow_reg = qdev->rx_ring_shadow_reg_area +
2428             (rx_ring->cq_id * sizeof(u64) * 4);
2429         u64 shadow_reg_dma = qdev->rx_ring_shadow_reg_dma +
2430             (rx_ring->cq_id * sizeof(u64) * 4);
2431         void __iomem *doorbell_area =
2432             qdev->doorbell_area + (DB_PAGE_SIZE * (128 + rx_ring->cq_id));
2433         int err = 0;
2434         u16 bq_len;
2435
2436         /* Set up the shadow registers for this ring. */
2437         rx_ring->prod_idx_sh_reg = shadow_reg;
2438         rx_ring->prod_idx_sh_reg_dma = shadow_reg_dma;
2439         shadow_reg += sizeof(u64);
2440         shadow_reg_dma += sizeof(u64);
2441         rx_ring->lbq_base_indirect = shadow_reg;
2442         rx_ring->lbq_base_indirect_dma = shadow_reg_dma;
2443         shadow_reg += sizeof(u64);
2444         shadow_reg_dma += sizeof(u64);
2445         rx_ring->sbq_base_indirect = shadow_reg;
2446         rx_ring->sbq_base_indirect_dma = shadow_reg_dma;
2447
2448         /* PCI doorbell mem area + 0x00 for consumer index register */
2449         rx_ring->cnsmr_idx_db_reg = (u32 __iomem *) doorbell_area;
2450         rx_ring->cnsmr_idx = 0;
2451         rx_ring->curr_entry = rx_ring->cq_base;
2452
2453         /* PCI doorbell mem area + 0x04 for valid register */
2454         rx_ring->valid_db_reg = doorbell_area + 0x04;
2455
2456         /* PCI doorbell mem area + 0x18 for large buffer consumer */
2457         rx_ring->lbq_prod_idx_db_reg = (u32 __iomem *) (doorbell_area + 0x18);
2458
2459         /* PCI doorbell mem area + 0x1c */
2460         rx_ring->sbq_prod_idx_db_reg = (u32 __iomem *) (doorbell_area + 0x1c);
2461
2462         memset((void *)cqicb, 0, sizeof(struct cqicb));
2463         cqicb->msix_vect = rx_ring->irq;
2464
2465         bq_len = (rx_ring->cq_len == 65536) ? 0 : (u16) rx_ring->cq_len;
2466         cqicb->len = cpu_to_le16(bq_len | LEN_V | LEN_CPP_CONT);
2467
2468         cqicb->addr = cpu_to_le64(rx_ring->cq_base_dma);
2469
2470         cqicb->prod_idx_addr = cpu_to_le64(rx_ring->prod_idx_sh_reg_dma);
2471
2472         /*
2473          * Set up the control block load flags.
2474          */
2475         cqicb->flags = FLAGS_LC |       /* Load queue base address */
2476             FLAGS_LV |          /* Load MSI-X vector */
2477             FLAGS_LI;           /* Load irq delay values */
2478         if (rx_ring->lbq_len) {
2479                 cqicb->flags |= FLAGS_LL;       /* Load lbq values */
2480                 *((u64 *) rx_ring->lbq_base_indirect) = rx_ring->lbq_base_dma;
2481                 cqicb->lbq_addr =
2482                     cpu_to_le64(rx_ring->lbq_base_indirect_dma);
2483                 bq_len = (rx_ring->lbq_buf_size == 65536) ? 0 :
2484                         (u16) rx_ring->lbq_buf_size;
2485                 cqicb->lbq_buf_size = cpu_to_le16(bq_len);
2486                 bq_len = (rx_ring->lbq_len == 65536) ? 0 :
2487                         (u16) rx_ring->lbq_len;
2488                 cqicb->lbq_len = cpu_to_le16(bq_len);
2489                 rx_ring->lbq_prod_idx = rx_ring->lbq_len - 16;
2490                 rx_ring->lbq_curr_idx = 0;
2491                 rx_ring->lbq_clean_idx = rx_ring->lbq_prod_idx;
2492                 rx_ring->lbq_free_cnt = 16;
2493         }
2494         if (rx_ring->sbq_len) {
2495                 cqicb->flags |= FLAGS_LS;       /* Load sbq values */
2496                 *((u64 *) rx_ring->sbq_base_indirect) = rx_ring->sbq_base_dma;
2497                 cqicb->sbq_addr =
2498                     cpu_to_le64(rx_ring->sbq_base_indirect_dma);
2499                 cqicb->sbq_buf_size =
2500                     cpu_to_le16(((rx_ring->sbq_buf_size / 2) + 8) & 0xfffffff8);
2501                 bq_len = (rx_ring->sbq_len == 65536) ? 0 :
2502                         (u16) rx_ring->sbq_len;
2503                 cqicb->sbq_len = cpu_to_le16(bq_len);
2504                 rx_ring->sbq_prod_idx = rx_ring->sbq_len - 16;
2505                 rx_ring->sbq_curr_idx = 0;
2506                 rx_ring->sbq_clean_idx = rx_ring->sbq_prod_idx;
2507                 rx_ring->sbq_free_cnt = 16;
2508         }
2509         switch (rx_ring->type) {
2510         case TX_Q:
2511                 /* If there's only one interrupt, then we use
2512                  * worker threads to process the outbound
2513                  * completion handling rx_rings. We do this so
2514                  * they can be run on multiple CPUs. There is
2515                  * room to play with this more where we would only
2516                  * run in a worker if there are more than x number
2517                  * of outbound completions on the queue and more
2518                  * than one queue active.  Some threshold that
2519                  * would indicate a benefit in spite of the cost
2520                  * of a context switch.
2521                  * If there's more than one interrupt, then the
2522                  * outbound completions are processed in the ISR.
2523                  */
2524                 if (!test_bit(QL_MSIX_ENABLED, &qdev->flags))
2525                         INIT_DELAYED_WORK(&rx_ring->rx_work, ql_tx_clean);
2526                 else {
2527                         /* With all debug warnings on we see a WARN_ON message
2528                          * when we free the skb in the interrupt context.
2529                          */
2530                         INIT_DELAYED_WORK(&rx_ring->rx_work, ql_tx_clean);
2531                 }
2532                 cqicb->irq_delay = cpu_to_le16(qdev->tx_coalesce_usecs);
2533                 cqicb->pkt_delay = cpu_to_le16(qdev->tx_max_coalesced_frames);
2534                 break;
2535         case DEFAULT_Q:
2536                 INIT_DELAYED_WORK(&rx_ring->rx_work, ql_rx_clean);
2537                 cqicb->irq_delay = 0;
2538                 cqicb->pkt_delay = 0;
2539                 break;
2540         case RX_Q:
2541                 /* Inbound completion handling rx_rings run in
2542                  * separate NAPI contexts.
2543                  */
2544                 netif_napi_add(qdev->ndev, &rx_ring->napi, ql_napi_poll_msix,
2545                                64);
2546                 cqicb->irq_delay = cpu_to_le16(qdev->rx_coalesce_usecs);
2547                 cqicb->pkt_delay = cpu_to_le16(qdev->rx_max_coalesced_frames);
2548                 break;
2549         default:
2550                 QPRINTK(qdev, IFUP, DEBUG, "Invalid rx_ring->type = %d.\n",
2551                         rx_ring->type);
2552         }
2553         QPRINTK(qdev, IFUP, INFO, "Initializing rx work queue.\n");
2554         err = ql_write_cfg(qdev, cqicb, sizeof(struct cqicb),
2555                            CFG_LCQ, rx_ring->cq_id);
2556         if (err) {
2557                 QPRINTK(qdev, IFUP, ERR, "Failed to load CQICB.\n");
2558                 return err;
2559         }
2560         QPRINTK(qdev, IFUP, INFO, "Successfully loaded CQICB.\n");
2561         /*
2562          * Advance the producer index for the buffer queues.
2563          */
2564         wmb();
2565         if (rx_ring->lbq_len)
2566                 ql_write_db_reg(rx_ring->lbq_prod_idx,
2567                                 rx_ring->lbq_prod_idx_db_reg);
2568         if (rx_ring->sbq_len)
2569                 ql_write_db_reg(rx_ring->sbq_prod_idx,
2570                                 rx_ring->sbq_prod_idx_db_reg);
2571         return err;
2572 }
2573
2574 static int ql_start_tx_ring(struct ql_adapter *qdev, struct tx_ring *tx_ring)
2575 {
2576         struct wqicb *wqicb = (struct wqicb *)tx_ring;
2577         void __iomem *doorbell_area =
2578             qdev->doorbell_area + (DB_PAGE_SIZE * tx_ring->wq_id);
2579         void *shadow_reg = qdev->tx_ring_shadow_reg_area +
2580             (tx_ring->wq_id * sizeof(u64));
2581         u64 shadow_reg_dma = qdev->tx_ring_shadow_reg_dma +
2582             (tx_ring->wq_id * sizeof(u64));
2583         int err = 0;
2584
2585         /*
2586          * Assign doorbell registers for this tx_ring.
2587          */
2588         /* TX PCI doorbell mem area for tx producer index */
2589         tx_ring->prod_idx_db_reg = (u32 __iomem *) doorbell_area;
2590         tx_ring->prod_idx = 0;
2591         /* TX PCI doorbell mem area + 0x04 */
2592         tx_ring->valid_db_reg = doorbell_area + 0x04;
2593
2594         /*
2595          * Assign shadow registers for this tx_ring.
2596          */
2597         tx_ring->cnsmr_idx_sh_reg = shadow_reg;
2598         tx_ring->cnsmr_idx_sh_reg_dma = shadow_reg_dma;
2599
2600         wqicb->len = cpu_to_le16(tx_ring->wq_len | Q_LEN_V | Q_LEN_CPP_CONT);
2601         wqicb->flags = cpu_to_le16(Q_FLAGS_LC |
2602                                    Q_FLAGS_LB | Q_FLAGS_LI | Q_FLAGS_LO);
2603         wqicb->cq_id_rss = cpu_to_le16(tx_ring->cq_id);
2604         wqicb->rid = 0;
2605         wqicb->addr = cpu_to_le64(tx_ring->wq_base_dma);
2606
2607         wqicb->cnsmr_idx_addr = cpu_to_le64(tx_ring->cnsmr_idx_sh_reg_dma);
2608
2609         ql_init_tx_ring(qdev, tx_ring);
2610
2611         err = ql_write_cfg(qdev, wqicb, sizeof(wqicb), CFG_LRQ,
2612                            (u16) tx_ring->wq_id);
2613         if (err) {
2614                 QPRINTK(qdev, IFUP, ERR, "Failed to load tx_ring.\n");
2615                 return err;
2616         }
2617         QPRINTK(qdev, IFUP, INFO, "Successfully loaded WQICB.\n");
2618         return err;
2619 }
2620
2621 static void ql_disable_msix(struct ql_adapter *qdev)
2622 {
2623         if (test_bit(QL_MSIX_ENABLED, &qdev->flags)) {
2624                 pci_disable_msix(qdev->pdev);
2625                 clear_bit(QL_MSIX_ENABLED, &qdev->flags);
2626                 kfree(qdev->msi_x_entry);
2627                 qdev->msi_x_entry = NULL;
2628         } else if (test_bit(QL_MSI_ENABLED, &qdev->flags)) {
2629                 pci_disable_msi(qdev->pdev);
2630                 clear_bit(QL_MSI_ENABLED, &qdev->flags);
2631         }
2632 }
2633
2634 static void ql_enable_msix(struct ql_adapter *qdev)
2635 {
2636         int i;
2637
2638         qdev->intr_count = 1;
2639         /* Get the MSIX vectors. */
2640         if (irq_type == MSIX_IRQ) {
2641                 /* Try to alloc space for the msix struct,
2642                  * if it fails then go to MSI/legacy.
2643                  */
2644                 qdev->msi_x_entry = kcalloc(qdev->rx_ring_count,
2645                                             sizeof(struct msix_entry),
2646                                             GFP_KERNEL);
2647                 if (!qdev->msi_x_entry) {
2648                         irq_type = MSI_IRQ;
2649                         goto msi;
2650                 }
2651
2652                 for (i = 0; i < qdev->rx_ring_count; i++)
2653                         qdev->msi_x_entry[i].entry = i;
2654
2655                 if (!pci_enable_msix
2656                     (qdev->pdev, qdev->msi_x_entry, qdev->rx_ring_count)) {
2657                         set_bit(QL_MSIX_ENABLED, &qdev->flags);
2658                         qdev->intr_count = qdev->rx_ring_count;
2659                         QPRINTK(qdev, IFUP, INFO,
2660                                 "MSI-X Enabled, got %d vectors.\n",
2661                                 qdev->intr_count);
2662                         return;
2663                 } else {
2664                         kfree(qdev->msi_x_entry);
2665                         qdev->msi_x_entry = NULL;
2666                         QPRINTK(qdev, IFUP, WARNING,
2667                                 "MSI-X Enable failed, trying MSI.\n");
2668                         irq_type = MSI_IRQ;
2669                 }
2670         }
2671 msi:
2672         if (irq_type == MSI_IRQ) {
2673                 if (!pci_enable_msi(qdev->pdev)) {
2674                         set_bit(QL_MSI_ENABLED, &qdev->flags);
2675                         QPRINTK(qdev, IFUP, INFO,
2676                                 "Running with MSI interrupts.\n");
2677                         return;
2678                 }
2679         }
2680         irq_type = LEG_IRQ;
2681         QPRINTK(qdev, IFUP, DEBUG, "Running with legacy interrupts.\n");
2682 }
2683
2684 /*
2685  * Here we build the intr_context structures based on
2686  * our rx_ring count and intr vector count.
2687  * The intr_context structure is used to hook each vector
2688  * to possibly different handlers.
2689  */
2690 static void ql_resolve_queues_to_irqs(struct ql_adapter *qdev)
2691 {
2692         int i = 0;
2693         struct intr_context *intr_context = &qdev->intr_context[0];
2694
2695         ql_enable_msix(qdev);
2696
2697         if (likely(test_bit(QL_MSIX_ENABLED, &qdev->flags))) {
2698                 /* Each rx_ring has it's
2699                  * own intr_context since we have separate
2700                  * vectors for each queue.
2701                  * This only true when MSI-X is enabled.
2702                  */
2703                 for (i = 0; i < qdev->intr_count; i++, intr_context++) {
2704                         qdev->rx_ring[i].irq = i;
2705                         intr_context->intr = i;
2706                         intr_context->qdev = qdev;
2707                         /*
2708                          * We set up each vectors enable/disable/read bits so
2709                          * there's no bit/mask calculations in the critical path.
2710                          */
2711                         intr_context->intr_en_mask =
2712                             INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK |
2713                             INTR_EN_TYPE_ENABLE | INTR_EN_IHD_MASK | INTR_EN_IHD
2714                             | i;
2715                         intr_context->intr_dis_mask =
2716                             INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK |
2717                             INTR_EN_TYPE_DISABLE | INTR_EN_IHD_MASK |
2718                             INTR_EN_IHD | i;
2719                         intr_context->intr_read_mask =
2720                             INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK |
2721                             INTR_EN_TYPE_READ | INTR_EN_IHD_MASK | INTR_EN_IHD |
2722                             i;
2723
2724                         if (i == 0) {
2725                                 /*
2726                                  * Default queue handles bcast/mcast plus
2727                                  * async events.  Needs buffers.
2728                                  */
2729                                 intr_context->handler = qlge_isr;
2730                                 sprintf(intr_context->name, "%s-default-queue",
2731                                         qdev->ndev->name);
2732                         } else if (i < qdev->rss_ring_first_cq_id) {
2733                                 /*
2734                                  * Outbound queue is for outbound completions only.
2735                                  */
2736                                 intr_context->handler = qlge_msix_tx_isr;
2737                                 sprintf(intr_context->name, "%s-tx-%d",
2738                                         qdev->ndev->name, i);
2739                         } else {
2740                                 /*
2741                                  * Inbound queues handle unicast frames only.
2742                                  */
2743                                 intr_context->handler = qlge_msix_rx_isr;
2744                                 sprintf(intr_context->name, "%s-rx-%d",
2745                                         qdev->ndev->name, i);
2746                         }
2747                 }
2748         } else {
2749                 /*
2750                  * All rx_rings use the same intr_context since
2751                  * there is only one vector.
2752                  */
2753                 intr_context->intr = 0;
2754                 intr_context->qdev = qdev;
2755                 /*
2756                  * We set up each vectors enable/disable/read bits so
2757                  * there's no bit/mask calculations in the critical path.
2758                  */
2759                 intr_context->intr_en_mask =
2760                     INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK | INTR_EN_TYPE_ENABLE;
2761                 intr_context->intr_dis_mask =
2762                     INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK |
2763                     INTR_EN_TYPE_DISABLE;
2764                 intr_context->intr_read_mask =
2765                     INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK | INTR_EN_TYPE_READ;
2766                 /*
2767                  * Single interrupt means one handler for all rings.
2768                  */
2769                 intr_context->handler = qlge_isr;
2770                 sprintf(intr_context->name, "%s-single_irq", qdev->ndev->name);
2771                 for (i = 0; i < qdev->rx_ring_count; i++)
2772                         qdev->rx_ring[i].irq = 0;
2773         }
2774 }
2775
2776 static void ql_free_irq(struct ql_adapter *qdev)
2777 {
2778         int i;
2779         struct intr_context *intr_context = &qdev->intr_context[0];
2780
2781         for (i = 0; i < qdev->intr_count; i++, intr_context++) {
2782                 if (intr_context->hooked) {
2783                         if (test_bit(QL_MSIX_ENABLED, &qdev->flags)) {
2784                                 free_irq(qdev->msi_x_entry[i].vector,
2785                                          &qdev->rx_ring[i]);
2786                                 QPRINTK(qdev, IFDOWN, ERR,
2787                                         "freeing msix interrupt %d.\n", i);
2788                         } else {
2789                                 free_irq(qdev->pdev->irq, &qdev->rx_ring[0]);
2790                                 QPRINTK(qdev, IFDOWN, ERR,
2791                                         "freeing msi interrupt %d.\n", i);
2792                         }
2793                 }
2794         }
2795         ql_disable_msix(qdev);
2796 }
2797
2798 static int ql_request_irq(struct ql_adapter *qdev)
2799 {
2800         int i;
2801         int status = 0;
2802         struct pci_dev *pdev = qdev->pdev;
2803         struct intr_context *intr_context = &qdev->intr_context[0];
2804
2805         ql_resolve_queues_to_irqs(qdev);
2806
2807         for (i = 0; i < qdev->intr_count; i++, intr_context++) {
2808                 atomic_set(&intr_context->irq_cnt, 0);
2809                 if (test_bit(QL_MSIX_ENABLED, &qdev->flags)) {
2810                         status = request_irq(qdev->msi_x_entry[i].vector,
2811                                              intr_context->handler,
2812                                              0,
2813                                              intr_context->name,
2814                                              &qdev->rx_ring[i]);
2815                         if (status) {
2816                                 QPRINTK(qdev, IFUP, ERR,
2817                                         "Failed request for MSIX interrupt %d.\n",
2818                                         i);
2819                                 goto err_irq;
2820                         } else {
2821                                 QPRINTK(qdev, IFUP, INFO,
2822                                         "Hooked intr %d, queue type %s%s%s, with name %s.\n",
2823                                         i,
2824                                         qdev->rx_ring[i].type ==
2825                                         DEFAULT_Q ? "DEFAULT_Q" : "",
2826                                         qdev->rx_ring[i].type ==
2827                                         TX_Q ? "TX_Q" : "",
2828                                         qdev->rx_ring[i].type ==
2829                                         RX_Q ? "RX_Q" : "", intr_context->name);
2830                         }
2831                 } else {
2832                         QPRINTK(qdev, IFUP, DEBUG,
2833                                 "trying msi or legacy interrupts.\n");
2834                         QPRINTK(qdev, IFUP, DEBUG,
2835                                 "%s: irq = %d.\n", __func__, pdev->irq);
2836                         QPRINTK(qdev, IFUP, DEBUG,
2837                                 "%s: context->name = %s.\n", __func__,
2838                                intr_context->name);
2839                         QPRINTK(qdev, IFUP, DEBUG,
2840                                 "%s: dev_id = 0x%p.\n", __func__,
2841                                &qdev->rx_ring[0]);
2842                         status =
2843                             request_irq(pdev->irq, qlge_isr,
2844                                         test_bit(QL_MSI_ENABLED,
2845                                                  &qdev->
2846                                                  flags) ? 0 : IRQF_SHARED,
2847                                         intr_context->name, &qdev->rx_ring[0]);
2848                         if (status)
2849                                 goto err_irq;
2850
2851                         QPRINTK(qdev, IFUP, ERR,
2852                                 "Hooked intr %d, queue type %s%s%s, with name %s.\n",
2853                                 i,
2854                                 qdev->rx_ring[0].type ==
2855                                 DEFAULT_Q ? "DEFAULT_Q" : "",
2856                                 qdev->rx_ring[0].type == TX_Q ? "TX_Q" : "",
2857                                 qdev->rx_ring[0].type == RX_Q ? "RX_Q" : "",
2858                                 intr_context->name);
2859                 }
2860                 intr_context->hooked = 1;
2861         }
2862         return status;
2863 err_irq:
2864         QPRINTK(qdev, IFUP, ERR, "Failed to get the interrupts!!!/n");
2865         ql_free_irq(qdev);
2866         return status;
2867 }
2868
2869 static int ql_start_rss(struct ql_adapter *qdev)
2870 {
2871         struct ricb *ricb = &qdev->ricb;
2872         int status = 0;
2873         int i;
2874         u8 *hash_id = (u8 *) ricb->hash_cq_id;
2875
2876         memset((void *)ricb, 0, sizeof(ricb));
2877
2878         ricb->base_cq = qdev->rss_ring_first_cq_id | RSS_L4K;
2879         ricb->flags =
2880             (RSS_L6K | RSS_LI | RSS_LB | RSS_LM | RSS_RI4 | RSS_RI6 | RSS_RT4 |
2881              RSS_RT6);
2882         ricb->mask = cpu_to_le16(qdev->rss_ring_count - 1);
2883
2884         /*
2885          * Fill out the Indirection Table.
2886          */
2887         for (i = 0; i < 32; i++)
2888                 hash_id[i] = i & 1;
2889
2890         /*
2891          * Random values for the IPv6 and IPv4 Hash Keys.
2892          */
2893         get_random_bytes((void *)&ricb->ipv6_hash_key[0], 40);
2894         get_random_bytes((void *)&ricb->ipv4_hash_key[0], 16);
2895
2896         QPRINTK(qdev, IFUP, INFO, "Initializing RSS.\n");
2897
2898         status = ql_write_cfg(qdev, ricb, sizeof(ricb), CFG_LR, 0);
2899         if (status) {
2900                 QPRINTK(qdev, IFUP, ERR, "Failed to load RICB.\n");
2901                 return status;
2902         }
2903         QPRINTK(qdev, IFUP, INFO, "Successfully loaded RICB.\n");
2904         return status;
2905 }
2906
2907 /* Initialize the frame-to-queue routing. */
2908 static int ql_route_initialize(struct ql_adapter *qdev)
2909 {
2910         int status = 0;
2911         int i;
2912
2913         /* Clear all the entries in the routing table. */
2914         for (i = 0; i < 16; i++) {
2915                 status = ql_set_routing_reg(qdev, i, 0, 0);
2916                 if (status) {
2917                         QPRINTK(qdev, IFUP, ERR,
2918                                 "Failed to init routing register for CAM packets.\n");
2919                         return status;
2920                 }
2921         }
2922
2923         status = ql_set_routing_reg(qdev, RT_IDX_ALL_ERR_SLOT, RT_IDX_ERR, 1);
2924         if (status) {
2925                 QPRINTK(qdev, IFUP, ERR,
2926                         "Failed to init routing register for error packets.\n");
2927                 return status;
2928         }
2929         status = ql_set_routing_reg(qdev, RT_IDX_BCAST_SLOT, RT_IDX_BCAST, 1);
2930         if (status) {
2931                 QPRINTK(qdev, IFUP, ERR,
2932                         "Failed to init routing register for broadcast packets.\n");
2933                 return status;
2934         }
2935         /* If we have more than one inbound queue, then turn on RSS in the
2936          * routing block.
2937          */
2938         if (qdev->rss_ring_count > 1) {
2939                 status = ql_set_routing_reg(qdev, RT_IDX_RSS_MATCH_SLOT,
2940                                         RT_IDX_RSS_MATCH, 1);
2941                 if (status) {
2942                         QPRINTK(qdev, IFUP, ERR,
2943                                 "Failed to init routing register for MATCH RSS packets.\n");
2944                         return status;
2945                 }
2946         }
2947
2948         status = ql_set_routing_reg(qdev, RT_IDX_CAM_HIT_SLOT,
2949                                     RT_IDX_CAM_HIT, 1);
2950         if (status) {
2951                 QPRINTK(qdev, IFUP, ERR,
2952                         "Failed to init routing register for CAM packets.\n");
2953                 return status;
2954         }
2955         return status;
2956 }
2957
2958 static int ql_adapter_initialize(struct ql_adapter *qdev)
2959 {
2960         u32 value, mask;
2961         int i;
2962         int status = 0;
2963
2964         /*
2965          * Set up the System register to halt on errors.
2966          */
2967         value = SYS_EFE | SYS_FAE;
2968         mask = value << 16;
2969         ql_write32(qdev, SYS, mask | value);
2970
2971         /* Set the default queue. */
2972         value = NIC_RCV_CFG_DFQ;
2973         mask = NIC_RCV_CFG_DFQ_MASK;
2974         ql_write32(qdev, NIC_RCV_CFG, (mask | value));
2975
2976         /* Set the MPI interrupt to enabled. */
2977         ql_write32(qdev, INTR_MASK, (INTR_MASK_PI << 16) | INTR_MASK_PI);
2978
2979         /* Enable the function, set pagesize, enable error checking. */
2980         value = FSC_FE | FSC_EPC_INBOUND | FSC_EPC_OUTBOUND |
2981             FSC_EC | FSC_VM_PAGE_4K | FSC_SH;
2982
2983         /* Set/clear header splitting. */
2984         mask = FSC_VM_PAGESIZE_MASK |
2985             FSC_DBL_MASK | FSC_DBRST_MASK | (value << 16);
2986         ql_write32(qdev, FSC, mask | value);
2987
2988         ql_write32(qdev, SPLT_HDR, SPLT_HDR_EP |
2989                 min(SMALL_BUFFER_SIZE, MAX_SPLIT_SIZE));
2990
2991         /* Start up the rx queues. */
2992         for (i = 0; i < qdev->rx_ring_count; i++) {
2993                 status = ql_start_rx_ring(qdev, &qdev->rx_ring[i]);
2994                 if (status) {
2995                         QPRINTK(qdev, IFUP, ERR,
2996                                 "Failed to start rx ring[%d].\n", i);
2997                         return status;
2998                 }
2999         }
3000
3001         /* If there is more than one inbound completion queue
3002          * then download a RICB to configure RSS.
3003          */
3004         if (qdev->rss_ring_count > 1) {
3005                 status = ql_start_rss(qdev);
3006                 if (status) {
3007                         QPRINTK(qdev, IFUP, ERR, "Failed to start RSS.\n");
3008                         return status;
3009                 }
3010         }
3011
3012         /* Start up the tx queues. */
3013         for (i = 0; i < qdev->tx_ring_count; i++) {
3014                 status = ql_start_tx_ring(qdev, &qdev->tx_ring[i]);
3015                 if (status) {
3016                         QPRINTK(qdev, IFUP, ERR,
3017                                 "Failed to start tx ring[%d].\n", i);
3018                         return status;
3019                 }
3020         }
3021
3022         status = ql_port_initialize(qdev);
3023         if (status) {
3024                 QPRINTK(qdev, IFUP, ERR, "Failed to start port.\n");
3025                 return status;
3026         }
3027
3028         status = ql_set_mac_addr_reg(qdev, (u8 *) qdev->ndev->perm_addr,
3029                                      MAC_ADDR_TYPE_CAM_MAC, qdev->func);
3030         if (status) {
3031                 QPRINTK(qdev, IFUP, ERR, "Failed to init mac address.\n");
3032                 return status;
3033         }
3034
3035         status = ql_route_initialize(qdev);
3036         if (status) {
3037                 QPRINTK(qdev, IFUP, ERR, "Failed to init routing table.\n");
3038                 return status;
3039         }
3040
3041         /* Start NAPI for the RSS queues. */
3042         for (i = qdev->rss_ring_first_cq_id; i < qdev->rx_ring_count; i++) {
3043                 QPRINTK(qdev, IFUP, INFO, "Enabling NAPI for rx_ring[%d].\n",
3044                         i);
3045                 napi_enable(&qdev->rx_ring[i].napi);
3046         }
3047
3048         return status;
3049 }
3050
3051 /* Issue soft reset to chip. */
3052 static int ql_adapter_reset(struct ql_adapter *qdev)
3053 {
3054         u32 value;
3055         int max_wait_time;
3056         int status = 0;
3057         int resetCnt = 0;
3058
3059 #define MAX_RESET_CNT   1
3060 issueReset:
3061         resetCnt++;
3062         QPRINTK(qdev, IFDOWN, DEBUG, "Issue soft reset to chip.\n");
3063         ql_write32(qdev, RST_FO, (RST_FO_FR << 16) | RST_FO_FR);
3064         /* Wait for reset to complete. */
3065         max_wait_time = 3;
3066         QPRINTK(qdev, IFDOWN, DEBUG, "Wait %d seconds for reset to complete.\n",
3067                 max_wait_time);
3068         do {
3069                 value = ql_read32(qdev, RST_FO);
3070                 if ((value & RST_FO_FR) == 0)
3071                         break;
3072
3073                 ssleep(1);
3074         } while ((--max_wait_time));
3075         if (value & RST_FO_FR) {
3076                 QPRINTK(qdev, IFDOWN, ERR,
3077                         "Stuck in SoftReset:  FSC_SR:0x%08x\n", value);
3078                 if (resetCnt < MAX_RESET_CNT)
3079                         goto issueReset;
3080         }
3081         if (max_wait_time == 0) {
3082                 status = -ETIMEDOUT;
3083                 QPRINTK(qdev, IFDOWN, ERR,
3084                         "ETIMEOUT!!! errored out of resetting the chip!\n");
3085         }
3086
3087         return status;
3088 }
3089
3090 static void ql_display_dev_info(struct net_device *ndev)
3091 {
3092         struct ql_adapter *qdev = (struct ql_adapter *)netdev_priv(ndev);
3093
3094         QPRINTK(qdev, PROBE, INFO,
3095                 "Function #%d, NIC Roll %d, NIC Rev = %d, "
3096                 "XG Roll = %d, XG Rev = %d.\n",
3097                 qdev->func,
3098                 qdev->chip_rev_id & 0x0000000f,
3099                 qdev->chip_rev_id >> 4 & 0x0000000f,
3100                 qdev->chip_rev_id >> 8 & 0x0000000f,
3101                 qdev->chip_rev_id >> 12 & 0x0000000f);
3102         QPRINTK(qdev, PROBE, INFO, "MAC address %pM\n", ndev->dev_addr);
3103 }
3104
3105 static int ql_adapter_down(struct ql_adapter *qdev)
3106 {
3107         struct net_device *ndev = qdev->ndev;
3108         int i, status = 0;
3109         struct rx_ring *rx_ring;
3110
3111         netif_stop_queue(ndev);
3112         netif_carrier_off(ndev);
3113
3114         /* Don't kill the reset worker thread if we
3115          * are in the process of recovery.
3116          */
3117         if (test_bit(QL_ADAPTER_UP, &qdev->flags))
3118                 cancel_delayed_work_sync(&qdev->asic_reset_work);
3119         cancel_delayed_work_sync(&qdev->mpi_reset_work);
3120         cancel_delayed_work_sync(&qdev->mpi_work);
3121
3122         /* The default queue at index 0 is always processed in
3123          * a workqueue.
3124          */
3125         cancel_delayed_work_sync(&qdev->rx_ring[0].rx_work);
3126
3127         /* The rest of the rx_rings are processed in
3128          * a workqueue only if it's a single interrupt
3129          * environment (MSI/Legacy).
3130          */
3131         for (i = 1; i < qdev->rx_ring_count; i++) {
3132                 rx_ring = &qdev->rx_ring[i];
3133                 /* Only the RSS rings use NAPI on multi irq
3134                  * environment.  Outbound completion processing
3135                  * is done in interrupt context.
3136                  */
3137                 if (i >= qdev->rss_ring_first_cq_id) {
3138                         napi_disable(&rx_ring->napi);
3139                 } else {
3140                         cancel_delayed_work_sync(&rx_ring->rx_work);
3141                 }
3142         }
3143
3144         clear_bit(QL_ADAPTER_UP, &qdev->flags);
3145
3146         ql_disable_interrupts(qdev);
3147
3148         ql_tx_ring_clean(qdev);
3149
3150         spin_lock(&qdev->hw_lock);
3151         status = ql_adapter_reset(qdev);
3152         if (status)
3153                 QPRINTK(qdev, IFDOWN, ERR, "reset(func #%d) FAILED!\n",
3154                         qdev->func);
3155         spin_unlock(&qdev->hw_lock);
3156         return status;
3157 }
3158
3159 static int ql_adapter_up(struct ql_adapter *qdev)
3160 {
3161         int err = 0;
3162
3163         spin_lock(&qdev->hw_lock);
3164         err = ql_adapter_initialize(qdev);
3165         if (err) {
3166                 QPRINTK(qdev, IFUP, INFO, "Unable to initialize adapter.\n");
3167                 spin_unlock(&qdev->hw_lock);
3168                 goto err_init;
3169         }
3170         spin_unlock(&qdev->hw_lock);
3171         set_bit(QL_ADAPTER_UP, &qdev->flags);
3172         ql_enable_interrupts(qdev);
3173         ql_enable_all_completion_interrupts(qdev);
3174         if ((ql_read32(qdev, STS) & qdev->port_init)) {
3175                 netif_carrier_on(qdev->ndev);
3176                 netif_start_queue(qdev->ndev);
3177         }
3178
3179         return 0;
3180 err_init:
3181         ql_adapter_reset(qdev);
3182         return err;
3183 }
3184
3185 static int ql_cycle_adapter(struct ql_adapter *qdev)
3186 {
3187         int status;
3188
3189         status = ql_adapter_down(qdev);
3190         if (status)
3191                 goto error;
3192
3193         status = ql_adapter_up(qdev);
3194         if (status)
3195                 goto error;
3196
3197         return status;
3198 error:
3199         QPRINTK(qdev, IFUP, ALERT,
3200                 "Driver up/down cycle failed, closing device\n");
3201         rtnl_lock();
3202         dev_close(qdev->ndev);
3203         rtnl_unlock();
3204         return status;
3205 }
3206
3207 static void ql_release_adapter_resources(struct ql_adapter *qdev)
3208 {
3209         ql_free_mem_resources(qdev);
3210         ql_free_irq(qdev);
3211 }
3212
3213 static int ql_get_adapter_resources(struct ql_adapter *qdev)
3214 {
3215         int status = 0;
3216
3217         if (ql_alloc_mem_resources(qdev)) {
3218                 QPRINTK(qdev, IFUP, ERR, "Unable to  allocate memory.\n");
3219                 return -ENOMEM;
3220         }
3221         status = ql_request_irq(qdev);
3222         if (status)
3223                 goto err_irq;
3224         return status;
3225 err_irq:
3226         ql_free_mem_resources(qdev);
3227         return status;
3228 }
3229
3230 static int qlge_close(struct net_device *ndev)
3231 {
3232         struct ql_adapter *qdev = netdev_priv(ndev);
3233
3234         /*
3235          * Wait for device to recover from a reset.
3236          * (Rarely happens, but possible.)
3237          */
3238         while (!test_bit(QL_ADAPTER_UP, &qdev->flags))
3239                 msleep(1);
3240         ql_adapter_down(qdev);
3241         ql_release_adapter_resources(qdev);
3242         return 0;
3243 }
3244
3245 static int ql_configure_rings(struct ql_adapter *qdev)
3246 {
3247         int i;
3248         struct rx_ring *rx_ring;
3249         struct tx_ring *tx_ring;
3250         int cpu_cnt = num_online_cpus();
3251
3252         /*
3253          * For each processor present we allocate one
3254          * rx_ring for outbound completions, and one
3255          * rx_ring for inbound completions.  Plus there is
3256          * always the one default queue.  For the CPU
3257          * counts we end up with the following rx_rings:
3258          * rx_ring count =
3259          *  one default queue +
3260          *  (CPU count * outbound completion rx_ring) +
3261          *  (CPU count * inbound (RSS) completion rx_ring)
3262          * To keep it simple we limit the total number of
3263          * queues to < 32, so we truncate CPU to 8.
3264          * This limitation can be removed when requested.
3265          */
3266
3267         if (cpu_cnt > MAX_CPUS)
3268                 cpu_cnt = MAX_CPUS;
3269
3270         /*
3271          * rx_ring[0] is always the default queue.
3272          */
3273         /* Allocate outbound completion ring for each CPU. */
3274         qdev->tx_ring_count = cpu_cnt;
3275         /* Allocate inbound completion (RSS) ring for each CPU. */
3276         qdev->rss_ring_count = cpu_cnt;
3277         /* cq_id for the first inbound ring handler. */
3278         qdev->rss_ring_first_cq_id = cpu_cnt + 1;
3279         /*
3280          * qdev->rx_ring_count:
3281          * Total number of rx_rings.  This includes the one
3282          * default queue, a number of outbound completion
3283          * handler rx_rings, and the number of inbound
3284          * completion handler rx_rings.
3285          */
3286         qdev->rx_ring_count = qdev->tx_ring_count + qdev->rss_ring_count + 1;
3287
3288         for (i = 0; i < qdev->tx_ring_count; i++) {
3289                 tx_ring = &qdev->tx_ring[i];
3290                 memset((void *)tx_ring, 0, sizeof(tx_ring));
3291                 tx_ring->qdev = qdev;
3292                 tx_ring->wq_id = i;
3293                 tx_ring->wq_len = qdev->tx_ring_size;
3294                 tx_ring->wq_size =
3295                     tx_ring->wq_len * sizeof(struct ob_mac_iocb_req);
3296
3297                 /*
3298                  * The completion queue ID for the tx rings start
3299                  * immediately after the default Q ID, which is zero.
3300                  */
3301                 tx_ring->cq_id = i + 1;
3302         }
3303
3304         for (i = 0; i < qdev->rx_ring_count; i++) {
3305                 rx_ring = &qdev->rx_ring[i];
3306                 memset((void *)rx_ring, 0, sizeof(rx_ring));
3307                 rx_ring->qdev = qdev;
3308                 rx_ring->cq_id = i;
3309                 rx_ring->cpu = i % cpu_cnt;     /* CPU to run handler on. */
3310                 if (i == 0) {   /* Default queue at index 0. */
3311                         /*
3312                          * Default queue handles bcast/mcast plus
3313                          * async events.  Needs buffers.
3314                          */
3315                         rx_ring->cq_len = qdev->rx_ring_size;
3316                         rx_ring->cq_size =
3317                             rx_ring->cq_len * sizeof(struct ql_net_rsp_iocb);
3318                         rx_ring->lbq_len = NUM_LARGE_BUFFERS;
3319                         rx_ring->lbq_size =
3320                             rx_ring->lbq_len * sizeof(__le64);
3321                         rx_ring->lbq_buf_size = LARGE_BUFFER_SIZE;
3322                         rx_ring->sbq_len = NUM_SMALL_BUFFERS;
3323                         rx_ring->sbq_size =
3324                             rx_ring->sbq_len * sizeof(__le64);
3325                         rx_ring->sbq_buf_size = SMALL_BUFFER_SIZE * 2;
3326                         rx_ring->type = DEFAULT_Q;
3327                 } else if (i < qdev->rss_ring_first_cq_id) {
3328                         /*
3329                          * Outbound queue handles outbound completions only.
3330                          */
3331                         /* outbound cq is same size as tx_ring it services. */
3332                         rx_ring->cq_len = qdev->tx_ring_size;
3333                         rx_ring->cq_size =
3334                             rx_ring->cq_len * sizeof(struct ql_net_rsp_iocb);
3335                         rx_ring->lbq_len = 0;
3336                         rx_ring->lbq_size = 0;
3337                         rx_ring->lbq_buf_size = 0;
3338                         rx_ring->sbq_len = 0;
3339                         rx_ring->sbq_size = 0;
3340                         rx_ring->sbq_buf_size = 0;
3341                         rx_ring->type = TX_Q;
3342                 } else {        /* Inbound completions (RSS) queues */
3343                         /*
3344                          * Inbound queues handle unicast frames only.
3345                          */
3346                         rx_ring->cq_len = qdev->rx_ring_size;
3347                         rx_ring->cq_size =
3348                             rx_ring->cq_len * sizeof(struct ql_net_rsp_iocb);
3349                         rx_ring->lbq_len = NUM_LARGE_BUFFERS;
3350                         rx_ring->lbq_size =
3351                             rx_ring->lbq_len * sizeof(__le64);
3352                         rx_ring->lbq_buf_size = LARGE_BUFFER_SIZE;
3353                         rx_ring->sbq_len = NUM_SMALL_BUFFERS;
3354                         rx_ring->sbq_size =
3355                             rx_ring->sbq_len * sizeof(__le64);
3356                         rx_ring->sbq_buf_size = SMALL_BUFFER_SIZE * 2;
3357                         rx_ring->type = RX_Q;
3358                 }
3359         }
3360         return 0;
3361 }
3362
3363 static int qlge_open(struct net_device *ndev)
3364 {
3365         int err = 0;
3366         struct ql_adapter *qdev = netdev_priv(ndev);
3367
3368         err = ql_configure_rings(qdev);
3369         if (err)
3370                 return err;
3371
3372         err = ql_get_adapter_resources(qdev);
3373         if (err)
3374                 goto error_up;
3375
3376         err = ql_adapter_up(qdev);
3377         if (err)
3378                 goto error_up;
3379
3380         return err;
3381
3382 error_up:
3383         ql_release_adapter_resources(qdev);
3384         return err;
3385 }
3386
3387 static int qlge_change_mtu(struct net_device *ndev, int new_mtu)
3388 {
3389         struct ql_adapter *qdev = netdev_priv(ndev);
3390
3391         if (ndev->mtu == 1500 && new_mtu == 9000) {
3392                 QPRINTK(qdev, IFUP, ERR, "Changing to jumbo MTU.\n");
3393         } else if (ndev->mtu == 9000 && new_mtu == 1500) {
3394                 QPRINTK(qdev, IFUP, ERR, "Changing to normal MTU.\n");
3395         } else if ((ndev->mtu == 1500 && new_mtu == 1500) ||
3396                    (ndev->mtu == 9000 && new_mtu == 9000)) {
3397                 return 0;
3398         } else
3399                 return -EINVAL;
3400         ndev->mtu = new_mtu;
3401         return 0;
3402 }
3403
3404 static struct net_device_stats *qlge_get_stats(struct net_device
3405                                                *ndev)
3406 {
3407         struct ql_adapter *qdev = netdev_priv(ndev);
3408         return &qdev->stats;
3409 }
3410
3411 static void qlge_set_multicast_list(struct net_device *ndev)
3412 {
3413         struct ql_adapter *qdev = (struct ql_adapter *)netdev_priv(ndev);
3414         struct dev_mc_list *mc_ptr;
3415         int i;
3416
3417         spin_lock(&qdev->hw_lock);
3418         /*
3419          * Set or clear promiscuous mode if a
3420          * transition is taking place.
3421          */
3422         if (ndev->flags & IFF_PROMISC) {
3423                 if (!test_bit(QL_PROMISCUOUS, &qdev->flags)) {
3424                         if (ql_set_routing_reg
3425                             (qdev, RT_IDX_PROMISCUOUS_SLOT, RT_IDX_VALID, 1)) {
3426                                 QPRINTK(qdev, HW, ERR,
3427                                         "Failed to set promiscous mode.\n");
3428                         } else {
3429                                 set_bit(QL_PROMISCUOUS, &qdev->flags);
3430                         }
3431                 }
3432         } else {
3433                 if (test_bit(QL_PROMISCUOUS, &qdev->flags)) {
3434                         if (ql_set_routing_reg
3435                             (qdev, RT_IDX_PROMISCUOUS_SLOT, RT_IDX_VALID, 0)) {
3436                                 QPRINTK(qdev, HW, ERR,
3437                                         "Failed to clear promiscous mode.\n");
3438                         } else {
3439                                 clear_bit(QL_PROMISCUOUS, &qdev->flags);
3440                         }
3441                 }
3442         }
3443
3444         /*
3445          * Set or clear all multicast mode if a
3446          * transition is taking place.
3447          */
3448         if ((ndev->flags & IFF_ALLMULTI) ||
3449             (ndev->mc_count > MAX_MULTICAST_ENTRIES)) {
3450                 if (!test_bit(QL_ALLMULTI, &qdev->flags)) {
3451                         if (ql_set_routing_reg
3452                             (qdev, RT_IDX_ALLMULTI_SLOT, RT_IDX_MCAST, 1)) {
3453                                 QPRINTK(qdev, HW, ERR,
3454                                         "Failed to set all-multi mode.\n");
3455                         } else {
3456                                 set_bit(QL_ALLMULTI, &qdev->flags);
3457                         }
3458                 }
3459         } else {
3460                 if (test_bit(QL_ALLMULTI, &qdev->flags)) {
3461                         if (ql_set_routing_reg
3462                             (qdev, RT_IDX_ALLMULTI_SLOT, RT_IDX_MCAST, 0)) {
3463                                 QPRINTK(qdev, HW, ERR,
3464                                         "Failed to clear all-multi mode.\n");
3465                         } else {
3466                                 clear_bit(QL_ALLMULTI, &qdev->flags);
3467                         }
3468                 }
3469         }
3470
3471         if (ndev->mc_count) {
3472                 for (i = 0, mc_ptr = ndev->mc_list; mc_ptr;
3473                      i++, mc_ptr = mc_ptr->next)
3474                         if (ql_set_mac_addr_reg(qdev, (u8 *) mc_ptr->dmi_addr,
3475                                                 MAC_ADDR_TYPE_MULTI_MAC, i)) {
3476                                 QPRINTK(qdev, HW, ERR,
3477                                         "Failed to loadmulticast address.\n");
3478                                 goto exit;
3479                         }
3480                 if (ql_set_routing_reg
3481                     (qdev, RT_IDX_MCAST_MATCH_SLOT, RT_IDX_MCAST_MATCH, 1)) {
3482                         QPRINTK(qdev, HW, ERR,
3483                                 "Failed to set multicast match mode.\n");
3484                 } else {
3485                         set_bit(QL_ALLMULTI, &qdev->flags);
3486                 }
3487         }
3488 exit:
3489         spin_unlock(&qdev->hw_lock);
3490 }
3491
3492 static int qlge_set_mac_address(struct net_device *ndev, void *p)
3493 {
3494         struct ql_adapter *qdev = (struct ql_adapter *)netdev_priv(ndev);
3495         struct sockaddr *addr = p;
3496         int ret = 0;
3497
3498         if (netif_running(ndev))
3499                 return -EBUSY;
3500
3501         if (!is_valid_ether_addr(addr->sa_data))
3502                 return -EADDRNOTAVAIL;
3503         memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len);
3504
3505         spin_lock(&qdev->hw_lock);
3506         if (ql_set_mac_addr_reg(qdev, (u8 *) ndev->dev_addr,
3507                         MAC_ADDR_TYPE_CAM_MAC, qdev->func)) {/* Unicast */
3508                 QPRINTK(qdev, HW, ERR, "Failed to load MAC address.\n");
3509                 ret = -1;
3510         }
3511         spin_unlock(&qdev->hw_lock);
3512
3513         return ret;
3514 }
3515
3516 static void qlge_tx_timeout(struct net_device *ndev)
3517 {
3518         struct ql_adapter *qdev = (struct ql_adapter *)netdev_priv(ndev);
3519         ql_queue_asic_error(qdev);
3520 }
3521
3522 static void ql_asic_reset_work(struct work_struct *work)
3523 {
3524         struct ql_adapter *qdev =
3525             container_of(work, struct ql_adapter, asic_reset_work.work);
3526         ql_cycle_adapter(qdev);
3527 }
3528
3529 static void ql_get_board_info(struct ql_adapter *qdev)
3530 {
3531         qdev->func =
3532             (ql_read32(qdev, STS) & STS_FUNC_ID_MASK) >> STS_FUNC_ID_SHIFT;
3533         if (qdev->func) {
3534                 qdev->xg_sem_mask = SEM_XGMAC1_MASK;
3535                 qdev->port_link_up = STS_PL1;
3536                 qdev->port_init = STS_PI1;
3537                 qdev->mailbox_in = PROC_ADDR_MPI_RISC | PROC_ADDR_FUNC2_MBI;
3538                 qdev->mailbox_out = PROC_ADDR_MPI_RISC | PROC_ADDR_FUNC2_MBO;
3539         } else {
3540                 qdev->xg_sem_mask = SEM_XGMAC0_MASK;
3541                 qdev->port_link_up = STS_PL0;
3542                 qdev->port_init = STS_PI0;
3543                 qdev->mailbox_in = PROC_ADDR_MPI_RISC | PROC_ADDR_FUNC0_MBI;
3544                 qdev->mailbox_out = PROC_ADDR_MPI_RISC | PROC_ADDR_FUNC0_MBO;
3545         }
3546         qdev->chip_rev_id = ql_read32(qdev, REV_ID);
3547 }
3548
3549 static void ql_release_all(struct pci_dev *pdev)
3550 {
3551         struct net_device *ndev = pci_get_drvdata(pdev);
3552         struct ql_adapter *qdev = netdev_priv(ndev);
3553
3554         if (qdev->workqueue) {
3555                 destroy_workqueue(qdev->workqueue);
3556                 qdev->workqueue = NULL;
3557         }
3558         if (qdev->q_workqueue) {
3559                 destroy_workqueue(qdev->q_workqueue);
3560                 qdev->q_workqueue = NULL;
3561         }
3562         if (qdev->reg_base)
3563                 iounmap(qdev->reg_base);
3564         if (qdev->doorbell_area)
3565                 iounmap(qdev->doorbell_area);
3566         pci_release_regions(pdev);
3567         pci_set_drvdata(pdev, NULL);
3568 }
3569
3570 static int __devinit ql_init_device(struct pci_dev *pdev,
3571                                     struct net_device *ndev, int cards_found)
3572 {
3573         struct ql_adapter *qdev = netdev_priv(ndev);
3574         int pos, err = 0;
3575         u16 val16;
3576
3577         memset((void *)qdev, 0, sizeof(qdev));
3578         err = pci_enable_device(pdev);
3579         if (err) {
3580                 dev_err(&pdev->dev, "PCI device enable failed.\n");
3581                 return err;
3582         }
3583
3584         pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
3585         if (pos <= 0) {
3586                 dev_err(&pdev->dev, PFX "Cannot find PCI Express capability, "
3587                         "aborting.\n");
3588                 goto err_out;
3589         } else {
3590                 pci_read_config_word(pdev, pos + PCI_EXP_DEVCTL, &val16);
3591                 val16 &= ~PCI_EXP_DEVCTL_NOSNOOP_EN;
3592                 val16 |= (PCI_EXP_DEVCTL_CERE |
3593                           PCI_EXP_DEVCTL_NFERE |
3594                           PCI_EXP_DEVCTL_FERE | PCI_EXP_DEVCTL_URRE);
3595                 pci_write_config_word(pdev, pos + PCI_EXP_DEVCTL, val16);
3596         }
3597
3598         err = pci_request_regions(pdev, DRV_NAME);
3599         if (err) {
3600                 dev_err(&pdev->dev, "PCI region request failed.\n");
3601                 goto err_out;
3602         }
3603
3604         pci_set_master(pdev);
3605         if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
3606                 set_bit(QL_DMA64, &qdev->flags);
3607                 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
3608         } else {
3609                 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3610                 if (!err)
3611                        err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
3612         }
3613
3614         if (err) {
3615                 dev_err(&pdev->dev, "No usable DMA configuration.\n");
3616                 goto err_out;
3617         }
3618
3619         pci_set_drvdata(pdev, ndev);
3620         qdev->reg_base =
3621             ioremap_nocache(pci_resource_start(pdev, 1),
3622                             pci_resource_len(pdev, 1));
3623         if (!qdev->reg_base) {
3624                 dev_err(&pdev->dev, "Register mapping failed.\n");
3625                 err = -ENOMEM;
3626                 goto err_out;
3627         }
3628
3629         qdev->doorbell_area_size = pci_resource_len(pdev, 3);
3630         qdev->doorbell_area =
3631             ioremap_nocache(pci_resource_start(pdev, 3),
3632                             pci_resource_len(pdev, 3));
3633         if (!qdev->doorbell_area) {
3634                 dev_err(&pdev->dev, "Doorbell register mapping failed.\n");
3635                 err = -ENOMEM;
3636                 goto err_out;
3637         }
3638
3639         ql_get_board_info(qdev);
3640         qdev->ndev = ndev;
3641         qdev->pdev = pdev;
3642         qdev->msg_enable = netif_msg_init(debug, default_msg);
3643         spin_lock_init(&qdev->hw_lock);
3644         spin_lock_init(&qdev->stats_lock);
3645
3646         /* make sure the EEPROM is good */
3647         err = ql_get_flash_params(qdev);
3648         if (err) {
3649                 dev_err(&pdev->dev, "Invalid FLASH.\n");
3650                 goto err_out;
3651         }
3652
3653         if (!is_valid_ether_addr(qdev->flash.mac_addr))
3654                 goto err_out;
3655
3656         memcpy(ndev->dev_addr, qdev->flash.mac_addr, ndev->addr_len);
3657         memcpy(ndev->perm_addr, ndev->dev_addr, ndev->addr_len);
3658
3659         /* Set up the default ring sizes. */
3660         qdev->tx_ring_size = NUM_TX_RING_ENTRIES;
3661         qdev->rx_ring_size = NUM_RX_RING_ENTRIES;
3662
3663         /* Set up the coalescing parameters. */
3664         qdev->rx_coalesce_usecs = DFLT_COALESCE_WAIT;
3665         qdev->tx_coalesce_usecs = DFLT_COALESCE_WAIT;
3666         qdev->rx_max_coalesced_frames = DFLT_INTER_FRAME_WAIT;
3667         qdev->tx_max_coalesced_frames = DFLT_INTER_FRAME_WAIT;
3668
3669         /*
3670          * Set up the operating parameters.
3671          */
3672         qdev->rx_csum = 1;
3673
3674         qdev->q_workqueue = create_workqueue(ndev->name);
3675         qdev->workqueue = create_singlethread_workqueue(ndev->name);
3676         INIT_DELAYED_WORK(&qdev->asic_reset_work, ql_asic_reset_work);
3677         INIT_DELAYED_WORK(&qdev->mpi_reset_work, ql_mpi_reset_work);
3678         INIT_DELAYED_WORK(&qdev->mpi_work, ql_mpi_work);
3679
3680         if (!cards_found) {
3681                 dev_info(&pdev->dev, "%s\n", DRV_STRING);
3682                 dev_info(&pdev->dev, "Driver name: %s, Version: %s.\n",
3683                          DRV_NAME, DRV_VERSION);
3684         }
3685         return 0;
3686 err_out:
3687         ql_release_all(pdev);
3688         pci_disable_device(pdev);
3689         return err;
3690 }
3691
3692
3693 static const struct net_device_ops qlge_netdev_ops = {
3694         .ndo_open               = qlge_open,
3695         .ndo_stop               = qlge_close,
3696         .ndo_start_xmit         = qlge_send,
3697         .ndo_change_mtu         = qlge_change_mtu,
3698         .ndo_get_stats          = qlge_get_stats,
3699         .ndo_set_multicast_list = qlge_set_multicast_list,
3700         .ndo_set_mac_address    = qlge_set_mac_address,
3701         .ndo_validate_addr      = eth_validate_addr,
3702         .ndo_tx_timeout         = qlge_tx_timeout,
3703         .ndo_vlan_rx_register   = ql_vlan_rx_register,
3704         .ndo_vlan_rx_add_vid    = ql_vlan_rx_add_vid,
3705         .ndo_vlan_rx_kill_vid   = ql_vlan_rx_kill_vid,
3706 };
3707
3708 static int __devinit qlge_probe(struct pci_dev *pdev,
3709                                 const struct pci_device_id *pci_entry)
3710 {
3711         struct net_device *ndev = NULL;
3712         struct ql_adapter *qdev = NULL;
3713         static int cards_found = 0;
3714         int err = 0;
3715
3716         ndev = alloc_etherdev(sizeof(struct ql_adapter));
3717         if (!ndev)
3718                 return -ENOMEM;
3719
3720         err = ql_init_device(pdev, ndev, cards_found);
3721         if (err < 0) {
3722                 free_netdev(ndev);
3723                 return err;
3724         }
3725
3726         qdev = netdev_priv(ndev);
3727         SET_NETDEV_DEV(ndev, &pdev->dev);
3728         ndev->features = (0
3729                           | NETIF_F_IP_CSUM
3730                           | NETIF_F_SG
3731                           | NETIF_F_TSO
3732                           | NETIF_F_TSO6
3733                           | NETIF_F_TSO_ECN
3734                           | NETIF_F_HW_VLAN_TX
3735                           | NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_FILTER);
3736
3737         if (test_bit(QL_DMA64, &qdev->flags))
3738                 ndev->features |= NETIF_F_HIGHDMA;
3739
3740         /*
3741          * Set up net_device structure.
3742          */
3743         ndev->tx_queue_len = qdev->tx_ring_size;
3744         ndev->irq = pdev->irq;
3745
3746         ndev->netdev_ops = &qlge_netdev_ops;
3747         SET_ETHTOOL_OPS(ndev, &qlge_ethtool_ops);
3748         ndev->watchdog_timeo = 10 * HZ;
3749
3750         err = register_netdev(ndev);
3751         if (err) {
3752                 dev_err(&pdev->dev, "net device registration failed.\n");
3753                 ql_release_all(pdev);
3754                 pci_disable_device(pdev);
3755                 return err;
3756         }
3757         netif_carrier_off(ndev);
3758         netif_stop_queue(ndev);
3759         ql_display_dev_info(ndev);
3760         cards_found++;
3761         return 0;
3762 }
3763
3764 static void __devexit qlge_remove(struct pci_dev *pdev)
3765 {
3766         struct net_device *ndev = pci_get_drvdata(pdev);
3767         unregister_netdev(ndev);
3768         ql_release_all(pdev);
3769         pci_disable_device(pdev);
3770         free_netdev(ndev);
3771 }
3772
3773 /*
3774  * This callback is called by the PCI subsystem whenever
3775  * a PCI bus error is detected.
3776  */
3777 static pci_ers_result_t qlge_io_error_detected(struct pci_dev *pdev,
3778                                                enum pci_channel_state state)
3779 {
3780         struct net_device *ndev = pci_get_drvdata(pdev);
3781         struct ql_adapter *qdev = netdev_priv(ndev);
3782
3783         if (netif_running(ndev))
3784                 ql_adapter_down(qdev);
3785
3786         pci_disable_device(pdev);
3787
3788         /* Request a slot reset. */
3789         return PCI_ERS_RESULT_NEED_RESET;
3790 }
3791
3792 /*
3793  * This callback is called after the PCI buss has been reset.
3794  * Basically, this tries to restart the card from scratch.
3795  * This is a shortened version of the device probe/discovery code,
3796  * it resembles the first-half of the () routine.
3797  */
3798 static pci_ers_result_t qlge_io_slot_reset(struct pci_dev *pdev)
3799 {
3800         struct net_device *ndev = pci_get_drvdata(pdev);
3801         struct ql_adapter *qdev = netdev_priv(ndev);
3802
3803         if (pci_enable_device(pdev)) {
3804                 QPRINTK(qdev, IFUP, ERR,
3805                         "Cannot re-enable PCI device after reset.\n");
3806                 return PCI_ERS_RESULT_DISCONNECT;
3807         }
3808
3809         pci_set_master(pdev);
3810
3811         netif_carrier_off(ndev);
3812         netif_stop_queue(ndev);
3813         ql_adapter_reset(qdev);
3814
3815         /* Make sure the EEPROM is good */
3816         memcpy(ndev->perm_addr, ndev->dev_addr, ndev->addr_len);
3817
3818         if (!is_valid_ether_addr(ndev->perm_addr)) {
3819                 QPRINTK(qdev, IFUP, ERR, "After reset, invalid MAC address.\n");
3820                 return PCI_ERS_RESULT_DISCONNECT;
3821         }
3822
3823         return PCI_ERS_RESULT_RECOVERED;
3824 }
3825
3826 static void qlge_io_resume(struct pci_dev *pdev)
3827 {
3828         struct net_device *ndev = pci_get_drvdata(pdev);
3829         struct ql_adapter *qdev = netdev_priv(ndev);
3830
3831         pci_set_master(pdev);
3832
3833         if (netif_running(ndev)) {
3834                 if (ql_adapter_up(qdev)) {
3835                         QPRINTK(qdev, IFUP, ERR,
3836                                 "Device initialization failed after reset.\n");
3837                         return;
3838                 }
3839         }
3840
3841         netif_device_attach(ndev);
3842 }
3843
3844 static struct pci_error_handlers qlge_err_handler = {
3845         .error_detected = qlge_io_error_detected,
3846         .slot_reset = qlge_io_slot_reset,
3847         .resume = qlge_io_resume,
3848 };
3849
3850 static int qlge_suspend(struct pci_dev *pdev, pm_message_t state)
3851 {
3852         struct net_device *ndev = pci_get_drvdata(pdev);
3853         struct ql_adapter *qdev = netdev_priv(ndev);
3854         int err, i;
3855
3856         netif_device_detach(ndev);
3857
3858         if (netif_running(ndev)) {
3859                 err = ql_adapter_down(qdev);
3860                 if (!err)
3861                         return err;
3862         }
3863
3864         for (i = qdev->rss_ring_first_cq_id; i < qdev->rx_ring_count; i++)
3865                 netif_napi_del(&qdev->rx_ring[i].napi);
3866
3867         err = pci_save_state(pdev);
3868         if (err)
3869                 return err;
3870
3871         pci_disable_device(pdev);
3872
3873         pci_set_power_state(pdev, pci_choose_state(pdev, state));
3874
3875         return 0;
3876 }
3877
3878 #ifdef CONFIG_PM
3879 static int qlge_resume(struct pci_dev *pdev)
3880 {
3881         struct net_device *ndev = pci_get_drvdata(pdev);
3882         struct ql_adapter *qdev = netdev_priv(ndev);
3883         int err;
3884
3885         pci_set_power_state(pdev, PCI_D0);
3886         pci_restore_state(pdev);
3887         err = pci_enable_device(pdev);
3888         if (err) {
3889                 QPRINTK(qdev, IFUP, ERR, "Cannot enable PCI device from suspend\n");
3890                 return err;
3891         }
3892         pci_set_master(pdev);
3893
3894         pci_enable_wake(pdev, PCI_D3hot, 0);
3895         pci_enable_wake(pdev, PCI_D3cold, 0);
3896
3897         if (netif_running(ndev)) {
3898                 err = ql_adapter_up(qdev);
3899                 if (err)
3900                         return err;
3901         }
3902
3903         netif_device_attach(ndev);
3904
3905         return 0;
3906 }
3907 #endif /* CONFIG_PM */
3908
3909 static void qlge_shutdown(struct pci_dev *pdev)
3910 {
3911         qlge_suspend(pdev, PMSG_SUSPEND);
3912 }
3913
3914 static struct pci_driver qlge_driver = {
3915         .name = DRV_NAME,
3916         .id_table = qlge_pci_tbl,
3917         .probe = qlge_probe,
3918         .remove = __devexit_p(qlge_remove),
3919 #ifdef CONFIG_PM
3920         .suspend = qlge_suspend,
3921         .resume = qlge_resume,
3922 #endif
3923         .shutdown = qlge_shutdown,
3924         .err_handler = &qlge_err_handler
3925 };
3926
3927 static int __init qlge_init_module(void)
3928 {
3929         return pci_register_driver(&qlge_driver);
3930 }
3931
3932 static void __exit qlge_exit(void)
3933 {
3934         pci_unregister_driver(&qlge_driver);
3935 }
3936
3937 module_init(qlge_init_module);
3938 module_exit(qlge_exit);