2 * QLogic qlge NIC HBA Driver
3 * Copyright (c) 2003-2008 QLogic Corporation
4 * See LICENSE.qlge for copyright and licensing details.
5 * Author: Linux qlge network device driver by
6 * Ron Mercer <ron.mercer@qlogic.com>
8 #include <linux/kernel.h>
9 #include <linux/init.h>
10 #include <linux/types.h>
11 #include <linux/module.h>
12 #include <linux/list.h>
13 #include <linux/pci.h>
14 #include <linux/dma-mapping.h>
15 #include <linux/pagemap.h>
16 #include <linux/sched.h>
17 #include <linux/slab.h>
18 #include <linux/dmapool.h>
19 #include <linux/mempool.h>
20 #include <linux/spinlock.h>
21 #include <linux/kthread.h>
22 #include <linux/interrupt.h>
23 #include <linux/errno.h>
24 #include <linux/ioport.h>
27 #include <linux/ipv6.h>
29 #include <linux/tcp.h>
30 #include <linux/udp.h>
31 #include <linux/if_arp.h>
32 #include <linux/if_ether.h>
33 #include <linux/netdevice.h>
34 #include <linux/etherdevice.h>
35 #include <linux/ethtool.h>
36 #include <linux/skbuff.h>
37 #include <linux/rtnetlink.h>
38 #include <linux/if_vlan.h>
39 #include <linux/delay.h>
41 #include <linux/vmalloc.h>
42 #include <net/ip6_checksum.h>
46 char qlge_driver_name[] = DRV_NAME;
47 const char qlge_driver_version[] = DRV_VERSION;
49 MODULE_AUTHOR("Ron Mercer <ron.mercer@qlogic.com>");
50 MODULE_DESCRIPTION(DRV_STRING " ");
51 MODULE_LICENSE("GPL");
52 MODULE_VERSION(DRV_VERSION);
54 static const u32 default_msg =
55 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK |
56 /* NETIF_MSG_TIMER | */
62 NETIF_MSG_INTR | NETIF_MSG_TX_DONE | NETIF_MSG_RX_STATUS |
63 /* NETIF_MSG_PKTDATA | */
64 NETIF_MSG_HW | NETIF_MSG_WOL | 0;
66 static int debug = 0x00007fff; /* defaults above */
67 module_param(debug, int, 0);
68 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
73 static int irq_type = MSIX_IRQ;
74 module_param(irq_type, int, MSIX_IRQ);
75 MODULE_PARM_DESC(irq_type, "0 = MSI-X, 1 = MSI, 2 = Legacy.");
77 static struct pci_device_id qlge_pci_tbl[] __devinitdata = {
78 {PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, QLGE_DEVICE_ID)},
79 {PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, QLGE_DEVICE_ID1)},
80 /* required last entry */
84 MODULE_DEVICE_TABLE(pci, qlge_pci_tbl);
86 /* This hardware semaphore causes exclusive access to
87 * resources shared between the NIC driver, MPI firmware,
88 * FCOE firmware and the FC driver.
90 static int ql_sem_trylock(struct ql_adapter *qdev, u32 sem_mask)
96 sem_bits = SEM_SET << SEM_XGMAC0_SHIFT;
99 sem_bits = SEM_SET << SEM_XGMAC1_SHIFT;
102 sem_bits = SEM_SET << SEM_ICB_SHIFT;
104 case SEM_MAC_ADDR_MASK:
105 sem_bits = SEM_SET << SEM_MAC_ADDR_SHIFT;
108 sem_bits = SEM_SET << SEM_FLASH_SHIFT;
111 sem_bits = SEM_SET << SEM_PROBE_SHIFT;
113 case SEM_RT_IDX_MASK:
114 sem_bits = SEM_SET << SEM_RT_IDX_SHIFT;
116 case SEM_PROC_REG_MASK:
117 sem_bits = SEM_SET << SEM_PROC_REG_SHIFT;
120 QPRINTK(qdev, PROBE, ALERT, "Bad Semaphore mask!.\n");
124 ql_write32(qdev, SEM, sem_bits | sem_mask);
125 return !(ql_read32(qdev, SEM) & sem_bits);
128 int ql_sem_spinlock(struct ql_adapter *qdev, u32 sem_mask)
130 unsigned int seconds = 3;
132 if (!ql_sem_trylock(qdev, sem_mask))
139 void ql_sem_unlock(struct ql_adapter *qdev, u32 sem_mask)
141 ql_write32(qdev, SEM, sem_mask);
142 ql_read32(qdev, SEM); /* flush */
145 /* This function waits for a specific bit to come ready
146 * in a given register. It is used mostly by the initialize
147 * process, but is also used in kernel thread API such as
148 * netdev->set_multi, netdev->set_mac_address, netdev->vlan_rx_add_vid.
150 int ql_wait_reg_rdy(struct ql_adapter *qdev, u32 reg, u32 bit, u32 err_bit)
153 int count = UDELAY_COUNT;
156 temp = ql_read32(qdev, reg);
158 /* check for errors */
159 if (temp & err_bit) {
160 QPRINTK(qdev, PROBE, ALERT,
161 "register 0x%.08x access error, value = 0x%.08x!.\n",
164 } else if (temp & bit)
166 udelay(UDELAY_DELAY);
169 QPRINTK(qdev, PROBE, ALERT,
170 "Timed out waiting for reg %x to come ready.\n", reg);
174 /* The CFG register is used to download TX and RX control blocks
175 * to the chip. This function waits for an operation to complete.
177 static int ql_wait_cfg(struct ql_adapter *qdev, u32 bit)
179 int count = UDELAY_COUNT;
183 temp = ql_read32(qdev, CFG);
188 udelay(UDELAY_DELAY);
195 /* Used to issue init control blocks to hw. Maps control block,
196 * sets address, triggers download, waits for completion.
198 int ql_write_cfg(struct ql_adapter *qdev, void *ptr, int size, u32 bit,
208 (bit & (CFG_LRQ | CFG_LR | CFG_LCQ)) ? PCI_DMA_TODEVICE :
211 map = pci_map_single(qdev->pdev, ptr, size, direction);
212 if (pci_dma_mapping_error(qdev->pdev, map)) {
213 QPRINTK(qdev, IFUP, ERR, "Couldn't map DMA area.\n");
217 status = ql_wait_cfg(qdev, bit);
219 QPRINTK(qdev, IFUP, ERR,
220 "Timed out waiting for CFG to come ready.\n");
224 status = ql_sem_spinlock(qdev, SEM_ICB_MASK);
227 ql_write32(qdev, ICB_L, (u32) map);
228 ql_write32(qdev, ICB_H, (u32) (map >> 32));
229 ql_sem_unlock(qdev, SEM_ICB_MASK); /* does flush too */
231 mask = CFG_Q_MASK | (bit << 16);
232 value = bit | (q_id << CFG_Q_SHIFT);
233 ql_write32(qdev, CFG, (mask | value));
236 * Wait for the bit to clear after signaling hw.
238 status = ql_wait_cfg(qdev, bit);
240 pci_unmap_single(qdev->pdev, map, size, direction);
244 /* Get a specific MAC address from the CAM. Used for debug and reg dump. */
245 int ql_get_mac_addr_reg(struct ql_adapter *qdev, u32 type, u16 index,
251 status = ql_sem_spinlock(qdev, SEM_MAC_ADDR_MASK);
255 case MAC_ADDR_TYPE_MULTI_MAC:
256 case MAC_ADDR_TYPE_CAM_MAC:
259 ql_wait_reg_rdy(qdev,
260 MAC_ADDR_IDX, MAC_ADDR_MW, MAC_ADDR_E);
263 ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */
264 (index << MAC_ADDR_IDX_SHIFT) | /* index */
265 MAC_ADDR_ADR | MAC_ADDR_RS | type); /* type */
267 ql_wait_reg_rdy(qdev,
268 MAC_ADDR_IDX, MAC_ADDR_MR, MAC_ADDR_E);
271 *value++ = ql_read32(qdev, MAC_ADDR_DATA);
273 ql_wait_reg_rdy(qdev,
274 MAC_ADDR_IDX, MAC_ADDR_MW, MAC_ADDR_E);
277 ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */
278 (index << MAC_ADDR_IDX_SHIFT) | /* index */
279 MAC_ADDR_ADR | MAC_ADDR_RS | type); /* type */
281 ql_wait_reg_rdy(qdev,
282 MAC_ADDR_IDX, MAC_ADDR_MR, MAC_ADDR_E);
285 *value++ = ql_read32(qdev, MAC_ADDR_DATA);
286 if (type == MAC_ADDR_TYPE_CAM_MAC) {
288 ql_wait_reg_rdy(qdev,
289 MAC_ADDR_IDX, MAC_ADDR_MW, MAC_ADDR_E);
292 ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */
293 (index << MAC_ADDR_IDX_SHIFT) | /* index */
294 MAC_ADDR_ADR | MAC_ADDR_RS | type); /* type */
296 ql_wait_reg_rdy(qdev, MAC_ADDR_IDX,
297 MAC_ADDR_MR, MAC_ADDR_E);
300 *value++ = ql_read32(qdev, MAC_ADDR_DATA);
304 case MAC_ADDR_TYPE_VLAN:
305 case MAC_ADDR_TYPE_MULTI_FLTR:
307 QPRINTK(qdev, IFUP, CRIT,
308 "Address type %d not yet supported.\n", type);
312 ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK);
316 /* Set up a MAC, multicast or VLAN address for the
317 * inbound frame matching.
319 static int ql_set_mac_addr_reg(struct ql_adapter *qdev, u8 *addr, u32 type,
325 status = ql_sem_spinlock(qdev, SEM_MAC_ADDR_MASK);
329 case MAC_ADDR_TYPE_MULTI_MAC:
330 case MAC_ADDR_TYPE_CAM_MAC:
333 u32 upper = (addr[0] << 8) | addr[1];
335 (addr[2] << 24) | (addr[3] << 16) | (addr[4] << 8) |
338 QPRINTK(qdev, IFUP, INFO,
339 "Adding %s address %pM"
340 " at index %d in the CAM.\n",
342 MAC_ADDR_TYPE_MULTI_MAC) ? "MULTICAST" :
343 "UNICAST"), addr, index);
346 ql_wait_reg_rdy(qdev,
347 MAC_ADDR_IDX, MAC_ADDR_MW, MAC_ADDR_E);
350 ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */
351 (index << MAC_ADDR_IDX_SHIFT) | /* index */
353 ql_write32(qdev, MAC_ADDR_DATA, lower);
355 ql_wait_reg_rdy(qdev,
356 MAC_ADDR_IDX, MAC_ADDR_MW, MAC_ADDR_E);
359 ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */
360 (index << MAC_ADDR_IDX_SHIFT) | /* index */
362 ql_write32(qdev, MAC_ADDR_DATA, upper);
364 ql_wait_reg_rdy(qdev,
365 MAC_ADDR_IDX, MAC_ADDR_MW, MAC_ADDR_E);
368 ql_write32(qdev, MAC_ADDR_IDX, (offset) | /* offset */
369 (index << MAC_ADDR_IDX_SHIFT) | /* index */
371 /* This field should also include the queue id
372 and possibly the function id. Right now we hardcode
373 the route field to NIC core.
375 if (type == MAC_ADDR_TYPE_CAM_MAC) {
376 cam_output = (CAM_OUT_ROUTE_NIC |
378 func << CAM_OUT_FUNC_SHIFT) |
380 rss_ring_first_cq_id <<
381 CAM_OUT_CQ_ID_SHIFT));
383 cam_output |= CAM_OUT_RV;
384 /* route to NIC core */
385 ql_write32(qdev, MAC_ADDR_DATA, cam_output);
389 case MAC_ADDR_TYPE_VLAN:
391 u32 enable_bit = *((u32 *) &addr[0]);
392 /* For VLAN, the addr actually holds a bit that
393 * either enables or disables the vlan id we are
394 * addressing. It's either MAC_ADDR_E on or off.
395 * That's bit-27 we're talking about.
397 QPRINTK(qdev, IFUP, INFO, "%s VLAN ID %d %s the CAM.\n",
398 (enable_bit ? "Adding" : "Removing"),
399 index, (enable_bit ? "to" : "from"));
402 ql_wait_reg_rdy(qdev,
403 MAC_ADDR_IDX, MAC_ADDR_MW, MAC_ADDR_E);
406 ql_write32(qdev, MAC_ADDR_IDX, offset | /* offset */
407 (index << MAC_ADDR_IDX_SHIFT) | /* index */
409 enable_bit); /* enable/disable */
412 case MAC_ADDR_TYPE_MULTI_FLTR:
414 QPRINTK(qdev, IFUP, CRIT,
415 "Address type %d not yet supported.\n", type);
419 ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK);
423 /* Get a specific frame routing value from the CAM.
424 * Used for debug and reg dump.
426 int ql_get_routing_reg(struct ql_adapter *qdev, u32 index, u32 *value)
430 status = ql_sem_spinlock(qdev, SEM_RT_IDX_MASK);
434 status = ql_wait_reg_rdy(qdev, RT_IDX, RT_IDX_MW, RT_IDX_E);
438 ql_write32(qdev, RT_IDX,
439 RT_IDX_TYPE_NICQ | RT_IDX_RS | (index << RT_IDX_IDX_SHIFT));
440 status = ql_wait_reg_rdy(qdev, RT_IDX, RT_IDX_MR, RT_IDX_E);
443 *value = ql_read32(qdev, RT_DATA);
445 ql_sem_unlock(qdev, SEM_RT_IDX_MASK);
449 /* The NIC function for this chip has 16 routing indexes. Each one can be used
450 * to route different frame types to various inbound queues. We send broadcast/
451 * multicast/error frames to the default queue for slow handling,
452 * and CAM hit/RSS frames to the fast handling queues.
454 static int ql_set_routing_reg(struct ql_adapter *qdev, u32 index, u32 mask,
460 status = ql_sem_spinlock(qdev, SEM_RT_IDX_MASK);
464 QPRINTK(qdev, IFUP, DEBUG,
465 "%s %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s mask %s the routing reg.\n",
466 (enable ? "Adding" : "Removing"),
467 ((index == RT_IDX_ALL_ERR_SLOT) ? "MAC ERROR/ALL ERROR" : ""),
468 ((index == RT_IDX_IP_CSUM_ERR_SLOT) ? "IP CSUM ERROR" : ""),
470 RT_IDX_TCP_UDP_CSUM_ERR_SLOT) ? "TCP/UDP CSUM ERROR" : ""),
471 ((index == RT_IDX_BCAST_SLOT) ? "BROADCAST" : ""),
472 ((index == RT_IDX_MCAST_MATCH_SLOT) ? "MULTICAST MATCH" : ""),
473 ((index == RT_IDX_ALLMULTI_SLOT) ? "ALL MULTICAST MATCH" : ""),
474 ((index == RT_IDX_UNUSED6_SLOT) ? "UNUSED6" : ""),
475 ((index == RT_IDX_UNUSED7_SLOT) ? "UNUSED7" : ""),
476 ((index == RT_IDX_RSS_MATCH_SLOT) ? "RSS ALL/IPV4 MATCH" : ""),
477 ((index == RT_IDX_RSS_IPV6_SLOT) ? "RSS IPV6" : ""),
478 ((index == RT_IDX_RSS_TCP4_SLOT) ? "RSS TCP4" : ""),
479 ((index == RT_IDX_RSS_TCP6_SLOT) ? "RSS TCP6" : ""),
480 ((index == RT_IDX_CAM_HIT_SLOT) ? "CAM HIT" : ""),
481 ((index == RT_IDX_UNUSED013) ? "UNUSED13" : ""),
482 ((index == RT_IDX_UNUSED014) ? "UNUSED14" : ""),
483 ((index == RT_IDX_PROMISCUOUS_SLOT) ? "PROMISCUOUS" : ""),
484 (enable ? "to" : "from"));
489 value = RT_IDX_DST_CAM_Q | /* dest */
490 RT_IDX_TYPE_NICQ | /* type */
491 (RT_IDX_CAM_HIT_SLOT << RT_IDX_IDX_SHIFT);/* index */
494 case RT_IDX_VALID: /* Promiscuous Mode frames. */
496 value = RT_IDX_DST_DFLT_Q | /* dest */
497 RT_IDX_TYPE_NICQ | /* type */
498 (RT_IDX_PROMISCUOUS_SLOT << RT_IDX_IDX_SHIFT);/* index */
501 case RT_IDX_ERR: /* Pass up MAC,IP,TCP/UDP error frames. */
503 value = RT_IDX_DST_DFLT_Q | /* dest */
504 RT_IDX_TYPE_NICQ | /* type */
505 (RT_IDX_ALL_ERR_SLOT << RT_IDX_IDX_SHIFT);/* index */
508 case RT_IDX_BCAST: /* Pass up Broadcast frames to default Q. */
510 value = RT_IDX_DST_DFLT_Q | /* dest */
511 RT_IDX_TYPE_NICQ | /* type */
512 (RT_IDX_BCAST_SLOT << RT_IDX_IDX_SHIFT);/* index */
515 case RT_IDX_MCAST: /* Pass up All Multicast frames. */
517 value = RT_IDX_DST_CAM_Q | /* dest */
518 RT_IDX_TYPE_NICQ | /* type */
519 (RT_IDX_ALLMULTI_SLOT << RT_IDX_IDX_SHIFT);/* index */
522 case RT_IDX_MCAST_MATCH: /* Pass up matched Multicast frames. */
524 value = RT_IDX_DST_CAM_Q | /* dest */
525 RT_IDX_TYPE_NICQ | /* type */
526 (RT_IDX_MCAST_MATCH_SLOT << RT_IDX_IDX_SHIFT);/* index */
529 case RT_IDX_RSS_MATCH: /* Pass up matched RSS frames. */
531 value = RT_IDX_DST_RSS | /* dest */
532 RT_IDX_TYPE_NICQ | /* type */
533 (RT_IDX_RSS_MATCH_SLOT << RT_IDX_IDX_SHIFT);/* index */
536 case 0: /* Clear the E-bit on an entry. */
538 value = RT_IDX_DST_DFLT_Q | /* dest */
539 RT_IDX_TYPE_NICQ | /* type */
540 (index << RT_IDX_IDX_SHIFT);/* index */
544 QPRINTK(qdev, IFUP, ERR, "Mask type %d not yet supported.\n",
551 status = ql_wait_reg_rdy(qdev, RT_IDX, RT_IDX_MW, 0);
554 value |= (enable ? RT_IDX_E : 0);
555 ql_write32(qdev, RT_IDX, value);
556 ql_write32(qdev, RT_DATA, enable ? mask : 0);
559 ql_sem_unlock(qdev, SEM_RT_IDX_MASK);
563 static void ql_enable_interrupts(struct ql_adapter *qdev)
565 ql_write32(qdev, INTR_EN, (INTR_EN_EI << 16) | INTR_EN_EI);
568 static void ql_disable_interrupts(struct ql_adapter *qdev)
570 ql_write32(qdev, INTR_EN, (INTR_EN_EI << 16));
573 /* If we're running with multiple MSI-X vectors then we enable on the fly.
574 * Otherwise, we may have multiple outstanding workers and don't want to
575 * enable until the last one finishes. In this case, the irq_cnt gets
576 * incremented everytime we queue a worker and decremented everytime
577 * a worker finishes. Once it hits zero we enable the interrupt.
579 u32 ql_enable_completion_interrupt(struct ql_adapter *qdev, u32 intr)
582 unsigned long hw_flags = 0;
583 struct intr_context *ctx = qdev->intr_context + intr;
585 if (likely(test_bit(QL_MSIX_ENABLED, &qdev->flags) && intr)) {
586 /* Always enable if we're MSIX multi interrupts and
587 * it's not the default (zeroeth) interrupt.
589 ql_write32(qdev, INTR_EN,
591 var = ql_read32(qdev, STS);
595 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
596 if (atomic_dec_and_test(&ctx->irq_cnt)) {
597 ql_write32(qdev, INTR_EN,
599 var = ql_read32(qdev, STS);
601 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
605 static u32 ql_disable_completion_interrupt(struct ql_adapter *qdev, u32 intr)
608 unsigned long hw_flags;
609 struct intr_context *ctx;
611 /* HW disables for us if we're MSIX multi interrupts and
612 * it's not the default (zeroeth) interrupt.
614 if (likely(test_bit(QL_MSIX_ENABLED, &qdev->flags) && intr))
617 ctx = qdev->intr_context + intr;
618 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
619 if (!atomic_read(&ctx->irq_cnt)) {
620 ql_write32(qdev, INTR_EN,
622 var = ql_read32(qdev, STS);
624 atomic_inc(&ctx->irq_cnt);
625 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
629 static void ql_enable_all_completion_interrupts(struct ql_adapter *qdev)
632 for (i = 0; i < qdev->intr_count; i++) {
633 /* The enable call does a atomic_dec_and_test
634 * and enables only if the result is zero.
635 * So we precharge it here.
637 if (unlikely(!test_bit(QL_MSIX_ENABLED, &qdev->flags) ||
639 atomic_set(&qdev->intr_context[i].irq_cnt, 1);
640 ql_enable_completion_interrupt(qdev, i);
645 static int ql_read_flash_word(struct ql_adapter *qdev, int offset, u32 *data)
648 /* wait for reg to come ready */
649 status = ql_wait_reg_rdy(qdev,
650 FLASH_ADDR, FLASH_ADDR_RDY, FLASH_ADDR_ERR);
653 /* set up for reg read */
654 ql_write32(qdev, FLASH_ADDR, FLASH_ADDR_R | offset);
655 /* wait for reg to come ready */
656 status = ql_wait_reg_rdy(qdev,
657 FLASH_ADDR, FLASH_ADDR_RDY, FLASH_ADDR_ERR);
661 *data = ql_read32(qdev, FLASH_DATA);
666 static int ql_get_flash_params(struct ql_adapter *qdev)
670 u32 *p = (u32 *)&qdev->flash;
672 if (ql_sem_spinlock(qdev, SEM_FLASH_MASK))
675 for (i = 0; i < sizeof(qdev->flash) / sizeof(u32); i++, p++) {
676 status = ql_read_flash_word(qdev, i, p);
678 QPRINTK(qdev, IFUP, ERR, "Error reading flash.\n");
684 ql_sem_unlock(qdev, SEM_FLASH_MASK);
688 /* xgmac register are located behind the xgmac_addr and xgmac_data
689 * register pair. Each read/write requires us to wait for the ready
690 * bit before reading/writing the data.
692 static int ql_write_xgmac_reg(struct ql_adapter *qdev, u32 reg, u32 data)
695 /* wait for reg to come ready */
696 status = ql_wait_reg_rdy(qdev,
697 XGMAC_ADDR, XGMAC_ADDR_RDY, XGMAC_ADDR_XME);
700 /* write the data to the data reg */
701 ql_write32(qdev, XGMAC_DATA, data);
702 /* trigger the write */
703 ql_write32(qdev, XGMAC_ADDR, reg);
707 /* xgmac register are located behind the xgmac_addr and xgmac_data
708 * register pair. Each read/write requires us to wait for the ready
709 * bit before reading/writing the data.
711 int ql_read_xgmac_reg(struct ql_adapter *qdev, u32 reg, u32 *data)
714 /* wait for reg to come ready */
715 status = ql_wait_reg_rdy(qdev,
716 XGMAC_ADDR, XGMAC_ADDR_RDY, XGMAC_ADDR_XME);
719 /* set up for reg read */
720 ql_write32(qdev, XGMAC_ADDR, reg | XGMAC_ADDR_R);
721 /* wait for reg to come ready */
722 status = ql_wait_reg_rdy(qdev,
723 XGMAC_ADDR, XGMAC_ADDR_RDY, XGMAC_ADDR_XME);
727 *data = ql_read32(qdev, XGMAC_DATA);
732 /* This is used for reading the 64-bit statistics regs. */
733 int ql_read_xgmac_reg64(struct ql_adapter *qdev, u32 reg, u64 *data)
739 status = ql_read_xgmac_reg(qdev, reg, &lo);
743 status = ql_read_xgmac_reg(qdev, reg + 4, &hi);
747 *data = (u64) lo | ((u64) hi << 32);
753 /* Take the MAC Core out of reset.
754 * Enable statistics counting.
755 * Take the transmitter/receiver out of reset.
756 * This functionality may be done in the MPI firmware at a
759 static int ql_port_initialize(struct ql_adapter *qdev)
764 if (ql_sem_trylock(qdev, qdev->xg_sem_mask)) {
765 /* Another function has the semaphore, so
766 * wait for the port init bit to come ready.
768 QPRINTK(qdev, LINK, INFO,
769 "Another function has the semaphore, so wait for the port init bit to come ready.\n");
770 status = ql_wait_reg_rdy(qdev, STS, qdev->port_init, 0);
772 QPRINTK(qdev, LINK, CRIT,
773 "Port initialize timed out.\n");
778 QPRINTK(qdev, LINK, INFO, "Got xgmac semaphore!.\n");
779 /* Set the core reset. */
780 status = ql_read_xgmac_reg(qdev, GLOBAL_CFG, &data);
783 data |= GLOBAL_CFG_RESET;
784 status = ql_write_xgmac_reg(qdev, GLOBAL_CFG, data);
788 /* Clear the core reset and turn on jumbo for receiver. */
789 data &= ~GLOBAL_CFG_RESET; /* Clear core reset. */
790 data |= GLOBAL_CFG_JUMBO; /* Turn on jumbo. */
791 data |= GLOBAL_CFG_TX_STAT_EN;
792 data |= GLOBAL_CFG_RX_STAT_EN;
793 status = ql_write_xgmac_reg(qdev, GLOBAL_CFG, data);
797 /* Enable transmitter, and clear it's reset. */
798 status = ql_read_xgmac_reg(qdev, TX_CFG, &data);
801 data &= ~TX_CFG_RESET; /* Clear the TX MAC reset. */
802 data |= TX_CFG_EN; /* Enable the transmitter. */
803 status = ql_write_xgmac_reg(qdev, TX_CFG, data);
807 /* Enable receiver and clear it's reset. */
808 status = ql_read_xgmac_reg(qdev, RX_CFG, &data);
811 data &= ~RX_CFG_RESET; /* Clear the RX MAC reset. */
812 data |= RX_CFG_EN; /* Enable the receiver. */
813 status = ql_write_xgmac_reg(qdev, RX_CFG, data);
819 ql_write_xgmac_reg(qdev, MAC_TX_PARAMS, MAC_TX_PARAMS_JUMBO | (0x2580 << 16));
823 ql_write_xgmac_reg(qdev, MAC_RX_PARAMS, 0x2580);
827 /* Signal to the world that the port is enabled. */
828 ql_write32(qdev, STS, ((qdev->port_init << 16) | qdev->port_init));
830 ql_sem_unlock(qdev, qdev->xg_sem_mask);
834 /* Get the next large buffer. */
835 static struct bq_desc *ql_get_curr_lbuf(struct rx_ring *rx_ring)
837 struct bq_desc *lbq_desc = &rx_ring->lbq[rx_ring->lbq_curr_idx];
838 rx_ring->lbq_curr_idx++;
839 if (rx_ring->lbq_curr_idx == rx_ring->lbq_len)
840 rx_ring->lbq_curr_idx = 0;
841 rx_ring->lbq_free_cnt++;
845 /* Get the next small buffer. */
846 static struct bq_desc *ql_get_curr_sbuf(struct rx_ring *rx_ring)
848 struct bq_desc *sbq_desc = &rx_ring->sbq[rx_ring->sbq_curr_idx];
849 rx_ring->sbq_curr_idx++;
850 if (rx_ring->sbq_curr_idx == rx_ring->sbq_len)
851 rx_ring->sbq_curr_idx = 0;
852 rx_ring->sbq_free_cnt++;
856 /* Update an rx ring index. */
857 static void ql_update_cq(struct rx_ring *rx_ring)
859 rx_ring->cnsmr_idx++;
860 rx_ring->curr_entry++;
861 if (unlikely(rx_ring->cnsmr_idx == rx_ring->cq_len)) {
862 rx_ring->cnsmr_idx = 0;
863 rx_ring->curr_entry = rx_ring->cq_base;
867 static void ql_write_cq_idx(struct rx_ring *rx_ring)
869 ql_write_db_reg(rx_ring->cnsmr_idx, rx_ring->cnsmr_idx_db_reg);
872 /* Process (refill) a large buffer queue. */
873 static void ql_update_lbq(struct ql_adapter *qdev, struct rx_ring *rx_ring)
875 int clean_idx = rx_ring->lbq_clean_idx;
876 struct bq_desc *lbq_desc;
877 struct bq_element *bq;
881 while (rx_ring->lbq_free_cnt > 16) {
882 for (i = 0; i < 16; i++) {
883 QPRINTK(qdev, RX_STATUS, DEBUG,
884 "lbq: try cleaning clean_idx = %d.\n",
886 lbq_desc = &rx_ring->lbq[clean_idx];
888 if (lbq_desc->p.lbq_page == NULL) {
889 QPRINTK(qdev, RX_STATUS, DEBUG,
890 "lbq: getting new page for index %d.\n",
892 lbq_desc->p.lbq_page = alloc_page(GFP_ATOMIC);
893 if (lbq_desc->p.lbq_page == NULL) {
894 QPRINTK(qdev, RX_STATUS, ERR,
895 "Couldn't get a page.\n");
898 map = pci_map_page(qdev->pdev,
899 lbq_desc->p.lbq_page,
902 if (pci_dma_mapping_error(qdev->pdev, map)) {
903 QPRINTK(qdev, RX_STATUS, ERR,
904 "PCI mapping failed.\n");
907 pci_unmap_addr_set(lbq_desc, mapaddr, map);
908 pci_unmap_len_set(lbq_desc, maplen, PAGE_SIZE);
909 bq->addr_lo = /*lbq_desc->addr_lo = */
911 bq->addr_hi = /*lbq_desc->addr_hi = */
912 cpu_to_le32(map >> 32);
915 if (clean_idx == rx_ring->lbq_len)
919 rx_ring->lbq_clean_idx = clean_idx;
920 rx_ring->lbq_prod_idx += 16;
921 if (rx_ring->lbq_prod_idx == rx_ring->lbq_len)
922 rx_ring->lbq_prod_idx = 0;
923 QPRINTK(qdev, RX_STATUS, DEBUG,
924 "lbq: updating prod idx = %d.\n",
925 rx_ring->lbq_prod_idx);
926 ql_write_db_reg(rx_ring->lbq_prod_idx,
927 rx_ring->lbq_prod_idx_db_reg);
928 rx_ring->lbq_free_cnt -= 16;
932 /* Process (refill) a small buffer queue. */
933 static void ql_update_sbq(struct ql_adapter *qdev, struct rx_ring *rx_ring)
935 int clean_idx = rx_ring->sbq_clean_idx;
936 struct bq_desc *sbq_desc;
937 struct bq_element *bq;
941 while (rx_ring->sbq_free_cnt > 16) {
942 for (i = 0; i < 16; i++) {
943 sbq_desc = &rx_ring->sbq[clean_idx];
944 QPRINTK(qdev, RX_STATUS, DEBUG,
945 "sbq: try cleaning clean_idx = %d.\n",
948 if (sbq_desc->p.skb == NULL) {
949 QPRINTK(qdev, RX_STATUS, DEBUG,
950 "sbq: getting new skb for index %d.\n",
953 netdev_alloc_skb(qdev->ndev,
954 rx_ring->sbq_buf_size);
955 if (sbq_desc->p.skb == NULL) {
956 QPRINTK(qdev, PROBE, ERR,
957 "Couldn't get an skb.\n");
958 rx_ring->sbq_clean_idx = clean_idx;
961 skb_reserve(sbq_desc->p.skb, QLGE_SB_PAD);
962 map = pci_map_single(qdev->pdev,
963 sbq_desc->p.skb->data,
964 rx_ring->sbq_buf_size /
965 2, PCI_DMA_FROMDEVICE);
966 pci_unmap_addr_set(sbq_desc, mapaddr, map);
967 pci_unmap_len_set(sbq_desc, maplen,
968 rx_ring->sbq_buf_size / 2);
969 bq->addr_lo = cpu_to_le32(map);
970 bq->addr_hi = cpu_to_le32(map >> 32);
974 if (clean_idx == rx_ring->sbq_len)
977 rx_ring->sbq_clean_idx = clean_idx;
978 rx_ring->sbq_prod_idx += 16;
979 if (rx_ring->sbq_prod_idx == rx_ring->sbq_len)
980 rx_ring->sbq_prod_idx = 0;
981 QPRINTK(qdev, RX_STATUS, DEBUG,
982 "sbq: updating prod idx = %d.\n",
983 rx_ring->sbq_prod_idx);
984 ql_write_db_reg(rx_ring->sbq_prod_idx,
985 rx_ring->sbq_prod_idx_db_reg);
987 rx_ring->sbq_free_cnt -= 16;
991 static void ql_update_buffer_queues(struct ql_adapter *qdev,
992 struct rx_ring *rx_ring)
994 ql_update_sbq(qdev, rx_ring);
995 ql_update_lbq(qdev, rx_ring);
998 /* Unmaps tx buffers. Can be called from send() if a pci mapping
999 * fails at some stage, or from the interrupt when a tx completes.
1001 static void ql_unmap_send(struct ql_adapter *qdev,
1002 struct tx_ring_desc *tx_ring_desc, int mapped)
1005 for (i = 0; i < mapped; i++) {
1006 if (i == 0 || (i == 7 && mapped > 7)) {
1008 * Unmap the skb->data area, or the
1009 * external sglist (AKA the Outbound
1010 * Address List (OAL)).
1011 * If its the zeroeth element, then it's
1012 * the skb->data area. If it's the 7th
1013 * element and there is more than 6 frags,
1017 QPRINTK(qdev, TX_DONE, DEBUG,
1018 "unmapping OAL area.\n");
1020 pci_unmap_single(qdev->pdev,
1021 pci_unmap_addr(&tx_ring_desc->map[i],
1023 pci_unmap_len(&tx_ring_desc->map[i],
1027 QPRINTK(qdev, TX_DONE, DEBUG, "unmapping frag %d.\n",
1029 pci_unmap_page(qdev->pdev,
1030 pci_unmap_addr(&tx_ring_desc->map[i],
1032 pci_unmap_len(&tx_ring_desc->map[i],
1033 maplen), PCI_DMA_TODEVICE);
1039 /* Map the buffers for this transmit. This will return
1040 * NETDEV_TX_BUSY or NETDEV_TX_OK based on success.
1042 static int ql_map_send(struct ql_adapter *qdev,
1043 struct ob_mac_iocb_req *mac_iocb_ptr,
1044 struct sk_buff *skb, struct tx_ring_desc *tx_ring_desc)
1046 int len = skb_headlen(skb);
1048 int frag_idx, err, map_idx = 0;
1049 struct tx_buf_desc *tbd = mac_iocb_ptr->tbd;
1050 int frag_cnt = skb_shinfo(skb)->nr_frags;
1053 QPRINTK(qdev, TX_QUEUED, DEBUG, "frag_cnt = %d.\n", frag_cnt);
1056 * Map the skb buffer first.
1058 map = pci_map_single(qdev->pdev, skb->data, len, PCI_DMA_TODEVICE);
1060 err = pci_dma_mapping_error(qdev->pdev, map);
1062 QPRINTK(qdev, TX_QUEUED, ERR,
1063 "PCI mapping failed with error: %d\n", err);
1065 return NETDEV_TX_BUSY;
1068 tbd->len = cpu_to_le32(len);
1069 tbd->addr = cpu_to_le64(map);
1070 pci_unmap_addr_set(&tx_ring_desc->map[map_idx], mapaddr, map);
1071 pci_unmap_len_set(&tx_ring_desc->map[map_idx], maplen, len);
1075 * This loop fills the remainder of the 8 address descriptors
1076 * in the IOCB. If there are more than 7 fragments, then the
1077 * eighth address desc will point to an external list (OAL).
1078 * When this happens, the remainder of the frags will be stored
1081 for (frag_idx = 0; frag_idx < frag_cnt; frag_idx++, map_idx++) {
1082 skb_frag_t *frag = &skb_shinfo(skb)->frags[frag_idx];
1084 if (frag_idx == 6 && frag_cnt > 7) {
1085 /* Let's tack on an sglist.
1086 * Our control block will now
1088 * iocb->seg[0] = skb->data
1089 * iocb->seg[1] = frag[0]
1090 * iocb->seg[2] = frag[1]
1091 * iocb->seg[3] = frag[2]
1092 * iocb->seg[4] = frag[3]
1093 * iocb->seg[5] = frag[4]
1094 * iocb->seg[6] = frag[5]
1095 * iocb->seg[7] = ptr to OAL (external sglist)
1096 * oal->seg[0] = frag[6]
1097 * oal->seg[1] = frag[7]
1098 * oal->seg[2] = frag[8]
1099 * oal->seg[3] = frag[9]
1100 * oal->seg[4] = frag[10]
1103 /* Tack on the OAL in the eighth segment of IOCB. */
1104 map = pci_map_single(qdev->pdev, &tx_ring_desc->oal,
1107 err = pci_dma_mapping_error(qdev->pdev, map);
1109 QPRINTK(qdev, TX_QUEUED, ERR,
1110 "PCI mapping outbound address list with error: %d\n",
1115 tbd->addr = cpu_to_le64(map);
1117 * The length is the number of fragments
1118 * that remain to be mapped times the length
1119 * of our sglist (OAL).
1122 cpu_to_le32((sizeof(struct tx_buf_desc) *
1123 (frag_cnt - frag_idx)) | TX_DESC_C);
1124 pci_unmap_addr_set(&tx_ring_desc->map[map_idx], mapaddr,
1126 pci_unmap_len_set(&tx_ring_desc->map[map_idx], maplen,
1127 sizeof(struct oal));
1128 tbd = (struct tx_buf_desc *)&tx_ring_desc->oal;
1133 pci_map_page(qdev->pdev, frag->page,
1134 frag->page_offset, frag->size,
1137 err = pci_dma_mapping_error(qdev->pdev, map);
1139 QPRINTK(qdev, TX_QUEUED, ERR,
1140 "PCI mapping frags failed with error: %d.\n",
1145 tbd->addr = cpu_to_le64(map);
1146 tbd->len = cpu_to_le32(frag->size);
1147 pci_unmap_addr_set(&tx_ring_desc->map[map_idx], mapaddr, map);
1148 pci_unmap_len_set(&tx_ring_desc->map[map_idx], maplen,
1152 /* Save the number of segments we've mapped. */
1153 tx_ring_desc->map_cnt = map_idx;
1154 /* Terminate the last segment. */
1155 tbd->len = cpu_to_le32(le32_to_cpu(tbd->len) | TX_DESC_E);
1156 return NETDEV_TX_OK;
1160 * If the first frag mapping failed, then i will be zero.
1161 * This causes the unmap of the skb->data area. Otherwise
1162 * we pass in the number of frags that mapped successfully
1163 * so they can be umapped.
1165 ql_unmap_send(qdev, tx_ring_desc, map_idx);
1166 return NETDEV_TX_BUSY;
1169 static void ql_realign_skb(struct sk_buff *skb, int len)
1171 void *temp_addr = skb->data;
1173 /* Undo the skb_reserve(skb,32) we did before
1174 * giving to hardware, and realign data on
1175 * a 2-byte boundary.
1177 skb->data -= QLGE_SB_PAD - NET_IP_ALIGN;
1178 skb->tail -= QLGE_SB_PAD - NET_IP_ALIGN;
1179 skb_copy_to_linear_data(skb, temp_addr,
1184 * This function builds an skb for the given inbound
1185 * completion. It will be rewritten for readability in the near
1186 * future, but for not it works well.
1188 static struct sk_buff *ql_build_rx_skb(struct ql_adapter *qdev,
1189 struct rx_ring *rx_ring,
1190 struct ib_mac_iocb_rsp *ib_mac_rsp)
1192 struct bq_desc *lbq_desc;
1193 struct bq_desc *sbq_desc;
1194 struct sk_buff *skb = NULL;
1195 u32 length = le32_to_cpu(ib_mac_rsp->data_len);
1196 u32 hdr_len = le32_to_cpu(ib_mac_rsp->hdr_len);
1199 * Handle the header buffer if present.
1201 if (ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HV &&
1202 ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HS) {
1203 QPRINTK(qdev, RX_STATUS, DEBUG, "Header of %d bytes in small buffer.\n", hdr_len);
1205 * Headers fit nicely into a small buffer.
1207 sbq_desc = ql_get_curr_sbuf(rx_ring);
1208 pci_unmap_single(qdev->pdev,
1209 pci_unmap_addr(sbq_desc, mapaddr),
1210 pci_unmap_len(sbq_desc, maplen),
1211 PCI_DMA_FROMDEVICE);
1212 skb = sbq_desc->p.skb;
1213 ql_realign_skb(skb, hdr_len);
1214 skb_put(skb, hdr_len);
1215 sbq_desc->p.skb = NULL;
1219 * Handle the data buffer(s).
1221 if (unlikely(!length)) { /* Is there data too? */
1222 QPRINTK(qdev, RX_STATUS, DEBUG,
1223 "No Data buffer in this packet.\n");
1227 if (ib_mac_rsp->flags3 & IB_MAC_IOCB_RSP_DS) {
1228 if (ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HS) {
1229 QPRINTK(qdev, RX_STATUS, DEBUG,
1230 "Headers in small, data of %d bytes in small, combine them.\n", length);
1232 * Data is less than small buffer size so it's
1233 * stuffed in a small buffer.
1234 * For this case we append the data
1235 * from the "data" small buffer to the "header" small
1238 sbq_desc = ql_get_curr_sbuf(rx_ring);
1239 pci_dma_sync_single_for_cpu(qdev->pdev,
1241 (sbq_desc, mapaddr),
1244 PCI_DMA_FROMDEVICE);
1245 memcpy(skb_put(skb, length),
1246 sbq_desc->p.skb->data, length);
1247 pci_dma_sync_single_for_device(qdev->pdev,
1254 PCI_DMA_FROMDEVICE);
1256 QPRINTK(qdev, RX_STATUS, DEBUG,
1257 "%d bytes in a single small buffer.\n", length);
1258 sbq_desc = ql_get_curr_sbuf(rx_ring);
1259 skb = sbq_desc->p.skb;
1260 ql_realign_skb(skb, length);
1261 skb_put(skb, length);
1262 pci_unmap_single(qdev->pdev,
1263 pci_unmap_addr(sbq_desc,
1265 pci_unmap_len(sbq_desc,
1267 PCI_DMA_FROMDEVICE);
1268 sbq_desc->p.skb = NULL;
1270 } else if (ib_mac_rsp->flags3 & IB_MAC_IOCB_RSP_DL) {
1271 if (ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HS) {
1272 QPRINTK(qdev, RX_STATUS, DEBUG,
1273 "Header in small, %d bytes in large. Chain large to small!\n", length);
1275 * The data is in a single large buffer. We
1276 * chain it to the header buffer's skb and let
1279 lbq_desc = ql_get_curr_lbuf(rx_ring);
1280 pci_unmap_page(qdev->pdev,
1281 pci_unmap_addr(lbq_desc,
1283 pci_unmap_len(lbq_desc, maplen),
1284 PCI_DMA_FROMDEVICE);
1285 QPRINTK(qdev, RX_STATUS, DEBUG,
1286 "Chaining page to skb.\n");
1287 skb_fill_page_desc(skb, 0, lbq_desc->p.lbq_page,
1290 skb->data_len += length;
1291 skb->truesize += length;
1292 lbq_desc->p.lbq_page = NULL;
1295 * The headers and data are in a single large buffer. We
1296 * copy it to a new skb and let it go. This can happen with
1297 * jumbo mtu on a non-TCP/UDP frame.
1299 lbq_desc = ql_get_curr_lbuf(rx_ring);
1300 skb = netdev_alloc_skb(qdev->ndev, length);
1302 QPRINTK(qdev, PROBE, DEBUG,
1303 "No skb available, drop the packet.\n");
1306 skb_reserve(skb, NET_IP_ALIGN);
1307 QPRINTK(qdev, RX_STATUS, DEBUG,
1308 "%d bytes of headers and data in large. Chain page to new skb and pull tail.\n", length);
1309 skb_fill_page_desc(skb, 0, lbq_desc->p.lbq_page,
1312 skb->data_len += length;
1313 skb->truesize += length;
1315 lbq_desc->p.lbq_page = NULL;
1316 __pskb_pull_tail(skb,
1317 (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_V) ?
1318 VLAN_ETH_HLEN : ETH_HLEN);
1322 * The data is in a chain of large buffers
1323 * pointed to by a small buffer. We loop
1324 * thru and chain them to the our small header
1326 * frags: There are 18 max frags and our small
1327 * buffer will hold 32 of them. The thing is,
1328 * we'll use 3 max for our 9000 byte jumbo
1329 * frames. If the MTU goes up we could
1330 * eventually be in trouble.
1332 int size, offset, i = 0;
1333 struct bq_element *bq, bq_array[8];
1334 sbq_desc = ql_get_curr_sbuf(rx_ring);
1335 pci_unmap_single(qdev->pdev,
1336 pci_unmap_addr(sbq_desc, mapaddr),
1337 pci_unmap_len(sbq_desc, maplen),
1338 PCI_DMA_FROMDEVICE);
1339 if (!(ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HS)) {
1341 * This is an non TCP/UDP IP frame, so
1342 * the headers aren't split into a small
1343 * buffer. We have to use the small buffer
1344 * that contains our sg list as our skb to
1345 * send upstairs. Copy the sg list here to
1346 * a local buffer and use it to find the
1349 QPRINTK(qdev, RX_STATUS, DEBUG,
1350 "%d bytes of headers & data in chain of large.\n", length);
1351 skb = sbq_desc->p.skb;
1353 memcpy(bq, skb->data, sizeof(bq_array));
1354 sbq_desc->p.skb = NULL;
1355 skb_reserve(skb, NET_IP_ALIGN);
1357 QPRINTK(qdev, RX_STATUS, DEBUG,
1358 "Headers in small, %d bytes of data in chain of large.\n", length);
1359 bq = (struct bq_element *)sbq_desc->p.skb->data;
1361 while (length > 0) {
1362 lbq_desc = ql_get_curr_lbuf(rx_ring);
1363 if ((bq->addr_lo & ~BQ_MASK) != lbq_desc->bq->addr_lo) {
1364 QPRINTK(qdev, RX_STATUS, ERR,
1365 "Panic!!! bad large buffer address, expected 0x%.08x, got 0x%.08x.\n",
1366 lbq_desc->bq->addr_lo, bq->addr_lo);
1369 pci_unmap_page(qdev->pdev,
1370 pci_unmap_addr(lbq_desc,
1372 pci_unmap_len(lbq_desc,
1374 PCI_DMA_FROMDEVICE);
1375 size = (length < PAGE_SIZE) ? length : PAGE_SIZE;
1378 QPRINTK(qdev, RX_STATUS, DEBUG,
1379 "Adding page %d to skb for %d bytes.\n",
1381 skb_fill_page_desc(skb, i, lbq_desc->p.lbq_page,
1384 skb->data_len += size;
1385 skb->truesize += size;
1387 lbq_desc->p.lbq_page = NULL;
1391 __pskb_pull_tail(skb, (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_V) ?
1392 VLAN_ETH_HLEN : ETH_HLEN);
1397 /* Process an inbound completion from an rx ring. */
1398 static void ql_process_mac_rx_intr(struct ql_adapter *qdev,
1399 struct rx_ring *rx_ring,
1400 struct ib_mac_iocb_rsp *ib_mac_rsp)
1402 struct net_device *ndev = qdev->ndev;
1403 struct sk_buff *skb = NULL;
1405 QL_DUMP_IB_MAC_RSP(ib_mac_rsp);
1407 skb = ql_build_rx_skb(qdev, rx_ring, ib_mac_rsp);
1408 if (unlikely(!skb)) {
1409 QPRINTK(qdev, RX_STATUS, DEBUG,
1410 "No skb available, drop packet.\n");
1414 prefetch(skb->data);
1416 if (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) {
1417 QPRINTK(qdev, RX_STATUS, DEBUG, "%s%s%s Multicast.\n",
1418 (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) ==
1419 IB_MAC_IOCB_RSP_M_HASH ? "Hash" : "",
1420 (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) ==
1421 IB_MAC_IOCB_RSP_M_REG ? "Registered" : "",
1422 (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) ==
1423 IB_MAC_IOCB_RSP_M_PROM ? "Promiscuous" : "");
1425 if (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_P) {
1426 QPRINTK(qdev, RX_STATUS, DEBUG, "Promiscuous Packet.\n");
1428 if (ib_mac_rsp->flags1 & (IB_MAC_IOCB_RSP_IE | IB_MAC_IOCB_RSP_TE)) {
1429 QPRINTK(qdev, RX_STATUS, ERR,
1430 "Bad checksum for this %s packet.\n",
1432 flags2 & IB_MAC_IOCB_RSP_T) ? "TCP" : "UDP"));
1433 skb->ip_summed = CHECKSUM_NONE;
1434 } else if (qdev->rx_csum &&
1435 ((ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_T) ||
1436 ((ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_U) &&
1437 !(ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_NU)))) {
1438 QPRINTK(qdev, RX_STATUS, DEBUG, "RX checksum done!\n");
1439 skb->ip_summed = CHECKSUM_UNNECESSARY;
1441 qdev->stats.rx_packets++;
1442 qdev->stats.rx_bytes += skb->len;
1443 skb->protocol = eth_type_trans(skb, ndev);
1444 if (qdev->vlgrp && (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_V)) {
1445 QPRINTK(qdev, RX_STATUS, DEBUG,
1446 "Passing a VLAN packet upstream.\n");
1447 vlan_hwaccel_rx(skb, qdev->vlgrp,
1448 le16_to_cpu(ib_mac_rsp->vlan_id));
1450 QPRINTK(qdev, RX_STATUS, DEBUG,
1451 "Passing a normal packet upstream.\n");
1456 /* Process an outbound completion from an rx ring. */
1457 static void ql_process_mac_tx_intr(struct ql_adapter *qdev,
1458 struct ob_mac_iocb_rsp *mac_rsp)
1460 struct tx_ring *tx_ring;
1461 struct tx_ring_desc *tx_ring_desc;
1463 QL_DUMP_OB_MAC_RSP(mac_rsp);
1464 tx_ring = &qdev->tx_ring[mac_rsp->txq_idx];
1465 tx_ring_desc = &tx_ring->q[mac_rsp->tid];
1466 ql_unmap_send(qdev, tx_ring_desc, tx_ring_desc->map_cnt);
1467 qdev->stats.tx_bytes += tx_ring_desc->map_cnt;
1468 qdev->stats.tx_packets++;
1469 dev_kfree_skb(tx_ring_desc->skb);
1470 tx_ring_desc->skb = NULL;
1472 if (unlikely(mac_rsp->flags1 & (OB_MAC_IOCB_RSP_E |
1475 OB_MAC_IOCB_RSP_P | OB_MAC_IOCB_RSP_B))) {
1476 if (mac_rsp->flags1 & OB_MAC_IOCB_RSP_E) {
1477 QPRINTK(qdev, TX_DONE, WARNING,
1478 "Total descriptor length did not match transfer length.\n");
1480 if (mac_rsp->flags1 & OB_MAC_IOCB_RSP_S) {
1481 QPRINTK(qdev, TX_DONE, WARNING,
1482 "Frame too short to be legal, not sent.\n");
1484 if (mac_rsp->flags1 & OB_MAC_IOCB_RSP_L) {
1485 QPRINTK(qdev, TX_DONE, WARNING,
1486 "Frame too long, but sent anyway.\n");
1488 if (mac_rsp->flags1 & OB_MAC_IOCB_RSP_B) {
1489 QPRINTK(qdev, TX_DONE, WARNING,
1490 "PCI backplane error. Frame not sent.\n");
1493 atomic_inc(&tx_ring->tx_count);
1496 /* Fire up a handler to reset the MPI processor. */
1497 void ql_queue_fw_error(struct ql_adapter *qdev)
1499 netif_stop_queue(qdev->ndev);
1500 netif_carrier_off(qdev->ndev);
1501 queue_delayed_work(qdev->workqueue, &qdev->mpi_reset_work, 0);
1504 void ql_queue_asic_error(struct ql_adapter *qdev)
1506 netif_stop_queue(qdev->ndev);
1507 netif_carrier_off(qdev->ndev);
1508 ql_disable_interrupts(qdev);
1509 queue_delayed_work(qdev->workqueue, &qdev->asic_reset_work, 0);
1512 static void ql_process_chip_ae_intr(struct ql_adapter *qdev,
1513 struct ib_ae_iocb_rsp *ib_ae_rsp)
1515 switch (ib_ae_rsp->event) {
1516 case MGMT_ERR_EVENT:
1517 QPRINTK(qdev, RX_ERR, ERR,
1518 "Management Processor Fatal Error.\n");
1519 ql_queue_fw_error(qdev);
1522 case CAM_LOOKUP_ERR_EVENT:
1523 QPRINTK(qdev, LINK, ERR,
1524 "Multiple CAM hits lookup occurred.\n");
1525 QPRINTK(qdev, DRV, ERR, "This event shouldn't occur.\n");
1526 ql_queue_asic_error(qdev);
1529 case SOFT_ECC_ERROR_EVENT:
1530 QPRINTK(qdev, RX_ERR, ERR, "Soft ECC error detected.\n");
1531 ql_queue_asic_error(qdev);
1534 case PCI_ERR_ANON_BUF_RD:
1535 QPRINTK(qdev, RX_ERR, ERR,
1536 "PCI error occurred when reading anonymous buffers from rx_ring %d.\n",
1538 ql_queue_asic_error(qdev);
1542 QPRINTK(qdev, DRV, ERR, "Unexpected event %d.\n",
1544 ql_queue_asic_error(qdev);
1549 static int ql_clean_outbound_rx_ring(struct rx_ring *rx_ring)
1551 struct ql_adapter *qdev = rx_ring->qdev;
1552 u32 prod = ql_read_sh_reg(rx_ring->prod_idx_sh_reg);
1553 struct ob_mac_iocb_rsp *net_rsp = NULL;
1556 /* While there are entries in the completion queue. */
1557 while (prod != rx_ring->cnsmr_idx) {
1559 QPRINTK(qdev, RX_STATUS, DEBUG,
1560 "cq_id = %d, prod = %d, cnsmr = %d.\n.", rx_ring->cq_id,
1561 prod, rx_ring->cnsmr_idx);
1563 net_rsp = (struct ob_mac_iocb_rsp *)rx_ring->curr_entry;
1565 switch (net_rsp->opcode) {
1567 case OPCODE_OB_MAC_TSO_IOCB:
1568 case OPCODE_OB_MAC_IOCB:
1569 ql_process_mac_tx_intr(qdev, net_rsp);
1572 QPRINTK(qdev, RX_STATUS, DEBUG,
1573 "Hit default case, not handled! dropping the packet, opcode = %x.\n",
1577 ql_update_cq(rx_ring);
1578 prod = ql_read_sh_reg(rx_ring->prod_idx_sh_reg);
1580 ql_write_cq_idx(rx_ring);
1581 if (netif_queue_stopped(qdev->ndev) && net_rsp != NULL) {
1582 struct tx_ring *tx_ring = &qdev->tx_ring[net_rsp->txq_idx];
1583 if (atomic_read(&tx_ring->queue_stopped) &&
1584 (atomic_read(&tx_ring->tx_count) > (tx_ring->wq_len / 4)))
1586 * The queue got stopped because the tx_ring was full.
1587 * Wake it up, because it's now at least 25% empty.
1589 netif_wake_queue(qdev->ndev);
1595 static int ql_clean_inbound_rx_ring(struct rx_ring *rx_ring, int budget)
1597 struct ql_adapter *qdev = rx_ring->qdev;
1598 u32 prod = ql_read_sh_reg(rx_ring->prod_idx_sh_reg);
1599 struct ql_net_rsp_iocb *net_rsp;
1602 /* While there are entries in the completion queue. */
1603 while (prod != rx_ring->cnsmr_idx) {
1605 QPRINTK(qdev, RX_STATUS, DEBUG,
1606 "cq_id = %d, prod = %d, cnsmr = %d.\n.", rx_ring->cq_id,
1607 prod, rx_ring->cnsmr_idx);
1609 net_rsp = rx_ring->curr_entry;
1611 switch (net_rsp->opcode) {
1612 case OPCODE_IB_MAC_IOCB:
1613 ql_process_mac_rx_intr(qdev, rx_ring,
1614 (struct ib_mac_iocb_rsp *)
1618 case OPCODE_IB_AE_IOCB:
1619 ql_process_chip_ae_intr(qdev, (struct ib_ae_iocb_rsp *)
1624 QPRINTK(qdev, RX_STATUS, DEBUG,
1625 "Hit default case, not handled! dropping the packet, opcode = %x.\n",
1630 ql_update_cq(rx_ring);
1631 prod = ql_read_sh_reg(rx_ring->prod_idx_sh_reg);
1632 if (count == budget)
1635 ql_update_buffer_queues(qdev, rx_ring);
1636 ql_write_cq_idx(rx_ring);
1640 static int ql_napi_poll_msix(struct napi_struct *napi, int budget)
1642 struct rx_ring *rx_ring = container_of(napi, struct rx_ring, napi);
1643 struct ql_adapter *qdev = rx_ring->qdev;
1644 int work_done = ql_clean_inbound_rx_ring(rx_ring, budget);
1646 QPRINTK(qdev, RX_STATUS, DEBUG, "Enter, NAPI POLL cq_id = %d.\n",
1649 if (work_done < budget) {
1650 __netif_rx_complete(qdev->ndev, napi);
1651 ql_enable_completion_interrupt(qdev, rx_ring->irq);
1656 static void ql_vlan_rx_register(struct net_device *ndev, struct vlan_group *grp)
1658 struct ql_adapter *qdev = netdev_priv(ndev);
1662 QPRINTK(qdev, IFUP, DEBUG, "Turning on VLAN in NIC_RCV_CFG.\n");
1663 ql_write32(qdev, NIC_RCV_CFG, NIC_RCV_CFG_VLAN_MASK |
1664 NIC_RCV_CFG_VLAN_MATCH_AND_NON);
1666 QPRINTK(qdev, IFUP, DEBUG,
1667 "Turning off VLAN in NIC_RCV_CFG.\n");
1668 ql_write32(qdev, NIC_RCV_CFG, NIC_RCV_CFG_VLAN_MASK);
1672 static void ql_vlan_rx_add_vid(struct net_device *ndev, u16 vid)
1674 struct ql_adapter *qdev = netdev_priv(ndev);
1675 u32 enable_bit = MAC_ADDR_E;
1677 spin_lock(&qdev->hw_lock);
1678 if (ql_set_mac_addr_reg
1679 (qdev, (u8 *) &enable_bit, MAC_ADDR_TYPE_VLAN, vid)) {
1680 QPRINTK(qdev, IFUP, ERR, "Failed to init vlan address.\n");
1682 spin_unlock(&qdev->hw_lock);
1685 static void ql_vlan_rx_kill_vid(struct net_device *ndev, u16 vid)
1687 struct ql_adapter *qdev = netdev_priv(ndev);
1690 spin_lock(&qdev->hw_lock);
1691 if (ql_set_mac_addr_reg
1692 (qdev, (u8 *) &enable_bit, MAC_ADDR_TYPE_VLAN, vid)) {
1693 QPRINTK(qdev, IFUP, ERR, "Failed to clear vlan address.\n");
1695 spin_unlock(&qdev->hw_lock);
1699 /* Worker thread to process a given rx_ring that is dedicated
1700 * to outbound completions.
1702 static void ql_tx_clean(struct work_struct *work)
1704 struct rx_ring *rx_ring =
1705 container_of(work, struct rx_ring, rx_work.work);
1706 ql_clean_outbound_rx_ring(rx_ring);
1707 ql_enable_completion_interrupt(rx_ring->qdev, rx_ring->irq);
1711 /* Worker thread to process a given rx_ring that is dedicated
1712 * to inbound completions.
1714 static void ql_rx_clean(struct work_struct *work)
1716 struct rx_ring *rx_ring =
1717 container_of(work, struct rx_ring, rx_work.work);
1718 ql_clean_inbound_rx_ring(rx_ring, 64);
1719 ql_enable_completion_interrupt(rx_ring->qdev, rx_ring->irq);
1722 /* MSI-X Multiple Vector Interrupt Handler for outbound completions. */
1723 static irqreturn_t qlge_msix_tx_isr(int irq, void *dev_id)
1725 struct rx_ring *rx_ring = dev_id;
1726 queue_delayed_work_on(rx_ring->cpu, rx_ring->qdev->q_workqueue,
1727 &rx_ring->rx_work, 0);
1731 /* MSI-X Multiple Vector Interrupt Handler for inbound completions. */
1732 static irqreturn_t qlge_msix_rx_isr(int irq, void *dev_id)
1734 struct rx_ring *rx_ring = dev_id;
1735 struct ql_adapter *qdev = rx_ring->qdev;
1736 netif_rx_schedule(qdev->ndev, &rx_ring->napi);
1740 /* This handles a fatal error, MPI activity, and the default
1741 * rx_ring in an MSI-X multiple vector environment.
1742 * In MSI/Legacy environment it also process the rest of
1745 static irqreturn_t qlge_isr(int irq, void *dev_id)
1747 struct rx_ring *rx_ring = dev_id;
1748 struct ql_adapter *qdev = rx_ring->qdev;
1749 struct intr_context *intr_context = &qdev->intr_context[0];
1754 spin_lock(&qdev->hw_lock);
1755 if (atomic_read(&qdev->intr_context[0].irq_cnt)) {
1756 QPRINTK(qdev, INTR, DEBUG, "Shared Interrupt, Not ours!\n");
1757 spin_unlock(&qdev->hw_lock);
1760 spin_unlock(&qdev->hw_lock);
1762 var = ql_disable_completion_interrupt(qdev, intr_context->intr);
1765 * Check for fatal error.
1768 ql_queue_asic_error(qdev);
1769 QPRINTK(qdev, INTR, ERR, "Got fatal error, STS = %x.\n", var);
1770 var = ql_read32(qdev, ERR_STS);
1771 QPRINTK(qdev, INTR, ERR,
1772 "Resetting chip. Error Status Register = 0x%x\n", var);
1777 * Check MPI processor activity.
1781 * We've got an async event or mailbox completion.
1782 * Handle it and clear the source of the interrupt.
1784 QPRINTK(qdev, INTR, ERR, "Got MPI processor interrupt.\n");
1785 ql_disable_completion_interrupt(qdev, intr_context->intr);
1786 queue_delayed_work_on(smp_processor_id(), qdev->workqueue,
1787 &qdev->mpi_work, 0);
1792 * Check the default queue and wake handler if active.
1794 rx_ring = &qdev->rx_ring[0];
1795 if (ql_read_sh_reg(rx_ring->prod_idx_sh_reg) != rx_ring->cnsmr_idx) {
1796 QPRINTK(qdev, INTR, INFO, "Waking handler for rx_ring[0].\n");
1797 ql_disable_completion_interrupt(qdev, intr_context->intr);
1798 queue_delayed_work_on(smp_processor_id(), qdev->q_workqueue,
1799 &rx_ring->rx_work, 0);
1803 if (!test_bit(QL_MSIX_ENABLED, &qdev->flags)) {
1805 * Start the DPC for each active queue.
1807 for (i = 1; i < qdev->rx_ring_count; i++) {
1808 rx_ring = &qdev->rx_ring[i];
1809 if (ql_read_sh_reg(rx_ring->prod_idx_sh_reg) !=
1810 rx_ring->cnsmr_idx) {
1811 QPRINTK(qdev, INTR, INFO,
1812 "Waking handler for rx_ring[%d].\n", i);
1813 ql_disable_completion_interrupt(qdev,
1816 if (i < qdev->rss_ring_first_cq_id)
1817 queue_delayed_work_on(rx_ring->cpu,
1822 netif_rx_schedule(qdev->ndev,
1828 ql_enable_completion_interrupt(qdev, intr_context->intr);
1829 return work_done ? IRQ_HANDLED : IRQ_NONE;
1832 static int ql_tso(struct sk_buff *skb, struct ob_mac_tso_iocb_req *mac_iocb_ptr)
1835 if (skb_is_gso(skb)) {
1837 if (skb_header_cloned(skb)) {
1838 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
1843 mac_iocb_ptr->opcode = OPCODE_OB_MAC_TSO_IOCB;
1844 mac_iocb_ptr->flags3 |= OB_MAC_TSO_IOCB_IC;
1845 mac_iocb_ptr->frame_len = cpu_to_le32((u32) skb->len);
1846 mac_iocb_ptr->total_hdrs_len =
1847 cpu_to_le16(skb_transport_offset(skb) + tcp_hdrlen(skb));
1848 mac_iocb_ptr->net_trans_offset =
1849 cpu_to_le16(skb_network_offset(skb) |
1850 skb_transport_offset(skb)
1851 << OB_MAC_TRANSPORT_HDR_SHIFT);
1852 mac_iocb_ptr->mss = cpu_to_le16(skb_shinfo(skb)->gso_size);
1853 mac_iocb_ptr->flags2 |= OB_MAC_TSO_IOCB_LSO;
1854 if (likely(skb->protocol == htons(ETH_P_IP))) {
1855 struct iphdr *iph = ip_hdr(skb);
1857 mac_iocb_ptr->flags1 |= OB_MAC_TSO_IOCB_IP4;
1858 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
1862 } else if (skb->protocol == htons(ETH_P_IPV6)) {
1863 mac_iocb_ptr->flags1 |= OB_MAC_TSO_IOCB_IP6;
1864 tcp_hdr(skb)->check =
1865 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
1866 &ipv6_hdr(skb)->daddr,
1874 static void ql_hw_csum_setup(struct sk_buff *skb,
1875 struct ob_mac_tso_iocb_req *mac_iocb_ptr)
1878 struct iphdr *iph = ip_hdr(skb);
1880 mac_iocb_ptr->opcode = OPCODE_OB_MAC_TSO_IOCB;
1881 mac_iocb_ptr->frame_len = cpu_to_le32((u32) skb->len);
1882 mac_iocb_ptr->net_trans_offset =
1883 cpu_to_le16(skb_network_offset(skb) |
1884 skb_transport_offset(skb) << OB_MAC_TRANSPORT_HDR_SHIFT);
1886 mac_iocb_ptr->flags1 |= OB_MAC_TSO_IOCB_IP4;
1887 len = (ntohs(iph->tot_len) - (iph->ihl << 2));
1888 if (likely(iph->protocol == IPPROTO_TCP)) {
1889 check = &(tcp_hdr(skb)->check);
1890 mac_iocb_ptr->flags2 |= OB_MAC_TSO_IOCB_TC;
1891 mac_iocb_ptr->total_hdrs_len =
1892 cpu_to_le16(skb_transport_offset(skb) +
1893 (tcp_hdr(skb)->doff << 2));
1895 check = &(udp_hdr(skb)->check);
1896 mac_iocb_ptr->flags2 |= OB_MAC_TSO_IOCB_UC;
1897 mac_iocb_ptr->total_hdrs_len =
1898 cpu_to_le16(skb_transport_offset(skb) +
1899 sizeof(struct udphdr));
1901 *check = ~csum_tcpudp_magic(iph->saddr,
1902 iph->daddr, len, iph->protocol, 0);
1905 static int qlge_send(struct sk_buff *skb, struct net_device *ndev)
1907 struct tx_ring_desc *tx_ring_desc;
1908 struct ob_mac_iocb_req *mac_iocb_ptr;
1909 struct ql_adapter *qdev = netdev_priv(ndev);
1911 struct tx_ring *tx_ring;
1912 u32 tx_ring_idx = (u32) QL_TXQ_IDX(qdev, skb);
1914 tx_ring = &qdev->tx_ring[tx_ring_idx];
1916 if (unlikely(atomic_read(&tx_ring->tx_count) < 2)) {
1917 QPRINTK(qdev, TX_QUEUED, INFO,
1918 "%s: shutting down tx queue %d du to lack of resources.\n",
1919 __func__, tx_ring_idx);
1920 netif_stop_queue(ndev);
1921 atomic_inc(&tx_ring->queue_stopped);
1922 return NETDEV_TX_BUSY;
1924 tx_ring_desc = &tx_ring->q[tx_ring->prod_idx];
1925 mac_iocb_ptr = tx_ring_desc->queue_entry;
1926 memset((void *)mac_iocb_ptr, 0, sizeof(mac_iocb_ptr));
1927 if (ql_map_send(qdev, mac_iocb_ptr, skb, tx_ring_desc) != NETDEV_TX_OK) {
1928 QPRINTK(qdev, TX_QUEUED, ERR, "Could not map the segments.\n");
1929 return NETDEV_TX_BUSY;
1932 mac_iocb_ptr->opcode = OPCODE_OB_MAC_IOCB;
1933 mac_iocb_ptr->tid = tx_ring_desc->index;
1934 /* We use the upper 32-bits to store the tx queue for this IO.
1935 * When we get the completion we can use it to establish the context.
1937 mac_iocb_ptr->txq_idx = tx_ring_idx;
1938 tx_ring_desc->skb = skb;
1940 mac_iocb_ptr->frame_len = cpu_to_le16((u16) skb->len);
1942 if (qdev->vlgrp && vlan_tx_tag_present(skb)) {
1943 QPRINTK(qdev, TX_QUEUED, DEBUG, "Adding a vlan tag %d.\n",
1944 vlan_tx_tag_get(skb));
1945 mac_iocb_ptr->flags3 |= OB_MAC_IOCB_V;
1946 mac_iocb_ptr->vlan_tci = cpu_to_le16(vlan_tx_tag_get(skb));
1948 tso = ql_tso(skb, (struct ob_mac_tso_iocb_req *)mac_iocb_ptr);
1950 dev_kfree_skb_any(skb);
1951 return NETDEV_TX_OK;
1952 } else if (unlikely(!tso) && (skb->ip_summed == CHECKSUM_PARTIAL)) {
1953 ql_hw_csum_setup(skb,
1954 (struct ob_mac_tso_iocb_req *)mac_iocb_ptr);
1956 QL_DUMP_OB_MAC_IOCB(mac_iocb_ptr);
1957 tx_ring->prod_idx++;
1958 if (tx_ring->prod_idx == tx_ring->wq_len)
1959 tx_ring->prod_idx = 0;
1962 ql_write_db_reg(tx_ring->prod_idx, tx_ring->prod_idx_db_reg);
1963 ndev->trans_start = jiffies;
1964 QPRINTK(qdev, TX_QUEUED, DEBUG, "tx queued, slot %d, len %d\n",
1965 tx_ring->prod_idx, skb->len);
1967 atomic_dec(&tx_ring->tx_count);
1968 return NETDEV_TX_OK;
1971 static void ql_free_shadow_space(struct ql_adapter *qdev)
1973 if (qdev->rx_ring_shadow_reg_area) {
1974 pci_free_consistent(qdev->pdev,
1976 qdev->rx_ring_shadow_reg_area,
1977 qdev->rx_ring_shadow_reg_dma);
1978 qdev->rx_ring_shadow_reg_area = NULL;
1980 if (qdev->tx_ring_shadow_reg_area) {
1981 pci_free_consistent(qdev->pdev,
1983 qdev->tx_ring_shadow_reg_area,
1984 qdev->tx_ring_shadow_reg_dma);
1985 qdev->tx_ring_shadow_reg_area = NULL;
1989 static int ql_alloc_shadow_space(struct ql_adapter *qdev)
1991 qdev->rx_ring_shadow_reg_area =
1992 pci_alloc_consistent(qdev->pdev,
1993 PAGE_SIZE, &qdev->rx_ring_shadow_reg_dma);
1994 if (qdev->rx_ring_shadow_reg_area == NULL) {
1995 QPRINTK(qdev, IFUP, ERR,
1996 "Allocation of RX shadow space failed.\n");
1999 qdev->tx_ring_shadow_reg_area =
2000 pci_alloc_consistent(qdev->pdev, PAGE_SIZE,
2001 &qdev->tx_ring_shadow_reg_dma);
2002 if (qdev->tx_ring_shadow_reg_area == NULL) {
2003 QPRINTK(qdev, IFUP, ERR,
2004 "Allocation of TX shadow space failed.\n");
2005 goto err_wqp_sh_area;
2010 pci_free_consistent(qdev->pdev,
2012 qdev->rx_ring_shadow_reg_area,
2013 qdev->rx_ring_shadow_reg_dma);
2017 static void ql_init_tx_ring(struct ql_adapter *qdev, struct tx_ring *tx_ring)
2019 struct tx_ring_desc *tx_ring_desc;
2021 struct ob_mac_iocb_req *mac_iocb_ptr;
2023 mac_iocb_ptr = tx_ring->wq_base;
2024 tx_ring_desc = tx_ring->q;
2025 for (i = 0; i < tx_ring->wq_len; i++) {
2026 tx_ring_desc->index = i;
2027 tx_ring_desc->skb = NULL;
2028 tx_ring_desc->queue_entry = mac_iocb_ptr;
2032 atomic_set(&tx_ring->tx_count, tx_ring->wq_len);
2033 atomic_set(&tx_ring->queue_stopped, 0);
2036 static void ql_free_tx_resources(struct ql_adapter *qdev,
2037 struct tx_ring *tx_ring)
2039 if (tx_ring->wq_base) {
2040 pci_free_consistent(qdev->pdev, tx_ring->wq_size,
2041 tx_ring->wq_base, tx_ring->wq_base_dma);
2042 tx_ring->wq_base = NULL;
2048 static int ql_alloc_tx_resources(struct ql_adapter *qdev,
2049 struct tx_ring *tx_ring)
2052 pci_alloc_consistent(qdev->pdev, tx_ring->wq_size,
2053 &tx_ring->wq_base_dma);
2055 if ((tx_ring->wq_base == NULL)
2056 || tx_ring->wq_base_dma & (tx_ring->wq_size - 1)) {
2057 QPRINTK(qdev, IFUP, ERR, "tx_ring alloc failed.\n");
2061 kmalloc(tx_ring->wq_len * sizeof(struct tx_ring_desc), GFP_KERNEL);
2062 if (tx_ring->q == NULL)
2067 pci_free_consistent(qdev->pdev, tx_ring->wq_size,
2068 tx_ring->wq_base, tx_ring->wq_base_dma);
2072 static void ql_free_lbq_buffers(struct ql_adapter *qdev, struct rx_ring *rx_ring)
2075 struct bq_desc *lbq_desc;
2077 for (i = 0; i < rx_ring->lbq_len; i++) {
2078 lbq_desc = &rx_ring->lbq[i];
2079 if (lbq_desc->p.lbq_page) {
2080 pci_unmap_page(qdev->pdev,
2081 pci_unmap_addr(lbq_desc, mapaddr),
2082 pci_unmap_len(lbq_desc, maplen),
2083 PCI_DMA_FROMDEVICE);
2085 put_page(lbq_desc->p.lbq_page);
2086 lbq_desc->p.lbq_page = NULL;
2088 lbq_desc->bq->addr_lo = 0;
2089 lbq_desc->bq->addr_hi = 0;
2094 * Allocate and map a page for each element of the lbq.
2096 static int ql_alloc_lbq_buffers(struct ql_adapter *qdev,
2097 struct rx_ring *rx_ring)
2100 struct bq_desc *lbq_desc;
2102 struct bq_element *bq = rx_ring->lbq_base;
2104 for (i = 0; i < rx_ring->lbq_len; i++) {
2105 lbq_desc = &rx_ring->lbq[i];
2106 memset(lbq_desc, 0, sizeof(lbq_desc));
2108 lbq_desc->index = i;
2109 lbq_desc->p.lbq_page = alloc_page(GFP_ATOMIC);
2110 if (unlikely(!lbq_desc->p.lbq_page)) {
2111 QPRINTK(qdev, IFUP, ERR, "failed alloc_page().\n");
2114 map = pci_map_page(qdev->pdev,
2115 lbq_desc->p.lbq_page,
2116 0, PAGE_SIZE, PCI_DMA_FROMDEVICE);
2117 if (pci_dma_mapping_error(qdev->pdev, map)) {
2118 QPRINTK(qdev, IFUP, ERR,
2119 "PCI mapping failed.\n");
2122 pci_unmap_addr_set(lbq_desc, mapaddr, map);
2123 pci_unmap_len_set(lbq_desc, maplen, PAGE_SIZE);
2124 bq->addr_lo = cpu_to_le32(map);
2125 bq->addr_hi = cpu_to_le32(map >> 32);
2131 ql_free_lbq_buffers(qdev, rx_ring);
2135 static void ql_free_sbq_buffers(struct ql_adapter *qdev, struct rx_ring *rx_ring)
2138 struct bq_desc *sbq_desc;
2140 for (i = 0; i < rx_ring->sbq_len; i++) {
2141 sbq_desc = &rx_ring->sbq[i];
2142 if (sbq_desc == NULL) {
2143 QPRINTK(qdev, IFUP, ERR, "sbq_desc %d is NULL.\n", i);
2146 if (sbq_desc->p.skb) {
2147 pci_unmap_single(qdev->pdev,
2148 pci_unmap_addr(sbq_desc, mapaddr),
2149 pci_unmap_len(sbq_desc, maplen),
2150 PCI_DMA_FROMDEVICE);
2151 dev_kfree_skb(sbq_desc->p.skb);
2152 sbq_desc->p.skb = NULL;
2154 if (sbq_desc->bq == NULL) {
2155 QPRINTK(qdev, IFUP, ERR, "sbq_desc->bq %d is NULL.\n",
2159 sbq_desc->bq->addr_lo = 0;
2160 sbq_desc->bq->addr_hi = 0;
2164 /* Allocate and map an skb for each element of the sbq. */
2165 static int ql_alloc_sbq_buffers(struct ql_adapter *qdev,
2166 struct rx_ring *rx_ring)
2169 struct bq_desc *sbq_desc;
2170 struct sk_buff *skb;
2172 struct bq_element *bq = rx_ring->sbq_base;
2174 for (i = 0; i < rx_ring->sbq_len; i++) {
2175 sbq_desc = &rx_ring->sbq[i];
2176 memset(sbq_desc, 0, sizeof(sbq_desc));
2177 sbq_desc->index = i;
2179 skb = netdev_alloc_skb(qdev->ndev, rx_ring->sbq_buf_size);
2180 if (unlikely(!skb)) {
2181 /* Better luck next round */
2182 QPRINTK(qdev, IFUP, ERR,
2183 "small buff alloc failed for %d bytes at index %d.\n",
2184 rx_ring->sbq_buf_size, i);
2187 skb_reserve(skb, QLGE_SB_PAD);
2188 sbq_desc->p.skb = skb;
2190 * Map only half the buffer. Because the
2191 * other half may get some data copied to it
2192 * when the completion arrives.
2194 map = pci_map_single(qdev->pdev,
2196 rx_ring->sbq_buf_size / 2,
2197 PCI_DMA_FROMDEVICE);
2198 if (pci_dma_mapping_error(qdev->pdev, map)) {
2199 QPRINTK(qdev, IFUP, ERR, "PCI mapping failed.\n");
2202 pci_unmap_addr_set(sbq_desc, mapaddr, map);
2203 pci_unmap_len_set(sbq_desc, maplen, rx_ring->sbq_buf_size / 2);
2204 bq->addr_lo = /*sbq_desc->addr_lo = */
2206 bq->addr_hi = /*sbq_desc->addr_hi = */
2207 cpu_to_le32(map >> 32);
2212 ql_free_sbq_buffers(qdev, rx_ring);
2216 static void ql_free_rx_resources(struct ql_adapter *qdev,
2217 struct rx_ring *rx_ring)
2219 if (rx_ring->sbq_len)
2220 ql_free_sbq_buffers(qdev, rx_ring);
2221 if (rx_ring->lbq_len)
2222 ql_free_lbq_buffers(qdev, rx_ring);
2224 /* Free the small buffer queue. */
2225 if (rx_ring->sbq_base) {
2226 pci_free_consistent(qdev->pdev,
2228 rx_ring->sbq_base, rx_ring->sbq_base_dma);
2229 rx_ring->sbq_base = NULL;
2232 /* Free the small buffer queue control blocks. */
2233 kfree(rx_ring->sbq);
2234 rx_ring->sbq = NULL;
2236 /* Free the large buffer queue. */
2237 if (rx_ring->lbq_base) {
2238 pci_free_consistent(qdev->pdev,
2240 rx_ring->lbq_base, rx_ring->lbq_base_dma);
2241 rx_ring->lbq_base = NULL;
2244 /* Free the large buffer queue control blocks. */
2245 kfree(rx_ring->lbq);
2246 rx_ring->lbq = NULL;
2248 /* Free the rx queue. */
2249 if (rx_ring->cq_base) {
2250 pci_free_consistent(qdev->pdev,
2252 rx_ring->cq_base, rx_ring->cq_base_dma);
2253 rx_ring->cq_base = NULL;
2257 /* Allocate queues and buffers for this completions queue based
2258 * on the values in the parameter structure. */
2259 static int ql_alloc_rx_resources(struct ql_adapter *qdev,
2260 struct rx_ring *rx_ring)
2264 * Allocate the completion queue for this rx_ring.
2267 pci_alloc_consistent(qdev->pdev, rx_ring->cq_size,
2268 &rx_ring->cq_base_dma);
2270 if (rx_ring->cq_base == NULL) {
2271 QPRINTK(qdev, IFUP, ERR, "rx_ring alloc failed.\n");
2275 if (rx_ring->sbq_len) {
2277 * Allocate small buffer queue.
2280 pci_alloc_consistent(qdev->pdev, rx_ring->sbq_size,
2281 &rx_ring->sbq_base_dma);
2283 if (rx_ring->sbq_base == NULL) {
2284 QPRINTK(qdev, IFUP, ERR,
2285 "Small buffer queue allocation failed.\n");
2290 * Allocate small buffer queue control blocks.
2293 kmalloc(rx_ring->sbq_len * sizeof(struct bq_desc),
2295 if (rx_ring->sbq == NULL) {
2296 QPRINTK(qdev, IFUP, ERR,
2297 "Small buffer queue control block allocation failed.\n");
2301 if (ql_alloc_sbq_buffers(qdev, rx_ring)) {
2302 QPRINTK(qdev, IFUP, ERR,
2303 "Small buffer allocation failed.\n");
2308 if (rx_ring->lbq_len) {
2310 * Allocate large buffer queue.
2313 pci_alloc_consistent(qdev->pdev, rx_ring->lbq_size,
2314 &rx_ring->lbq_base_dma);
2316 if (rx_ring->lbq_base == NULL) {
2317 QPRINTK(qdev, IFUP, ERR,
2318 "Large buffer queue allocation failed.\n");
2322 * Allocate large buffer queue control blocks.
2325 kmalloc(rx_ring->lbq_len * sizeof(struct bq_desc),
2327 if (rx_ring->lbq == NULL) {
2328 QPRINTK(qdev, IFUP, ERR,
2329 "Large buffer queue control block allocation failed.\n");
2334 * Allocate the buffers.
2336 if (ql_alloc_lbq_buffers(qdev, rx_ring)) {
2337 QPRINTK(qdev, IFUP, ERR,
2338 "Large buffer allocation failed.\n");
2346 ql_free_rx_resources(qdev, rx_ring);
2350 static void ql_tx_ring_clean(struct ql_adapter *qdev)
2352 struct tx_ring *tx_ring;
2353 struct tx_ring_desc *tx_ring_desc;
2357 * Loop through all queues and free
2360 for (j = 0; j < qdev->tx_ring_count; j++) {
2361 tx_ring = &qdev->tx_ring[j];
2362 for (i = 0; i < tx_ring->wq_len; i++) {
2363 tx_ring_desc = &tx_ring->q[i];
2364 if (tx_ring_desc && tx_ring_desc->skb) {
2365 QPRINTK(qdev, IFDOWN, ERR,
2366 "Freeing lost SKB %p, from queue %d, index %d.\n",
2367 tx_ring_desc->skb, j,
2368 tx_ring_desc->index);
2369 ql_unmap_send(qdev, tx_ring_desc,
2370 tx_ring_desc->map_cnt);
2371 dev_kfree_skb(tx_ring_desc->skb);
2372 tx_ring_desc->skb = NULL;
2378 static void ql_free_ring_cb(struct ql_adapter *qdev)
2380 kfree(qdev->ring_mem);
2383 static int ql_alloc_ring_cb(struct ql_adapter *qdev)
2385 /* Allocate space for tx/rx ring control blocks. */
2386 qdev->ring_mem_size =
2387 (qdev->tx_ring_count * sizeof(struct tx_ring)) +
2388 (qdev->rx_ring_count * sizeof(struct rx_ring));
2389 qdev->ring_mem = kmalloc(qdev->ring_mem_size, GFP_KERNEL);
2390 if (qdev->ring_mem == NULL) {
2393 qdev->rx_ring = qdev->ring_mem;
2394 qdev->tx_ring = qdev->ring_mem +
2395 (qdev->rx_ring_count * sizeof(struct rx_ring));
2400 static void ql_free_mem_resources(struct ql_adapter *qdev)
2404 for (i = 0; i < qdev->tx_ring_count; i++)
2405 ql_free_tx_resources(qdev, &qdev->tx_ring[i]);
2406 for (i = 0; i < qdev->rx_ring_count; i++)
2407 ql_free_rx_resources(qdev, &qdev->rx_ring[i]);
2408 ql_free_shadow_space(qdev);
2411 static int ql_alloc_mem_resources(struct ql_adapter *qdev)
2415 /* Allocate space for our shadow registers and such. */
2416 if (ql_alloc_shadow_space(qdev))
2419 for (i = 0; i < qdev->rx_ring_count; i++) {
2420 if (ql_alloc_rx_resources(qdev, &qdev->rx_ring[i]) != 0) {
2421 QPRINTK(qdev, IFUP, ERR,
2422 "RX resource allocation failed.\n");
2426 /* Allocate tx queue resources */
2427 for (i = 0; i < qdev->tx_ring_count; i++) {
2428 if (ql_alloc_tx_resources(qdev, &qdev->tx_ring[i]) != 0) {
2429 QPRINTK(qdev, IFUP, ERR,
2430 "TX resource allocation failed.\n");
2437 ql_free_mem_resources(qdev);
2441 /* Set up the rx ring control block and pass it to the chip.
2442 * The control block is defined as
2443 * "Completion Queue Initialization Control Block", or cqicb.
2445 static int ql_start_rx_ring(struct ql_adapter *qdev, struct rx_ring *rx_ring)
2447 struct cqicb *cqicb = &rx_ring->cqicb;
2448 void *shadow_reg = qdev->rx_ring_shadow_reg_area +
2449 (rx_ring->cq_id * sizeof(u64) * 4);
2450 u64 shadow_reg_dma = qdev->rx_ring_shadow_reg_dma +
2451 (rx_ring->cq_id * sizeof(u64) * 4);
2452 void __iomem *doorbell_area =
2453 qdev->doorbell_area + (DB_PAGE_SIZE * (128 + rx_ring->cq_id));
2457 /* Set up the shadow registers for this ring. */
2458 rx_ring->prod_idx_sh_reg = shadow_reg;
2459 rx_ring->prod_idx_sh_reg_dma = shadow_reg_dma;
2460 shadow_reg += sizeof(u64);
2461 shadow_reg_dma += sizeof(u64);
2462 rx_ring->lbq_base_indirect = shadow_reg;
2463 rx_ring->lbq_base_indirect_dma = shadow_reg_dma;
2464 shadow_reg += sizeof(u64);
2465 shadow_reg_dma += sizeof(u64);
2466 rx_ring->sbq_base_indirect = shadow_reg;
2467 rx_ring->sbq_base_indirect_dma = shadow_reg_dma;
2469 /* PCI doorbell mem area + 0x00 for consumer index register */
2470 rx_ring->cnsmr_idx_db_reg = (u32 __iomem *) doorbell_area;
2471 rx_ring->cnsmr_idx = 0;
2472 rx_ring->curr_entry = rx_ring->cq_base;
2474 /* PCI doorbell mem area + 0x04 for valid register */
2475 rx_ring->valid_db_reg = doorbell_area + 0x04;
2477 /* PCI doorbell mem area + 0x18 for large buffer consumer */
2478 rx_ring->lbq_prod_idx_db_reg = (u32 __iomem *) (doorbell_area + 0x18);
2480 /* PCI doorbell mem area + 0x1c */
2481 rx_ring->sbq_prod_idx_db_reg = (u32 __iomem *) (doorbell_area + 0x1c);
2483 memset((void *)cqicb, 0, sizeof(struct cqicb));
2484 cqicb->msix_vect = rx_ring->irq;
2486 cqicb->len = cpu_to_le16(rx_ring->cq_len | LEN_V | LEN_CPP_CONT);
2488 cqicb->addr_lo = cpu_to_le32(rx_ring->cq_base_dma);
2489 cqicb->addr_hi = cpu_to_le32((u64) rx_ring->cq_base_dma >> 32);
2491 cqicb->prod_idx_addr_lo = cpu_to_le32(rx_ring->prod_idx_sh_reg_dma);
2492 cqicb->prod_idx_addr_hi =
2493 cpu_to_le32((u64) rx_ring->prod_idx_sh_reg_dma >> 32);
2496 * Set up the control block load flags.
2498 cqicb->flags = FLAGS_LC | /* Load queue base address */
2499 FLAGS_LV | /* Load MSI-X vector */
2500 FLAGS_LI; /* Load irq delay values */
2501 if (rx_ring->lbq_len) {
2502 cqicb->flags |= FLAGS_LL; /* Load lbq values */
2503 *((u64 *) rx_ring->lbq_base_indirect) = rx_ring->lbq_base_dma;
2504 cqicb->lbq_addr_lo =
2505 cpu_to_le32(rx_ring->lbq_base_indirect_dma);
2506 cqicb->lbq_addr_hi =
2507 cpu_to_le32((u64) rx_ring->lbq_base_indirect_dma >> 32);
2508 cqicb->lbq_buf_size = cpu_to_le32(rx_ring->lbq_buf_size);
2509 bq_len = (u16) rx_ring->lbq_len;
2510 cqicb->lbq_len = cpu_to_le16(bq_len);
2511 rx_ring->lbq_prod_idx = rx_ring->lbq_len - 16;
2512 rx_ring->lbq_curr_idx = 0;
2513 rx_ring->lbq_clean_idx = rx_ring->lbq_prod_idx;
2514 rx_ring->lbq_free_cnt = 16;
2516 if (rx_ring->sbq_len) {
2517 cqicb->flags |= FLAGS_LS; /* Load sbq values */
2518 *((u64 *) rx_ring->sbq_base_indirect) = rx_ring->sbq_base_dma;
2519 cqicb->sbq_addr_lo =
2520 cpu_to_le32(rx_ring->sbq_base_indirect_dma);
2521 cqicb->sbq_addr_hi =
2522 cpu_to_le32((u64) rx_ring->sbq_base_indirect_dma >> 32);
2523 cqicb->sbq_buf_size =
2524 cpu_to_le16(((rx_ring->sbq_buf_size / 2) + 8) & 0xfffffff8);
2525 bq_len = (u16) rx_ring->sbq_len;
2526 cqicb->sbq_len = cpu_to_le16(bq_len);
2527 rx_ring->sbq_prod_idx = rx_ring->sbq_len - 16;
2528 rx_ring->sbq_curr_idx = 0;
2529 rx_ring->sbq_clean_idx = rx_ring->sbq_prod_idx;
2530 rx_ring->sbq_free_cnt = 16;
2532 switch (rx_ring->type) {
2534 /* If there's only one interrupt, then we use
2535 * worker threads to process the outbound
2536 * completion handling rx_rings. We do this so
2537 * they can be run on multiple CPUs. There is
2538 * room to play with this more where we would only
2539 * run in a worker if there are more than x number
2540 * of outbound completions on the queue and more
2541 * than one queue active. Some threshold that
2542 * would indicate a benefit in spite of the cost
2543 * of a context switch.
2544 * If there's more than one interrupt, then the
2545 * outbound completions are processed in the ISR.
2547 if (!test_bit(QL_MSIX_ENABLED, &qdev->flags))
2548 INIT_DELAYED_WORK(&rx_ring->rx_work, ql_tx_clean);
2550 /* With all debug warnings on we see a WARN_ON message
2551 * when we free the skb in the interrupt context.
2553 INIT_DELAYED_WORK(&rx_ring->rx_work, ql_tx_clean);
2555 cqicb->irq_delay = cpu_to_le16(qdev->tx_coalesce_usecs);
2556 cqicb->pkt_delay = cpu_to_le16(qdev->tx_max_coalesced_frames);
2559 INIT_DELAYED_WORK(&rx_ring->rx_work, ql_rx_clean);
2560 cqicb->irq_delay = 0;
2561 cqicb->pkt_delay = 0;
2564 /* Inbound completion handling rx_rings run in
2565 * separate NAPI contexts.
2567 netif_napi_add(qdev->ndev, &rx_ring->napi, ql_napi_poll_msix,
2569 cqicb->irq_delay = cpu_to_le16(qdev->rx_coalesce_usecs);
2570 cqicb->pkt_delay = cpu_to_le16(qdev->rx_max_coalesced_frames);
2573 QPRINTK(qdev, IFUP, DEBUG, "Invalid rx_ring->type = %d.\n",
2576 QPRINTK(qdev, IFUP, INFO, "Initializing rx work queue.\n");
2577 err = ql_write_cfg(qdev, cqicb, sizeof(struct cqicb),
2578 CFG_LCQ, rx_ring->cq_id);
2580 QPRINTK(qdev, IFUP, ERR, "Failed to load CQICB.\n");
2583 QPRINTK(qdev, IFUP, INFO, "Successfully loaded CQICB.\n");
2585 * Advance the producer index for the buffer queues.
2588 if (rx_ring->lbq_len)
2589 ql_write_db_reg(rx_ring->lbq_prod_idx,
2590 rx_ring->lbq_prod_idx_db_reg);
2591 if (rx_ring->sbq_len)
2592 ql_write_db_reg(rx_ring->sbq_prod_idx,
2593 rx_ring->sbq_prod_idx_db_reg);
2597 static int ql_start_tx_ring(struct ql_adapter *qdev, struct tx_ring *tx_ring)
2599 struct wqicb *wqicb = (struct wqicb *)tx_ring;
2600 void __iomem *doorbell_area =
2601 qdev->doorbell_area + (DB_PAGE_SIZE * tx_ring->wq_id);
2602 void *shadow_reg = qdev->tx_ring_shadow_reg_area +
2603 (tx_ring->wq_id * sizeof(u64));
2604 u64 shadow_reg_dma = qdev->tx_ring_shadow_reg_dma +
2605 (tx_ring->wq_id * sizeof(u64));
2609 * Assign doorbell registers for this tx_ring.
2611 /* TX PCI doorbell mem area for tx producer index */
2612 tx_ring->prod_idx_db_reg = (u32 __iomem *) doorbell_area;
2613 tx_ring->prod_idx = 0;
2614 /* TX PCI doorbell mem area + 0x04 */
2615 tx_ring->valid_db_reg = doorbell_area + 0x04;
2618 * Assign shadow registers for this tx_ring.
2620 tx_ring->cnsmr_idx_sh_reg = shadow_reg;
2621 tx_ring->cnsmr_idx_sh_reg_dma = shadow_reg_dma;
2623 wqicb->len = cpu_to_le16(tx_ring->wq_len | Q_LEN_V | Q_LEN_CPP_CONT);
2624 wqicb->flags = cpu_to_le16(Q_FLAGS_LC |
2625 Q_FLAGS_LB | Q_FLAGS_LI | Q_FLAGS_LO);
2626 wqicb->cq_id_rss = cpu_to_le16(tx_ring->cq_id);
2628 wqicb->addr_lo = cpu_to_le32(tx_ring->wq_base_dma);
2629 wqicb->addr_hi = cpu_to_le32((u64) tx_ring->wq_base_dma >> 32);
2631 wqicb->cnsmr_idx_addr_lo = cpu_to_le32(tx_ring->cnsmr_idx_sh_reg_dma);
2632 wqicb->cnsmr_idx_addr_hi =
2633 cpu_to_le32((u64) tx_ring->cnsmr_idx_sh_reg_dma >> 32);
2635 ql_init_tx_ring(qdev, tx_ring);
2637 err = ql_write_cfg(qdev, wqicb, sizeof(wqicb), CFG_LRQ,
2638 (u16) tx_ring->wq_id);
2640 QPRINTK(qdev, IFUP, ERR, "Failed to load tx_ring.\n");
2643 QPRINTK(qdev, IFUP, INFO, "Successfully loaded WQICB.\n");
2647 static void ql_disable_msix(struct ql_adapter *qdev)
2649 if (test_bit(QL_MSIX_ENABLED, &qdev->flags)) {
2650 pci_disable_msix(qdev->pdev);
2651 clear_bit(QL_MSIX_ENABLED, &qdev->flags);
2652 kfree(qdev->msi_x_entry);
2653 qdev->msi_x_entry = NULL;
2654 } else if (test_bit(QL_MSI_ENABLED, &qdev->flags)) {
2655 pci_disable_msi(qdev->pdev);
2656 clear_bit(QL_MSI_ENABLED, &qdev->flags);
2660 static void ql_enable_msix(struct ql_adapter *qdev)
2664 qdev->intr_count = 1;
2665 /* Get the MSIX vectors. */
2666 if (irq_type == MSIX_IRQ) {
2667 /* Try to alloc space for the msix struct,
2668 * if it fails then go to MSI/legacy.
2670 qdev->msi_x_entry = kcalloc(qdev->rx_ring_count,
2671 sizeof(struct msix_entry),
2673 if (!qdev->msi_x_entry) {
2678 for (i = 0; i < qdev->rx_ring_count; i++)
2679 qdev->msi_x_entry[i].entry = i;
2681 if (!pci_enable_msix
2682 (qdev->pdev, qdev->msi_x_entry, qdev->rx_ring_count)) {
2683 set_bit(QL_MSIX_ENABLED, &qdev->flags);
2684 qdev->intr_count = qdev->rx_ring_count;
2685 QPRINTK(qdev, IFUP, INFO,
2686 "MSI-X Enabled, got %d vectors.\n",
2690 kfree(qdev->msi_x_entry);
2691 qdev->msi_x_entry = NULL;
2692 QPRINTK(qdev, IFUP, WARNING,
2693 "MSI-X Enable failed, trying MSI.\n");
2698 if (irq_type == MSI_IRQ) {
2699 if (!pci_enable_msi(qdev->pdev)) {
2700 set_bit(QL_MSI_ENABLED, &qdev->flags);
2701 QPRINTK(qdev, IFUP, INFO,
2702 "Running with MSI interrupts.\n");
2707 QPRINTK(qdev, IFUP, DEBUG, "Running with legacy interrupts.\n");
2711 * Here we build the intr_context structures based on
2712 * our rx_ring count and intr vector count.
2713 * The intr_context structure is used to hook each vector
2714 * to possibly different handlers.
2716 static void ql_resolve_queues_to_irqs(struct ql_adapter *qdev)
2719 struct intr_context *intr_context = &qdev->intr_context[0];
2721 ql_enable_msix(qdev);
2723 if (likely(test_bit(QL_MSIX_ENABLED, &qdev->flags))) {
2724 /* Each rx_ring has it's
2725 * own intr_context since we have separate
2726 * vectors for each queue.
2727 * This only true when MSI-X is enabled.
2729 for (i = 0; i < qdev->intr_count; i++, intr_context++) {
2730 qdev->rx_ring[i].irq = i;
2731 intr_context->intr = i;
2732 intr_context->qdev = qdev;
2734 * We set up each vectors enable/disable/read bits so
2735 * there's no bit/mask calculations in the critical path.
2737 intr_context->intr_en_mask =
2738 INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK |
2739 INTR_EN_TYPE_ENABLE | INTR_EN_IHD_MASK | INTR_EN_IHD
2741 intr_context->intr_dis_mask =
2742 INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK |
2743 INTR_EN_TYPE_DISABLE | INTR_EN_IHD_MASK |
2745 intr_context->intr_read_mask =
2746 INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK |
2747 INTR_EN_TYPE_READ | INTR_EN_IHD_MASK | INTR_EN_IHD |
2752 * Default queue handles bcast/mcast plus
2753 * async events. Needs buffers.
2755 intr_context->handler = qlge_isr;
2756 sprintf(intr_context->name, "%s-default-queue",
2758 } else if (i < qdev->rss_ring_first_cq_id) {
2760 * Outbound queue is for outbound completions only.
2762 intr_context->handler = qlge_msix_tx_isr;
2763 sprintf(intr_context->name, "%s-txq-%d",
2764 qdev->ndev->name, i);
2767 * Inbound queues handle unicast frames only.
2769 intr_context->handler = qlge_msix_rx_isr;
2770 sprintf(intr_context->name, "%s-rxq-%d",
2771 qdev->ndev->name, i);
2776 * All rx_rings use the same intr_context since
2777 * there is only one vector.
2779 intr_context->intr = 0;
2780 intr_context->qdev = qdev;
2782 * We set up each vectors enable/disable/read bits so
2783 * there's no bit/mask calculations in the critical path.
2785 intr_context->intr_en_mask =
2786 INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK | INTR_EN_TYPE_ENABLE;
2787 intr_context->intr_dis_mask =
2788 INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK |
2789 INTR_EN_TYPE_DISABLE;
2790 intr_context->intr_read_mask =
2791 INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK | INTR_EN_TYPE_READ;
2793 * Single interrupt means one handler for all rings.
2795 intr_context->handler = qlge_isr;
2796 sprintf(intr_context->name, "%s-single_irq", qdev->ndev->name);
2797 for (i = 0; i < qdev->rx_ring_count; i++)
2798 qdev->rx_ring[i].irq = 0;
2802 static void ql_free_irq(struct ql_adapter *qdev)
2805 struct intr_context *intr_context = &qdev->intr_context[0];
2807 for (i = 0; i < qdev->intr_count; i++, intr_context++) {
2808 if (intr_context->hooked) {
2809 if (test_bit(QL_MSIX_ENABLED, &qdev->flags)) {
2810 free_irq(qdev->msi_x_entry[i].vector,
2812 QPRINTK(qdev, IFDOWN, ERR,
2813 "freeing msix interrupt %d.\n", i);
2815 free_irq(qdev->pdev->irq, &qdev->rx_ring[0]);
2816 QPRINTK(qdev, IFDOWN, ERR,
2817 "freeing msi interrupt %d.\n", i);
2821 ql_disable_msix(qdev);
2824 static int ql_request_irq(struct ql_adapter *qdev)
2828 struct pci_dev *pdev = qdev->pdev;
2829 struct intr_context *intr_context = &qdev->intr_context[0];
2831 ql_resolve_queues_to_irqs(qdev);
2833 for (i = 0; i < qdev->intr_count; i++, intr_context++) {
2834 atomic_set(&intr_context->irq_cnt, 0);
2835 if (test_bit(QL_MSIX_ENABLED, &qdev->flags)) {
2836 status = request_irq(qdev->msi_x_entry[i].vector,
2837 intr_context->handler,
2842 QPRINTK(qdev, IFUP, ERR,
2843 "Failed request for MSIX interrupt %d.\n",
2847 QPRINTK(qdev, IFUP, INFO,
2848 "Hooked intr %d, queue type %s%s%s, with name %s.\n",
2850 qdev->rx_ring[i].type ==
2851 DEFAULT_Q ? "DEFAULT_Q" : "",
2852 qdev->rx_ring[i].type ==
2854 qdev->rx_ring[i].type ==
2855 RX_Q ? "RX_Q" : "", intr_context->name);
2858 QPRINTK(qdev, IFUP, DEBUG,
2859 "trying msi or legacy interrupts.\n");
2860 QPRINTK(qdev, IFUP, DEBUG,
2861 "%s: irq = %d.\n", __func__, pdev->irq);
2862 QPRINTK(qdev, IFUP, DEBUG,
2863 "%s: context->name = %s.\n", __func__,
2864 intr_context->name);
2865 QPRINTK(qdev, IFUP, DEBUG,
2866 "%s: dev_id = 0x%p.\n", __func__,
2869 request_irq(pdev->irq, qlge_isr,
2870 test_bit(QL_MSI_ENABLED,
2872 flags) ? 0 : IRQF_SHARED,
2873 intr_context->name, &qdev->rx_ring[0]);
2877 QPRINTK(qdev, IFUP, ERR,
2878 "Hooked intr %d, queue type %s%s%s, with name %s.\n",
2880 qdev->rx_ring[0].type ==
2881 DEFAULT_Q ? "DEFAULT_Q" : "",
2882 qdev->rx_ring[0].type == TX_Q ? "TX_Q" : "",
2883 qdev->rx_ring[0].type == RX_Q ? "RX_Q" : "",
2884 intr_context->name);
2886 intr_context->hooked = 1;
2890 QPRINTK(qdev, IFUP, ERR, "Failed to get the interrupts!!!/n");
2895 static int ql_start_rss(struct ql_adapter *qdev)
2897 struct ricb *ricb = &qdev->ricb;
2900 u8 *hash_id = (u8 *) ricb->hash_cq_id;
2902 memset((void *)ricb, 0, sizeof(ricb));
2904 ricb->base_cq = qdev->rss_ring_first_cq_id | RSS_L4K;
2906 (RSS_L6K | RSS_LI | RSS_LB | RSS_LM | RSS_RI4 | RSS_RI6 | RSS_RT4 |
2908 ricb->mask = cpu_to_le16(qdev->rss_ring_count - 1);
2911 * Fill out the Indirection Table.
2913 for (i = 0; i < 32; i++)
2917 * Random values for the IPv6 and IPv4 Hash Keys.
2919 get_random_bytes((void *)&ricb->ipv6_hash_key[0], 40);
2920 get_random_bytes((void *)&ricb->ipv4_hash_key[0], 16);
2922 QPRINTK(qdev, IFUP, INFO, "Initializing RSS.\n");
2924 status = ql_write_cfg(qdev, ricb, sizeof(ricb), CFG_LR, 0);
2926 QPRINTK(qdev, IFUP, ERR, "Failed to load RICB.\n");
2929 QPRINTK(qdev, IFUP, INFO, "Successfully loaded RICB.\n");
2933 /* Initialize the frame-to-queue routing. */
2934 static int ql_route_initialize(struct ql_adapter *qdev)
2939 /* Clear all the entries in the routing table. */
2940 for (i = 0; i < 16; i++) {
2941 status = ql_set_routing_reg(qdev, i, 0, 0);
2943 QPRINTK(qdev, IFUP, ERR,
2944 "Failed to init routing register for CAM packets.\n");
2949 status = ql_set_routing_reg(qdev, RT_IDX_ALL_ERR_SLOT, RT_IDX_ERR, 1);
2951 QPRINTK(qdev, IFUP, ERR,
2952 "Failed to init routing register for error packets.\n");
2955 status = ql_set_routing_reg(qdev, RT_IDX_BCAST_SLOT, RT_IDX_BCAST, 1);
2957 QPRINTK(qdev, IFUP, ERR,
2958 "Failed to init routing register for broadcast packets.\n");
2961 /* If we have more than one inbound queue, then turn on RSS in the
2964 if (qdev->rss_ring_count > 1) {
2965 status = ql_set_routing_reg(qdev, RT_IDX_RSS_MATCH_SLOT,
2966 RT_IDX_RSS_MATCH, 1);
2968 QPRINTK(qdev, IFUP, ERR,
2969 "Failed to init routing register for MATCH RSS packets.\n");
2974 status = ql_set_routing_reg(qdev, RT_IDX_CAM_HIT_SLOT,
2977 QPRINTK(qdev, IFUP, ERR,
2978 "Failed to init routing register for CAM packets.\n");
2984 static int ql_adapter_initialize(struct ql_adapter *qdev)
2991 * Set up the System register to halt on errors.
2993 value = SYS_EFE | SYS_FAE;
2995 ql_write32(qdev, SYS, mask | value);
2997 /* Set the default queue. */
2998 value = NIC_RCV_CFG_DFQ;
2999 mask = NIC_RCV_CFG_DFQ_MASK;
3000 ql_write32(qdev, NIC_RCV_CFG, (mask | value));
3002 /* Set the MPI interrupt to enabled. */
3003 ql_write32(qdev, INTR_MASK, (INTR_MASK_PI << 16) | INTR_MASK_PI);
3005 /* Enable the function, set pagesize, enable error checking. */
3006 value = FSC_FE | FSC_EPC_INBOUND | FSC_EPC_OUTBOUND |
3007 FSC_EC | FSC_VM_PAGE_4K | FSC_SH;
3009 /* Set/clear header splitting. */
3010 mask = FSC_VM_PAGESIZE_MASK |
3011 FSC_DBL_MASK | FSC_DBRST_MASK | (value << 16);
3012 ql_write32(qdev, FSC, mask | value);
3014 ql_write32(qdev, SPLT_HDR, SPLT_HDR_EP |
3015 min(SMALL_BUFFER_SIZE, MAX_SPLIT_SIZE));
3017 /* Start up the rx queues. */
3018 for (i = 0; i < qdev->rx_ring_count; i++) {
3019 status = ql_start_rx_ring(qdev, &qdev->rx_ring[i]);
3021 QPRINTK(qdev, IFUP, ERR,
3022 "Failed to start rx ring[%d].\n", i);
3027 /* If there is more than one inbound completion queue
3028 * then download a RICB to configure RSS.
3030 if (qdev->rss_ring_count > 1) {
3031 status = ql_start_rss(qdev);
3033 QPRINTK(qdev, IFUP, ERR, "Failed to start RSS.\n");
3038 /* Start up the tx queues. */
3039 for (i = 0; i < qdev->tx_ring_count; i++) {
3040 status = ql_start_tx_ring(qdev, &qdev->tx_ring[i]);
3042 QPRINTK(qdev, IFUP, ERR,
3043 "Failed to start tx ring[%d].\n", i);
3048 status = ql_port_initialize(qdev);
3050 QPRINTK(qdev, IFUP, ERR, "Failed to start port.\n");
3054 status = ql_set_mac_addr_reg(qdev, (u8 *) qdev->ndev->perm_addr,
3055 MAC_ADDR_TYPE_CAM_MAC, qdev->func);
3057 QPRINTK(qdev, IFUP, ERR, "Failed to init mac address.\n");
3061 status = ql_route_initialize(qdev);
3063 QPRINTK(qdev, IFUP, ERR, "Failed to init routing table.\n");
3067 /* Start NAPI for the RSS queues. */
3068 for (i = qdev->rss_ring_first_cq_id; i < qdev->rx_ring_count; i++) {
3069 QPRINTK(qdev, IFUP, INFO, "Enabling NAPI for rx_ring[%d].\n",
3071 napi_enable(&qdev->rx_ring[i].napi);
3077 /* Issue soft reset to chip. */
3078 static int ql_adapter_reset(struct ql_adapter *qdev)
3085 #define MAX_RESET_CNT 1
3088 QPRINTK(qdev, IFDOWN, DEBUG, "Issue soft reset to chip.\n");
3089 ql_write32(qdev, RST_FO, (RST_FO_FR << 16) | RST_FO_FR);
3090 /* Wait for reset to complete. */
3092 QPRINTK(qdev, IFDOWN, DEBUG, "Wait %d seconds for reset to complete.\n",
3095 value = ql_read32(qdev, RST_FO);
3096 if ((value & RST_FO_FR) == 0)
3100 } while ((--max_wait_time));
3101 if (value & RST_FO_FR) {
3102 QPRINTK(qdev, IFDOWN, ERR,
3103 "Stuck in SoftReset: FSC_SR:0x%08x\n", value);
3104 if (resetCnt < MAX_RESET_CNT)
3107 if (max_wait_time == 0) {
3108 status = -ETIMEDOUT;
3109 QPRINTK(qdev, IFDOWN, ERR,
3110 "ETIMEOUT!!! errored out of resetting the chip!\n");
3116 static void ql_display_dev_info(struct net_device *ndev)
3118 struct ql_adapter *qdev = (struct ql_adapter *)netdev_priv(ndev);
3120 QPRINTK(qdev, PROBE, INFO,
3121 "Function #%d, NIC Roll %d, NIC Rev = %d, "
3122 "XG Roll = %d, XG Rev = %d.\n",
3124 qdev->chip_rev_id & 0x0000000f,
3125 qdev->chip_rev_id >> 4 & 0x0000000f,
3126 qdev->chip_rev_id >> 8 & 0x0000000f,
3127 qdev->chip_rev_id >> 12 & 0x0000000f);
3128 QPRINTK(qdev, PROBE, INFO, "MAC address %pM\n", ndev->dev_addr);
3131 static int ql_adapter_down(struct ql_adapter *qdev)
3133 struct net_device *ndev = qdev->ndev;
3135 struct rx_ring *rx_ring;
3137 netif_stop_queue(ndev);
3138 netif_carrier_off(ndev);
3140 cancel_delayed_work_sync(&qdev->asic_reset_work);
3141 cancel_delayed_work_sync(&qdev->mpi_reset_work);
3142 cancel_delayed_work_sync(&qdev->mpi_work);
3144 /* The default queue at index 0 is always processed in
3147 cancel_delayed_work_sync(&qdev->rx_ring[0].rx_work);
3149 /* The rest of the rx_rings are processed in
3150 * a workqueue only if it's a single interrupt
3151 * environment (MSI/Legacy).
3153 for (i = 1; i > qdev->rx_ring_count; i++) {
3154 rx_ring = &qdev->rx_ring[i];
3155 /* Only the RSS rings use NAPI on multi irq
3156 * environment. Outbound completion processing
3157 * is done in interrupt context.
3159 if (i >= qdev->rss_ring_first_cq_id) {
3160 napi_disable(&rx_ring->napi);
3162 cancel_delayed_work_sync(&rx_ring->rx_work);
3166 clear_bit(QL_ADAPTER_UP, &qdev->flags);
3168 ql_disable_interrupts(qdev);
3170 ql_tx_ring_clean(qdev);
3172 spin_lock(&qdev->hw_lock);
3173 status = ql_adapter_reset(qdev);
3175 QPRINTK(qdev, IFDOWN, ERR, "reset(func #%d) FAILED!\n",
3177 spin_unlock(&qdev->hw_lock);
3181 static int ql_adapter_up(struct ql_adapter *qdev)
3185 spin_lock(&qdev->hw_lock);
3186 err = ql_adapter_initialize(qdev);
3188 QPRINTK(qdev, IFUP, INFO, "Unable to initialize adapter.\n");
3189 spin_unlock(&qdev->hw_lock);
3192 spin_unlock(&qdev->hw_lock);
3193 set_bit(QL_ADAPTER_UP, &qdev->flags);
3194 ql_enable_interrupts(qdev);
3195 ql_enable_all_completion_interrupts(qdev);
3196 if ((ql_read32(qdev, STS) & qdev->port_init)) {
3197 netif_carrier_on(qdev->ndev);
3198 netif_start_queue(qdev->ndev);
3203 ql_adapter_reset(qdev);
3207 static int ql_cycle_adapter(struct ql_adapter *qdev)
3211 status = ql_adapter_down(qdev);
3215 status = ql_adapter_up(qdev);
3221 QPRINTK(qdev, IFUP, ALERT,
3222 "Driver up/down cycle failed, closing device\n");
3224 dev_close(qdev->ndev);
3229 static void ql_release_adapter_resources(struct ql_adapter *qdev)
3231 ql_free_mem_resources(qdev);
3235 static int ql_get_adapter_resources(struct ql_adapter *qdev)
3239 if (ql_alloc_mem_resources(qdev)) {
3240 QPRINTK(qdev, IFUP, ERR, "Unable to allocate memory.\n");
3243 status = ql_request_irq(qdev);
3248 ql_free_mem_resources(qdev);
3252 static int qlge_close(struct net_device *ndev)
3254 struct ql_adapter *qdev = netdev_priv(ndev);
3257 * Wait for device to recover from a reset.
3258 * (Rarely happens, but possible.)
3260 while (!test_bit(QL_ADAPTER_UP, &qdev->flags))
3262 ql_adapter_down(qdev);
3263 ql_release_adapter_resources(qdev);
3264 ql_free_ring_cb(qdev);
3268 static int ql_configure_rings(struct ql_adapter *qdev)
3271 struct rx_ring *rx_ring;
3272 struct tx_ring *tx_ring;
3273 int cpu_cnt = num_online_cpus();
3276 * For each processor present we allocate one
3277 * rx_ring for outbound completions, and one
3278 * rx_ring for inbound completions. Plus there is
3279 * always the one default queue. For the CPU
3280 * counts we end up with the following rx_rings:
3282 * one default queue +
3283 * (CPU count * outbound completion rx_ring) +
3284 * (CPU count * inbound (RSS) completion rx_ring)
3285 * To keep it simple we limit the total number of
3286 * queues to < 32, so we truncate CPU to 8.
3287 * This limitation can be removed when requested.
3294 * rx_ring[0] is always the default queue.
3296 /* Allocate outbound completion ring for each CPU. */
3297 qdev->tx_ring_count = cpu_cnt;
3298 /* Allocate inbound completion (RSS) ring for each CPU. */
3299 qdev->rss_ring_count = cpu_cnt;
3300 /* cq_id for the first inbound ring handler. */
3301 qdev->rss_ring_first_cq_id = cpu_cnt + 1;
3303 * qdev->rx_ring_count:
3304 * Total number of rx_rings. This includes the one
3305 * default queue, a number of outbound completion
3306 * handler rx_rings, and the number of inbound
3307 * completion handler rx_rings.
3309 qdev->rx_ring_count = qdev->tx_ring_count + qdev->rss_ring_count + 1;
3311 if (ql_alloc_ring_cb(qdev))
3314 for (i = 0; i < qdev->tx_ring_count; i++) {
3315 tx_ring = &qdev->tx_ring[i];
3316 memset((void *)tx_ring, 0, sizeof(tx_ring));
3317 tx_ring->qdev = qdev;
3319 tx_ring->wq_len = qdev->tx_ring_size;
3321 tx_ring->wq_len * sizeof(struct ob_mac_iocb_req);
3324 * The completion queue ID for the tx rings start
3325 * immediately after the default Q ID, which is zero.
3327 tx_ring->cq_id = i + 1;
3330 for (i = 0; i < qdev->rx_ring_count; i++) {
3331 rx_ring = &qdev->rx_ring[i];
3332 memset((void *)rx_ring, 0, sizeof(rx_ring));
3333 rx_ring->qdev = qdev;
3335 rx_ring->cpu = i % cpu_cnt; /* CPU to run handler on. */
3336 if (i == 0) { /* Default queue at index 0. */
3338 * Default queue handles bcast/mcast plus
3339 * async events. Needs buffers.
3341 rx_ring->cq_len = qdev->rx_ring_size;
3343 rx_ring->cq_len * sizeof(struct ql_net_rsp_iocb);
3344 rx_ring->lbq_len = NUM_LARGE_BUFFERS;
3346 rx_ring->lbq_len * sizeof(struct bq_element);
3347 rx_ring->lbq_buf_size = LARGE_BUFFER_SIZE;
3348 rx_ring->sbq_len = NUM_SMALL_BUFFERS;
3350 rx_ring->sbq_len * sizeof(struct bq_element);
3351 rx_ring->sbq_buf_size = SMALL_BUFFER_SIZE * 2;
3352 rx_ring->type = DEFAULT_Q;
3353 } else if (i < qdev->rss_ring_first_cq_id) {
3355 * Outbound queue handles outbound completions only.
3357 /* outbound cq is same size as tx_ring it services. */
3358 rx_ring->cq_len = qdev->tx_ring_size;
3360 rx_ring->cq_len * sizeof(struct ql_net_rsp_iocb);
3361 rx_ring->lbq_len = 0;
3362 rx_ring->lbq_size = 0;
3363 rx_ring->lbq_buf_size = 0;
3364 rx_ring->sbq_len = 0;
3365 rx_ring->sbq_size = 0;
3366 rx_ring->sbq_buf_size = 0;
3367 rx_ring->type = TX_Q;
3368 } else { /* Inbound completions (RSS) queues */
3370 * Inbound queues handle unicast frames only.
3372 rx_ring->cq_len = qdev->rx_ring_size;
3374 rx_ring->cq_len * sizeof(struct ql_net_rsp_iocb);
3375 rx_ring->lbq_len = NUM_LARGE_BUFFERS;
3377 rx_ring->lbq_len * sizeof(struct bq_element);
3378 rx_ring->lbq_buf_size = LARGE_BUFFER_SIZE;
3379 rx_ring->sbq_len = NUM_SMALL_BUFFERS;
3381 rx_ring->sbq_len * sizeof(struct bq_element);
3382 rx_ring->sbq_buf_size = SMALL_BUFFER_SIZE * 2;
3383 rx_ring->type = RX_Q;
3389 static int qlge_open(struct net_device *ndev)
3392 struct ql_adapter *qdev = netdev_priv(ndev);
3394 err = ql_configure_rings(qdev);
3398 err = ql_get_adapter_resources(qdev);
3402 err = ql_adapter_up(qdev);
3409 ql_release_adapter_resources(qdev);
3410 ql_free_ring_cb(qdev);
3414 static int qlge_change_mtu(struct net_device *ndev, int new_mtu)
3416 struct ql_adapter *qdev = netdev_priv(ndev);
3418 if (ndev->mtu == 1500 && new_mtu == 9000) {
3419 QPRINTK(qdev, IFUP, ERR, "Changing to jumbo MTU.\n");
3420 } else if (ndev->mtu == 9000 && new_mtu == 1500) {
3421 QPRINTK(qdev, IFUP, ERR, "Changing to normal MTU.\n");
3422 } else if ((ndev->mtu == 1500 && new_mtu == 1500) ||
3423 (ndev->mtu == 9000 && new_mtu == 9000)) {
3427 ndev->mtu = new_mtu;
3431 static struct net_device_stats *qlge_get_stats(struct net_device
3434 struct ql_adapter *qdev = netdev_priv(ndev);
3435 return &qdev->stats;
3438 static void qlge_set_multicast_list(struct net_device *ndev)
3440 struct ql_adapter *qdev = (struct ql_adapter *)netdev_priv(ndev);
3441 struct dev_mc_list *mc_ptr;
3444 spin_lock(&qdev->hw_lock);
3446 * Set or clear promiscuous mode if a
3447 * transition is taking place.
3449 if (ndev->flags & IFF_PROMISC) {
3450 if (!test_bit(QL_PROMISCUOUS, &qdev->flags)) {
3451 if (ql_set_routing_reg
3452 (qdev, RT_IDX_PROMISCUOUS_SLOT, RT_IDX_VALID, 1)) {
3453 QPRINTK(qdev, HW, ERR,
3454 "Failed to set promiscous mode.\n");
3456 set_bit(QL_PROMISCUOUS, &qdev->flags);
3460 if (test_bit(QL_PROMISCUOUS, &qdev->flags)) {
3461 if (ql_set_routing_reg
3462 (qdev, RT_IDX_PROMISCUOUS_SLOT, RT_IDX_VALID, 0)) {
3463 QPRINTK(qdev, HW, ERR,
3464 "Failed to clear promiscous mode.\n");
3466 clear_bit(QL_PROMISCUOUS, &qdev->flags);
3472 * Set or clear all multicast mode if a
3473 * transition is taking place.
3475 if ((ndev->flags & IFF_ALLMULTI) ||
3476 (ndev->mc_count > MAX_MULTICAST_ENTRIES)) {
3477 if (!test_bit(QL_ALLMULTI, &qdev->flags)) {
3478 if (ql_set_routing_reg
3479 (qdev, RT_IDX_ALLMULTI_SLOT, RT_IDX_MCAST, 1)) {
3480 QPRINTK(qdev, HW, ERR,
3481 "Failed to set all-multi mode.\n");
3483 set_bit(QL_ALLMULTI, &qdev->flags);
3487 if (test_bit(QL_ALLMULTI, &qdev->flags)) {
3488 if (ql_set_routing_reg
3489 (qdev, RT_IDX_ALLMULTI_SLOT, RT_IDX_MCAST, 0)) {
3490 QPRINTK(qdev, HW, ERR,
3491 "Failed to clear all-multi mode.\n");
3493 clear_bit(QL_ALLMULTI, &qdev->flags);
3498 if (ndev->mc_count) {
3499 for (i = 0, mc_ptr = ndev->mc_list; mc_ptr;
3500 i++, mc_ptr = mc_ptr->next)
3501 if (ql_set_mac_addr_reg(qdev, (u8 *) mc_ptr->dmi_addr,
3502 MAC_ADDR_TYPE_MULTI_MAC, i)) {
3503 QPRINTK(qdev, HW, ERR,
3504 "Failed to loadmulticast address.\n");
3507 if (ql_set_routing_reg
3508 (qdev, RT_IDX_MCAST_MATCH_SLOT, RT_IDX_MCAST_MATCH, 1)) {
3509 QPRINTK(qdev, HW, ERR,
3510 "Failed to set multicast match mode.\n");
3512 set_bit(QL_ALLMULTI, &qdev->flags);
3516 spin_unlock(&qdev->hw_lock);
3519 static int qlge_set_mac_address(struct net_device *ndev, void *p)
3521 struct ql_adapter *qdev = (struct ql_adapter *)netdev_priv(ndev);
3522 struct sockaddr *addr = p;
3525 if (netif_running(ndev))
3528 if (!is_valid_ether_addr(addr->sa_data))
3529 return -EADDRNOTAVAIL;
3530 memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len);
3532 spin_lock(&qdev->hw_lock);
3533 if (ql_set_mac_addr_reg(qdev, (u8 *) ndev->dev_addr,
3534 MAC_ADDR_TYPE_CAM_MAC, qdev->func)) {/* Unicast */
3535 QPRINTK(qdev, HW, ERR, "Failed to load MAC address.\n");
3538 spin_unlock(&qdev->hw_lock);
3543 static void qlge_tx_timeout(struct net_device *ndev)
3545 struct ql_adapter *qdev = (struct ql_adapter *)netdev_priv(ndev);
3546 queue_delayed_work(qdev->workqueue, &qdev->asic_reset_work, 0);
3549 static void ql_asic_reset_work(struct work_struct *work)
3551 struct ql_adapter *qdev =
3552 container_of(work, struct ql_adapter, asic_reset_work.work);
3553 ql_cycle_adapter(qdev);
3556 static void ql_get_board_info(struct ql_adapter *qdev)
3559 (ql_read32(qdev, STS) & STS_FUNC_ID_MASK) >> STS_FUNC_ID_SHIFT;
3561 qdev->xg_sem_mask = SEM_XGMAC1_MASK;
3562 qdev->port_link_up = STS_PL1;
3563 qdev->port_init = STS_PI1;
3564 qdev->mailbox_in = PROC_ADDR_MPI_RISC | PROC_ADDR_FUNC2_MBI;
3565 qdev->mailbox_out = PROC_ADDR_MPI_RISC | PROC_ADDR_FUNC2_MBO;
3567 qdev->xg_sem_mask = SEM_XGMAC0_MASK;
3568 qdev->port_link_up = STS_PL0;
3569 qdev->port_init = STS_PI0;
3570 qdev->mailbox_in = PROC_ADDR_MPI_RISC | PROC_ADDR_FUNC0_MBI;
3571 qdev->mailbox_out = PROC_ADDR_MPI_RISC | PROC_ADDR_FUNC0_MBO;
3573 qdev->chip_rev_id = ql_read32(qdev, REV_ID);
3576 static void ql_release_all(struct pci_dev *pdev)
3578 struct net_device *ndev = pci_get_drvdata(pdev);
3579 struct ql_adapter *qdev = netdev_priv(ndev);
3581 if (qdev->workqueue) {
3582 destroy_workqueue(qdev->workqueue);
3583 qdev->workqueue = NULL;
3585 if (qdev->q_workqueue) {
3586 destroy_workqueue(qdev->q_workqueue);
3587 qdev->q_workqueue = NULL;
3590 iounmap(qdev->reg_base);
3591 if (qdev->doorbell_area)
3592 iounmap(qdev->doorbell_area);
3593 pci_release_regions(pdev);
3594 pci_set_drvdata(pdev, NULL);
3597 static int __devinit ql_init_device(struct pci_dev *pdev,
3598 struct net_device *ndev, int cards_found)
3600 struct ql_adapter *qdev = netdev_priv(ndev);
3604 memset((void *)qdev, 0, sizeof(qdev));
3605 err = pci_enable_device(pdev);
3607 dev_err(&pdev->dev, "PCI device enable failed.\n");
3611 pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
3613 dev_err(&pdev->dev, PFX "Cannot find PCI Express capability, "
3617 pci_read_config_word(pdev, pos + PCI_EXP_DEVCTL, &val16);
3618 val16 &= ~PCI_EXP_DEVCTL_NOSNOOP_EN;
3619 val16 |= (PCI_EXP_DEVCTL_CERE |
3620 PCI_EXP_DEVCTL_NFERE |
3621 PCI_EXP_DEVCTL_FERE | PCI_EXP_DEVCTL_URRE);
3622 pci_write_config_word(pdev, pos + PCI_EXP_DEVCTL, val16);
3625 err = pci_request_regions(pdev, DRV_NAME);
3627 dev_err(&pdev->dev, "PCI region request failed.\n");
3631 pci_set_master(pdev);
3632 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
3633 set_bit(QL_DMA64, &qdev->flags);
3634 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
3636 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3638 err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
3642 dev_err(&pdev->dev, "No usable DMA configuration.\n");
3646 pci_set_drvdata(pdev, ndev);
3648 ioremap_nocache(pci_resource_start(pdev, 1),
3649 pci_resource_len(pdev, 1));
3650 if (!qdev->reg_base) {
3651 dev_err(&pdev->dev, "Register mapping failed.\n");
3656 qdev->doorbell_area_size = pci_resource_len(pdev, 3);
3657 qdev->doorbell_area =
3658 ioremap_nocache(pci_resource_start(pdev, 3),
3659 pci_resource_len(pdev, 3));
3660 if (!qdev->doorbell_area) {
3661 dev_err(&pdev->dev, "Doorbell register mapping failed.\n");
3666 ql_get_board_info(qdev);
3669 qdev->msg_enable = netif_msg_init(debug, default_msg);
3670 spin_lock_init(&qdev->hw_lock);
3671 spin_lock_init(&qdev->stats_lock);
3673 /* make sure the EEPROM is good */
3674 err = ql_get_flash_params(qdev);
3676 dev_err(&pdev->dev, "Invalid FLASH.\n");
3680 if (!is_valid_ether_addr(qdev->flash.mac_addr))
3683 memcpy(ndev->dev_addr, qdev->flash.mac_addr, ndev->addr_len);
3684 memcpy(ndev->perm_addr, ndev->dev_addr, ndev->addr_len);
3686 /* Set up the default ring sizes. */
3687 qdev->tx_ring_size = NUM_TX_RING_ENTRIES;
3688 qdev->rx_ring_size = NUM_RX_RING_ENTRIES;
3690 /* Set up the coalescing parameters. */
3691 qdev->rx_coalesce_usecs = DFLT_COALESCE_WAIT;
3692 qdev->tx_coalesce_usecs = DFLT_COALESCE_WAIT;
3693 qdev->rx_max_coalesced_frames = DFLT_INTER_FRAME_WAIT;
3694 qdev->tx_max_coalesced_frames = DFLT_INTER_FRAME_WAIT;
3697 * Set up the operating parameters.
3701 qdev->q_workqueue = create_workqueue(ndev->name);
3702 qdev->workqueue = create_singlethread_workqueue(ndev->name);
3703 INIT_DELAYED_WORK(&qdev->asic_reset_work, ql_asic_reset_work);
3704 INIT_DELAYED_WORK(&qdev->mpi_reset_work, ql_mpi_reset_work);
3705 INIT_DELAYED_WORK(&qdev->mpi_work, ql_mpi_work);
3708 dev_info(&pdev->dev, "%s\n", DRV_STRING);
3709 dev_info(&pdev->dev, "Driver name: %s, Version: %s.\n",
3710 DRV_NAME, DRV_VERSION);
3714 ql_release_all(pdev);
3715 pci_disable_device(pdev);
3720 static const struct net_device_ops qlge_netdev_ops = {
3721 .ndo_open = qlge_open,
3722 .ndo_stop = qlge_close,
3723 .ndo_start_xmit = qlge_send,
3724 .ndo_change_mtu = qlge_change_mtu,
3725 .ndo_get_stats = qlge_get_stats,
3726 .ndo_set_multicast_list = qlge_set_multicast_list,
3727 .ndo_set_mac_address = qlge_set_mac_address,
3728 .ndo_validate_addr = eth_validate_addr,
3729 .ndo_tx_timeout = qlge_tx_timeout,
3730 .ndo_vlan_rx_register = ql_vlan_rx_register,
3731 .ndo_vlan_rx_add_vid = ql_vlan_rx_add_vid,
3732 .ndo_vlan_rx_kill_vid = ql_vlan_rx_kill_vid,
3735 static int __devinit qlge_probe(struct pci_dev *pdev,
3736 const struct pci_device_id *pci_entry)
3738 struct net_device *ndev = NULL;
3739 struct ql_adapter *qdev = NULL;
3740 static int cards_found = 0;
3743 ndev = alloc_etherdev(sizeof(struct ql_adapter));
3747 err = ql_init_device(pdev, ndev, cards_found);
3753 qdev = netdev_priv(ndev);
3754 SET_NETDEV_DEV(ndev, &pdev->dev);
3761 | NETIF_F_HW_VLAN_TX
3762 | NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_FILTER);
3764 if (test_bit(QL_DMA64, &qdev->flags))
3765 ndev->features |= NETIF_F_HIGHDMA;
3768 * Set up net_device structure.
3770 ndev->tx_queue_len = qdev->tx_ring_size;
3771 ndev->irq = pdev->irq;
3773 ndev->netdev_ops = &qlge_netdev_ops;
3774 SET_ETHTOOL_OPS(ndev, &qlge_ethtool_ops);
3775 ndev->watchdog_timeo = 10 * HZ;
3777 err = register_netdev(ndev);
3779 dev_err(&pdev->dev, "net device registration failed.\n");
3780 ql_release_all(pdev);
3781 pci_disable_device(pdev);
3784 netif_carrier_off(ndev);
3785 netif_stop_queue(ndev);
3786 ql_display_dev_info(ndev);
3791 static void __devexit qlge_remove(struct pci_dev *pdev)
3793 struct net_device *ndev = pci_get_drvdata(pdev);
3794 unregister_netdev(ndev);
3795 ql_release_all(pdev);
3796 pci_disable_device(pdev);
3801 * This callback is called by the PCI subsystem whenever
3802 * a PCI bus error is detected.
3804 static pci_ers_result_t qlge_io_error_detected(struct pci_dev *pdev,
3805 enum pci_channel_state state)
3807 struct net_device *ndev = pci_get_drvdata(pdev);
3808 struct ql_adapter *qdev = netdev_priv(ndev);
3810 if (netif_running(ndev))
3811 ql_adapter_down(qdev);
3813 pci_disable_device(pdev);
3815 /* Request a slot reset. */
3816 return PCI_ERS_RESULT_NEED_RESET;
3820 * This callback is called after the PCI buss has been reset.
3821 * Basically, this tries to restart the card from scratch.
3822 * This is a shortened version of the device probe/discovery code,
3823 * it resembles the first-half of the () routine.
3825 static pci_ers_result_t qlge_io_slot_reset(struct pci_dev *pdev)
3827 struct net_device *ndev = pci_get_drvdata(pdev);
3828 struct ql_adapter *qdev = netdev_priv(ndev);
3830 if (pci_enable_device(pdev)) {
3831 QPRINTK(qdev, IFUP, ERR,
3832 "Cannot re-enable PCI device after reset.\n");
3833 return PCI_ERS_RESULT_DISCONNECT;
3836 pci_set_master(pdev);
3838 netif_carrier_off(ndev);
3839 netif_stop_queue(ndev);
3840 ql_adapter_reset(qdev);
3842 /* Make sure the EEPROM is good */
3843 memcpy(ndev->perm_addr, ndev->dev_addr, ndev->addr_len);
3845 if (!is_valid_ether_addr(ndev->perm_addr)) {
3846 QPRINTK(qdev, IFUP, ERR, "After reset, invalid MAC address.\n");
3847 return PCI_ERS_RESULT_DISCONNECT;
3850 return PCI_ERS_RESULT_RECOVERED;
3853 static void qlge_io_resume(struct pci_dev *pdev)
3855 struct net_device *ndev = pci_get_drvdata(pdev);
3856 struct ql_adapter *qdev = netdev_priv(ndev);
3858 pci_set_master(pdev);
3860 if (netif_running(ndev)) {
3861 if (ql_adapter_up(qdev)) {
3862 QPRINTK(qdev, IFUP, ERR,
3863 "Device initialization failed after reset.\n");
3868 netif_device_attach(ndev);
3871 static struct pci_error_handlers qlge_err_handler = {
3872 .error_detected = qlge_io_error_detected,
3873 .slot_reset = qlge_io_slot_reset,
3874 .resume = qlge_io_resume,
3877 static int qlge_suspend(struct pci_dev *pdev, pm_message_t state)
3879 struct net_device *ndev = pci_get_drvdata(pdev);
3880 struct ql_adapter *qdev = netdev_priv(ndev);
3883 netif_device_detach(ndev);
3885 if (netif_running(ndev)) {
3886 err = ql_adapter_down(qdev);
3891 err = pci_save_state(pdev);
3895 pci_disable_device(pdev);
3897 pci_set_power_state(pdev, pci_choose_state(pdev, state));
3903 static int qlge_resume(struct pci_dev *pdev)
3905 struct net_device *ndev = pci_get_drvdata(pdev);
3906 struct ql_adapter *qdev = netdev_priv(ndev);
3909 pci_set_power_state(pdev, PCI_D0);
3910 pci_restore_state(pdev);
3911 err = pci_enable_device(pdev);
3913 QPRINTK(qdev, IFUP, ERR, "Cannot enable PCI device from suspend\n");
3916 pci_set_master(pdev);
3918 pci_enable_wake(pdev, PCI_D3hot, 0);
3919 pci_enable_wake(pdev, PCI_D3cold, 0);
3921 if (netif_running(ndev)) {
3922 err = ql_adapter_up(qdev);
3927 netif_device_attach(ndev);
3931 #endif /* CONFIG_PM */
3933 static void qlge_shutdown(struct pci_dev *pdev)
3935 qlge_suspend(pdev, PMSG_SUSPEND);
3938 static struct pci_driver qlge_driver = {
3940 .id_table = qlge_pci_tbl,
3941 .probe = qlge_probe,
3942 .remove = __devexit_p(qlge_remove),
3944 .suspend = qlge_suspend,
3945 .resume = qlge_resume,
3947 .shutdown = qlge_shutdown,
3948 .err_handler = &qlge_err_handler
3951 static int __init qlge_init_module(void)
3953 return pci_register_driver(&qlge_driver);
3956 static void __exit qlge_exit(void)
3958 pci_unregister_driver(&qlge_driver);
3961 module_init(qlge_init_module);
3962 module_exit(qlge_exit);