drivers/net/s2io.c

   1 /************************************************************************
   2  * s2io.c: A Linux PCI-X Ethernet driver for Neterion 10GbE Server NIC
   3  * Copyright(c) 2002-2005 Neterion Inc.
   4
   5  * This software may be used and distributed according to the terms of
   6  * the GNU General Public License (GPL), incorporated herein by reference.
   7  * Drivers based on or derived from this code fall under the GPL and must
   8  * retain the authorship, copyright and license notice.  This file is not
   9  * a complete program and may only be used when the entire operating
  10  * system is licensed under the GPL.
  11  * See the file COPYING in this distribution for more information.
  12  *
  13  * Credits:
  14  * Jeff Garzik          : For pointing out the improper error condition
  15  *                        check in the s2io_xmit routine and also some
  16  *                        issues in the Tx watch dog function. Also for
  17  *                        patiently answering all those innumerable
  18  *                        questions regaring the 2.6 porting issues.
  19  * Stephen Hemminger    : Providing proper 2.6 porting mechanism for some
  20  *                        macros available only in 2.6 Kernel.
  21  * Francois Romieu      : For pointing out all code part that were
  22  *                        deprecated and also styling related comments.
  23  * Grant Grundler       : For helping me get rid of some Architecture
  24  *                        dependent code.
  25  * Christopher Hellwig  : Some more 2.6 specific issues in the driver.
  26  *
  27  * The module loadable parameters that are supported by the driver and a brief
  28  * explaination of all the variables.
  29  *
  30  * rx_ring_num : This can be used to program the number of receive rings used
  31  * in the driver.
  32  * rx_ring_sz: This defines the number of receive blocks each ring can have.
  33  *     This is also an array of size 8.
  34  * rx_ring_mode: This defines the operation mode of all 8 rings. The valid
  35  *              values are 1, 2 and 3.
  36  * tx_fifo_num: This defines the number of Tx FIFOs thats used int the driver.
  37  * tx_fifo_len: This too is an array of 8. Each element defines the number of
  38  * Tx descriptors that can be associated with each corresponding FIFO.
  39  * intr_type: This defines the type of interrupt. The values can be 0(INTA),
  40  *     1(MSI), 2(MSI_X). Default value is '0(INTA)'
  41  * lro: Specifies whether to enable Large Receive Offload (LRO) or not.
  42  *     Possible values '1' for enable '0' for disable. Default is '0'
  43  * lro_max_pkts: This parameter defines maximum number of packets can be
  44  *     aggregated as a single large packet
  45  ************************************************************************/
  46
  47 #include <linux/config.h>
  48 #include <linux/module.h>
  49 #include <linux/types.h>
  50 #include <linux/errno.h>
  51 #include <linux/ioport.h>
  52 #include <linux/pci.h>
  53 #include <linux/dma-mapping.h>
  54 #include <linux/kernel.h>
  55 #include <linux/netdevice.h>
  56 #include <linux/etherdevice.h>
  57 #include <linux/skbuff.h>
  58 #include <linux/init.h>
  59 #include <linux/delay.h>
  60 #include <linux/stddef.h>
  61 #include <linux/ioctl.h>
  62 #include <linux/timex.h>
  63 #include <linux/sched.h>
  64 #include <linux/ethtool.h>
  65 #include <linux/workqueue.h>
  66 #include <linux/if_vlan.h>
  67 #include <linux/ip.h>
  68 #include <linux/tcp.h>
  69 #include <net/tcp.h>
  70
  71 #include <asm/system.h>
  72 #include <asm/uaccess.h>
  73 #include <asm/io.h>
  74 #include <asm/div64.h>
  75
  76 /* local include */
  77 #include "s2io.h"
  78 #include "s2io-regs.h"
  79
  80 #define DRV_VERSION "2.0.11.2"
  81
  82 /* S2io Driver name & version. */
  83 static char s2io_driver_name[] = "Neterion";
  84 static char s2io_driver_version[] = DRV_VERSION;
  85
  86 static int rxd_size[4] = {32,48,48,64};
  87 static int rxd_count[4] = {127,85,85,63};
  88
  89 static inline int RXD_IS_UP2DT(RxD_t *rxdp)
  90 {
  91         int ret;
  92
  93         ret = ((!(rxdp->Control_1 & RXD_OWN_XENA)) &&
  94                 (GET_RXD_MARKER(rxdp->Control_2) != THE_RXD_MARK));
  95
  96         return ret;
  97 }
  98
  99 /*
 100  * Cards with following subsystem_id have a link state indication
 101  * problem, 600B, 600C, 600D, 640B, 640C and 640D.
 102  * macro below identifies these cards given the subsystem_id.
 103  */
 104 #define CARDS_WITH_FAULTY_LINK_INDICATORS(dev_type, subid) \
 105         (dev_type == XFRAME_I_DEVICE) ?                 \
 106                 ((((subid >= 0x600B) && (subid <= 0x600D)) || \
 107                  ((subid >= 0x640B) && (subid <= 0x640D))) ? 1 : 0) : 0
 108
 109 #define LINK_IS_UP(val64) (!(val64 & (ADAPTER_STATUS_RMAC_REMOTE_FAULT | \
 110                                       ADAPTER_STATUS_RMAC_LOCAL_FAULT)))
 111 #define TASKLET_IN_USE test_and_set_bit(0, (&sp->tasklet_status))
 112 #define PANIC   1
 113 #define LOW     2
 114 static inline int rx_buffer_level(nic_t * sp, int rxb_size, int ring)
 115 {
 116         mac_info_t *mac_control;
 117
 118         mac_control = &sp->mac_control;
 119         if (rxb_size <= rxd_count[sp->rxd_mode])
 120                 return PANIC;
 121         else if ((mac_control->rings[ring].pkt_cnt - rxb_size) > 16)
 122                 return  LOW;
 123         return 0;
 124 }
 125
 126 /* Ethtool related variables and Macros. */
 127 static char s2io_gstrings[][ETH_GSTRING_LEN] = {
 128         "Register test\t(offline)",
 129         "Eeprom test\t(offline)",
 130         "Link test\t(online)",
 131         "RLDRAM test\t(offline)",
 132         "BIST Test\t(offline)"
 133 };
 134
 135 static char ethtool_stats_keys[][ETH_GSTRING_LEN] = {
 136         {"tmac_frms"},
 137         {"tmac_data_octets"},
 138         {"tmac_drop_frms"},
 139         {"tmac_mcst_frms"},
 140         {"tmac_bcst_frms"},
 141         {"tmac_pause_ctrl_frms"},
 142         {"tmac_any_err_frms"},
 143         {"tmac_vld_ip_octets"},
 144         {"tmac_vld_ip"},
 145         {"tmac_drop_ip"},
 146         {"tmac_icmp"},
 147         {"tmac_rst_tcp"},
 148         {"tmac_tcp"},
 149         {"tmac_udp"},
 150         {"rmac_vld_frms"},
 151         {"rmac_data_octets"},
 152         {"rmac_fcs_err_frms"},
 153         {"rmac_drop_frms"},
 154         {"rmac_vld_mcst_frms"},
 155         {"rmac_vld_bcst_frms"},
 156         {"rmac_in_rng_len_err_frms"},
 157         {"rmac_long_frms"},
 158         {"rmac_pause_ctrl_frms"},
 159         {"rmac_discarded_frms"},
 160         {"rmac_usized_frms"},
 161         {"rmac_osized_frms"},
 162         {"rmac_frag_frms"},
 163         {"rmac_jabber_frms"},
 164         {"rmac_ip"},
 165         {"rmac_ip_octets"},
 166         {"rmac_hdr_err_ip"},
 167         {"rmac_drop_ip"},
 168         {"rmac_icmp"},
 169         {"rmac_tcp"},
 170         {"rmac_udp"},
 171         {"rmac_err_drp_udp"},
 172         {"rmac_pause_cnt"},
 173         {"rmac_accepted_ip"},
 174         {"rmac_err_tcp"},
 175         {"\n DRIVER STATISTICS"},
 176         {"single_bit_ecc_errs"},
 177         {"double_bit_ecc_errs"},
 178         ("lro_aggregated_pkts"),
 179         ("lro_flush_both_count"),
 180         ("lro_out_of_sequence_pkts"),
 181         ("lro_flush_due_to_max_pkts"),
 182         ("lro_avg_aggr_pkts"),
 183 };
 184
 185 #define S2IO_STAT_LEN sizeof(ethtool_stats_keys)/ ETH_GSTRING_LEN
 186 #define S2IO_STAT_STRINGS_LEN S2IO_STAT_LEN * ETH_GSTRING_LEN
 187
 188 #define S2IO_TEST_LEN   sizeof(s2io_gstrings) / ETH_GSTRING_LEN
 189 #define S2IO_STRINGS_LEN        S2IO_TEST_LEN * ETH_GSTRING_LEN
 190
 191 #define S2IO_TIMER_CONF(timer, handle, arg, exp)                \
 192                         init_timer(&timer);                     \
 193                         timer.function = handle;                \
 194                         timer.data = (unsigned long) arg;       \
 195                         mod_timer(&timer, (jiffies + exp))      \
 196
 197 /* Add the vlan */
 198 static void s2io_vlan_rx_register(struct net_device *dev,
 199                                         struct vlan_group *grp)
 200 {
 201         nic_t *nic = dev->priv;
 202         unsigned long flags;
 203
 204         spin_lock_irqsave(&nic->tx_lock, flags);
 205         nic->vlgrp = grp;
 206         spin_unlock_irqrestore(&nic->tx_lock, flags);
 207 }
 208
 209 /* Unregister the vlan */
 210 static void s2io_vlan_rx_kill_vid(struct net_device *dev, unsigned long vid)
 211 {
 212         nic_t *nic = dev->priv;
 213         unsigned long flags;
 214
 215         spin_lock_irqsave(&nic->tx_lock, flags);
 216         if (nic->vlgrp)
 217                 nic->vlgrp->vlan_devices[vid] = NULL;
 218         spin_unlock_irqrestore(&nic->tx_lock, flags);
 219 }
 220
 221 /*
 222  * Constants to be programmed into the Xena's registers, to configure
 223  * the XAUI.
 224  */
 225
 226 #define END_SIGN        0x0
 227 static const u64 herc_act_dtx_cfg[] = {
 228         /* Set address */
 229         0x8000051536750000ULL, 0x80000515367500E0ULL,
 230         /* Write data */
 231         0x8000051536750004ULL, 0x80000515367500E4ULL,
 232         /* Set address */
 233         0x80010515003F0000ULL, 0x80010515003F00E0ULL,
 234         /* Write data */
 235         0x80010515003F0004ULL, 0x80010515003F00E4ULL,
 236         /* Set address */
 237         0x801205150D440000ULL, 0x801205150D4400E0ULL,
 238         /* Write data */
 239         0x801205150D440004ULL, 0x801205150D4400E4ULL,
 240         /* Set address */
 241         0x80020515F2100000ULL, 0x80020515F21000E0ULL,
 242         /* Write data */
 243         0x80020515F2100004ULL, 0x80020515F21000E4ULL,
 244         /* Done */
 245         END_SIGN
 246 };
 247
 248 static const u64 xena_dtx_cfg[] = {
 249         /* Set address */
 250         0x8000051500000000ULL, 0x80000515000000E0ULL,
 251         /* Write data */
 252         0x80000515D9350004ULL, 0x80000515D93500E4ULL,
 253         /* Set address */
 254         0x8001051500000000ULL, 0x80010515000000E0ULL,
 255         /* Write data */
 256         0x80010515001E0004ULL, 0x80010515001E00E4ULL,
 257         /* Set address */
 258         0x8002051500000000ULL, 0x80020515000000E0ULL,
 259         /* Write data */
 260         0x80020515F2100004ULL, 0x80020515F21000E4ULL,
 261         END_SIGN
 262 };
 263
 264 /*
 265  * Constants for Fixing the MacAddress problem seen mostly on
 266  * Alpha machines.
 267  */
 268 static const u64 fix_mac[] = {
 269         0x0060000000000000ULL, 0x0060600000000000ULL,
 270         0x0040600000000000ULL, 0x0000600000000000ULL,
 271         0x0020600000000000ULL, 0x0060600000000000ULL,
 272         0x0020600000000000ULL, 0x0060600000000000ULL,
 273         0x0020600000000000ULL, 0x0060600000000000ULL,
 274         0x0020600000000000ULL, 0x0060600000000000ULL,
 275         0x0020600000000000ULL, 0x0060600000000000ULL,
 276         0x0020600000000000ULL, 0x0060600000000000ULL,
 277         0x0020600000000000ULL, 0x0060600000000000ULL,
 278         0x0020600000000000ULL, 0x0060600000000000ULL,
 279         0x0020600000000000ULL, 0x0060600000000000ULL,
 280         0x0020600000000000ULL, 0x0060600000000000ULL,
 281         0x0020600000000000ULL, 0x0000600000000000ULL,
 282         0x0040600000000000ULL, 0x0060600000000000ULL,
 283         END_SIGN
 284 };
 285
 286 /* Module Loadable parameters. */
 287 static unsigned int tx_fifo_num = 1;
 288 static unsigned int tx_fifo_len[MAX_TX_FIFOS] =
 289     {DEFAULT_FIFO_0_LEN, [1 ...(MAX_TX_FIFOS - 1)] = DEFAULT_FIFO_1_7_LEN};
 290 static unsigned int rx_ring_num = 1;
 291 static unsigned int rx_ring_sz[MAX_RX_RINGS] =
 292     {[0 ...(MAX_RX_RINGS - 1)] = SMALL_BLK_CNT};
 293 static unsigned int rts_frm_len[MAX_RX_RINGS] =
 294     {[0 ...(MAX_RX_RINGS - 1)] = 0 };
 295 static unsigned int rx_ring_mode = 1;
 296 static unsigned int use_continuous_tx_intrs = 1;
 297 static unsigned int rmac_pause_time = 0x100;
 298 static unsigned int mc_pause_threshold_q0q3 = 187;
 299 static unsigned int mc_pause_threshold_q4q7 = 187;
 300 static unsigned int shared_splits;
 301 static unsigned int tmac_util_period = 5;
 302 static unsigned int rmac_util_period = 5;
 303 static unsigned int bimodal = 0;
 304 static unsigned int l3l4hdr_size = 128;
 305 #ifndef CONFIG_S2IO_NAPI
 306 static unsigned int indicate_max_pkts;
 307 #endif
 308 /* Frequency of Rx desc syncs expressed as power of 2 */
 309 static unsigned int rxsync_frequency = 3;
 310 /* Interrupt type. Values can be 0(INTA), 1(MSI), 2(MSI_X) */
 311 static unsigned int intr_type = 0;
 312 /* Large receive offload feature */
 313 static unsigned int lro = 0;
 314 /* Max pkts to be aggregated by LRO at one time. If not specified,
 315  * aggregation happens until we hit max IP pkt size(64K)
 316  */
 317 static unsigned int lro_max_pkts = 0xFFFF;
 318
 319 /*
 320  * S2IO device table.
 321  * This table lists all the devices that this driver supports.
 322  */
 323 static struct pci_device_id s2io_tbl[] __devinitdata = {
 324         {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_WIN,
 325          PCI_ANY_ID, PCI_ANY_ID},
 326         {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_UNI,
 327          PCI_ANY_ID, PCI_ANY_ID},
 328         {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_WIN,
 329          PCI_ANY_ID, PCI_ANY_ID},
 330         {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_UNI,
 331          PCI_ANY_ID, PCI_ANY_ID},
 332         {0,}
 333 };
 334
 335 MODULE_DEVICE_TABLE(pci, s2io_tbl);
 336
 337 static struct pci_driver s2io_driver = {
 338       .name = "S2IO",
 339       .id_table = s2io_tbl,
 340       .probe = s2io_init_nic,
 341       .remove = __devexit_p(s2io_rem_nic),
 342 };
 343
 344 /* A simplifier macro used both by init and free shared_mem Fns(). */
 345 #define TXD_MEM_PAGE_CNT(len, per_each) ((len+per_each - 1) / per_each)
 346
 347 /**
 348  * init_shared_mem - Allocation and Initialization of Memory
 349  * @nic: Device private variable.
 350  * Description: The function allocates all the memory areas shared
 351  * between the NIC and the driver. This includes Tx descriptors,
 352  * Rx descriptors and the statistics block.
 353  */
 354
 355 static int init_shared_mem(struct s2io_nic *nic)
 356 {
 357         u32 size;
 358         void *tmp_v_addr, *tmp_v_addr_next;
 359         dma_addr_t tmp_p_addr, tmp_p_addr_next;
 360         RxD_block_t *pre_rxd_blk = NULL;
 361         int i, j, blk_cnt, rx_sz, tx_sz;
 362         int lst_size, lst_per_page;
 363         struct net_device *dev = nic->dev;
 364         unsigned long tmp;
 365         buffAdd_t *ba;
 366
 367         mac_info_t *mac_control;
 368         struct config_param *config;
 369
 370         mac_control = &nic->mac_control;
 371         config = &nic->config;
 372
 373
 374         /* Allocation and initialization of TXDLs in FIOFs */
 375         size = 0;
 376         for (i = 0; i < config->tx_fifo_num; i++) {
 377                 size += config->tx_cfg[i].fifo_len;
 378         }
 379         if (size > MAX_AVAILABLE_TXDS) {
 380                 DBG_PRINT(ERR_DBG, "%s: Requested TxDs too high, ",
 381                           __FUNCTION__);
 382                 DBG_PRINT(ERR_DBG, "Requested: %d, max supported: 8192\n", size);
 383                 return FAILURE;
 384         }
 385
 386         lst_size = (sizeof(TxD_t) * config->max_txds);
 387         tx_sz = lst_size * size;
 388         lst_per_page = PAGE_SIZE / lst_size;
 389
 390         for (i = 0; i < config->tx_fifo_num; i++) {
 391                 int fifo_len = config->tx_cfg[i].fifo_len;
 392                 int list_holder_size = fifo_len * sizeof(list_info_hold_t);
 393                 mac_control->fifos[i].list_info = kmalloc(list_holder_size,
 394                                                           GFP_KERNEL);
 395                 if (!mac_control->fifos[i].list_info) {
 396                         DBG_PRINT(ERR_DBG,
 397                                   "Malloc failed for list_info\n");
 398                         return -ENOMEM;
 399                 }
 400                 memset(mac_control->fifos[i].list_info, 0, list_holder_size);
 401         }
 402         for (i = 0; i < config->tx_fifo_num; i++) {
 403                 int page_num = TXD_MEM_PAGE_CNT(config->tx_cfg[i].fifo_len,
 404                                                 lst_per_page);
 405                 mac_control->fifos[i].tx_curr_put_info.offset = 0;
 406                 mac_control->fifos[i].tx_curr_put_info.fifo_len =
 407                     config->tx_cfg[i].fifo_len - 1;
 408                 mac_control->fifos[i].tx_curr_get_info.offset = 0;
 409                 mac_control->fifos[i].tx_curr_get_info.fifo_len =
 410                     config->tx_cfg[i].fifo_len - 1;
 411                 mac_control->fifos[i].fifo_no = i;
 412                 mac_control->fifos[i].nic = nic;
 413                 mac_control->fifos[i].max_txds = MAX_SKB_FRAGS + 2;
 414
 415                 for (j = 0; j < page_num; j++) {
 416                         int k = 0;
 417                         dma_addr_t tmp_p;
 418                         void *tmp_v;
 419                         tmp_v = pci_alloc_consistent(nic->pdev,
 420                                                      PAGE_SIZE, &tmp_p);
 421                         if (!tmp_v) {
 422                                 DBG_PRINT(ERR_DBG,
 423                                           "pci_alloc_consistent ");
 424                                 DBG_PRINT(ERR_DBG, "failed for TxDL\n");
 425                                 return -ENOMEM;
 426                         }
 427                         /* If we got a zero DMA address(can happen on
 428                          * certain platforms like PPC), reallocate.
 429                          * Store virtual address of page we don't want,
 430                          * to be freed later.
 431                          */
 432                         if (!tmp_p) {
 433                                 mac_control->zerodma_virt_addr = tmp_v;
 434                                 DBG_PRINT(INIT_DBG,
 435                                 "%s: Zero DMA address for TxDL. ", dev->name);
 436                                 DBG_PRINT(INIT_DBG,
 437                                 "Virtual address %p\n", tmp_v);
 438                                 tmp_v = pci_alloc_consistent(nic->pdev,
 439                                                      PAGE_SIZE, &tmp_p);
 440                                 if (!tmp_v) {
 441                                         DBG_PRINT(ERR_DBG,
 442                                           "pci_alloc_consistent ");
 443                                         DBG_PRINT(ERR_DBG, "failed for TxDL\n");
 444                                         return -ENOMEM;
 445                                 }
 446                         }
 447                         while (k < lst_per_page) {
 448                                 int l = (j * lst_per_page) + k;
 449                                 if (l == config->tx_cfg[i].fifo_len)
 450                                         break;
 451                                 mac_control->fifos[i].list_info[l].list_virt_addr =
 452                                     tmp_v + (k * lst_size);
 453                                 mac_control->fifos[i].list_info[l].list_phy_addr =
 454                                     tmp_p + (k * lst_size);
 455                                 k++;
 456                         }
 457                 }
 458         }
 459
 460         nic->ufo_in_band_v = kmalloc((sizeof(u64) * size), GFP_KERNEL);
 461         if (!nic->ufo_in_band_v)
 462                 return -ENOMEM;
 463
 464         /* Allocation and initialization of RXDs in Rings */
 465         size = 0;
 466         for (i = 0; i < config->rx_ring_num; i++) {
 467                 if (config->rx_cfg[i].num_rxd %
 468                     (rxd_count[nic->rxd_mode] + 1)) {
 469                         DBG_PRINT(ERR_DBG, "%s: RxD count of ", dev->name);
 470                         DBG_PRINT(ERR_DBG, "Ring%d is not a multiple of ",
 471                                   i);
 472                         DBG_PRINT(ERR_DBG, "RxDs per Block");
 473                         return FAILURE;
 474                 }
 475                 size += config->rx_cfg[i].num_rxd;
 476                 mac_control->rings[i].block_count =
 477                         config->rx_cfg[i].num_rxd /
 478                         (rxd_count[nic->rxd_mode] + 1 );
 479                 mac_control->rings[i].pkt_cnt = config->rx_cfg[i].num_rxd -
 480                         mac_control->rings[i].block_count;
 481         }
 482         if (nic->rxd_mode == RXD_MODE_1)
 483                 size = (size * (sizeof(RxD1_t)));
 484         else
 485                 size = (size * (sizeof(RxD3_t)));
 486         rx_sz = size;
 487
 488         for (i = 0; i < config->rx_ring_num; i++) {
 489                 mac_control->rings[i].rx_curr_get_info.block_index = 0;
 490                 mac_control->rings[i].rx_curr_get_info.offset = 0;
 491                 mac_control->rings[i].rx_curr_get_info.ring_len =
 492                     config->rx_cfg[i].num_rxd - 1;
 493                 mac_control->rings[i].rx_curr_put_info.block_index = 0;
 494                 mac_control->rings[i].rx_curr_put_info.offset = 0;
 495                 mac_control->rings[i].rx_curr_put_info.ring_len =
 496                     config->rx_cfg[i].num_rxd - 1;
 497                 mac_control->rings[i].nic = nic;
 498                 mac_control->rings[i].ring_no = i;
 499
 500                 blk_cnt = config->rx_cfg[i].num_rxd /
 501                                 (rxd_count[nic->rxd_mode] + 1);
 502                 /*  Allocating all the Rx blocks */
 503                 for (j = 0; j < blk_cnt; j++) {
 504                         rx_block_info_t *rx_blocks;
 505                         int l;
 506
 507                         rx_blocks = &mac_control->rings[i].rx_blocks[j];
 508                         size = SIZE_OF_BLOCK; //size is always page size
 509                         tmp_v_addr = pci_alloc_consistent(nic->pdev, size,
 510                                                           &tmp_p_addr);
 511                         if (tmp_v_addr == NULL) {
 512                                 /*
 513                                  * In case of failure, free_shared_mem()
 514                                  * is called, which should free any
 515                                  * memory that was alloced till the
 516                                  * failure happened.
 517                                  */
 518                                 rx_blocks->block_virt_addr = tmp_v_addr;
 519                                 return -ENOMEM;
 520                         }
 521                         memset(tmp_v_addr, 0, size);
 522                         rx_blocks->block_virt_addr = tmp_v_addr;
 523                         rx_blocks->block_dma_addr = tmp_p_addr;
 524                         rx_blocks->rxds = kmalloc(sizeof(rxd_info_t)*
 525                                                   rxd_count[nic->rxd_mode],
 526                                                   GFP_KERNEL);
 527                         for (l=0; l<rxd_count[nic->rxd_mode];l++) {
 528                                 rx_blocks->rxds[l].virt_addr =
 529                                         rx_blocks->block_virt_addr +
 530                                         (rxd_size[nic->rxd_mode] * l);
 531                                 rx_blocks->rxds[l].dma_addr =
 532                                         rx_blocks->block_dma_addr +
 533                                         (rxd_size[nic->rxd_mode] * l);
 534                         }
 535                 }
 536                 /* Interlinking all Rx Blocks */
 537                 for (j = 0; j < blk_cnt; j++) {
 538                         tmp_v_addr =
 539                                 mac_control->rings[i].rx_blocks[j].block_virt_addr;
 540                         tmp_v_addr_next =
 541                                 mac_control->rings[i].rx_blocks[(j + 1) %
 542                                               blk_cnt].block_virt_addr;
 543                         tmp_p_addr =
 544                                 mac_control->rings[i].rx_blocks[j].block_dma_addr;
 545                         tmp_p_addr_next =
 546                                 mac_control->rings[i].rx_blocks[(j + 1) %
 547                                               blk_cnt].block_dma_addr;
 548
 549                         pre_rxd_blk = (RxD_block_t *) tmp_v_addr;
 550                         pre_rxd_blk->reserved_2_pNext_RxD_block =
 551                             (unsigned long) tmp_v_addr_next;
 552                         pre_rxd_blk->pNext_RxD_Blk_physical =
 553                             (u64) tmp_p_addr_next;
 554                 }
 555         }
 556         if (nic->rxd_mode >= RXD_MODE_3A) {
 557                 /*
 558                  * Allocation of Storages for buffer addresses in 2BUFF mode
 559                  * and the buffers as well.
 560                  */
 561                 for (i = 0; i < config->rx_ring_num; i++) {
 562                         blk_cnt = config->rx_cfg[i].num_rxd /
 563                            (rxd_count[nic->rxd_mode]+ 1);
 564                         mac_control->rings[i].ba =
 565                                 kmalloc((sizeof(buffAdd_t *) * blk_cnt),
 566                                      GFP_KERNEL);
 567                         if (!mac_control->rings[i].ba)
 568                                 return -ENOMEM;
 569                         for (j = 0; j < blk_cnt; j++) {
 570                                 int k = 0;
 571                                 mac_control->rings[i].ba[j] =
 572                                         kmalloc((sizeof(buffAdd_t) *
 573                                                 (rxd_count[nic->rxd_mode] + 1)),
 574                                                 GFP_KERNEL);
 575                                 if (!mac_control->rings[i].ba[j])
 576                                         return -ENOMEM;
 577                                 while (k != rxd_count[nic->rxd_mode]) {
 578                                         ba = &mac_control->rings[i].ba[j][k];
 579
 580                                         ba->ba_0_org = (void *) kmalloc
 581                                             (BUF0_LEN + ALIGN_SIZE, GFP_KERNEL);
 582                                         if (!ba->ba_0_org)
 583                                                 return -ENOMEM;
 584                                         tmp = (unsigned long)ba->ba_0_org;
 585                                         tmp += ALIGN_SIZE;
 586                                         tmp &= ~((unsigned long) ALIGN_SIZE);
 587                                         ba->ba_0 = (void *) tmp;
 588
 589                                         ba->ba_1_org = (void *) kmalloc
 590                                             (BUF1_LEN + ALIGN_SIZE, GFP_KERNEL);
 591                                         if (!ba->ba_1_org)
 592                                                 return -ENOMEM;
 593                                         tmp = (unsigned long) ba->ba_1_org;
 594                                         tmp += ALIGN_SIZE;
 595                                         tmp &= ~((unsigned long) ALIGN_SIZE);
 596                                         ba->ba_1 = (void *) tmp;
 597                                         k++;
 598                                 }
 599                         }
 600                 }
 601         }
 602
 603         /* Allocation and initialization of Statistics block */
 604         size = sizeof(StatInfo_t);
 605         mac_control->stats_mem = pci_alloc_consistent
 606             (nic->pdev, size, &mac_control->stats_mem_phy);
 607
 608         if (!mac_control->stats_mem) {
 609                 /*
 610                  * In case of failure, free_shared_mem() is called, which
 611                  * should free any memory that was alloced till the
 612                  * failure happened.
 613                  */
 614                 return -ENOMEM;
 615         }
 616         mac_control->stats_mem_sz = size;
 617
 618         tmp_v_addr = mac_control->stats_mem;
 619         mac_control->stats_info = (StatInfo_t *) tmp_v_addr;
 620         memset(tmp_v_addr, 0, size);
 621         DBG_PRINT(INIT_DBG, "%s:Ring Mem PHY: 0x%llx\n", dev->name,
 622                   (unsigned long long) tmp_p_addr);
 623
 624         return SUCCESS;
 625 }
 626
 627 /**
 628  * free_shared_mem - Free the allocated Memory
 629  * @nic:  Device private variable.
 630  * Description: This function is to free all memory locations allocated by
 631  * the init_shared_mem() function and return it to the kernel.
 632  */
 633
 634 static void free_shared_mem(struct s2io_nic *nic)
 635 {
 636         int i, j, blk_cnt, size;
 637         void *tmp_v_addr;
 638         dma_addr_t tmp_p_addr;
 639         mac_info_t *mac_control;
 640         struct config_param *config;
 641         int lst_size, lst_per_page;
 642         struct net_device *dev = nic->dev;
 643
 644         if (!nic)
 645                 return;
 646
 647         mac_control = &nic->mac_control;
 648         config = &nic->config;
 649
 650         lst_size = (sizeof(TxD_t) * config->max_txds);
 651         lst_per_page = PAGE_SIZE / lst_size;
 652
 653         for (i = 0; i < config->tx_fifo_num; i++) {
 654                 int page_num = TXD_MEM_PAGE_CNT(config->tx_cfg[i].fifo_len,
 655                                                 lst_per_page);
 656                 for (j = 0; j < page_num; j++) {
 657                         int mem_blks = (j * lst_per_page);
 658                         if (!mac_control->fifos[i].list_info)
 659                                 return;
 660                         if (!mac_control->fifos[i].list_info[mem_blks].
 661                                  list_virt_addr)
 662                                 break;
 663                         pci_free_consistent(nic->pdev, PAGE_SIZE,
 664                                             mac_control->fifos[i].
 665                                             list_info[mem_blks].
 666                                             list_virt_addr,
 667                                             mac_control->fifos[i].
 668                                             list_info[mem_blks].
 669                                             list_phy_addr);
 670                 }
 671                 /* If we got a zero DMA address during allocation,
 672                  * free the page now
 673                  */
 674                 if (mac_control->zerodma_virt_addr) {
 675                         pci_free_consistent(nic->pdev, PAGE_SIZE,
 676                                             mac_control->zerodma_virt_addr,
 677                                             (dma_addr_t)0);
 678                         DBG_PRINT(INIT_DBG,
 679                                 "%s: Freeing TxDL with zero DMA addr. ",
 680                                 dev->name);
 681                         DBG_PRINT(INIT_DBG, "Virtual address %p\n",
 682                                 mac_control->zerodma_virt_addr);
 683                 }
 684                 kfree(mac_control->fifos[i].list_info);
 685         }
 686
 687         size = SIZE_OF_BLOCK;
 688         for (i = 0; i < config->rx_ring_num; i++) {
 689                 blk_cnt = mac_control->rings[i].block_count;
 690                 for (j = 0; j < blk_cnt; j++) {
 691                         tmp_v_addr = mac_control->rings[i].rx_blocks[j].
 692                                 block_virt_addr;
 693                         tmp_p_addr = mac_control->rings[i].rx_blocks[j].
 694                                 block_dma_addr;
 695                         if (tmp_v_addr == NULL)
 696                                 break;
 697                         pci_free_consistent(nic->pdev, size,
 698                                             tmp_v_addr, tmp_p_addr);
 699                         kfree(mac_control->rings[i].rx_blocks[j].rxds);
 700                 }
 701         }
 702
 703         if (nic->rxd_mode >= RXD_MODE_3A) {
 704                 /* Freeing buffer storage addresses in 2BUFF mode. */
 705                 for (i = 0; i < config->rx_ring_num; i++) {
 706                         blk_cnt = config->rx_cfg[i].num_rxd /
 707                             (rxd_count[nic->rxd_mode] + 1);
 708                         for (j = 0; j < blk_cnt; j++) {
 709                                 int k = 0;
 710                                 if (!mac_control->rings[i].ba[j])
 711                                         continue;
 712                                 while (k != rxd_count[nic->rxd_mode]) {
 713                                         buffAdd_t *ba =
 714                                                 &mac_control->rings[i].ba[j][k];
 715                                         kfree(ba->ba_0_org);
 716                                         kfree(ba->ba_1_org);
 717                                         k++;
 718                                 }
 719                                 kfree(mac_control->rings[i].ba[j]);
 720                         }
 721                         kfree(mac_control->rings[i].ba);
 722                 }
 723         }
 724
 725         if (mac_control->stats_mem) {
 726                 pci_free_consistent(nic->pdev,
 727                                     mac_control->stats_mem_sz,
 728                                     mac_control->stats_mem,
 729                                     mac_control->stats_mem_phy);
 730         }
 731         if (nic->ufo_in_band_v)
 732                 kfree(nic->ufo_in_band_v);
 733 }
 734
 735 /**
 736  * s2io_verify_pci_mode -
 737  */
 738
 739 static int s2io_verify_pci_mode(nic_t *nic)
 740 {
 741         XENA_dev_config_t __iomem *bar0 = nic->bar0;
 742         register u64 val64 = 0;
 743         int     mode;
 744
 745         val64 = readq(&bar0->pci_mode);
 746         mode = (u8)GET_PCI_MODE(val64);
 747
 748         if ( val64 & PCI_MODE_UNKNOWN_MODE)
 749                 return -1;      /* Unknown PCI mode */
 750         return mode;
 751 }
 752
 753 #define NEC_VENID   0x1033
 754 #define NEC_DEVID   0x0125
 755 static int s2io_on_nec_bridge(struct pci_dev *s2io_pdev)
 756 {
 757         struct pci_dev *tdev = NULL;
 758         while ((tdev = pci_find_device(PCI_ANY_ID, PCI_ANY_ID, tdev)) != NULL) {
 759                 if ((tdev->vendor == NEC_VENID) && (tdev->device == NEC_DEVID)){
 760                         if (tdev->bus == s2io_pdev->bus->parent)
 761                                 return 1;
 762                 }
 763         }
 764         return 0;
 765 }
 766
 767 int bus_speed[8] = {33, 133, 133, 200, 266, 133, 200, 266};
 768 /**
 769  * s2io_print_pci_mode -
 770  */
 771 static int s2io_print_pci_mode(nic_t *nic)
 772 {
 773         XENA_dev_config_t __iomem *bar0 = nic->bar0;
 774         register u64 val64 = 0;
 775         int     mode;
 776         struct config_param *config = &nic->config;
 777
 778         val64 = readq(&bar0->pci_mode);
 779         mode = (u8)GET_PCI_MODE(val64);
 780
 781         if ( val64 & PCI_MODE_UNKNOWN_MODE)
 782                 return -1;      /* Unknown PCI mode */
 783
 784         config->bus_speed = bus_speed[mode];
 785
 786         if (s2io_on_nec_bridge(nic->pdev)) {
 787                 DBG_PRINT(ERR_DBG, "%s: Device is on PCI-E bus\n",
 788                                                         nic->dev->name);
 789                 return mode;
 790         }
 791
 792         if (val64 & PCI_MODE_32_BITS) {
 793                 DBG_PRINT(ERR_DBG, "%s: Device is on 32 bit ", nic->dev->name);
 794         } else {
 795                 DBG_PRINT(ERR_DBG, "%s: Device is on 64 bit ", nic->dev->name);
 796         }
 797
 798         switch(mode) {
 799                 case PCI_MODE_PCI_33:
 800                         DBG_PRINT(ERR_DBG, "33MHz PCI bus\n");
 801                         break;
 802                 case PCI_MODE_PCI_66:
 803                         DBG_PRINT(ERR_DBG, "66MHz PCI bus\n");
 804                         break;
 805                 case PCI_MODE_PCIX_M1_66:
 806                         DBG_PRINT(ERR_DBG, "66MHz PCIX(M1) bus\n");
 807                         break;
 808                 case PCI_MODE_PCIX_M1_100:
 809                         DBG_PRINT(ERR_DBG, "100MHz PCIX(M1) bus\n");
 810                         break;
 811                 case PCI_MODE_PCIX_M1_133:
 812                         DBG_PRINT(ERR_DBG, "133MHz PCIX(M1) bus\n");
 813                         break;
 814                 case PCI_MODE_PCIX_M2_66:
 815                         DBG_PRINT(ERR_DBG, "133MHz PCIX(M2) bus\n");
 816                         break;
 817                 case PCI_MODE_PCIX_M2_100:
 818                         DBG_PRINT(ERR_DBG, "200MHz PCIX(M2) bus\n");
 819                         break;
 820                 case PCI_MODE_PCIX_M2_133:
 821                         DBG_PRINT(ERR_DBG, "266MHz PCIX(M2) bus\n");
 822                         break;
 823                 default:
 824                         return -1;      /* Unsupported bus speed */
 825         }
 826
 827         return mode;
 828 }
 829
 830 /**
 831  *  init_nic - Initialization of hardware
 832  *  @nic: device peivate variable
 833  *  Description: The function sequentially configures every block
 834  *  of the H/W from their reset values.
 835  *  Return Value:  SUCCESS on success and
 836  *  '-1' on failure (endian settings incorrect).
 837  */
 838
 839 static int init_nic(struct s2io_nic *nic)
 840 {
 841         XENA_dev_config_t __iomem *bar0 = nic->bar0;
 842         struct net_device *dev = nic->dev;
 843         register u64 val64 = 0;
 844         void __iomem *add;
 845         u32 time;
 846         int i, j;
 847         mac_info_t *mac_control;
 848         struct config_param *config;
 849         int dtx_cnt = 0;
 850         unsigned long long mem_share;
 851         int mem_size;
 852
 853         mac_control = &nic->mac_control;
 854         config = &nic->config;
 855
 856         /* to set the swapper controle on the card */
 857         if(s2io_set_swapper(nic)) {
 858                 DBG_PRINT(ERR_DBG,"ERROR: Setting Swapper failed\n");
 859                 return -1;
 860         }
 861
 862         /*
 863          * Herc requires EOI to be removed from reset before XGXS, so..
 864          */
 865         if (nic->device_type & XFRAME_II_DEVICE) {
 866                 val64 = 0xA500000000ULL;
 867                 writeq(val64, &bar0->sw_reset);
 868                 msleep(500);
 869                 val64 = readq(&bar0->sw_reset);
 870         }
 871
 872         /* Remove XGXS from reset state */
 873         val64 = 0;
 874         writeq(val64, &bar0->sw_reset);
 875         msleep(500);
 876         val64 = readq(&bar0->sw_reset);
 877
 878         /*  Enable Receiving broadcasts */
 879         add = &bar0->mac_cfg;
 880         val64 = readq(&bar0->mac_cfg);
 881         val64 |= MAC_RMAC_BCAST_ENABLE;
 882         writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
 883         writel((u32) val64, add);
 884         writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
 885         writel((u32) (val64 >> 32), (add + 4));
 886
 887         /* Read registers in all blocks */
 888         val64 = readq(&bar0->mac_int_mask);
 889         val64 = readq(&bar0->mc_int_mask);
 890         val64 = readq(&bar0->xgxs_int_mask);
 891
 892         /*  Set MTU */
 893         val64 = dev->mtu;
 894         writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len);
 895
 896         if (nic->device_type & XFRAME_II_DEVICE) {
 897                 while (herc_act_dtx_cfg[dtx_cnt] != END_SIGN) {
 898                         SPECIAL_REG_WRITE(herc_act_dtx_cfg[dtx_cnt],
 899                                           &bar0->dtx_control, UF);
 900                         if (dtx_cnt & 0x1)
 901                                 msleep(1); /* Necessary!! */
 902                         dtx_cnt++;
 903                 }
 904         } else {
 905                 while (xena_dtx_cfg[dtx_cnt] != END_SIGN) {
 906                         SPECIAL_REG_WRITE(xena_dtx_cfg[dtx_cnt],
 907                                           &bar0->dtx_control, UF);
 908                         val64 = readq(&bar0->dtx_control);
 909                         dtx_cnt++;
 910                 }
 911         }
 912
 913         /*  Tx DMA Initialization */
 914         val64 = 0;
 915         writeq(val64, &bar0->tx_fifo_partition_0);
 916         writeq(val64, &bar0->tx_fifo_partition_1);
 917         writeq(val64, &bar0->tx_fifo_partition_2);
 918         writeq(val64, &bar0->tx_fifo_partition_3);
 919
 920
 921         for (i = 0, j = 0; i < config->tx_fifo_num; i++) {
 922                 val64 |=
 923                     vBIT(config->tx_cfg[i].fifo_len - 1, ((i * 32) + 19),
 924                          13) | vBIT(config->tx_cfg[i].fifo_priority,
 925                                     ((i * 32) + 5), 3);
 926
 927                 if (i == (config->tx_fifo_num - 1)) {
 928                         if (i % 2 == 0)
 929                                 i++;
 930                 }
 931
 932                 switch (i) {
 933                 case 1:
 934                         writeq(val64, &bar0->tx_fifo_partition_0);
 935                         val64 = 0;
 936                         break;
 937                 case 3:
 938                         writeq(val64, &bar0->tx_fifo_partition_1);
 939                         val64 = 0;
 940                         break;
 941                 case 5:
 942                         writeq(val64, &bar0->tx_fifo_partition_2);
 943                         val64 = 0;
 944                         break;
 945                 case 7:
 946                         writeq(val64, &bar0->tx_fifo_partition_3);
 947                         break;
 948                 }
 949         }
 950
 951         /* Enable Tx FIFO partition 0. */
 952         val64 = readq(&bar0->tx_fifo_partition_0);
 953         val64 |= BIT(0);        /* To enable the FIFO partition. */
 954         writeq(val64, &bar0->tx_fifo_partition_0);
 955
 956         /*
 957          * Disable 4 PCCs for Xena1, 2 and 3 as per H/W bug
 958          * SXE-008 TRANSMIT DMA ARBITRATION ISSUE.
 959          */
 960         if ((nic->device_type == XFRAME_I_DEVICE) &&
 961                 (get_xena_rev_id(nic->pdev) < 4))
 962                 writeq(PCC_ENABLE_FOUR, &bar0->pcc_enable);
 963
 964         val64 = readq(&bar0->tx_fifo_partition_0);
 965         DBG_PRINT(INIT_DBG, "Fifo partition at: 0x%p is: 0x%llx\n",
 966                   &bar0->tx_fifo_partition_0, (unsigned long long) val64);
 967
 968         /*
 969          * Initialization of Tx_PA_CONFIG register to ignore packet
 970          * integrity checking.
 971          */
 972         val64 = readq(&bar0->tx_pa_cfg);
 973         val64 |= TX_PA_CFG_IGNORE_FRM_ERR | TX_PA_CFG_IGNORE_SNAP_OUI |
 974             TX_PA_CFG_IGNORE_LLC_CTRL | TX_PA_CFG_IGNORE_L2_ERR;
 975         writeq(val64, &bar0->tx_pa_cfg);
 976
 977         /* Rx DMA intialization. */
 978         val64 = 0;
 979         for (i = 0; i < config->rx_ring_num; i++) {
 980                 val64 |=
 981                     vBIT(config->rx_cfg[i].ring_priority, (5 + (i * 8)),
 982                          3);
 983         }
 984         writeq(val64, &bar0->rx_queue_priority);
 985
 986         /*
 987          * Allocating equal share of memory to all the
 988          * configured Rings.
 989          */
 990         val64 = 0;
 991         if (nic->device_type & XFRAME_II_DEVICE)
 992                 mem_size = 32;
 993         else
 994                 mem_size = 64;
 995
 996         for (i = 0; i < config->rx_ring_num; i++) {
 997                 switch (i) {
 998                 case 0:
 999                         mem_share = (mem_size / config->rx_ring_num +
1000                                      mem_size % config->rx_ring_num);
1001                         val64 |= RX_QUEUE_CFG_Q0_SZ(mem_share);
1002                         continue;
1003                 case 1:
1004                         mem_share = (mem_size / config->rx_ring_num);
1005                         val64 |= RX_QUEUE_CFG_Q1_SZ(mem_share);
1006                         continue;
1007                 case 2:
1008                         mem_share = (mem_size / config->rx_ring_num);
1009                         val64 |= RX_QUEUE_CFG_Q2_SZ(mem_share);
1010                         continue;
1011                 case 3:
1012                         mem_share = (mem_size / config->rx_ring_num);
1013                         val64 |= RX_QUEUE_CFG_Q3_SZ(mem_share);
1014                         continue;
1015                 case 4:
1016                         mem_share = (mem_size / config->rx_ring_num);
1017                         val64 |= RX_QUEUE_CFG_Q4_SZ(mem_share);
1018                         continue;
1019                 case 5:
1020                         mem_share = (mem_size / config->rx_ring_num);
1021                         val64 |= RX_QUEUE_CFG_Q5_SZ(mem_share);
1022                         continue;
1023                 case 6:
1024                         mem_share = (mem_size / config->rx_ring_num);
1025                         val64 |= RX_QUEUE_CFG_Q6_SZ(mem_share);
1026                         continue;
1027                 case 7:
1028                         mem_share = (mem_size / config->rx_ring_num);
1029                         val64 |= RX_QUEUE_CFG_Q7_SZ(mem_share);
1030                         continue;
1031                 }
1032         }
1033         writeq(val64, &bar0->rx_queue_cfg);
1034
1035         /*
1036          * Filling Tx round robin registers
1037          * as per the number of FIFOs
1038          */
1039         switch (config->tx_fifo_num) {
1040         case 1:
1041                 val64 = 0x0000000000000000ULL;
1042                 writeq(val64, &bar0->tx_w_round_robin_0);
1043                 writeq(val64, &bar0->tx_w_round_robin_1);
1044                 writeq(val64, &bar0->tx_w_round_robin_2);
1045                 writeq(val64, &bar0->tx_w_round_robin_3);
1046                 writeq(val64, &bar0->tx_w_round_robin_4);
1047                 break;
1048         case 2:
1049                 val64 = 0x0000010000010000ULL;
1050                 writeq(val64, &bar0->tx_w_round_robin_0);
1051                 val64 = 0x0100000100000100ULL;
1052                 writeq(val64, &bar0->tx_w_round_robin_1);
1053                 val64 = 0x0001000001000001ULL;
1054                 writeq(val64, &bar0->tx_w_round_robin_2);
1055                 val64 = 0x0000010000010000ULL;
1056                 writeq(val64, &bar0->tx_w_round_robin_3);
1057                 val64 = 0x0100000000000000ULL;
1058                 writeq(val64, &bar0->tx_w_round_robin_4);
1059                 break;
1060         case 3:
1061                 val64 = 0x0001000102000001ULL;
1062                 writeq(val64, &bar0->tx_w_round_robin_0);
1063                 val64 = 0x0001020000010001ULL;
1064                 writeq(val64, &bar0->tx_w_round_robin_1);
1065                 val64 = 0x0200000100010200ULL;
1066                 writeq(val64, &bar0->tx_w_round_robin_2);
1067                 val64 = 0x0001000102000001ULL;
1068                 writeq(val64, &bar0->tx_w_round_robin_3);
1069                 val64 = 0x0001020000000000ULL;
1070                 writeq(val64, &bar0->tx_w_round_robin_4);
1071                 break;
1072         case 4:
1073                 val64 = 0x0001020300010200ULL;
1074                 writeq(val64, &bar0->tx_w_round_robin_0);
1075                 val64 = 0x0100000102030001ULL;
1076                 writeq(val64, &bar0->tx_w_round_robin_1);
1077                 val64 = 0x0200010000010203ULL;
1078                 writeq(val64, &bar0->tx_w_round_robin_2);
1079                 val64 = 0x0001020001000001ULL;
1080                 writeq(val64, &bar0->tx_w_round_robin_3);
1081                 val64 = 0x0203000100000000ULL;
1082                 writeq(val64, &bar0->tx_w_round_robin_4);
1083                 break;
1084         case 5:
1085                 val64 = 0x0001000203000102ULL;
1086                 writeq(val64, &bar0->tx_w_round_robin_0);
1087                 val64 = 0x0001020001030004ULL;
1088                 writeq(val64, &bar0->tx_w_round_robin_1);
1089                 val64 = 0x0001000203000102ULL;
1090                 writeq(val64, &bar0->tx_w_round_robin_2);
1091                 val64 = 0x0001020001030004ULL;
1092                 writeq(val64, &bar0->tx_w_round_robin_3);
1093                 val64 = 0x0001000000000000ULL;
1094                 writeq(val64, &bar0->tx_w_round_robin_4);
1095                 break;
1096         case 6:
1097                 val64 = 0x0001020304000102ULL;
1098                 writeq(val64, &bar0->tx_w_round_robin_0);
1099                 val64 = 0x0304050001020001ULL;
1100                 writeq(val64, &bar0->tx_w_round_robin_1);
1101                 val64 = 0x0203000100000102ULL;
1102                 writeq(val64, &bar0->tx_w_round_robin_2);
1103                 val64 = 0x0304000102030405ULL;
1104                 writeq(val64, &bar0->tx_w_round_robin_3);
1105                 val64 = 0x0001000200000000ULL;
1106                 writeq(val64, &bar0->tx_w_round_robin_4);
1107                 break;
1108         case 7:
1109                 val64 = 0x0001020001020300ULL;
1110                 writeq(val64, &bar0->tx_w_round_robin_0);
1111                 val64 = 0x0102030400010203ULL;
1112                 writeq(val64, &bar0->tx_w_round_robin_1);
1113                 val64 = 0x0405060001020001ULL;
1114                 writeq(val64, &bar0->tx_w_round_robin_2);
1115                 val64 = 0x0304050000010200ULL;
1116                 writeq(val64, &bar0->tx_w_round_robin_3);
1117                 val64 = 0x0102030000000000ULL;
1118                 writeq(val64, &bar0->tx_w_round_robin_4);
1119                 break;
1120         case 8:
1121                 val64 = 0x0001020300040105ULL;
1122                 writeq(val64, &bar0->tx_w_round_robin_0);
1123                 val64 = 0x0200030106000204ULL;
1124                 writeq(val64, &bar0->tx_w_round_robin_1);
1125                 val64 = 0x0103000502010007ULL;
1126                 writeq(val64, &bar0->tx_w_round_robin_2);
1127                 val64 = 0x0304010002060500ULL;
1128                 writeq(val64, &bar0->tx_w_round_robin_3);
1129                 val64 = 0x0103020400000000ULL;
1130                 writeq(val64, &bar0->tx_w_round_robin_4);
1131                 break;
1132         }
1133
1134         /* Filling the Rx round robin registers as per the
1135          * number of Rings and steering based on QoS.
1136          */
1137         switch (config->rx_ring_num) {
1138         case 1:
1139                 val64 = 0x8080808080808080ULL;
1140                 writeq(val64, &bar0->rts_qos_steering);
1141                 break;
1142         case 2:
1143                 val64 = 0x0000010000010000ULL;
1144                 writeq(val64, &bar0->rx_w_round_robin_0);
1145                 val64 = 0x0100000100000100ULL;
1146                 writeq(val64, &bar0->rx_w_round_robin_1);
1147                 val64 = 0x0001000001000001ULL;
1148                 writeq(val64, &bar0->rx_w_round_robin_2);
1149                 val64 = 0x0000010000010000ULL;
1150                 writeq(val64, &bar0->rx_w_round_robin_3);
1151                 val64 = 0x0100000000000000ULL;
1152                 writeq(val64, &bar0->rx_w_round_robin_4);
1153
1154                 val64 = 0x8080808040404040ULL;
1155                 writeq(val64, &bar0->rts_qos_steering);
1156                 break;
1157         case 3:
1158                 val64 = 0x0001000102000001ULL;
1159                 writeq(val64, &bar0->rx_w_round_robin_0);
1160                 val64 = 0x0001020000010001ULL;
1161                 writeq(val64, &bar0->rx_w_round_robin_1);
1162                 val64 = 0x0200000100010200ULL;
1163                 writeq(val64, &bar0->rx_w_round_robin_2);
1164                 val64 = 0x0001000102000001ULL;
1165                 writeq(val64, &bar0->rx_w_round_robin_3);
1166                 val64 = 0x0001020000000000ULL;
1167                 writeq(val64, &bar0->rx_w_round_robin_4);
1168
1169                 val64 = 0x8080804040402020ULL;
1170                 writeq(val64, &bar0->rts_qos_steering);
1171                 break;
1172         case 4:
1173                 val64 = 0x0001020300010200ULL;
1174                 writeq(val64, &bar0->rx_w_round_robin_0);
1175                 val64 = 0x0100000102030001ULL;
1176                 writeq(val64, &bar0->rx_w_round_robin_1);
1177                 val64 = 0x0200010000010203ULL;
1178                 writeq(val64, &bar0->rx_w_round_robin_2);
1179                 val64 = 0x0001020001000001ULL;
1180                 writeq(val64, &bar0->rx_w_round_robin_3);
1181                 val64 = 0x0203000100000000ULL;
1182                 writeq(val64, &bar0->rx_w_round_robin_4);
1183
1184                 val64 = 0x8080404020201010ULL;
1185                 writeq(val64, &bar0->rts_qos_steering);
1186                 break;
1187         case 5:
1188                 val64 = 0x0001000203000102ULL;
1189                 writeq(val64, &bar0->rx_w_round_robin_0);
1190                 val64 = 0x0001020001030004ULL;
1191                 writeq(val64, &bar0->rx_w_round_robin_1);
1192                 val64 = 0x0001000203000102ULL;
1193                 writeq(val64, &bar0->rx_w_round_robin_2);
1194                 val64 = 0x0001020001030004ULL;
1195                 writeq(val64, &bar0->rx_w_round_robin_3);
1196                 val64 = 0x0001000000000000ULL;
1197                 writeq(val64, &bar0->rx_w_round_robin_4);
1198
1199                 val64 = 0x8080404020201008ULL;
1200                 writeq(val64, &bar0->rts_qos_steering);
1201                 break;
1202         case 6:
1203                 val64 = 0x0001020304000102ULL;
1204                 writeq(val64, &bar0->rx_w_round_robin_0);
1205                 val64 = 0x0304050001020001ULL;
1206                 writeq(val64, &bar0->rx_w_round_robin_1);
1207                 val64 = 0x0203000100000102ULL;
1208                 writeq(val64, &bar0->rx_w_round_robin_2);
1209                 val64 = 0x0304000102030405ULL;
1210                 writeq(val64, &bar0->rx_w_round_robin_3);
1211                 val64 = 0x0001000200000000ULL;
1212                 writeq(val64, &bar0->rx_w_round_robin_4);
1213
1214                 val64 = 0x8080404020100804ULL;
1215                 writeq(val64, &bar0->rts_qos_steering);
1216                 break;
1217         case 7:
1218                 val64 = 0x0001020001020300ULL;
1219                 writeq(val64, &bar0->rx_w_round_robin_0);
1220                 val64 = 0x0102030400010203ULL;
1221                 writeq(val64, &bar0->rx_w_round_robin_1);
1222                 val64 = 0x0405060001020001ULL;
1223                 writeq(val64, &bar0->rx_w_round_robin_2);
1224                 val64 = 0x0304050000010200ULL;
1225                 writeq(val64, &bar0->rx_w_round_robin_3);
1226                 val64 = 0x0102030000000000ULL;
1227                 writeq(val64, &bar0->rx_w_round_robin_4);
1228
1229                 val64 = 0x8080402010080402ULL;
1230                 writeq(val64, &bar0->rts_qos_steering);
1231                 break;
1232         case 8:
1233                 val64 = 0x0001020300040105ULL;
1234                 writeq(val64, &bar0->rx_w_round_robin_0);
1235                 val64 = 0x0200030106000204ULL;
1236                 writeq(val64, &bar0->rx_w_round_robin_1);
1237                 val64 = 0x0103000502010007ULL;
1238                 writeq(val64, &bar0->rx_w_round_robin_2);
1239                 val64 = 0x0304010002060500ULL;
1240                 writeq(val64, &bar0->rx_w_round_robin_3);
1241                 val64 = 0x0103020400000000ULL;
1242                 writeq(val64, &bar0->rx_w_round_robin_4);
1243
1244                 val64 = 0x8040201008040201ULL;
1245                 writeq(val64, &bar0->rts_qos_steering);
1246                 break;
1247         }
1248
1249         /* UDP Fix */
1250         val64 = 0;
1251         for (i = 0; i < 8; i++)
1252                 writeq(val64, &bar0->rts_frm_len_n[i]);
1253
1254         /* Set the default rts frame length for the rings configured */
1255         val64 = MAC_RTS_FRM_LEN_SET(dev->mtu+22);
1256         for (i = 0 ; i < config->rx_ring_num ; i++)
1257                 writeq(val64, &bar0->rts_frm_len_n[i]);
1258
1259         /* Set the frame length for the configured rings
1260          * desired by the user
1261          */
1262         for (i = 0; i < config->rx_ring_num; i++) {
1263                 /* If rts_frm_len[i] == 0 then it is assumed that user not
1264                  * specified frame length steering.
1265                  * If the user provides the frame length then program
1266                  * the rts_frm_len register for those values or else
1267                  * leave it as it is.
1268                  */
1269                 if (rts_frm_len[i] != 0) {
1270                         writeq(MAC_RTS_FRM_LEN_SET(rts_frm_len[i]),
1271                                 &bar0->rts_frm_len_n[i]);
1272                 }
1273         }
1274
1275         /* Program statistics memory */
1276         writeq(mac_control->stats_mem_phy, &bar0->stat_addr);
1277
1278         if (nic->device_type == XFRAME_II_DEVICE) {
1279                 val64 = STAT_BC(0x320);
1280                 writeq(val64, &bar0->stat_byte_cnt);
1281         }
1282
1283         /*
1284          * Initializing the sampling rate for the device to calculate the
1285          * bandwidth utilization.
1286          */
1287         val64 = MAC_TX_LINK_UTIL_VAL(tmac_util_period) |
1288             MAC_RX_LINK_UTIL_VAL(rmac_util_period);
1289         writeq(val64, &bar0->mac_link_util);
1290
1291
1292         /*
1293          * Initializing the Transmit and Receive Traffic Interrupt
1294          * Scheme.
1295          */
1296         /*
1297          * TTI Initialization. Default Tx timer gets us about
1298          * 250 interrupts per sec. Continuous interrupts are enabled
1299          * by default.
1300          */
1301         if (nic->device_type == XFRAME_II_DEVICE) {
1302                 int count = (nic->config.bus_speed * 125)/2;
1303                 val64 = TTI_DATA1_MEM_TX_TIMER_VAL(count);
1304         } else {
1305
1306                 val64 = TTI_DATA1_MEM_TX_TIMER_VAL(0x2078);
1307         }
1308         val64 |= TTI_DATA1_MEM_TX_URNG_A(0xA) |
1309             TTI_DATA1_MEM_TX_URNG_B(0x10) |
1310             TTI_DATA1_MEM_TX_URNG_C(0x30) | TTI_DATA1_MEM_TX_TIMER_AC_EN;
1311                 if (use_continuous_tx_intrs)
1312                         val64 |= TTI_DATA1_MEM_TX_TIMER_CI_EN;
1313         writeq(val64, &bar0->tti_data1_mem);
1314
1315         val64 = TTI_DATA2_MEM_TX_UFC_A(0x10) |
1316             TTI_DATA2_MEM_TX_UFC_B(0x20) |
1317             TTI_DATA2_MEM_TX_UFC_C(0x70) | TTI_DATA2_MEM_TX_UFC_D(0x80);
1318         writeq(val64, &bar0->tti_data2_mem);
1319
1320         val64 = TTI_CMD_MEM_WE | TTI_CMD_MEM_STROBE_NEW_CMD;
1321         writeq(val64, &bar0->tti_command_mem);
1322
1323         /*
1324          * Once the operation completes, the Strobe bit of the command
1325          * register will be reset. We poll for this particular condition
1326          * We wait for a maximum of 500ms for the operation to complete,
1327          * if it's not complete by then we return error.
1328          */
1329         time = 0;
1330         while (TRUE) {
1331                 val64 = readq(&bar0->tti_command_mem);
1332                 if (!(val64 & TTI_CMD_MEM_STROBE_NEW_CMD)) {
1333                         break;
1334                 }
1335                 if (time > 10) {
1336                         DBG_PRINT(ERR_DBG, "%s: TTI init Failed\n",
1337                                   dev->name);
1338                         return -1;
1339                 }
1340                 msleep(50);
1341                 time++;
1342         }
1343
1344         if (nic->config.bimodal) {
1345                 int k = 0;
1346                 for (k = 0; k < config->rx_ring_num; k++) {
1347                         val64 = TTI_CMD_MEM_WE | TTI_CMD_MEM_STROBE_NEW_CMD;
1348                         val64 |= TTI_CMD_MEM_OFFSET(0x38+k);
1349                         writeq(val64, &bar0->tti_command_mem);
1350
1351                 /*
1352                  * Once the operation completes, the Strobe bit of the command
1353                  * register will be reset. We poll for this particular condition
1354                  * We wait for a maximum of 500ms for the operation to complete,
1355                  * if it's not complete by then we return error.
1356                 */
1357                         time = 0;
1358                         while (TRUE) {
1359                                 val64 = readq(&bar0->tti_command_mem);
1360                                 if (!(val64 & TTI_CMD_MEM_STROBE_NEW_CMD)) {
1361                                         break;
1362                                 }
1363                                 if (time > 10) {
1364                                         DBG_PRINT(ERR_DBG,
1365                                                 "%s: TTI init Failed\n",
1366                                         dev->name);
1367                                         return -1;
1368                                 }
1369                                 time++;
1370                                 msleep(50);
1371                         }
1372                 }
1373         } else {
1374
1375                 /* RTI Initialization */
1376                 if (nic->device_type == XFRAME_II_DEVICE) {
1377                         /*
1378                          * Programmed to generate Apprx 500 Intrs per
1379                          * second
1380                          */
1381                         int count = (nic->config.bus_speed * 125)/4;
1382                         val64 = RTI_DATA1_MEM_RX_TIMER_VAL(count);
1383                 } else {
1384                         val64 = RTI_DATA1_MEM_RX_TIMER_VAL(0xFFF);
1385                 }
1386                 val64 |= RTI_DATA1_MEM_RX_URNG_A(0xA) |
1387                     RTI_DATA1_MEM_RX_URNG_B(0x10) |
1388                     RTI_DATA1_MEM_RX_URNG_C(0x30) | RTI_DATA1_MEM_RX_TIMER_AC_EN;
1389
1390                 writeq(val64, &bar0->rti_data1_mem);
1391
1392                 val64 = RTI_DATA2_MEM_RX_UFC_A(0x1) |
1393                     RTI_DATA2_MEM_RX_UFC_B(0x2) ;
1394                 if (nic->intr_type == MSI_X)
1395                     val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x20) | \
1396                                 RTI_DATA2_MEM_RX_UFC_D(0x40));
1397                 else
1398                     val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x40) | \
1399                                 RTI_DATA2_MEM_RX_UFC_D(0x80));
1400                 writeq(val64, &bar0->rti_data2_mem);
1401
1402                 for (i = 0; i < config->rx_ring_num; i++) {
1403                         val64 = RTI_CMD_MEM_WE | RTI_CMD_MEM_STROBE_NEW_CMD
1404                                         | RTI_CMD_MEM_OFFSET(i);
1405                         writeq(val64, &bar0->rti_command_mem);
1406
1407                         /*
1408                          * Once the operation completes, the Strobe bit of the
1409                          * command register will be reset. We poll for this
1410                          * particular condition. We wait for a maximum of 500ms
1411                          * for the operation to complete, if it's not complete
1412                          * by then we return error.
1413                          */
1414                         time = 0;
1415                         while (TRUE) {
1416                                 val64 = readq(&bar0->rti_command_mem);
1417                                 if (!(val64 & RTI_CMD_MEM_STROBE_NEW_CMD)) {
1418                                         break;
1419                                 }
1420                                 if (time > 10) {
1421                                         DBG_PRINT(ERR_DBG, "%s: RTI init Failed\n",
1422                                                   dev->name);
1423                                         return -1;
1424                                 }
1425                                 time++;
1426                                 msleep(50);
1427                         }
1428                 }
1429         }
1430
1431         /*
1432          * Initializing proper values as Pause threshold into all
1433          * the 8 Queues on Rx side.
1434          */
1435         writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q0q3);
1436         writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q4q7);
1437
1438         /* Disable RMAC PAD STRIPPING */
1439         add = &bar0->mac_cfg;
1440         val64 = readq(&bar0->mac_cfg);
1441         val64 &= ~(MAC_CFG_RMAC_STRIP_PAD);
1442         writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1443         writel((u32) (val64), add);
1444         writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1445         writel((u32) (val64 >> 32), (add + 4));
1446         val64 = readq(&bar0->mac_cfg);
1447
1448         /* Enable FCS stripping by adapter */
1449         add = &bar0->mac_cfg;
1450         val64 = readq(&bar0->mac_cfg);
1451         val64 |= MAC_CFG_RMAC_STRIP_FCS;
1452         if (nic->device_type == XFRAME_II_DEVICE)
1453                 writeq(val64, &bar0->mac_cfg);
1454         else {
1455                 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1456                 writel((u32) (val64), add);
1457                 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1458                 writel((u32) (val64 >> 32), (add + 4));
1459         }
1460
1461         /*
1462          * Set the time value to be inserted in the pause frame
1463          * generated by xena.
1464          */
1465         val64 = readq(&bar0->rmac_pause_cfg);
1466         val64 &= ~(RMAC_PAUSE_HG_PTIME(0xffff));
1467         val64 |= RMAC_PAUSE_HG_PTIME(nic->mac_control.rmac_pause_time);
1468         writeq(val64, &bar0->rmac_pause_cfg);
1469
1470         /*
1471          * Set the Threshold Limit for Generating the pause frame
1472          * If the amount of data in any Queue exceeds ratio of
1473          * (mac_control.mc_pause_threshold_q0q3 or q4q7)/256
1474          * pause frame is generated
1475          */
1476         val64 = 0;
1477         for (i = 0; i < 4; i++) {
1478                 val64 |=
1479                     (((u64) 0xFF00 | nic->mac_control.
1480                       mc_pause_threshold_q0q3)
1481                      << (i * 2 * 8));
1482         }
1483         writeq(val64, &bar0->mc_pause_thresh_q0q3);
1484
1485         val64 = 0;
1486         for (i = 0; i < 4; i++) {
1487                 val64 |=
1488                     (((u64) 0xFF00 | nic->mac_control.
1489                       mc_pause_threshold_q4q7)
1490                      << (i * 2 * 8));
1491         }
1492         writeq(val64, &bar0->mc_pause_thresh_q4q7);
1493
1494         /*
1495          * TxDMA will stop Read request if the number of read split has
1496          * exceeded the limit pointed by shared_splits
1497          */
1498         val64 = readq(&bar0->pic_control);
1499         val64 |= PIC_CNTL_SHARED_SPLITS(shared_splits);
1500         writeq(val64, &bar0->pic_control);
1501
1502         if (nic->config.bus_speed == 266) {
1503                 writeq(TXREQTO_VAL(0x7f) | TXREQTO_EN, &bar0->txreqtimeout);
1504                 writeq(0x0, &bar0->read_retry_delay);
1505                 writeq(0x0, &bar0->write_retry_delay);
1506         }
1507
1508         /*
1509          * Programming the Herc to split every write transaction
1510          * that does not start on an ADB to reduce disconnects.
1511          */
1512         if (nic->device_type == XFRAME_II_DEVICE) {
1513                 val64 = EXT_REQ_EN | MISC_LINK_STABILITY_PRD(3);
1514                 writeq(val64, &bar0->misc_control);
1515                 val64 = readq(&bar0->pic_control2);
1516                 val64 &= ~(BIT(13)|BIT(14)|BIT(15));
1517                 writeq(val64, &bar0->pic_control2);
1518         }
1519         if (strstr(nic->product_name, "CX4")) {
1520                 val64 = TMAC_AVG_IPG(0x17);
1521                 writeq(val64, &bar0->tmac_avg_ipg);
1522         }
1523
1524         return SUCCESS;
1525 }
1526 #define LINK_UP_DOWN_INTERRUPT          1
1527 #define MAC_RMAC_ERR_TIMER              2
1528
1529 static int s2io_link_fault_indication(nic_t *nic)
1530 {
1531         if (nic->intr_type != INTA)
1532                 return MAC_RMAC_ERR_TIMER;
1533         if (nic->device_type == XFRAME_II_DEVICE)
1534                 return LINK_UP_DOWN_INTERRUPT;
1535         else
1536                 return MAC_RMAC_ERR_TIMER;
1537 }
1538
1539 /**
1540  *  en_dis_able_nic_intrs - Enable or Disable the interrupts
1541  *  @nic: device private variable,
1542  *  @mask: A mask indicating which Intr block must be modified and,
1543  *  @flag: A flag indicating whether to enable or disable the Intrs.
1544  *  Description: This function will either disable or enable the interrupts
1545  *  depending on the flag argument. The mask argument can be used to
1546  *  enable/disable any Intr block.
1547  *  Return Value: NONE.
1548  */
1549
1550 static void en_dis_able_nic_intrs(struct s2io_nic *nic, u16 mask, int flag)
1551 {
1552         XENA_dev_config_t __iomem *bar0 = nic->bar0;
1553         register u64 val64 = 0, temp64 = 0;
1554
1555         /*  Top level interrupt classification */
1556         /*  PIC Interrupts */
1557         if ((mask & (TX_PIC_INTR | RX_PIC_INTR))) {
1558                 /*  Enable PIC Intrs in the general intr mask register */
1559                 val64 = TXPIC_INT_M | PIC_RX_INT_M;
1560                 if (flag == ENABLE_INTRS) {
1561                         temp64 = readq(&bar0->general_int_mask);
1562                         temp64 &= ~((u64) val64);
1563                         writeq(temp64, &bar0->general_int_mask);
1564                         /*
1565                          * If Hercules adapter enable GPIO otherwise
1566                          * disabled all PCIX, Flash, MDIO, IIC and GPIO
1567                          * interrupts for now.
1568                          * TODO
1569                          */
1570                         if (s2io_link_fault_indication(nic) ==
1571                                         LINK_UP_DOWN_INTERRUPT ) {
1572                                 temp64 = readq(&bar0->pic_int_mask);
1573                                 temp64 &= ~((u64) PIC_INT_GPIO);
1574                                 writeq(temp64, &bar0->pic_int_mask);
1575                                 temp64 = readq(&bar0->gpio_int_mask);
1576                                 temp64 &= ~((u64) GPIO_INT_MASK_LINK_UP);
1577                                 writeq(temp64, &bar0->gpio_int_mask);
1578                         } else {
1579                                 writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
1580                         }
1581                         /*
1582                          * No MSI Support is available presently, so TTI and
1583                          * RTI interrupts are also disabled.
1584                          */
1585                 } else if (flag == DISABLE_INTRS) {
1586                         /*
1587                          * Disable PIC Intrs in the general
1588                          * intr mask register
1589                          */
1590                         writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
1591                         temp64 = readq(&bar0->general_int_mask);
1592                         val64 |= temp64;
1593                         writeq(val64, &bar0->general_int_mask);
1594                 }
1595         }
1596
1597         /*  DMA Interrupts */
1598         /*  Enabling/Disabling Tx DMA interrupts */
1599         if (mask & TX_DMA_INTR) {
1600                 /* Enable TxDMA Intrs in the general intr mask register */
1601                 val64 = TXDMA_INT_M;
1602                 if (flag == ENABLE_INTRS) {
1603                         temp64 = readq(&bar0->general_int_mask);
1604                         temp64 &= ~((u64) val64);
1605                         writeq(temp64, &bar0->general_int_mask);
1606                         /*
1607                          * Keep all interrupts other than PFC interrupt
1608                          * and PCC interrupt disabled in DMA level.
1609                          */
1610                         val64 = DISABLE_ALL_INTRS & ~(TXDMA_PFC_INT_M |
1611                                                       TXDMA_PCC_INT_M);
1612                         writeq(val64, &bar0->txdma_int_mask);
1613                         /*
1614                          * Enable only the MISC error 1 interrupt in PFC block
1615                          */
1616                         val64 = DISABLE_ALL_INTRS & (~PFC_MISC_ERR_1);
1617                         writeq(val64, &bar0->pfc_err_mask);
1618                         /*
1619                          * Enable only the FB_ECC error interrupt in PCC block
1620                          */
1621                         val64 = DISABLE_ALL_INTRS & (~PCC_FB_ECC_ERR);
1622                         writeq(val64, &bar0->pcc_err_mask);
1623                 } else if (flag == DISABLE_INTRS) {
1624                         /*
1625                          * Disable TxDMA Intrs in the general intr mask
1626                          * register
1627                          */
1628                         writeq(DISABLE_ALL_INTRS, &bar0->txdma_int_mask);
1629                         writeq(DISABLE_ALL_INTRS, &bar0->pfc_err_mask);
1630                         temp64 = readq(&bar0->general_int_mask);
1631                         val64 |= temp64;
1632                         writeq(val64, &bar0->general_int_mask);
1633                 }
1634         }
1635
1636         /*  Enabling/Disabling Rx DMA interrupts */
1637         if (mask & RX_DMA_INTR) {
1638                 /*  Enable RxDMA Intrs in the general intr mask register */
1639                 val64 = RXDMA_INT_M;
1640                 if (flag == ENABLE_INTRS) {
1641                         temp64 = readq(&bar0->general_int_mask);
1642                         temp64 &= ~((u64) val64);
1643                         writeq(temp64, &bar0->general_int_mask);
1644                         /*
1645                          * All RxDMA block interrupts are disabled for now
1646                          * TODO
1647                          */
1648                         writeq(DISABLE_ALL_INTRS, &bar0->rxdma_int_mask);
1649                 } else if (flag == DISABLE_INTRS) {
1650                         /*
1651                          * Disable RxDMA Intrs in the general intr mask
1652                          * register
1653                          */
1654                         writeq(DISABLE_ALL_INTRS, &bar0->rxdma_int_mask);
1655                         temp64 = readq(&bar0->general_int_mask);
1656                         val64 |= temp64;
1657                         writeq(val64, &bar0->general_int_mask);
1658                 }
1659         }
1660
1661         /*  MAC Interrupts */
1662         /*  Enabling/Disabling MAC interrupts */
1663         if (mask & (TX_MAC_INTR | RX_MAC_INTR)) {
1664                 val64 = TXMAC_INT_M | RXMAC_INT_M;
1665                 if (flag == ENABLE_INTRS) {
1666                         temp64 = readq(&bar0->general_int_mask);
1667                         temp64 &= ~((u64) val64);
1668                         writeq(temp64, &bar0->general_int_mask);
1669                         /*
1670                          * All MAC block error interrupts are disabled for now
1671                          * TODO
1672                          */
1673                 } else if (flag == DISABLE_INTRS) {
1674                         /*
1675                          * Disable MAC Intrs in the general intr mask register
1676                          */
1677                         writeq(DISABLE_ALL_INTRS, &bar0->mac_int_mask);
1678                         writeq(DISABLE_ALL_INTRS,
1679                                &bar0->mac_rmac_err_mask);
1680
1681                         temp64 = readq(&bar0->general_int_mask);
1682                         val64 |= temp64;
1683                         writeq(val64, &bar0->general_int_mask);
1684                 }
1685         }
1686
1687         /*  XGXS Interrupts */
1688         if (mask & (TX_XGXS_INTR | RX_XGXS_INTR)) {
1689                 val64 = TXXGXS_INT_M | RXXGXS_INT_M;
1690                 if (flag == ENABLE_INTRS) {
1691                         temp64 = readq(&bar0->general_int_mask);
1692                         temp64 &= ~((u64) val64);
1693                         writeq(temp64, &bar0->general_int_mask);
1694                         /*
1695                          * All XGXS block error interrupts are disabled for now
1696                          * TODO
1697                          */
1698                         writeq(DISABLE_ALL_INTRS, &bar0->xgxs_int_mask);
1699                 } else if (flag == DISABLE_INTRS) {
1700                         /*
1701                          * Disable MC Intrs in the general intr mask register
1702                          */
1703                         writeq(DISABLE_ALL_INTRS, &bar0->xgxs_int_mask);
1704                         temp64 = readq(&bar0->general_int_mask);
1705                         val64 |= temp64;
1706                         writeq(val64, &bar0->general_int_mask);
1707                 }
1708         }
1709
1710         /*  Memory Controller(MC) interrupts */
1711         if (mask & MC_INTR) {
1712                 val64 = MC_INT_M;
1713                 if (flag == ENABLE_INTRS) {
1714                         temp64 = readq(&bar0->general_int_mask);
1715                         temp64 &= ~((u64) val64);
1716                         writeq(temp64, &bar0->general_int_mask);
1717                         /*
1718                          * Enable all MC Intrs.
1719                          */
1720                         writeq(0x0, &bar0->mc_int_mask);
1721                         writeq(0x0, &bar0->mc_err_mask);
1722                 } else if (flag == DISABLE_INTRS) {
1723                         /*
1724                          * Disable MC Intrs in the general intr mask register
1725                          */
1726                         writeq(DISABLE_ALL_INTRS, &bar0->mc_int_mask);
1727                         temp64 = readq(&bar0->general_int_mask);
1728                         val64 |= temp64;
1729                         writeq(val64, &bar0->general_int_mask);
1730                 }
1731         }
1732
1733
1734         /*  Tx traffic interrupts */
1735         if (mask & TX_TRAFFIC_INTR) {
1736                 val64 = TXTRAFFIC_INT_M;
1737                 if (flag == ENABLE_INTRS) {
1738                         temp64 = readq(&bar0->general_int_mask);
1739                         temp64 &= ~((u64) val64);
1740                         writeq(temp64, &bar0->general_int_mask);
1741                         /*
1742                          * Enable all the Tx side interrupts
1743                          * writing 0 Enables all 64 TX interrupt levels
1744                          */
1745                         writeq(0x0, &bar0->tx_traffic_mask);
1746                 } else if (flag == DISABLE_INTRS) {
1747                         /*
1748                          * Disable Tx Traffic Intrs in the general intr mask
1749                          * register.
1750                          */
1751                         writeq(DISABLE_ALL_INTRS, &bar0->tx_traffic_mask);
1752                         temp64 = readq(&bar0->general_int_mask);
1753                         val64 |= temp64;
1754                         writeq(val64, &bar0->general_int_mask);
1755                 }
1756         }
1757
1758         /*  Rx traffic interrupts */
1759         if (mask & RX_TRAFFIC_INTR) {
1760                 val64 = RXTRAFFIC_INT_M;
1761                 if (flag == ENABLE_INTRS) {
1762                         temp64 = readq(&bar0->general_int_mask);
1763                         temp64 &= ~((u64) val64);
1764                         writeq(temp64, &bar0->general_int_mask);
1765                         /* writing 0 Enables all 8 RX interrupt levels */
1766                         writeq(0x0, &bar0->rx_traffic_mask);
1767                 } else if (flag == DISABLE_INTRS) {
1768                         /*
1769                          * Disable Rx Traffic Intrs in the general intr mask
1770                          * register.
1771                          */
1772                         writeq(DISABLE_ALL_INTRS, &bar0->rx_traffic_mask);
1773                         temp64 = readq(&bar0->general_int_mask);
1774                         val64 |= temp64;
1775                         writeq(val64, &bar0->general_int_mask);
1776                 }
1777         }
1778 }
1779
1780 static int check_prc_pcc_state(u64 val64, int flag, int rev_id, int herc)
1781 {
1782         int ret = 0;
1783
1784         if (flag == FALSE) {
1785                 if ((!herc && (rev_id >= 4)) || herc) {
1786                         if (!(val64 & ADAPTER_STATUS_RMAC_PCC_IDLE) &&
1787                             ((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ==
1788                              ADAPTER_STATUS_RC_PRC_QUIESCENT)) {
1789                                 ret = 1;
1790                         }
1791                 }else {
1792                         if (!(val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE) &&
1793                             ((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ==
1794                              ADAPTER_STATUS_RC_PRC_QUIESCENT)) {
1795                                 ret = 1;
1796                         }
1797                 }
1798         } else {
1799                 if ((!herc && (rev_id >= 4)) || herc) {
1800                         if (((val64 & ADAPTER_STATUS_RMAC_PCC_IDLE) ==
1801                              ADAPTER_STATUS_RMAC_PCC_IDLE) &&
1802                             (!(val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ||
1803                              ((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ==
1804                               ADAPTER_STATUS_RC_PRC_QUIESCENT))) {
1805                                 ret = 1;
1806                         }
1807                 } else {
1808                         if (((val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE) ==
1809                              ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE) &&
1810                             (!(val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ||
1811                              ((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ==
1812                               ADAPTER_STATUS_RC_PRC_QUIESCENT))) {
1813                                 ret = 1;
1814                         }
1815                 }
1816         }
1817
1818         return ret;
1819 }
1820 /**
1821  *  verify_xena_quiescence - Checks whether the H/W is ready
1822  *  @val64 :  Value read from adapter status register.
1823  *  @flag : indicates if the adapter enable bit was ever written once
1824  *  before.
1825  *  Description: Returns whether the H/W is ready to go or not. Depending
1826  *  on whether adapter enable bit was written or not the comparison
1827  *  differs and the calling function passes the input argument flag to
1828  *  indicate this.
1829  *  Return: 1 If xena is quiescence
1830  *          0 If Xena is not quiescence
1831  */
1832
1833 static int verify_xena_quiescence(nic_t *sp, u64 val64, int flag)
1834 {
1835         int ret = 0, herc;
1836         u64 tmp64 = ~((u64) val64);
1837         int rev_id = get_xena_rev_id(sp->pdev);
1838
1839         herc = (sp->device_type == XFRAME_II_DEVICE);
1840         if (!
1841             (tmp64 &
1842              (ADAPTER_STATUS_TDMA_READY | ADAPTER_STATUS_RDMA_READY |
1843               ADAPTER_STATUS_PFC_READY | ADAPTER_STATUS_TMAC_BUF_EMPTY |
1844               ADAPTER_STATUS_PIC_QUIESCENT | ADAPTER_STATUS_MC_DRAM_READY |
1845               ADAPTER_STATUS_MC_QUEUES_READY | ADAPTER_STATUS_M_PLL_LOCK |
1846               ADAPTER_STATUS_P_PLL_LOCK))) {
1847                 ret = check_prc_pcc_state(val64, flag, rev_id, herc);
1848         }
1849
1850         return ret;
1851 }
1852
1853 /**
1854  * fix_mac_address -  Fix for Mac addr problem on Alpha platforms
1855  * @sp: Pointer to device specifc structure
1856  * Description :
1857  * New procedure to clear mac address reading  problems on Alpha platforms
1858  *
1859  */
1860
1861 static void fix_mac_address(nic_t * sp)
1862 {
1863         XENA_dev_config_t __iomem *bar0 = sp->bar0;
1864         u64 val64;
1865         int i = 0;
1866
1867         while (fix_mac[i] != END_SIGN) {
1868                 writeq(fix_mac[i++], &bar0->gpio_control);
1869                 udelay(10);
1870                 val64 = readq(&bar0->gpio_control);
1871         }
1872 }
1873
1874 /**
1875  *  start_nic - Turns the device on
1876  *  @nic : device private variable.
1877  *  Description:
1878  *  This function actually turns the device on. Before this  function is
1879  *  called,all Registers are configured from their reset states
1880  *  and shared memory is allocated but the NIC is still quiescent. On
1881  *  calling this function, the device interrupts are cleared and the NIC is
1882  *  literally switched on by writing into the adapter control register.
1883  *  Return Value:
1884  *  SUCCESS on success and -1 on failure.
1885  */
1886
1887 static int start_nic(struct s2io_nic *nic)
1888 {
1889         XENA_dev_config_t __iomem *bar0 = nic->bar0;
1890         struct net_device *dev = nic->dev;
1891         register u64 val64 = 0;
1892         u16 interruptible;
1893         u16 subid, i;
1894         mac_info_t *mac_control;
1895         struct config_param *config;
1896
1897         mac_control = &nic->mac_control;
1898         config = &nic->config;
1899
1900         /*  PRC Initialization and configuration */
1901         for (i = 0; i < config->rx_ring_num; i++) {
1902                 writeq((u64) mac_control->rings[i].rx_blocks[0].block_dma_addr,
1903                        &bar0->prc_rxd0_n[i]);
1904
1905                 val64 = readq(&bar0->prc_ctrl_n[i]);
1906                 if (nic->config.bimodal)
1907                         val64 |= PRC_CTRL_BIMODAL_INTERRUPT;
1908                 if (nic->rxd_mode == RXD_MODE_1)
1909                         val64 |= PRC_CTRL_RC_ENABLED;
1910                 else
1911                         val64 |= PRC_CTRL_RC_ENABLED | PRC_CTRL_RING_MODE_3;
1912                 if (nic->device_type == XFRAME_II_DEVICE)
1913                         val64 |= PRC_CTRL_GROUP_READS;
1914                 val64 &= ~PRC_CTRL_RXD_BACKOFF_INTERVAL(0xFFFFFF);
1915                 val64 |= PRC_CTRL_RXD_BACKOFF_INTERVAL(0x1000);
1916                 writeq(val64, &bar0->prc_ctrl_n[i]);
1917         }
1918
1919         if (nic->rxd_mode == RXD_MODE_3B) {
1920                 /* Enabling 2 buffer mode by writing into Rx_pa_cfg reg. */
1921                 val64 = readq(&bar0->rx_pa_cfg);
1922                 val64 |= RX_PA_CFG_IGNORE_L2_ERR;
1923                 writeq(val64, &bar0->rx_pa_cfg);
1924         }
1925
1926         /*
1927          * Enabling MC-RLDRAM. After enabling the device, we timeout
1928          * for around 100ms, which is approximately the time required
1929          * for the device to be ready for operation.
1930          */
1931         val64 = readq(&bar0->mc_rldram_mrs);
1932         val64 |= MC_RLDRAM_QUEUE_SIZE_ENABLE | MC_RLDRAM_MRS_ENABLE;
1933         SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
1934         val64 = readq(&bar0->mc_rldram_mrs);
1935
1936         msleep(100);    /* Delay by around 100 ms. */
1937
1938         /* Enabling ECC Protection. */
1939         val64 = readq(&bar0->adapter_control);
1940         val64 &= ~ADAPTER_ECC_EN;
1941         writeq(val64, &bar0->adapter_control);
1942
1943         /*
1944          * Clearing any possible Link state change interrupts that
1945          * could have popped up just before Enabling the card.
1946          */
1947         val64 = readq(&bar0->mac_rmac_err_reg);
1948         if (val64)
1949                 writeq(val64, &bar0->mac_rmac_err_reg);
1950
1951         /*
1952          * Verify if the device is ready to be enabled, if so enable
1953          * it.
1954          */
1955         val64 = readq(&bar0->adapter_status);
1956         if (!verify_xena_quiescence(nic, val64, nic->device_enabled_once)) {
1957                 DBG_PRINT(ERR_DBG, "%s: device is not ready, ", dev->name);
1958                 DBG_PRINT(ERR_DBG, "Adapter status reads: 0x%llx\n",
1959                           (unsigned long long) val64);
1960                 return FAILURE;
1961         }
1962
1963         /*  Enable select interrupts */
1964         if (nic->intr_type != INTA)
1965                 en_dis_able_nic_intrs(nic, ENA_ALL_INTRS, DISABLE_INTRS);
1966         else {
1967                 interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR;
1968                 interruptible |= TX_PIC_INTR | RX_PIC_INTR;
1969                 interruptible |= TX_MAC_INTR | RX_MAC_INTR;
1970                 en_dis_able_nic_intrs(nic, interruptible, ENABLE_INTRS);
1971         }
1972
1973         /*
1974          * With some switches, link might be already up at this point.
1975          * Because of this weird behavior, when we enable laser,
1976          * we may not get link. We need to handle this. We cannot
1977          * figure out which switch is misbehaving. So we are forced to
1978          * make a global change.
1979          */
1980
1981         /* Enabling Laser. */
1982         val64 = readq(&bar0->adapter_control);
1983         val64 |= ADAPTER_EOI_TX_ON;
1984         writeq(val64, &bar0->adapter_control);
1985
1986         if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) {
1987                 /*
1988                  * Dont see link state interrupts initally on some switches,
1989                  * so directly scheduling the link state task here.
1990                  */
1991                 schedule_work(&nic->set_link_task);
1992         }
1993         /* SXE-002: Initialize link and activity LED */
1994         subid = nic->pdev->subsystem_device;
1995         if (((subid & 0xFF) >= 0x07) &&
1996             (nic->device_type == XFRAME_I_DEVICE)) {
1997                 val64 = readq(&bar0->gpio_control);
1998                 val64 |= 0x0000800000000000ULL;
1999                 writeq(val64, &bar0->gpio_control);
2000                 val64 = 0x0411040400000000ULL;
2001                 writeq(val64, (void __iomem *)bar0 + 0x2700);
2002         }
2003
2004         return SUCCESS;
2005 }
2006 /**
2007  * s2io_txdl_getskb - Get the skb from txdl, unmap and return skb
2008  */
2009 static struct sk_buff *s2io_txdl_getskb(fifo_info_t *fifo_data, TxD_t *txdlp, int get_off)
2010 {
2011         nic_t *nic = fifo_data->nic;
2012         struct sk_buff *skb;
2013         TxD_t *txds;
2014         u16 j, frg_cnt;
2015
2016         txds = txdlp;
2017         if (txds->Host_Control == (u64)(long)nic->ufo_in_band_v) {
2018                 pci_unmap_single(nic->pdev, (dma_addr_t)
2019                         txds->Buffer_Pointer, sizeof(u64),
2020                         PCI_DMA_TODEVICE);
2021                 txds++;
2022         }
2023
2024         skb = (struct sk_buff *) ((unsigned long)
2025                         txds->Host_Control);
2026         if (!skb) {
2027                 memset(txdlp, 0, (sizeof(TxD_t) * fifo_data->max_txds));
2028                 return NULL;
2029         }
2030         pci_unmap_single(nic->pdev, (dma_addr_t)
2031                          txds->Buffer_Pointer,
2032                          skb->len - skb->data_len,
2033                          PCI_DMA_TODEVICE);
2034         frg_cnt = skb_shinfo(skb)->nr_frags;
2035         if (frg_cnt) {
2036                 txds++;
2037                 for (j = 0; j < frg_cnt; j++, txds++) {
2038                         skb_frag_t *frag = &skb_shinfo(skb)->frags[j];
2039                         if (!txds->Buffer_Pointer)
2040                                 break;
2041                         pci_unmap_page(nic->pdev, (dma_addr_t)
2042                                         txds->Buffer_Pointer,
2043                                        frag->size, PCI_DMA_TODEVICE);
2044                 }
2045         }
2046         txdlp->Host_Control = 0;
2047         return(skb);
2048 }
2049
2050 /**
2051  *  free_tx_buffers - Free all queued Tx buffers
2052  *  @nic : device private variable.
2053  *  Description:
2054  *  Free all queued Tx buffers.
2055  *  Return Value: void
2056 */
2057
2058 static void free_tx_buffers(struct s2io_nic *nic)
2059 {
2060         struct net_device *dev = nic->dev;
2061         struct sk_buff *skb;
2062         TxD_t *txdp;
2063         int i, j;
2064         mac_info_t *mac_control;
2065         struct config_param *config;
2066         int cnt = 0;
2067
2068         mac_control = &nic->mac_control;
2069         config = &nic->config;
2070
2071         for (i = 0; i < config->tx_fifo_num; i++) {
2072                 for (j = 0; j < config->tx_cfg[i].fifo_len - 1; j++) {
2073                         txdp = (TxD_t *) mac_control->fifos[i].list_info[j].
2074                             list_virt_addr;
2075                         skb = s2io_txdl_getskb(&mac_control->fifos[i], txdp, j);
2076                         if (skb) {
2077                                 dev_kfree_skb(skb);
2078                                 cnt++;
2079                         }
2080                 }
2081                 DBG_PRINT(INTR_DBG,
2082                           "%s:forcibly freeing %d skbs on FIFO%d\n",
2083                           dev->name, cnt, i);
2084                 mac_control->fifos[i].tx_curr_get_info.offset = 0;
2085                 mac_control->fifos[i].tx_curr_put_info.offset = 0;
2086         }
2087 }
2088
2089 /**
2090  *   stop_nic -  To stop the nic
2091  *   @nic ; device private variable.
2092  *   Description:
2093  *   This function does exactly the opposite of what the start_nic()
2094  *   function does. This function is called to stop the device.
2095  *   Return Value:
2096  *   void.
2097  */
2098
2099 static void stop_nic(struct s2io_nic *nic)
2100 {
2101         XENA_dev_config_t __iomem *bar0 = nic->bar0;
2102         register u64 val64 = 0;
2103         u16 interruptible, i;
2104         mac_info_t *mac_control;
2105         struct config_param *config;
2106
2107         mac_control = &nic->mac_control;
2108         config = &nic->config;
2109
2110         /*  Disable all interrupts */
2111         interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR;
2112         interruptible |= TX_PIC_INTR | RX_PIC_INTR;
2113         interruptible |= TX_MAC_INTR | RX_MAC_INTR;
2114         en_dis_able_nic_intrs(nic, interruptible, DISABLE_INTRS);
2115
2116         /*  Disable PRCs */
2117         for (i = 0; i < config->rx_ring_num; i++) {
2118                 val64 = readq(&bar0->prc_ctrl_n[i]);
2119                 val64 &= ~((u64) PRC_CTRL_RC_ENABLED);
2120                 writeq(val64, &bar0->prc_ctrl_n[i]);
2121         }
2122 }
2123
2124 static int fill_rxd_3buf(nic_t *nic, RxD_t *rxdp, struct sk_buff *skb)
2125 {
2126         struct net_device *dev = nic->dev;
2127         struct sk_buff *frag_list;
2128         void *tmp;
2129
2130         /* Buffer-1 receives L3/L4 headers */
2131         ((RxD3_t*)rxdp)->Buffer1_ptr = pci_map_single
2132                         (nic->pdev, skb->data, l3l4hdr_size + 4,
2133                         PCI_DMA_FROMDEVICE);
2134
2135         /* skb_shinfo(skb)->frag_list will have L4 data payload */
2136         skb_shinfo(skb)->frag_list = dev_alloc_skb(dev->mtu + ALIGN_SIZE);
2137         if (skb_shinfo(skb)->frag_list == NULL) {
2138                 DBG_PRINT(ERR_DBG, "%s: dev_alloc_skb failed\n ", dev->name);
2139                 return -ENOMEM ;
2140         }
2141         frag_list = skb_shinfo(skb)->frag_list;
2142         frag_list->next = NULL;
2143         tmp = (void *)ALIGN((long)frag_list->data, ALIGN_SIZE + 1);
2144         frag_list->data = tmp;
2145         frag_list->tail = tmp;
2146
2147         /* Buffer-2 receives L4 data payload */
2148         ((RxD3_t*)rxdp)->Buffer2_ptr = pci_map_single(nic->pdev,
2149                                 frag_list->data, dev->mtu,
2150                                 PCI_DMA_FROMDEVICE);
2151         rxdp->Control_2 |= SET_BUFFER1_SIZE_3(l3l4hdr_size + 4);
2152         rxdp->Control_2 |= SET_BUFFER2_SIZE_3(dev->mtu);
2153
2154         return SUCCESS;
2155 }
2156
2157 /**
2158  *  fill_rx_buffers - Allocates the Rx side skbs
2159  *  @nic:  device private variable
2160  *  @ring_no: ring number
2161  *  Description:
2162  *  The function allocates Rx side skbs and puts the physical
2163  *  address of these buffers into the RxD buffer pointers, so that the NIC
2164  *  can DMA the received frame into these locations.
2165  *  The NIC supports 3 receive modes, viz
2166  *  1. single buffer,
2167  *  2. three buffer and
2168  *  3. Five buffer modes.
2169  *  Each mode defines how many fragments the received frame will be split
2170  *  up into by the NIC. The frame is split into L3 header, L4 Header,
2171  *  L4 payload in three buffer mode and in 5 buffer mode, L4 payload itself
2172  *  is split into 3 fragments. As of now only single buffer mode is
2173  *  supported.
2174  *   Return Value:
2175  *  SUCCESS on success or an appropriate -ve value on failure.
2176  */
2177
2178 static int fill_rx_buffers(struct s2io_nic *nic, int ring_no)
2179 {
2180         struct net_device *dev = nic->dev;
2181         struct sk_buff *skb;
2182         RxD_t *rxdp;
2183         int off, off1, size, block_no, block_no1;
2184         u32 alloc_tab = 0;
2185         u32 alloc_cnt;
2186         mac_info_t *mac_control;
2187         struct config_param *config;
2188         u64 tmp;
2189         buffAdd_t *ba;
2190 #ifndef CONFIG_S2IO_NAPI
2191         unsigned long flags;
2192 #endif
2193         RxD_t *first_rxdp = NULL;
2194
2195         mac_control = &nic->mac_control;
2196         config = &nic->config;
2197         alloc_cnt = mac_control->rings[ring_no].pkt_cnt -
2198             atomic_read(&nic->rx_bufs_left[ring_no]);
2199
2200         block_no1 = mac_control->rings[ring_no].rx_curr_get_info.block_index;
2201         off1 = mac_control->rings[ring_no].rx_curr_get_info.offset;
2202         while (alloc_tab < alloc_cnt) {
2203                 block_no = mac_control->rings[ring_no].rx_curr_put_info.
2204                     block_index;
2205                 off = mac_control->rings[ring_no].rx_curr_put_info.offset;
2206
2207                 rxdp = mac_control->rings[ring_no].
2208                                 rx_blocks[block_no].rxds[off].virt_addr;
2209
2210                 if ((block_no == block_no1) && (off == off1) &&
2211                                         (rxdp->Host_Control)) {
2212                         DBG_PRINT(INTR_DBG, "%s: Get and Put",
2213                                   dev->name);
2214                         DBG_PRINT(INTR_DBG, " info equated\n");
2215                         goto end;
2216                 }
2217                 if (off && (off == rxd_count[nic->rxd_mode])) {
2218                         mac_control->rings[ring_no].rx_curr_put_info.
2219                             block_index++;
2220                         if (mac_control->rings[ring_no].rx_curr_put_info.
2221                             block_index == mac_control->rings[ring_no].
2222                                         block_count)
2223                                 mac_control->rings[ring_no].rx_curr_put_info.
2224                                         block_index = 0;
2225                         block_no = mac_control->rings[ring_no].
2226                                         rx_curr_put_info.block_index;
2227                         if (off == rxd_count[nic->rxd_mode])
2228                                 off = 0;
2229                         mac_control->rings[ring_no].rx_curr_put_info.
2230                                 offset = off;
2231                         rxdp = mac_control->rings[ring_no].
2232                                 rx_blocks[block_no].block_virt_addr;
2233                         DBG_PRINT(INTR_DBG, "%s: Next block at: %p\n",
2234                                   dev->name, rxdp);
2235                 }
2236 #ifndef CONFIG_S2IO_NAPI
2237                 spin_lock_irqsave(&nic->put_lock, flags);
2238                 mac_control->rings[ring_no].put_pos =
2239                     (block_no * (rxd_count[nic->rxd_mode] + 1)) + off;
2240                 spin_unlock_irqrestore(&nic->put_lock, flags);
2241 #endif
2242                 if ((rxdp->Control_1 & RXD_OWN_XENA) &&
2243                         ((nic->rxd_mode >= RXD_MODE_3A) &&
2244                                 (rxdp->Control_2 & BIT(0)))) {
2245                         mac_control->rings[ring_no].rx_curr_put_info.
2246                                         offset = off;
2247                         goto end;
2248                 }
2249                 /* calculate size of skb based on ring mode */
2250                 size = dev->mtu + HEADER_ETHERNET_II_802_3_SIZE +
2251                                 HEADER_802_2_SIZE + HEADER_SNAP_SIZE;
2252                 if (nic->rxd_mode == RXD_MODE_1)
2253                         size += NET_IP_ALIGN;
2254                 else if (nic->rxd_mode == RXD_MODE_3B)
2255                         size = dev->mtu + ALIGN_SIZE + BUF0_LEN + 4;
2256                 else
2257                         size = l3l4hdr_size + ALIGN_SIZE + BUF0_LEN + 4;
2258
2259                 /* allocate skb */
2260                 skb = dev_alloc_skb(size);
2261                 if(!skb) {
2262                         DBG_PRINT(ERR_DBG, "%s: Out of ", dev->name);
2263                         DBG_PRINT(ERR_DBG, "memory to allocate SKBs\n");
2264                         if (first_rxdp) {
2265                                 wmb();
2266                                 first_rxdp->Control_1 |= RXD_OWN_XENA;
2267                         }
2268                         return -ENOMEM ;
2269                 }
2270                 if (nic->rxd_mode == RXD_MODE_1) {
2271                         /* 1 buffer mode - normal operation mode */
2272                         memset(rxdp, 0, sizeof(RxD1_t));
2273                         skb_reserve(skb, NET_IP_ALIGN);
2274                         ((RxD1_t*)rxdp)->Buffer0_ptr = pci_map_single
2275                             (nic->pdev, skb->data, size - NET_IP_ALIGN,
2276                                 PCI_DMA_FROMDEVICE);
2277                         rxdp->Control_2 = SET_BUFFER0_SIZE_1(size - NET_IP_ALIGN);
2278
2279                 } else if (nic->rxd_mode >= RXD_MODE_3A) {
2280                         /*
2281                          * 2 or 3 buffer mode -
2282                          * Both 2 buffer mode and 3 buffer mode provides 128
2283                          * byte aligned receive buffers.
2284                          *
2285                          * 3 buffer mode provides header separation where in
2286                          * skb->data will have L3/L4 headers where as
2287                          * skb_shinfo(skb)->frag_list will have the L4 data
2288                          * payload
2289                          */
2290
2291                         memset(rxdp, 0, sizeof(RxD3_t));
2292                         ba = &mac_control->rings[ring_no].ba[block_no][off];
2293                         skb_reserve(skb, BUF0_LEN);
2294                         tmp = (u64)(unsigned long) skb->data;
2295                         tmp += ALIGN_SIZE;
2296                         tmp &= ~ALIGN_SIZE;
2297                         skb->data = (void *) (unsigned long)tmp;
2298                         skb->tail = (void *) (unsigned long)tmp;
2299
2300                         ((RxD3_t*)rxdp)->Buffer0_ptr =
2301                             pci_map_single(nic->pdev, ba->ba_0, BUF0_LEN,
2302                                            PCI_DMA_FROMDEVICE);
2303                         rxdp->Control_2 = SET_BUFFER0_SIZE_3(BUF0_LEN);
2304                         if (nic->rxd_mode == RXD_MODE_3B) {
2305                                 /* Two buffer mode */
2306
2307                                 /*
2308                                  * Buffer2 will have L3/L4 header plus
2309                                  * L4 payload
2310                                  */
2311                                 ((RxD3_t*)rxdp)->Buffer2_ptr = pci_map_single
2312                                 (nic->pdev, skb->data, dev->mtu + 4,
2313                                                 PCI_DMA_FROMDEVICE);
2314
2315                                 /* Buffer-1 will be dummy buffer not used */
2316                                 ((RxD3_t*)rxdp)->Buffer1_ptr =
2317                                 pci_map_single(nic->pdev, ba->ba_1, BUF1_LEN,
2318                                         PCI_DMA_FROMDEVICE);
2319                                 rxdp->Control_2 |= SET_BUFFER1_SIZE_3(1);
2320                                 rxdp->Control_2 |= SET_BUFFER2_SIZE_3
2321                                                                 (dev->mtu + 4);
2322                         } else {
2323                                 /* 3 buffer mode */
2324                                 if (fill_rxd_3buf(nic, rxdp, skb) == -ENOMEM) {
2325                                         dev_kfree_skb_irq(skb);
2326                                         if (first_rxdp) {
2327                                                 wmb();
2328                                                 first_rxdp->Control_1 |=
2329                                                         RXD_OWN_XENA;
2330                                         }
2331                                         return -ENOMEM ;
2332                                 }
2333                         }
2334                         rxdp->Control_2 |= BIT(0);
2335                 }
2336                 rxdp->Host_Control = (unsigned long) (skb);
2337                 if (alloc_tab & ((1 << rxsync_frequency) - 1))
2338                         rxdp->Control_1 |= RXD_OWN_XENA;
2339                 off++;
2340                 if (off == (rxd_count[nic->rxd_mode] + 1))
2341                         off = 0;
2342                 mac_control->rings[ring_no].rx_curr_put_info.offset = off;
2343
2344                 rxdp->Control_2 |= SET_RXD_MARKER;
2345                 if (!(alloc_tab & ((1 << rxsync_frequency) - 1))) {
2346                         if (first_rxdp) {
2347                                 wmb();
2348                                 first_rxdp->Control_1 |= RXD_OWN_XENA;
2349                         }
2350                         first_rxdp = rxdp;
2351                 }
2352                 atomic_inc(&nic->rx_bufs_left[ring_no]);
2353                 alloc_tab++;
2354         }
2355
2356       end:
2357         /* Transfer ownership of first descriptor to adapter just before
2358          * exiting. Before that, use memory barrier so that ownership
2359          * and other fields are seen by adapter correctly.
2360          */
2361         if (first_rxdp) {
2362                 wmb();
2363                 first_rxdp->Control_1 |= RXD_OWN_XENA;
2364         }
2365
2366         return SUCCESS;
2367 }
2368
2369 static void free_rxd_blk(struct s2io_nic *sp, int ring_no, int blk)
2370 {
2371         struct net_device *dev = sp->dev;
2372         int j;
2373         struct sk_buff *skb;
2374         RxD_t *rxdp;
2375         mac_info_t *mac_control;
2376         buffAdd_t *ba;
2377
2378         mac_control = &sp->mac_control;
2379         for (j = 0 ; j < rxd_count[sp->rxd_mode]; j++) {
2380                 rxdp = mac_control->rings[ring_no].
2381                                 rx_blocks[blk].rxds[j].virt_addr;
2382                 skb = (struct sk_buff *)
2383                         ((unsigned long) rxdp->Host_Control);
2384                 if (!skb) {
2385                         continue;
2386                 }
2387                 if (sp->rxd_mode == RXD_MODE_1) {
2388                         pci_unmap_single(sp->pdev, (dma_addr_t)
2389                                  ((RxD1_t*)rxdp)->Buffer0_ptr,
2390                                  dev->mtu +
2391                                  HEADER_ETHERNET_II_802_3_SIZE
2392                                  + HEADER_802_2_SIZE +
2393                                  HEADER_SNAP_SIZE,
2394                                  PCI_DMA_FROMDEVICE);
2395                         memset(rxdp, 0, sizeof(RxD1_t));
2396                 } else if(sp->rxd_mode == RXD_MODE_3B) {
2397                         ba = &mac_control->rings[ring_no].
2398                                 ba[blk][j];
2399                         pci_unmap_single(sp->pdev, (dma_addr_t)
2400                                  ((RxD3_t*)rxdp)->Buffer0_ptr,
2401                                  BUF0_LEN,
2402                                  PCI_DMA_FROMDEVICE);
2403                         pci_unmap_single(sp->pdev, (dma_addr_t)
2404                                  ((RxD3_t*)rxdp)->Buffer1_ptr,
2405                                  BUF1_LEN,
2406                                  PCI_DMA_FROMDEVICE);
2407                         pci_unmap_single(sp->pdev, (dma_addr_t)
2408                                  ((RxD3_t*)rxdp)->Buffer2_ptr,
2409                                  dev->mtu + 4,
2410                                  PCI_DMA_FROMDEVICE);
2411                         memset(rxdp, 0, sizeof(RxD3_t));
2412                 } else {
2413                         pci_unmap_single(sp->pdev, (dma_addr_t)
2414                                 ((RxD3_t*)rxdp)->Buffer0_ptr, BUF0_LEN,
2415                                 PCI_DMA_FROMDEVICE);
2416                         pci_unmap_single(sp->pdev, (dma_addr_t)
2417                                 ((RxD3_t*)rxdp)->Buffer1_ptr,
2418                                 l3l4hdr_size + 4,
2419                                 PCI_DMA_FROMDEVICE);
2420                         pci_unmap_single(sp->pdev, (dma_addr_t)
2421                                 ((RxD3_t*)rxdp)->Buffer2_ptr, dev->mtu,
2422                                 PCI_DMA_FROMDEVICE);
2423                         memset(rxdp, 0, sizeof(RxD3_t));
2424                 }
2425                 dev_kfree_skb(skb);
2426                 atomic_dec(&sp->rx_bufs_left[ring_no]);
2427         }
2428 }
2429
2430 /**
2431  *  free_rx_buffers - Frees all Rx buffers
2432  *  @sp: device private variable.
2433  *  Description:
2434  *  This function will free all Rx buffers allocated by host.
2435  *  Return Value:
2436  *  NONE.
2437  */
2438
2439 static void free_rx_buffers(struct s2io_nic *sp)
2440 {
2441         struct net_device *dev = sp->dev;
2442         int i, blk = 0, buf_cnt = 0;
2443         mac_info_t *mac_control;
2444         struct config_param *config;
2445
2446         mac_control = &sp->mac_control;
2447         config = &sp->config;
2448
2449         for (i = 0; i < config->rx_ring_num; i++) {
2450                 for (blk = 0; blk < rx_ring_sz[i]; blk++)
2451                         free_rxd_blk(sp,i,blk);
2452
2453                 mac_control->rings[i].rx_curr_put_info.block_index = 0;
2454                 mac_control->rings[i].rx_curr_get_info.block_index = 0;
2455                 mac_control->rings[i].rx_curr_put_info.offset = 0;
2456                 mac_control->rings[i].rx_curr_get_info.offset = 0;
2457                 atomic_set(&sp->rx_bufs_left[i], 0);
2458                 DBG_PRINT(INIT_DBG, "%s:Freed 0x%x Rx Buffers on ring%d\n",
2459                           dev->name, buf_cnt, i);
2460         }
2461 }
2462
2463 /**
2464  * s2io_poll - Rx interrupt handler for NAPI support
2465  * @dev : pointer to the device structure.
2466  * @budget : The number of packets that were budgeted to be processed
2467  * during  one pass through the 'Poll" function.
2468  * Description:
2469  * Comes into picture only if NAPI support has been incorporated. It does
2470  * the same thing that rx_intr_handler does, but not in a interrupt context
2471  * also It will process only a given number of packets.
2472  * Return value:
2473  * 0 on success and 1 if there are No Rx packets to be processed.
2474  */
2475
2476 #if defined(CONFIG_S2IO_NAPI)
2477 static int s2io_poll(struct net_device *dev, int *budget)
2478 {
2479         nic_t *nic = dev->priv;
2480         int pkt_cnt = 0, org_pkts_to_process;
2481         mac_info_t *mac_control;
2482         struct config_param *config;
2483         XENA_dev_config_t __iomem *bar0 = nic->bar0;
2484         u64 val64 = 0xFFFFFFFFFFFFFFFFULL;
2485         int i;
2486
2487         atomic_inc(&nic->isr_cnt);
2488         mac_control = &nic->mac_control;
2489         config = &nic->config;
2490
2491         nic->pkts_to_process = *budget;
2492         if (nic->pkts_to_process > dev->quota)
2493                 nic->pkts_to_process = dev->quota;
2494         org_pkts_to_process = nic->pkts_to_process;
2495
2496         writeq(val64, &bar0->rx_traffic_int);
2497         val64 = readl(&bar0->rx_traffic_int);
2498
2499         for (i = 0; i < config->rx_ring_num; i++) {
2500                 rx_intr_handler(&mac_control->rings[i]);
2501                 pkt_cnt = org_pkts_to_process - nic->pkts_to_process;
2502                 if (!nic->pkts_to_process) {
2503                         /* Quota for the current iteration has been met */
2504                         goto no_rx;
2505                 }
2506         }
2507         if (!pkt_cnt)
2508                 pkt_cnt = 1;
2509
2510         dev->quota -= pkt_cnt;
2511         *budget -= pkt_cnt;
2512         netif_rx_complete(dev);
2513
2514         for (i = 0; i < config->rx_ring_num; i++) {
2515                 if (fill_rx_buffers(nic, i) == -ENOMEM) {
2516                         DBG_PRINT(ERR_DBG, "%s:Out of memory", dev->name);
2517                         DBG_PRINT(ERR_DBG, " in Rx Poll!!\n");
2518                         break;
2519                 }
2520         }
2521         /* Re enable the Rx interrupts. */
2522         writeq(0x0, &bar0->rx_traffic_mask);
2523         val64 = readl(&bar0->rx_traffic_mask);
2524         atomic_dec(&nic->isr_cnt);
2525         return 0;
2526
2527 no_rx:
2528         dev->quota -= pkt_cnt;
2529         *budget -= pkt_cnt;
2530
2531         for (i = 0; i < config->rx_ring_num; i++) {
2532                 if (fill_rx_buffers(nic, i) == -ENOMEM) {
2533                         DBG_PRINT(ERR_DBG, "%s:Out of memory", dev->name);
2534                         DBG_PRINT(ERR_DBG, " in Rx Poll!!\n");
2535                         break;
2536                 }
2537         }
2538         atomic_dec(&nic->isr_cnt);
2539         return 1;
2540 }
2541 #endif
2542
2543 /**
2544  *  rx_intr_handler - Rx interrupt handler
2545  *  @nic: device private variable.
2546  *  Description:
2547  *  If the interrupt is because of a received frame or if the
2548  *  receive ring contains fresh as yet un-processed frames,this function is
2549  *  called. It picks out the RxD at which place the last Rx processing had
2550  *  stopped and sends the skb to the OSM's Rx handler and then increments
2551  *  the offset.
2552  *  Return Value:
2553  *  NONE.
2554  */
2555 static void rx_intr_handler(ring_info_t *ring_data)
2556 {
2557         nic_t *nic = ring_data->nic;
2558         struct net_device *dev = (struct net_device *) nic->dev;
2559         int get_block, put_block, put_offset;
2560         rx_curr_get_info_t get_info, put_info;
2561         RxD_t *rxdp;
2562         struct sk_buff *skb;
2563 #ifndef CONFIG_S2IO_NAPI
2564         int pkt_cnt = 0;
2565 #endif
2566         int i;
2567
2568         spin_lock(&nic->rx_lock);
2569         if (atomic_read(&nic->card_state) == CARD_DOWN) {
2570                 DBG_PRINT(INTR_DBG, "%s: %s going down for reset\n",
2571                           __FUNCTION__, dev->name);
2572                 spin_unlock(&nic->rx_lock);
2573                 return;
2574         }
2575
2576         get_info = ring_data->rx_curr_get_info;
2577         get_block = get_info.block_index;
2578         put_info = ring_data->rx_curr_put_info;
2579         put_block = put_info.block_index;
2580         rxdp = ring_data->rx_blocks[get_block].rxds[get_info.offset].virt_addr;
2581 #ifndef CONFIG_S2IO_NAPI
2582         spin_lock(&nic->put_lock);
2583         put_offset = ring_data->put_pos;
2584         spin_unlock(&nic->put_lock);
2585 #else
2586         put_offset = (put_block * (rxd_count[nic->rxd_mode] + 1)) +
2587                 put_info.offset;
2588 #endif
2589         while (RXD_IS_UP2DT(rxdp)) {
2590                 /* If your are next to put index then it's FIFO full condition */
2591                 if ((get_block == put_block) &&
2592                     (get_info.offset + 1) == put_info.offset) {
2593                         DBG_PRINT(ERR_DBG, "%s: Ring Full\n",dev->name);
2594                         break;
2595                 }
2596                 skb = (struct sk_buff *) ((unsigned long)rxdp->Host_Control);
2597                 if (skb == NULL) {
2598                         DBG_PRINT(ERR_DBG, "%s: The skb is ",
2599                                   dev->name);
2600                         DBG_PRINT(ERR_DBG, "Null in Rx Intr\n");
2601                         spin_unlock(&nic->rx_lock);
2602                         return;
2603                 }
2604                 if (nic->rxd_mode == RXD_MODE_1) {
2605                         pci_unmap_single(nic->pdev, (dma_addr_t)
2606                                  ((RxD1_t*)rxdp)->Buffer0_ptr,
2607                                  dev->mtu +
2608                                  HEADER_ETHERNET_II_802_3_SIZE +
2609                                  HEADER_802_2_SIZE +
2610                                  HEADER_SNAP_SIZE,
2611                                  PCI_DMA_FROMDEVICE);
2612                 } else if (nic->rxd_mode == RXD_MODE_3B) {
2613                         pci_unmap_single(nic->pdev, (dma_addr_t)
2614                                  ((RxD3_t*)rxdp)->Buffer0_ptr,
2615                                  BUF0_LEN, PCI_DMA_FROMDEVICE);
2616                         pci_unmap_single(nic->pdev, (dma_addr_t)
2617                                  ((RxD3_t*)rxdp)->Buffer1_ptr,
2618                                  BUF1_LEN, PCI_DMA_FROMDEVICE);
2619                         pci_unmap_single(nic->pdev, (dma_addr_t)
2620                                  ((RxD3_t*)rxdp)->Buffer2_ptr,
2621                                  dev->mtu + 4,
2622                                  PCI_DMA_FROMDEVICE);
2623                 } else {
2624                         pci_unmap_single(nic->pdev, (dma_addr_t)
2625                                          ((RxD3_t*)rxdp)->Buffer0_ptr, BUF0_LEN,
2626                                          PCI_DMA_FROMDEVICE);
2627                         pci_unmap_single(nic->pdev, (dma_addr_t)
2628                                          ((RxD3_t*)rxdp)->Buffer1_ptr,
2629                                          l3l4hdr_size + 4,
2630                                          PCI_DMA_FROMDEVICE);
2631                         pci_unmap_single(nic->pdev, (dma_addr_t)
2632                                          ((RxD3_t*)rxdp)->Buffer2_ptr,
2633                                          dev->mtu, PCI_DMA_FROMDEVICE);
2634                 }
2635                 prefetch(skb->data);
2636                 rx_osm_handler(ring_data, rxdp);
2637                 get_info.offset++;
2638                 ring_data->rx_curr_get_info.offset = get_info.offset;
2639                 rxdp = ring_data->rx_blocks[get_block].
2640                                 rxds[get_info.offset].virt_addr;
2641                 if (get_info.offset == rxd_count[nic->rxd_mode]) {
2642                         get_info.offset = 0;
2643                         ring_data->rx_curr_get_info.offset = get_info.offset;
2644                         get_block++;
2645                         if (get_block == ring_data->block_count)
2646                                 get_block = 0;
2647                         ring_data->rx_curr_get_info.block_index = get_block;
2648                         rxdp = ring_data->rx_blocks[get_block].block_virt_addr;
2649                 }
2650
2651 #ifdef CONFIG_S2IO_NAPI
2652                 nic->pkts_to_process -= 1;
2653                 if (!nic->pkts_to_process)
2654                         break;
2655 #else
2656                 pkt_cnt++;
2657                 if ((indicate_max_pkts) && (pkt_cnt > indicate_max_pkts))
2658                         break;
2659 #endif
2660         }
2661         if (nic->lro) {
2662                 /* Clear all LRO sessions before exiting */
2663                 for (i=0; i<MAX_LRO_SESSIONS; i++) {
2664                         lro_t *lro = &nic->lro0_n[i];
2665                         if (lro->in_use) {
2666                                 update_L3L4_header(nic, lro);
2667                                 queue_rx_frame(lro->parent);
2668                                 clear_lro_session(lro);
2669                         }
2670                 }
2671         }
2672
2673         spin_unlock(&nic->rx_lock);
2674 }
2675
2676 /**
2677  *  tx_intr_handler - Transmit interrupt handler
2678  *  @nic : device private variable
2679  *  Description:
2680  *  If an interrupt was raised to indicate DMA complete of the
2681  *  Tx packet, this function is called. It identifies the last TxD
2682  *  whose buffer was freed and frees all skbs whose data have already
2683  *  DMA'ed into the NICs internal memory.
2684  *  Return Value:
2685  *  NONE
2686  */
2687
2688 static void tx_intr_handler(fifo_info_t *fifo_data)
2689 {
2690         nic_t *nic = fifo_data->nic;
2691         struct net_device *dev = (struct net_device *) nic->dev;
2692         tx_curr_get_info_t get_info, put_info;
2693         struct sk_buff *skb;
2694         TxD_t *txdlp;
2695
2696         get_info = fifo_data->tx_curr_get_info;
2697         put_info = fifo_data->tx_curr_put_info;
2698         txdlp = (TxD_t *) fifo_data->list_info[get_info.offset].
2699             list_virt_addr;
2700         while ((!(txdlp->Control_1 & TXD_LIST_OWN_XENA)) &&
2701                (get_info.offset != put_info.offset) &&
2702                (txdlp->Host_Control)) {
2703                 /* Check for TxD errors */
2704                 if (txdlp->Control_1 & TXD_T_CODE) {
2705                         unsigned long long err;
2706                         err = txdlp->Control_1 & TXD_T_CODE;
2707                         if ((err >> 48) == 0xA) {
2708                                 DBG_PRINT(TX_DBG, "TxD returned due \
2709 to loss of link\n");
2710                         }
2711                         else {
2712                                 DBG_PRINT(ERR_DBG, "***TxD error \
2713 %llx\n", err);
2714                         }
2715                 }
2716
2717                 skb = s2io_txdl_getskb(fifo_data, txdlp, get_info.offset);
2718                 if (skb == NULL) {
2719                         DBG_PRINT(ERR_DBG, "%s: Null skb ",
2720                         __FUNCTION__);
2721                         DBG_PRINT(ERR_DBG, "in Tx Free Intr\n");
2722                         return;
2723                 }
2724
2725                 /* Updating the statistics block */
2726                 nic->stats.tx_bytes += skb->len;
2727                 dev_kfree_skb_irq(skb);
2728
2729                 get_info.offset++;
2730                 if (get_info.offset == get_info.fifo_len + 1)
2731                         get_info.offset = 0;
2732                 txdlp = (TxD_t *) fifo_data->list_info
2733                     [get_info.offset].list_virt_addr;
2734                 fifo_data->tx_curr_get_info.offset =
2735                     get_info.offset;
2736         }
2737
2738         spin_lock(&nic->tx_lock);
2739         if (netif_queue_stopped(dev))
2740                 netif_wake_queue(dev);
2741         spin_unlock(&nic->tx_lock);
2742 }
2743
2744 /**
2745  *  alarm_intr_handler - Alarm Interrrupt handler
2746  *  @nic: device private variable
2747  *  Description: If the interrupt was neither because of Rx packet or Tx
2748  *  complete, this function is called. If the interrupt was to indicate
2749  *  a loss of link, the OSM link status handler is invoked for any other
2750  *  alarm interrupt the block that raised the interrupt is displayed
2751  *  and a H/W reset is issued.
2752  *  Return Value:
2753  *  NONE
2754 */
2755
2756 static void alarm_intr_handler(struct s2io_nic *nic)
2757 {
2758         struct net_device *dev = (struct net_device *) nic->dev;
2759         XENA_dev_config_t __iomem *bar0 = nic->bar0;
2760         register u64 val64 = 0, err_reg = 0;
2761
2762         /* Handling link status change error Intr */
2763         if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) {
2764                 err_reg = readq(&bar0->mac_rmac_err_reg);
2765                 writeq(err_reg, &bar0->mac_rmac_err_reg);
2766                 if (err_reg & RMAC_LINK_STATE_CHANGE_INT) {
2767                         schedule_work(&nic->set_link_task);
2768                 }
2769         }
2770
2771         /* Handling Ecc errors */
2772         val64 = readq(&bar0->mc_err_reg);
2773         writeq(val64, &bar0->mc_err_reg);
2774         if (val64 & (MC_ERR_REG_ECC_ALL_SNG | MC_ERR_REG_ECC_ALL_DBL)) {
2775                 if (val64 & MC_ERR_REG_ECC_ALL_DBL) {
2776                         nic->mac_control.stats_info->sw_stat.
2777                                 double_ecc_errs++;
2778                         DBG_PRINT(INIT_DBG, "%s: Device indicates ",
2779                                   dev->name);
2780                         DBG_PRINT(INIT_DBG, "double ECC error!!\n");
2781                         if (nic->device_type != XFRAME_II_DEVICE) {
2782                                 /* Reset XframeI only if critical error */
2783                                 if (val64 & (MC_ERR_REG_MIRI_ECC_DB_ERR_0 |
2784                                              MC_ERR_REG_MIRI_ECC_DB_ERR_1)) {
2785                                         netif_stop_queue(dev);
2786                                         schedule_work(&nic->rst_timer_task);
2787                                 }
2788                         }
2789                 } else {
2790                         nic->mac_control.stats_info->sw_stat.
2791                                 single_ecc_errs++;
2792                 }
2793         }
2794
2795         /* In case of a serious error, the device will be Reset. */
2796         val64 = readq(&bar0->serr_source);
2797         if (val64 & SERR_SOURCE_ANY) {
2798                 DBG_PRINT(ERR_DBG, "%s: Device indicates ", dev->name);
2799                 DBG_PRINT(ERR_DBG, "serious error %llx!!\n",
2800                           (unsigned long long)val64);
2801                 netif_stop_queue(dev);
2802                 schedule_work(&nic->rst_timer_task);
2803         }
2804
2805         /*
2806          * Also as mentioned in the latest Errata sheets if the PCC_FB_ECC
2807          * Error occurs, the adapter will be recycled by disabling the
2808          * adapter enable bit and enabling it again after the device
2809          * becomes Quiescent.
2810          */
2811         val64 = readq(&bar0->pcc_err_reg);
2812         writeq(val64, &bar0->pcc_err_reg);
2813         if (val64 & PCC_FB_ECC_DB_ERR) {
2814                 u64 ac = readq(&bar0->adapter_control);
2815                 ac &= ~(ADAPTER_CNTL_EN);
2816                 writeq(ac, &bar0->adapter_control);
2817                 ac = readq(&bar0->adapter_control);
2818                 schedule_work(&nic->set_link_task);
2819         }
2820
2821         /* Other type of interrupts are not being handled now,  TODO */
2822 }
2823
2824 /**
2825  *  wait_for_cmd_complete - waits for a command to complete.
2826  *  @sp : private member of the device structure, which is a pointer to the
2827  *  s2io_nic structure.
2828  *  Description: Function that waits for a command to Write into RMAC
2829  *  ADDR DATA registers to be completed and returns either success or
2830  *  error depending on whether the command was complete or not.
2831  *  Return value:
2832  *   SUCCESS on success and FAILURE on failure.
2833  */
2834
2835 static int wait_for_cmd_complete(void *addr, u64 busy_bit)
2836 {
2837         int ret = FAILURE, cnt = 0;
2838         u64 val64;
2839
2840         while (TRUE) {
2841                 val64 = readq(addr);
2842                 if (!(val64 & busy_bit)) {
2843                         ret = SUCCESS;
2844                         break;
2845                 }
2846
2847                 if(in_interrupt())
2848                         mdelay(50);
2849                 else
2850                         msleep(50);
2851
2852                 if (cnt++ > 10)
2853                         break;
2854         }
2855         return ret;
2856 }
2857
2858 /**
2859  *  s2io_reset - Resets the card.
2860  *  @sp : private member of the device structure.
2861  *  Description: Function to Reset the card. This function then also
2862  *  restores the previously saved PCI configuration space registers as
2863  *  the card reset also resets the configuration space.
2864  *  Return value:
2865  *  void.
2866  */
2867
2868 static void s2io_reset(nic_t * sp)
2869 {
2870         XENA_dev_config_t __iomem *bar0 = sp->bar0;
2871         u64 val64;
2872         u16 subid, pci_cmd;
2873
2874         /* Back up  the PCI-X CMD reg, dont want to lose MMRBC, OST settings */
2875         pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER, &(pci_cmd));
2876
2877         val64 = SW_RESET_ALL;
2878         writeq(val64, &bar0->sw_reset);
2879
2880         /*
2881          * At this stage, if the PCI write is indeed completed, the
2882          * card is reset and so is the PCI Config space of the device.
2883          * So a read cannot be issued at this stage on any of the
2884          * registers to ensure the write into "sw_reset" register
2885          * has gone through.
2886          * Question: Is there any system call that will explicitly force
2887          * all the write commands still pending on the bus to be pushed
2888          * through?
2889          * As of now I'am just giving a 250ms delay and hoping that the
2890          * PCI write to sw_reset register is done by this time.
2891          */
2892         msleep(250);
2893         if (strstr(sp->product_name, "CX4")) {
2894                 msleep(750);
2895         }
2896
2897         /* Restore the PCI state saved during initialization. */
2898         pci_restore_state(sp->pdev);
2899         pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
2900                                      pci_cmd);
2901         s2io_init_pci(sp);
2902
2903         msleep(250);
2904
2905         /* Set swapper to enable I/O register access */
2906         s2io_set_swapper(sp);
2907
2908         /* Restore the MSIX table entries from local variables */
2909         restore_xmsi_data(sp);
2910
2911         /* Clear certain PCI/PCI-X fields after reset */
2912         if (sp->device_type == XFRAME_II_DEVICE) {
2913                 /* Clear parity err detect bit */
2914                 pci_write_config_word(sp->pdev, PCI_STATUS, 0x8000);
2915
2916                 /* Clearing PCIX Ecc status register */
2917                 pci_write_config_dword(sp->pdev, 0x68, 0x7C);
2918
2919                 /* Clearing PCI_STATUS error reflected here */
2920                 writeq(BIT(62), &bar0->txpic_int_reg);
2921         }
2922
2923         /* Reset device statistics maintained by OS */
2924         memset(&sp->stats, 0, sizeof (struct net_device_stats));
2925
2926         /* SXE-002: Configure link and activity LED to turn it off */
2927         subid = sp->pdev->subsystem_device;
2928         if (((subid & 0xFF) >= 0x07) &&
2929             (sp->device_type == XFRAME_I_DEVICE)) {
2930                 val64 = readq(&bar0->gpio_control);
2931                 val64 |= 0x0000800000000000ULL;
2932                 writeq(val64, &bar0->gpio_control);
2933                 val64 = 0x0411040400000000ULL;
2934                 writeq(val64, (void __iomem *)bar0 + 0x2700);
2935         }
2936
2937         /*
2938          * Clear spurious ECC interrupts that would have occured on
2939          * XFRAME II cards after reset.
2940          */
2941         if (sp->device_type == XFRAME_II_DEVICE) {
2942                 val64 = readq(&bar0->pcc_err_reg);
2943                 writeq(val64, &bar0->pcc_err_reg);
2944         }
2945
2946         sp->device_enabled_once = FALSE;
2947 }
2948
2949 /**
2950  *  s2io_set_swapper - to set the swapper controle on the card
2951  *  @sp : private member of the device structure,
2952  *  pointer to the s2io_nic structure.
2953  *  Description: Function to set the swapper control on the card
2954  *  correctly depending on the 'endianness' of the system.
2955  *  Return value:
2956  *  SUCCESS on success and FAILURE on failure.
2957  */
2958
2959 static int s2io_set_swapper(nic_t * sp)
2960 {
2961         struct net_device *dev = sp->dev;
2962         XENA_dev_config_t __iomem *bar0 = sp->bar0;
2963         u64 val64, valt, valr;
2964
2965         /*
2966          * Set proper endian settings and verify the same by reading
2967          * the PIF Feed-back register.
2968          */
2969
2970         val64 = readq(&bar0->pif_rd_swapper_fb);
2971         if (val64 != 0x0123456789ABCDEFULL) {
2972                 int i = 0;
2973                 u64 value[] = { 0xC30000C3C30000C3ULL,   /* FE=1, SE=1 */
2974                                 0x8100008181000081ULL,  /* FE=1, SE=0 */
2975                                 0x4200004242000042ULL,  /* FE=0, SE=1 */
2976                                 0};                     /* FE=0, SE=0 */
2977
2978                 while(i<4) {
2979                         writeq(value[i], &bar0->swapper_ctrl);
2980                         val64 = readq(&bar0->pif_rd_swapper_fb);
2981                         if (val64 == 0x0123456789ABCDEFULL)
2982                                 break;
2983                         i++;
2984                 }
2985                 if (i == 4) {
2986                         DBG_PRINT(ERR_DBG, "%s: Endian settings are wrong, ",
2987                                 dev->name);
2988                         DBG_PRINT(ERR_DBG, "feedback read %llx\n",
2989                                 (unsigned long long) val64);
2990                         return FAILURE;
2991                 }
2992                 valr = value[i];
2993         } else {
2994                 valr = readq(&bar0->swapper_ctrl);
2995         }
2996
2997         valt = 0x0123456789ABCDEFULL;
2998         writeq(valt, &bar0->xmsi_address);
2999         val64 = readq(&bar0->xmsi_address);
3000
3001         if(val64 != valt) {
3002                 int i = 0;
3003                 u64 value[] = { 0x00C3C30000C3C300ULL,  /* FE=1, SE=1 */
3004                                 0x0081810000818100ULL,  /* FE=1, SE=0 */
3005                                 0x0042420000424200ULL,  /* FE=0, SE=1 */
3006                                 0};                     /* FE=0, SE=0 */
3007
3008                 while(i<4) {
3009                         writeq((value[i] | valr), &bar0->swapper_ctrl);
3010                         writeq(valt, &bar0->xmsi_address);
3011                         val64 = readq(&bar0->xmsi_address);
3012                         if(val64 == valt)
3013                                 break;
3014                         i++;
3015                 }
3016                 if(i == 4) {
3017                         unsigned long long x = val64;
3018                         DBG_PRINT(ERR_DBG, "Write failed, Xmsi_addr ");
3019                         DBG_PRINT(ERR_DBG, "reads:0x%llx\n", x);
3020                         return FAILURE;
3021                 }
3022         }
3023         val64 = readq(&bar0->swapper_ctrl);
3024         val64 &= 0xFFFF000000000000ULL;
3025
3026 #ifdef  __BIG_ENDIAN
3027         /*
3028          * The device by default set to a big endian format, so a
3029          * big endian driver need not set anything.
3030          */
3031         val64 |= (SWAPPER_CTRL_TXP_FE |
3032                  SWAPPER_CTRL_TXP_SE |
3033                  SWAPPER_CTRL_TXD_R_FE |
3034                  SWAPPER_CTRL_TXD_W_FE |
3035                  SWAPPER_CTRL_TXF_R_FE |
3036                  SWAPPER_CTRL_RXD_R_FE |
3037                  SWAPPER_CTRL_RXD_W_FE |
3038                  SWAPPER_CTRL_RXF_W_FE |
3039                  SWAPPER_CTRL_XMSI_FE |
3040                  SWAPPER_CTRL_STATS_FE | SWAPPER_CTRL_STATS_SE);
3041         if (sp->intr_type == INTA)
3042                 val64 |= SWAPPER_CTRL_XMSI_SE;
3043         writeq(val64, &bar0->swapper_ctrl);
3044 #else
3045         /*
3046          * Initially we enable all bits to make it accessible by the
3047          * driver, then we selectively enable only those bits that
3048          * we want to set.
3049          */
3050         val64 |= (SWAPPER_CTRL_TXP_FE |
3051                  SWAPPER_CTRL_TXP_SE |
3052                  SWAPPER_CTRL_TXD_R_FE |
3053                  SWAPPER_CTRL_TXD_R_SE |
3054                  SWAPPER_CTRL_TXD_W_FE |
3055                  SWAPPER_CTRL_TXD_W_SE |
3056                  SWAPPER_CTRL_TXF_R_FE |
3057                  SWAPPER_CTRL_RXD_R_FE |
3058                  SWAPPER_CTRL_RXD_R_SE |
3059                  SWAPPER_CTRL_RXD_W_FE |
3060                  SWAPPER_CTRL_RXD_W_SE |
3061                  SWAPPER_CTRL_RXF_W_FE |
3062                  SWAPPER_CTRL_XMSI_FE |
3063                  SWAPPER_CTRL_STATS_FE | SWAPPER_CTRL_STATS_SE);
3064         if (sp->intr_type == INTA)
3065                 val64 |= SWAPPER_CTRL_XMSI_SE;
3066         writeq(val64, &bar0->swapper_ctrl);
3067 #endif
3068         val64 = readq(&bar0->swapper_ctrl);
3069
3070         /*
3071          * Verifying if endian settings are accurate by reading a
3072          * feedback register.
3073          */
3074         val64 = readq(&bar0->pif_rd_swapper_fb);
3075         if (val64 != 0x0123456789ABCDEFULL) {
3076                 /* Endian settings are incorrect, calls for another dekko. */
3077                 DBG_PRINT(ERR_DBG, "%s: Endian settings are wrong, ",
3078                           dev->name);
3079                 DBG_PRINT(ERR_DBG, "feedback read %llx\n",
3080                           (unsigned long long) val64);
3081                 return FAILURE;
3082         }
3083
3084         return SUCCESS;
3085 }
3086
3087 static int wait_for_msix_trans(nic_t *nic, int i)
3088 {
3089         XENA_dev_config_t __iomem *bar0 = nic->bar0;
3090         u64 val64;
3091         int ret = 0, cnt = 0;
3092
3093         do {
3094                 val64 = readq(&bar0->xmsi_access);
3095                 if (!(val64 & BIT(15)))
3096                         break;
3097                 mdelay(1);
3098                 cnt++;
3099         } while(cnt < 5);
3100         if (cnt == 5) {
3101                 DBG_PRINT(ERR_DBG, "XMSI # %d Access failed\n", i);
3102                 ret = 1;
3103         }
3104
3105         return ret;
3106 }
3107
3108 static void restore_xmsi_data(nic_t *nic)
3109 {
3110         XENA_dev_config_t __iomem *bar0 = nic->bar0;
3111         u64 val64;
3112         int i;
3113
3114         for (i=0; i< nic->avail_msix_vectors; i++) {
3115                 writeq(nic->msix_info[i].addr, &bar0->xmsi_address);
3116                 writeq(nic->msix_info[i].data, &bar0->xmsi_data);
3117                 val64 = (BIT(7) | BIT(15) | vBIT(i, 26, 6));
3118                 writeq(val64, &bar0->xmsi_access);
3119                 if (wait_for_msix_trans(nic, i)) {
3120                         DBG_PRINT(ERR_DBG, "failed in %s\n", __FUNCTION__);
3121                         continue;
3122                 }
3123         }
3124 }
3125
3126 static void store_xmsi_data(nic_t *nic)
3127 {
3128         XENA_dev_config_t __iomem *bar0 = nic->bar0;
3129         u64 val64, addr, data;
3130         int i;
3131
3132         /* Store and display */
3133         for (i=0; i< nic->avail_msix_vectors; i++) {
3134                 val64 = (BIT(15) | vBIT(i, 26, 6));
3135                 writeq(val64, &bar0->xmsi_access);
3136                 if (wait_for_msix_trans(nic, i)) {
3137                         DBG_PRINT(ERR_DBG, "failed in %s\n", __FUNCTION__);
3138                         continue;
3139                 }
3140                 addr = readq(&bar0->xmsi_address);
3141                 data = readq(&bar0->xmsi_data);
3142                 if (addr && data) {
3143                         nic->msix_info[i].addr = addr;
3144                         nic->msix_info[i].data = data;
3145                 }
3146         }
3147 }
3148
3149 int s2io_enable_msi(nic_t *nic)
3150 {
3151         XENA_dev_config_t __iomem *bar0 = nic->bar0;
3152         u16 msi_ctrl, msg_val;
3153         struct config_param *config = &nic->config;
3154         struct net_device *dev = nic->dev;
3155         u64 val64, tx_mat, rx_mat;
3156         int i, err;
3157
3158         val64 = readq(&bar0->pic_control);
3159         val64 &= ~BIT(1);
3160         writeq(val64, &bar0->pic_control);
3161
3162         err = pci_enable_msi(nic->pdev);
3163         if (err) {
3164                 DBG_PRINT(ERR_DBG, "%s: enabling MSI failed\n",
3165                           nic->dev->name);
3166                 return err;
3167         }
3168
3169         /*
3170          * Enable MSI and use MSI-1 in stead of the standard MSI-0
3171          * for interrupt handling.
3172          */
3173         pci_read_config_word(nic->pdev, 0x4c, &msg_val);
3174         msg_val ^= 0x1;
3175         pci_write_config_word(nic->pdev, 0x4c, msg_val);
3176         pci_read_config_word(nic->pdev, 0x4c, &msg_val);
3177
3178         pci_read_config_word(nic->pdev, 0x42, &msi_ctrl);
3179         msi_ctrl |= 0x10;
3180         pci_write_config_word(nic->pdev, 0x42, msi_ctrl);
3181
3182         /* program MSI-1 into all usable Tx_Mat and Rx_Mat fields */
3183         tx_mat = readq(&bar0->tx_mat0_n[0]);
3184         for (i=0; i<config->tx_fifo_num; i++) {
3185                 tx_mat |= TX_MAT_SET(i, 1);
3186         }
3187         writeq(tx_mat, &bar0->tx_mat0_n[0]);
3188
3189         rx_mat = readq(&bar0->rx_mat);
3190         for (i=0; i<config->rx_ring_num; i++) {
3191                 rx_mat |= RX_MAT_SET(i, 1);
3192         }
3193         writeq(rx_mat, &bar0->rx_mat);
3194
3195         dev->irq = nic->pdev->irq;
3196         return 0;
3197 }
3198
3199 static int s2io_enable_msi_x(nic_t *nic)
3200 {
3201         XENA_dev_config_t __iomem *bar0 = nic->bar0;
3202         u64 tx_mat, rx_mat;
3203         u16 msi_control; /* Temp variable */
3204         int ret, i, j, msix_indx = 1;
3205
3206         nic->entries = kmalloc(MAX_REQUESTED_MSI_X * sizeof(struct msix_entry),
3207                                GFP_KERNEL);
3208         if (nic->entries == NULL) {
3209                 DBG_PRINT(ERR_DBG, "%s: Memory allocation failed\n", __FUNCTION__);
3210                 return -ENOMEM;
3211         }
3212         memset(nic->entries, 0, MAX_REQUESTED_MSI_X * sizeof(struct msix_entry));
3213
3214         nic->s2io_entries =
3215                 kmalloc(MAX_REQUESTED_MSI_X * sizeof(struct s2io_msix_entry),
3216                                    GFP_KERNEL);
3217         if (nic->s2io_entries == NULL) {
3218                 DBG_PRINT(ERR_DBG, "%s: Memory allocation failed\n", __FUNCTION__);
3219                 kfree(nic->entries);
3220                 return -ENOMEM;
3221         }
3222         memset(nic->s2io_entries, 0,
3223                MAX_REQUESTED_MSI_X * sizeof(struct s2io_msix_entry));
3224
3225         for (i=0; i< MAX_REQUESTED_MSI_X; i++) {
3226                 nic->entries[i].entry = i;
3227                 nic->s2io_entries[i].entry = i;
3228                 nic->s2io_entries[i].arg = NULL;
3229                 nic->s2io_entries[i].in_use = 0;
3230         }
3231
3232         tx_mat = readq(&bar0->tx_mat0_n[0]);
3233         for (i=0; i<nic->config.tx_fifo_num; i++, msix_indx++) {
3234                 tx_mat |= TX_MAT_SET(i, msix_indx);
3235                 nic->s2io_entries[msix_indx].arg = &nic->mac_control.fifos[i];
3236                 nic->s2io_entries[msix_indx].type = MSIX_FIFO_TYPE;
3237                 nic->s2io_entries[msix_indx].in_use = MSIX_FLG;
3238         }
3239         writeq(tx_mat, &bar0->tx_mat0_n[0]);
3240
3241         if (!nic->config.bimodal) {
3242                 rx_mat = readq(&bar0->rx_mat);
3243                 for (j=0; j<nic->config.rx_ring_num; j++, msix_indx++) {
3244                         rx_mat |= RX_MAT_SET(j, msix_indx);
3245                         nic->s2io_entries[msix_indx].arg = &nic->mac_control.rings[j];
3246                         nic->s2io_entries[msix_indx].type = MSIX_RING_TYPE;
3247                         nic->s2io_entries[msix_indx].in_use = MSIX_FLG;
3248                 }
3249                 writeq(rx_mat, &bar0->rx_mat);
3250         } else {
3251                 tx_mat = readq(&bar0->tx_mat0_n[7]);
3252                 for (j=0; j<nic->config.rx_ring_num; j++, msix_indx++) {
3253                         tx_mat |= TX_MAT_SET(i, msix_indx);
3254                         nic->s2io_entries[msix_indx].arg = &nic->mac_control.rings[j];
3255                         nic->s2io_entries[msix_indx].type = MSIX_RING_TYPE;
3256                         nic->s2io_entries[msix_indx].in_use = MSIX_FLG;
3257                 }
3258                 writeq(tx_mat, &bar0->tx_mat0_n[7]);
3259         }
3260
3261         nic->avail_msix_vectors = 0;
3262         ret = pci_enable_msix(nic->pdev, nic->entries, MAX_REQUESTED_MSI_X);
3263         /* We fail init if error or we get less vectors than min required */
3264         if (ret >= (nic->config.tx_fifo_num + nic->config.rx_ring_num + 1)) {
3265                 nic->avail_msix_vectors = ret;
3266                 ret = pci_enable_msix(nic->pdev, nic->entries, ret);
3267         }
3268         if (ret) {
3269                 DBG_PRINT(ERR_DBG, "%s: Enabling MSIX failed\n", nic->dev->name);
3270                 kfree(nic->entries);
3271                 kfree(nic->s2io_entries);
3272                 nic->entries = NULL;
3273                 nic->s2io_entries = NULL;
3274                 nic->avail_msix_vectors = 0;
3275                 return -ENOMEM;
3276         }
3277         if (!nic->avail_msix_vectors)
3278                 nic->avail_msix_vectors = MAX_REQUESTED_MSI_X;
3279
3280         /*
3281          * To enable MSI-X, MSI also needs to be enabled, due to a bug
3282          * in the herc NIC. (Temp change, needs to be removed later)
3283          */
3284         pci_read_config_word(nic->pdev, 0x42, &msi_control);
3285         msi_control |= 0x1; /* Enable MSI */
3286         pci_write_config_word(nic->pdev, 0x42, msi_control);
3287
3288         return 0;
3289 }
3290
3291 /* ********************************************************* *
3292  * Functions defined below concern the OS part of the driver *
3293  * ********************************************************* */
3294
3295 /**
3296  *  s2io_open - open entry point of the driver
3297  *  @dev : pointer to the device structure.
3298  *  Description:
3299  *  This function is the open entry point of the driver. It mainly calls a
3300  *  function to allocate Rx buffers and inserts them into the buffer
3301  *  descriptors and then enables the Rx part of the NIC.
3302  *  Return value:
3303  *  0 on success and an appropriate (-)ve integer as defined in errno.h
3304  *   file on failure.
3305  */
3306
3307 static int s2io_open(struct net_device *dev)
3308 {
3309         nic_t *sp = dev->priv;
3310         int err = 0;
3311
3312         /*
3313          * Make sure you have link off by default every time
3314          * Nic is initialized
3315          */
3316         netif_carrier_off(dev);
3317         sp->last_link_state = 0;
3318
3319         /* Initialize H/W and enable interrupts */
3320         err = s2io_card_up(sp);
3321         if (err) {
3322                 DBG_PRINT(ERR_DBG, "%s: H/W initialization failed\n",
3323                           dev->name);
3324                 if (err == -ENODEV)
3325                         goto hw_init_failed;
3326                 else
3327                         goto hw_enable_failed;
3328         }
3329
3330         /* Store the values of the MSIX table in the nic_t structure */
3331         store_xmsi_data(sp);
3332
3333         /* After proper initialization of H/W, register ISR */
3334         if (sp->intr_type == MSI) {
3335                 err = request_irq((int) sp->pdev->irq, s2io_msi_handle,
3336                         SA_SHIRQ, sp->name, dev);
3337                 if (err) {
3338                         DBG_PRINT(ERR_DBG, "%s: MSI registration \
3339 failed\n", dev->name);
3340                         goto isr_registration_failed;
3341                 }
3342         }
3343         if (sp->intr_type == MSI_X) {
3344                 int i;
3345
3346                 for (i=1; (sp->s2io_entries[i].in_use == MSIX_FLG); i++) {
3347                         if (sp->s2io_entries[i].type == MSIX_FIFO_TYPE) {
3348                                 sprintf(sp->desc1, "%s:MSI-X-%d-TX",
3349                                         dev->name, i);
3350                                 err = request_irq(sp->entries[i].vector,
3351                                           s2io_msix_fifo_handle, 0, sp->desc1,
3352                                           sp->s2io_entries[i].arg);
3353                                 DBG_PRINT(ERR_DBG, "%s @ 0x%llx\n", sp->desc1,
3354                                     (unsigned long long)sp->msix_info[i].addr);
3355                         } else {
3356                                 sprintf(sp->desc2, "%s:MSI-X-%d-RX",
3357                                         dev->name, i);
3358                                 err = request_irq(sp->entries[i].vector,
3359                                           s2io_msix_ring_handle, 0, sp->desc2,
3360                                           sp->s2io_entries[i].arg);
3361                                 DBG_PRINT(ERR_DBG, "%s @ 0x%llx\n", sp->desc2,
3362                                      (unsigned long long)sp->msix_info[i].addr);
3363                         }
3364                         if (err) {
3365                                 DBG_PRINT(ERR_DBG, "%s: MSI-X-%d registration \
3366 failed\n", dev->name, i);
3367                                 DBG_PRINT(ERR_DBG, "Returned: %d\n", err);
3368                                 goto isr_registration_failed;
3369                         }
3370                         sp->s2io_entries[i].in_use = MSIX_REGISTERED_SUCCESS;
3371                 }
3372         }
3373         if (sp->intr_type == INTA) {
3374                 err = request_irq((int) sp->pdev->irq, s2io_isr, SA_SHIRQ,
3375                                 sp->name, dev);
3376                 if (err) {
3377                         DBG_PRINT(ERR_DBG, "%s: ISR registration failed\n",
3378                                   dev->name);
3379                         goto isr_registration_failed;
3380                 }
3381         }
3382
3383         if (s2io_set_mac_addr(dev, dev->dev_addr) == FAILURE) {
3384                 DBG_PRINT(ERR_DBG, "Set Mac Address Failed\n");
3385                 err = -ENODEV;
3386                 goto setting_mac_address_failed;
3387         }
3388
3389         netif_start_queue(dev);
3390         return 0;
3391
3392 setting_mac_address_failed:
3393         if (sp->intr_type != MSI_X)
3394                 free_irq(sp->pdev->irq, dev);
3395 isr_registration_failed:
3396         del_timer_sync(&sp->alarm_timer);
3397         if (sp->intr_type == MSI_X) {
3398                 int i;
3399                 u16 msi_control; /* Temp variable */
3400                 for (i=1; (sp->s2io_entries[i].in_use ==
3401                                 MSIX_REGISTERED_SUCCESS); i++) {
3402                         int vector = sp->entries[i].vector;
3403                         void *arg = sp->s2io_entries[i].arg;
3404
3405                         free_irq(vector, arg);
3406                 }
3407                 pci_disable_msix(sp->pdev);
3408
3409                 /* Temp */
3410                 pci_read_config_word(sp->pdev, 0x42, &msi_control);
3411                 msi_control &= 0xFFFE; /* Disable MSI */
3412                 pci_write_config_word(sp->pdev, 0x42, msi_control);
3413         }
3414         else if (sp->intr_type == MSI)
3415                 pci_disable_msi(sp->pdev);
3416 hw_enable_failed:
3417         s2io_reset(sp);
3418 hw_init_failed:
3419         if (sp->intr_type == MSI_X) {
3420                 if (sp->entries)
3421                         kfree(sp->entries);
3422                 if (sp->s2io_entries)
3423                         kfree(sp->s2io_entries);
3424         }
3425         return err;
3426 }
3427
3428 /**
3429  *  s2io_close -close entry point of the driver
3430  *  @dev : device pointer.
3431  *  Description:
3432  *  This is the stop entry point of the driver. It needs to undo exactly
3433  *  whatever was done by the open entry point,thus it's usually referred to
3434  *  as the close function.Among other things this function mainly stops the
3435  *  Rx side of the NIC and frees all the Rx buffers in the Rx rings.
3436  *  Return value:
3437  *  0 on success and an appropriate (-)ve integer as defined in errno.h
3438  *  file on failure.
3439  */
3440
3441 static int s2io_close(struct net_device *dev)
3442 {
3443         nic_t *sp = dev->priv;
3444
3445         flush_scheduled_work();
3446         netif_stop_queue(dev);
3447         /* Reset card, kill tasklet and free Tx and Rx buffers. */
3448         s2io_card_down(sp, 1);
3449
3450         sp->device_close_flag = TRUE;   /* Device is shut down. */
3451         return 0;
3452 }
3453
3454 /**
3455  *  s2io_xmit - Tx entry point of te driver
3456  *  @skb : the socket buffer containing the Tx data.
3457  *  @dev : device pointer.
3458  *  Description :
3459  *  This function is the Tx entry point of the driver. S2IO NIC supports
3460  *  certain protocol assist features on Tx side, namely  CSO, S/G, LSO.
3461  *  NOTE: when device cant queue the pkt,just the trans_start variable will
3462  *  not be upadted.
3463  *  Return value:
3464  *  0 on success & 1 on failure.
3465  */
3466
3467 static int s2io_xmit(struct sk_buff *skb, struct net_device *dev)
3468 {
3469         nic_t *sp = dev->priv;
3470         u16 frg_cnt, frg_len, i, queue, queue_len, put_off, get_off;
3471         register u64 val64;
3472         TxD_t *txdp;
3473         TxFIFO_element_t __iomem *tx_fifo;
3474         unsigned long flags;
3475 #ifdef NETIF_F_TSO
3476         int mss;
3477 #endif
3478         u16 vlan_tag = 0;
3479         int vlan_priority = 0;
3480         mac_info_t *mac_control;
3481         struct config_param *config;
3482
3483         mac_control = &sp->mac_control;
3484         config = &sp->config;
3485
3486         DBG_PRINT(TX_DBG, "%s: In Neterion Tx routine\n", dev->name);
3487         spin_lock_irqsave(&sp->tx_lock, flags);
3488         if (atomic_read(&sp->card_state) == CARD_DOWN) {
3489                 DBG_PRINT(TX_DBG, "%s: Card going down for reset\n",
3490                           dev->name);
3491                 spin_unlock_irqrestore(&sp->tx_lock, flags);
3492                 dev_kfree_skb(skb);
3493                 return 0;
3494         }
3495
3496         queue = 0;
3497
3498         /* Get Fifo number to Transmit based on vlan priority */
3499         if (sp->vlgrp && vlan_tx_tag_present(skb)) {
3500                 vlan_tag = vlan_tx_tag_get(skb);
3501                 vlan_priority = vlan_tag >> 13;
3502                 queue = config->fifo_mapping[vlan_priority];
3503         }
3504
3505         put_off = (u16) mac_control->fifos[queue].tx_curr_put_info.offset;
3506         get_off = (u16) mac_control->fifos[queue].tx_curr_get_info.offset;
3507         txdp = (TxD_t *) mac_control->fifos[queue].list_info[put_off].
3508                 list_virt_addr;
3509
3510         queue_len = mac_control->fifos[queue].tx_curr_put_info.fifo_len + 1;
3511         /* Avoid "put" pointer going beyond "get" pointer */
3512         if (txdp->Host_Control ||
3513                    ((put_off+1) == queue_len ? 0 : (put_off+1)) == get_off) {
3514                 DBG_PRINT(TX_DBG, "Error in xmit, No free TXDs.\n");
3515                 netif_stop_queue(dev);
3516                 dev_kfree_skb(skb);
3517                 spin_unlock_irqrestore(&sp->tx_lock, flags);
3518                 return 0;
3519         }
3520
3521         /* A buffer with no data will be dropped */
3522         if (!skb->len) {
3523                 DBG_PRINT(TX_DBG, "%s:Buffer has no data..\n", dev->name);
3524                 dev_kfree_skb(skb);
3525                 spin_unlock_irqrestore(&sp->tx_lock, flags);
3526                 return 0;
3527         }
3528
3529         txdp->Control_1 = 0;
3530         txdp->Control_2 = 0;
3531 #ifdef NETIF_F_TSO
3532         mss = skb_shinfo(skb)->tso_size;
3533         if (mss) {
3534                 txdp->Control_1 |= TXD_TCP_LSO_EN;
3535                 txdp->Control_1 |= TXD_TCP_LSO_MSS(mss);
3536         }
3537 #endif
3538         if (skb->ip_summed == CHECKSUM_HW) {
3539                 txdp->Control_2 |=
3540                     (TXD_TX_CKO_IPV4_EN | TXD_TX_CKO_TCP_EN |
3541                      TXD_TX_CKO_UDP_EN);
3542         }
3543         txdp->Control_1 |= TXD_GATHER_CODE_FIRST;
3544         txdp->Control_1 |= TXD_LIST_OWN_XENA;
3545         txdp->Control_2 |= config->tx_intr_type;
3546
3547         if (sp->vlgrp && vlan_tx_tag_present(skb)) {
3548                 txdp->Control_2 |= TXD_VLAN_ENABLE;
3549                 txdp->Control_2 |= TXD_VLAN_TAG(vlan_tag);
3550         }
3551
3552         frg_len = skb->len - skb->data_len;
3553         if (skb_shinfo(skb)->ufo_size) {
3554                 int ufo_size;
3555
3556                 ufo_size = skb_shinfo(skb)->ufo_size;
3557                 ufo_size &= ~7;
3558                 txdp->Control_1 |= TXD_UFO_EN;
3559                 txdp->Control_1 |= TXD_UFO_MSS(ufo_size);
3560                 txdp->Control_1 |= TXD_BUFFER0_SIZE(8);
3561 #ifdef __BIG_ENDIAN
3562                 sp->ufo_in_band_v[put_off] =
3563                                 (u64)skb_shinfo(skb)->ip6_frag_id;
3564 #else
3565                 sp->ufo_in_band_v[put_off] =
3566                                 (u64)skb_shinfo(skb)->ip6_frag_id << 32;
3567 #endif
3568                 txdp->Host_Control = (unsigned long)sp->ufo_in_band_v;
3569                 txdp->Buffer_Pointer = pci_map_single(sp->pdev,
3570                                         sp->ufo_in_band_v,
3571                                         sizeof(u64), PCI_DMA_TODEVICE);
3572                 txdp++;
3573                 txdp->Control_1 = 0;
3574                 txdp->Control_2 = 0;
3575         }
3576
3577         txdp->Buffer_Pointer = pci_map_single
3578             (sp->pdev, skb->data, frg_len, PCI_DMA_TODEVICE);
3579         txdp->Host_Control = (unsigned long) skb;
3580         txdp->Control_1 |= TXD_BUFFER0_SIZE(frg_len);
3581
3582         if (skb_shinfo(skb)->ufo_size)
3583                 txdp->Control_1 |= TXD_UFO_EN;
3584
3585         frg_cnt = skb_shinfo(skb)->nr_frags;
3586         /* For fragmented SKB. */
3587         for (i = 0; i < frg_cnt; i++) {
3588                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
3589                 /* A '0' length fragment will be ignored */
3590                 if (!frag->size)
3591                         continue;
3592                 txdp++;
3593                 txdp->Buffer_Pointer = (u64) pci_map_page
3594                     (sp->pdev, frag->page, frag->page_offset,
3595                      frag->size, PCI_DMA_TODEVICE);
3596                 txdp->Control_1 = TXD_BUFFER0_SIZE(frag->size);
3597                 if (skb_shinfo(skb)->ufo_size)
3598                         txdp->Control_1 |= TXD_UFO_EN;
3599         }
3600         txdp->Control_1 |= TXD_GATHER_CODE_LAST;
3601
3602         if (skb_shinfo(skb)->ufo_size)
3603                 frg_cnt++; /* as Txd0 was used for inband header */
3604
3605         tx_fifo = mac_control->tx_FIFO_start[queue];
3606         val64 = mac_control->fifos[queue].list_info[put_off].list_phy_addr;
3607         writeq(val64, &tx_fifo->TxDL_Pointer);
3608
3609         val64 = (TX_FIFO_LAST_TXD_NUM(frg_cnt) | TX_FIFO_FIRST_LIST |
3610                  TX_FIFO_LAST_LIST);
3611
3612 #ifdef NETIF_F_TSO
3613         if (mss)
3614                 val64 |= TX_FIFO_SPECIAL_FUNC;
3615 #endif
3616         if (skb_shinfo(skb)->ufo_size)
3617                 val64 |= TX_FIFO_SPECIAL_FUNC;
3618         writeq(val64, &tx_fifo->List_Control);
3619
3620         mmiowb();
3621
3622         put_off++;
3623         if (put_off == mac_control->fifos[queue].tx_curr_put_info.fifo_len + 1)
3624                 put_off = 0;
3625         mac_control->fifos[queue].tx_curr_put_info.offset = put_off;
3626
3627         /* Avoid "put" pointer going beyond "get" pointer */
3628         if (((put_off+1) == queue_len ? 0 : (put_off+1)) == get_off) {
3629                 DBG_PRINT(TX_DBG,
3630                           "No free TxDs for xmit, Put: 0x%x Get:0x%x\n",
3631                           put_off, get_off);
3632                 netif_stop_queue(dev);
3633         }
3634
3635         dev->trans_start = jiffies;
3636         spin_unlock_irqrestore(&sp->tx_lock, flags);
3637
3638         return 0;
3639 }
3640
3641 static void
3642 s2io_alarm_handle(unsigned long data)
3643 {
3644         nic_t *sp = (nic_t *)data;
3645
3646         alarm_intr_handler(sp);
3647         mod_timer(&sp->alarm_timer, jiffies + HZ / 2);
3648 }
3649
3650 static irqreturn_t
3651 s2io_msi_handle(int irq, void *dev_id, struct pt_regs *regs)
3652 {
3653         struct net_device *dev = (struct net_device *) dev_id;
3654         nic_t *sp = dev->priv;
3655         int i;
3656         int ret;
3657         mac_info_t *mac_control;
3658         struct config_param *config;
3659
3660         atomic_inc(&sp->isr_cnt);
3661         mac_control = &sp->mac_control;
3662         config = &sp->config;
3663         DBG_PRINT(INTR_DBG, "%s: MSI handler\n", __FUNCTION__);
3664
3665         /* If Intr is because of Rx Traffic */
3666         for (i = 0; i < config->rx_ring_num; i++)
3667                 rx_intr_handler(&mac_control->rings[i]);
3668
3669         /* If Intr is because of Tx Traffic */
3670         for (i = 0; i < config->tx_fifo_num; i++)
3671                 tx_intr_handler(&mac_control->fifos[i]);
3672
3673         /*
3674          * If the Rx buffer count is below the panic threshold then
3675          * reallocate the buffers from the interrupt handler itself,
3676          * else schedule a tasklet to reallocate the buffers.
3677          */
3678         for (i = 0; i < config->rx_ring_num; i++) {
3679                 if (!sp->lro) {
3680                         int rxb_size = atomic_read(&sp->rx_bufs_left[i]);
3681                         int level = rx_buffer_level(sp, rxb_size, i);
3682
3683                         if ((level == PANIC) && (!TASKLET_IN_USE)) {
3684                                 DBG_PRINT(INTR_DBG, "%s: Rx BD hit ",
3685                                                         dev->name);
3686                                 DBG_PRINT(INTR_DBG, "PANIC levels\n");
3687                                 if ((ret = fill_rx_buffers(sp, i)) == -ENOMEM) {
3688                                         DBG_PRINT(ERR_DBG, "%s:Out of memory",
3689                                                   dev->name);
3690                                         DBG_PRINT(ERR_DBG, " in ISR!!\n");
3691                                         clear_bit(0, (&sp->tasklet_status));
3692                                         atomic_dec(&sp->isr_cnt);
3693                                         return IRQ_HANDLED;
3694                                 }
3695                                 clear_bit(0, (&sp->tasklet_status));
3696                         } else if (level == LOW) {
3697                                 tasklet_schedule(&sp->task);
3698                         }
3699                 }
3700                 else if (fill_rx_buffers(sp, i) == -ENOMEM) {
3701                                 DBG_PRINT(ERR_DBG, "%s:Out of memory",
3702                                                         dev->name);
3703                                 DBG_PRINT(ERR_DBG, " in Rx Intr!!\n");
3704                                 break;
3705                 }
3706         }
3707
3708         atomic_dec(&sp->isr_cnt);
3709         return IRQ_HANDLED;
3710 }
3711
3712 static irqreturn_t
3713 s2io_msix_ring_handle(int irq, void *dev_id, struct pt_regs *regs)
3714 {
3715         ring_info_t *ring = (ring_info_t *)dev_id;
3716         nic_t *sp = ring->nic;
3717         struct net_device *dev = (struct net_device *) dev_id;
3718         int rxb_size, level, rng_n;
3719
3720         atomic_inc(&sp->isr_cnt);
3721         rx_intr_handler(ring);
3722
3723         rng_n = ring->ring_no;
3724         if (!sp->lro) {
3725                 rxb_size = atomic_read(&sp->rx_bufs_left[rng_n]);
3726                 level = rx_buffer_level(sp, rxb_size, rng_n);
3727
3728                 if ((level == PANIC) && (!TASKLET_IN_USE)) {
3729                         int ret;
3730                         DBG_PRINT(INTR_DBG, "%s: Rx BD hit ", __FUNCTION__);
3731                         DBG_PRINT(INTR_DBG, "PANIC levels\n");
3732                         if ((ret = fill_rx_buffers(sp, rng_n)) == -ENOMEM) {
3733                                 DBG_PRINT(ERR_DBG, "Out of memory in %s",
3734                                           __FUNCTION__);
3735                                 clear_bit(0, (&sp->tasklet_status));
3736                                 return IRQ_HANDLED;
3737                         }
3738                         clear_bit(0, (&sp->tasklet_status));
3739                 } else if (level == LOW) {
3740                         tasklet_schedule(&sp->task);
3741                 }
3742         }
3743         else if (fill_rx_buffers(sp, rng_n) == -ENOMEM) {
3744                         DBG_PRINT(ERR_DBG, "%s:Out of memory", dev->name);
3745                         DBG_PRINT(ERR_DBG, " in Rx Intr!!\n");
3746         }
3747
3748         atomic_dec(&sp->isr_cnt);
3749
3750         return IRQ_HANDLED;
3751 }
3752
3753 static irqreturn_t
3754 s2io_msix_fifo_handle(int irq, void *dev_id, struct pt_regs *regs)
3755 {
3756         fifo_info_t *fifo = (fifo_info_t *)dev_id;
3757         nic_t *sp = fifo->nic;
3758
3759         atomic_inc(&sp->isr_cnt);
3760         tx_intr_handler(fifo);
3761         atomic_dec(&sp->isr_cnt);
3762         return IRQ_HANDLED;
3763 }
3764
3765 static void s2io_txpic_intr_handle(nic_t *sp)
3766 {
3767         XENA_dev_config_t __iomem *bar0 = sp->bar0;
3768         u64 val64;
3769
3770         val64 = readq(&bar0->pic_int_status);
3771         if (val64 & PIC_INT_GPIO) {
3772                 val64 = readq(&bar0->gpio_int_reg);
3773                 if ((val64 & GPIO_INT_REG_LINK_DOWN) &&
3774                     (val64 & GPIO_INT_REG_LINK_UP)) {
3775                         /*
3776                          * This is unstable state so clear both up/down
3777                          * interrupt and adapter to re-evaluate the link state.
3778                          */
3779                         val64 |=  GPIO_INT_REG_LINK_DOWN;
3780                         val64 |= GPIO_INT_REG_LINK_UP;
3781                         writeq(val64, &bar0->gpio_int_reg);
3782                         val64 = readq(&bar0->gpio_int_mask);
3783                         val64 &= ~(GPIO_INT_MASK_LINK_UP |
3784                                    GPIO_INT_MASK_LINK_DOWN);
3785                         writeq(val64, &bar0->gpio_int_mask);
3786                 }
3787                 else if (val64 & GPIO_INT_REG_LINK_UP) {
3788                         val64 = readq(&bar0->adapter_status);
3789                         if (verify_xena_quiescence(sp, val64,
3790                                                    sp->device_enabled_once)) {
3791                                 /* Enable Adapter */
3792                                 val64 = readq(&bar0->adapter_control);
3793                                 val64 |= ADAPTER_CNTL_EN;
3794                                 writeq(val64, &bar0->adapter_control);
3795                                 val64 |= ADAPTER_LED_ON;
3796                                 writeq(val64, &bar0->adapter_control);
3797                                 if (!sp->device_enabled_once)
3798                                         sp->device_enabled_once = 1;
3799
3800                                 s2io_link(sp, LINK_UP);
3801                                 /*
3802                                  * unmask link down interrupt and mask link-up
3803                                  * intr
3804                                  */
3805                                 val64 = readq(&bar0->gpio_int_mask);
3806                                 val64 &= ~GPIO_INT_MASK_LINK_DOWN;
3807                                 val64 |= GPIO_INT_MASK_LINK_UP;
3808                                 writeq(val64, &bar0->gpio_int_mask);
3809
3810                         }
3811                 }else if (val64 & GPIO_INT_REG_LINK_DOWN) {
3812                         val64 = readq(&bar0->adapter_status);
3813                         if (verify_xena_quiescence(sp, val64,
3814                                                    sp->device_enabled_once)) {
3815                                 s2io_link(sp, LINK_DOWN);
3816                                 /* Link is down so unmaks link up interrupt */
3817                                 val64 = readq(&bar0->gpio_int_mask);
3818                                 val64 &= ~GPIO_INT_MASK_LINK_UP;
3819                                 val64 |= GPIO_INT_MASK_LINK_DOWN;
3820                                 writeq(val64, &bar0->gpio_int_mask);
3821                         }
3822                 }
3823         }
3824         val64 = readq(&bar0->gpio_int_mask);
3825 }
3826
3827 /**
3828  *  s2io_isr - ISR handler of the device .
3829  *  @irq: the irq of the device.
3830  *  @dev_id: a void pointer to the dev structure of the NIC.
3831  *  @pt_regs: pointer to the registers pushed on the stack.
3832  *  Description:  This function is the ISR handler of the device. It
3833  *  identifies the reason for the interrupt and calls the relevant
3834  *  service routines. As a contongency measure, this ISR allocates the
3835  *  recv buffers, if their numbers are below the panic value which is
3836  *  presently set to 25% of the original number of rcv buffers allocated.
3837  *  Return value:
3838  *   IRQ_HANDLED: will be returned if IRQ was handled by this routine
3839  *   IRQ_NONE: will be returned if interrupt is not from our device
3840  */
3841 static irqreturn_t s2io_isr(int irq, void *dev_id, struct pt_regs *regs)
3842 {
3843         struct net_device *dev = (struct net_device *) dev_id;
3844         nic_t *sp = dev->priv;
3845         XENA_dev_config_t __iomem *bar0 = sp->bar0;
3846         int i;
3847         u64 reason = 0, val64;
3848         mac_info_t *mac_control;
3849         struct config_param *config;
3850
3851         atomic_inc(&sp->isr_cnt);
3852         mac_control = &sp->mac_control;
3853         config = &sp->config;
3854
3855         /*
3856          * Identify the cause for interrupt and call the appropriate
3857          * interrupt handler. Causes for the interrupt could be;
3858          * 1. Rx of packet.
3859          * 2. Tx complete.
3860          * 3. Link down.
3861          * 4. Error in any functional blocks of the NIC.
3862          */
3863         reason = readq(&bar0->general_int_status);
3864
3865         if (!reason) {
3866                 /* The interrupt was not raised by Xena. */
3867                 atomic_dec(&sp->isr_cnt);
3868                 return IRQ_NONE;
3869         }
3870
3871         val64 = 0xFFFFFFFFFFFFFFFFULL;
3872 #ifdef CONFIG_S2IO_NAPI
3873         if (reason & GEN_INTR_RXTRAFFIC) {
3874                 if (netif_rx_schedule_prep(dev)) {
3875                         writeq(val64, &bar0->rx_traffic_mask);
3876                         __netif_rx_schedule(dev);
3877                 }
3878         }
3879 #else
3880         /*
3881          * Rx handler is called by default, without checking for the
3882          * cause of interrupt.
3883          * rx_traffic_int reg is an R1 register, writing all 1's
3884          * will ensure that the actual interrupt causing bit get's
3885          * cleared and hence a read can be avoided.
3886          */
3887         writeq(val64, &bar0->rx_traffic_int);
3888         for (i = 0; i < config->rx_ring_num; i++) {
3889                 rx_intr_handler(&mac_control->rings[i]);
3890         }
3891 #endif
3892
3893         /*
3894          * tx_traffic_int reg is an R1 register, writing all 1's
3895          * will ensure that the actual interrupt causing bit get's
3896          * cleared and hence a read can be avoided.
3897          */
3898         writeq(val64, &bar0->tx_traffic_int);
3899
3900         for (i = 0; i < config->tx_fifo_num; i++)
3901                 tx_intr_handler(&mac_control->fifos[i]);
3902
3903         if (reason & GEN_INTR_TXPIC)
3904                 s2io_txpic_intr_handle(sp);
3905         /*
3906          * If the Rx buffer count is below the panic threshold then
3907          * reallocate the buffers from the interrupt handler itself,
3908          * else schedule a tasklet to reallocate the buffers.
3909          */
3910 #ifndef CONFIG_S2IO_NAPI
3911         for (i = 0; i < config->rx_ring_num; i++) {
3912                 if (!sp->lro) {
3913                         int ret;
3914                         int rxb_size = atomic_read(&sp->rx_bufs_left[i]);
3915                         int level = rx_buffer_level(sp, rxb_size, i);
3916
3917                         if ((level == PANIC) && (!TASKLET_IN_USE)) {
3918                                 DBG_PRINT(INTR_DBG, "%s: Rx BD hit ",
3919                                                         dev->name);
3920                                 DBG_PRINT(INTR_DBG, "PANIC levels\n");
3921                                 if ((ret = fill_rx_buffers(sp, i)) == -ENOMEM) {
3922                                         DBG_PRINT(ERR_DBG, "%s:Out of memory",
3923                                                   dev->name);
3924                                         DBG_PRINT(ERR_DBG, " in ISR!!\n");
3925                                         clear_bit(0, (&sp->tasklet_status));
3926                                         atomic_dec(&sp->isr_cnt);
3927                                         return IRQ_HANDLED;
3928                                 }
3929                                 clear_bit(0, (&sp->tasklet_status));
3930                         } else if (level == LOW) {
3931                                 tasklet_schedule(&sp->task);
3932                         }
3933                 }
3934                 else if (fill_rx_buffers(sp, i) == -ENOMEM) {
3935                                 DBG_PRINT(ERR_DBG, "%s:Out of memory",
3936                                                         dev->name);
3937                                 DBG_PRINT(ERR_DBG, " in Rx intr!!\n");
3938                                 break;
3939                 }
3940         }
3941 #endif
3942
3943         atomic_dec(&sp->isr_cnt);
3944         return IRQ_HANDLED;
3945 }
3946
3947 /**
3948  * s2io_updt_stats -
3949  */
3950 static void s2io_updt_stats(nic_t *sp)
3951 {
3952         XENA_dev_config_t __iomem *bar0 = sp->bar0;
3953         u64 val64;
3954         int cnt = 0;
3955
3956         if (atomic_read(&sp->card_state) == CARD_UP) {
3957                 /* Apprx 30us on a 133 MHz bus */
3958                 val64 = SET_UPDT_CLICKS(10) |
3959                         STAT_CFG_ONE_SHOT_EN | STAT_CFG_STAT_EN;
3960                 writeq(val64, &bar0->stat_cfg);
3961                 do {
3962                         udelay(100);
3963                         val64 = readq(&bar0->stat_cfg);
3964                         if (!(val64 & BIT(0)))
3965                                 break;
3966                         cnt++;
3967                         if (cnt == 5)
3968                                 break; /* Updt failed */
3969                 } while(1);
3970         }
3971 }
3972
3973 /**
3974  *  s2io_get_stats - Updates the device statistics structure.
3975  *  @dev : pointer to the device structure.
3976  *  Description:
3977  *  This function updates the device statistics structure in the s2io_nic
3978  *  structure and returns a pointer to the same.
3979  *  Return value:
3980  *  pointer to the updated net_device_stats structure.
3981  */
3982
3983 static struct net_device_stats *s2io_get_stats(struct net_device *dev)
3984 {
3985         nic_t *sp = dev->priv;
3986         mac_info_t *mac_control;
3987         struct config_param *config;
3988
3989
3990         mac_control = &sp->mac_control;
3991         config = &sp->config;
3992
3993         /* Configure Stats for immediate updt */
3994         s2io_updt_stats(sp);
3995
3996         sp->stats.tx_packets =
3997                 le32_to_cpu(mac_control->stats_info->tmac_frms);
3998         sp->stats.tx_errors =
3999                 le32_to_cpu(mac_control->stats_info->tmac_any_err_frms);
4000         sp->stats.rx_errors =
4001                 le32_to_cpu(mac_control->stats_info->rmac_drop_frms);
4002         sp->stats.multicast =
4003                 le32_to_cpu(mac_control->stats_info->rmac_vld_mcst_frms);
4004         sp->stats.rx_length_errors =
4005                 le32_to_cpu(mac_control->stats_info->rmac_long_frms);
4006
4007         return (&sp->stats);
4008 }
4009
4010 /**
4011  *  s2io_set_multicast - entry point for multicast address enable/disable.
4012  *  @dev : pointer to the device structure
4013  *  Description:
4014  *  This function is a driver entry point which gets called by the kernel
4015  *  whenever multicast addresses must be enabled/disabled. This also gets
4016  *  called to set/reset promiscuous mode. Depending on the deivce flag, we
4017  *  determine, if multicast address must be enabled or if promiscuous mode
4018  *  is to be disabled etc.
4019  *  Return value:
4020  *  void.
4021  */
4022
4023 static void s2io_set_multicast(struct net_device *dev)
4024 {
4025         int i, j, prev_cnt;
4026         struct dev_mc_list *mclist;
4027         nic_t *sp = dev->priv;
4028         XENA_dev_config_t __iomem *bar0 = sp->bar0;
4029         u64 val64 = 0, multi_mac = 0x010203040506ULL, mask =
4030             0xfeffffffffffULL;
4031         u64 dis_addr = 0xffffffffffffULL, mac_addr = 0;
4032         void __iomem *add;
4033
4034         if ((dev->flags & IFF_ALLMULTI) && (!sp->m_cast_flg)) {
4035                 /*  Enable all Multicast addresses */
4036                 writeq(RMAC_ADDR_DATA0_MEM_ADDR(multi_mac),
4037                        &bar0->rmac_addr_data0_mem);
4038                 writeq(RMAC_ADDR_DATA1_MEM_MASK(mask),
4039                        &bar0->rmac_addr_data1_mem);
4040                 val64 = RMAC_ADDR_CMD_MEM_WE |
4041                     RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
4042                     RMAC_ADDR_CMD_MEM_OFFSET(MAC_MC_ALL_MC_ADDR_OFFSET);
4043                 writeq(val64, &bar0->rmac_addr_cmd_mem);
4044                 /* Wait till command completes */
4045                 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
4046                                       RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING);
4047
4048                 sp->m_cast_flg = 1;
4049                 sp->all_multi_pos = MAC_MC_ALL_MC_ADDR_OFFSET;
4050         } else if ((dev->flags & IFF_ALLMULTI) && (sp->m_cast_flg)) {
4051                 /*  Disable all Multicast addresses */
4052                 writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr),
4053                        &bar0->rmac_addr_data0_mem);
4054                 writeq(RMAC_ADDR_DATA1_MEM_MASK(0x0),
4055                        &bar0->rmac_addr_data1_mem);
4056                 val64 = RMAC_ADDR_CMD_MEM_WE |
4057                     RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
4058                     RMAC_ADDR_CMD_MEM_OFFSET(sp->all_multi_pos);
4059                 writeq(val64, &bar0->rmac_addr_cmd_mem);
4060                 /* Wait till command completes */
4061                 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
4062                                       RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING);
4063
4064                 sp->m_cast_flg = 0;
4065                 sp->all_multi_pos = 0;
4066         }
4067
4068         if ((dev->flags & IFF_PROMISC) && (!sp->promisc_flg)) {
4069                 /*  Put the NIC into promiscuous mode */
4070                 add = &bar0->mac_cfg;
4071                 val64 = readq(&bar0->mac_cfg);
4072                 val64 |= MAC_CFG_RMAC_PROM_ENABLE;
4073
4074                 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
4075                 writel((u32) val64, add);
4076                 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
4077                 writel((u32) (val64 >> 32), (add + 4));
4078
4079                 val64 = readq(&bar0->mac_cfg);
4080                 sp->promisc_flg = 1;
4081                 DBG_PRINT(INFO_DBG, "%s: entered promiscuous mode\n",
4082                           dev->name);
4083         } else if (!(dev->flags & IFF_PROMISC) && (sp->promisc_flg)) {
4084                 /*  Remove the NIC from promiscuous mode */
4085                 add = &bar0->mac_cfg;
4086                 val64 = readq(&bar0->mac_cfg);
4087                 val64 &= ~MAC_CFG_RMAC_PROM_ENABLE;
4088
4089                 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
4090                 writel((u32) val64, add);
4091                 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
4092                 writel((u32) (val64 >> 32), (add + 4));
4093
4094                 val64 = readq(&bar0->mac_cfg);
4095                 sp->promisc_flg = 0;
4096                 DBG_PRINT(INFO_DBG, "%s: left promiscuous mode\n",
4097                           dev->name);
4098         }
4099
4100         /*  Update individual M_CAST address list */
4101         if ((!sp->m_cast_flg) && dev->mc_count) {
4102                 if (dev->mc_count >
4103                     (MAX_ADDRS_SUPPORTED - MAC_MC_ADDR_START_OFFSET - 1)) {
4104                         DBG_PRINT(ERR_DBG, "%s: No more Rx filters ",
4105                                   dev->name);
4106                         DBG_PRINT(ERR_DBG, "can be added, please enable ");
4107                         DBG_PRINT(ERR_DBG, "ALL_MULTI instead\n");
4108                         return;
4109                 }
4110
4111                 prev_cnt = sp->mc_addr_count;
4112                 sp->mc_addr_count = dev->mc_count;
4113
4114                 /* Clear out the previous list of Mc in the H/W. */
4115                 for (i = 0; i < prev_cnt; i++) {
4116                         writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr),
4117                                &bar0->rmac_addr_data0_mem);
4118                         writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL),
4119                                 &bar0->rmac_addr_data1_mem);
4120                         val64 = RMAC_ADDR_CMD_MEM_WE |
4121                             RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
4122                             RMAC_ADDR_CMD_MEM_OFFSET
4123                             (MAC_MC_ADDR_START_OFFSET + i);
4124                         writeq(val64, &bar0->rmac_addr_cmd_mem);
4125
4126                         /* Wait for command completes */
4127                         if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
4128                                       RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING)) {
4129                                 DBG_PRINT(ERR_DBG, "%s: Adding ",
4130                                           dev->name);
4131                                 DBG_PRINT(ERR_DBG, "Multicasts failed\n");
4132                                 return;
4133                         }
4134                 }
4135
4136                 /* Create the new Rx filter list and update the same in H/W. */
4137                 for (i = 0, mclist = dev->mc_list; i < dev->mc_count;
4138                      i++, mclist = mclist->next) {
4139                         memcpy(sp->usr_addrs[i].addr, mclist->dmi_addr,
4140                                ETH_ALEN);
4141                         mac_addr = 0;
4142                         for (j = 0; j < ETH_ALEN; j++) {
4143                                 mac_addr |= mclist->dmi_addr[j];
4144                                 mac_addr <<= 8;
4145                         }
4146                         mac_addr >>= 8;
4147                         writeq(RMAC_ADDR_DATA0_MEM_ADDR(mac_addr),
4148                                &bar0->rmac_addr_data0_mem);
4149                         writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL),
4150                                 &bar0->rmac_addr_data1_mem);
4151                         val64 = RMAC_ADDR_CMD_MEM_WE |
4152                             RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
4153                             RMAC_ADDR_CMD_MEM_OFFSET
4154                             (i + MAC_MC_ADDR_START_OFFSET);
4155                         writeq(val64, &bar0->rmac_addr_cmd_mem);
4156
4157                         /* Wait for command completes */
4158                         if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
4159                                       RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING)) {
4160                                 DBG_PRINT(ERR_DBG, "%s: Adding ",
4161                                           dev->name);
4162                                 DBG_PRINT(ERR_DBG, "Multicasts failed\n");
4163                                 return;
4164                         }
4165                 }
4166         }
4167 }
4168
4169 /**
4170  *  s2io_set_mac_addr - Programs the Xframe mac address
4171  *  @dev : pointer to the device structure.
4172  *  @addr: a uchar pointer to the new mac address which is to be set.
4173  *  Description : This procedure will program the Xframe to receive
4174  *  frames with new Mac Address
4175  *  Return value: SUCCESS on success and an appropriate (-)ve integer
4176  *  as defined in errno.h file on failure.
4177  */
4178
4179 static int s2io_set_mac_addr(struct net_device *dev, u8 * addr)
4180 {
4181         nic_t *sp = dev->priv;
4182         XENA_dev_config_t __iomem *bar0 = sp->bar0;
4183         register u64 val64, mac_addr = 0;
4184         int i;
4185
4186         /*
4187          * Set the new MAC address as the new unicast filter and reflect this
4188          * change on the device address registered with the OS. It will be
4189          * at offset 0.
4190          */
4191         for (i = 0; i < ETH_ALEN; i++) {
4192                 mac_addr <<= 8;
4193                 mac_addr |= addr[i];
4194         }
4195
4196         writeq(RMAC_ADDR_DATA0_MEM_ADDR(mac_addr),
4197                &bar0->rmac_addr_data0_mem);
4198
4199         val64 =
4200             RMAC_ADDR_CMD_MEM_WE | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
4201             RMAC_ADDR_CMD_MEM_OFFSET(0);
4202         writeq(val64, &bar0->rmac_addr_cmd_mem);
4203         /* Wait till command completes */
4204         if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
4205                       RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING)) {
4206                 DBG_PRINT(ERR_DBG, "%s: set_mac_addr failed\n", dev->name);
4207                 return FAILURE;
4208         }
4209
4210         return SUCCESS;
4211 }
4212
4213 /**
4214  * s2io_ethtool_sset - Sets different link parameters.
4215  * @sp : private member of the device structure, which is a pointer to the  * s2io_nic structure.
4216  * @info: pointer to the structure with parameters given by ethtool to set
4217  * link information.
4218  * Description:
4219  * The function sets different link parameters provided by the user onto
4220  * the NIC.
4221  * Return value:
4222  * 0 on success.
4223 */
4224
4225 static int s2io_ethtool_sset(struct net_device *dev,
4226                              struct ethtool_cmd *info)
4227 {
4228         nic_t *sp = dev->priv;
4229         if ((info->autoneg == AUTONEG_ENABLE) ||
4230             (info->speed != SPEED_10000) || (info->duplex != DUPLEX_FULL))
4231                 return -EINVAL;
4232         else {
4233                 s2io_close(sp->dev);
4234                 s2io_open(sp->dev);
4235         }
4236
4237         return 0;
4238 }
4239
4240 /**
4241  * s2io_ethtol_gset - Return link specific information.
4242  * @sp : private member of the device structure, pointer to the
4243  *      s2io_nic structure.
4244  * @info : pointer to the structure with parameters given by ethtool
4245  * to return link information.
4246  * Description:
4247  * Returns link specific information like speed, duplex etc.. to ethtool.
4248  * Return value :
4249  * return 0 on success.
4250  */
4251
4252 static int s2io_ethtool_gset(struct net_device *dev, struct ethtool_cmd *info)
4253 {
4254         nic_t *sp = dev->priv;
4255         info->supported = (SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE);
4256         info->advertising = (SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE);
4257         info->port = PORT_FIBRE;
4258         /* info->transceiver?? TODO */
4259
4260         if (netif_carrier_ok(sp->dev)) {
4261                 info->speed = 10000;
4262                 info->duplex = DUPLEX_FULL;
4263         } else {
4264                 info->speed = -1;
4265                 info->duplex = -1;
4266         }
4267
4268         info->autoneg = AUTONEG_DISABLE;
4269         return 0;
4270 }
4271
4272 /**
4273  * s2io_ethtool_gdrvinfo - Returns driver specific information.
4274  * @sp : private member of the device structure, which is a pointer to the
4275  * s2io_nic structure.
4276  * @info : pointer to the structure with parameters given by ethtool to
4277  * return driver information.
4278  * Description:
4279  * Returns driver specefic information like name, version etc.. to ethtool.
4280  * Return value:
4281  *  void
4282  */
4283
4284 static void s2io_ethtool_gdrvinfo(struct net_device *dev,
4285                                   struct ethtool_drvinfo *info)
4286 {
4287         nic_t *sp = dev->priv;
4288
4289         strncpy(info->driver, s2io_driver_name, sizeof(info->driver));
4290         strncpy(info->version, s2io_driver_version, sizeof(info->version));
4291         strncpy(info->fw_version, "", sizeof(info->fw_version));
4292         strncpy(info->bus_info, pci_name(sp->pdev), sizeof(info->bus_info));
4293         info->regdump_len = XENA_REG_SPACE;
4294         info->eedump_len = XENA_EEPROM_SPACE;
4295         info->testinfo_len = S2IO_TEST_LEN;
4296         info->n_stats = S2IO_STAT_LEN;
4297 }
4298
4299 /**
4300  *  s2io_ethtool_gregs - dumps the entire space of Xfame into the buffer.
4301  *  @sp: private member of the device structure, which is a pointer to the
4302  *  s2io_nic structure.
4303  *  @regs : pointer to the structure with parameters given by ethtool for
4304  *  dumping the registers.
4305  *  @reg_space: The input argumnet into which all the registers are dumped.
4306  *  Description:
4307  *  Dumps the entire register space of xFrame NIC into the user given
4308  *  buffer area.
4309  * Return value :
4310  * void .
4311 */
4312
4313 static void s2io_ethtool_gregs(struct net_device *dev,
4314                                struct ethtool_regs *regs, void *space)
4315 {
4316         int i;
4317         u64 reg;
4318         u8 *reg_space = (u8 *) space;
4319         nic_t *sp = dev->priv;
4320
4321         regs->len = XENA_REG_SPACE;
4322         regs->version = sp->pdev->subsystem_device;
4323
4324         for (i = 0; i < regs->len; i += 8) {
4325                 reg = readq(sp->bar0 + i);
4326                 memcpy((reg_space + i), &reg, 8);
4327         }
4328 }
4329
4330 /**
4331  *  s2io_phy_id  - timer function that alternates adapter LED.
4332  *  @data : address of the private member of the device structure, which
4333  *  is a pointer to the s2io_nic structure, provided as an u32.
4334  * Description: This is actually the timer function that alternates the
4335  * adapter LED bit of the adapter control bit to set/reset every time on
4336  * invocation. The timer is set for 1/2 a second, hence tha NIC blinks
4337  *  once every second.
4338 */
4339 static void s2io_phy_id(unsigned long data)
4340 {
4341         nic_t *sp = (nic_t *) data;
4342         XENA_dev_config_t __iomem *bar0 = sp->bar0;
4343         u64 val64 = 0;
4344         u16 subid;
4345
4346         subid = sp->pdev->subsystem_device;
4347         if ((sp->device_type == XFRAME_II_DEVICE) ||
4348                    ((subid & 0xFF) >= 0x07)) {
4349                 val64 = readq(&bar0->gpio_control);
4350                 val64 ^= GPIO_CTRL_GPIO_0;
4351                 writeq(val64, &bar0->gpio_control);
4352         } else {
4353                 val64 = readq(&bar0->adapter_control);
4354                 val64 ^= ADAPTER_LED_ON;
4355                 writeq(val64, &bar0->adapter_control);
4356         }
4357
4358         mod_timer(&sp->id_timer, jiffies + HZ / 2);
4359 }
4360
4361 /**
4362  * s2io_ethtool_idnic - To physically identify the nic on the system.
4363  * @sp : private member of the device structure, which is a pointer to the
4364  * s2io_nic structure.
4365  * @id : pointer to the structure with identification parameters given by
4366  * ethtool.
4367  * Description: Used to physically identify the NIC on the system.
4368  * The Link LED will blink for a time specified by the user for
4369  * identification.
4370  * NOTE: The Link has to be Up to be able to blink the LED. Hence
4371  * identification is possible only if it's link is up.
4372  * Return value:
4373  * int , returns 0 on success
4374  */
4375
4376 static int s2io_ethtool_idnic(struct net_device *dev, u32 data)
4377 {
4378         u64 val64 = 0, last_gpio_ctrl_val;
4379         nic_t *sp = dev->priv;
4380         XENA_dev_config_t __iomem *bar0 = sp->bar0;
4381         u16 subid;
4382
4383         subid = sp->pdev->subsystem_device;
4384         last_gpio_ctrl_val = readq(&bar0->gpio_control);
4385         if ((sp->device_type == XFRAME_I_DEVICE) &&
4386                 ((subid & 0xFF) < 0x07)) {
4387                 val64 = readq(&bar0->adapter_control);
4388                 if (!(val64 & ADAPTER_CNTL_EN)) {
4389                         printk(KERN_ERR
4390                                "Adapter Link down, cannot blink LED\n");
4391                         return -EFAULT;
4392                 }
4393         }
4394         if (sp->id_timer.function == NULL) {
4395                 init_timer(&sp->id_timer);
4396                 sp->id_timer.function = s2io_phy_id;
4397                 sp->id_timer.data = (unsigned long) sp;
4398         }
4399         mod_timer(&sp->id_timer, jiffies);
4400         if (data)
4401                 msleep_interruptible(data * HZ);
4402         else
4403                 msleep_interruptible(MAX_FLICKER_TIME);
4404         del_timer_sync(&sp->id_timer);
4405
4406         if (CARDS_WITH_FAULTY_LINK_INDICATORS(sp->device_type, subid)) {
4407                 writeq(last_gpio_ctrl_val, &bar0->gpio_control);
4408                 last_gpio_ctrl_val = readq(&bar0->gpio_control);
4409         }
4410
4411         return 0;
4412 }
4413
4414 /**
4415  * s2io_ethtool_getpause_data -Pause frame frame generation and reception.
4416  * @sp : private member of the device structure, which is a pointer to the
4417  *      s2io_nic structure.
4418  * @ep : pointer to the structure with pause parameters given by ethtool.
4419  * Description:
4420  * Returns the Pause frame generation and reception capability of the NIC.
4421  * Return value:
4422  *  void
4423  */
4424 static void s2io_ethtool_getpause_data(struct net_device *dev,
4425                                        struct ethtool_pauseparam *ep)
4426 {
4427         u64 val64;
4428         nic_t *sp = dev->priv;
4429         XENA_dev_config_t __iomem *bar0 = sp->bar0;
4430
4431         val64 = readq(&bar0->rmac_pause_cfg);
4432         if (val64 & RMAC_PAUSE_GEN_ENABLE)
4433                 ep->tx_pause = TRUE;
4434         if (val64 & RMAC_PAUSE_RX_ENABLE)
4435                 ep->rx_pause = TRUE;
4436         ep->autoneg = FALSE;
4437 }
4438
4439 /**
4440  * s2io_ethtool_setpause_data -  set/reset pause frame generation.
4441  * @sp : private member of the device structure, which is a pointer to the
4442  *      s2io_nic structure.
4443  * @ep : pointer to the structure with pause parameters given by ethtool.
4444  * Description:
4445  * It can be used to set or reset Pause frame generation or reception
4446  * support of the NIC.
4447  * Return value:
4448  * int, returns 0 on Success
4449  */
4450
4451 static int s2io_ethtool_setpause_data(struct net_device *dev,
4452                                struct ethtool_pauseparam *ep)
4453 {
4454         u64 val64;
4455         nic_t *sp = dev->priv;
4456         XENA_dev_config_t __iomem *bar0 = sp->bar0;
4457
4458         val64 = readq(&bar0->rmac_pause_cfg);
4459         if (ep->tx_pause)
4460                 val64 |= RMAC_PAUSE_GEN_ENABLE;
4461         else
4462                 val64 &= ~RMAC_PAUSE_GEN_ENABLE;
4463         if (ep->rx_pause)
4464                 val64 |= RMAC_PAUSE_RX_ENABLE;
4465         else
4466                 val64 &= ~RMAC_PAUSE_RX_ENABLE;
4467         writeq(val64, &bar0->rmac_pause_cfg);
4468         return 0;
4469 }
4470
4471 /**
4472  * read_eeprom - reads 4 bytes of data from user given offset.
4473  * @sp : private member of the device structure, which is a pointer to the
4474  *      s2io_nic structure.
4475  * @off : offset at which the data must be written
4476  * @data : Its an output parameter where the data read at the given
4477  *      offset is stored.
4478  * Description:
4479  * Will read 4 bytes of data from the user given offset and return the
4480  * read data.
4481  * NOTE: Will allow to read only part of the EEPROM visible through the
4482  *   I2C bus.
4483  * Return value:
4484  *  -1 on failure and 0 on success.
4485  */
4486
4487 #define S2IO_DEV_ID             5
4488 static int read_eeprom(nic_t * sp, int off, u64 * data)
4489 {
4490         int ret = -1;
4491         u32 exit_cnt = 0;
4492         u64 val64;
4493         XENA_dev_config_t __iomem *bar0 = sp->bar0;
4494
4495         if (sp->device_type == XFRAME_I_DEVICE) {
4496                 val64 = I2C_CONTROL_DEV_ID(S2IO_DEV_ID) | I2C_CONTROL_ADDR(off) |
4497                     I2C_CONTROL_BYTE_CNT(0x3) | I2C_CONTROL_READ |
4498                     I2C_CONTROL_CNTL_START;
4499                 SPECIAL_REG_WRITE(val64, &bar0->i2c_control, LF);
4500
4501                 while (exit_cnt < 5) {
4502                         val64 = readq(&bar0->i2c_control);
4503                         if (I2C_CONTROL_CNTL_END(val64)) {
4504                                 *data = I2C_CONTROL_GET_DATA(val64);
4505                                 ret = 0;
4506                                 break;
4507                         }
4508                         msleep(50);
4509                         exit_cnt++;
4510                 }
4511         }
4512
4513         if (sp->device_type == XFRAME_II_DEVICE) {
4514                 val64 = SPI_CONTROL_KEY(0x9) | SPI_CONTROL_SEL1 |
4515                         SPI_CONTROL_BYTECNT(0x3) |
4516                         SPI_CONTROL_CMD(0x3) | SPI_CONTROL_ADDR(off);
4517                 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
4518                 val64 |= SPI_CONTROL_REQ;
4519                 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
4520                 while (exit_cnt < 5) {
4521                         val64 = readq(&bar0->spi_control);
4522                         if (val64 & SPI_CONTROL_NACK) {
4523                                 ret = 1;
4524                                 break;
4525                         } else if (val64 & SPI_CONTROL_DONE) {
4526                                 *data = readq(&bar0->spi_data);
4527                                 *data &= 0xffffff;
4528                                 ret = 0;
4529                                 break;
4530                         }
4531                         msleep(50);
4532                         exit_cnt++;
4533                 }
4534         }
4535         return ret;
4536 }
4537
4538 /**
4539  *  write_eeprom - actually writes the relevant part of the data value.
4540  *  @sp : private member of the device structure, which is a pointer to the
4541  *       s2io_nic structure.
4542  *  @off : offset at which the data must be written
4543  *  @data : The data that is to be written
4544  *  @cnt : Number of bytes of the data that are actually to be written into
4545  *  the Eeprom. (max of 3)
4546  * Description:
4547  *  Actually writes the relevant part of the data value into the Eeprom
4548  *  through the I2C bus.
4549  * Return value:
4550  *  0 on success, -1 on failure.
4551  */
4552
4553 static int write_eeprom(nic_t * sp, int off, u64 data, int cnt)
4554 {
4555         int exit_cnt = 0, ret = -1;
4556         u64 val64;
4557         XENA_dev_config_t __iomem *bar0 = sp->bar0;
4558
4559         if (sp->device_type == XFRAME_I_DEVICE) {
4560                 val64 = I2C_CONTROL_DEV_ID(S2IO_DEV_ID) | I2C_CONTROL_ADDR(off) |
4561                     I2C_CONTROL_BYTE_CNT(cnt) | I2C_CONTROL_SET_DATA((u32)data) |
4562                     I2C_CONTROL_CNTL_START;
4563                 SPECIAL_REG_WRITE(val64, &bar0->i2c_control, LF);
4564
4565                 while (exit_cnt < 5) {
4566                         val64 = readq(&bar0->i2c_control);
4567                         if (I2C_CONTROL_CNTL_END(val64)) {
4568                                 if (!(val64 & I2C_CONTROL_NACK))
4569                                         ret = 0;
4570                                 break;
4571                         }
4572                         msleep(50);
4573                         exit_cnt++;
4574                 }
4575         }
4576
4577         if (sp->device_type == XFRAME_II_DEVICE) {
4578                 int write_cnt = (cnt == 8) ? 0 : cnt;
4579                 writeq(SPI_DATA_WRITE(data,(cnt<<3)), &bar0->spi_data);
4580
4581                 val64 = SPI_CONTROL_KEY(0x9) | SPI_CONTROL_SEL1 |
4582                         SPI_CONTROL_BYTECNT(write_cnt) |
4583                         SPI_CONTROL_CMD(0x2) | SPI_CONTROL_ADDR(off);
4584                 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
4585                 val64 |= SPI_CONTROL_REQ;
4586                 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
4587                 while (exit_cnt < 5) {
4588                         val64 = readq(&bar0->spi_control);
4589                         if (val64 & SPI_CONTROL_NACK) {
4590                                 ret = 1;
4591                                 break;
4592                         } else if (val64 & SPI_CONTROL_DONE) {
4593                                 ret = 0;
4594                                 break;
4595                         }
4596                         msleep(50);
4597                         exit_cnt++;
4598                 }
4599         }
4600         return ret;
4601 }
4602 static void s2io_vpd_read(nic_t *nic)
4603 {
4604         u8 vpd_data[256],data;
4605         int i=0, cnt, fail = 0;
4606         int vpd_addr = 0x80;
4607
4608         if (nic->device_type == XFRAME_II_DEVICE) {
4609                 strcpy(nic->product_name, "Xframe II 10GbE network adapter");
4610                 vpd_addr = 0x80;
4611         }
4612         else {
4613                 strcpy(nic->product_name, "Xframe I 10GbE network adapter");
4614                 vpd_addr = 0x50;
4615         }
4616
4617         for (i = 0; i < 256; i +=4 ) {
4618                 pci_write_config_byte(nic->pdev, (vpd_addr + 2), i);
4619                 pci_read_config_byte(nic->pdev,  (vpd_addr + 2), &data);
4620                 pci_write_config_byte(nic->pdev, (vpd_addr + 3), 0);
4621                 for (cnt = 0; cnt <5; cnt++) {
4622                         msleep(2);
4623                         pci_read_config_byte(nic->pdev, (vpd_addr + 3), &data);
4624                         if (data == 0x80)
4625                                 break;
4626                 }
4627                 if (cnt >= 5) {
4628                         DBG_PRINT(ERR_DBG, "Read of VPD data failed\n");
4629                         fail = 1;
4630                         break;
4631                 }
4632                 pci_read_config_dword(nic->pdev,  (vpd_addr + 4),
4633                                       (u32 *)&vpd_data[i]);
4634         }
4635         if ((!fail) && (vpd_data[1] < VPD_PRODUCT_NAME_LEN)) {
4636                 memset(nic->product_name, 0, vpd_data[1]);
4637                 memcpy(nic->product_name, &vpd_data[3], vpd_data[1]);
4638         }
4639 }
4640
4641 /**
4642  *  s2io_ethtool_geeprom  - reads the value stored in the Eeprom.
4643  *  @sp : private member of the device structure, which is a pointer to the *       s2io_nic structure.
4644  *  @eeprom : pointer to the user level structure provided by ethtool,
4645  *  containing all relevant information.
4646  *  @data_buf : user defined value to be written into Eeprom.
4647  *  Description: Reads the values stored in the Eeprom at given offset
4648  *  for a given length. Stores these values int the input argument data
4649  *  buffer 'data_buf' and returns these to the caller (ethtool.)
4650  *  Return value:
4651  *  int  0 on success
4652  */
4653
4654 static int s2io_ethtool_geeprom(struct net_device *dev,
4655                          struct ethtool_eeprom *eeprom, u8 * data_buf)
4656 {
4657         u32 i, valid;
4658         u64 data;
4659         nic_t *sp = dev->priv;
4660
4661         eeprom->magic = sp->pdev->vendor | (sp->pdev->device << 16);
4662
4663         if ((eeprom->offset + eeprom->len) > (XENA_EEPROM_SPACE))
4664                 eeprom->len = XENA_EEPROM_SPACE - eeprom->offset;
4665
4666         for (i = 0; i < eeprom->len; i += 4) {
4667                 if (read_eeprom(sp, (eeprom->offset + i), &data)) {
4668                         DBG_PRINT(ERR_DBG, "Read of EEPROM failed\n");
4669                         return -EFAULT;
4670                 }
4671                 valid = INV(data);
4672                 memcpy((data_buf + i), &valid, 4);
4673         }
4674         return 0;
4675 }
4676
4677 /**
4678  *  s2io_ethtool_seeprom - tries to write the user provided value in Eeprom
4679  *  @sp : private member of the device structure, which is a pointer to the
4680  *  s2io_nic structure.
4681  *  @eeprom : pointer to the user level structure provided by ethtool,
4682  *  containing all relevant information.
4683  *  @data_buf ; user defined value to be written into Eeprom.
4684  *  Description:
4685  *  Tries to write the user provided value in the Eeprom, at the offset
4686  *  given by the user.
4687  *  Return value:
4688  *  0 on success, -EFAULT on failure.
4689  */
4690
4691 static int s2io_ethtool_seeprom(struct net_device *dev,
4692                                 struct ethtool_eeprom *eeprom,
4693                                 u8 * data_buf)
4694 {
4695         int len = eeprom->len, cnt = 0;
4696         u64 valid = 0, data;
4697         nic_t *sp = dev->priv;
4698
4699         if (eeprom->magic != (sp->pdev->vendor | (sp->pdev->device << 16))) {
4700                 DBG_PRINT(ERR_DBG,
4701                           "ETHTOOL_WRITE_EEPROM Err: Magic value ");
4702                 DBG_PRINT(ERR_DBG, "is wrong, Its not 0x%x\n",
4703                           eeprom->magic);
4704                 return -EFAULT;
4705         }
4706
4707         while (len) {
4708                 data = (u32) data_buf[cnt] & 0x000000FF;
4709                 if (data) {
4710                         valid = (u32) (data << 24);
4711                 } else
4712                         valid = data;
4713
4714                 if (write_eeprom(sp, (eeprom->offset + cnt), valid, 0)) {
4715                         DBG_PRINT(ERR_DBG,
4716                                   "ETHTOOL_WRITE_EEPROM Err: Cannot ");
4717                         DBG_PRINT(ERR_DBG,
4718                                   "write into the specified offset\n");
4719                         return -EFAULT;
4720                 }
4721                 cnt++;
4722                 len--;
4723         }
4724
4725         return 0;
4726 }
4727
4728 /**
4729  * s2io_register_test - reads and writes into all clock domains.
4730  * @sp : private member of the device structure, which is a pointer to the
4731  * s2io_nic structure.
4732  * @data : variable that returns the result of each of the test conducted b
4733  * by the driver.
4734  * Description:
4735  * Read and write into all clock domains. The NIC has 3 clock domains,
4736  * see that registers in all the three regions are accessible.
4737  * Return value:
4738  * 0 on success.
4739  */
4740
4741 static int s2io_register_test(nic_t * sp, uint64_t * data)
4742 {
4743         XENA_dev_config_t __iomem *bar0 = sp->bar0;
4744         u64 val64 = 0, exp_val;
4745         int fail = 0;
4746
4747         val64 = readq(&bar0->pif_rd_swapper_fb);
4748         if (val64 != 0x123456789abcdefULL) {
4749                 fail = 1;
4750                 DBG_PRINT(INFO_DBG, "Read Test level 1 fails\n");
4751         }
4752
4753         val64 = readq(&bar0->rmac_pause_cfg);
4754         if (val64 != 0xc000ffff00000000ULL) {
4755                 fail = 1;
4756                 DBG_PRINT(INFO_DBG, "Read Test level 2 fails\n");
4757         }
4758
4759         val64 = readq(&bar0->rx_queue_cfg);
4760         if (sp->device_type == XFRAME_II_DEVICE)
4761                 exp_val = 0x0404040404040404ULL;
4762         else
4763                 exp_val = 0x0808080808080808ULL;
4764         if (val64 != exp_val) {
4765                 fail = 1;
4766                 DBG_PRINT(INFO_DBG, "Read Test level 3 fails\n");
4767         }
4768
4769         val64 = readq(&bar0->xgxs_efifo_cfg);
4770         if (val64 != 0x000000001923141EULL) {
4771                 fail = 1;
4772                 DBG_PRINT(INFO_DBG, "Read Test level 4 fails\n");
4773         }
4774
4775         val64 = 0x5A5A5A5A5A5A5A5AULL;
4776         writeq(val64, &bar0->xmsi_data);
4777         val64 = readq(&bar0->xmsi_data);
4778         if (val64 != 0x5A5A5A5A5A5A5A5AULL) {
4779                 fail = 1;
4780                 DBG_PRINT(ERR_DBG, "Write Test level 1 fails\n");
4781         }
4782
4783         val64 = 0xA5A5A5A5A5A5A5A5ULL;
4784         writeq(val64, &bar0->xmsi_data);
4785         val64 = readq(&bar0->xmsi_data);
4786         if (val64 != 0xA5A5A5A5A5A5A5A5ULL) {
4787                 fail = 1;
4788                 DBG_PRINT(ERR_DBG, "Write Test level 2 fails\n");
4789         }
4790
4791         *data = fail;
4792         return fail;
4793 }
4794
4795 /**
4796  * s2io_eeprom_test - to verify that EEprom in the xena can be programmed.
4797  * @sp : private member of the device structure, which is a pointer to the
4798  * s2io_nic structure.
4799  * @data:variable that returns the result of each of the test conducted by
4800  * the driver.
4801  * Description:
4802  * Verify that EEPROM in the xena can be programmed using I2C_CONTROL
4803  * register.
4804  * Return value:
4805  * 0 on success.
4806  */
4807
4808 static int s2io_eeprom_test(nic_t * sp, uint64_t * data)
4809 {
4810         int fail = 0;
4811         u64 ret_data, org_4F0, org_7F0;
4812         u8 saved_4F0 = 0, saved_7F0 = 0;
4813         struct net_device *dev = sp->dev;
4814
4815         /* Test Write Error at offset 0 */
4816         /* Note that SPI interface allows write access to all areas
4817          * of EEPROM. Hence doing all negative testing only for Xframe I.
4818          */
4819         if (sp->device_type == XFRAME_I_DEVICE)
4820                 if (!write_eeprom(sp, 0, 0, 3))
4821                         fail = 1;
4822
4823         /* Save current values at offsets 0x4F0 and 0x7F0 */
4824         if (!read_eeprom(sp, 0x4F0, &org_4F0))
4825                 saved_4F0 = 1;
4826         if (!read_eeprom(sp, 0x7F0, &org_7F0))
4827                 saved_7F0 = 1;
4828
4829         /* Test Write at offset 4f0 */
4830         if (write_eeprom(sp, 0x4F0, 0x012345, 3))
4831                 fail = 1;
4832         if (read_eeprom(sp, 0x4F0, &ret_data))
4833                 fail = 1;
4834
4835         if (ret_data != 0x012345) {
4836                 DBG_PRINT(ERR_DBG, "%s: eeprom test error at offset 0x4F0. "
4837                         "Data written %llx Data read %llx\n",
4838                         dev->name, (unsigned long long)0x12345,
4839                         (unsigned long long)ret_data);
4840                 fail = 1;
4841         }
4842
4843         /* Reset the EEPROM data go FFFF */
4844         write_eeprom(sp, 0x4F0, 0xFFFFFF, 3);
4845
4846         /* Test Write Request Error at offset 0x7c */
4847         if (sp->device_type == XFRAME_I_DEVICE)
4848                 if (!write_eeprom(sp, 0x07C, 0, 3))
4849                         fail = 1;
4850
4851         /* Test Write Request at offset 0x7f0 */
4852         if (write_eeprom(sp, 0x7F0, 0x012345, 3))
4853                 fail = 1;
4854         if (read_eeprom(sp, 0x7F0, &ret_data))
4855                 fail = 1;
4856
4857         if (ret_data != 0x012345) {
4858                 DBG_PRINT(ERR_DBG, "%s: eeprom test error at offset 0x7F0. "
4859                         "Data written %llx Data read %llx\n",
4860                         dev->name, (unsigned long long)0x12345,
4861                         (unsigned long long)ret_data);
4862                 fail = 1;
4863         }
4864
4865         /* Reset the EEPROM data go FFFF */
4866         write_eeprom(sp, 0x7F0, 0xFFFFFF, 3);
4867
4868         if (sp->device_type == XFRAME_I_DEVICE) {
4869                 /* Test Write Error at offset 0x80 */
4870                 if (!write_eeprom(sp, 0x080, 0, 3))
4871                         fail = 1;
4872
4873                 /* Test Write Error at offset 0xfc */
4874                 if (!write_eeprom(sp, 0x0FC, 0, 3))
4875                         fail = 1;
4876
4877                 /* Test Write Error at offset 0x100 */
4878                 if (!write_eeprom(sp, 0x100, 0, 3))
4879                         fail = 1;
4880
4881                 /* Test Write Error at offset 4ec */
4882                 if (!write_eeprom(sp, 0x4EC, 0, 3))
4883                         fail = 1;
4884         }
4885
4886         /* Restore values at offsets 0x4F0 and 0x7F0 */
4887         if (saved_4F0)
4888                 write_eeprom(sp, 0x4F0, org_4F0, 3);
4889         if (saved_7F0)
4890                 write_eeprom(sp, 0x7F0, org_7F0, 3);
4891
4892         *data = fail;
4893         return fail;
4894 }
4895
4896 /**
4897  * s2io_bist_test - invokes the MemBist test of the card .
4898  * @sp : private member of the device structure, which is a pointer to the
4899  * s2io_nic structure.
4900  * @data:variable that returns the result of each of the test conducted by
4901  * the driver.
4902  * Description:
4903  * This invokes the MemBist test of the card. We give around
4904  * 2 secs time for the Test to complete. If it's still not complete
4905  * within this peiod, we consider that the test failed.
4906  * Return value:
4907  * 0 on success and -1 on failure.
4908  */
4909
4910 static int s2io_bist_test(nic_t * sp, uint64_t * data)
4911 {
4912         u8 bist = 0;
4913         int cnt = 0, ret = -1;
4914
4915         pci_read_config_byte(sp->pdev, PCI_BIST, &bist);
4916         bist |= PCI_BIST_START;
4917         pci_write_config_word(sp->pdev, PCI_BIST, bist);
4918
4919         while (cnt < 20) {
4920                 pci_read_config_byte(sp->pdev, PCI_BIST, &bist);
4921                 if (!(bist & PCI_BIST_START)) {
4922                         *data = (bist & PCI_BIST_CODE_MASK);
4923                         ret = 0;
4924                         break;
4925                 }
4926                 msleep(100);
4927                 cnt++;
4928         }
4929
4930         return ret;
4931 }
4932
4933 /**
4934  * s2io-link_test - verifies the link state of the nic
4935  * @sp ; private member of the device structure, which is a pointer to the
4936  * s2io_nic structure.
4937  * @data: variable that returns the result of each of the test conducted by
4938  * the driver.
4939  * Description:
4940  * The function verifies the link state of the NIC and updates the input
4941  * argument 'data' appropriately.
4942  * Return value:
4943  * 0 on success.
4944  */
4945
4946 static int s2io_link_test(nic_t * sp, uint64_t * data)
4947 {
4948         XENA_dev_config_t __iomem *bar0 = sp->bar0;
4949         u64 val64;
4950
4951         val64 = readq(&bar0->adapter_status);
4952         if(!(LINK_IS_UP(val64)))
4953                 *data = 1;
4954         else
4955                 *data = 0;
4956
4957         return 0;
4958 }
4959
4960 /**
4961  * s2io_rldram_test - offline test for access to the RldRam chip on the NIC
4962  * @sp - private member of the device structure, which is a pointer to the
4963  * s2io_nic structure.
4964  * @data - variable that returns the result of each of the test
4965  * conducted by the driver.
4966  * Description:
4967  *  This is one of the offline test that tests the read and write
4968  *  access to the RldRam chip on the NIC.
4969  * Return value:
4970  *  0 on success.
4971  */
4972
4973 static int s2io_rldram_test(nic_t * sp, uint64_t * data)
4974 {
4975         XENA_dev_config_t __iomem *bar0 = sp->bar0;
4976         u64 val64;
4977         int cnt, iteration = 0, test_fail = 0;
4978
4979         val64 = readq(&bar0->adapter_control);
4980         val64 &= ~ADAPTER_ECC_EN;
4981         writeq(val64, &bar0->adapter_control);
4982
4983         val64 = readq(&bar0->mc_rldram_test_ctrl);
4984         val64 |= MC_RLDRAM_TEST_MODE;
4985         SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
4986
4987         val64 = readq(&bar0->mc_rldram_mrs);
4988         val64 |= MC_RLDRAM_QUEUE_SIZE_ENABLE;
4989         SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
4990
4991         val64 |= MC_RLDRAM_MRS_ENABLE;
4992         SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
4993
4994         while (iteration < 2) {
4995                 val64 = 0x55555555aaaa0000ULL;
4996                 if (iteration == 1) {
4997                         val64 ^= 0xFFFFFFFFFFFF0000ULL;
4998                 }
4999                 writeq(val64, &bar0->mc_rldram_test_d0);
5000
5001                 val64 = 0xaaaa5a5555550000ULL;
5002                 if (iteration == 1) {
5003                         val64 ^= 0xFFFFFFFFFFFF0000ULL;
5004                 }
5005                 writeq(val64, &bar0->mc_rldram_test_d1);
5006
5007                 val64 = 0x55aaaaaaaa5a0000ULL;
5008                 if (iteration == 1) {
5009                         val64 ^= 0xFFFFFFFFFFFF0000ULL;
5010                 }
5011                 writeq(val64, &bar0->mc_rldram_test_d2);
5012
5013                 val64 = (u64) (0x0000003ffffe0100ULL);
5014                 writeq(val64, &bar0->mc_rldram_test_add);
5015
5016                 val64 = MC_RLDRAM_TEST_MODE | MC_RLDRAM_TEST_WRITE |
5017                         MC_RLDRAM_TEST_GO;
5018                 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
5019
5020                 for (cnt = 0; cnt < 5; cnt++) {
5021                         val64 = readq(&bar0->mc_rldram_test_ctrl);
5022                         if (val64 & MC_RLDRAM_TEST_DONE)
5023                                 break;
5024                         msleep(200);
5025                 }
5026
5027                 if (cnt == 5)
5028                         break;
5029
5030                 val64 = MC_RLDRAM_TEST_MODE | MC_RLDRAM_TEST_GO;
5031                 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
5032
5033                 for (cnt = 0; cnt < 5; cnt++) {
5034                         val64 = readq(&bar0->mc_rldram_test_ctrl);
5035                         if (val64 & MC_RLDRAM_TEST_DONE)
5036                                 break;
5037                         msleep(500);
5038                 }
5039
5040                 if (cnt == 5)
5041                         break;
5042
5043                 val64 = readq(&bar0->mc_rldram_test_ctrl);
5044                 if (!(val64 & MC_RLDRAM_TEST_PASS))
5045                         test_fail = 1;
5046
5047                 iteration++;
5048         }
5049
5050         *data = test_fail;
5051
5052         /* Bring the adapter out of test mode */
5053         SPECIAL_REG_WRITE(0, &bar0->mc_rldram_test_ctrl, LF);
5054
5055         return test_fail;
5056 }
5057
5058 /**
5059  *  s2io_ethtool_test - conducts 6 tsets to determine the health of card.
5060  *  @sp : private member of the device structure, which is a pointer to the
5061  *  s2io_nic structure.
5062  *  @ethtest : pointer to a ethtool command specific structure that will be
5063  *  returned to the user.
5064  *  @data : variable that returns the result of each of the test
5065  * conducted by the driver.
5066  * Description:
5067  *  This function conducts 6 tests ( 4 offline and 2 online) to determine
5068  *  the health of the card.
5069  * Return value:
5070  *  void
5071  */
5072
5073 static void s2io_ethtool_test(struct net_device *dev,
5074                               struct ethtool_test *ethtest,
5075                               uint64_t * data)
5076 {
5077         nic_t *sp = dev->priv;
5078         int orig_state = netif_running(sp->dev);
5079
5080         if (ethtest->flags == ETH_TEST_FL_OFFLINE) {
5081                 /* Offline Tests. */
5082                 if (orig_state)
5083                         s2io_close(sp->dev);
5084
5085                 if (s2io_register_test(sp, &data[0]))
5086                         ethtest->flags |= ETH_TEST_FL_FAILED;
5087
5088                 s2io_reset(sp);
5089
5090                 if (s2io_rldram_test(sp, &data[3]))
5091                         ethtest->flags |= ETH_TEST_FL_FAILED;
5092
5093                 s2io_reset(sp);
5094
5095                 if (s2io_eeprom_test(sp, &data[1]))
5096                         ethtest->flags |= ETH_TEST_FL_FAILED;
5097
5098                 if (s2io_bist_test(sp, &data[4]))
5099                         ethtest->flags |= ETH_TEST_FL_FAILED;
5100
5101                 if (orig_state)
5102                         s2io_open(sp->dev);
5103
5104                 data[2] = 0;
5105         } else {
5106                 /* Online Tests. */
5107                 if (!orig_state) {
5108                         DBG_PRINT(ERR_DBG,
5109                                   "%s: is not up, cannot run test\n",
5110                                   dev->name);
5111                         data[0] = -1;
5112                         data[1] = -1;
5113                         data[2] = -1;
5114                         data[3] = -1;
5115                         data[4] = -1;
5116                 }
5117
5118                 if (s2io_link_test(sp, &data[2]))
5119                         ethtest->flags |= ETH_TEST_FL_FAILED;
5120
5121                 data[0] = 0;
5122                 data[1] = 0;
5123                 data[3] = 0;
5124                 data[4] = 0;
5125         }
5126 }
5127
5128 static void s2io_get_ethtool_stats(struct net_device *dev,
5129                                    struct ethtool_stats *estats,
5130                                    u64 * tmp_stats)
5131 {
5132         int i = 0;
5133         nic_t *sp = dev->priv;
5134         StatInfo_t *stat_info = sp->mac_control.stats_info;
5135         u64 tmp;
5136
5137         s2io_updt_stats(sp);
5138         tmp_stats[i++] =
5139                 (u64)le32_to_cpu(stat_info->tmac_frms_oflow) << 32  |
5140                 le32_to_cpu(stat_info->tmac_frms);
5141         tmp_stats[i++] =
5142                 (u64)le32_to_cpu(stat_info->tmac_data_octets_oflow) << 32 |
5143                 le32_to_cpu(stat_info->tmac_data_octets);
5144         tmp_stats[i++] = le64_to_cpu(stat_info->tmac_drop_frms);
5145         tmp_stats[i++] =
5146                 (u64)le32_to_cpu(stat_info->tmac_mcst_frms_oflow) << 32 |
5147                 le32_to_cpu(stat_info->tmac_mcst_frms);
5148         tmp_stats[i++] =
5149                 (u64)le32_to_cpu(stat_info->tmac_bcst_frms_oflow) << 32 |
5150                 le32_to_cpu(stat_info->tmac_bcst_frms);
5151         tmp_stats[i++] = le64_to_cpu(stat_info->tmac_pause_ctrl_frms);
5152         tmp_stats[i++] =
5153                 (u64)le32_to_cpu(stat_info->tmac_any_err_frms_oflow) << 32 |
5154                 le32_to_cpu(stat_info->tmac_any_err_frms);
5155         tmp_stats[i++] = le64_to_cpu(stat_info->tmac_vld_ip_octets);
5156         tmp_stats[i++] =
5157                 (u64)le32_to_cpu(stat_info->tmac_vld_ip_oflow) << 32 |
5158                 le32_to_cpu(stat_info->tmac_vld_ip);
5159         tmp_stats[i++] =
5160                 (u64)le32_to_cpu(stat_info->tmac_drop_ip_oflow) << 32 |
5161                 le32_to_cpu(stat_info->tmac_drop_ip);
5162         tmp_stats[i++] =
5163                 (u64)le32_to_cpu(stat_info->tmac_icmp_oflow) << 32 |
5164                 le32_to_cpu(stat_info->tmac_icmp);
5165         tmp_stats[i++] =
5166                 (u64)le32_to_cpu(stat_info->tmac_rst_tcp_oflow) << 32 |
5167                 le32_to_cpu(stat_info->tmac_rst_tcp);
5168         tmp_stats[i++] = le64_to_cpu(stat_info->tmac_tcp);
5169         tmp_stats[i++] = (u64)le32_to_cpu(stat_info->tmac_udp_oflow) << 32 |
5170                 le32_to_cpu(stat_info->tmac_udp);
5171         tmp_stats[i++] =
5172                 (u64)le32_to_cpu(stat_info->rmac_vld_frms_oflow) << 32 |
5173                 le32_to_cpu(stat_info->rmac_vld_frms);
5174         tmp_stats[i++] =
5175                 (u64)le32_to_cpu(stat_info->rmac_data_octets_oflow) << 32 |
5176                 le32_to_cpu(stat_info->rmac_data_octets);
5177         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_fcs_err_frms);
5178         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_drop_frms);
5179         tmp_stats[i++] =
5180                 (u64)le32_to_cpu(stat_info->rmac_vld_mcst_frms_oflow) << 32 |
5181                 le32_to_cpu(stat_info->rmac_vld_mcst_frms);
5182         tmp_stats[i++] =
5183                 (u64)le32_to_cpu(stat_info->rmac_vld_bcst_frms_oflow) << 32 |
5184                 le32_to_cpu(stat_info->rmac_vld_bcst_frms);
5185         tmp_stats[i++] = le32_to_cpu(stat_info->rmac_in_rng_len_err_frms);
5186         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_long_frms);
5187         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_pause_ctrl_frms);
5188         tmp_stats[i++] =
5189                 (u64)le32_to_cpu(stat_info->rmac_discarded_frms_oflow) << 32 |
5190                 le32_to_cpu(stat_info->rmac_discarded_frms);
5191         tmp_stats[i++] =
5192                 (u64)le32_to_cpu(stat_info->rmac_usized_frms_oflow) << 32 |
5193                 le32_to_cpu(stat_info->rmac_usized_frms);
5194         tmp_stats[i++] =
5195                 (u64)le32_to_cpu(stat_info->rmac_osized_frms_oflow) << 32 |
5196                 le32_to_cpu(stat_info->rmac_osized_frms);
5197         tmp_stats[i++] =
5198                 (u64)le32_to_cpu(stat_info->rmac_frag_frms_oflow) << 32 |
5199                 le32_to_cpu(stat_info->rmac_frag_frms);
5200         tmp_stats[i++] =
5201                 (u64)le32_to_cpu(stat_info->rmac_jabber_frms_oflow) << 32 |
5202                 le32_to_cpu(stat_info->rmac_jabber_frms);
5203         tmp_stats[i++] = (u64)le32_to_cpu(stat_info->rmac_ip_oflow) << 32 |
5204                 le32_to_cpu(stat_info->rmac_ip);
5205         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ip_octets);
5206         tmp_stats[i++] = le32_to_cpu(stat_info->rmac_hdr_err_ip);
5207         tmp_stats[i++] = (u64)le32_to_cpu(stat_info->rmac_drop_ip_oflow) << 32 |
5208                 le32_to_cpu(stat_info->rmac_drop_ip);
5209         tmp_stats[i++] = (u64)le32_to_cpu(stat_info->rmac_icmp_oflow) << 32 |
5210                 le32_to_cpu(stat_info->rmac_icmp);
5211         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_tcp);
5212         tmp_stats[i++] = (u64)le32_to_cpu(stat_info->rmac_udp_oflow) << 32 |
5213                 le32_to_cpu(stat_info->rmac_udp);
5214         tmp_stats[i++] =
5215                 (u64)le32_to_cpu(stat_info->rmac_err_drp_udp_oflow) << 32 |
5216                 le32_to_cpu(stat_info->rmac_err_drp_udp);
5217         tmp_stats[i++] =
5218                 (u64)le32_to_cpu(stat_info->rmac_pause_cnt_oflow) << 32 |
5219                 le32_to_cpu(stat_info->rmac_pause_cnt);
5220         tmp_stats[i++] =
5221                 (u64)le32_to_cpu(stat_info->rmac_accepted_ip_oflow) << 32 |
5222                 le32_to_cpu(stat_info->rmac_accepted_ip);
5223         tmp_stats[i++] = le32_to_cpu(stat_info->rmac_err_tcp);
5224         tmp_stats[i++] = 0;
5225         tmp_stats[i++] = stat_info->sw_stat.single_ecc_errs;
5226         tmp_stats[i++] = stat_info->sw_stat.double_ecc_errs;
5227         tmp_stats[i++] = stat_info->sw_stat.clubbed_frms_cnt;
5228         tmp_stats[i++] = stat_info->sw_stat.sending_both;
5229         tmp_stats[i++] = stat_info->sw_stat.outof_sequence_pkts;
5230         tmp_stats[i++] = stat_info->sw_stat.flush_max_pkts;
5231         tmp = 0;
5232         if (stat_info->sw_stat.num_aggregations) {
5233                 tmp = stat_info->sw_stat.sum_avg_pkts_aggregated;
5234                 do_div(tmp, stat_info->sw_stat.num_aggregations);
5235         }
5236         tmp_stats[i++] = tmp;
5237 }
5238
5239 static int s2io_ethtool_get_regs_len(struct net_device *dev)
5240 {
5241         return (XENA_REG_SPACE);
5242 }
5243
5244
5245 static u32 s2io_ethtool_get_rx_csum(struct net_device * dev)
5246 {
5247         nic_t *sp = dev->priv;
5248
5249         return (sp->rx_csum);
5250 }
5251
5252 static int s2io_ethtool_set_rx_csum(struct net_device *dev, u32 data)
5253 {
5254         nic_t *sp = dev->priv;
5255
5256         if (data)
5257                 sp->rx_csum = 1;
5258         else
5259                 sp->rx_csum = 0;
5260
5261         return 0;
5262 }
5263
5264 static int s2io_get_eeprom_len(struct net_device *dev)
5265 {
5266         return (XENA_EEPROM_SPACE);
5267 }
5268
5269 static int s2io_ethtool_self_test_count(struct net_device *dev)
5270 {
5271         return (S2IO_TEST_LEN);
5272 }
5273
5274 static void s2io_ethtool_get_strings(struct net_device *dev,
5275                                      u32 stringset, u8 * data)
5276 {
5277         switch (stringset) {
5278         case ETH_SS_TEST:
5279                 memcpy(data, s2io_gstrings, S2IO_STRINGS_LEN);
5280                 break;
5281         case ETH_SS_STATS:
5282                 memcpy(data, &ethtool_stats_keys,
5283                        sizeof(ethtool_stats_keys));
5284         }
5285 }
5286 static int s2io_ethtool_get_stats_count(struct net_device *dev)
5287 {
5288         return (S2IO_STAT_LEN);
5289 }
5290
5291 static int s2io_ethtool_op_set_tx_csum(struct net_device *dev, u32 data)
5292 {
5293         if (data)
5294                 dev->features |= NETIF_F_IP_CSUM;
5295         else
5296                 dev->features &= ~NETIF_F_IP_CSUM;
5297
5298         return 0;
5299 }
5300
5301
5302 static struct ethtool_ops netdev_ethtool_ops = {
5303         .get_settings = s2io_ethtool_gset,
5304         .set_settings = s2io_ethtool_sset,
5305         .get_drvinfo = s2io_ethtool_gdrvinfo,
5306         .get_regs_len = s2io_ethtool_get_regs_len,
5307         .get_regs = s2io_ethtool_gregs,
5308         .get_link = ethtool_op_get_link,
5309         .get_eeprom_len = s2io_get_eeprom_len,
5310         .get_eeprom = s2io_ethtool_geeprom,
5311         .set_eeprom = s2io_ethtool_seeprom,
5312         .get_pauseparam = s2io_ethtool_getpause_data,
5313         .set_pauseparam = s2io_ethtool_setpause_data,
5314         .get_rx_csum = s2io_ethtool_get_rx_csum,
5315         .set_rx_csum = s2io_ethtool_set_rx_csum,
5316         .get_tx_csum = ethtool_op_get_tx_csum,
5317         .set_tx_csum = s2io_ethtool_op_set_tx_csum,
5318         .get_sg = ethtool_op_get_sg,
5319         .set_sg = ethtool_op_set_sg,
5320 #ifdef NETIF_F_TSO
5321         .get_tso = ethtool_op_get_tso,
5322         .set_tso = ethtool_op_set_tso,
5323 #endif
5324         .get_ufo = ethtool_op_get_ufo,
5325         .set_ufo = ethtool_op_set_ufo,
5326         .self_test_count = s2io_ethtool_self_test_count,
5327         .self_test = s2io_ethtool_test,
5328         .get_strings = s2io_ethtool_get_strings,
5329         .phys_id = s2io_ethtool_idnic,
5330         .get_stats_count = s2io_ethtool_get_stats_count,
5331         .get_ethtool_stats = s2io_get_ethtool_stats
5332 };
5333
5334 /**
5335  *  s2io_ioctl - Entry point for the Ioctl
5336  *  @dev :  Device pointer.
5337  *  @ifr :  An IOCTL specefic structure, that can contain a pointer to
5338  *  a proprietary structure used to pass information to the driver.
5339  *  @cmd :  This is used to distinguish between the different commands that
5340  *  can be passed to the IOCTL functions.
5341  *  Description:
5342  *  Currently there are no special functionality supported in IOCTL, hence
5343  *  function always return EOPNOTSUPPORTED
5344  */
5345
5346 static int s2io_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
5347 {
5348         return -EOPNOTSUPP;
5349 }
5350
5351 /**
5352  *  s2io_change_mtu - entry point to change MTU size for the device.
5353  *   @dev : device pointer.
5354  *   @new_mtu : the new MTU size for the device.
5355  *   Description: A driver entry point to change MTU size for the device.
5356  *   Before changing the MTU the device must be stopped.
5357  *  Return value:
5358  *   0 on success and an appropriate (-)ve integer as defined in errno.h
5359  *   file on failure.
5360  */
5361
5362 static int s2io_change_mtu(struct net_device *dev, int new_mtu)
5363 {
5364         nic_t *sp = dev->priv;
5365
5366         if ((new_mtu < MIN_MTU) || (new_mtu > S2IO_JUMBO_SIZE)) {
5367                 DBG_PRINT(ERR_DBG, "%s: MTU size is invalid.\n",
5368                           dev->name);
5369                 return -EPERM;
5370         }
5371
5372         dev->mtu = new_mtu;
5373         if (netif_running(dev)) {
5374                 s2io_card_down(sp, 0);
5375                 netif_stop_queue(dev);
5376                 if (s2io_card_up(sp)) {
5377                         DBG_PRINT(ERR_DBG, "%s: Device bring up failed\n",
5378                                   __FUNCTION__);
5379                 }
5380                 if (netif_queue_stopped(dev))
5381                         netif_wake_queue(dev);
5382         } else { /* Device is down */
5383                 XENA_dev_config_t __iomem *bar0 = sp->bar0;
5384                 u64 val64 = new_mtu;
5385
5386                 writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len);
5387         }
5388
5389         return 0;
5390 }
5391
5392 /**
5393  *  s2io_tasklet - Bottom half of the ISR.
5394  *  @dev_adr : address of the device structure in dma_addr_t format.
5395  *  Description:
5396  *  This is the tasklet or the bottom half of the ISR. This is
5397  *  an extension of the ISR which is scheduled by the scheduler to be run
5398  *  when the load on the CPU is low. All low priority tasks of the ISR can
5399  *  be pushed into the tasklet. For now the tasklet is used only to
5400  *  replenish the Rx buffers in the Rx buffer descriptors.
5401  *  Return value:
5402  *  void.
5403  */
5404
5405 static void s2io_tasklet(unsigned long dev_addr)
5406 {
5407         struct net_device *dev = (struct net_device *) dev_addr;
5408         nic_t *sp = dev->priv;
5409         int i, ret;
5410         mac_info_t *mac_control;
5411         struct config_param *config;
5412
5413         mac_control = &sp->mac_control;
5414         config = &sp->config;
5415
5416         if (!TASKLET_IN_USE) {
5417                 for (i = 0; i < config->rx_ring_num; i++) {
5418                         ret = fill_rx_buffers(sp, i);
5419                         if (ret == -ENOMEM) {
5420                                 DBG_PRINT(ERR_DBG, "%s: Out of ",
5421                                           dev->name);
5422                                 DBG_PRINT(ERR_DBG, "memory in tasklet\n");
5423                                 break;
5424                         } else if (ret == -EFILL) {
5425                                 DBG_PRINT(ERR_DBG,
5426                                           "%s: Rx Ring %d is full\n",
5427                                           dev->name, i);
5428                                 break;
5429                         }
5430                 }
5431                 clear_bit(0, (&sp->tasklet_status));
5432         }
5433 }
5434
5435 /**
5436  * s2io_set_link - Set the LInk status
5437  * @data: long pointer to device private structue
5438  * Description: Sets the link status for the adapter
5439  */
5440
5441 static void s2io_set_link(unsigned long data)
5442 {
5443         nic_t *nic = (nic_t *) data;
5444         struct net_device *dev = nic->dev;
5445         XENA_dev_config_t __iomem *bar0 = nic->bar0;
5446         register u64 val64;
5447         u16 subid;
5448
5449         if (test_and_set_bit(0, &(nic->link_state))) {
5450                 /* The card is being reset, no point doing anything */
5451                 return;
5452         }
5453
5454         subid = nic->pdev->subsystem_device;
5455         if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) {
5456                 /*
5457                  * Allow a small delay for the NICs self initiated
5458                  * cleanup to complete.
5459                  */
5460                 msleep(100);
5461         }
5462
5463         val64 = readq(&bar0->adapter_status);
5464         if (verify_xena_quiescence(nic, val64, nic->device_enabled_once)) {
5465                 if (LINK_IS_UP(val64)) {
5466                         val64 = readq(&bar0->adapter_control);
5467                         val64 |= ADAPTER_CNTL_EN;
5468                         writeq(val64, &bar0->adapter_control);
5469                         if (CARDS_WITH_FAULTY_LINK_INDICATORS(nic->device_type,
5470                                                              subid)) {
5471                                 val64 = readq(&bar0->gpio_control);
5472                                 val64 |= GPIO_CTRL_GPIO_0;
5473                                 writeq(val64, &bar0->gpio_control);
5474                                 val64 = readq(&bar0->gpio_control);
5475                         } else {
5476                                 val64 |= ADAPTER_LED_ON;
5477                                 writeq(val64, &bar0->adapter_control);
5478                         }
5479                         if (s2io_link_fault_indication(nic) ==
5480                                                 MAC_RMAC_ERR_TIMER) {
5481                                 val64 = readq(&bar0->adapter_status);
5482                                 if (!LINK_IS_UP(val64)) {
5483                                         DBG_PRINT(ERR_DBG, "%s:", dev->name);
5484                                         DBG_PRINT(ERR_DBG, " Link down");
5485                                         DBG_PRINT(ERR_DBG, "after ");
5486                                         DBG_PRINT(ERR_DBG, "enabling ");
5487                                         DBG_PRINT(ERR_DBG, "device \n");
5488                                 }
5489                         }
5490                         if (nic->device_enabled_once == FALSE) {
5491                                 nic->device_enabled_once = TRUE;
5492                         }
5493                         s2io_link(nic, LINK_UP);
5494                 } else {
5495                         if (CARDS_WITH_FAULTY_LINK_INDICATORS(nic->device_type,
5496                                                               subid)) {
5497                                 val64 = readq(&bar0->gpio_control);
5498                                 val64 &= ~GPIO_CTRL_GPIO_0;
5499                                 writeq(val64, &bar0->gpio_control);
5500                                 val64 = readq(&bar0->gpio_control);
5501                         }
5502                         s2io_link(nic, LINK_DOWN);
5503                 }
5504         } else {                /* NIC is not Quiescent. */
5505                 DBG_PRINT(ERR_DBG, "%s: Error: ", dev->name);
5506                 DBG_PRINT(ERR_DBG, "device is not Quiescent\n");
5507                 netif_stop_queue(dev);
5508         }
5509         clear_bit(0, &(nic->link_state));
5510 }
5511
5512 static void s2io_card_down(nic_t * sp, int flag)
5513 {
5514         int cnt = 0;
5515         XENA_dev_config_t __iomem *bar0 = sp->bar0;
5516         unsigned long flags;
5517         register u64 val64 = 0;
5518         struct net_device *dev = sp->dev;
5519
5520         del_timer_sync(&sp->alarm_timer);
5521         /* If s2io_set_link task is executing, wait till it completes. */
5522         while (test_and_set_bit(0, &(sp->link_state))) {
5523                 msleep(50);
5524         }
5525         atomic_set(&sp->card_state, CARD_DOWN);
5526
5527         /* disable Tx and Rx traffic on the NIC */
5528         stop_nic(sp);
5529         if (flag) {
5530                 if (sp->intr_type == MSI_X) {
5531                         int i;
5532                         u16 msi_control;
5533
5534                         for (i=1; (sp->s2io_entries[i].in_use ==
5535                                 MSIX_REGISTERED_SUCCESS); i++) {
5536                                 int vector = sp->entries[i].vector;
5537                                 void *arg = sp->s2io_entries[i].arg;
5538
5539                                 free_irq(vector, arg);
5540                         }
5541                         pci_read_config_word(sp->pdev, 0x42, &msi_control);
5542                         msi_control &= 0xFFFE; /* Disable MSI */
5543                         pci_write_config_word(sp->pdev, 0x42, msi_control);
5544                         pci_disable_msix(sp->pdev);
5545                 } else {
5546                         free_irq(sp->pdev->irq, dev);
5547                         if (sp->intr_type == MSI)
5548                                 pci_disable_msi(sp->pdev);
5549                 }
5550         }
5551         /* Waiting till all Interrupt handlers are complete */
5552         cnt = 0;
5553         do {
5554                 msleep(10);
5555                 if (!atomic_read(&sp->isr_cnt))
5556                         break;
5557                 cnt++;
5558         } while(cnt < 5);
5559
5560         /* Kill tasklet. */
5561         tasklet_kill(&sp->task);
5562
5563         /* Check if the device is Quiescent and then Reset the NIC */
5564         do {
5565                 val64 = readq(&bar0->adapter_status);
5566                 if (verify_xena_quiescence(sp, val64, sp->device_enabled_once)) {
5567                         break;
5568                 }
5569
5570                 msleep(50);
5571                 cnt++;
5572                 if (cnt == 10) {
5573                         DBG_PRINT(ERR_DBG,
5574                                   "s2io_close:Device not Quiescent ");
5575                         DBG_PRINT(ERR_DBG, "adaper status reads 0x%llx\n",
5576                                   (unsigned long long) val64);
5577                         break;
5578                 }
5579         } while (1);
5580         s2io_reset(sp);
5581
5582         spin_lock_irqsave(&sp->tx_lock, flags);
5583         /* Free all Tx buffers */
5584         free_tx_buffers(sp);
5585         spin_unlock_irqrestore(&sp->tx_lock, flags);
5586
5587         /* Free all Rx buffers */
5588         spin_lock_irqsave(&sp->rx_lock, flags);
5589         free_rx_buffers(sp);
5590         spin_unlock_irqrestore(&sp->rx_lock, flags);
5591
5592         clear_bit(0, &(sp->link_state));
5593 }
5594
5595 static int s2io_card_up(nic_t * sp)
5596 {
5597         int i, ret = 0;
5598         mac_info_t *mac_control;
5599         struct config_param *config;
5600         struct net_device *dev = (struct net_device *) sp->dev;
5601
5602         /* Initialize the H/W I/O registers */
5603         if (init_nic(sp) != 0) {
5604                 DBG_PRINT(ERR_DBG, "%s: H/W initialization failed\n",
5605                           dev->name);
5606                 return -ENODEV;
5607         }
5608
5609         if (sp->intr_type == MSI)
5610                 ret = s2io_enable_msi(sp);
5611         else if (sp->intr_type == MSI_X)
5612                 ret = s2io_enable_msi_x(sp);
5613         if (ret) {
5614                 DBG_PRINT(ERR_DBG, "%s: Defaulting to INTA\n", dev->name);
5615                 sp->intr_type = INTA;
5616         }
5617
5618         /*
5619          * Initializing the Rx buffers. For now we are considering only 1
5620          * Rx ring and initializing buffers into 30 Rx blocks
5621          */
5622         mac_control = &sp->mac_control;
5623         config = &sp->config;
5624
5625         for (i = 0; i < config->rx_ring_num; i++) {
5626                 if ((ret = fill_rx_buffers(sp, i))) {
5627                         DBG_PRINT(ERR_DBG, "%s: Out of memory in Open\n",
5628                                   dev->name);
5629                         s2io_reset(sp);
5630                         free_rx_buffers(sp);
5631                         return -ENOMEM;
5632                 }
5633                 DBG_PRINT(INFO_DBG, "Buf in ring:%d is %d:\n", i,
5634                           atomic_read(&sp->rx_bufs_left[i]));
5635         }
5636
5637         /* Setting its receive mode */
5638         s2io_set_multicast(dev);
5639
5640         if (sp->lro) {
5641                 /* Initialize max aggregatable pkts based on MTU */
5642                 sp->lro_max_aggr_per_sess = ((1<<16) - 1) / dev->mtu;
5643                 /* Check if we can use(if specified) user provided value */
5644                 if (lro_max_pkts < sp->lro_max_aggr_per_sess)
5645                         sp->lro_max_aggr_per_sess = lro_max_pkts;
5646         }
5647
5648         /* Enable tasklet for the device */
5649         tasklet_init(&sp->task, s2io_tasklet, (unsigned long) dev);
5650
5651         /* Enable Rx Traffic and interrupts on the NIC */
5652         if (start_nic(sp)) {
5653                 DBG_PRINT(ERR_DBG, "%s: Starting NIC failed\n", dev->name);
5654                 tasklet_kill(&sp->task);
5655                 s2io_reset(sp);
5656                 free_irq(dev->irq, dev);
5657                 free_rx_buffers(sp);
5658                 return -ENODEV;
5659         }
5660
5661         S2IO_TIMER_CONF(sp->alarm_timer, s2io_alarm_handle, sp, (HZ/2));
5662
5663         atomic_set(&sp->card_state, CARD_UP);
5664         return 0;
5665 }
5666
5667 /**
5668  * s2io_restart_nic - Resets the NIC.
5669  * @data : long pointer to the device private structure
5670  * Description:
5671  * This function is scheduled to be run by the s2io_tx_watchdog
5672  * function after 0.5 secs to reset the NIC. The idea is to reduce
5673  * the run time of the watch dog routine which is run holding a
5674  * spin lock.
5675  */
5676
5677 static void s2io_restart_nic(unsigned long data)
5678 {
5679         struct net_device *dev = (struct net_device *) data;
5680         nic_t *sp = dev->priv;
5681
5682         s2io_card_down(sp, 0);
5683         if (s2io_card_up(sp)) {
5684                 DBG_PRINT(ERR_DBG, "%s: Device bring up failed\n",
5685                           dev->name);
5686         }
5687         netif_wake_queue(dev);
5688         DBG_PRINT(ERR_DBG, "%s: was reset by Tx watchdog timer\n",
5689                   dev->name);
5690
5691 }
5692
5693 /**
5694  *  s2io_tx_watchdog - Watchdog for transmit side.
5695  *  @dev : Pointer to net device structure
5696  *  Description:
5697  *  This function is triggered if the Tx Queue is stopped
5698  *  for a pre-defined amount of time when the Interface is still up.
5699  *  If the Interface is jammed in such a situation, the hardware is
5700  *  reset (by s2io_close) and restarted again (by s2io_open) to
5701  *  overcome any problem that might have been caused in the hardware.
5702  *  Return value:
5703  *  void
5704  */
5705
5706 static void s2io_tx_watchdog(struct net_device *dev)
5707 {
5708         nic_t *sp = dev->priv;
5709
5710         if (netif_carrier_ok(dev)) {
5711                 schedule_work(&sp->rst_timer_task);
5712         }
5713 }
5714
5715 /**
5716  *   rx_osm_handler - To perform some OS related operations on SKB.
5717  *   @sp: private member of the device structure,pointer to s2io_nic structure.
5718  *   @skb : the socket buffer pointer.
5719  *   @len : length of the packet
5720  *   @cksum : FCS checksum of the frame.
5721  *   @ring_no : the ring from which this RxD was extracted.
5722  *   Description:
5723  *   This function is called by the Tx interrupt serivce routine to perform
5724  *   some OS related operations on the SKB before passing it to the upper
5725  *   layers. It mainly checks if the checksum is OK, if so adds it to the
5726  *   SKBs cksum variable, increments the Rx packet count and passes the SKB
5727  *   to the upper layer. If the checksum is wrong, it increments the Rx
5728  *   packet error count, frees the SKB and returns error.
5729  *   Return value:
5730  *   SUCCESS on success and -1 on failure.
5731  */
5732 static int rx_osm_handler(ring_info_t *ring_data, RxD_t * rxdp)
5733 {
5734         nic_t *sp = ring_data->nic;
5735         struct net_device *dev = (struct net_device *) sp->dev;
5736         struct sk_buff *skb = (struct sk_buff *)
5737                 ((unsigned long) rxdp->Host_Control);
5738         int ring_no = ring_data->ring_no;
5739         u16 l3_csum, l4_csum;
5740         unsigned long long err = rxdp->Control_1 & RXD_T_CODE;
5741         lro_t *lro;
5742
5743         skb->dev = dev;
5744
5745         if (err) {
5746                 /*
5747                 * Drop the packet if bad transfer code. Exception being
5748                 * 0x5, which could be due to unsupported IPv6 extension header.
5749                 * In this case, we let stack handle the packet.
5750                 * Note that in this case, since checksum will be incorrect,
5751                 * stack will validate the same.
5752                 */
5753                 if (err && ((err >> 48) != 0x5)) {
5754                         DBG_PRINT(ERR_DBG, "%s: Rx error Value: 0x%llx\n",
5755                                 dev->name, err);
5756                         sp->stats.rx_crc_errors++;
5757                         dev_kfree_skb(skb);
5758                         atomic_dec(&sp->rx_bufs_left[ring_no]);
5759                         rxdp->Host_Control = 0;
5760                         return 0;
5761                 }
5762         }
5763
5764         /* Updating statistics */
5765         rxdp->Host_Control = 0;
5766         sp->rx_pkt_count++;
5767         sp->stats.rx_packets++;
5768         if (sp->rxd_mode == RXD_MODE_1) {
5769                 int len = RXD_GET_BUFFER0_SIZE_1(rxdp->Control_2);
5770
5771                 sp->stats.rx_bytes += len;
5772                 skb_put(skb, len);
5773
5774         } else if (sp->rxd_mode >= RXD_MODE_3A) {
5775                 int get_block = ring_data->rx_curr_get_info.block_index;
5776                 int get_off = ring_data->rx_curr_get_info.offset;
5777                 int buf0_len = RXD_GET_BUFFER0_SIZE_3(rxdp->Control_2);
5778                 int buf2_len = RXD_GET_BUFFER2_SIZE_3(rxdp->Control_2);
5779                 unsigned char *buff = skb_push(skb, buf0_len);
5780
5781                 buffAdd_t *ba = &ring_data->ba[get_block][get_off];
5782                 sp->stats.rx_bytes += buf0_len + buf2_len;
5783                 memcpy(buff, ba->ba_0, buf0_len);
5784
5785                 if (sp->rxd_mode == RXD_MODE_3A) {
5786                         int buf1_len = RXD_GET_BUFFER1_SIZE_3(rxdp->Control_2);
5787
5788                         skb_put(skb, buf1_len);
5789                         skb->len += buf2_len;
5790                         skb->data_len += buf2_len;
5791                         skb->truesize += buf2_len;
5792                         skb_put(skb_shinfo(skb)->frag_list, buf2_len);
5793                         sp->stats.rx_bytes += buf1_len;
5794
5795                 } else
5796                         skb_put(skb, buf2_len);
5797         }
5798
5799         if ((rxdp->Control_1 & TCP_OR_UDP_FRAME) && ((!sp->lro) ||
5800             (sp->lro && (!(rxdp->Control_1 & RXD_FRAME_IP_FRAG)))) &&
5801             (sp->rx_csum)) {
5802                 l3_csum = RXD_GET_L3_CKSUM(rxdp->Control_1);
5803                 l4_csum = RXD_GET_L4_CKSUM(rxdp->Control_1);
5804                 if ((l3_csum == L3_CKSUM_OK) && (l4_csum == L4_CKSUM_OK)) {
5805                         /*
5806                          * NIC verifies if the Checksum of the received
5807                          * frame is Ok or not and accordingly returns
5808                          * a flag in the RxD.
5809                          */
5810                         skb->ip_summed = CHECKSUM_UNNECESSARY;
5811                         if (sp->lro) {
5812                                 u32 tcp_len;
5813                                 u8 *tcp;
5814                                 int ret = 0;
5815
5816                                 ret = s2io_club_tcp_session(skb->data, &tcp,
5817                                                 &tcp_len, &lro, rxdp, sp);
5818                                 switch (ret) {
5819                                         case 3: /* Begin anew */
5820                                                 lro->parent = skb;
5821                                                 goto aggregate;
5822                                         case 1: /* Aggregate */
5823                                         {
5824                                                 lro_append_pkt(sp, lro,
5825                                                         skb, tcp_len);
5826                                                 goto aggregate;
5827                                         }
5828                                         case 4: /* Flush session */
5829                                         {
5830                                                 lro_append_pkt(sp, lro,
5831                                                         skb, tcp_len);
5832                                                 queue_rx_frame(lro->parent);
5833                                                 clear_lro_session(lro);
5834                                                 sp->mac_control.stats_info->
5835                                                     sw_stat.flush_max_pkts++;
5836                                                 goto aggregate;
5837                                         }
5838                                         case 2: /* Flush both */
5839                                                 lro->parent->data_len =
5840                                                         lro->frags_len;
5841                                                 sp->mac_control.stats_info->
5842                                                      sw_stat.sending_both++;
5843                                                 queue_rx_frame(lro->parent);
5844                                                 clear_lro_session(lro);
5845                                                 goto send_up;
5846                                         case 0: /* sessions exceeded */
5847                                         case -1: /* non-TCP or not
5848                                                   * L2 aggregatable
5849                                                   */
5850                                         case 5: /*
5851                                                  * First pkt in session not
5852                                                  * L3/L4 aggregatable
5853                                                  */
5854                                                 break;
5855                                         default:
5856                                                 DBG_PRINT(ERR_DBG,
5857                                                         "%s: Samadhana!!\n",
5858                                                          __FUNCTION__);
5859                                                 BUG();
5860                                 }
5861                         }
5862                 } else {
5863                         /*
5864                          * Packet with erroneous checksum, let the
5865                          * upper layers deal with it.
5866                          */
5867                         skb->ip_summed = CHECKSUM_NONE;
5868                 }
5869         } else {
5870                 skb->ip_summed = CHECKSUM_NONE;
5871         }
5872
5873         if (!sp->lro) {
5874                 skb->protocol = eth_type_trans(skb, dev);
5875 #ifdef CONFIG_S2IO_NAPI
5876                 if (sp->vlgrp && RXD_GET_VLAN_TAG(rxdp->Control_2)) {
5877                         /* Queueing the vlan frame to the upper layer */
5878                         vlan_hwaccel_receive_skb(skb, sp->vlgrp,
5879                                 RXD_GET_VLAN_TAG(rxdp->Control_2));
5880                 } else {
5881                         netif_receive_skb(skb);
5882                 }
5883 #else
5884                 if (sp->vlgrp && RXD_GET_VLAN_TAG(rxdp->Control_2)) {
5885                         /* Queueing the vlan frame to the upper layer */
5886                         vlan_hwaccel_rx(skb, sp->vlgrp,
5887                                 RXD_GET_VLAN_TAG(rxdp->Control_2));
5888                 } else {
5889                         netif_rx(skb);
5890                 }
5891 #endif
5892         } else {
5893 send_up:
5894                 queue_rx_frame(skb);
5895         }
5896         dev->last_rx = jiffies;
5897 aggregate:
5898         atomic_dec(&sp->rx_bufs_left[ring_no]);
5899         return SUCCESS;
5900 }
5901
5902 /**
5903  *  s2io_link - stops/starts the Tx queue.
5904  *  @sp : private member of the device structure, which is a pointer to the
5905  *  s2io_nic structure.
5906  *  @link : inidicates whether link is UP/DOWN.
5907  *  Description:
5908  *  This function stops/starts the Tx queue depending on whether the link
5909  *  status of the NIC is is down or up. This is called by the Alarm
5910  *  interrupt handler whenever a link change interrupt comes up.
5911  *  Return value:
5912  *  void.
5913  */
5914
5915 static void s2io_link(nic_t * sp, int link)
5916 {
5917         struct net_device *dev = (struct net_device *) sp->dev;
5918
5919         if (link != sp->last_link_state) {
5920                 if (link == LINK_DOWN) {
5921                         DBG_PRINT(ERR_DBG, "%s: Link down\n", dev->name);
5922                         netif_carrier_off(dev);
5923                 } else {
5924                         DBG_PRINT(ERR_DBG, "%s: Link Up\n", dev->name);
5925                         netif_carrier_on(dev);
5926                 }
5927         }
5928         sp->last_link_state = link;
5929 }
5930
5931 /**
5932  *  get_xena_rev_id - to identify revision ID of xena.
5933  *  @pdev : PCI Dev structure
5934  *  Description:
5935  *  Function to identify the Revision ID of xena.
5936  *  Return value:
5937  *  returns the revision ID of the device.
5938  */
5939
5940 static int get_xena_rev_id(struct pci_dev *pdev)
5941 {
5942         u8 id = 0;
5943         int ret;
5944         ret = pci_read_config_byte(pdev, PCI_REVISION_ID, (u8 *) & id);
5945         return id;
5946 }
5947
5948 /**
5949  *  s2io_init_pci -Initialization of PCI and PCI-X configuration registers .
5950  *  @sp : private member of the device structure, which is a pointer to the
5951  *  s2io_nic structure.
5952  *  Description:
5953  *  This function initializes a few of the PCI and PCI-X configuration registers
5954  *  with recommended values.
5955  *  Return value:
5956  *  void
5957  */
5958
5959 static void s2io_init_pci(nic_t * sp)
5960 {
5961         u16 pci_cmd = 0, pcix_cmd = 0;
5962
5963         /* Enable Data Parity Error Recovery in PCI-X command register. */
5964         pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
5965                              &(pcix_cmd));
5966         pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
5967                               (pcix_cmd | 1));
5968         pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
5969                              &(pcix_cmd));
5970
5971         /* Set the PErr Response bit in PCI command register. */
5972         pci_read_config_word(sp->pdev, PCI_COMMAND, &pci_cmd);
5973         pci_write_config_word(sp->pdev, PCI_COMMAND,
5974                               (pci_cmd | PCI_COMMAND_PARITY));
5975         pci_read_config_word(sp->pdev, PCI_COMMAND, &pci_cmd);
5976 }
5977
5978 MODULE_AUTHOR("Raghavendra Koushik <raghavendra.koushik@neterion.com>");
5979 MODULE_LICENSE("GPL");
5980 MODULE_VERSION(DRV_VERSION);
5981
5982 module_param(tx_fifo_num, int, 0);
5983 module_param(rx_ring_num, int, 0);
5984 module_param(rx_ring_mode, int, 0);
5985 module_param_array(tx_fifo_len, uint, NULL, 0);
5986 module_param_array(rx_ring_sz, uint, NULL, 0);
5987 module_param_array(rts_frm_len, uint, NULL, 0);
5988 module_param(use_continuous_tx_intrs, int, 1);
5989 module_param(rmac_pause_time, int, 0);
5990 module_param(mc_pause_threshold_q0q3, int, 0);
5991 module_param(mc_pause_threshold_q4q7, int, 0);
5992 module_param(shared_splits, int, 0);
5993 module_param(tmac_util_period, int, 0);
5994 module_param(rmac_util_period, int, 0);
5995 module_param(bimodal, bool, 0);
5996 module_param(l3l4hdr_size, int , 0);
5997 #ifndef CONFIG_S2IO_NAPI
5998 module_param(indicate_max_pkts, int, 0);
5999 #endif
6000 module_param(rxsync_frequency, int, 0);
6001 module_param(intr_type, int, 0);
6002 module_param(lro, int, 0);
6003 module_param(lro_max_pkts, int, 0);
6004
6005 static int s2io_verify_parm(struct pci_dev *pdev, u8 *dev_intr_type)
6006 {
6007         if ( tx_fifo_num > 8) {
6008                 DBG_PRINT(ERR_DBG, "s2io: Requested number of Tx fifos not "
6009                          "supported\n");
6010                 DBG_PRINT(ERR_DBG, "s2io: Default to 8 Tx fifos\n");
6011                 tx_fifo_num = 8;
6012         }
6013         if ( rx_ring_num > 8) {
6014                 DBG_PRINT(ERR_DBG, "s2io: Requested number of Rx rings not "
6015                          "supported\n");
6016                 DBG_PRINT(ERR_DBG, "s2io: Default to 8 Rx rings\n");
6017                 rx_ring_num = 8;
6018         }
6019 #ifdef CONFIG_S2IO_NAPI
6020         if (*dev_intr_type != INTA) {
6021                 DBG_PRINT(ERR_DBG, "s2io: NAPI cannot be enabled when "
6022                           "MSI/MSI-X is enabled. Defaulting to INTA\n");
6023                 *dev_intr_type = INTA;
6024         }
6025 #endif
6026 #ifndef CONFIG_PCI_MSI
6027         if (*dev_intr_type != INTA) {
6028                 DBG_PRINT(ERR_DBG, "s2io: This kernel does not support"
6029                           "MSI/MSI-X. Defaulting to INTA\n");
6030                 *dev_intr_type = INTA;
6031         }
6032 #else
6033         if (*dev_intr_type > MSI_X) {
6034                 DBG_PRINT(ERR_DBG, "s2io: Wrong intr_type requested. "
6035                           "Defaulting to INTA\n");
6036                 *dev_intr_type = INTA;
6037         }
6038 #endif
6039         if ((*dev_intr_type == MSI_X) &&
6040                         ((pdev->device != PCI_DEVICE_ID_HERC_WIN) &&
6041                         (pdev->device != PCI_DEVICE_ID_HERC_UNI))) {
6042                 DBG_PRINT(ERR_DBG, "s2io: Xframe I does not support MSI_X. "
6043                                         "Defaulting to INTA\n");
6044                 *dev_intr_type = INTA;
6045         }
6046         if (rx_ring_mode > 3) {
6047                 DBG_PRINT(ERR_DBG, "s2io: Requested ring mode not supported\n");
6048                 DBG_PRINT(ERR_DBG, "s2io: Defaulting to 3-buffer mode\n");
6049                 rx_ring_mode = 3;
6050         }
6051         return SUCCESS;
6052 }
6053
6054 /**
6055  *  s2io_init_nic - Initialization of the adapter .
6056  *  @pdev : structure containing the PCI related information of the device.
6057  *  @pre: List of PCI devices supported by the driver listed in s2io_tbl.
6058  *  Description:
6059  *  The function initializes an adapter identified by the pci_dec structure.
6060  *  All OS related initialization including memory and device structure and
6061  *  initlaization of the device private variable is done. Also the swapper
6062  *  control register is initialized to enable read and write into the I/O
6063  *  registers of the device.
6064  *  Return value:
6065  *  returns 0 on success and negative on failure.
6066  */
6067
6068 static int __devinit
6069 s2io_init_nic(struct pci_dev *pdev, const struct pci_device_id *pre)
6070 {
6071         nic_t *sp;
6072         struct net_device *dev;
6073         int i, j, ret;
6074         int dma_flag = FALSE;
6075         u32 mac_up, mac_down;
6076         u64 val64 = 0, tmp64 = 0;
6077         XENA_dev_config_t __iomem *bar0 = NULL;
6078         u16 subid;
6079         mac_info_t *mac_control;
6080         struct config_param *config;
6081         int mode;
6082         u8 dev_intr_type = intr_type;
6083
6084         if ((ret = s2io_verify_parm(pdev, &dev_intr_type)))
6085                 return ret;
6086
6087         if ((ret = pci_enable_device(pdev))) {
6088                 DBG_PRINT(ERR_DBG,
6089                           "s2io_init_nic: pci_enable_device failed\n");
6090                 return ret;
6091         }
6092
6093         if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
6094                 DBG_PRINT(INIT_DBG, "s2io_init_nic: Using 64bit DMA\n");
6095                 dma_flag = TRUE;
6096                 if (pci_set_consistent_dma_mask
6097                     (pdev, DMA_64BIT_MASK)) {
6098                         DBG_PRINT(ERR_DBG,
6099                                   "Unable to obtain 64bit DMA for \
6100                                         consistent allocations\n");
6101                         pci_disable_device(pdev);
6102                         return -ENOMEM;
6103                 }
6104         } else if (!pci_set_dma_mask(pdev, DMA_32BIT_MASK)) {
6105                 DBG_PRINT(INIT_DBG, "s2io_init_nic: Using 32bit DMA\n");
6106         } else {
6107                 pci_disable_device(pdev);
6108                 return -ENOMEM;
6109         }
6110         if (dev_intr_type != MSI_X) {
6111                 if (pci_request_regions(pdev, s2io_driver_name)) {
6112                         DBG_PRINT(ERR_DBG, "Request Regions failed\n"),
6113                             pci_disable_device(pdev);
6114                         return -ENODEV;
6115                 }
6116         }
6117         else {
6118                 if (!(request_mem_region(pci_resource_start(pdev, 0),
6119                          pci_resource_len(pdev, 0), s2io_driver_name))) {
6120                         DBG_PRINT(ERR_DBG, "bar0 Request Regions failed\n");
6121                         pci_disable_device(pdev);
6122                         return -ENODEV;
6123                 }
6124                 if (!(request_mem_region(pci_resource_start(pdev, 2),
6125                          pci_resource_len(pdev, 2), s2io_driver_name))) {
6126                         DBG_PRINT(ERR_DBG, "bar1 Request Regions failed\n");
6127                         release_mem_region(pci_resource_start(pdev, 0),
6128                                    pci_resource_len(pdev, 0));
6129                         pci_disable_device(pdev);
6130                         return -ENODEV;
6131                 }
6132         }
6133
6134         dev = alloc_etherdev(sizeof(nic_t));
6135         if (dev == NULL) {
6136                 DBG_PRINT(ERR_DBG, "Device allocation failed\n");
6137                 pci_disable_device(pdev);
6138                 pci_release_regions(pdev);
6139                 return -ENODEV;
6140         }
6141
6142         pci_set_master(pdev);
6143         pci_set_drvdata(pdev, dev);
6144         SET_MODULE_OWNER(dev);
6145         SET_NETDEV_DEV(dev, &pdev->dev);
6146
6147         /*  Private member variable initialized to s2io NIC structure */
6148         sp = dev->priv;
6149         memset(sp, 0, sizeof(nic_t));
6150         sp->dev = dev;
6151         sp->pdev = pdev;
6152         sp->high_dma_flag = dma_flag;
6153         sp->device_enabled_once = FALSE;
6154         if (rx_ring_mode == 1)
6155                 sp->rxd_mode = RXD_MODE_1;
6156         if (rx_ring_mode == 2)
6157                 sp->rxd_mode = RXD_MODE_3B;
6158         if (rx_ring_mode == 3)
6159                 sp->rxd_mode = RXD_MODE_3A;
6160
6161         sp->intr_type = dev_intr_type;
6162
6163         if ((pdev->device == PCI_DEVICE_ID_HERC_WIN) ||
6164                 (pdev->device == PCI_DEVICE_ID_HERC_UNI))
6165                 sp->device_type = XFRAME_II_DEVICE;
6166         else
6167                 sp->device_type = XFRAME_I_DEVICE;
6168
6169         sp->lro = lro;
6170
6171         /* Initialize some PCI/PCI-X fields of the NIC. */
6172         s2io_init_pci(sp);
6173
6174         /*
6175          * Setting the device configuration parameters.
6176          * Most of these parameters can be specified by the user during
6177          * module insertion as they are module loadable parameters. If
6178          * these parameters are not not specified during load time, they
6179          * are initialized with default values.
6180          */
6181         mac_control = &sp->mac_control;
6182         config = &sp->config;
6183
6184         /* Tx side parameters. */
6185         config->tx_fifo_num = tx_fifo_num;
6186         for (i = 0; i < MAX_TX_FIFOS; i++) {
6187                 config->tx_cfg[i].fifo_len = tx_fifo_len[i];
6188                 config->tx_cfg[i].fifo_priority = i;
6189         }
6190
6191         /* mapping the QoS priority to the configured fifos */
6192         for (i = 0; i < MAX_TX_FIFOS; i++)
6193                 config->fifo_mapping[i] = fifo_map[config->tx_fifo_num][i];
6194
6195         config->tx_intr_type = TXD_INT_TYPE_UTILZ;
6196         for (i = 0; i < config->tx_fifo_num; i++) {
6197                 config->tx_cfg[i].f_no_snoop =
6198                     (NO_SNOOP_TXD | NO_SNOOP_TXD_BUFFER);
6199                 if (config->tx_cfg[i].fifo_len < 65) {
6200                         config->tx_intr_type = TXD_INT_TYPE_PER_LIST;
6201                         break;
6202                 }
6203         }
6204         /* + 2 because one Txd for skb->data and one Txd for UFO */
6205         config->max_txds = MAX_SKB_FRAGS + 2;
6206
6207         /* Rx side parameters. */
6208         config->rx_ring_num = rx_ring_num;
6209         for (i = 0; i < MAX_RX_RINGS; i++) {
6210                 config->rx_cfg[i].num_rxd = rx_ring_sz[i] *
6211                     (rxd_count[sp->rxd_mode] + 1);
6212                 config->rx_cfg[i].ring_priority = i;
6213         }
6214
6215         for (i = 0; i < rx_ring_num; i++) {
6216                 config->rx_cfg[i].ring_org = RING_ORG_BUFF1;
6217                 config->rx_cfg[i].f_no_snoop =
6218                     (NO_SNOOP_RXD | NO_SNOOP_RXD_BUFFER);
6219         }
6220
6221         /*  Setting Mac Control parameters */
6222         mac_control->rmac_pause_time = rmac_pause_time;
6223         mac_control->mc_pause_threshold_q0q3 = mc_pause_threshold_q0q3;
6224         mac_control->mc_pause_threshold_q4q7 = mc_pause_threshold_q4q7;
6225
6226
6227         /* Initialize Ring buffer parameters. */
6228         for (i = 0; i < config->rx_ring_num; i++)
6229                 atomic_set(&sp->rx_bufs_left[i], 0);
6230
6231         /* Initialize the number of ISRs currently running */
6232         atomic_set(&sp->isr_cnt, 0);
6233
6234         /*  initialize the shared memory used by the NIC and the host */
6235         if (init_shared_mem(sp)) {
6236                 DBG_PRINT(ERR_DBG, "%s: Memory allocation failed\n",
6237                           __FUNCTION__);
6238                 ret = -ENOMEM;
6239                 goto mem_alloc_failed;
6240         }
6241
6242         sp->bar0 = ioremap(pci_resource_start(pdev, 0),
6243                                      pci_resource_len(pdev, 0));
6244         if (!sp->bar0) {
6245                 DBG_PRINT(ERR_DBG, "%s: S2IO: cannot remap io mem1\n",
6246                           dev->name);
6247                 ret = -ENOMEM;
6248                 goto bar0_remap_failed;
6249         }
6250
6251         sp->bar1 = ioremap(pci_resource_start(pdev, 2),
6252                                      pci_resource_len(pdev, 2));
6253         if (!sp->bar1) {
6254                 DBG_PRINT(ERR_DBG, "%s: S2IO: cannot remap io mem2\n",
6255                           dev->name);
6256                 ret = -ENOMEM;
6257                 goto bar1_remap_failed;
6258         }
6259
6260         dev->irq = pdev->irq;
6261         dev->base_addr = (unsigned long) sp->bar0;
6262
6263         /* Initializing the BAR1 address as the start of the FIFO pointer. */
6264         for (j = 0; j < MAX_TX_FIFOS; j++) {
6265                 mac_control->tx_FIFO_start[j] = (TxFIFO_element_t __iomem *)
6266                     (sp->bar1 + (j * 0x00020000));
6267         }
6268
6269         /*  Driver entry points */
6270         dev->open = &s2io_open;
6271         dev->stop = &s2io_close;
6272         dev->hard_start_xmit = &s2io_xmit;
6273         dev->get_stats = &s2io_get_stats;
6274         dev->set_multicast_list = &s2io_set_multicast;
6275         dev->do_ioctl = &s2io_ioctl;
6276         dev->change_mtu = &s2io_change_mtu;
6277         SET_ETHTOOL_OPS(dev, &netdev_ethtool_ops);
6278         dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
6279         dev->vlan_rx_register = s2io_vlan_rx_register;
6280         dev->vlan_rx_kill_vid = (void *)s2io_vlan_rx_kill_vid;
6281
6282         /*
6283          * will use eth_mac_addr() for  dev->set_mac_address
6284          * mac address will be set every time dev->open() is called
6285          */
6286 #if defined(CONFIG_S2IO_NAPI)
6287         dev->poll = s2io_poll;
6288         dev->weight = 32;
6289 #endif
6290
6291         dev->features |= NETIF_F_SG | NETIF_F_IP_CSUM;
6292         if (sp->high_dma_flag == TRUE)
6293                 dev->features |= NETIF_F_HIGHDMA;
6294 #ifdef NETIF_F_TSO
6295         dev->features |= NETIF_F_TSO;
6296 #endif
6297         if (sp->device_type & XFRAME_II_DEVICE) {
6298                 dev->features |= NETIF_F_UFO;
6299                 dev->features |= NETIF_F_HW_CSUM;
6300         }
6301
6302         dev->tx_timeout = &s2io_tx_watchdog;
6303         dev->watchdog_timeo = WATCH_DOG_TIMEOUT;
6304         INIT_WORK(&sp->rst_timer_task,
6305                   (void (*)(void *)) s2io_restart_nic, dev);
6306         INIT_WORK(&sp->set_link_task,
6307                   (void (*)(void *)) s2io_set_link, sp);
6308
6309         pci_save_state(sp->pdev);
6310
6311         /* Setting swapper control on the NIC, for proper reset operation */
6312         if (s2io_set_swapper(sp)) {
6313                 DBG_PRINT(ERR_DBG, "%s:swapper settings are wrong\n",
6314                           dev->name);
6315                 ret = -EAGAIN;
6316                 goto set_swap_failed;
6317         }
6318
6319         /* Verify if the Herc works on the slot its placed into */
6320         if (sp->device_type & XFRAME_II_DEVICE) {
6321                 mode = s2io_verify_pci_mode(sp);
6322                 if (mode < 0) {
6323                         DBG_PRINT(ERR_DBG, "%s: ", __FUNCTION__);
6324                         DBG_PRINT(ERR_DBG, " Unsupported PCI bus mode\n");
6325                         ret = -EBADSLT;
6326                         goto set_swap_failed;
6327                 }
6328         }
6329
6330         /* Not needed for Herc */
6331         if (sp->device_type & XFRAME_I_DEVICE) {
6332                 /*
6333                  * Fix for all "FFs" MAC address problems observed on
6334                  * Alpha platforms
6335                  */
6336                 fix_mac_address(sp);
6337                 s2io_reset(sp);
6338         }
6339
6340         /*
6341          * MAC address initialization.
6342          * For now only one mac address will be read and used.
6343          */
6344         bar0 = sp->bar0;
6345         val64 = RMAC_ADDR_CMD_MEM_RD | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
6346             RMAC_ADDR_CMD_MEM_OFFSET(0 + MAC_MAC_ADDR_START_OFFSET);
6347         writeq(val64, &bar0->rmac_addr_cmd_mem);
6348         wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
6349                       RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING);
6350         tmp64 = readq(&bar0->rmac_addr_data0_mem);
6351         mac_down = (u32) tmp64;
6352         mac_up = (u32) (tmp64 >> 32);
6353
6354         memset(sp->def_mac_addr[0].mac_addr, 0, sizeof(ETH_ALEN));
6355
6356         sp->def_mac_addr[0].mac_addr[3] = (u8) (mac_up);
6357         sp->def_mac_addr[0].mac_addr[2] = (u8) (mac_up >> 8);
6358         sp->def_mac_addr[0].mac_addr[1] = (u8) (mac_up >> 16);
6359         sp->def_mac_addr[0].mac_addr[0] = (u8) (mac_up >> 24);
6360         sp->def_mac_addr[0].mac_addr[5] = (u8) (mac_down >> 16);
6361         sp->def_mac_addr[0].mac_addr[4] = (u8) (mac_down >> 24);
6362
6363         /*  Set the factory defined MAC address initially   */
6364         dev->addr_len = ETH_ALEN;
6365         memcpy(dev->dev_addr, sp->def_mac_addr, ETH_ALEN);
6366
6367         /*
6368          * Initialize the tasklet status and link state flags
6369          * and the card state parameter
6370          */
6371         atomic_set(&(sp->card_state), 0);
6372         sp->tasklet_status = 0;
6373         sp->link_state = 0;
6374
6375         /* Initialize spinlocks */
6376         spin_lock_init(&sp->tx_lock);
6377 #ifndef CONFIG_S2IO_NAPI
6378         spin_lock_init(&sp->put_lock);
6379 #endif
6380         spin_lock_init(&sp->rx_lock);
6381
6382         /*
6383          * SXE-002: Configure link and activity LED to init state
6384          * on driver load.
6385          */
6386         subid = sp->pdev->subsystem_device;
6387         if ((subid & 0xFF) >= 0x07) {
6388                 val64 = readq(&bar0->gpio_control);
6389                 val64 |= 0x0000800000000000ULL;
6390                 writeq(val64, &bar0->gpio_control);
6391                 val64 = 0x0411040400000000ULL;
6392                 writeq(val64, (void __iomem *) bar0 + 0x2700);
6393                 val64 = readq(&bar0->gpio_control);
6394         }
6395
6396         sp->rx_csum = 1;        /* Rx chksum verify enabled by default */
6397
6398         if (register_netdev(dev)) {
6399                 DBG_PRINT(ERR_DBG, "Device registration failed\n");
6400                 ret = -ENODEV;
6401                 goto register_failed;
6402         }
6403         s2io_vpd_read(sp);
6404         DBG_PRINT(ERR_DBG, "%s: Neterion %s",dev->name, sp->product_name);
6405         DBG_PRINT(ERR_DBG, "(rev %d), Driver version %s\n",
6406                                 get_xena_rev_id(sp->pdev),
6407                                 s2io_driver_version);
6408         DBG_PRINT(ERR_DBG, "Copyright(c) 2002-2005 Neterion Inc.\n");
6409         DBG_PRINT(ERR_DBG, "%s: MAC ADDR: "
6410                           "%02x:%02x:%02x:%02x:%02x:%02x\n", dev->name,
6411                           sp->def_mac_addr[0].mac_addr[0],
6412                           sp->def_mac_addr[0].mac_addr[1],
6413                           sp->def_mac_addr[0].mac_addr[2],
6414                           sp->def_mac_addr[0].mac_addr[3],
6415                           sp->def_mac_addr[0].mac_addr[4],
6416                           sp->def_mac_addr[0].mac_addr[5]);
6417         if (sp->device_type & XFRAME_II_DEVICE) {
6418                 mode = s2io_print_pci_mode(sp);
6419                 if (mode < 0) {
6420                         DBG_PRINT(ERR_DBG, " Unsupported PCI bus mode\n");
6421                         ret = -EBADSLT;
6422                         unregister_netdev(dev);
6423                         goto set_swap_failed;
6424                 }
6425         }
6426         switch(sp->rxd_mode) {
6427                 case RXD_MODE_1:
6428                     DBG_PRINT(ERR_DBG, "%s: 1-Buffer receive mode enabled\n",
6429                                                 dev->name);
6430                     break;
6431                 case RXD_MODE_3B:
6432                     DBG_PRINT(ERR_DBG, "%s: 2-Buffer receive mode enabled\n",
6433                                                 dev->name);
6434                     break;
6435                 case RXD_MODE_3A:
6436                     DBG_PRINT(ERR_DBG, "%s: 3-Buffer receive mode enabled\n",
6437                                                 dev->name);
6438                     break;
6439         }
6440 #ifdef CONFIG_S2IO_NAPI
6441         DBG_PRINT(ERR_DBG, "%s: NAPI enabled\n", dev->name);
6442 #endif
6443         switch(sp->intr_type) {
6444                 case INTA:
6445                     DBG_PRINT(ERR_DBG, "%s: Interrupt type INTA\n", dev->name);
6446                     break;
6447                 case MSI:
6448                     DBG_PRINT(ERR_DBG, "%s: Interrupt type MSI\n", dev->name);
6449                     break;
6450                 case MSI_X:
6451                     DBG_PRINT(ERR_DBG, "%s: Interrupt type MSI-X\n", dev->name);
6452                     break;
6453         }
6454         if (sp->lro)
6455                 DBG_PRINT(ERR_DBG, "%s: Large receive offload enabled\n",
6456                           dev->name);
6457
6458         /* Initialize device name */
6459         sprintf(sp->name, "%s Neterion %s", dev->name, sp->product_name);
6460
6461         /* Initialize bimodal Interrupts */
6462         sp->config.bimodal = bimodal;
6463         if (!(sp->device_type & XFRAME_II_DEVICE) && bimodal) {
6464                 sp->config.bimodal = 0;
6465                 DBG_PRINT(ERR_DBG,"%s:Bimodal intr not supported by Xframe I\n",
6466                         dev->name);
6467         }
6468
6469         /*
6470          * Make Link state as off at this point, when the Link change
6471          * interrupt comes the state will be automatically changed to
6472          * the right state.
6473          */
6474         netif_carrier_off(dev);
6475
6476         return 0;
6477
6478       register_failed:
6479       set_swap_failed:
6480         iounmap(sp->bar1);
6481       bar1_remap_failed:
6482         iounmap(sp->bar0);
6483       bar0_remap_failed:
6484       mem_alloc_failed:
6485         free_shared_mem(sp);
6486         pci_disable_device(pdev);
6487         if (dev_intr_type != MSI_X)
6488                 pci_release_regions(pdev);
6489         else {
6490                 release_mem_region(pci_resource_start(pdev, 0),
6491                         pci_resource_len(pdev, 0));
6492                 release_mem_region(pci_resource_start(pdev, 2),
6493                         pci_resource_len(pdev, 2));
6494         }
6495         pci_set_drvdata(pdev, NULL);
6496         free_netdev(dev);
6497
6498         return ret;
6499 }
6500
6501 /**
6502  * s2io_rem_nic - Free the PCI device
6503  * @pdev: structure containing the PCI related information of the device.
6504  * Description: This function is called by the Pci subsystem to release a
6505  * PCI device and free up all resource held up by the device. This could
6506  * be in response to a Hot plug event or when the driver is to be removed
6507  * from memory.
6508  */
6509
6510 static void __devexit s2io_rem_nic(struct pci_dev *pdev)
6511 {
6512         struct net_device *dev =
6513             (struct net_device *) pci_get_drvdata(pdev);
6514         nic_t *sp;
6515
6516         if (dev == NULL) {
6517                 DBG_PRINT(ERR_DBG, "Driver Data is NULL!!\n");
6518                 return;
6519         }
6520
6521         sp = dev->priv;
6522         unregister_netdev(dev);
6523
6524         free_shared_mem(sp);
6525         iounmap(sp->bar0);
6526         iounmap(sp->bar1);
6527         pci_disable_device(pdev);
6528         if (sp->intr_type != MSI_X)
6529                 pci_release_regions(pdev);
6530         else {
6531                 release_mem_region(pci_resource_start(pdev, 0),
6532                         pci_resource_len(pdev, 0));
6533                 release_mem_region(pci_resource_start(pdev, 2),
6534                         pci_resource_len(pdev, 2));
6535         }
6536         pci_set_drvdata(pdev, NULL);
6537         free_netdev(dev);
6538 }
6539
6540 /**
6541  * s2io_starter - Entry point for the driver
6542  * Description: This function is the entry point for the driver. It verifies
6543  * the module loadable parameters and initializes PCI configuration space.
6544  */
6545
6546 int __init s2io_starter(void)
6547 {
6548         return pci_module_init(&s2io_driver);
6549 }
6550
6551 /**
6552  * s2io_closer - Cleanup routine for the driver
6553  * Description: This function is the cleanup routine for the driver. It unregist * ers the driver.
6554  */
6555
6556 static void s2io_closer(void)
6557 {
6558         pci_unregister_driver(&s2io_driver);
6559         DBG_PRINT(INIT_DBG, "cleanup done\n");
6560 }
6561
6562 module_init(s2io_starter);
6563 module_exit(s2io_closer);
6564
6565 static int check_L2_lro_capable(u8 *buffer, struct iphdr **ip,
6566                 struct tcphdr **tcp, RxD_t *rxdp)
6567 {
6568         int ip_off;
6569         u8 l2_type = (u8)((rxdp->Control_1 >> 37) & 0x7), ip_len;
6570
6571         if (!(rxdp->Control_1 & RXD_FRAME_PROTO_TCP)) {
6572                 DBG_PRINT(INIT_DBG,"%s: Non-TCP frames not supported for LRO\n",
6573                           __FUNCTION__);
6574                 return -1;
6575         }
6576
6577         /* TODO:
6578          * By default the VLAN field in the MAC is stripped by the card, if this
6579          * feature is turned off in rx_pa_cfg register, then the ip_off field
6580          * has to be shifted by a further 2 bytes
6581          */
6582         switch (l2_type) {
6583                 case 0: /* DIX type */
6584                 case 4: /* DIX type with VLAN */
6585                         ip_off = HEADER_ETHERNET_II_802_3_SIZE;
6586                         break;
6587                 /* LLC, SNAP etc are considered non-mergeable */
6588                 default:
6589                         return -1;
6590         }
6591
6592         *ip = (struct iphdr *)((u8 *)buffer + ip_off);
6593         ip_len = (u8)((*ip)->ihl);
6594         ip_len <<= 2;
6595         *tcp = (struct tcphdr *)((unsigned long)*ip + ip_len);
6596
6597         return 0;
6598 }
6599
6600 static int check_for_socket_match(lro_t *lro, struct iphdr *ip,
6601                                   struct tcphdr *tcp)
6602 {
6603         DBG_PRINT(INFO_DBG,"%s: Been here...\n", __FUNCTION__);
6604         if ((lro->iph->saddr != ip->saddr) || (lro->iph->daddr != ip->daddr) ||
6605            (lro->tcph->source != tcp->source) || (lro->tcph->dest != tcp->dest))
6606                 return -1;
6607         return 0;
6608 }
6609
6610 static inline int get_l4_pyld_length(struct iphdr *ip, struct tcphdr *tcp)
6611 {
6612         return(ntohs(ip->tot_len) - (ip->ihl << 2) - (tcp->doff << 2));
6613 }
6614
6615 static void initiate_new_session(lro_t *lro, u8 *l2h,
6616                      struct iphdr *ip, struct tcphdr *tcp, u32 tcp_pyld_len)
6617 {
6618         DBG_PRINT(INFO_DBG,"%s: Been here...\n", __FUNCTION__);
6619         lro->l2h = l2h;
6620         lro->iph = ip;
6621         lro->tcph = tcp;
6622         lro->tcp_next_seq = tcp_pyld_len + ntohl(tcp->seq);
6623         lro->tcp_ack = ntohl(tcp->ack_seq);
6624         lro->sg_num = 1;
6625         lro->total_len = ntohs(ip->tot_len);
6626         lro->frags_len = 0;
6627         /*
6628          * check if we saw TCP timestamp. Other consistency checks have
6629          * already been done.
6630          */
6631         if (tcp->doff == 8) {
6632                 u32 *ptr;
6633                 ptr = (u32 *)(tcp+1);
6634                 lro->saw_ts = 1;
6635                 lro->cur_tsval = *(ptr+1);
6636                 lro->cur_tsecr = *(ptr+2);
6637         }
6638         lro->in_use = 1;
6639 }
6640
6641 static void update_L3L4_header(nic_t *sp, lro_t *lro)
6642 {
6643         struct iphdr *ip = lro->iph;
6644         struct tcphdr *tcp = lro->tcph;
6645         u16 nchk;
6646         StatInfo_t *statinfo = sp->mac_control.stats_info;
6647         DBG_PRINT(INFO_DBG,"%s: Been here...\n", __FUNCTION__);
6648
6649         /* Update L3 header */
6650         ip->tot_len = htons(lro->total_len);
6651         ip->check = 0;
6652         nchk = ip_fast_csum((u8 *)lro->iph, ip->ihl);
6653         ip->check = nchk;
6654
6655         /* Update L4 header */
6656         tcp->ack_seq = lro->tcp_ack;
6657         tcp->window = lro->window;
6658
6659         /* Update tsecr field if this session has timestamps enabled */
6660         if (lro->saw_ts) {
6661                 u32 *ptr = (u32 *)(tcp + 1);
6662                 *(ptr+2) = lro->cur_tsecr;
6663         }
6664
6665         /* Update counters required for calculation of
6666          * average no. of packets aggregated.
6667          */
6668         statinfo->sw_stat.sum_avg_pkts_aggregated += lro->sg_num;
6669         statinfo->sw_stat.num_aggregations++;
6670 }
6671
6672 static void aggregate_new_rx(lro_t *lro, struct iphdr *ip,
6673                 struct tcphdr *tcp, u32 l4_pyld)
6674 {
6675         DBG_PRINT(INFO_DBG,"%s: Been here...\n", __FUNCTION__);
6676         lro->total_len += l4_pyld;
6677         lro->frags_len += l4_pyld;
6678         lro->tcp_next_seq += l4_pyld;
6679         lro->sg_num++;
6680
6681         /* Update ack seq no. and window ad(from this pkt) in LRO object */
6682         lro->tcp_ack = tcp->ack_seq;
6683         lro->window = tcp->window;
6684
6685         if (lro->saw_ts) {
6686                 u32 *ptr;
6687                 /* Update tsecr and tsval from this packet */
6688                 ptr = (u32 *) (tcp + 1);
6689                 lro->cur_tsval = *(ptr + 1);
6690                 lro->cur_tsecr = *(ptr + 2);
6691         }
6692 }
6693
6694 static int verify_l3_l4_lro_capable(lro_t *l_lro, struct iphdr *ip,
6695                                     struct tcphdr *tcp, u32 tcp_pyld_len)
6696 {
6697         u8 *ptr;
6698
6699         DBG_PRINT(INFO_DBG,"%s: Been here...\n", __FUNCTION__);
6700
6701         if (!tcp_pyld_len) {
6702                 /* Runt frame or a pure ack */
6703                 return -1;
6704         }
6705
6706         if (ip->ihl != 5) /* IP has options */
6707                 return -1;
6708
6709         if (tcp->urg || tcp->psh || tcp->rst || tcp->syn || tcp->fin ||
6710                                                                 !tcp->ack) {
6711                 /*
6712                  * Currently recognize only the ack control word and
6713                  * any other control field being set would result in
6714                  * flushing the LRO session
6715                  */
6716                 return -1;
6717         }
6718
6719         /*
6720          * Allow only one TCP timestamp option. Don't aggregate if
6721          * any other options are detected.
6722          */
6723         if (tcp->doff != 5 && tcp->doff != 8)
6724                 return -1;
6725
6726         if (tcp->doff == 8) {
6727                 ptr = (u8 *)(tcp + 1);
6728                 while (*ptr == TCPOPT_NOP)
6729                         ptr++;
6730                 if (*ptr != TCPOPT_TIMESTAMP || *(ptr+1) != TCPOLEN_TIMESTAMP)
6731                         return -1;
6732
6733                 /* Ensure timestamp value increases monotonically */
6734                 if (l_lro)
6735                         if (l_lro->cur_tsval > *((u32 *)(ptr+2)))
6736                                 return -1;
6737
6738                 /* timestamp echo reply should be non-zero */
6739                 if (*((u32 *)(ptr+6)) == 0)
6740                         return -1;
6741         }
6742
6743         return 0;
6744 }
6745
6746 static int
6747 s2io_club_tcp_session(u8 *buffer, u8 **tcp, u32 *tcp_len, lro_t **lro,
6748                       RxD_t *rxdp, nic_t *sp)
6749 {
6750         struct iphdr *ip;
6751         struct tcphdr *tcph;
6752         int ret = 0, i;
6753
6754         if (!(ret = check_L2_lro_capable(buffer, &ip, (struct tcphdr **)tcp,
6755                                          rxdp))) {
6756                 DBG_PRINT(INFO_DBG,"IP Saddr: %x Daddr: %x\n",
6757                           ip->saddr, ip->daddr);
6758         } else {
6759                 return ret;
6760         }
6761
6762         tcph = (struct tcphdr *)*tcp;
6763         *tcp_len = get_l4_pyld_length(ip, tcph);
6764         for (i=0; i<MAX_LRO_SESSIONS; i++) {
6765                 lro_t *l_lro = &sp->lro0_n[i];
6766                 if (l_lro->in_use) {
6767                         if (check_for_socket_match(l_lro, ip, tcph))
6768                                 continue;
6769                         /* Sock pair matched */
6770                         *lro = l_lro;
6771
6772                         if ((*lro)->tcp_next_seq != ntohl(tcph->seq)) {
6773                                 DBG_PRINT(INFO_DBG, "%s:Out of order. expected "
6774                                           "0x%x, actual 0x%x\n", __FUNCTION__,
6775                                           (*lro)->tcp_next_seq,
6776                                           ntohl(tcph->seq));
6777
6778                                 sp->mac_control.stats_info->
6779                                    sw_stat.outof_sequence_pkts++;
6780                                 ret = 2;
6781                                 break;
6782                         }
6783
6784                         if (!verify_l3_l4_lro_capable(l_lro, ip, tcph,*tcp_len))
6785                                 ret = 1; /* Aggregate */
6786                         else
6787                                 ret = 2; /* Flush both */
6788                         break;
6789                 }
6790         }
6791
6792         if (ret == 0) {
6793                 /* Before searching for available LRO objects,
6794                  * check if the pkt is L3/L4 aggregatable. If not
6795                  * don't create new LRO session. Just send this
6796                  * packet up.
6797                  */
6798                 if (verify_l3_l4_lro_capable(NULL, ip, tcph, *tcp_len)) {
6799                         return 5;
6800                 }
6801
6802                 for (i=0; i<MAX_LRO_SESSIONS; i++) {
6803                         lro_t *l_lro = &sp->lro0_n[i];
6804                         if (!(l_lro->in_use)) {
6805                                 *lro = l_lro;
6806                                 ret = 3; /* Begin anew */
6807                                 break;
6808                         }
6809                 }
6810         }
6811
6812         if (ret == 0) { /* sessions exceeded */
6813                 DBG_PRINT(INFO_DBG,"%s:All LRO sessions already in use\n",
6814                           __FUNCTION__);
6815                 *lro = NULL;
6816                 return ret;
6817         }
6818
6819         switch (ret) {
6820                 case 3:
6821                         initiate_new_session(*lro, buffer, ip, tcph, *tcp_len);
6822                         break;
6823                 case 2:
6824                         update_L3L4_header(sp, *lro);
6825                         break;
6826                 case 1:
6827                         aggregate_new_rx(*lro, ip, tcph, *tcp_len);
6828                         if ((*lro)->sg_num == sp->lro_max_aggr_per_sess) {
6829                                 update_L3L4_header(sp, *lro);
6830                                 ret = 4; /* Flush the LRO */
6831                         }
6832                         break;
6833                 default:
6834                         DBG_PRINT(ERR_DBG,"%s:Dont know, can't say!!\n",
6835                                 __FUNCTION__);
6836                         break;
6837         }
6838
6839         return ret;
6840 }
6841
6842 static void clear_lro_session(lro_t *lro)
6843 {
6844         static u16 lro_struct_size = sizeof(lro_t);
6845
6846         memset(lro, 0, lro_struct_size);
6847 }
6848
6849 static void queue_rx_frame(struct sk_buff *skb)
6850 {
6851         struct net_device *dev = skb->dev;
6852
6853         skb->protocol = eth_type_trans(skb, dev);
6854 #ifdef CONFIG_S2IO_NAPI
6855         netif_receive_skb(skb);
6856 #else
6857         netif_rx(skb);
6858 #endif
6859 }
6860
6861 static void lro_append_pkt(nic_t *sp, lro_t *lro, struct sk_buff *skb,
6862                            u32 tcp_len)
6863 {
6864         struct sk_buff *tmp, *first = lro->parent;
6865
6866         first->len += tcp_len;
6867         first->data_len = lro->frags_len;
6868         skb_pull(skb, (skb->len - tcp_len));
6869         if ((tmp = skb_shinfo(first)->frag_list)) {
6870                 while (tmp->next)
6871                         tmp = tmp->next;
6872                 tmp->next = skb;
6873         }
6874         else
6875                 skb_shinfo(first)->frag_list = skb;
6876         sp->mac_control.stats_info->sw_stat.clubbed_frms_cnt++;
6877         return;
6878 }