2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
28 * - coalescing setting?
32 * - variable ring size
38 #include <linux/config.h>
39 #include <linux/crc32.h>
40 #include <linux/kernel.h>
41 #include <linux/version.h>
42 #include <linux/module.h>
43 #include <linux/netdevice.h>
44 #include <linux/etherdevice.h>
45 #include <linux/ethtool.h>
46 #include <linux/pci.h>
48 #include <linux/tcp.h>
50 #include <linux/delay.h>
56 #define DRV_NAME "sky2"
57 #define DRV_VERSION "0.4"
58 #define PFX DRV_NAME " "
61 * The Yukon II chipset takes 64 bit command blocks (called list elements)
62 * that are organized into three (receive, transmit, status) different rings
63 * similar to Tigon3. A transmit can require several elements;
64 * a receive requires one (or two if using 64 bit dma).
67 #ifdef CONFIG_SKY2_EC_A1
68 #define is_ec_a1(hw) \
69 ((hw)->chip_id == CHIP_ID_YUKON_EC && \
70 (hw)->chip_rev == CHIP_REV_YU_EC_A1)
72 #define is_ec_a1(hw) 0
75 #define RX_LE_SIZE 256
76 #define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
77 #define RX_MAX_PENDING (RX_LE_SIZE/2 - 1)
78 #define RX_DEF_PENDING 128
79 #define RX_COPY_THRESHOLD 128
81 #define TX_RING_SIZE 512
82 #define TX_DEF_PENDING (TX_RING_SIZE - 1)
83 #define TX_MIN_PENDING 64
84 #define MAX_SKB_TX_LE (4 + 2*MAX_SKB_FRAGS)
86 #define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
87 #define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
88 #define ETH_JUMBO_MTU 9000
89 #define TX_WATCHDOG (5 * HZ)
90 #define NAPI_WEIGHT 64
91 #define PHY_RETRIES 1000
93 static const u32 default_msg =
94 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
95 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
96 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN | NETIF_MSG_INTR;
98 static int debug = -1; /* defaults above */
99 module_param(debug, int, 0);
100 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
102 static const struct pci_device_id sky2_id_table[] = {
103 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) },
104 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) },
105 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) },
106 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b01) },
107 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) },
108 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) },
109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) },
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) },
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) },
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) },
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) },
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) },
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) },
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) },
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) },
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) },
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) },
123 MODULE_DEVICE_TABLE(pci, sky2_id_table);
125 /* Avoid conditionals by using array */
126 static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
127 static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
129 static const char *yukon_name[] = {
130 [CHIP_ID_YUKON_LITE - CHIP_ID_YUKON] = "Lite", /* 0xb0 */
131 [CHIP_ID_YUKON_LP - CHIP_ID_YUKON] = "LP", /* 0xb2 */
132 [CHIP_ID_YUKON_XL - CHIP_ID_YUKON] = "XL", /* 0xb3 */
134 [CHIP_ID_YUKON_EC - CHIP_ID_YUKON] = "EC", /* 0xb6 */
135 [CHIP_ID_YUKON_FE - CHIP_ID_YUKON] = "FE", /* 0xb7 */
139 /* Access to external PHY */
140 static void gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
144 gma_write16(hw, port, GM_SMI_DATA, val);
145 gma_write16(hw, port, GM_SMI_CTRL,
146 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
148 for (i = 0; i < PHY_RETRIES; i++) {
149 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
153 printk(KERN_WARNING PFX "%s: phy write timeout\n", hw->dev[port]->name);
156 static u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
160 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
161 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
163 for (i = 0; i < PHY_RETRIES; i++) {
164 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL)
169 printk(KERN_WARNING PFX "%s: phy read timeout\n", hw->dev[port]->name);
171 return gma_read16(hw, port, GM_SMI_DATA);
174 static void sky2_phy_reset(struct sky2_hw *hw, unsigned port)
178 /* disable all GMAC IRQ's */
179 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
180 /* disable PHY IRQs */
181 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
183 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
184 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
185 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
186 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
188 reg = gma_read16(hw, port, GM_RX_CTRL);
189 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
190 gma_write16(hw, port, GM_RX_CTRL, reg);
193 static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
195 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
196 u16 ctrl, ct1000, adv, pg, ledctrl, ledover;
198 if (sky2->autoneg == AUTONEG_ENABLE && hw->chip_id != CHIP_ID_YUKON_XL) {
199 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
201 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
203 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
205 if (hw->chip_id == CHIP_ID_YUKON_EC)
206 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
208 ectrl |= PHY_M_EC_M_DSC(2) | PHY_M_EC_S_DSC(3);
210 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
213 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
215 if (hw->chip_id == CHIP_ID_YUKON_FE) {
216 /* enable automatic crossover */
217 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
219 /* disable energy detect */
220 ctrl &= ~PHY_M_PC_EN_DET_MSK;
222 /* enable automatic crossover */
223 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
225 if (sky2->autoneg == AUTONEG_ENABLE &&
226 hw->chip_id == CHIP_ID_YUKON_XL) {
227 ctrl &= ~PHY_M_PC_DSC_MSK;
228 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
231 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
233 /* workaround for deviation #4.88 (CRC errors) */
234 /* disable Automatic Crossover */
236 ctrl &= ~PHY_M_PC_MDIX_MSK;
237 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
239 if (hw->chip_id == CHIP_ID_YUKON_XL) {
240 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
241 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
242 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
243 ctrl &= ~PHY_M_MAC_MD_MSK;
244 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
245 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
247 /* select page 1 to access Fiber registers */
248 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
252 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
253 if (sky2->autoneg == AUTONEG_DISABLE)
258 ctrl |= PHY_CT_RESET;
259 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
265 if (sky2->autoneg == AUTONEG_ENABLE) {
267 if (sky2->advertising & ADVERTISED_1000baseT_Full)
268 ct1000 |= PHY_M_1000C_AFD;
269 if (sky2->advertising & ADVERTISED_1000baseT_Half)
270 ct1000 |= PHY_M_1000C_AHD;
271 if (sky2->advertising & ADVERTISED_100baseT_Full)
272 adv |= PHY_M_AN_100_FD;
273 if (sky2->advertising & ADVERTISED_100baseT_Half)
274 adv |= PHY_M_AN_100_HD;
275 if (sky2->advertising & ADVERTISED_10baseT_Full)
276 adv |= PHY_M_AN_10_FD;
277 if (sky2->advertising & ADVERTISED_10baseT_Half)
278 adv |= PHY_M_AN_10_HD;
279 } else /* special defines for FIBER (88E1011S only) */
280 adv |= PHY_M_AN_1000X_AHD | PHY_M_AN_1000X_AFD;
282 /* Set Flow-control capabilities */
283 if (sky2->tx_pause && sky2->rx_pause)
284 adv |= PHY_AN_PAUSE_CAP; /* symmetric */
285 else if (sky2->rx_pause && !sky2->tx_pause)
286 adv |= PHY_AN_PAUSE_ASYM | PHY_AN_PAUSE_CAP;
287 else if (!sky2->rx_pause && sky2->tx_pause)
288 adv |= PHY_AN_PAUSE_ASYM; /* local */
290 /* Restart Auto-negotiation */
291 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
293 /* forced speed/duplex settings */
294 ct1000 = PHY_M_1000C_MSE;
296 if (sky2->duplex == DUPLEX_FULL)
297 ctrl |= PHY_CT_DUP_MD;
299 switch (sky2->speed) {
301 ctrl |= PHY_CT_SP1000;
304 ctrl |= PHY_CT_SP100;
308 ctrl |= PHY_CT_RESET;
311 if (hw->chip_id != CHIP_ID_YUKON_FE)
312 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
314 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
315 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
317 /* Setup Phy LED's */
318 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
321 switch (hw->chip_id) {
322 case CHIP_ID_YUKON_FE:
323 /* on 88E3082 these bits are at 11..9 (shifted left) */
324 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
326 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
328 /* delete ACT LED control bits */
329 ctrl &= ~PHY_M_FELP_LED1_MSK;
330 /* change ACT LED control to blink mode */
331 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
332 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
335 case CHIP_ID_YUKON_XL:
336 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
338 /* select page 3 to access LED control register */
339 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
341 /* set LED Function Control register */
342 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
343 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
344 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
345 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
347 /* set Polarity Control register */
348 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
349 (PHY_M_POLC_LS1_P_MIX(4) |
350 PHY_M_POLC_IS0_P_MIX(4) |
351 PHY_M_POLC_LOS_CTRL(2) |
352 PHY_M_POLC_INIT_CTRL(2) |
353 PHY_M_POLC_STA1_CTRL(2) |
354 PHY_M_POLC_STA0_CTRL(2)));
356 /* restore page register */
357 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
361 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
362 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
363 /* turn off the Rx LED (LED_RX) */
364 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
367 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
369 if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
370 /* turn on 100 Mbps LED (LED_LINK100) */
371 ledover |= PHY_M_LED_MO_100(MO_LED_ON);
375 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
377 /* Enable phy interrupt on autonegotiation complete (or link up) */
378 if (sky2->autoneg == AUTONEG_ENABLE)
379 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
381 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
384 static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
386 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
389 const u8 *addr = hw->dev[port]->dev_addr;
391 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
392 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
394 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
396 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
397 /* WA DEV_472 -- looks like crossed wires on port 2 */
398 /* clear GMAC 1 Control reset */
399 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
401 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
402 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
403 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
404 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
405 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
408 if (sky2->autoneg == AUTONEG_DISABLE) {
409 reg = gma_read16(hw, port, GM_GP_CTRL);
410 reg |= GM_GPCR_AU_ALL_DIS;
411 gma_write16(hw, port, GM_GP_CTRL, reg);
412 gma_read16(hw, port, GM_GP_CTRL);
414 switch (sky2->speed) {
416 reg |= GM_GPCR_SPEED_1000;
419 reg |= GM_GPCR_SPEED_100;
422 if (sky2->duplex == DUPLEX_FULL)
423 reg |= GM_GPCR_DUP_FULL;
425 reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL;
427 if (!sky2->tx_pause && !sky2->rx_pause) {
428 sky2_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
430 GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
431 } else if (sky2->tx_pause && !sky2->rx_pause) {
432 /* disable Rx flow-control */
433 reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
436 gma_write16(hw, port, GM_GP_CTRL, reg);
438 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
440 spin_lock_bh(&hw->phy_lock);
441 sky2_phy_init(hw, port);
442 spin_unlock_bh(&hw->phy_lock);
445 reg = gma_read16(hw, port, GM_PHY_ADDR);
446 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
448 for (i = 0; i < GM_MIB_CNT_SIZE; i++)
449 gma_read16(hw, port, GM_MIB_CNT_BASE + 8 * i);
450 gma_write16(hw, port, GM_PHY_ADDR, reg);
452 /* transmit control */
453 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
455 /* receive control reg: unicast + multicast + no FCS */
456 gma_write16(hw, port, GM_RX_CTRL,
457 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
459 /* transmit flow control */
460 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
462 /* transmit parameter */
463 gma_write16(hw, port, GM_TX_PARAM,
464 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
465 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
466 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
467 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
469 /* serial mode register */
470 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
471 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
473 if (hw->dev[port]->mtu > 1500)
474 reg |= GM_SMOD_JUMBO_ENA;
476 gma_write16(hw, port, GM_SERIAL_MODE, reg);
478 /* virtual address for data */
479 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
481 /* physical address: used for pause frames */
482 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
484 /* ignore counter overflows */
485 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
486 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
487 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
489 /* Configure Rx MAC FIFO */
490 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
491 sky2_write16(hw, SK_REG(port, RX_GMF_CTRL_T),
492 GMF_OPER_ON | GMF_RX_F_FL_ON);
494 /* Flush Rx MAC FIFO on any flowcontrol or error */
495 reg = GMR_FS_ANY_ERR;
496 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev <= 1)
497 reg = 0; /* WA Dev #4115 */
499 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), reg);
500 /* Set threshold to 0xa (64 bytes)
501 * ASF disabled so no need to do WA dev #4.30
503 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF);
505 /* Configure Tx MAC FIFO */
506 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
507 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
510 static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, size_t len)
516 end = start + len - 1;
518 pr_debug("sky2_ramset start=%d end=%d\n", start, end);
520 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
521 sky2_write32(hw, RB_ADDR(q, RB_START), start);
522 sky2_write32(hw, RB_ADDR(q, RB_END), end);
523 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
524 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
526 if (q == Q_R1 || q == Q_R2) {
531 pr_debug(" utpp=%d ltpp=%d\n", rxup, rxlo);
533 /* Set thresholds on receive queue's */
534 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), rxup);
535 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), rxlo);
537 /* Enable store & forward on Tx queue's because
538 * Tx FIFO is only 1K on Yukon
540 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
543 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
544 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
547 /* Setup Bus Memory Interface */
548 static void sky2_qset(struct sky2_hw *hw, u16 q, u32 wm)
550 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
551 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
552 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
553 sky2_write32(hw, Q_ADDR(q, Q_WM), wm);
556 /* Setup prefetch unit registers. This is the interface between
557 * hardware and driver list elements
559 static inline void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
562 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
563 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
564 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32);
565 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr);
566 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
567 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
569 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
572 static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2)
574 struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod;
576 sky2->tx_prod = (sky2->tx_prod + 1) % TX_RING_SIZE;
581 * This is a workaround code taken from syskonnect sk98lin driver
582 * to deal with chip bug on Yukon EC rev 0 in the wraparound case.
584 static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q,
585 u16 idx, u16 *last, u16 size)
587 if (is_ec_a1(hw) && idx < *last) {
588 u16 hwget = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));
591 /* Start prefetching again */
592 sky2_write8(hw, Y2_QADDR(q, PREF_UNIT_FIFO_WM), 0xe0);
596 if (hwget == size - 1) {
597 /* set watermark to one list element */
598 sky2_write8(hw, Y2_QADDR(q, PREF_UNIT_FIFO_WM), 8);
600 /* set put index to first list element */
601 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), 0);
602 } else /* have hardware go to end of list */
603 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX),
607 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
609 *last = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX));
613 static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
615 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
616 sky2->rx_put = (sky2->rx_put + 1) % RX_LE_SIZE;
620 /* Build description to hardware about buffer */
621 static inline void sky2_rx_add(struct sky2_port *sky2, struct ring_info *re)
623 struct sky2_rx_le *le;
624 u32 hi = (re->mapaddr >> 16) >> 16;
626 re->idx = sky2->rx_put;
627 if (sky2->rx_addr64 != hi) {
628 le = sky2_next_rx(sky2);
629 le->addr = cpu_to_le32(hi);
631 le->opcode = OP_ADDR64 | HW_OWNER;
632 sky2->rx_addr64 = hi;
635 le = sky2_next_rx(sky2);
636 le->addr = cpu_to_le32((u32) re->mapaddr);
637 le->length = cpu_to_le16(re->maplen);
639 le->opcode = OP_PACKET | HW_OWNER;
642 /* Tell receiver about new buffers. */
643 static inline void rx_set_put(struct net_device *dev)
645 struct sky2_port *sky2 = netdev_priv(dev);
647 if (sky2->rx_last_put != sky2->rx_put)
648 sky2_put_idx(sky2->hw, rxqaddr[sky2->port], sky2->rx_put,
649 &sky2->rx_last_put, RX_LE_SIZE);
652 /* Tell chip where to start receive checksum.
653 * Actually has two checksums, but set both same to avoid possible byte
656 static void rx_set_checksum(struct sky2_port *sky2)
658 struct sky2_rx_le *le;
660 le = sky2_next_rx(sky2);
661 le->addr = (ETH_HLEN << 16) | ETH_HLEN;
663 le->opcode = OP_TCPSTART | HW_OWNER;
665 sky2_write16(sky2->hw, Y2_QADDR(rxqaddr[sky2->port],
666 PREF_UNIT_PUT_IDX), sky2->rx_put);
667 sky2_read16(sky2->hw, Y2_QADDR(rxqaddr[sky2->port], PREF_UNIT_PUT_IDX));
669 sky2_write32(sky2->hw,
670 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
671 sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
676 /* Cleanout receive buffer area, assumes receiver hardware stopped */
677 static void sky2_rx_clean(struct sky2_port *sky2)
681 memset(sky2->rx_le, 0, RX_LE_BYTES);
682 for (i = 0; i < sky2->rx_pending; i++) {
683 struct ring_info *re = sky2->rx_ring + i;
686 pci_unmap_single(sky2->hw->pdev,
687 re->mapaddr, re->maplen,
695 static inline struct sk_buff *sky2_rx_alloc(struct sky2_port *sky2,
697 unsigned int gfp_mask)
701 skb = alloc_skb(size + NET_IP_ALIGN, gfp_mask);
703 skb->dev = sky2->netdev;
704 skb_reserve(skb, NET_IP_ALIGN);
710 * Allocate and setup receiver buffer pool.
711 * In case of 64 bit dma, there are 2X as many list elements
712 * available as ring entries
713 * and need to reserve one list element so we don't wrap around.
715 static int sky2_rx_fill(struct sky2_port *sky2)
718 const unsigned rx_buf_size = sky2->netdev->mtu + ETH_HLEN + 8;
720 for (i = 0; i < sky2->rx_pending; i++) {
721 struct ring_info *re = sky2->rx_ring + i;
723 re->skb = sky2_rx_alloc(sky2, rx_buf_size, GFP_KERNEL);
727 re->mapaddr = pci_map_single(sky2->hw->pdev, re->skb->data,
728 rx_buf_size, PCI_DMA_FROMDEVICE);
729 re->maplen = rx_buf_size;
730 sky2_rx_add(sky2, re);
739 /* Bring up network interface. */
740 static int sky2_up(struct net_device *dev)
742 struct sky2_port *sky2 = netdev_priv(dev);
743 struct sky2_hw *hw = sky2->hw;
744 unsigned port = sky2->port;
745 u32 ramsize, rxspace;
748 if (netif_msg_ifup(sky2))
749 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
751 /* must be power of 2 */
752 sky2->tx_le = pci_alloc_consistent(hw->pdev,
754 sizeof(struct sky2_tx_le),
759 sky2->tx_ring = kmalloc(TX_RING_SIZE * sizeof(struct ring_info),
763 sky2->tx_prod = sky2->tx_cons = 0;
764 memset(sky2->tx_ring, 0, TX_RING_SIZE * sizeof(struct ring_info));
766 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
770 memset(sky2->rx_le, 0, RX_LE_BYTES);
772 sky2->rx_ring = kmalloc(sky2->rx_pending * sizeof(struct ring_info),
777 sky2_mac_init(hw, port);
779 /* Configure RAM buffers */
780 if (hw->chip_id == CHIP_ID_YUKON_FE ||
781 (hw->chip_id == CHIP_ID_YUKON_EC && hw->chip_rev == 2))
784 u8 e0 = sky2_read8(hw, B2_E_0);
785 ramsize = (e0 == 0) ? (128 * 1024) : (e0 * 4096);
789 rxspace = (2 * ramsize) / 3;
790 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
791 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
793 /* Make sure SyncQ is disabled */
794 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
797 sky2_qset(hw, rxqaddr[port], is_pciex(hw) ? 0x80 : 0x600);
798 sky2_qset(hw, txqaddr[port], 0x600);
800 sky2->rx_put = sky2->rx_next = 0;
801 sky2_prefetch_init(hw, rxqaddr[port], sky2->rx_le_map, RX_LE_SIZE - 1);
803 rx_set_checksum(sky2);
805 err = sky2_rx_fill(sky2);
809 /* Give buffers to receiver */
810 sky2_write16(sky2->hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_PUT_IDX),
812 sky2->rx_last_put = sky2_read16(sky2->hw,
813 Y2_QADDR(rxqaddr[port],
816 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
819 /* Enable interrupts from phy/mac for port */
820 hw->intr_mask |= (port == 0) ? Y2_IS_PORT_1 : Y2_IS_PORT_2;
821 sky2_write32(hw, B0_IMSK, hw->intr_mask);
826 pci_free_consistent(hw->pdev, RX_LE_BYTES,
827 sky2->rx_le, sky2->rx_le_map);
829 pci_free_consistent(hw->pdev,
830 TX_RING_SIZE * sizeof(struct sky2_tx_le),
831 sky2->tx_le, sky2->tx_le_map);
833 kfree(sky2->tx_ring);
835 kfree(sky2->rx_ring);
840 /* Modular subtraction in ring */
841 static inline int tx_dist(unsigned tail, unsigned head)
843 return (head >= tail ? head : head + TX_RING_SIZE) - tail;
846 /* Number of list elements available for next tx */
847 static inline int tx_avail(const struct sky2_port *sky2)
849 return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod);
852 /* Estimate of number of transmit list elements required */
853 static inline unsigned tx_le_req(const struct sk_buff *skb)
857 count = sizeof(dma_addr_t) / sizeof(u32);
858 count += skb_shinfo(skb)->nr_frags * count;
860 if (skb_shinfo(skb)->tso_size)
870 * Put one packet in ring for transmit.
871 * A single packet can generate multiple list elements, and
872 * the number of ring elements will probably be less than the number
873 * of list elements used.
875 static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
877 struct sky2_port *sky2 = netdev_priv(dev);
878 struct sky2_hw *hw = sky2->hw;
879 struct sky2_tx_le *le;
880 struct ring_info *re;
888 local_irq_save(flags);
889 if (!spin_trylock(&sky2->tx_lock)) {
890 local_irq_restore(flags);
891 return NETDEV_TX_LOCKED;
894 if (unlikely(tx_avail(sky2) < tx_le_req(skb))) {
895 netif_stop_queue(dev);
896 spin_unlock_irqrestore(&sky2->tx_lock, flags);
898 printk(KERN_WARNING PFX "%s: ring full when queue awake!\n",
900 return NETDEV_TX_BUSY;
903 if (unlikely(netif_msg_tx_queued(sky2)))
904 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
905 dev->name, sky2->tx_prod, skb->len);
907 len = skb_headlen(skb);
908 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
909 addr64 = (mapping >> 16) >> 16;
911 re = sky2->tx_ring + sky2->tx_prod;
913 /* Send high bits if changed */
914 if (addr64 != sky2->tx_addr64) {
915 le = get_tx_le(sky2);
916 le->tx.addr = cpu_to_le32(addr64);
918 le->opcode = OP_ADDR64 | HW_OWNER;
919 sky2->tx_addr64 = addr64;
922 /* Check for TCP Segmentation Offload */
923 mss = skb_shinfo(skb)->tso_size;
925 /* just drop the packet if non-linear expansion fails */
926 if (skb_header_cloned(skb) &&
927 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
928 dev_kfree_skb_any(skb);
932 mss += ((skb->h.th->doff - 5) * 4); /* TCP options */
933 mss += (skb->nh.iph->ihl * 4) + sizeof(struct tcphdr);
937 if (mss != sky2->tx_last_mss) {
938 le = get_tx_le(sky2);
939 le->tx.tso.size = cpu_to_le16(mss);
941 le->opcode = OP_LRGLEN | HW_OWNER;
943 sky2->tx_last_mss = mss;
946 /* Handle TCP checksum offload */
948 if (skb->ip_summed == CHECKSUM_HW) {
949 u16 hdr = skb->h.raw - skb->data;
950 u16 offset = hdr + skb->csum;
952 ctrl = CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
953 if (skb->nh.iph->protocol == IPPROTO_UDP)
956 le = get_tx_le(sky2);
957 le->tx.csum.start = cpu_to_le16(hdr);
958 le->tx.csum.offset = cpu_to_le16(offset);
959 le->length = 0; /* initial checksum value */
960 le->ctrl = 1; /* one packet */
961 le->opcode = OP_TCPLISW | HW_OWNER;
964 le = get_tx_le(sky2);
965 le->tx.addr = cpu_to_le32((u32) mapping);
966 le->length = cpu_to_le16(len);
968 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
970 /* Record the transmit mapping info */
972 re->mapaddr = mapping;
975 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
976 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
977 struct ring_info *fre;
979 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
980 frag->size, PCI_DMA_TODEVICE);
981 addr64 = (mapping >> 16) >> 16;
982 if (addr64 != sky2->tx_addr64) {
983 le = get_tx_le(sky2);
984 le->tx.addr = cpu_to_le32(addr64);
986 le->opcode = OP_ADDR64 | HW_OWNER;
987 sky2->tx_addr64 = addr64;
990 le = get_tx_le(sky2);
991 le->tx.addr = cpu_to_le32((u32) mapping);
992 le->length = cpu_to_le16(frag->size);
994 le->opcode = OP_BUFFER | HW_OWNER;
997 + ((re - sky2->tx_ring) + i + 1) % TX_RING_SIZE;
999 fre->mapaddr = mapping;
1000 fre->maplen = frag->size;
1002 re->idx = sky2->tx_prod;
1005 sky2_put_idx(sky2->hw, txqaddr[sky2->port], sky2->tx_prod,
1006 &sky2->tx_last_put, TX_RING_SIZE);
1008 if (tx_avail(sky2) < MAX_SKB_TX_LE + 1)
1009 netif_stop_queue(dev);
1013 spin_unlock_irqrestore(&sky2->tx_lock, flags);
1015 dev->trans_start = jiffies;
1016 return NETDEV_TX_OK;
1020 * Free ring elements from starting at tx_cons until "done"
1022 * NB: the hardware will tell us about partial completion of multi-part
1023 * buffers; these are defered until completion.
1025 static void sky2_tx_complete(struct net_device *dev, u16 done)
1027 struct sky2_port *sky2 = netdev_priv(dev);
1030 if (netif_msg_tx_done(sky2))
1031 printk(KERN_DEBUG "%s: tx done, upto %u\n", dev->name, done);
1033 spin_lock(&sky2->tx_lock);
1035 while (sky2->tx_cons != done) {
1036 struct ring_info *re = sky2->tx_ring + sky2->tx_cons;
1037 struct sk_buff *skb;
1039 /* Check for partial status */
1040 if (tx_dist(sky2->tx_cons, done)
1041 < tx_dist(sky2->tx_cons, re->idx))
1045 pci_unmap_single(sky2->hw->pdev,
1046 re->mapaddr, re->maplen, PCI_DMA_TODEVICE);
1048 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1049 struct ring_info *fre;
1051 sky2->tx_ring + (sky2->tx_cons + i +
1053 pci_unmap_page(sky2->hw->pdev, fre->mapaddr,
1054 fre->maplen, PCI_DMA_TODEVICE);
1057 dev_kfree_skb_any(skb);
1059 sky2->tx_cons = re->idx;
1063 if (netif_queue_stopped(dev) && tx_avail(sky2) > MAX_SKB_TX_LE)
1064 netif_wake_queue(dev);
1065 spin_unlock(&sky2->tx_lock);
1068 /* Cleanup all untransmitted buffers, assume transmitter not running */
1069 static inline void sky2_tx_clean(struct sky2_port *sky2)
1071 sky2_tx_complete(sky2->netdev, sky2->tx_prod);
1074 /* Network shutdown */
1075 static int sky2_down(struct net_device *dev)
1077 struct sky2_port *sky2 = netdev_priv(dev);
1078 struct sky2_hw *hw = sky2->hw;
1079 unsigned port = sky2->port;
1083 if (netif_msg_ifdown(sky2))
1084 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1086 netif_stop_queue(dev);
1088 sky2_phy_reset(hw, port);
1090 /* Stop transmitter */
1091 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1092 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1094 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
1095 RB_RST_SET | RB_DIS_OP_MD);
1097 ctrl = gma_read16(hw, port, GM_GP_CTRL);
1098 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
1099 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1101 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1103 /* Workaround shared GMAC reset */
1104 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
1105 && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
1106 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1108 /* Disable Force Sync bit and Enable Alloc bit */
1109 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1110 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1112 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1113 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1114 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1116 /* Reset the PCI FIFO of the async Tx queue */
1117 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1118 BMU_RST_SET | BMU_FIFO_RST);
1120 /* Reset the Tx prefetch units */
1121 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1124 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1127 * The RX Stop command will not work for Yukon-2 if the BMU does not
1128 * reach the end of packet and since we can't make sure that we have
1129 * incoming data, we must reset the BMU while it is not doing a DMA
1130 * transfer. Since it is possible that the RX path is still active,
1131 * the RX RAM buffer will be stopped first, so any possible incoming
1132 * data will not trigger a DMA. After the RAM buffer is stopped, the
1133 * BMU is polled until any DMA in progress is ended and only then it
1137 /* disable the RAM Buffer receive queue */
1138 sky2_write8(hw, RB_ADDR(rxqaddr[port], RB_CTRL), RB_DIS_OP_MD);
1140 for (i = 0; i < 0xffff; i++)
1141 if (sky2_read8(hw, RB_ADDR(rxqaddr[port], Q_RSL))
1142 == sky2_read8(hw, RB_ADDR(rxqaddr[port], Q_RL)))
1145 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR),
1146 BMU_RST_SET | BMU_FIFO_RST);
1147 /* reset the Rx prefetch unit */
1148 sky2_write32(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_CTRL),
1151 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1152 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1154 /* turn off led's */
1155 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
1157 sky2_tx_clean(sky2);
1158 sky2_rx_clean(sky2);
1160 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1161 sky2->rx_le, sky2->rx_le_map);
1162 kfree(sky2->rx_ring);
1164 pci_free_consistent(hw->pdev,
1165 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1166 sky2->tx_le, sky2->tx_le_map);
1167 kfree(sky2->tx_ring);
1172 static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1177 if (hw->chip_id == CHIP_ID_YUKON_FE)
1178 return (aux & PHY_M_PS_SPEED_100) ? SPEED_100 : SPEED_10;
1180 switch (aux & PHY_M_PS_SPEED_MSK) {
1181 case PHY_M_PS_SPEED_1000:
1183 case PHY_M_PS_SPEED_100:
1190 static void sky2_link_up(struct sky2_port *sky2)
1192 struct sky2_hw *hw = sky2->hw;
1193 unsigned port = sky2->port;
1196 /* disable Rx GMAC FIFO flush mode */
1197 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RX_F_FL_OFF);
1199 /* Enable Transmit FIFO Underrun */
1200 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
1202 reg = gma_read16(hw, port, GM_GP_CTRL);
1203 if (sky2->duplex == DUPLEX_FULL || sky2->autoneg == AUTONEG_ENABLE)
1204 reg |= GM_GPCR_DUP_FULL;
1207 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1208 gma_write16(hw, port, GM_GP_CTRL, reg);
1209 gma_read16(hw, port, GM_GP_CTRL);
1211 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1213 netif_carrier_on(sky2->netdev);
1214 netif_wake_queue(sky2->netdev);
1216 /* Turn on link LED */
1217 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
1218 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
1220 if (hw->chip_id == CHIP_ID_YUKON_XL) {
1221 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
1223 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
1224 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
1225 PHY_M_LEDC_INIT_CTRL(sky2->speed ==
1227 PHY_M_LEDC_STA1_CTRL(sky2->speed ==
1228 SPEED_100 ? 7 : 0) |
1229 PHY_M_LEDC_STA0_CTRL(sky2->speed ==
1230 SPEED_1000 ? 7 : 0));
1231 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
1234 if (netif_msg_link(sky2))
1235 printk(KERN_INFO PFX
1236 "%s: Link is up at %d Mbps, %s duplex, flowcontrol %s\n",
1237 sky2->netdev->name, sky2->speed,
1238 sky2->duplex == DUPLEX_FULL ? "full" : "half",
1239 (sky2->tx_pause && sky2->rx_pause) ? "both" :
1240 sky2->tx_pause ? "tx" : sky2->rx_pause ? "rx" : "none");
1243 static void sky2_link_down(struct sky2_port *sky2)
1245 struct sky2_hw *hw = sky2->hw;
1246 unsigned port = sky2->port;
1249 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1251 reg = gma_read16(hw, port, GM_GP_CTRL);
1252 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1253 gma_write16(hw, port, GM_GP_CTRL, reg);
1254 gma_read16(hw, port, GM_GP_CTRL); /* PCI post */
1256 if (sky2->rx_pause && !sky2->tx_pause) {
1257 /* restore Asymmetric Pause bit */
1258 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,
1259 gm_phy_read(hw, port, PHY_MARV_AUNE_ADV)
1263 sky2_phy_reset(hw, port);
1265 netif_carrier_off(sky2->netdev);
1266 netif_stop_queue(sky2->netdev);
1268 /* Turn on link LED */
1269 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
1271 if (netif_msg_link(sky2))
1272 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
1273 sky2_phy_init(hw, port);
1276 static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
1278 struct sky2_hw *hw = sky2->hw;
1279 unsigned port = sky2->port;
1282 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
1284 if (lpa & PHY_M_AN_RF) {
1285 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
1289 if (hw->chip_id != CHIP_ID_YUKON_FE &&
1290 gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) {
1291 printk(KERN_ERR PFX "%s: master/slave fault",
1292 sky2->netdev->name);
1296 if (!(aux & PHY_M_PS_SPDUP_RES)) {
1297 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
1298 sky2->netdev->name);
1302 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1304 sky2->speed = sky2_phy_speed(hw, aux);
1306 /* Pause bits are offset (9..8) */
1307 if (hw->chip_id == CHIP_ID_YUKON_XL)
1310 sky2->rx_pause = (aux & PHY_M_PS_RX_P_EN) != 0;
1311 sky2->tx_pause = (aux & PHY_M_PS_TX_P_EN) != 0;
1313 if ((sky2->tx_pause || sky2->rx_pause)
1314 && !(sky2->speed < SPEED_1000 && sky2->duplex == DUPLEX_HALF))
1315 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
1317 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1323 * Interrrupt from PHY are handled in tasklet (soft irq)
1324 * because accessing phy registers requires spin wait which might
1325 * cause excess interrupt latency.
1327 static void sky2_phy_task(unsigned long data)
1329 struct sky2_port *sky2 = (struct sky2_port *)data;
1330 struct sky2_hw *hw = sky2->hw;
1331 u16 istatus, phystat;
1333 spin_lock(&hw->phy_lock);
1334 istatus = gm_phy_read(hw, sky2->port, PHY_MARV_INT_STAT);
1335 phystat = gm_phy_read(hw, sky2->port, PHY_MARV_PHY_STAT);
1337 if (netif_msg_intr(sky2))
1338 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
1339 sky2->netdev->name, istatus, phystat);
1341 if (istatus & PHY_M_IS_AN_COMPL) {
1342 if (sky2_autoneg_done(sky2, phystat) == 0)
1347 if (istatus & PHY_M_IS_LSP_CHANGE)
1348 sky2->speed = sky2_phy_speed(hw, phystat);
1350 if (istatus & PHY_M_IS_DUP_CHANGE)
1352 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1354 if (istatus & PHY_M_IS_LST_CHANGE) {
1355 if (phystat & PHY_M_PS_LINK_UP)
1358 sky2_link_down(sky2);
1361 spin_unlock(&hw->phy_lock);
1363 local_irq_disable();
1364 hw->intr_mask |= (sky2->port == 0) ? Y2_IS_IRQ_PHY1 : Y2_IS_IRQ_PHY2;
1365 sky2_write32(hw, B0_IMSK, hw->intr_mask);
1369 static void sky2_tx_timeout(struct net_device *dev)
1371 struct sky2_port *sky2 = netdev_priv(dev);
1373 if (netif_msg_timer(sky2))
1374 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
1376 sky2_write32(sky2->hw, Q_ADDR(txqaddr[sky2->port], Q_CSR), BMU_STOP);
1377 sky2_read32(sky2->hw, Q_ADDR(txqaddr[sky2->port], Q_CSR));
1379 sky2_tx_clean(sky2);
1382 static int sky2_change_mtu(struct net_device *dev, int new_mtu)
1386 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
1389 if (netif_running(dev))
1394 if (netif_running(dev))
1401 * Receive one packet.
1402 * For small packets or errors, just reuse existing skb.
1403 * For larger pakects, get new buffer.
1405 static struct sk_buff *sky2_receive(struct sky2_hw *hw, unsigned port,
1406 u16 length, u32 status)
1408 struct net_device *dev = hw->dev[port];
1409 struct sky2_port *sky2 = netdev_priv(dev);
1410 struct ring_info *re = sky2->rx_ring + sky2->rx_next;
1411 struct sk_buff *skb, *nskb;
1412 const unsigned int rx_buf_size = dev->mtu + ETH_HLEN + 8;
1414 if (unlikely(netif_msg_rx_status(sky2)))
1415 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
1416 dev->name, sky2->rx_next, status, length);
1418 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
1421 if (!(status & GMR_FS_RX_OK)
1422 || (status & GMR_FS_ANY_ERR)
1423 || (length << 16) != (status & GMR_FS_LEN)
1424 || length > rx_buf_size)
1427 if (length < RX_COPY_THRESHOLD) {
1428 nskb = sky2_rx_alloc(sky2, length, GFP_ATOMIC);
1432 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->mapaddr,
1433 length, PCI_DMA_FROMDEVICE);
1434 memcpy(nskb->data, re->skb->data, length);
1435 pci_dma_sync_single_for_device(sky2->hw->pdev, re->mapaddr,
1436 length, PCI_DMA_FROMDEVICE);
1439 nskb = sky2_rx_alloc(sky2, rx_buf_size, GFP_ATOMIC);
1444 pci_unmap_single(sky2->hw->pdev, re->mapaddr,
1445 re->maplen, PCI_DMA_FROMDEVICE);
1446 prefetch(skb->data);
1449 re->mapaddr = pci_map_single(sky2->hw->pdev, nskb->data,
1450 rx_buf_size, PCI_DMA_FROMDEVICE);
1451 re->maplen = rx_buf_size;
1455 BUG_ON(re->skb == skb);
1456 sky2_rx_add(sky2, re);
1460 if (status & GMR_FS_GOOD_FC)
1463 if (netif_msg_rx_err(sky2))
1464 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
1465 sky2->netdev->name, status, length);
1467 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
1468 sky2->net_stats.rx_length_errors++;
1469 if (status & GMR_FS_FRAGMENT)
1470 sky2->net_stats.rx_frame_errors++;
1471 if (status & GMR_FS_CRC_ERR)
1472 sky2->net_stats.rx_crc_errors++;
1473 if (status & GMR_FS_RX_FF_OV)
1474 sky2->net_stats.rx_fifo_errors++;
1478 /* Transmit ring index in reported status block is encoded as:
1480 * | TXS2 | TXA2 | TXS1 | TXA1
1482 static inline u16 tx_index(u8 port, u32 status, u16 len)
1485 return status & 0xfff;
1487 return ((status >> 24) & 0xff) | (len & 0xf) << 8;
1491 * Both ports share the same status interrupt, therefore there is only
1494 static int sky2_poll(struct net_device *dev, int *budget)
1496 struct sky2_port *sky2 = netdev_priv(dev);
1497 struct sky2_hw *hw = sky2->hw;
1498 unsigned int to_do = min(dev->quota, *budget);
1499 unsigned int work_done = 0;
1501 unsigned char summed[2] = { CHECKSUM_NONE, CHECKSUM_NONE };
1502 unsigned int csum[2];
1504 hwidx = sky2_read16(hw, STAT_PUT_IDX);
1506 while (hw->st_idx != hwidx && work_done < to_do) {
1507 struct sky2_status_le *le = hw->st_le + hw->st_idx;
1508 struct sk_buff *skb;
1513 status = le32_to_cpu(le->status);
1514 length = le16_to_cpu(le->length);
1517 BUG_ON(port >= hw->ports || hw->dev[port] == NULL);
1519 switch (le->opcode & ~HW_OWNER) {
1521 skb = sky2_receive(hw, port, length, status);
1523 __skb_put(skb, length);
1524 skb->protocol = eth_type_trans(skb, dev);
1526 /* Add hw checksum if available */
1527 skb->ip_summed = summed[port];
1528 skb->csum = csum[port];
1530 /* Clear for next packet */
1532 summed[port] = CHECKSUM_NONE;
1534 netif_receive_skb(skb);
1536 dev->last_rx = jiffies;
1542 /* Save computed checksum for next rx */
1543 csum[port] = le16_to_cpu(status & 0xffff);
1544 summed[port] = CHECKSUM_HW;
1548 sky2_tx_complete(hw->dev[port],
1549 tx_index(port, status, length));
1552 case OP_RXTIMESTAMP:
1556 if (net_ratelimit())
1557 printk(KERN_WARNING PFX
1558 "unknown status opcode 0x%x\n",
1563 hw->st_idx = (hw->st_idx + 1) % STATUS_RING_SIZE;
1564 if (hw->st_idx == hwidx) {
1565 hwidx = sky2_read16(hw, STAT_PUT_IDX);
1573 rx_set_put(hw->dev[0]);
1576 rx_set_put(hw->dev[1]);
1578 *budget -= work_done;
1579 dev->quota -= work_done;
1580 if (work_done < to_do) {
1582 * Another chip workaround, need to restart TX timer if status
1583 * LE was handled. WA_DEV_43_418
1586 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
1587 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
1590 hw->intr_mask |= Y2_IS_STAT_BMU;
1591 sky2_write32(hw, B0_IMSK, hw->intr_mask);
1592 sky2_read32(hw, B0_IMSK);
1593 netif_rx_complete(dev);
1596 return work_done >= to_do;
1600 static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
1602 struct net_device *dev = hw->dev[port];
1604 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
1607 if (status & Y2_IS_PAR_RD1) {
1608 printk(KERN_ERR PFX "%s: ram data read parity error\n",
1611 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
1614 if (status & Y2_IS_PAR_WR1) {
1615 printk(KERN_ERR PFX "%s: ram data write parity error\n",
1618 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
1621 if (status & Y2_IS_PAR_MAC1) {
1622 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
1623 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
1626 if (status & Y2_IS_PAR_RX1) {
1627 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
1628 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
1631 if (status & Y2_IS_TCP_TXA1) {
1632 printk(KERN_ERR PFX "%s: TCP segmentation error\n", dev->name);
1633 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
1637 static void sky2_hw_intr(struct sky2_hw *hw)
1639 u32 status = sky2_read32(hw, B0_HWE_ISRC);
1641 if (status & Y2_IS_TIST_OV)
1642 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
1644 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
1647 pci_read_config_word(hw->pdev, PCI_STATUS, &pci_err);
1648 printk(KERN_ERR PFX "%s: pci hw error (0x%x)\n",
1649 pci_name(hw->pdev), pci_err);
1651 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
1652 pci_write_config_word(hw->pdev, PCI_STATUS,
1653 pci_err | PCI_STATUS_ERROR_BITS);
1654 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
1657 if (status & Y2_IS_PCI_EXP) {
1658 /* PCI-Express uncorrectable Error occured */
1661 pci_read_config_dword(hw->pdev, PEX_UNC_ERR_STAT, &pex_err);
1663 printk(KERN_ERR PFX "%s: pci express error (0x%x)\n",
1664 pci_name(hw->pdev), pex_err);
1666 /* clear the interrupt */
1667 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
1668 pci_write_config_dword(hw->pdev, PEX_UNC_ERR_STAT,
1670 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
1672 if (pex_err & PEX_FATAL_ERRORS) {
1673 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
1674 hwmsk &= ~Y2_IS_PCI_EXP;
1675 sky2_write32(hw, B0_HWE_IMSK, hwmsk);
1679 if (status & Y2_HWE_L1_MASK)
1680 sky2_hw_error(hw, 0, status);
1682 if (status & Y2_HWE_L1_MASK)
1683 sky2_hw_error(hw, 1, status);
1686 static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
1688 struct net_device *dev = hw->dev[port];
1689 struct sky2_port *sky2 = netdev_priv(dev);
1690 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
1692 if (netif_msg_intr(sky2))
1693 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
1696 if (status & GM_IS_RX_FF_OR) {
1697 ++sky2->net_stats.rx_fifo_errors;
1698 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
1701 if (status & GM_IS_TX_FF_UR) {
1702 ++sky2->net_stats.tx_fifo_errors;
1703 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
1707 static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
1709 struct net_device *dev = hw->dev[port];
1710 struct sky2_port *sky2 = netdev_priv(dev);
1712 hw->intr_mask &= ~(port == 0 ? Y2_IS_IRQ_PHY1 : Y2_IS_IRQ_PHY2);
1713 sky2_write32(hw, B0_IMSK, hw->intr_mask);
1714 tasklet_schedule(&sky2->phy_task);
1717 static irqreturn_t sky2_intr(int irq, void *dev_id, struct pt_regs *regs)
1719 struct sky2_hw *hw = dev_id;
1722 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
1723 if (status == 0 || status == ~0)
1726 if (status & Y2_IS_HW_ERR)
1729 /* Do NAPI for Rx and Tx status */
1730 if ((status & Y2_IS_STAT_BMU) && netif_rx_schedule_test(hw->dev[0])) {
1731 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
1733 hw->intr_mask &= ~Y2_IS_STAT_BMU;
1734 sky2_write32(hw, B0_IMSK, hw->intr_mask);
1735 __netif_rx_schedule(hw->dev[0]);
1738 if (status & Y2_IS_IRQ_PHY1)
1739 sky2_phy_intr(hw, 0);
1741 if (status & Y2_IS_IRQ_PHY2)
1742 sky2_phy_intr(hw, 1);
1744 if (status & Y2_IS_IRQ_MAC1)
1745 sky2_mac_intr(hw, 0);
1747 if (status & Y2_IS_IRQ_MAC2)
1748 sky2_mac_intr(hw, 1);
1750 sky2_write32(hw, B0_Y2_SP_ICR, 2);
1752 sky2_read32(hw, B0_IMSK);
1757 #ifdef CONFIG_NET_POLL_CONTROLLER
1758 static void sky2_netpoll(struct net_device *dev)
1760 struct sky2_port *sky2 = netdev_priv(dev);
1762 sky2_intr(sky2->hw->pdev->irq, sky2->hw, NULL);
1766 /* Chip internal frequency for clock calculations */
1767 static inline u32 sky2_khz(const struct sky2_hw *hw)
1769 switch (hw->chip_id) {
1770 case CHIP_ID_YUKON_EC:
1771 return 125000; /* 125 Mhz */
1772 case CHIP_ID_YUKON_FE:
1773 return 100000; /* 100 Mhz */
1774 default: /* YUKON_XL */
1775 return 156000; /* 156 Mhz */
1779 static inline u32 sky2_ms2clk(const struct sky2_hw *hw, u32 ms)
1781 return sky2_khz(hw) * ms;
1784 static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
1786 return (sky2_khz(hw) * us) / 1000;
1789 static int sky2_reset(struct sky2_hw *hw)
1796 ctst = sky2_read32(hw, B0_CTST);
1798 sky2_write8(hw, B0_CTST, CS_RST_CLR);
1799 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
1800 if (hw->chip_id < CHIP_ID_YUKON_XL || hw->chip_id > CHIP_ID_YUKON_FE) {
1801 printk(KERN_ERR PFX "%s: unsupported chip type 0x%x\n",
1802 pci_name(hw->pdev), hw->chip_id);
1806 /* ring for status responses */
1807 hw->st_le = pci_alloc_consistent(hw->pdev, STATUS_LE_BYTES,
1813 if (hw->chip_id <= CHIP_ID_YUKON_EC) {
1814 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
1815 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
1819 sky2_write8(hw, B0_CTST, CS_RST_SET);
1820 sky2_write8(hw, B0_CTST, CS_RST_CLR);
1822 /* clear PCI errors, if any */
1823 pci_read_config_word(hw->pdev, PCI_STATUS, &status);
1824 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
1825 pci_write_config_word(hw->pdev, PCI_STATUS,
1826 status | PCI_STATUS_ERROR_BITS);
1828 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
1830 /* clear any PEX errors */
1833 pci_write_config_dword(hw->pdev, PEX_UNC_ERR_STAT,
1835 pci_read_config_word(hw->pdev, PEX_LNK_STAT, &lstat);
1838 pmd_type = sky2_read8(hw, B2_PMD_TYP);
1839 hw->copper = !(pmd_type == 'L' || pmd_type == 'S');
1842 t8 = sky2_read8(hw, B2_Y2_HW_RES);
1843 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
1844 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
1847 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
1849 /* switch power to VCC (WA for VAUX problem) */
1850 sky2_write8(hw, B0_POWER_CTRL,
1851 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
1853 /* disable Core Clock Division, */
1854 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
1856 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
1857 /* enable bits are inverted */
1858 sky2_write8(hw, B2_Y2_CLK_GATE,
1859 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
1860 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
1861 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
1863 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
1865 /* Turn off phy power saving */
1866 pci_read_config_dword(hw->pdev, PCI_DEV_REG1, &power);
1867 power &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
1869 /* looks like this xl is back asswards .. */
1870 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1) {
1871 power |= PCI_Y2_PHY1_COMA;
1873 power |= PCI_Y2_PHY2_COMA;
1875 pci_write_config_dword(hw->pdev, PCI_DEV_REG1, power);
1877 for (i = 0; i < hw->ports; i++) {
1878 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
1879 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
1882 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
1884 /* Clear I2C IRQ noise */
1885 sky2_write32(hw, B2_I2C_IRQ, 1);
1887 /* turn off hardware timer (unused) */
1888 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
1889 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
1891 sky2_write8(hw, B0_Y2LED, LED_STAT_ON);
1893 /* Turn on descriptor polling (every 75us) */
1894 sky2_write32(hw, B28_DPT_INI, sky2_us2clk(hw, 75));
1895 sky2_write8(hw, B28_DPT_CTRL, DPT_START);
1897 /* Turn off receive timestamp */
1898 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
1899 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
1901 /* enable the Tx Arbiters */
1902 for (i = 0; i < hw->ports; i++)
1903 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
1905 /* Initialize ram interface */
1906 for (i = 0; i < hw->ports; i++) {
1907 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
1909 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
1910 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
1911 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
1912 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
1913 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
1914 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
1915 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
1916 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
1917 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
1918 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
1919 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
1920 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
1926 /* change Max. Read Request Size to 2048 bytes */
1927 pci_read_config_word(hw->pdev, PEX_DEV_CTRL, &pctrl);
1928 pctrl &= ~PEX_DC_MAX_RRS_MSK;
1929 pctrl |= PEX_DC_MAX_RD_RQ_SIZE(4);
1932 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
1933 pci_write_config_word(hw->pdev, PEX_DEV_CTRL, pctrl);
1934 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
1937 sky2_write32(hw, B0_HWE_IMSK, Y2_HWE_ALL_MASK);
1939 spin_lock_bh(&hw->phy_lock);
1940 for (i = 0; i < hw->ports; i++)
1941 sky2_phy_reset(hw, i);
1942 spin_unlock_bh(&hw->phy_lock);
1944 memset(hw->st_le, 0, STATUS_LE_BYTES);
1947 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
1948 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
1950 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
1951 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
1953 /* Set the list last index */
1954 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
1956 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_ms2clk(hw, 10));
1958 /* These status setup values are copied from SysKonnect's driver */
1960 /* WA for dev. #4.3 */
1961 sky2_write16(hw, STAT_TX_IDX_TH, 0xfff); /* Tx Threshold */
1963 /* set Status-FIFO watermark */
1964 sky2_write8(hw, STAT_FIFO_WM, 0x21); /* WA for dev. #4.18 */
1966 /* set Status-FIFO ISR watermark */
1967 sky2_write8(hw, STAT_FIFO_ISR_WM, 0x07); /* WA for dev. #4.18 */
1970 sky2_write16(hw, STAT_TX_IDX_TH, 0x000a);
1972 /* set Status-FIFO watermark */
1973 sky2_write8(hw, STAT_FIFO_WM, 0x10);
1975 /* set Status-FIFO ISR watermark */
1976 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
1977 sky2_write8(hw, STAT_FIFO_ISR_WM, 0x10);
1980 sky2_write8(hw, STAT_FIFO_ISR_WM, 0x04);
1982 sky2_write32(hw, STAT_ISR_TIMER_INI, 0x0190);
1985 /* enable status unit */
1986 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
1988 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
1989 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
1990 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
1995 static inline u32 sky2_supported_modes(const struct sky2_hw *hw)
1999 modes = SUPPORTED_10baseT_Half
2000 | SUPPORTED_10baseT_Full
2001 | SUPPORTED_100baseT_Half
2002 | SUPPORTED_100baseT_Full
2003 | SUPPORTED_Autoneg | SUPPORTED_TP;
2005 if (hw->chip_id != CHIP_ID_YUKON_FE)
2006 modes |= SUPPORTED_1000baseT_Half
2007 | SUPPORTED_1000baseT_Full;
2009 modes = SUPPORTED_1000baseT_Full | SUPPORTED_FIBRE
2010 | SUPPORTED_Autoneg;
2014 static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2016 struct sky2_port *sky2 = netdev_priv(dev);
2017 struct sky2_hw *hw = sky2->hw;
2019 ecmd->transceiver = XCVR_INTERNAL;
2020 ecmd->supported = sky2_supported_modes(hw);
2021 ecmd->phy_address = PHY_ADDR_MARV;
2023 ecmd->supported = SUPPORTED_10baseT_Half
2024 | SUPPORTED_10baseT_Full
2025 | SUPPORTED_100baseT_Half
2026 | SUPPORTED_100baseT_Full
2027 | SUPPORTED_1000baseT_Half
2028 | SUPPORTED_1000baseT_Full
2029 | SUPPORTED_Autoneg | SUPPORTED_TP;
2030 ecmd->port = PORT_TP;
2032 ecmd->port = PORT_FIBRE;
2034 ecmd->advertising = sky2->advertising;
2035 ecmd->autoneg = sky2->autoneg;
2036 ecmd->speed = sky2->speed;
2037 ecmd->duplex = sky2->duplex;
2041 static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2043 struct sky2_port *sky2 = netdev_priv(dev);
2044 const struct sky2_hw *hw = sky2->hw;
2045 u32 supported = sky2_supported_modes(hw);
2047 if (ecmd->autoneg == AUTONEG_ENABLE) {
2048 ecmd->advertising = supported;
2054 switch (ecmd->speed) {
2056 if (ecmd->duplex == DUPLEX_FULL)
2057 setting = SUPPORTED_1000baseT_Full;
2058 else if (ecmd->duplex == DUPLEX_HALF)
2059 setting = SUPPORTED_1000baseT_Half;
2064 if (ecmd->duplex == DUPLEX_FULL)
2065 setting = SUPPORTED_100baseT_Full;
2066 else if (ecmd->duplex == DUPLEX_HALF)
2067 setting = SUPPORTED_100baseT_Half;
2073 if (ecmd->duplex == DUPLEX_FULL)
2074 setting = SUPPORTED_10baseT_Full;
2075 else if (ecmd->duplex == DUPLEX_HALF)
2076 setting = SUPPORTED_10baseT_Half;
2084 if ((setting & supported) == 0)
2087 sky2->speed = ecmd->speed;
2088 sky2->duplex = ecmd->duplex;
2091 sky2->autoneg = ecmd->autoneg;
2092 sky2->advertising = ecmd->advertising;
2094 if (netif_running(dev)) {
2102 static void sky2_get_drvinfo(struct net_device *dev,
2103 struct ethtool_drvinfo *info)
2105 struct sky2_port *sky2 = netdev_priv(dev);
2107 strcpy(info->driver, DRV_NAME);
2108 strcpy(info->version, DRV_VERSION);
2109 strcpy(info->fw_version, "N/A");
2110 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
2113 static const struct sky2_stat {
2114 char name[ETH_GSTRING_LEN];
2117 { "tx_bytes", GM_TXO_OK_HI },
2118 { "rx_bytes", GM_RXO_OK_HI },
2119 { "tx_broadcast", GM_TXF_BC_OK },
2120 { "rx_broadcast", GM_RXF_BC_OK },
2121 { "tx_multicast", GM_TXF_MC_OK },
2122 { "rx_multicast", GM_RXF_MC_OK },
2123 { "tx_unicast", GM_TXF_UC_OK },
2124 { "rx_unicast", GM_RXF_UC_OK },
2125 { "tx_mac_pause", GM_TXF_MPAUSE },
2126 { "rx_mac_pause", GM_RXF_MPAUSE },
2127 { "collisions", GM_TXF_SNG_COL },
2128 { "late_collision",GM_TXF_LAT_COL },
2129 { "aborted", GM_TXF_ABO_COL },
2130 { "multi_collisions", GM_TXF_MUL_COL },
2131 { "fifo_underrun", GM_TXE_FIFO_UR },
2132 { "fifo_overflow", GM_RXE_FIFO_OV },
2133 { "rx_toolong", GM_RXF_LNG_ERR },
2134 { "rx_jabber", GM_RXF_JAB_PKT },
2135 { "rx_runt", GM_RXE_FRAG },
2136 { "rx_too_long", GM_RXF_LNG_ERR },
2137 { "rx_fcs_error", GM_RXF_FCS_ERR },
2140 static u32 sky2_get_rx_csum(struct net_device *dev)
2142 struct sky2_port *sky2 = netdev_priv(dev);
2144 return sky2->rx_csum;
2147 static int sky2_set_rx_csum(struct net_device *dev, u32 data)
2149 struct sky2_port *sky2 = netdev_priv(dev);
2151 sky2->rx_csum = data;
2153 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
2154 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
2159 static u32 sky2_get_msglevel(struct net_device *netdev)
2161 struct sky2_port *sky2 = netdev_priv(netdev);
2162 return sky2->msg_enable;
2165 static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
2167 struct sky2_hw *hw = sky2->hw;
2168 unsigned port = sky2->port;
2171 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
2172 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
2173 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
2174 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
2176 for (i = 2; i < count; i++)
2177 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
2180 static void sky2_set_msglevel(struct net_device *netdev, u32 value)
2182 struct sky2_port *sky2 = netdev_priv(netdev);
2183 sky2->msg_enable = value;
2186 static int sky2_get_stats_count(struct net_device *dev)
2188 return ARRAY_SIZE(sky2_stats);
2191 static void sky2_get_ethtool_stats(struct net_device *dev,
2192 struct ethtool_stats *stats, u64 * data)
2194 struct sky2_port *sky2 = netdev_priv(dev);
2196 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
2199 static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
2203 switch (stringset) {
2205 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
2206 memcpy(data + i * ETH_GSTRING_LEN,
2207 sky2_stats[i].name, ETH_GSTRING_LEN);
2212 /* Use hardware MIB variables for critical path statistics and
2213 * transmit feedback not reported at interrupt.
2214 * Other errors are accounted for in interrupt handler.
2216 static struct net_device_stats *sky2_get_stats(struct net_device *dev)
2218 struct sky2_port *sky2 = netdev_priv(dev);
2221 sky2_phy_stats(sky2, data, ARRAY_SIZE(data));
2223 sky2->net_stats.tx_bytes = data[0];
2224 sky2->net_stats.rx_bytes = data[1];
2225 sky2->net_stats.tx_packets = data[2] + data[4] + data[6];
2226 sky2->net_stats.rx_packets = data[3] + data[5] + data[7];
2227 sky2->net_stats.multicast = data[5] + data[7];
2228 sky2->net_stats.collisions = data[10];
2229 sky2->net_stats.tx_aborted_errors = data[12];
2231 return &sky2->net_stats;
2234 static int sky2_set_mac_address(struct net_device *dev, void *p)
2236 struct sky2_port *sky2 = netdev_priv(dev);
2237 struct sockaddr *addr = p;
2240 if (!is_valid_ether_addr(addr->sa_data))
2241 return -EADDRNOTAVAIL;
2244 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
2245 memcpy_toio(sky2->hw->regs + B2_MAC_1 + sky2->port * 8,
2246 dev->dev_addr, ETH_ALEN);
2247 memcpy_toio(sky2->hw->regs + B2_MAC_2 + sky2->port * 8,
2248 dev->dev_addr, ETH_ALEN);
2249 if (dev->flags & IFF_UP)
2254 static void sky2_set_multicast(struct net_device *dev)
2256 struct sky2_port *sky2 = netdev_priv(dev);
2257 struct sky2_hw *hw = sky2->hw;
2258 unsigned port = sky2->port;
2259 struct dev_mc_list *list = dev->mc_list;
2263 memset(filter, 0, sizeof(filter));
2265 reg = gma_read16(hw, port, GM_RX_CTRL);
2266 reg |= GM_RXCR_UCF_ENA;
2268 if (dev->flags & IFF_PROMISC) /* promiscious */
2269 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
2270 else if ((dev->flags & IFF_ALLMULTI) || dev->mc_count > 16) /* all multicast */
2271 memset(filter, 0xff, sizeof(filter));
2272 else if (dev->mc_count == 0) /* no multicast */
2273 reg &= ~GM_RXCR_MCF_ENA;
2276 reg |= GM_RXCR_MCF_ENA;
2278 for (i = 0; list && i < dev->mc_count; i++, list = list->next) {
2279 u32 bit = ether_crc(ETH_ALEN, list->dmi_addr) & 0x3f;
2280 filter[bit / 8] |= 1 << (bit % 8);
2284 gma_write16(hw, port, GM_MC_ADDR_H1,
2285 (u16) filter[0] | ((u16) filter[1] << 8));
2286 gma_write16(hw, port, GM_MC_ADDR_H2,
2287 (u16) filter[2] | ((u16) filter[3] << 8));
2288 gma_write16(hw, port, GM_MC_ADDR_H3,
2289 (u16) filter[4] | ((u16) filter[5] << 8));
2290 gma_write16(hw, port, GM_MC_ADDR_H4,
2291 (u16) filter[6] | ((u16) filter[7] << 8));
2293 gma_write16(hw, port, GM_RX_CTRL, reg);
2296 /* Can have one global because blinking is controlled by
2297 * ethtool and that is always under RTNL mutex
2299 static inline void sky2_led(struct sky2_hw *hw, unsigned port, int on)
2303 spin_lock_bh(&hw->phy_lock);
2304 switch (hw->chip_id) {
2305 case CHIP_ID_YUKON_XL:
2306 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2307 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2308 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
2309 on ? (PHY_M_LEDC_LOS_CTRL(1) |
2310 PHY_M_LEDC_INIT_CTRL(7) |
2311 PHY_M_LEDC_STA1_CTRL(7) |
2312 PHY_M_LEDC_STA0_CTRL(7))
2315 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2319 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
2320 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
2321 on ? PHY_M_LED_MO_DUP(MO_LED_ON) |
2322 PHY_M_LED_MO_10(MO_LED_ON) |
2323 PHY_M_LED_MO_100(MO_LED_ON) |
2324 PHY_M_LED_MO_1000(MO_LED_ON) |
2325 PHY_M_LED_MO_RX(MO_LED_ON)
2326 : PHY_M_LED_MO_DUP(MO_LED_OFF) |
2327 PHY_M_LED_MO_10(MO_LED_OFF) |
2328 PHY_M_LED_MO_100(MO_LED_OFF) |
2329 PHY_M_LED_MO_1000(MO_LED_OFF) |
2330 PHY_M_LED_MO_RX(MO_LED_OFF));
2333 spin_unlock_bh(&hw->phy_lock);
2336 /* blink LED's for finding board */
2337 static int sky2_phys_id(struct net_device *dev, u32 data)
2339 struct sky2_port *sky2 = netdev_priv(dev);
2340 struct sky2_hw *hw = sky2->hw;
2341 unsigned port = sky2->port;
2342 u16 ledctrl, ledover = 0;
2346 if (!data || data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ))
2347 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT);
2351 /* save initial values */
2352 spin_lock_bh(&hw->phy_lock);
2353 if (hw->chip_id == CHIP_ID_YUKON_XL) {
2354 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2355 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2356 ledctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
2357 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2359 ledctrl = gm_phy_read(hw, port, PHY_MARV_LED_CTRL);
2360 ledover = gm_phy_read(hw, port, PHY_MARV_LED_OVER);
2362 spin_unlock_bh(&hw->phy_lock);
2365 sky2_led(hw, port, onoff);
2368 if (msleep_interruptible(250))
2369 break; /* interrupted */
2373 /* resume regularly scheduled programming */
2374 spin_lock_bh(&hw->phy_lock);
2375 if (hw->chip_id == CHIP_ID_YUKON_XL) {
2376 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2377 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2378 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ledctrl);
2379 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2381 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
2382 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
2384 spin_unlock_bh(&hw->phy_lock);
2389 static void sky2_get_pauseparam(struct net_device *dev,
2390 struct ethtool_pauseparam *ecmd)
2392 struct sky2_port *sky2 = netdev_priv(dev);
2394 ecmd->tx_pause = sky2->tx_pause;
2395 ecmd->rx_pause = sky2->rx_pause;
2396 ecmd->autoneg = sky2->autoneg;
2399 static int sky2_set_pauseparam(struct net_device *dev,
2400 struct ethtool_pauseparam *ecmd)
2402 struct sky2_port *sky2 = netdev_priv(dev);
2405 sky2->autoneg = ecmd->autoneg;
2406 sky2->tx_pause = ecmd->tx_pause != 0;
2407 sky2->rx_pause = ecmd->rx_pause != 0;
2409 if (netif_running(dev)) {
2418 static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2420 struct sky2_port *sky2 = netdev_priv(dev);
2422 wol->supported = WAKE_MAGIC;
2423 wol->wolopts = sky2->wol ? WAKE_MAGIC : 0;
2426 static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2428 struct sky2_port *sky2 = netdev_priv(dev);
2429 struct sky2_hw *hw = sky2->hw;
2431 if (wol->wolopts != WAKE_MAGIC && wol->wolopts != 0)
2434 sky2->wol = wol->wolopts == WAKE_MAGIC;
2437 memcpy_toio(hw->regs + WOL_MAC_ADDR, dev->dev_addr, ETH_ALEN);
2439 sky2_write16(hw, WOL_CTRL_STAT,
2440 WOL_CTL_ENA_PME_ON_MAGIC_PKT |
2441 WOL_CTL_ENA_MAGIC_PKT_UNIT);
2443 sky2_write16(hw, WOL_CTRL_STAT, WOL_CTL_DEFAULT);
2449 static void sky2_get_ringparam(struct net_device *dev,
2450 struct ethtool_ringparam *ering)
2452 struct sky2_port *sky2 = netdev_priv(dev);
2454 ering->rx_max_pending = RX_MAX_PENDING;
2455 ering->rx_mini_max_pending = 0;
2456 ering->rx_jumbo_max_pending = 0;
2457 ering->tx_max_pending = TX_RING_SIZE - 1;
2459 ering->rx_pending = sky2->rx_pending;
2460 ering->rx_mini_pending = 0;
2461 ering->rx_jumbo_pending = 0;
2462 ering->tx_pending = sky2->tx_pending;
2465 static int sky2_set_ringparam(struct net_device *dev,
2466 struct ethtool_ringparam *ering)
2468 struct sky2_port *sky2 = netdev_priv(dev);
2471 if (ering->rx_pending > RX_MAX_PENDING ||
2472 ering->rx_pending < 8 ||
2473 ering->tx_pending < MAX_SKB_TX_LE ||
2474 ering->tx_pending > TX_RING_SIZE - 1)
2477 if (netif_running(dev))
2480 sky2->rx_pending = ering->rx_pending;
2481 sky2->tx_pending = ering->tx_pending;
2483 if (netif_running(dev))
2489 #define SKY2_REGS_LEN 0x1000
2490 static int sky2_get_regs_len(struct net_device *dev)
2492 return SKY2_REGS_LEN;
2496 * Returns copy of control register region
2497 * I/O region is divided into banks and certain regions are unreadable
2499 static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
2502 const struct sky2_port *sky2 = netdev_priv(dev);
2504 const void __iomem *io = sky2->hw->regs;
2505 static const unsigned long bankmap = 0xfff3f305;
2508 for (offs = 0; offs < regs->len; offs += 128) {
2509 u32 len = min_t(u32, 128, regs->len - offs);
2511 if (bankmap & (1 << (offs / 128)))
2512 memcpy_fromio(p + offs, io + offs, len);
2514 memset(p + offs, 0, len);
2518 static struct ethtool_ops sky2_ethtool_ops = {
2519 .get_settings = sky2_get_settings,
2520 .set_settings = sky2_set_settings,
2521 .get_drvinfo = sky2_get_drvinfo,
2522 .get_msglevel = sky2_get_msglevel,
2523 .set_msglevel = sky2_set_msglevel,
2524 .get_regs_len = sky2_get_regs_len,
2525 .get_regs = sky2_get_regs,
2526 .get_link = ethtool_op_get_link,
2527 .get_sg = ethtool_op_get_sg,
2528 .set_sg = ethtool_op_set_sg,
2529 .get_tx_csum = ethtool_op_get_tx_csum,
2530 .set_tx_csum = ethtool_op_set_tx_csum,
2531 .get_tso = ethtool_op_get_tso,
2532 .set_tso = ethtool_op_set_tso,
2533 .get_rx_csum = sky2_get_rx_csum,
2534 .set_rx_csum = sky2_set_rx_csum,
2535 .get_strings = sky2_get_strings,
2536 .get_ringparam = sky2_get_ringparam,
2537 .set_ringparam = sky2_set_ringparam,
2538 .get_pauseparam = sky2_get_pauseparam,
2539 .set_pauseparam = sky2_set_pauseparam,
2541 .get_wol = sky2_get_wol,
2542 .set_wol = sky2_set_wol,
2544 .phys_id = sky2_phys_id,
2545 .get_stats_count = sky2_get_stats_count,
2546 .get_ethtool_stats = sky2_get_ethtool_stats,
2549 /* Initialize network device */
2550 static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
2551 unsigned port, int highmem)
2553 struct sky2_port *sky2;
2554 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
2557 printk(KERN_ERR "sky2 etherdev alloc failed");
2561 SET_MODULE_OWNER(dev);
2562 SET_NETDEV_DEV(dev, &hw->pdev->dev);
2563 dev->open = sky2_up;
2564 dev->stop = sky2_down;
2565 dev->hard_start_xmit = sky2_xmit_frame;
2566 dev->get_stats = sky2_get_stats;
2567 dev->set_multicast_list = sky2_set_multicast;
2568 dev->set_mac_address = sky2_set_mac_address;
2569 dev->change_mtu = sky2_change_mtu;
2570 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
2571 dev->tx_timeout = sky2_tx_timeout;
2572 dev->watchdog_timeo = TX_WATCHDOG;
2574 dev->poll = sky2_poll;
2575 dev->weight = NAPI_WEIGHT;
2576 #ifdef CONFIG_NET_POLL_CONTROLLER
2577 dev->poll_controller = sky2_netpoll;
2580 sky2 = netdev_priv(dev);
2583 sky2->msg_enable = netif_msg_init(debug, default_msg);
2585 spin_lock_init(&sky2->tx_lock);
2586 /* Auto speed and flow control */
2587 sky2->autoneg = AUTONEG_ENABLE;
2592 sky2->advertising = sky2_supported_modes(hw);
2594 tasklet_init(&sky2->phy_task, sky2_phy_task, (unsigned long)sky2);
2595 sky2->tx_pending = TX_DEF_PENDING;
2596 sky2->rx_pending = is_ec_a1(hw) ? 8 : RX_DEF_PENDING;
2598 hw->dev[port] = dev;
2602 dev->features |= NETIF_F_LLTX | NETIF_F_TSO;
2604 dev->features |= NETIF_F_HIGHDMA;
2605 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
2607 /* read the mac address */
2608 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
2610 /* device is off until link detection */
2611 netif_carrier_off(dev);
2612 netif_stop_queue(dev);
2617 static inline void sky2_show_addr(struct net_device *dev)
2619 const struct sky2_port *sky2 = netdev_priv(dev);
2621 if (netif_msg_probe(sky2))
2622 printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
2624 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
2625 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
2628 static int __devinit sky2_probe(struct pci_dev *pdev,
2629 const struct pci_device_id *ent)
2631 struct net_device *dev, *dev1 = NULL;
2633 int err, using_dac = 0;
2635 err = pci_enable_device(pdev);
2637 printk(KERN_ERR PFX "%s cannot enable PCI device\n",
2642 err = pci_request_regions(pdev, DRV_NAME);
2644 printk(KERN_ERR PFX "%s cannot obtain PCI resources\n",
2649 pci_set_master(pdev);
2651 if (sizeof(dma_addr_t) > sizeof(u32)) {
2652 err = pci_set_dma_mask(pdev, DMA_64BIT_MASK);
2658 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
2660 printk(KERN_ERR PFX "%s no usable DMA configuration\n",
2662 goto err_out_free_regions;
2666 /* byte swap decriptors in hardware */
2670 pci_read_config_dword(pdev, PCI_DEV_REG2, ®);
2671 reg |= PCI_REV_DESC;
2672 pci_write_config_dword(pdev, PCI_DEV_REG2, reg);
2677 hw = kmalloc(sizeof(*hw), GFP_KERNEL);
2679 printk(KERN_ERR PFX "%s: cannot allocate hardware struct\n",
2681 goto err_out_free_regions;
2684 memset(hw, 0, sizeof(*hw));
2686 spin_lock_init(&hw->phy_lock);
2688 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
2690 printk(KERN_ERR PFX "%s: cannot map device registers\n",
2692 goto err_out_free_hw;
2695 err = sky2_reset(hw);
2697 goto err_out_iounmap;
2699 printk(KERN_INFO PFX "addr 0x%lx irq %d Yukon-%s (0x%x) rev %d\n",
2700 pci_resource_start(pdev, 0), pdev->irq,
2701 yukon_name[hw->chip_id - CHIP_ID_YUKON],
2702 hw->chip_id, hw->chip_rev);
2704 dev = sky2_init_netdev(hw, 0, using_dac);
2706 goto err_out_free_pci;
2708 err = register_netdev(dev);
2710 printk(KERN_ERR PFX "%s: cannot register net device\n",
2712 goto err_out_free_netdev;
2715 sky2_show_addr(dev);
2717 if (hw->ports > 1 && (dev1 = sky2_init_netdev(hw, 1, using_dac))) {
2718 if (register_netdev(dev1) == 0)
2719 sky2_show_addr(dev1);
2721 /* Failure to register second port need not be fatal */
2722 printk(KERN_WARNING PFX
2723 "register of second port failed\n");
2729 err = request_irq(pdev->irq, sky2_intr, SA_SHIRQ, DRV_NAME, hw);
2731 printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
2732 pci_name(pdev), pdev->irq);
2733 goto err_out_unregister;
2736 hw->intr_mask = Y2_IS_BASE;
2737 sky2_write32(hw, B0_IMSK, hw->intr_mask);
2739 pci_set_drvdata(pdev, hw);
2745 unregister_netdev(dev1);
2748 unregister_netdev(dev);
2749 err_out_free_netdev:
2752 sky2_write8(hw, B0_CTST, CS_RST_SET);
2753 pci_free_consistent(hw->pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
2758 err_out_free_regions:
2759 pci_release_regions(pdev);
2760 pci_disable_device(pdev);
2765 static void __devexit sky2_remove(struct pci_dev *pdev)
2767 struct sky2_hw *hw = pci_get_drvdata(pdev);
2768 struct net_device *dev0, *dev1;
2776 unregister_netdev(dev1);
2777 unregister_netdev(dev0);
2779 sky2_write32(hw, B0_IMSK, 0);
2780 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
2781 sky2_write8(hw, B0_CTST, CS_RST_SET);
2783 free_irq(pdev->irq, hw);
2784 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
2785 pci_release_regions(pdev);
2786 pci_disable_device(pdev);
2793 pci_set_drvdata(pdev, NULL);
2797 static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
2799 struct sky2_hw *hw = pci_get_drvdata(pdev);
2802 for (i = 0; i < 2; i++) {
2803 struct net_device *dev = hw->dev[i];
2806 struct sky2_port *sky2 = netdev_priv(dev);
2807 if (netif_running(dev)) {
2808 netif_carrier_off(dev);
2811 netif_device_detach(dev);
2816 pci_save_state(pdev);
2817 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
2818 pci_disable_device(pdev);
2819 pci_set_power_state(pdev, pci_choose_state(pdev, state));
2824 static int sky2_resume(struct pci_dev *pdev)
2826 struct sky2_hw *hw = pci_get_drvdata(pdev);
2829 pci_set_power_state(pdev, PCI_D0);
2830 pci_restore_state(pdev);
2831 pci_enable_wake(pdev, PCI_D0, 0);
2835 for (i = 0; i < 2; i++) {
2836 struct net_device *dev = hw->dev[i];
2838 netif_device_attach(dev);
2839 if (netif_running(dev))
2847 static struct pci_driver sky2_driver = {
2849 .id_table = sky2_id_table,
2850 .probe = sky2_probe,
2851 .remove = __devexit_p(sky2_remove),
2853 .suspend = sky2_suspend,
2854 .resume = sky2_resume,
2858 static int __init sky2_init_module(void)
2860 return pci_module_init(&sky2_driver);
2863 static void __exit sky2_cleanup_module(void)
2865 pci_unregister_driver(&sky2_driver);
2868 module_init(sky2_init_module);
2869 module_exit(sky2_cleanup_module);
2871 MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
2872 MODULE_AUTHOR("Stephen Hemminger <shemminger@osdl.org>");
2873 MODULE_LICENSE("GPL");