2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
32 #include <linux/config.h>
33 #include <linux/crc32.h>
34 #include <linux/kernel.h>
35 #include <linux/version.h>
36 #include <linux/module.h>
37 #include <linux/netdevice.h>
38 #include <linux/dma-mapping.h>
39 #include <linux/etherdevice.h>
40 #include <linux/ethtool.h>
41 #include <linux/pci.h>
43 #include <linux/tcp.h>
45 #include <linux/delay.h>
46 #include <linux/workqueue.h>
47 #include <linux/if_vlan.h>
48 #include <linux/mii.h>
52 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
53 #define SKY2_VLAN_TAG_USED 1
58 #define DRV_NAME "sky2"
59 #define DRV_VERSION "0.9"
60 #define PFX DRV_NAME " "
63 * The Yukon II chipset takes 64 bit command blocks (called list elements)
64 * that are organized into three (receive, transmit, status) different rings
65 * similar to Tigon3. A transmit can require several elements;
66 * a receive requires one (or two if using 64 bit dma).
69 #define is_ec_a1(hw) \
70 unlikely((hw)->chip_id == CHIP_ID_YUKON_EC && \
71 (hw)->chip_rev == CHIP_REV_YU_EC_A1)
73 #define RX_LE_SIZE 512
74 #define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
75 #define RX_MAX_PENDING (RX_LE_SIZE/2 - 2)
76 #define RX_DEF_PENDING RX_MAX_PENDING
78 #define TX_RING_SIZE 512
79 #define TX_DEF_PENDING (TX_RING_SIZE - 1)
80 #define TX_MIN_PENDING 64
81 #define MAX_SKB_TX_LE (4 + 2*MAX_SKB_FRAGS)
83 #define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
84 #define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
85 #define ETH_JUMBO_MTU 9000
86 #define TX_WATCHDOG (5 * HZ)
87 #define NAPI_WEIGHT 64
88 #define PHY_RETRIES 1000
90 static const u32 default_msg =
91 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
92 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
93 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN | NETIF_MSG_INTR;
95 static int debug = -1; /* defaults above */
96 module_param(debug, int, 0);
97 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
99 static int copybreak __read_mostly = 256;
100 module_param(copybreak, int, 0);
101 MODULE_PARM_DESC(copybreak, "Receive copy threshold");
103 static const struct pci_device_id sky2_id_table[] = {
104 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) },
105 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) },
106 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) },
107 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b01) },
108 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) },
109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) },
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) },
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) },
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) },
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) },
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) },
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) },
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) },
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) },
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) },
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) },
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) },
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) },
122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) },
126 MODULE_DEVICE_TABLE(pci, sky2_id_table);
128 /* Avoid conditionals by using array */
129 static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
130 static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
132 /* This driver supports yukon2 chipset only */
133 static const char *yukon2_name[] = {
135 "EC Ultra", /* 0xb4 */
136 "UNKNOWN", /* 0xb5 */
141 /* Access to external PHY */
142 static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
146 gma_write16(hw, port, GM_SMI_DATA, val);
147 gma_write16(hw, port, GM_SMI_CTRL,
148 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
150 for (i = 0; i < PHY_RETRIES; i++) {
151 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
156 printk(KERN_WARNING PFX "%s: phy write timeout\n", hw->dev[port]->name);
160 static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
164 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
165 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
167 for (i = 0; i < PHY_RETRIES; i++) {
168 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL) {
169 *val = gma_read16(hw, port, GM_SMI_DATA);
179 static u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
183 if (__gm_phy_read(hw, port, reg, &v) != 0)
184 printk(KERN_WARNING PFX "%s: phy read timeout\n", hw->dev[port]->name);
188 static int sky2_set_power_state(struct sky2_hw *hw, pci_power_t state)
195 pr_debug("sky2_set_power_state %d\n", state);
196 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
198 pci_read_config_word(hw->pdev, hw->pm_cap + PCI_PM_PMC, &power_control);
199 vaux = (sky2_read8(hw, B0_CTST) & Y2_VAUX_AVAIL) &&
200 (power_control & PCI_PM_CAP_PME_D3cold);
202 pci_read_config_word(hw->pdev, hw->pm_cap + PCI_PM_CTRL, &power_control);
204 power_control |= PCI_PM_CTRL_PME_STATUS;
205 power_control &= ~(PCI_PM_CTRL_STATE_MASK);
209 /* switch power to VCC (WA for VAUX problem) */
210 sky2_write8(hw, B0_POWER_CTRL,
211 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
213 /* disable Core Clock Division, */
214 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
216 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
217 /* enable bits are inverted */
218 sky2_write8(hw, B2_Y2_CLK_GATE,
219 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
220 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
221 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
223 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
225 /* Turn off phy power saving */
226 pci_read_config_dword(hw->pdev, PCI_DEV_REG1, ®1);
227 reg1 &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
229 /* looks like this XL is back asswards .. */
230 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1) {
231 reg1 |= PCI_Y2_PHY1_COMA;
233 reg1 |= PCI_Y2_PHY2_COMA;
235 pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg1);
240 /* Turn on phy power saving */
241 pci_read_config_dword(hw->pdev, PCI_DEV_REG1, ®1);
242 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
243 reg1 &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
245 reg1 |= (PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
246 pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg1);
248 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
249 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
251 /* enable bits are inverted */
252 sky2_write8(hw, B2_Y2_CLK_GATE,
253 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
254 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
255 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
257 /* switch power to VAUX */
258 if (vaux && state != PCI_D3cold)
259 sky2_write8(hw, B0_POWER_CTRL,
260 (PC_VAUX_ENA | PC_VCC_ENA |
261 PC_VAUX_ON | PC_VCC_OFF));
264 printk(KERN_ERR PFX "Unknown power state %d\n", state);
268 pci_write_config_byte(hw->pdev, hw->pm_cap + PCI_PM_CTRL, power_control);
269 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
273 static void sky2_phy_reset(struct sky2_hw *hw, unsigned port)
277 /* disable all GMAC IRQ's */
278 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
279 /* disable PHY IRQs */
280 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
282 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
283 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
284 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
285 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
287 reg = gma_read16(hw, port, GM_RX_CTRL);
288 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
289 gma_write16(hw, port, GM_RX_CTRL, reg);
292 static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
294 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
295 u16 ctrl, ct1000, adv, pg, ledctrl, ledover;
297 if (sky2->autoneg == AUTONEG_ENABLE && hw->chip_id != CHIP_ID_YUKON_XL) {
298 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
300 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
302 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
304 if (hw->chip_id == CHIP_ID_YUKON_EC)
305 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
307 ectrl |= PHY_M_EC_M_DSC(2) | PHY_M_EC_S_DSC(3);
309 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
312 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
314 if (hw->chip_id == CHIP_ID_YUKON_FE) {
315 /* enable automatic crossover */
316 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
318 /* disable energy detect */
319 ctrl &= ~PHY_M_PC_EN_DET_MSK;
321 /* enable automatic crossover */
322 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
324 if (sky2->autoneg == AUTONEG_ENABLE &&
325 hw->chip_id == CHIP_ID_YUKON_XL) {
326 ctrl &= ~PHY_M_PC_DSC_MSK;
327 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
330 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
332 /* workaround for deviation #4.88 (CRC errors) */
333 /* disable Automatic Crossover */
335 ctrl &= ~PHY_M_PC_MDIX_MSK;
336 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
338 if (hw->chip_id == CHIP_ID_YUKON_XL) {
339 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
340 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
341 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
342 ctrl &= ~PHY_M_MAC_MD_MSK;
343 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
344 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
346 /* select page 1 to access Fiber registers */
347 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
351 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
352 if (sky2->autoneg == AUTONEG_DISABLE)
357 ctrl |= PHY_CT_RESET;
358 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
364 if (sky2->autoneg == AUTONEG_ENABLE) {
366 if (sky2->advertising & ADVERTISED_1000baseT_Full)
367 ct1000 |= PHY_M_1000C_AFD;
368 if (sky2->advertising & ADVERTISED_1000baseT_Half)
369 ct1000 |= PHY_M_1000C_AHD;
370 if (sky2->advertising & ADVERTISED_100baseT_Full)
371 adv |= PHY_M_AN_100_FD;
372 if (sky2->advertising & ADVERTISED_100baseT_Half)
373 adv |= PHY_M_AN_100_HD;
374 if (sky2->advertising & ADVERTISED_10baseT_Full)
375 adv |= PHY_M_AN_10_FD;
376 if (sky2->advertising & ADVERTISED_10baseT_Half)
377 adv |= PHY_M_AN_10_HD;
378 } else /* special defines for FIBER (88E1011S only) */
379 adv |= PHY_M_AN_1000X_AHD | PHY_M_AN_1000X_AFD;
381 /* Set Flow-control capabilities */
382 if (sky2->tx_pause && sky2->rx_pause)
383 adv |= PHY_AN_PAUSE_CAP; /* symmetric */
384 else if (sky2->rx_pause && !sky2->tx_pause)
385 adv |= PHY_AN_PAUSE_ASYM | PHY_AN_PAUSE_CAP;
386 else if (!sky2->rx_pause && sky2->tx_pause)
387 adv |= PHY_AN_PAUSE_ASYM; /* local */
389 /* Restart Auto-negotiation */
390 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
392 /* forced speed/duplex settings */
393 ct1000 = PHY_M_1000C_MSE;
395 if (sky2->duplex == DUPLEX_FULL)
396 ctrl |= PHY_CT_DUP_MD;
398 switch (sky2->speed) {
400 ctrl |= PHY_CT_SP1000;
403 ctrl |= PHY_CT_SP100;
407 ctrl |= PHY_CT_RESET;
410 if (hw->chip_id != CHIP_ID_YUKON_FE)
411 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
413 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
414 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
416 /* Setup Phy LED's */
417 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
420 switch (hw->chip_id) {
421 case CHIP_ID_YUKON_FE:
422 /* on 88E3082 these bits are at 11..9 (shifted left) */
423 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
425 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
427 /* delete ACT LED control bits */
428 ctrl &= ~PHY_M_FELP_LED1_MSK;
429 /* change ACT LED control to blink mode */
430 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
431 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
434 case CHIP_ID_YUKON_XL:
435 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
437 /* select page 3 to access LED control register */
438 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
440 /* set LED Function Control register */
441 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
442 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
443 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
444 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
446 /* set Polarity Control register */
447 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
448 (PHY_M_POLC_LS1_P_MIX(4) |
449 PHY_M_POLC_IS0_P_MIX(4) |
450 PHY_M_POLC_LOS_CTRL(2) |
451 PHY_M_POLC_INIT_CTRL(2) |
452 PHY_M_POLC_STA1_CTRL(2) |
453 PHY_M_POLC_STA0_CTRL(2)));
455 /* restore page register */
456 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
460 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
461 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
462 /* turn off the Rx LED (LED_RX) */
463 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
466 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
468 if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
469 /* turn on 100 Mbps LED (LED_LINK100) */
470 ledover |= PHY_M_LED_MO_100(MO_LED_ON);
474 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
476 /* Enable phy interrupt on auto-negotiation complete (or link up) */
477 if (sky2->autoneg == AUTONEG_ENABLE)
478 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
480 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
483 static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
485 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
488 const u8 *addr = hw->dev[port]->dev_addr;
490 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
491 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR|GPC_ENA_PAUSE);
493 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
495 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
496 /* WA DEV_472 -- looks like crossed wires on port 2 */
497 /* clear GMAC 1 Control reset */
498 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
500 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
501 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
502 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
503 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
504 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
507 if (sky2->autoneg == AUTONEG_DISABLE) {
508 reg = gma_read16(hw, port, GM_GP_CTRL);
509 reg |= GM_GPCR_AU_ALL_DIS;
510 gma_write16(hw, port, GM_GP_CTRL, reg);
511 gma_read16(hw, port, GM_GP_CTRL);
513 switch (sky2->speed) {
515 reg |= GM_GPCR_SPEED_1000;
518 reg |= GM_GPCR_SPEED_100;
521 if (sky2->duplex == DUPLEX_FULL)
522 reg |= GM_GPCR_DUP_FULL;
524 reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL;
526 if (!sky2->tx_pause && !sky2->rx_pause) {
527 sky2_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
529 GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
530 } else if (sky2->tx_pause && !sky2->rx_pause) {
531 /* disable Rx flow-control */
532 reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
535 gma_write16(hw, port, GM_GP_CTRL, reg);
537 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
539 down(&sky2->phy_sema);
540 sky2_phy_init(hw, port);
544 reg = gma_read16(hw, port, GM_PHY_ADDR);
545 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
547 for (i = 0; i < GM_MIB_CNT_SIZE; i++)
548 gma_read16(hw, port, GM_MIB_CNT_BASE + 8 * i);
549 gma_write16(hw, port, GM_PHY_ADDR, reg);
551 /* transmit control */
552 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
554 /* receive control reg: unicast + multicast + no FCS */
555 gma_write16(hw, port, GM_RX_CTRL,
556 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
558 /* transmit flow control */
559 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
561 /* transmit parameter */
562 gma_write16(hw, port, GM_TX_PARAM,
563 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
564 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
565 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
566 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
568 /* serial mode register */
569 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
570 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
572 if (hw->dev[port]->mtu > ETH_DATA_LEN)
573 reg |= GM_SMOD_JUMBO_ENA;
575 gma_write16(hw, port, GM_SERIAL_MODE, reg);
577 /* virtual address for data */
578 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
580 /* physical address: used for pause frames */
581 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
583 /* ignore counter overflows */
584 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
585 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
586 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
588 /* Configure Rx MAC FIFO */
589 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
590 sky2_write16(hw, SK_REG(port, RX_GMF_CTRL_T),
593 /* Flush Rx MAC FIFO on any flow control or error */
594 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
596 /* Set threshold to 0xa (64 bytes)
597 * ASF disabled so no need to do WA dev #4.30
599 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF);
601 /* Configure Tx MAC FIFO */
602 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
603 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
605 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
606 sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8);
607 sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
608 if (hw->dev[port]->mtu > ETH_DATA_LEN) {
609 /* set Tx GMAC FIFO Almost Empty Threshold */
610 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR), 0x180);
611 /* Disable Store & Forward mode for TX */
612 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);
618 static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, size_t len)
624 end = start + len - 1;
626 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
627 sky2_write32(hw, RB_ADDR(q, RB_START), start);
628 sky2_write32(hw, RB_ADDR(q, RB_END), end);
629 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
630 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
632 if (q == Q_R1 || q == Q_R2) {
638 /* Set thresholds on receive queue's */
639 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), rxup);
640 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), rxlo);
642 /* Enable store & forward on Tx queue's because
643 * Tx FIFO is only 1K on Yukon
645 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
648 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
649 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
652 /* Setup Bus Memory Interface */
653 static void sky2_qset(struct sky2_hw *hw, u16 q)
655 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
656 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
657 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
658 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
661 /* Setup prefetch unit registers. This is the interface between
662 * hardware and driver list elements
664 static inline void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
667 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
668 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
669 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32);
670 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr);
671 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
672 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
674 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
677 static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2)
679 struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod;
681 sky2->tx_prod = (sky2->tx_prod + 1) % TX_RING_SIZE;
686 * This is a workaround code taken from SysKonnect sk98lin driver
687 * to deal with chip bug on Yukon EC rev 0 in the wraparound case.
689 static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q,
690 u16 idx, u16 *last, u16 size)
692 if (is_ec_a1(hw) && idx < *last) {
693 u16 hwget = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));
696 /* Start prefetching again */
697 sky2_write8(hw, Y2_QADDR(q, PREF_UNIT_FIFO_WM), 0xe0);
701 if (hwget == size - 1) {
702 /* set watermark to one list element */
703 sky2_write8(hw, Y2_QADDR(q, PREF_UNIT_FIFO_WM), 8);
705 /* set put index to first list element */
706 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), 0);
707 } else /* have hardware go to end of list */
708 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX),
712 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
718 static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
720 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
721 sky2->rx_put = (sky2->rx_put + 1) % RX_LE_SIZE;
725 /* Return high part of DMA address (could be 32 or 64 bit) */
726 static inline u32 high32(dma_addr_t a)
728 return (a >> 16) >> 16;
731 /* Build description to hardware about buffer */
732 static inline void sky2_rx_add(struct sky2_port *sky2, dma_addr_t map)
734 struct sky2_rx_le *le;
735 u32 hi = high32(map);
736 u16 len = sky2->rx_bufsize;
738 if (sky2->rx_addr64 != hi) {
739 le = sky2_next_rx(sky2);
740 le->addr = cpu_to_le32(hi);
742 le->opcode = OP_ADDR64 | HW_OWNER;
743 sky2->rx_addr64 = high32(map + len);
746 le = sky2_next_rx(sky2);
747 le->addr = cpu_to_le32((u32) map);
748 le->length = cpu_to_le16(len);
750 le->opcode = OP_PACKET | HW_OWNER;
754 /* Tell chip where to start receive checksum.
755 * Actually has two checksums, but set both same to avoid possible byte
758 static void rx_set_checksum(struct sky2_port *sky2)
760 struct sky2_rx_le *le;
762 le = sky2_next_rx(sky2);
763 le->addr = (ETH_HLEN << 16) | ETH_HLEN;
765 le->opcode = OP_TCPSTART | HW_OWNER;
767 sky2_write32(sky2->hw,
768 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
769 sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
774 * The RX Stop command will not work for Yukon-2 if the BMU does not
775 * reach the end of packet and since we can't make sure that we have
776 * incoming data, we must reset the BMU while it is not doing a DMA
777 * transfer. Since it is possible that the RX path is still active,
778 * the RX RAM buffer will be stopped first, so any possible incoming
779 * data will not trigger a DMA. After the RAM buffer is stopped, the
780 * BMU is polled until any DMA in progress is ended and only then it
783 static void sky2_rx_stop(struct sky2_port *sky2)
785 struct sky2_hw *hw = sky2->hw;
786 unsigned rxq = rxqaddr[sky2->port];
789 /* disable the RAM Buffer receive queue */
790 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
792 for (i = 0; i < 0xffff; i++)
793 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
794 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
797 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
800 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
802 /* reset the Rx prefetch unit */
803 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
806 /* Clean out receive buffer area, assumes receiver hardware stopped */
807 static void sky2_rx_clean(struct sky2_port *sky2)
811 memset(sky2->rx_le, 0, RX_LE_BYTES);
812 for (i = 0; i < sky2->rx_pending; i++) {
813 struct ring_info *re = sky2->rx_ring + i;
816 pci_unmap_single(sky2->hw->pdev,
817 re->mapaddr, sky2->rx_bufsize,
825 /* Basic MII support */
826 static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
828 struct mii_ioctl_data *data = if_mii(ifr);
829 struct sky2_port *sky2 = netdev_priv(dev);
830 struct sky2_hw *hw = sky2->hw;
831 int err = -EOPNOTSUPP;
833 if (!netif_running(dev))
834 return -ENODEV; /* Phy still in reset */
838 data->phy_id = PHY_ADDR_MARV;
844 down(&sky2->phy_sema);
845 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
853 if (!capable(CAP_NET_ADMIN))
856 down(&sky2->phy_sema);
857 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
865 #ifdef SKY2_VLAN_TAG_USED
866 static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
868 struct sky2_port *sky2 = netdev_priv(dev);
869 struct sky2_hw *hw = sky2->hw;
870 u16 port = sky2->port;
872 spin_lock(&sky2->tx_lock);
874 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_ON);
875 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_ON);
878 spin_unlock(&sky2->tx_lock);
881 static void sky2_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
883 struct sky2_port *sky2 = netdev_priv(dev);
884 struct sky2_hw *hw = sky2->hw;
885 u16 port = sky2->port;
887 spin_lock(&sky2->tx_lock);
889 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_OFF);
890 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_OFF);
892 sky2->vlgrp->vlan_devices[vid] = NULL;
894 spin_unlock(&sky2->tx_lock);
899 * Allocate and setup receiver buffer pool.
900 * In case of 64 bit dma, there are 2X as many list elements
901 * available as ring entries
902 * and need to reserve one list element so we don't wrap around.
904 * It appears the hardware has a bug in the FIFO logic that
905 * cause it to hang if the FIFO gets overrun and the receive buffer
906 * is not aligned. This means we can't use skb_reserve to align
909 static int sky2_rx_start(struct sky2_port *sky2)
911 struct sky2_hw *hw = sky2->hw;
912 unsigned rxq = rxqaddr[sky2->port];
915 sky2->rx_put = sky2->rx_next = 0;
917 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
919 rx_set_checksum(sky2);
920 for (i = 0; i < sky2->rx_pending; i++) {
921 struct ring_info *re = sky2->rx_ring + i;
923 re->skb = dev_alloc_skb(sky2->rx_bufsize);
927 re->mapaddr = pci_map_single(hw->pdev, re->skb->data,
928 sky2->rx_bufsize, PCI_DMA_FROMDEVICE);
929 sky2_rx_add(sky2, re->mapaddr);
932 /* Tell chip about available buffers */
933 sky2_write16(hw, Y2_QADDR(rxq, PREF_UNIT_PUT_IDX), sky2->rx_put);
934 sky2->rx_last_put = sky2_read16(hw, Y2_QADDR(rxq, PREF_UNIT_PUT_IDX));
941 /* Bring up network interface. */
942 static int sky2_up(struct net_device *dev)
944 struct sky2_port *sky2 = netdev_priv(dev);
945 struct sky2_hw *hw = sky2->hw;
946 unsigned port = sky2->port;
947 u32 ramsize, rxspace;
950 if (netif_msg_ifup(sky2))
951 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
953 /* must be power of 2 */
954 sky2->tx_le = pci_alloc_consistent(hw->pdev,
956 sizeof(struct sky2_tx_le),
961 sky2->tx_ring = kcalloc(TX_RING_SIZE, sizeof(struct tx_ring_info),
965 sky2->tx_prod = sky2->tx_cons = 0;
967 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
971 memset(sky2->rx_le, 0, RX_LE_BYTES);
973 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct ring_info),
978 sky2_mac_init(hw, port);
980 /* Configure RAM buffers */
981 if (hw->chip_id == CHIP_ID_YUKON_FE ||
982 (hw->chip_id == CHIP_ID_YUKON_EC && hw->chip_rev == 2))
985 u8 e0 = sky2_read8(hw, B2_E_0);
986 ramsize = (e0 == 0) ? (128 * 1024) : (e0 * 4096);
990 rxspace = (2 * ramsize) / 3;
991 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
992 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
994 /* Make sure SyncQ is disabled */
995 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
998 sky2_qset(hw, txqaddr[port]);
999 if (hw->chip_id == CHIP_ID_YUKON_EC_U)
1000 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), 0x1a0);
1003 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1006 err = sky2_rx_start(sky2);
1010 /* Enable interrupts from phy/mac for port */
1011 hw->intr_mask |= (port == 0) ? Y2_IS_PORT_1 : Y2_IS_PORT_2;
1012 sky2_write32(hw, B0_IMSK, hw->intr_mask);
1017 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1018 sky2->rx_le, sky2->rx_le_map);
1020 pci_free_consistent(hw->pdev,
1021 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1022 sky2->tx_le, sky2->tx_le_map);
1024 kfree(sky2->tx_ring);
1026 kfree(sky2->rx_ring);
1031 /* Modular subtraction in ring */
1032 static inline int tx_dist(unsigned tail, unsigned head)
1034 return (head - tail) % TX_RING_SIZE;
1037 /* Number of list elements available for next tx */
1038 static inline int tx_avail(const struct sky2_port *sky2)
1040 return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod);
1043 /* Estimate of number of transmit list elements required */
1044 static inline unsigned tx_le_req(const struct sk_buff *skb)
1048 count = sizeof(dma_addr_t) / sizeof(u32);
1049 count += skb_shinfo(skb)->nr_frags * count;
1051 if (skb_shinfo(skb)->tso_size)
1054 if (skb->ip_summed == CHECKSUM_HW)
1061 * Put one packet in ring for transmit.
1062 * A single packet can generate multiple list elements, and
1063 * the number of ring elements will probably be less than the number
1064 * of list elements used.
1066 * No BH disabling for tx_lock here (like tg3)
1068 static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
1070 struct sky2_port *sky2 = netdev_priv(dev);
1071 struct sky2_hw *hw = sky2->hw;
1072 struct sky2_tx_le *le = NULL;
1073 struct tx_ring_info *re;
1080 if (!spin_trylock(&sky2->tx_lock))
1081 return NETDEV_TX_LOCKED;
1083 if (unlikely(tx_avail(sky2) < tx_le_req(skb))) {
1084 netif_stop_queue(dev);
1085 spin_unlock(&sky2->tx_lock);
1087 printk(KERN_WARNING PFX "%s: ring full when queue awake!\n",
1089 return NETDEV_TX_BUSY;
1092 if (unlikely(netif_msg_tx_queued(sky2)))
1093 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
1094 dev->name, sky2->tx_prod, skb->len);
1096 len = skb_headlen(skb);
1097 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
1098 addr64 = high32(mapping);
1100 re = sky2->tx_ring + sky2->tx_prod;
1102 /* Send high bits if changed or crosses boundary */
1103 if (addr64 != sky2->tx_addr64 || high32(mapping + len) != sky2->tx_addr64) {
1104 le = get_tx_le(sky2);
1105 le->tx.addr = cpu_to_le32(addr64);
1107 le->opcode = OP_ADDR64 | HW_OWNER;
1108 sky2->tx_addr64 = high32(mapping + len);
1111 /* Check for TCP Segmentation Offload */
1112 mss = skb_shinfo(skb)->tso_size;
1114 /* just drop the packet if non-linear expansion fails */
1115 if (skb_header_cloned(skb) &&
1116 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
1117 dev_kfree_skb_any(skb);
1121 mss += ((skb->h.th->doff - 5) * 4); /* TCP options */
1122 mss += (skb->nh.iph->ihl * 4) + sizeof(struct tcphdr);
1126 if (mss != sky2->tx_last_mss) {
1127 le = get_tx_le(sky2);
1128 le->tx.tso.size = cpu_to_le16(mss);
1129 le->tx.tso.rsvd = 0;
1130 le->opcode = OP_LRGLEN | HW_OWNER;
1132 sky2->tx_last_mss = mss;
1136 #ifdef SKY2_VLAN_TAG_USED
1137 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1138 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1140 le = get_tx_le(sky2);
1142 le->opcode = OP_VLAN|HW_OWNER;
1145 le->opcode |= OP_VLAN;
1146 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1151 /* Handle TCP checksum offload */
1152 if (skb->ip_summed == CHECKSUM_HW) {
1153 u16 hdr = skb->h.raw - skb->data;
1154 u16 offset = hdr + skb->csum;
1156 ctrl = CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1157 if (skb->nh.iph->protocol == IPPROTO_UDP)
1160 le = get_tx_le(sky2);
1161 le->tx.csum.start = cpu_to_le16(hdr);
1162 le->tx.csum.offset = cpu_to_le16(offset);
1163 le->length = 0; /* initial checksum value */
1164 le->ctrl = 1; /* one packet */
1165 le->opcode = OP_TCPLISW | HW_OWNER;
1168 le = get_tx_le(sky2);
1169 le->tx.addr = cpu_to_le32((u32) mapping);
1170 le->length = cpu_to_le16(len);
1172 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
1174 /* Record the transmit mapping info */
1176 pci_unmap_addr_set(re, mapaddr, mapping);
1178 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1179 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1180 struct tx_ring_info *fre;
1182 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1183 frag->size, PCI_DMA_TODEVICE);
1184 addr64 = (mapping >> 16) >> 16;
1185 if (addr64 != sky2->tx_addr64) {
1186 le = get_tx_le(sky2);
1187 le->tx.addr = cpu_to_le32(addr64);
1189 le->opcode = OP_ADDR64 | HW_OWNER;
1190 sky2->tx_addr64 = addr64;
1193 le = get_tx_le(sky2);
1194 le->tx.addr = cpu_to_le32((u32) mapping);
1195 le->length = cpu_to_le16(frag->size);
1197 le->opcode = OP_BUFFER | HW_OWNER;
1200 + ((re - sky2->tx_ring) + i + 1) % TX_RING_SIZE;
1201 pci_unmap_addr_set(fre, mapaddr, mapping);
1204 re->idx = sky2->tx_prod;
1207 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod,
1208 &sky2->tx_last_put, TX_RING_SIZE);
1210 if (tx_avail(sky2) <= MAX_SKB_TX_LE)
1211 netif_stop_queue(dev);
1215 spin_unlock(&sky2->tx_lock);
1217 dev->trans_start = jiffies;
1218 return NETDEV_TX_OK;
1222 * Free ring elements from starting at tx_cons until "done"
1224 * NB: the hardware will tell us about partial completion of multi-part
1225 * buffers; these are deferred until completion.
1227 static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
1229 struct net_device *dev = sky2->netdev;
1232 BUG_ON(done >= TX_RING_SIZE);
1234 if (unlikely(netif_msg_tx_done(sky2)))
1235 printk(KERN_DEBUG "%s: tx done, up to %u\n",
1238 spin_lock(&sky2->tx_lock);
1240 while (sky2->tx_cons != done) {
1241 struct tx_ring_info *re = sky2->tx_ring + sky2->tx_cons;
1242 struct sk_buff *skb;
1244 /* Check for partial status */
1245 if (tx_dist(sky2->tx_cons, done)
1246 < tx_dist(sky2->tx_cons, re->idx))
1250 pci_unmap_single(sky2->hw->pdev,
1251 pci_unmap_addr(re, mapaddr),
1252 skb_headlen(skb), PCI_DMA_TODEVICE);
1254 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1255 struct tx_ring_info *fre;
1257 sky2->tx_ring + (sky2->tx_cons + i +
1259 pci_unmap_page(sky2->hw->pdev,
1260 pci_unmap_addr(fre, mapaddr),
1261 skb_shinfo(skb)->frags[i].size,
1265 dev_kfree_skb_any(skb);
1267 sky2->tx_cons = re->idx;
1271 if (netif_queue_stopped(dev) && tx_avail(sky2) > MAX_SKB_TX_LE)
1272 netif_wake_queue(dev);
1273 spin_unlock(&sky2->tx_lock);
1276 /* Cleanup all untransmitted buffers, assume transmitter not running */
1277 static void sky2_tx_clean(struct sky2_port *sky2)
1279 sky2_tx_complete(sky2, sky2->tx_prod);
1282 /* Network shutdown */
1283 static int sky2_down(struct net_device *dev)
1285 struct sky2_port *sky2 = netdev_priv(dev);
1286 struct sky2_hw *hw = sky2->hw;
1287 unsigned port = sky2->port;
1290 if (netif_msg_ifdown(sky2))
1291 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1293 /* Stop more packets from being queued */
1294 netif_stop_queue(dev);
1296 /* Disable port IRQ */
1297 local_irq_disable();
1298 hw->intr_mask &= ~((sky2->port == 0) ? Y2_IS_IRQ_PHY1 : Y2_IS_IRQ_PHY2);
1299 sky2_write32(hw, B0_IMSK, hw->intr_mask);
1302 flush_scheduled_work();
1304 sky2_phy_reset(hw, port);
1306 /* Stop transmitter */
1307 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1308 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1310 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
1311 RB_RST_SET | RB_DIS_OP_MD);
1313 ctrl = gma_read16(hw, port, GM_GP_CTRL);
1314 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
1315 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1317 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1319 /* Workaround shared GMAC reset */
1320 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
1321 && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
1322 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1324 /* Disable Force Sync bit and Enable Alloc bit */
1325 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1326 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1328 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1329 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1330 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1332 /* Reset the PCI FIFO of the async Tx queue */
1333 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1334 BMU_RST_SET | BMU_FIFO_RST);
1336 /* Reset the Tx prefetch units */
1337 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1340 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1344 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1345 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1347 /* turn off LED's */
1348 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
1350 synchronize_irq(hw->pdev->irq);
1352 sky2_tx_clean(sky2);
1353 sky2_rx_clean(sky2);
1355 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1356 sky2->rx_le, sky2->rx_le_map);
1357 kfree(sky2->rx_ring);
1359 pci_free_consistent(hw->pdev,
1360 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1361 sky2->tx_le, sky2->tx_le_map);
1362 kfree(sky2->tx_ring);
1367 static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1372 if (hw->chip_id == CHIP_ID_YUKON_FE)
1373 return (aux & PHY_M_PS_SPEED_100) ? SPEED_100 : SPEED_10;
1375 switch (aux & PHY_M_PS_SPEED_MSK) {
1376 case PHY_M_PS_SPEED_1000:
1378 case PHY_M_PS_SPEED_100:
1385 static void sky2_link_up(struct sky2_port *sky2)
1387 struct sky2_hw *hw = sky2->hw;
1388 unsigned port = sky2->port;
1391 /* Enable Transmit FIFO Underrun */
1392 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
1394 reg = gma_read16(hw, port, GM_GP_CTRL);
1395 if (sky2->duplex == DUPLEX_FULL || sky2->autoneg == AUTONEG_ENABLE)
1396 reg |= GM_GPCR_DUP_FULL;
1399 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1400 gma_write16(hw, port, GM_GP_CTRL, reg);
1401 gma_read16(hw, port, GM_GP_CTRL);
1403 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1405 netif_carrier_on(sky2->netdev);
1406 netif_wake_queue(sky2->netdev);
1408 /* Turn on link LED */
1409 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
1410 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
1412 if (hw->chip_id == CHIP_ID_YUKON_XL) {
1413 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
1415 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
1416 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
1417 PHY_M_LEDC_INIT_CTRL(sky2->speed ==
1419 PHY_M_LEDC_STA1_CTRL(sky2->speed ==
1420 SPEED_100 ? 7 : 0) |
1421 PHY_M_LEDC_STA0_CTRL(sky2->speed ==
1422 SPEED_1000 ? 7 : 0));
1423 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
1426 if (netif_msg_link(sky2))
1427 printk(KERN_INFO PFX
1428 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
1429 sky2->netdev->name, sky2->speed,
1430 sky2->duplex == DUPLEX_FULL ? "full" : "half",
1431 (sky2->tx_pause && sky2->rx_pause) ? "both" :
1432 sky2->tx_pause ? "tx" : sky2->rx_pause ? "rx" : "none");
1435 static void sky2_link_down(struct sky2_port *sky2)
1437 struct sky2_hw *hw = sky2->hw;
1438 unsigned port = sky2->port;
1441 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1443 reg = gma_read16(hw, port, GM_GP_CTRL);
1444 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1445 gma_write16(hw, port, GM_GP_CTRL, reg);
1446 gma_read16(hw, port, GM_GP_CTRL); /* PCI post */
1448 if (sky2->rx_pause && !sky2->tx_pause) {
1449 /* restore Asymmetric Pause bit */
1450 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,
1451 gm_phy_read(hw, port, PHY_MARV_AUNE_ADV)
1455 sky2_phy_reset(hw, port);
1457 netif_carrier_off(sky2->netdev);
1458 netif_stop_queue(sky2->netdev);
1460 /* Turn on link LED */
1461 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
1463 if (netif_msg_link(sky2))
1464 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
1465 sky2_phy_init(hw, port);
1468 static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
1470 struct sky2_hw *hw = sky2->hw;
1471 unsigned port = sky2->port;
1474 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
1476 if (lpa & PHY_M_AN_RF) {
1477 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
1481 if (hw->chip_id != CHIP_ID_YUKON_FE &&
1482 gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) {
1483 printk(KERN_ERR PFX "%s: master/slave fault",
1484 sky2->netdev->name);
1488 if (!(aux & PHY_M_PS_SPDUP_RES)) {
1489 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
1490 sky2->netdev->name);
1494 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1496 sky2->speed = sky2_phy_speed(hw, aux);
1498 /* Pause bits are offset (9..8) */
1499 if (hw->chip_id == CHIP_ID_YUKON_XL)
1502 sky2->rx_pause = (aux & PHY_M_PS_RX_P_EN) != 0;
1503 sky2->tx_pause = (aux & PHY_M_PS_TX_P_EN) != 0;
1505 if ((sky2->tx_pause || sky2->rx_pause)
1506 && !(sky2->speed < SPEED_1000 && sky2->duplex == DUPLEX_HALF))
1507 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
1509 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1515 * Interrupt from PHY are handled outside of interrupt context
1516 * because accessing phy registers requires spin wait which might
1517 * cause excess interrupt latency.
1519 static void sky2_phy_task(void *arg)
1521 struct sky2_port *sky2 = arg;
1522 struct sky2_hw *hw = sky2->hw;
1523 u16 istatus, phystat;
1525 down(&sky2->phy_sema);
1526 istatus = gm_phy_read(hw, sky2->port, PHY_MARV_INT_STAT);
1527 phystat = gm_phy_read(hw, sky2->port, PHY_MARV_PHY_STAT);
1529 if (netif_msg_intr(sky2))
1530 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
1531 sky2->netdev->name, istatus, phystat);
1533 if (istatus & PHY_M_IS_AN_COMPL) {
1534 if (sky2_autoneg_done(sky2, phystat) == 0)
1539 if (istatus & PHY_M_IS_LSP_CHANGE)
1540 sky2->speed = sky2_phy_speed(hw, phystat);
1542 if (istatus & PHY_M_IS_DUP_CHANGE)
1544 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1546 if (istatus & PHY_M_IS_LST_CHANGE) {
1547 if (phystat & PHY_M_PS_LINK_UP)
1550 sky2_link_down(sky2);
1553 up(&sky2->phy_sema);
1555 local_irq_disable();
1556 hw->intr_mask |= (sky2->port == 0) ? Y2_IS_IRQ_PHY1 : Y2_IS_IRQ_PHY2;
1557 sky2_write32(hw, B0_IMSK, hw->intr_mask);
1561 static void sky2_tx_timeout(struct net_device *dev)
1563 struct sky2_port *sky2 = netdev_priv(dev);
1565 if (netif_msg_timer(sky2))
1566 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
1568 sky2_write32(sky2->hw, Q_ADDR(txqaddr[sky2->port], Q_CSR), BMU_STOP);
1569 sky2_read32(sky2->hw, Q_ADDR(txqaddr[sky2->port], Q_CSR));
1571 sky2_tx_clean(sky2);
1575 #define roundup(x, y) ((((x)+((y)-1))/(y))*(y))
1576 /* Want receive buffer size to be multiple of 64 bits, and incl room for vlan */
1577 static inline unsigned sky2_buf_size(int mtu)
1579 return roundup(mtu + ETH_HLEN + 4, 8);
1582 static int sky2_change_mtu(struct net_device *dev, int new_mtu)
1584 struct sky2_port *sky2 = netdev_priv(dev);
1585 struct sky2_hw *hw = sky2->hw;
1589 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
1592 if (hw->chip_id == CHIP_ID_YUKON_EC_U && new_mtu > ETH_DATA_LEN)
1595 if (!netif_running(dev)) {
1600 sky2_write32(hw, B0_IMSK, 0);
1602 dev->trans_start = jiffies; /* prevent tx timeout */
1603 netif_stop_queue(dev);
1604 netif_poll_disable(hw->dev[0]);
1606 ctl = gma_read16(hw, sky2->port, GM_GP_CTRL);
1607 gma_write16(hw, sky2->port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
1609 sky2_rx_clean(sky2);
1612 sky2->rx_bufsize = sky2_buf_size(new_mtu);
1613 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
1614 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
1616 if (dev->mtu > ETH_DATA_LEN)
1617 mode |= GM_SMOD_JUMBO_ENA;
1619 gma_write16(hw, sky2->port, GM_SERIAL_MODE, mode);
1621 sky2_write8(hw, RB_ADDR(rxqaddr[sky2->port], RB_CTRL), RB_ENA_OP_MD);
1623 err = sky2_rx_start(sky2);
1624 gma_write16(hw, sky2->port, GM_GP_CTRL, ctl);
1626 netif_poll_disable(hw->dev[0]);
1627 netif_wake_queue(dev);
1628 sky2_write32(hw, B0_IMSK, hw->intr_mask);
1634 * Receive one packet.
1635 * For small packets or errors, just reuse existing skb.
1636 * For larger packets, get new buffer.
1638 static struct sk_buff *sky2_receive(struct sky2_port *sky2,
1639 u16 length, u32 status)
1641 struct ring_info *re = sky2->rx_ring + sky2->rx_next;
1642 struct sk_buff *skb = NULL;
1644 if (unlikely(netif_msg_rx_status(sky2)))
1645 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
1646 sky2->netdev->name, sky2->rx_next, status, length);
1648 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
1650 if (status & GMR_FS_ANY_ERR)
1653 if (!(status & GMR_FS_RX_OK))
1656 if (length < copybreak) {
1657 skb = alloc_skb(length + 2, GFP_ATOMIC);
1661 skb_reserve(skb, 2);
1662 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->mapaddr,
1663 length, PCI_DMA_FROMDEVICE);
1664 memcpy(skb->data, re->skb->data, length);
1665 skb->ip_summed = re->skb->ip_summed;
1666 skb->csum = re->skb->csum;
1667 pci_dma_sync_single_for_device(sky2->hw->pdev, re->mapaddr,
1668 length, PCI_DMA_FROMDEVICE);
1670 struct sk_buff *nskb;
1672 nskb = dev_alloc_skb(sky2->rx_bufsize);
1678 pci_unmap_single(sky2->hw->pdev, re->mapaddr,
1679 sky2->rx_bufsize, PCI_DMA_FROMDEVICE);
1680 prefetch(skb->data);
1682 re->mapaddr = pci_map_single(sky2->hw->pdev, nskb->data,
1683 sky2->rx_bufsize, PCI_DMA_FROMDEVICE);
1686 skb_put(skb, length);
1688 re->skb->ip_summed = CHECKSUM_NONE;
1689 sky2_rx_add(sky2, re->mapaddr);
1691 /* Tell receiver about new buffers. */
1692 sky2_put_idx(sky2->hw, rxqaddr[sky2->port], sky2->rx_put,
1693 &sky2->rx_last_put, RX_LE_SIZE);
1698 if (netif_msg_rx_err(sky2))
1699 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
1700 sky2->netdev->name, status, length);
1702 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
1703 sky2->net_stats.rx_length_errors++;
1704 if (status & GMR_FS_FRAGMENT)
1705 sky2->net_stats.rx_frame_errors++;
1706 if (status & GMR_FS_CRC_ERR)
1707 sky2->net_stats.rx_crc_errors++;
1708 if (status & GMR_FS_RX_FF_OV)
1709 sky2->net_stats.rx_fifo_errors++;
1715 * Check for transmit complete
1717 #define TX_NO_STATUS 0xffff
1719 static inline void sky2_tx_check(struct sky2_hw *hw, int port, u16 last)
1721 if (last != TX_NO_STATUS) {
1722 struct net_device *dev = hw->dev[port];
1723 if (dev && netif_running(dev)) {
1724 struct sky2_port *sky2 = netdev_priv(dev);
1725 sky2_tx_complete(sky2, last);
1731 * Both ports share the same status interrupt, therefore there is only
1734 static int sky2_poll(struct net_device *dev0, int *budget)
1736 struct sky2_hw *hw = ((struct sky2_port *) netdev_priv(dev0))->hw;
1737 unsigned int to_do = min(dev0->quota, *budget);
1738 unsigned int work_done = 0;
1740 u16 tx_done[2] = { TX_NO_STATUS, TX_NO_STATUS };
1742 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
1743 hwidx = sky2_read16(hw, STAT_PUT_IDX);
1744 BUG_ON(hwidx >= STATUS_RING_SIZE);
1747 while (hwidx != hw->st_idx) {
1748 struct sky2_status_le *le = hw->st_le + hw->st_idx;
1749 struct net_device *dev;
1750 struct sky2_port *sky2;
1751 struct sk_buff *skb;
1756 le = hw->st_le + hw->st_idx;
1757 hw->st_idx = (hw->st_idx + 1) % STATUS_RING_SIZE;
1758 prefetch(hw->st_le + hw->st_idx);
1760 BUG_ON(le->link >= hw->ports || !hw->dev[le->link]);
1762 BUG_ON(le->link >= 2);
1763 dev = hw->dev[le->link];
1764 if (dev == NULL || !netif_running(dev))
1767 sky2 = netdev_priv(dev);
1768 status = le32_to_cpu(le->status);
1769 length = le16_to_cpu(le->length);
1770 op = le->opcode & ~HW_OWNER;
1775 skb = sky2_receive(sky2, length, status);
1780 skb->protocol = eth_type_trans(skb, dev);
1781 dev->last_rx = jiffies;
1783 #ifdef SKY2_VLAN_TAG_USED
1784 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
1785 vlan_hwaccel_receive_skb(skb,
1787 be16_to_cpu(sky2->rx_tag));
1790 netif_receive_skb(skb);
1792 if (++work_done >= to_do)
1796 #ifdef SKY2_VLAN_TAG_USED
1798 sky2->rx_tag = length;
1802 sky2->rx_tag = length;
1806 skb = sky2->rx_ring[sky2->rx_next].skb;
1807 skb->ip_summed = CHECKSUM_HW;
1808 skb->csum = le16_to_cpu(status);
1812 /* TX index reports status for both ports */
1813 tx_done[0] = status & 0xffff;
1814 tx_done[1] = ((status >> 24) & 0xff)
1815 | (u16)(length & 0xf) << 8;
1819 if (net_ratelimit())
1820 printk(KERN_WARNING PFX
1821 "unknown status opcode 0x%x\n", op);
1829 sky2_tx_check(hw, 0, tx_done[0]);
1830 sky2_tx_check(hw, 1, tx_done[1]);
1832 if (work_done < to_do) {
1833 /* need to restart TX timer */
1835 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
1836 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
1839 netif_rx_complete(dev0);
1840 hw->intr_mask |= Y2_IS_STAT_BMU;
1841 sky2_write32(hw, B0_IMSK, hw->intr_mask);
1845 *budget -= work_done;
1846 dev0->quota -= work_done;
1851 static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
1853 struct net_device *dev = hw->dev[port];
1855 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
1858 if (status & Y2_IS_PAR_RD1) {
1859 printk(KERN_ERR PFX "%s: ram data read parity error\n",
1862 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
1865 if (status & Y2_IS_PAR_WR1) {
1866 printk(KERN_ERR PFX "%s: ram data write parity error\n",
1869 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
1872 if (status & Y2_IS_PAR_MAC1) {
1873 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
1874 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
1877 if (status & Y2_IS_PAR_RX1) {
1878 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
1879 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
1882 if (status & Y2_IS_TCP_TXA1) {
1883 printk(KERN_ERR PFX "%s: TCP segmentation error\n", dev->name);
1884 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
1888 static void sky2_hw_intr(struct sky2_hw *hw)
1890 u32 status = sky2_read32(hw, B0_HWE_ISRC);
1892 if (status & Y2_IS_TIST_OV)
1893 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
1895 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
1898 pci_read_config_word(hw->pdev, PCI_STATUS, &pci_err);
1899 printk(KERN_ERR PFX "%s: pci hw error (0x%x)\n",
1900 pci_name(hw->pdev), pci_err);
1902 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
1903 pci_write_config_word(hw->pdev, PCI_STATUS,
1904 pci_err | PCI_STATUS_ERROR_BITS);
1905 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
1908 if (status & Y2_IS_PCI_EXP) {
1909 /* PCI-Express uncorrectable Error occurred */
1912 pci_read_config_dword(hw->pdev, PEX_UNC_ERR_STAT, &pex_err);
1914 printk(KERN_ERR PFX "%s: pci express error (0x%x)\n",
1915 pci_name(hw->pdev), pex_err);
1917 /* clear the interrupt */
1918 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
1919 pci_write_config_dword(hw->pdev, PEX_UNC_ERR_STAT,
1921 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
1923 if (pex_err & PEX_FATAL_ERRORS) {
1924 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
1925 hwmsk &= ~Y2_IS_PCI_EXP;
1926 sky2_write32(hw, B0_HWE_IMSK, hwmsk);
1930 if (status & Y2_HWE_L1_MASK)
1931 sky2_hw_error(hw, 0, status);
1933 if (status & Y2_HWE_L1_MASK)
1934 sky2_hw_error(hw, 1, status);
1937 static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
1939 struct net_device *dev = hw->dev[port];
1940 struct sky2_port *sky2 = netdev_priv(dev);
1941 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
1943 if (netif_msg_intr(sky2))
1944 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
1947 if (status & GM_IS_RX_FF_OR) {
1948 ++sky2->net_stats.rx_fifo_errors;
1949 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
1952 if (status & GM_IS_TX_FF_UR) {
1953 ++sky2->net_stats.tx_fifo_errors;
1954 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
1958 static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
1960 struct net_device *dev = hw->dev[port];
1961 struct sky2_port *sky2 = netdev_priv(dev);
1963 hw->intr_mask &= ~(port == 0 ? Y2_IS_IRQ_PHY1 : Y2_IS_IRQ_PHY2);
1964 sky2_write32(hw, B0_IMSK, hw->intr_mask);
1965 schedule_work(&sky2->phy_task);
1968 static irqreturn_t sky2_intr(int irq, void *dev_id, struct pt_regs *regs)
1970 struct sky2_hw *hw = dev_id;
1971 struct net_device *dev0 = hw->dev[0];
1974 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
1975 if (status == 0 || status == ~0)
1978 if (status & Y2_IS_HW_ERR)
1981 /* Do NAPI for Rx and Tx status */
1982 if (status & Y2_IS_STAT_BMU) {
1983 hw->intr_mask &= ~Y2_IS_STAT_BMU;
1984 sky2_write32(hw, B0_IMSK, hw->intr_mask);
1986 if (likely(__netif_rx_schedule_prep(dev0))) {
1987 prefetch(&hw->st_le[hw->st_idx]);
1988 __netif_rx_schedule(dev0);
1992 if (status & Y2_IS_IRQ_PHY1)
1993 sky2_phy_intr(hw, 0);
1995 if (status & Y2_IS_IRQ_PHY2)
1996 sky2_phy_intr(hw, 1);
1998 if (status & Y2_IS_IRQ_MAC1)
1999 sky2_mac_intr(hw, 0);
2001 if (status & Y2_IS_IRQ_MAC2)
2002 sky2_mac_intr(hw, 1);
2004 sky2_write32(hw, B0_Y2_SP_ICR, 2);
2006 sky2_read32(hw, B0_IMSK);
2011 #ifdef CONFIG_NET_POLL_CONTROLLER
2012 static void sky2_netpoll(struct net_device *dev)
2014 struct sky2_port *sky2 = netdev_priv(dev);
2016 sky2_intr(sky2->hw->pdev->irq, sky2->hw, NULL);
2020 /* Chip internal frequency for clock calculations */
2021 static inline u32 sky2_mhz(const struct sky2_hw *hw)
2023 switch (hw->chip_id) {
2024 case CHIP_ID_YUKON_EC:
2025 case CHIP_ID_YUKON_EC_U:
2026 return 125; /* 125 Mhz */
2027 case CHIP_ID_YUKON_FE:
2028 return 100; /* 100 Mhz */
2029 default: /* YUKON_XL */
2030 return 156; /* 156 Mhz */
2034 static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
2036 return sky2_mhz(hw) * us;
2039 static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
2041 return clk / sky2_mhz(hw);
2045 static int sky2_reset(struct sky2_hw *hw)
2052 ctst = sky2_read32(hw, B0_CTST);
2054 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2055 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
2056 if (hw->chip_id < CHIP_ID_YUKON_XL || hw->chip_id > CHIP_ID_YUKON_FE) {
2057 printk(KERN_ERR PFX "%s: unsupported chip type 0x%x\n",
2058 pci_name(hw->pdev), hw->chip_id);
2062 /* ring for status responses */
2063 hw->st_le = pci_alloc_consistent(hw->pdev, STATUS_LE_BYTES,
2069 if (hw->chip_id <= CHIP_ID_YUKON_EC) {
2070 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
2071 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
2075 sky2_write8(hw, B0_CTST, CS_RST_SET);
2076 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2078 /* clear PCI errors, if any */
2079 pci_read_config_word(hw->pdev, PCI_STATUS, &status);
2080 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2081 pci_write_config_word(hw->pdev, PCI_STATUS,
2082 status | PCI_STATUS_ERROR_BITS);
2084 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
2086 /* clear any PEX errors */
2089 pci_write_config_dword(hw->pdev, PEX_UNC_ERR_STAT,
2091 pci_read_config_word(hw->pdev, PEX_LNK_STAT, &lstat);
2094 pmd_type = sky2_read8(hw, B2_PMD_TYP);
2095 hw->copper = !(pmd_type == 'L' || pmd_type == 'S');
2098 t8 = sky2_read8(hw, B2_Y2_HW_RES);
2099 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
2100 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
2103 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2105 sky2_set_power_state(hw, PCI_D0);
2107 for (i = 0; i < hw->ports; i++) {
2108 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2109 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
2112 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2114 /* Clear I2C IRQ noise */
2115 sky2_write32(hw, B2_I2C_IRQ, 1);
2117 /* turn off hardware timer (unused) */
2118 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
2119 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
2121 sky2_write8(hw, B0_Y2LED, LED_STAT_ON);
2123 /* Turn on descriptor polling (every 75us) */
2124 sky2_write32(hw, B28_DPT_INI, sky2_us2clk(hw, 75));
2125 sky2_write8(hw, B28_DPT_CTRL, DPT_START);
2127 /* Turn off receive timestamp */
2128 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
2129 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2131 /* enable the Tx Arbiters */
2132 for (i = 0; i < hw->ports; i++)
2133 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
2135 /* Initialize ram interface */
2136 for (i = 0; i < hw->ports; i++) {
2137 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
2139 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
2140 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
2141 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
2142 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
2143 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
2144 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
2145 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
2146 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
2147 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
2148 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
2149 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
2150 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
2153 sky2_write32(hw, B0_HWE_IMSK, Y2_HWE_ALL_MASK);
2155 for (i = 0; i < hw->ports; i++)
2156 sky2_phy_reset(hw, i);
2158 memset(hw->st_le, 0, STATUS_LE_BYTES);
2161 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
2162 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
2164 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
2165 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
2167 /* Set the list last index */
2168 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
2170 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
2172 /* These status setup values are copied from SysKonnect's driver */
2174 /* WA for dev. #4.3 */
2175 sky2_write16(hw, STAT_TX_IDX_TH, 0xfff); /* Tx Threshold */
2177 /* set Status-FIFO watermark */
2178 sky2_write8(hw, STAT_FIFO_WM, 0x21); /* WA for dev. #4.18 */
2180 /* set Status-FIFO ISR watermark */
2181 sky2_write8(hw, STAT_FIFO_ISR_WM, 0x07); /* WA for dev. #4.18 */
2184 sky2_write16(hw, STAT_TX_IDX_TH, 0x000a);
2186 /* set Status-FIFO watermark */
2187 sky2_write8(hw, STAT_FIFO_WM, 0x10);
2189 /* set Status-FIFO ISR watermark */
2190 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
2191 sky2_write8(hw, STAT_FIFO_ISR_WM, 0x10);
2193 else /* WA dev 4.109 */
2194 sky2_write8(hw, STAT_FIFO_ISR_WM, 0x04);
2196 sky2_write32(hw, STAT_ISR_TIMER_INI, 0x0190);
2199 /* enable status unit */
2200 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
2202 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2203 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2204 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
2209 static inline u32 sky2_supported_modes(const struct sky2_hw *hw)
2213 modes = SUPPORTED_10baseT_Half
2214 | SUPPORTED_10baseT_Full
2215 | SUPPORTED_100baseT_Half
2216 | SUPPORTED_100baseT_Full
2217 | SUPPORTED_Autoneg | SUPPORTED_TP;
2219 if (hw->chip_id != CHIP_ID_YUKON_FE)
2220 modes |= SUPPORTED_1000baseT_Half
2221 | SUPPORTED_1000baseT_Full;
2223 modes = SUPPORTED_1000baseT_Full | SUPPORTED_FIBRE
2224 | SUPPORTED_Autoneg;
2228 static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2230 struct sky2_port *sky2 = netdev_priv(dev);
2231 struct sky2_hw *hw = sky2->hw;
2233 ecmd->transceiver = XCVR_INTERNAL;
2234 ecmd->supported = sky2_supported_modes(hw);
2235 ecmd->phy_address = PHY_ADDR_MARV;
2237 ecmd->supported = SUPPORTED_10baseT_Half
2238 | SUPPORTED_10baseT_Full
2239 | SUPPORTED_100baseT_Half
2240 | SUPPORTED_100baseT_Full
2241 | SUPPORTED_1000baseT_Half
2242 | SUPPORTED_1000baseT_Full
2243 | SUPPORTED_Autoneg | SUPPORTED_TP;
2244 ecmd->port = PORT_TP;
2246 ecmd->port = PORT_FIBRE;
2248 ecmd->advertising = sky2->advertising;
2249 ecmd->autoneg = sky2->autoneg;
2250 ecmd->speed = sky2->speed;
2251 ecmd->duplex = sky2->duplex;
2255 static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2257 struct sky2_port *sky2 = netdev_priv(dev);
2258 const struct sky2_hw *hw = sky2->hw;
2259 u32 supported = sky2_supported_modes(hw);
2261 if (ecmd->autoneg == AUTONEG_ENABLE) {
2262 ecmd->advertising = supported;
2268 switch (ecmd->speed) {
2270 if (ecmd->duplex == DUPLEX_FULL)
2271 setting = SUPPORTED_1000baseT_Full;
2272 else if (ecmd->duplex == DUPLEX_HALF)
2273 setting = SUPPORTED_1000baseT_Half;
2278 if (ecmd->duplex == DUPLEX_FULL)
2279 setting = SUPPORTED_100baseT_Full;
2280 else if (ecmd->duplex == DUPLEX_HALF)
2281 setting = SUPPORTED_100baseT_Half;
2287 if (ecmd->duplex == DUPLEX_FULL)
2288 setting = SUPPORTED_10baseT_Full;
2289 else if (ecmd->duplex == DUPLEX_HALF)
2290 setting = SUPPORTED_10baseT_Half;
2298 if ((setting & supported) == 0)
2301 sky2->speed = ecmd->speed;
2302 sky2->duplex = ecmd->duplex;
2305 sky2->autoneg = ecmd->autoneg;
2306 sky2->advertising = ecmd->advertising;
2308 if (netif_running(dev)) {
2316 static void sky2_get_drvinfo(struct net_device *dev,
2317 struct ethtool_drvinfo *info)
2319 struct sky2_port *sky2 = netdev_priv(dev);
2321 strcpy(info->driver, DRV_NAME);
2322 strcpy(info->version, DRV_VERSION);
2323 strcpy(info->fw_version, "N/A");
2324 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
2327 static const struct sky2_stat {
2328 char name[ETH_GSTRING_LEN];
2331 { "tx_bytes", GM_TXO_OK_HI },
2332 { "rx_bytes", GM_RXO_OK_HI },
2333 { "tx_broadcast", GM_TXF_BC_OK },
2334 { "rx_broadcast", GM_RXF_BC_OK },
2335 { "tx_multicast", GM_TXF_MC_OK },
2336 { "rx_multicast", GM_RXF_MC_OK },
2337 { "tx_unicast", GM_TXF_UC_OK },
2338 { "rx_unicast", GM_RXF_UC_OK },
2339 { "tx_mac_pause", GM_TXF_MPAUSE },
2340 { "rx_mac_pause", GM_RXF_MPAUSE },
2341 { "collisions", GM_TXF_SNG_COL },
2342 { "late_collision",GM_TXF_LAT_COL },
2343 { "aborted", GM_TXF_ABO_COL },
2344 { "multi_collisions", GM_TXF_MUL_COL },
2345 { "fifo_underrun", GM_TXE_FIFO_UR },
2346 { "fifo_overflow", GM_RXE_FIFO_OV },
2347 { "rx_toolong", GM_RXF_LNG_ERR },
2348 { "rx_jabber", GM_RXF_JAB_PKT },
2349 { "rx_runt", GM_RXE_FRAG },
2350 { "rx_too_long", GM_RXF_LNG_ERR },
2351 { "rx_fcs_error", GM_RXF_FCS_ERR },
2354 static u32 sky2_get_rx_csum(struct net_device *dev)
2356 struct sky2_port *sky2 = netdev_priv(dev);
2358 return sky2->rx_csum;
2361 static int sky2_set_rx_csum(struct net_device *dev, u32 data)
2363 struct sky2_port *sky2 = netdev_priv(dev);
2365 sky2->rx_csum = data;
2367 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
2368 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
2373 static u32 sky2_get_msglevel(struct net_device *netdev)
2375 struct sky2_port *sky2 = netdev_priv(netdev);
2376 return sky2->msg_enable;
2379 static int sky2_nway_reset(struct net_device *dev)
2381 struct sky2_port *sky2 = netdev_priv(dev);
2382 struct sky2_hw *hw = sky2->hw;
2384 if (sky2->autoneg != AUTONEG_ENABLE)
2387 netif_stop_queue(dev);
2389 down(&sky2->phy_sema);
2390 sky2_phy_reset(hw, sky2->port);
2391 sky2_phy_init(hw, sky2->port);
2392 up(&sky2->phy_sema);
2397 static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
2399 struct sky2_hw *hw = sky2->hw;
2400 unsigned port = sky2->port;
2403 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
2404 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
2405 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
2406 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
2408 for (i = 2; i < count; i++)
2409 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
2412 static void sky2_set_msglevel(struct net_device *netdev, u32 value)
2414 struct sky2_port *sky2 = netdev_priv(netdev);
2415 sky2->msg_enable = value;
2418 static int sky2_get_stats_count(struct net_device *dev)
2420 return ARRAY_SIZE(sky2_stats);
2423 static void sky2_get_ethtool_stats(struct net_device *dev,
2424 struct ethtool_stats *stats, u64 * data)
2426 struct sky2_port *sky2 = netdev_priv(dev);
2428 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
2431 static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
2435 switch (stringset) {
2437 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
2438 memcpy(data + i * ETH_GSTRING_LEN,
2439 sky2_stats[i].name, ETH_GSTRING_LEN);
2444 /* Use hardware MIB variables for critical path statistics and
2445 * transmit feedback not reported at interrupt.
2446 * Other errors are accounted for in interrupt handler.
2448 static struct net_device_stats *sky2_get_stats(struct net_device *dev)
2450 struct sky2_port *sky2 = netdev_priv(dev);
2453 sky2_phy_stats(sky2, data, ARRAY_SIZE(data));
2455 sky2->net_stats.tx_bytes = data[0];
2456 sky2->net_stats.rx_bytes = data[1];
2457 sky2->net_stats.tx_packets = data[2] + data[4] + data[6];
2458 sky2->net_stats.rx_packets = data[3] + data[5] + data[7];
2459 sky2->net_stats.multicast = data[5] + data[7];
2460 sky2->net_stats.collisions = data[10];
2461 sky2->net_stats.tx_aborted_errors = data[12];
2463 return &sky2->net_stats;
2466 static int sky2_set_mac_address(struct net_device *dev, void *p)
2468 struct sky2_port *sky2 = netdev_priv(dev);
2469 struct sockaddr *addr = p;
2472 if (!is_valid_ether_addr(addr->sa_data))
2473 return -EADDRNOTAVAIL;
2476 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
2477 memcpy_toio(sky2->hw->regs + B2_MAC_1 + sky2->port * 8,
2478 dev->dev_addr, ETH_ALEN);
2479 memcpy_toio(sky2->hw->regs + B2_MAC_2 + sky2->port * 8,
2480 dev->dev_addr, ETH_ALEN);
2481 if (dev->flags & IFF_UP)
2486 static void sky2_set_multicast(struct net_device *dev)
2488 struct sky2_port *sky2 = netdev_priv(dev);
2489 struct sky2_hw *hw = sky2->hw;
2490 unsigned port = sky2->port;
2491 struct dev_mc_list *list = dev->mc_list;
2495 memset(filter, 0, sizeof(filter));
2497 reg = gma_read16(hw, port, GM_RX_CTRL);
2498 reg |= GM_RXCR_UCF_ENA;
2500 if (dev->flags & IFF_PROMISC) /* promiscuous */
2501 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
2502 else if ((dev->flags & IFF_ALLMULTI) || dev->mc_count > 16) /* all multicast */
2503 memset(filter, 0xff, sizeof(filter));
2504 else if (dev->mc_count == 0) /* no multicast */
2505 reg &= ~GM_RXCR_MCF_ENA;
2508 reg |= GM_RXCR_MCF_ENA;
2510 for (i = 0; list && i < dev->mc_count; i++, list = list->next) {
2511 u32 bit = ether_crc(ETH_ALEN, list->dmi_addr) & 0x3f;
2512 filter[bit / 8] |= 1 << (bit % 8);
2516 gma_write16(hw, port, GM_MC_ADDR_H1,
2517 (u16) filter[0] | ((u16) filter[1] << 8));
2518 gma_write16(hw, port, GM_MC_ADDR_H2,
2519 (u16) filter[2] | ((u16) filter[3] << 8));
2520 gma_write16(hw, port, GM_MC_ADDR_H3,
2521 (u16) filter[4] | ((u16) filter[5] << 8));
2522 gma_write16(hw, port, GM_MC_ADDR_H4,
2523 (u16) filter[6] | ((u16) filter[7] << 8));
2525 gma_write16(hw, port, GM_RX_CTRL, reg);
2528 /* Can have one global because blinking is controlled by
2529 * ethtool and that is always under RTNL mutex
2531 static void sky2_led(struct sky2_hw *hw, unsigned port, int on)
2535 switch (hw->chip_id) {
2536 case CHIP_ID_YUKON_XL:
2537 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2538 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2539 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
2540 on ? (PHY_M_LEDC_LOS_CTRL(1) |
2541 PHY_M_LEDC_INIT_CTRL(7) |
2542 PHY_M_LEDC_STA1_CTRL(7) |
2543 PHY_M_LEDC_STA0_CTRL(7))
2546 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2550 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
2551 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
2552 on ? PHY_M_LED_MO_DUP(MO_LED_ON) |
2553 PHY_M_LED_MO_10(MO_LED_ON) |
2554 PHY_M_LED_MO_100(MO_LED_ON) |
2555 PHY_M_LED_MO_1000(MO_LED_ON) |
2556 PHY_M_LED_MO_RX(MO_LED_ON)
2557 : PHY_M_LED_MO_DUP(MO_LED_OFF) |
2558 PHY_M_LED_MO_10(MO_LED_OFF) |
2559 PHY_M_LED_MO_100(MO_LED_OFF) |
2560 PHY_M_LED_MO_1000(MO_LED_OFF) |
2561 PHY_M_LED_MO_RX(MO_LED_OFF));
2566 /* blink LED's for finding board */
2567 static int sky2_phys_id(struct net_device *dev, u32 data)
2569 struct sky2_port *sky2 = netdev_priv(dev);
2570 struct sky2_hw *hw = sky2->hw;
2571 unsigned port = sky2->port;
2572 u16 ledctrl, ledover = 0;
2577 if (!data || data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ))
2578 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT);
2582 /* save initial values */
2583 down(&sky2->phy_sema);
2584 if (hw->chip_id == CHIP_ID_YUKON_XL) {
2585 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2586 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2587 ledctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
2588 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2590 ledctrl = gm_phy_read(hw, port, PHY_MARV_LED_CTRL);
2591 ledover = gm_phy_read(hw, port, PHY_MARV_LED_OVER);
2595 while (!interrupted && ms > 0) {
2596 sky2_led(hw, port, onoff);
2599 up(&sky2->phy_sema);
2600 interrupted = msleep_interruptible(250);
2601 down(&sky2->phy_sema);
2606 /* resume regularly scheduled programming */
2607 if (hw->chip_id == CHIP_ID_YUKON_XL) {
2608 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2609 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2610 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ledctrl);
2611 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2613 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
2614 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
2616 up(&sky2->phy_sema);
2621 static void sky2_get_pauseparam(struct net_device *dev,
2622 struct ethtool_pauseparam *ecmd)
2624 struct sky2_port *sky2 = netdev_priv(dev);
2626 ecmd->tx_pause = sky2->tx_pause;
2627 ecmd->rx_pause = sky2->rx_pause;
2628 ecmd->autoneg = sky2->autoneg;
2631 static int sky2_set_pauseparam(struct net_device *dev,
2632 struct ethtool_pauseparam *ecmd)
2634 struct sky2_port *sky2 = netdev_priv(dev);
2637 sky2->autoneg = ecmd->autoneg;
2638 sky2->tx_pause = ecmd->tx_pause != 0;
2639 sky2->rx_pause = ecmd->rx_pause != 0;
2641 if (netif_running(dev)) {
2650 static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2652 struct sky2_port *sky2 = netdev_priv(dev);
2654 wol->supported = WAKE_MAGIC;
2655 wol->wolopts = sky2->wol ? WAKE_MAGIC : 0;
2658 static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2660 struct sky2_port *sky2 = netdev_priv(dev);
2661 struct sky2_hw *hw = sky2->hw;
2663 if (wol->wolopts != WAKE_MAGIC && wol->wolopts != 0)
2666 sky2->wol = wol->wolopts == WAKE_MAGIC;
2669 memcpy_toio(hw->regs + WOL_MAC_ADDR, dev->dev_addr, ETH_ALEN);
2671 sky2_write16(hw, WOL_CTRL_STAT,
2672 WOL_CTL_ENA_PME_ON_MAGIC_PKT |
2673 WOL_CTL_ENA_MAGIC_PKT_UNIT);
2675 sky2_write16(hw, WOL_CTRL_STAT, WOL_CTL_DEFAULT);
2681 static int sky2_get_coalesce(struct net_device *dev,
2682 struct ethtool_coalesce *ecmd)
2684 struct sky2_port *sky2 = netdev_priv(dev);
2685 struct sky2_hw *hw = sky2->hw;
2687 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
2688 ecmd->tx_coalesce_usecs = 0;
2690 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
2691 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
2693 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
2695 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
2696 ecmd->rx_coalesce_usecs = 0;
2698 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
2699 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
2701 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
2703 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
2704 ecmd->rx_coalesce_usecs_irq = 0;
2706 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
2707 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
2710 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
2715 /* Note: this affect both ports */
2716 static int sky2_set_coalesce(struct net_device *dev,
2717 struct ethtool_coalesce *ecmd)
2719 struct sky2_port *sky2 = netdev_priv(dev);
2720 struct sky2_hw *hw = sky2->hw;
2721 const u32 tmin = sky2_clk2us(hw, 1);
2722 const u32 tmax = 5000;
2724 if (ecmd->tx_coalesce_usecs != 0 &&
2725 (ecmd->tx_coalesce_usecs < tmin || ecmd->tx_coalesce_usecs > tmax))
2728 if (ecmd->rx_coalesce_usecs != 0 &&
2729 (ecmd->rx_coalesce_usecs < tmin || ecmd->rx_coalesce_usecs > tmax))
2732 if (ecmd->rx_coalesce_usecs_irq != 0 &&
2733 (ecmd->rx_coalesce_usecs_irq < tmin || ecmd->rx_coalesce_usecs_irq > tmax))
2736 if (ecmd->tx_max_coalesced_frames > 0xffff)
2738 if (ecmd->rx_max_coalesced_frames > 0xff)
2740 if (ecmd->rx_max_coalesced_frames_irq > 0xff)
2743 if (ecmd->tx_coalesce_usecs == 0)
2744 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
2746 sky2_write32(hw, STAT_TX_TIMER_INI,
2747 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
2748 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2750 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
2752 if (ecmd->rx_coalesce_usecs == 0)
2753 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
2755 sky2_write32(hw, STAT_LEV_TIMER_INI,
2756 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
2757 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2759 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
2761 if (ecmd->rx_coalesce_usecs_irq == 0)
2762 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
2764 sky2_write32(hw, STAT_TX_TIMER_INI,
2765 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
2766 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
2768 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
2772 static void sky2_get_ringparam(struct net_device *dev,
2773 struct ethtool_ringparam *ering)
2775 struct sky2_port *sky2 = netdev_priv(dev);
2777 ering->rx_max_pending = RX_MAX_PENDING;
2778 ering->rx_mini_max_pending = 0;
2779 ering->rx_jumbo_max_pending = 0;
2780 ering->tx_max_pending = TX_RING_SIZE - 1;
2782 ering->rx_pending = sky2->rx_pending;
2783 ering->rx_mini_pending = 0;
2784 ering->rx_jumbo_pending = 0;
2785 ering->tx_pending = sky2->tx_pending;
2788 static int sky2_set_ringparam(struct net_device *dev,
2789 struct ethtool_ringparam *ering)
2791 struct sky2_port *sky2 = netdev_priv(dev);
2794 if (ering->rx_pending > RX_MAX_PENDING ||
2795 ering->rx_pending < 8 ||
2796 ering->tx_pending < MAX_SKB_TX_LE ||
2797 ering->tx_pending > TX_RING_SIZE - 1)
2800 if (netif_running(dev))
2803 sky2->rx_pending = ering->rx_pending;
2804 sky2->tx_pending = ering->tx_pending;
2806 if (netif_running(dev))
2812 static int sky2_get_regs_len(struct net_device *dev)
2818 * Returns copy of control register region
2819 * Note: access to the RAM address register set will cause timeouts.
2821 static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
2824 const struct sky2_port *sky2 = netdev_priv(dev);
2825 const void __iomem *io = sky2->hw->regs;
2827 BUG_ON(regs->len < B3_RI_WTO_R1);
2829 memset(p, 0, regs->len);
2831 memcpy_fromio(p, io, B3_RAM_ADDR);
2833 memcpy_fromio(p + B3_RI_WTO_R1,
2835 regs->len - B3_RI_WTO_R1);
2838 static struct ethtool_ops sky2_ethtool_ops = {
2839 .get_settings = sky2_get_settings,
2840 .set_settings = sky2_set_settings,
2841 .get_drvinfo = sky2_get_drvinfo,
2842 .get_msglevel = sky2_get_msglevel,
2843 .set_msglevel = sky2_set_msglevel,
2844 .nway_reset = sky2_nway_reset,
2845 .get_regs_len = sky2_get_regs_len,
2846 .get_regs = sky2_get_regs,
2847 .get_link = ethtool_op_get_link,
2848 .get_sg = ethtool_op_get_sg,
2849 .set_sg = ethtool_op_set_sg,
2850 .get_tx_csum = ethtool_op_get_tx_csum,
2851 .set_tx_csum = ethtool_op_set_tx_csum,
2852 .get_tso = ethtool_op_get_tso,
2853 .set_tso = ethtool_op_set_tso,
2854 .get_rx_csum = sky2_get_rx_csum,
2855 .set_rx_csum = sky2_set_rx_csum,
2856 .get_strings = sky2_get_strings,
2857 .get_coalesce = sky2_get_coalesce,
2858 .set_coalesce = sky2_set_coalesce,
2859 .get_ringparam = sky2_get_ringparam,
2860 .set_ringparam = sky2_set_ringparam,
2861 .get_pauseparam = sky2_get_pauseparam,
2862 .set_pauseparam = sky2_set_pauseparam,
2864 .get_wol = sky2_get_wol,
2865 .set_wol = sky2_set_wol,
2867 .phys_id = sky2_phys_id,
2868 .get_stats_count = sky2_get_stats_count,
2869 .get_ethtool_stats = sky2_get_ethtool_stats,
2870 .get_perm_addr = ethtool_op_get_perm_addr,
2873 /* Initialize network device */
2874 static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
2875 unsigned port, int highmem)
2877 struct sky2_port *sky2;
2878 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
2881 printk(KERN_ERR "sky2 etherdev alloc failed");
2885 SET_MODULE_OWNER(dev);
2886 SET_NETDEV_DEV(dev, &hw->pdev->dev);
2887 dev->irq = hw->pdev->irq;
2888 dev->open = sky2_up;
2889 dev->stop = sky2_down;
2890 dev->do_ioctl = sky2_ioctl;
2891 dev->hard_start_xmit = sky2_xmit_frame;
2892 dev->get_stats = sky2_get_stats;
2893 dev->set_multicast_list = sky2_set_multicast;
2894 dev->set_mac_address = sky2_set_mac_address;
2895 dev->change_mtu = sky2_change_mtu;
2896 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
2897 dev->tx_timeout = sky2_tx_timeout;
2898 dev->watchdog_timeo = TX_WATCHDOG;
2900 dev->poll = sky2_poll;
2901 dev->weight = NAPI_WEIGHT;
2902 #ifdef CONFIG_NET_POLL_CONTROLLER
2903 dev->poll_controller = sky2_netpoll;
2906 sky2 = netdev_priv(dev);
2909 sky2->msg_enable = netif_msg_init(debug, default_msg);
2911 spin_lock_init(&sky2->tx_lock);
2912 /* Auto speed and flow control */
2913 sky2->autoneg = AUTONEG_ENABLE;
2918 sky2->advertising = sky2_supported_modes(hw);
2920 INIT_WORK(&sky2->phy_task, sky2_phy_task, sky2);
2921 init_MUTEX(&sky2->phy_sema);
2922 sky2->tx_pending = TX_DEF_PENDING;
2923 sky2->rx_pending = is_ec_a1(hw) ? 8 : RX_DEF_PENDING;
2924 sky2->rx_bufsize = sky2_buf_size(ETH_DATA_LEN);
2926 hw->dev[port] = dev;
2930 dev->features |= NETIF_F_LLTX;
2931 if (hw->chip_id != CHIP_ID_YUKON_EC_U)
2932 dev->features |= NETIF_F_TSO;
2934 dev->features |= NETIF_F_HIGHDMA;
2935 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
2937 #ifdef SKY2_VLAN_TAG_USED
2938 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
2939 dev->vlan_rx_register = sky2_vlan_rx_register;
2940 dev->vlan_rx_kill_vid = sky2_vlan_rx_kill_vid;
2943 /* read the mac address */
2944 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
2945 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
2947 /* device is off until link detection */
2948 netif_carrier_off(dev);
2949 netif_stop_queue(dev);
2954 static inline void sky2_show_addr(struct net_device *dev)
2956 const struct sky2_port *sky2 = netdev_priv(dev);
2958 if (netif_msg_probe(sky2))
2959 printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
2961 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
2962 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
2965 static int __devinit sky2_probe(struct pci_dev *pdev,
2966 const struct pci_device_id *ent)
2968 struct net_device *dev, *dev1 = NULL;
2970 int err, pm_cap, using_dac = 0;
2972 err = pci_enable_device(pdev);
2974 printk(KERN_ERR PFX "%s cannot enable PCI device\n",
2979 err = pci_request_regions(pdev, DRV_NAME);
2981 printk(KERN_ERR PFX "%s cannot obtain PCI resources\n",
2986 pci_set_master(pdev);
2988 /* Find power-management capability. */
2989 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
2991 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
2994 goto err_out_free_regions;
2997 if (sizeof(dma_addr_t) > sizeof(u32)) {
2998 err = pci_set_dma_mask(pdev, DMA_64BIT_MASK);
3004 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3006 printk(KERN_ERR PFX "%s no usable DMA configuration\n",
3008 goto err_out_free_regions;
3012 /* byte swap descriptors in hardware */
3016 pci_read_config_dword(pdev, PCI_DEV_REG2, ®);
3017 reg |= PCI_REV_DESC;
3018 pci_write_config_dword(pdev, PCI_DEV_REG2, reg);
3023 hw = kmalloc(sizeof(*hw), GFP_KERNEL);
3025 printk(KERN_ERR PFX "%s: cannot allocate hardware struct\n",
3027 goto err_out_free_regions;
3030 memset(hw, 0, sizeof(*hw));
3033 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
3035 printk(KERN_ERR PFX "%s: cannot map device registers\n",
3037 goto err_out_free_hw;
3039 hw->pm_cap = pm_cap;
3041 err = sky2_reset(hw);
3043 goto err_out_iounmap;
3045 printk(KERN_INFO PFX "v%s addr 0x%lx irq %d Yukon-%s (0x%x) rev %d\n",
3046 DRV_VERSION, pci_resource_start(pdev, 0), pdev->irq,
3047 yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
3048 hw->chip_id, hw->chip_rev);
3050 dev = sky2_init_netdev(hw, 0, using_dac);
3052 goto err_out_free_pci;
3054 err = register_netdev(dev);
3056 printk(KERN_ERR PFX "%s: cannot register net device\n",
3058 goto err_out_free_netdev;
3061 sky2_show_addr(dev);
3063 if (hw->ports > 1 && (dev1 = sky2_init_netdev(hw, 1, using_dac))) {
3064 if (register_netdev(dev1) == 0)
3065 sky2_show_addr(dev1);
3067 /* Failure to register second port need not be fatal */
3068 printk(KERN_WARNING PFX
3069 "register of second port failed\n");
3075 err = request_irq(pdev->irq, sky2_intr, SA_SHIRQ, DRV_NAME, hw);
3077 printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
3078 pci_name(pdev), pdev->irq);
3079 goto err_out_unregister;
3082 hw->intr_mask = Y2_IS_BASE;
3083 sky2_write32(hw, B0_IMSK, hw->intr_mask);
3085 pci_set_drvdata(pdev, hw);
3091 unregister_netdev(dev1);
3094 unregister_netdev(dev);
3095 err_out_free_netdev:
3098 sky2_write8(hw, B0_CTST, CS_RST_SET);
3099 pci_free_consistent(hw->pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
3104 err_out_free_regions:
3105 pci_release_regions(pdev);
3106 pci_disable_device(pdev);
3111 static void __devexit sky2_remove(struct pci_dev *pdev)
3113 struct sky2_hw *hw = pci_get_drvdata(pdev);
3114 struct net_device *dev0, *dev1;
3122 unregister_netdev(dev1);
3123 unregister_netdev(dev0);
3125 sky2_write32(hw, B0_IMSK, 0);
3126 sky2_set_power_state(hw, PCI_D3hot);
3127 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
3128 sky2_write8(hw, B0_CTST, CS_RST_SET);
3129 sky2_read8(hw, B0_CTST);
3131 free_irq(pdev->irq, hw);
3132 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
3133 pci_release_regions(pdev);
3134 pci_disable_device(pdev);
3142 pci_set_drvdata(pdev, NULL);
3146 static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
3148 struct sky2_hw *hw = pci_get_drvdata(pdev);
3151 for (i = 0; i < 2; i++) {
3152 struct net_device *dev = hw->dev[i];
3155 if (!netif_running(dev))
3159 netif_device_detach(dev);
3163 return sky2_set_power_state(hw, pci_choose_state(pdev, state));
3166 static int sky2_resume(struct pci_dev *pdev)
3168 struct sky2_hw *hw = pci_get_drvdata(pdev);
3171 pci_restore_state(pdev);
3172 pci_enable_wake(pdev, PCI_D0, 0);
3173 sky2_set_power_state(hw, PCI_D0);
3177 for (i = 0; i < 2; i++) {
3178 struct net_device *dev = hw->dev[i];
3180 if (netif_running(dev)) {
3181 netif_device_attach(dev);
3190 static struct pci_driver sky2_driver = {
3192 .id_table = sky2_id_table,
3193 .probe = sky2_probe,
3194 .remove = __devexit_p(sky2_remove),
3196 .suspend = sky2_suspend,
3197 .resume = sky2_resume,
3201 static int __init sky2_init_module(void)
3203 return pci_register_driver(&sky2_driver);
3206 static void __exit sky2_cleanup_module(void)
3208 pci_unregister_driver(&sky2_driver);
3211 module_init(sky2_init_module);
3212 module_exit(sky2_cleanup_module);
3214 MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
3215 MODULE_AUTHOR("Stephen Hemminger <shemminger@osdl.org>");
3216 MODULE_LICENSE("GPL");
3217 MODULE_VERSION(DRV_VERSION);