2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
26 #include <linux/config.h>
27 #include <linux/crc32.h>
28 #include <linux/kernel.h>
29 #include <linux/version.h>
30 #include <linux/module.h>
31 #include <linux/netdevice.h>
32 #include <linux/dma-mapping.h>
33 #include <linux/etherdevice.h>
34 #include <linux/ethtool.h>
35 #include <linux/pci.h>
37 #include <linux/tcp.h>
39 #include <linux/delay.h>
40 #include <linux/workqueue.h>
41 #include <linux/if_vlan.h>
42 #include <linux/prefetch.h>
43 #include <linux/mii.h>
47 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
48 #define SKY2_VLAN_TAG_USED 1
53 #define DRV_NAME "sky2"
54 #define DRV_VERSION "0.15"
55 #define PFX DRV_NAME " "
58 * The Yukon II chipset takes 64 bit command blocks (called list elements)
59 * that are organized into three (receive, transmit, status) different rings
60 * similar to Tigon3. A transmit can require several elements;
61 * a receive requires one (or two if using 64 bit dma).
64 #define is_ec_a1(hw) \
65 unlikely((hw)->chip_id == CHIP_ID_YUKON_EC && \
66 (hw)->chip_rev == CHIP_REV_YU_EC_A1)
68 #define RX_LE_SIZE 512
69 #define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
70 #define RX_MAX_PENDING (RX_LE_SIZE/2 - 2)
71 #define RX_DEF_PENDING RX_MAX_PENDING
72 #define RX_SKB_ALIGN 8
74 #define TX_RING_SIZE 512
75 #define TX_DEF_PENDING (TX_RING_SIZE - 1)
76 #define TX_MIN_PENDING 64
77 #define MAX_SKB_TX_LE (4 + 2*MAX_SKB_FRAGS)
79 #define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
80 #define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
81 #define ETH_JUMBO_MTU 9000
82 #define TX_WATCHDOG (5 * HZ)
83 #define NAPI_WEIGHT 64
84 #define PHY_RETRIES 1000
86 static const u32 default_msg =
87 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
88 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
89 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
91 static int debug = -1; /* defaults above */
92 module_param(debug, int, 0);
93 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
95 static int copybreak __read_mostly = 256;
96 module_param(copybreak, int, 0);
97 MODULE_PARM_DESC(copybreak, "Receive copy threshold");
99 static int disable_msi = 0;
100 module_param(disable_msi, int, 0);
101 MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
103 static const struct pci_device_id sky2_id_table[] = {
104 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) },
105 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) },
106 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) },
107 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b01) },
108 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) },
109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) },
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) },
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) },
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) },
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) },
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) },
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) },
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) },
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) },
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) },
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) },
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) },
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) },
122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) },
126 MODULE_DEVICE_TABLE(pci, sky2_id_table);
128 /* Avoid conditionals by using array */
129 static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
130 static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
132 /* This driver supports yukon2 chipset only */
133 static const char *yukon2_name[] = {
135 "EC Ultra", /* 0xb4 */
136 "UNKNOWN", /* 0xb5 */
141 /* Access to external PHY */
142 static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
146 gma_write16(hw, port, GM_SMI_DATA, val);
147 gma_write16(hw, port, GM_SMI_CTRL,
148 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
150 for (i = 0; i < PHY_RETRIES; i++) {
151 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
156 printk(KERN_WARNING PFX "%s: phy write timeout\n", hw->dev[port]->name);
160 static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
164 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
165 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
167 for (i = 0; i < PHY_RETRIES; i++) {
168 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL) {
169 *val = gma_read16(hw, port, GM_SMI_DATA);
179 static u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
183 if (__gm_phy_read(hw, port, reg, &v) != 0)
184 printk(KERN_WARNING PFX "%s: phy read timeout\n", hw->dev[port]->name);
188 static int sky2_set_power_state(struct sky2_hw *hw, pci_power_t state)
195 pr_debug("sky2_set_power_state %d\n", state);
196 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
198 pci_read_config_word(hw->pdev, hw->pm_cap + PCI_PM_PMC, &power_control);
199 vaux = (sky2_read16(hw, B0_CTST) & Y2_VAUX_AVAIL) &&
200 (power_control & PCI_PM_CAP_PME_D3cold);
202 pci_read_config_word(hw->pdev, hw->pm_cap + PCI_PM_CTRL, &power_control);
204 power_control |= PCI_PM_CTRL_PME_STATUS;
205 power_control &= ~(PCI_PM_CTRL_STATE_MASK);
209 /* switch power to VCC (WA for VAUX problem) */
210 sky2_write8(hw, B0_POWER_CTRL,
211 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
213 /* disable Core Clock Division, */
214 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
216 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
217 /* enable bits are inverted */
218 sky2_write8(hw, B2_Y2_CLK_GATE,
219 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
220 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
221 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
223 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
225 /* Turn off phy power saving */
226 pci_read_config_dword(hw->pdev, PCI_DEV_REG1, ®1);
227 reg1 &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
229 /* looks like this XL is back asswards .. */
230 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1) {
231 reg1 |= PCI_Y2_PHY1_COMA;
233 reg1 |= PCI_Y2_PHY2_COMA;
236 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
237 pci_write_config_dword(hw->pdev, PCI_DEV_REG3, 0);
238 pci_read_config_dword(hw->pdev, PCI_DEV_REG4, ®1);
239 reg1 &= P_ASPM_CONTROL_MSK;
240 pci_write_config_dword(hw->pdev, PCI_DEV_REG4, reg1);
241 pci_write_config_dword(hw->pdev, PCI_DEV_REG5, 0);
244 pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg1);
250 /* Turn on phy power saving */
251 pci_read_config_dword(hw->pdev, PCI_DEV_REG1, ®1);
252 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
253 reg1 &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
255 reg1 |= (PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
256 pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg1);
258 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
259 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
261 /* enable bits are inverted */
262 sky2_write8(hw, B2_Y2_CLK_GATE,
263 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
264 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
265 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
267 /* switch power to VAUX */
268 if (vaux && state != PCI_D3cold)
269 sky2_write8(hw, B0_POWER_CTRL,
270 (PC_VAUX_ENA | PC_VCC_ENA |
271 PC_VAUX_ON | PC_VCC_OFF));
274 printk(KERN_ERR PFX "Unknown power state %d\n", state);
278 pci_write_config_byte(hw->pdev, hw->pm_cap + PCI_PM_CTRL, power_control);
279 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
283 static void sky2_phy_reset(struct sky2_hw *hw, unsigned port)
287 /* disable all GMAC IRQ's */
288 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
289 /* disable PHY IRQs */
290 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
292 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
293 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
294 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
295 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
297 reg = gma_read16(hw, port, GM_RX_CTRL);
298 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
299 gma_write16(hw, port, GM_RX_CTRL, reg);
302 static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
304 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
305 u16 ctrl, ct1000, adv, pg, ledctrl, ledover;
307 if (sky2->autoneg == AUTONEG_ENABLE && hw->chip_id != CHIP_ID_YUKON_XL) {
308 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
310 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
312 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
314 if (hw->chip_id == CHIP_ID_YUKON_EC)
315 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
317 ectrl |= PHY_M_EC_M_DSC(2) | PHY_M_EC_S_DSC(3);
319 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
322 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
324 if (hw->chip_id == CHIP_ID_YUKON_FE) {
325 /* enable automatic crossover */
326 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
328 /* disable energy detect */
329 ctrl &= ~PHY_M_PC_EN_DET_MSK;
331 /* enable automatic crossover */
332 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
334 if (sky2->autoneg == AUTONEG_ENABLE &&
335 hw->chip_id == CHIP_ID_YUKON_XL) {
336 ctrl &= ~PHY_M_PC_DSC_MSK;
337 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
340 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
342 /* workaround for deviation #4.88 (CRC errors) */
343 /* disable Automatic Crossover */
345 ctrl &= ~PHY_M_PC_MDIX_MSK;
346 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
348 if (hw->chip_id == CHIP_ID_YUKON_XL) {
349 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
350 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
351 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
352 ctrl &= ~PHY_M_MAC_MD_MSK;
353 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
354 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
356 /* select page 1 to access Fiber registers */
357 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
361 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
362 if (sky2->autoneg == AUTONEG_DISABLE)
367 ctrl |= PHY_CT_RESET;
368 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
374 if (sky2->autoneg == AUTONEG_ENABLE) {
376 if (sky2->advertising & ADVERTISED_1000baseT_Full)
377 ct1000 |= PHY_M_1000C_AFD;
378 if (sky2->advertising & ADVERTISED_1000baseT_Half)
379 ct1000 |= PHY_M_1000C_AHD;
380 if (sky2->advertising & ADVERTISED_100baseT_Full)
381 adv |= PHY_M_AN_100_FD;
382 if (sky2->advertising & ADVERTISED_100baseT_Half)
383 adv |= PHY_M_AN_100_HD;
384 if (sky2->advertising & ADVERTISED_10baseT_Full)
385 adv |= PHY_M_AN_10_FD;
386 if (sky2->advertising & ADVERTISED_10baseT_Half)
387 adv |= PHY_M_AN_10_HD;
388 } else /* special defines for FIBER (88E1011S only) */
389 adv |= PHY_M_AN_1000X_AHD | PHY_M_AN_1000X_AFD;
391 /* Set Flow-control capabilities */
392 if (sky2->tx_pause && sky2->rx_pause)
393 adv |= PHY_AN_PAUSE_CAP; /* symmetric */
394 else if (sky2->rx_pause && !sky2->tx_pause)
395 adv |= PHY_AN_PAUSE_ASYM | PHY_AN_PAUSE_CAP;
396 else if (!sky2->rx_pause && sky2->tx_pause)
397 adv |= PHY_AN_PAUSE_ASYM; /* local */
399 /* Restart Auto-negotiation */
400 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
402 /* forced speed/duplex settings */
403 ct1000 = PHY_M_1000C_MSE;
405 if (sky2->duplex == DUPLEX_FULL)
406 ctrl |= PHY_CT_DUP_MD;
408 switch (sky2->speed) {
410 ctrl |= PHY_CT_SP1000;
413 ctrl |= PHY_CT_SP100;
417 ctrl |= PHY_CT_RESET;
420 if (hw->chip_id != CHIP_ID_YUKON_FE)
421 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
423 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
424 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
426 /* Setup Phy LED's */
427 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
430 switch (hw->chip_id) {
431 case CHIP_ID_YUKON_FE:
432 /* on 88E3082 these bits are at 11..9 (shifted left) */
433 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
435 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
437 /* delete ACT LED control bits */
438 ctrl &= ~PHY_M_FELP_LED1_MSK;
439 /* change ACT LED control to blink mode */
440 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
441 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
444 case CHIP_ID_YUKON_XL:
445 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
447 /* select page 3 to access LED control register */
448 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
450 /* set LED Function Control register */
451 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
452 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
453 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
454 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
456 /* set Polarity Control register */
457 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
458 (PHY_M_POLC_LS1_P_MIX(4) |
459 PHY_M_POLC_IS0_P_MIX(4) |
460 PHY_M_POLC_LOS_CTRL(2) |
461 PHY_M_POLC_INIT_CTRL(2) |
462 PHY_M_POLC_STA1_CTRL(2) |
463 PHY_M_POLC_STA0_CTRL(2)));
465 /* restore page register */
466 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
470 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
471 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
472 /* turn off the Rx LED (LED_RX) */
473 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
476 if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev >= 2) {
477 /* apply fixes in PHY AFE */
478 gm_phy_write(hw, port, 22, 255);
479 /* increase differential signal amplitude in 10BASE-T */
480 gm_phy_write(hw, port, 24, 0xaa99);
481 gm_phy_write(hw, port, 23, 0x2011);
483 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
484 gm_phy_write(hw, port, 24, 0xa204);
485 gm_phy_write(hw, port, 23, 0x2002);
487 /* set page register to 0 */
488 gm_phy_write(hw, port, 22, 0);
490 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
492 if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
493 /* turn on 100 Mbps LED (LED_LINK100) */
494 ledover |= PHY_M_LED_MO_100(MO_LED_ON);
498 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
501 /* Enable phy interrupt on auto-negotiation complete (or link up) */
502 if (sky2->autoneg == AUTONEG_ENABLE)
503 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
505 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
508 /* Force a renegotiation */
509 static void sky2_phy_reinit(struct sky2_port *sky2)
511 down(&sky2->phy_sema);
512 sky2_phy_init(sky2->hw, sky2->port);
516 static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
518 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
521 const u8 *addr = hw->dev[port]->dev_addr;
523 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
524 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR|GPC_ENA_PAUSE);
526 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
528 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
529 /* WA DEV_472 -- looks like crossed wires on port 2 */
530 /* clear GMAC 1 Control reset */
531 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
533 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
534 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
535 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
536 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
537 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
540 if (sky2->autoneg == AUTONEG_DISABLE) {
541 reg = gma_read16(hw, port, GM_GP_CTRL);
542 reg |= GM_GPCR_AU_ALL_DIS;
543 gma_write16(hw, port, GM_GP_CTRL, reg);
544 gma_read16(hw, port, GM_GP_CTRL);
546 switch (sky2->speed) {
548 reg &= ~GM_GPCR_SPEED_100;
549 reg |= GM_GPCR_SPEED_1000;
552 reg &= ~GM_GPCR_SPEED_1000;
553 reg |= GM_GPCR_SPEED_100;
556 reg &= ~(GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100);
560 if (sky2->duplex == DUPLEX_FULL)
561 reg |= GM_GPCR_DUP_FULL;
563 reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL;
565 if (!sky2->tx_pause && !sky2->rx_pause) {
566 sky2_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
568 GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
569 } else if (sky2->tx_pause && !sky2->rx_pause) {
570 /* disable Rx flow-control */
571 reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
574 gma_write16(hw, port, GM_GP_CTRL, reg);
576 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
578 down(&sky2->phy_sema);
579 sky2_phy_init(hw, port);
583 reg = gma_read16(hw, port, GM_PHY_ADDR);
584 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
586 for (i = 0; i < GM_MIB_CNT_SIZE; i++)
587 gma_read16(hw, port, GM_MIB_CNT_BASE + 8 * i);
588 gma_write16(hw, port, GM_PHY_ADDR, reg);
590 /* transmit control */
591 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
593 /* receive control reg: unicast + multicast + no FCS */
594 gma_write16(hw, port, GM_RX_CTRL,
595 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
597 /* transmit flow control */
598 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
600 /* transmit parameter */
601 gma_write16(hw, port, GM_TX_PARAM,
602 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
603 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
604 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
605 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
607 /* serial mode register */
608 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
609 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
611 if (hw->dev[port]->mtu > ETH_DATA_LEN)
612 reg |= GM_SMOD_JUMBO_ENA;
614 gma_write16(hw, port, GM_SERIAL_MODE, reg);
616 /* virtual address for data */
617 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
619 /* physical address: used for pause frames */
620 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
622 /* ignore counter overflows */
623 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
624 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
625 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
627 /* Configure Rx MAC FIFO */
628 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
629 sky2_write16(hw, SK_REG(port, RX_GMF_CTRL_T),
632 /* Flush Rx MAC FIFO on any flow control or error */
633 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
635 /* Set threshold to 0xa (64 bytes)
636 * ASF disabled so no need to do WA dev #4.30
638 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF);
640 /* Configure Tx MAC FIFO */
641 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
642 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
644 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
645 sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8);
646 sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
647 if (hw->dev[port]->mtu > ETH_DATA_LEN) {
648 /* set Tx GMAC FIFO Almost Empty Threshold */
649 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR), 0x180);
650 /* Disable Store & Forward mode for TX */
651 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);
657 /* Assign Ram Buffer allocation.
658 * start and end are in units of 4k bytes
659 * ram registers are in units of 64bit words
661 static void sky2_ramset(struct sky2_hw *hw, u16 q, u8 startk, u8 endk)
665 start = startk * 4096/8;
666 end = (endk * 4096/8) - 1;
668 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
669 sky2_write32(hw, RB_ADDR(q, RB_START), start);
670 sky2_write32(hw, RB_ADDR(q, RB_END), end);
671 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
672 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
674 if (q == Q_R1 || q == Q_R2) {
675 u32 space = (endk - startk) * 4096/8;
676 u32 tp = space - space/4;
678 /* On receive queue's set the thresholds
679 * give receiver priority when > 3/4 full
680 * send pause when down to 2K
682 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
683 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
686 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
687 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
689 /* Enable store & forward on Tx queue's because
690 * Tx FIFO is only 1K on Yukon
692 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
695 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
696 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
699 /* Setup Bus Memory Interface */
700 static void sky2_qset(struct sky2_hw *hw, u16 q)
702 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
703 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
704 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
705 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
708 /* Setup prefetch unit registers. This is the interface between
709 * hardware and driver list elements
711 static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
714 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
715 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
716 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32);
717 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr);
718 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
719 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
721 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
724 static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2)
726 struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod;
728 sky2->tx_prod = (sky2->tx_prod + 1) % TX_RING_SIZE;
733 * This is a workaround code taken from SysKonnect sk98lin driver
734 * to deal with chip bug on Yukon EC rev 0 in the wraparound case.
736 static void sky2_put_idx(struct sky2_hw *hw, unsigned q,
737 u16 idx, u16 *last, u16 size)
740 if (is_ec_a1(hw) && idx < *last) {
741 u16 hwget = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));
744 /* Start prefetching again */
745 sky2_write8(hw, Y2_QADDR(q, PREF_UNIT_FIFO_WM), 0xe0);
749 if (hwget == size - 1) {
750 /* set watermark to one list element */
751 sky2_write8(hw, Y2_QADDR(q, PREF_UNIT_FIFO_WM), 8);
753 /* set put index to first list element */
754 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), 0);
755 } else /* have hardware go to end of list */
756 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX),
760 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
767 static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
769 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
770 sky2->rx_put = (sky2->rx_put + 1) % RX_LE_SIZE;
774 /* Return high part of DMA address (could be 32 or 64 bit) */
775 static inline u32 high32(dma_addr_t a)
777 return sizeof(a) > sizeof(u32) ? (a >> 16) >> 16 : 0;
780 /* Build description to hardware about buffer */
781 static void sky2_rx_add(struct sky2_port *sky2, dma_addr_t map)
783 struct sky2_rx_le *le;
784 u32 hi = high32(map);
785 u16 len = sky2->rx_bufsize;
787 if (sky2->rx_addr64 != hi) {
788 le = sky2_next_rx(sky2);
789 le->addr = cpu_to_le32(hi);
791 le->opcode = OP_ADDR64 | HW_OWNER;
792 sky2->rx_addr64 = high32(map + len);
795 le = sky2_next_rx(sky2);
796 le->addr = cpu_to_le32((u32) map);
797 le->length = cpu_to_le16(len);
799 le->opcode = OP_PACKET | HW_OWNER;
803 /* Tell chip where to start receive checksum.
804 * Actually has two checksums, but set both same to avoid possible byte
807 static void rx_set_checksum(struct sky2_port *sky2)
809 struct sky2_rx_le *le;
811 le = sky2_next_rx(sky2);
812 le->addr = (ETH_HLEN << 16) | ETH_HLEN;
814 le->opcode = OP_TCPSTART | HW_OWNER;
816 sky2_write32(sky2->hw,
817 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
818 sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
823 * The RX Stop command will not work for Yukon-2 if the BMU does not
824 * reach the end of packet and since we can't make sure that we have
825 * incoming data, we must reset the BMU while it is not doing a DMA
826 * transfer. Since it is possible that the RX path is still active,
827 * the RX RAM buffer will be stopped first, so any possible incoming
828 * data will not trigger a DMA. After the RAM buffer is stopped, the
829 * BMU is polled until any DMA in progress is ended and only then it
832 static void sky2_rx_stop(struct sky2_port *sky2)
834 struct sky2_hw *hw = sky2->hw;
835 unsigned rxq = rxqaddr[sky2->port];
838 /* disable the RAM Buffer receive queue */
839 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
841 for (i = 0; i < 0xffff; i++)
842 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
843 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
846 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
849 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
851 /* reset the Rx prefetch unit */
852 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
855 /* Clean out receive buffer area, assumes receiver hardware stopped */
856 static void sky2_rx_clean(struct sky2_port *sky2)
860 memset(sky2->rx_le, 0, RX_LE_BYTES);
861 for (i = 0; i < sky2->rx_pending; i++) {
862 struct ring_info *re = sky2->rx_ring + i;
865 pci_unmap_single(sky2->hw->pdev,
866 re->mapaddr, sky2->rx_bufsize,
874 /* Basic MII support */
875 static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
877 struct mii_ioctl_data *data = if_mii(ifr);
878 struct sky2_port *sky2 = netdev_priv(dev);
879 struct sky2_hw *hw = sky2->hw;
880 int err = -EOPNOTSUPP;
882 if (!netif_running(dev))
883 return -ENODEV; /* Phy still in reset */
887 data->phy_id = PHY_ADDR_MARV;
893 down(&sky2->phy_sema);
894 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
902 if (!capable(CAP_NET_ADMIN))
905 down(&sky2->phy_sema);
906 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
914 #ifdef SKY2_VLAN_TAG_USED
915 static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
917 struct sky2_port *sky2 = netdev_priv(dev);
918 struct sky2_hw *hw = sky2->hw;
919 u16 port = sky2->port;
921 spin_lock_bh(&sky2->tx_lock);
923 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_ON);
924 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_ON);
927 spin_unlock_bh(&sky2->tx_lock);
930 static void sky2_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
932 struct sky2_port *sky2 = netdev_priv(dev);
933 struct sky2_hw *hw = sky2->hw;
934 u16 port = sky2->port;
936 spin_lock_bh(&sky2->tx_lock);
938 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_OFF);
939 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_OFF);
941 sky2->vlgrp->vlan_devices[vid] = NULL;
943 spin_unlock_bh(&sky2->tx_lock);
948 * It appears the hardware has a bug in the FIFO logic that
949 * cause it to hang if the FIFO gets overrun and the receive buffer
950 * is not aligned. ALso alloc_skb() won't align properly if slab
951 * debugging is enabled.
953 static inline struct sk_buff *sky2_alloc_skb(unsigned int size, gfp_t gfp_mask)
957 skb = alloc_skb(size + RX_SKB_ALIGN, gfp_mask);
959 unsigned long p = (unsigned long) skb->data;
961 ((p + RX_SKB_ALIGN - 1) & ~(RX_SKB_ALIGN - 1)) - p);
968 * Allocate and setup receiver buffer pool.
969 * In case of 64 bit dma, there are 2X as many list elements
970 * available as ring entries
971 * and need to reserve one list element so we don't wrap around.
973 static int sky2_rx_start(struct sky2_port *sky2)
975 struct sky2_hw *hw = sky2->hw;
976 unsigned rxq = rxqaddr[sky2->port];
979 sky2->rx_put = sky2->rx_next = 0;
982 if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev >= 2) {
983 /* MAC Rx RAM Read is controlled by hardware */
984 sky2_write32(hw, Q_ADDR(rxq, Q_F), F_M_RX_RAM_DIS);
987 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
989 rx_set_checksum(sky2);
990 for (i = 0; i < sky2->rx_pending; i++) {
991 struct ring_info *re = sky2->rx_ring + i;
993 re->skb = sky2_alloc_skb(sky2->rx_bufsize, GFP_KERNEL);
997 re->mapaddr = pci_map_single(hw->pdev, re->skb->data,
998 sky2->rx_bufsize, PCI_DMA_FROMDEVICE);
999 sky2_rx_add(sky2, re->mapaddr);
1002 /* Tell chip about available buffers */
1003 sky2_write16(hw, Y2_QADDR(rxq, PREF_UNIT_PUT_IDX), sky2->rx_put);
1004 sky2->rx_last_put = sky2_read16(hw, Y2_QADDR(rxq, PREF_UNIT_PUT_IDX));
1007 sky2_rx_clean(sky2);
1011 /* Bring up network interface. */
1012 static int sky2_up(struct net_device *dev)
1014 struct sky2_port *sky2 = netdev_priv(dev);
1015 struct sky2_hw *hw = sky2->hw;
1016 unsigned port = sky2->port;
1017 u32 ramsize, rxspace;
1020 if (netif_msg_ifup(sky2))
1021 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
1023 /* must be power of 2 */
1024 sky2->tx_le = pci_alloc_consistent(hw->pdev,
1026 sizeof(struct sky2_tx_le),
1031 sky2->tx_ring = kcalloc(TX_RING_SIZE, sizeof(struct tx_ring_info),
1035 sky2->tx_prod = sky2->tx_cons = 0;
1037 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1041 memset(sky2->rx_le, 0, RX_LE_BYTES);
1043 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct ring_info),
1048 sky2_mac_init(hw, port);
1050 /* Determine available ram buffer space (in 4K blocks).
1051 * Note: not sure about the FE setting below yet
1053 if (hw->chip_id == CHIP_ID_YUKON_FE)
1056 ramsize = sky2_read8(hw, B2_E_0);
1058 /* Give transmitter one third (rounded up) */
1059 rxspace = ramsize - (ramsize + 2) / 3;
1061 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1062 sky2_ramset(hw, txqaddr[port], rxspace, ramsize);
1064 /* Make sure SyncQ is disabled */
1065 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1068 sky2_qset(hw, txqaddr[port]);
1070 /* Set almost empty threshold */
1071 if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev == 1)
1072 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), 0x1a0);
1074 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1077 err = sky2_rx_start(sky2);
1081 /* Enable interrupts from phy/mac for port */
1082 hw->intr_mask |= (port == 0) ? Y2_IS_PORT_1 : Y2_IS_PORT_2;
1083 sky2_write32(hw, B0_IMSK, hw->intr_mask);
1088 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1089 sky2->rx_le, sky2->rx_le_map);
1093 pci_free_consistent(hw->pdev,
1094 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1095 sky2->tx_le, sky2->tx_le_map);
1098 kfree(sky2->tx_ring);
1099 kfree(sky2->rx_ring);
1101 sky2->tx_ring = NULL;
1102 sky2->rx_ring = NULL;
1106 /* Modular subtraction in ring */
1107 static inline int tx_dist(unsigned tail, unsigned head)
1109 return (head - tail) % TX_RING_SIZE;
1112 /* Number of list elements available for next tx */
1113 static inline int tx_avail(const struct sky2_port *sky2)
1115 return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod);
1118 /* Estimate of number of transmit list elements required */
1119 static unsigned tx_le_req(const struct sk_buff *skb)
1123 count = sizeof(dma_addr_t) / sizeof(u32);
1124 count += skb_shinfo(skb)->nr_frags * count;
1126 if (skb_shinfo(skb)->tso_size)
1129 if (skb->ip_summed == CHECKSUM_HW)
1136 * Put one packet in ring for transmit.
1137 * A single packet can generate multiple list elements, and
1138 * the number of ring elements will probably be less than the number
1139 * of list elements used.
1141 * No BH disabling for tx_lock here (like tg3)
1143 static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
1145 struct sky2_port *sky2 = netdev_priv(dev);
1146 struct sky2_hw *hw = sky2->hw;
1147 struct sky2_tx_le *le = NULL;
1148 struct tx_ring_info *re;
1155 /* No BH disabling for tx_lock here. We are running in BH disabled
1156 * context and TX reclaim runs via poll inside of a software
1157 * interrupt, and no related locks in IRQ processing.
1159 if (!spin_trylock(&sky2->tx_lock))
1160 return NETDEV_TX_LOCKED;
1162 if (unlikely(tx_avail(sky2) < tx_le_req(skb))) {
1163 /* There is a known but harmless race with lockless tx
1164 * and netif_stop_queue.
1166 if (!netif_queue_stopped(dev)) {
1167 netif_stop_queue(dev);
1168 if (net_ratelimit())
1169 printk(KERN_WARNING PFX "%s: ring full when queue awake!\n",
1172 spin_unlock(&sky2->tx_lock);
1174 return NETDEV_TX_BUSY;
1177 if (unlikely(netif_msg_tx_queued(sky2)))
1178 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
1179 dev->name, sky2->tx_prod, skb->len);
1181 len = skb_headlen(skb);
1182 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
1183 addr64 = high32(mapping);
1185 re = sky2->tx_ring + sky2->tx_prod;
1187 /* Send high bits if changed or crosses boundary */
1188 if (addr64 != sky2->tx_addr64 || high32(mapping + len) != sky2->tx_addr64) {
1189 le = get_tx_le(sky2);
1190 le->tx.addr = cpu_to_le32(addr64);
1192 le->opcode = OP_ADDR64 | HW_OWNER;
1193 sky2->tx_addr64 = high32(mapping + len);
1196 /* Check for TCP Segmentation Offload */
1197 mss = skb_shinfo(skb)->tso_size;
1199 /* just drop the packet if non-linear expansion fails */
1200 if (skb_header_cloned(skb) &&
1201 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
1202 dev_kfree_skb_any(skb);
1206 mss += ((skb->h.th->doff - 5) * 4); /* TCP options */
1207 mss += (skb->nh.iph->ihl * 4) + sizeof(struct tcphdr);
1211 if (mss != sky2->tx_last_mss) {
1212 le = get_tx_le(sky2);
1213 le->tx.tso.size = cpu_to_le16(mss);
1214 le->tx.tso.rsvd = 0;
1215 le->opcode = OP_LRGLEN | HW_OWNER;
1217 sky2->tx_last_mss = mss;
1221 #ifdef SKY2_VLAN_TAG_USED
1222 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1223 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1225 le = get_tx_le(sky2);
1227 le->opcode = OP_VLAN|HW_OWNER;
1230 le->opcode |= OP_VLAN;
1231 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1236 /* Handle TCP checksum offload */
1237 if (skb->ip_summed == CHECKSUM_HW) {
1238 u16 hdr = skb->h.raw - skb->data;
1239 u16 offset = hdr + skb->csum;
1241 ctrl = CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1242 if (skb->nh.iph->protocol == IPPROTO_UDP)
1245 le = get_tx_le(sky2);
1246 le->tx.csum.start = cpu_to_le16(hdr);
1247 le->tx.csum.offset = cpu_to_le16(offset);
1248 le->length = 0; /* initial checksum value */
1249 le->ctrl = 1; /* one packet */
1250 le->opcode = OP_TCPLISW | HW_OWNER;
1253 le = get_tx_le(sky2);
1254 le->tx.addr = cpu_to_le32((u32) mapping);
1255 le->length = cpu_to_le16(len);
1257 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
1259 /* Record the transmit mapping info */
1261 pci_unmap_addr_set(re, mapaddr, mapping);
1263 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1264 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1265 struct tx_ring_info *fre;
1267 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1268 frag->size, PCI_DMA_TODEVICE);
1269 addr64 = high32(mapping);
1270 if (addr64 != sky2->tx_addr64) {
1271 le = get_tx_le(sky2);
1272 le->tx.addr = cpu_to_le32(addr64);
1274 le->opcode = OP_ADDR64 | HW_OWNER;
1275 sky2->tx_addr64 = addr64;
1278 le = get_tx_le(sky2);
1279 le->tx.addr = cpu_to_le32((u32) mapping);
1280 le->length = cpu_to_le16(frag->size);
1282 le->opcode = OP_BUFFER | HW_OWNER;
1285 + ((re - sky2->tx_ring) + i + 1) % TX_RING_SIZE;
1286 pci_unmap_addr_set(fre, mapaddr, mapping);
1289 re->idx = sky2->tx_prod;
1292 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod,
1293 &sky2->tx_last_put, TX_RING_SIZE);
1295 if (tx_avail(sky2) <= MAX_SKB_TX_LE)
1296 netif_stop_queue(dev);
1299 spin_unlock(&sky2->tx_lock);
1301 dev->trans_start = jiffies;
1302 return NETDEV_TX_OK;
1306 * Free ring elements from starting at tx_cons until "done"
1308 * NB: the hardware will tell us about partial completion of multi-part
1309 * buffers; these are deferred until completion.
1311 static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
1313 struct net_device *dev = sky2->netdev;
1314 struct pci_dev *pdev = sky2->hw->pdev;
1318 BUG_ON(done >= TX_RING_SIZE);
1320 if (unlikely(netif_msg_tx_done(sky2)))
1321 printk(KERN_DEBUG "%s: tx done, up to %u\n",
1324 for (put = sky2->tx_cons; put != done; put = nxt) {
1325 struct tx_ring_info *re = sky2->tx_ring + put;
1326 struct sk_buff *skb = re->skb;
1329 BUG_ON(nxt >= TX_RING_SIZE);
1330 prefetch(sky2->tx_ring + nxt);
1332 /* Check for partial status */
1333 if (tx_dist(put, done) < tx_dist(put, nxt))
1337 pci_unmap_single(pdev, pci_unmap_addr(re, mapaddr),
1338 skb_headlen(skb), PCI_DMA_TODEVICE);
1340 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1341 struct tx_ring_info *fre;
1342 fre = sky2->tx_ring + (put + i + 1) % TX_RING_SIZE;
1343 pci_unmap_page(pdev, pci_unmap_addr(fre, mapaddr),
1344 skb_shinfo(skb)->frags[i].size,
1348 dev_kfree_skb_any(skb);
1351 sky2->tx_cons = put;
1352 if (netif_queue_stopped(dev) && tx_avail(sky2) > MAX_SKB_TX_LE)
1353 netif_wake_queue(dev);
1356 /* Cleanup all untransmitted buffers, assume transmitter not running */
1357 static void sky2_tx_clean(struct sky2_port *sky2)
1359 spin_lock_bh(&sky2->tx_lock);
1360 sky2_tx_complete(sky2, sky2->tx_prod);
1361 spin_unlock_bh(&sky2->tx_lock);
1364 /* Network shutdown */
1365 static int sky2_down(struct net_device *dev)
1367 struct sky2_port *sky2 = netdev_priv(dev);
1368 struct sky2_hw *hw = sky2->hw;
1369 unsigned port = sky2->port;
1372 /* Never really got started! */
1376 if (netif_msg_ifdown(sky2))
1377 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1379 /* Stop more packets from being queued */
1380 netif_stop_queue(dev);
1382 /* Disable port IRQ */
1383 local_irq_disable();
1384 hw->intr_mask &= ~((sky2->port == 0) ? Y2_IS_IRQ_PHY1 : Y2_IS_IRQ_PHY2);
1385 sky2_write32(hw, B0_IMSK, hw->intr_mask);
1388 flush_scheduled_work();
1390 sky2_phy_reset(hw, port);
1392 /* Stop transmitter */
1393 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1394 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1396 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
1397 RB_RST_SET | RB_DIS_OP_MD);
1399 ctrl = gma_read16(hw, port, GM_GP_CTRL);
1400 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
1401 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1403 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1405 /* Workaround shared GMAC reset */
1406 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
1407 && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
1408 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1410 /* Disable Force Sync bit and Enable Alloc bit */
1411 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1412 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1414 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1415 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1416 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1418 /* Reset the PCI FIFO of the async Tx queue */
1419 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1420 BMU_RST_SET | BMU_FIFO_RST);
1422 /* Reset the Tx prefetch units */
1423 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1426 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1430 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1431 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1433 /* turn off LED's */
1434 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
1436 synchronize_irq(hw->pdev->irq);
1438 sky2_tx_clean(sky2);
1439 sky2_rx_clean(sky2);
1441 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1442 sky2->rx_le, sky2->rx_le_map);
1443 kfree(sky2->rx_ring);
1445 pci_free_consistent(hw->pdev,
1446 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1447 sky2->tx_le, sky2->tx_le_map);
1448 kfree(sky2->tx_ring);
1453 sky2->rx_ring = NULL;
1454 sky2->tx_ring = NULL;
1459 static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1464 if (hw->chip_id == CHIP_ID_YUKON_FE)
1465 return (aux & PHY_M_PS_SPEED_100) ? SPEED_100 : SPEED_10;
1467 switch (aux & PHY_M_PS_SPEED_MSK) {
1468 case PHY_M_PS_SPEED_1000:
1470 case PHY_M_PS_SPEED_100:
1477 static void sky2_link_up(struct sky2_port *sky2)
1479 struct sky2_hw *hw = sky2->hw;
1480 unsigned port = sky2->port;
1483 /* Enable Transmit FIFO Underrun */
1484 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
1486 reg = gma_read16(hw, port, GM_GP_CTRL);
1487 if (sky2->autoneg == AUTONEG_DISABLE) {
1488 reg |= GM_GPCR_AU_ALL_DIS;
1490 /* Is write/read necessary? Copied from sky2_mac_init */
1491 gma_write16(hw, port, GM_GP_CTRL, reg);
1492 gma_read16(hw, port, GM_GP_CTRL);
1494 switch (sky2->speed) {
1496 reg &= ~GM_GPCR_SPEED_100;
1497 reg |= GM_GPCR_SPEED_1000;
1500 reg &= ~GM_GPCR_SPEED_1000;
1501 reg |= GM_GPCR_SPEED_100;
1504 reg &= ~(GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100);
1508 reg &= ~GM_GPCR_AU_ALL_DIS;
1510 if (sky2->duplex == DUPLEX_FULL || sky2->autoneg == AUTONEG_ENABLE)
1511 reg |= GM_GPCR_DUP_FULL;
1514 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1515 gma_write16(hw, port, GM_GP_CTRL, reg);
1516 gma_read16(hw, port, GM_GP_CTRL);
1518 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1520 netif_carrier_on(sky2->netdev);
1521 netif_wake_queue(sky2->netdev);
1523 /* Turn on link LED */
1524 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
1525 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
1527 if (hw->chip_id == CHIP_ID_YUKON_XL) {
1528 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
1530 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
1531 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
1532 PHY_M_LEDC_INIT_CTRL(sky2->speed ==
1534 PHY_M_LEDC_STA1_CTRL(sky2->speed ==
1535 SPEED_100 ? 7 : 0) |
1536 PHY_M_LEDC_STA0_CTRL(sky2->speed ==
1537 SPEED_1000 ? 7 : 0));
1538 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
1541 if (netif_msg_link(sky2))
1542 printk(KERN_INFO PFX
1543 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
1544 sky2->netdev->name, sky2->speed,
1545 sky2->duplex == DUPLEX_FULL ? "full" : "half",
1546 (sky2->tx_pause && sky2->rx_pause) ? "both" :
1547 sky2->tx_pause ? "tx" : sky2->rx_pause ? "rx" : "none");
1550 static void sky2_link_down(struct sky2_port *sky2)
1552 struct sky2_hw *hw = sky2->hw;
1553 unsigned port = sky2->port;
1556 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1558 reg = gma_read16(hw, port, GM_GP_CTRL);
1559 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1560 gma_write16(hw, port, GM_GP_CTRL, reg);
1561 gma_read16(hw, port, GM_GP_CTRL); /* PCI post */
1563 if (sky2->rx_pause && !sky2->tx_pause) {
1564 /* restore Asymmetric Pause bit */
1565 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,
1566 gm_phy_read(hw, port, PHY_MARV_AUNE_ADV)
1570 netif_carrier_off(sky2->netdev);
1571 netif_stop_queue(sky2->netdev);
1573 /* Turn on link LED */
1574 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
1576 if (netif_msg_link(sky2))
1577 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
1578 sky2_phy_init(hw, port);
1581 static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
1583 struct sky2_hw *hw = sky2->hw;
1584 unsigned port = sky2->port;
1587 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
1589 if (lpa & PHY_M_AN_RF) {
1590 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
1594 if (hw->chip_id != CHIP_ID_YUKON_FE &&
1595 gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) {
1596 printk(KERN_ERR PFX "%s: master/slave fault",
1597 sky2->netdev->name);
1601 if (!(aux & PHY_M_PS_SPDUP_RES)) {
1602 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
1603 sky2->netdev->name);
1607 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1609 sky2->speed = sky2_phy_speed(hw, aux);
1611 /* Pause bits are offset (9..8) */
1612 if (hw->chip_id == CHIP_ID_YUKON_XL)
1615 sky2->rx_pause = (aux & PHY_M_PS_RX_P_EN) != 0;
1616 sky2->tx_pause = (aux & PHY_M_PS_TX_P_EN) != 0;
1618 if ((sky2->tx_pause || sky2->rx_pause)
1619 && !(sky2->speed < SPEED_1000 && sky2->duplex == DUPLEX_HALF))
1620 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
1622 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1628 * Interrupt from PHY are handled outside of interrupt context
1629 * because accessing phy registers requires spin wait which might
1630 * cause excess interrupt latency.
1632 static void sky2_phy_task(void *arg)
1634 struct sky2_port *sky2 = arg;
1635 struct sky2_hw *hw = sky2->hw;
1636 u16 istatus, phystat;
1638 down(&sky2->phy_sema);
1639 istatus = gm_phy_read(hw, sky2->port, PHY_MARV_INT_STAT);
1640 phystat = gm_phy_read(hw, sky2->port, PHY_MARV_PHY_STAT);
1642 if (netif_msg_intr(sky2))
1643 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
1644 sky2->netdev->name, istatus, phystat);
1646 if (istatus & PHY_M_IS_AN_COMPL) {
1647 if (sky2_autoneg_done(sky2, phystat) == 0)
1652 if (istatus & PHY_M_IS_LSP_CHANGE)
1653 sky2->speed = sky2_phy_speed(hw, phystat);
1655 if (istatus & PHY_M_IS_DUP_CHANGE)
1657 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1659 if (istatus & PHY_M_IS_LST_CHANGE) {
1660 if (phystat & PHY_M_PS_LINK_UP)
1663 sky2_link_down(sky2);
1666 up(&sky2->phy_sema);
1668 local_irq_disable();
1669 hw->intr_mask |= (sky2->port == 0) ? Y2_IS_IRQ_PHY1 : Y2_IS_IRQ_PHY2;
1670 sky2_write32(hw, B0_IMSK, hw->intr_mask);
1675 /* Transmit timeout is only called if we are running, carries is up
1676 * and tx queue is full (stopped).
1678 static void sky2_tx_timeout(struct net_device *dev)
1680 struct sky2_port *sky2 = netdev_priv(dev);
1681 struct sky2_hw *hw = sky2->hw;
1682 unsigned txq = txqaddr[sky2->port];
1685 /* Maybe we just missed an status interrupt */
1686 spin_lock(&sky2->tx_lock);
1687 ridx = sky2_read16(hw,
1688 sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX);
1689 sky2_tx_complete(sky2, ridx);
1690 spin_unlock(&sky2->tx_lock);
1692 if (!netif_queue_stopped(dev)) {
1693 if (net_ratelimit())
1694 pr_info(PFX "transmit interrupt missed? recovered\n");
1698 if (netif_msg_timer(sky2))
1699 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
1701 sky2_write32(hw, Q_ADDR(txq, Q_CSR), BMU_STOP);
1702 sky2_write32(hw, Y2_QADDR(txq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
1704 sky2_tx_clean(sky2);
1707 sky2_prefetch_init(hw, txq, sky2->tx_le_map, TX_RING_SIZE - 1);
1711 #define roundup(x, y) ((((x)+((y)-1))/(y))*(y))
1712 /* Want receive buffer size to be multiple of 64 bits, and incl room for vlan */
1713 static inline unsigned sky2_buf_size(int mtu)
1715 return roundup(mtu + ETH_HLEN + 4, 8);
1718 static int sky2_change_mtu(struct net_device *dev, int new_mtu)
1720 struct sky2_port *sky2 = netdev_priv(dev);
1721 struct sky2_hw *hw = sky2->hw;
1725 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
1728 if (hw->chip_id == CHIP_ID_YUKON_EC_U && new_mtu > ETH_DATA_LEN)
1731 if (!netif_running(dev)) {
1736 sky2_write32(hw, B0_IMSK, 0);
1738 dev->trans_start = jiffies; /* prevent tx timeout */
1739 netif_stop_queue(dev);
1740 netif_poll_disable(hw->dev[0]);
1742 ctl = gma_read16(hw, sky2->port, GM_GP_CTRL);
1743 gma_write16(hw, sky2->port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
1745 sky2_rx_clean(sky2);
1748 sky2->rx_bufsize = sky2_buf_size(new_mtu);
1749 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
1750 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
1752 if (dev->mtu > ETH_DATA_LEN)
1753 mode |= GM_SMOD_JUMBO_ENA;
1755 gma_write16(hw, sky2->port, GM_SERIAL_MODE, mode);
1757 sky2_write8(hw, RB_ADDR(rxqaddr[sky2->port], RB_CTRL), RB_ENA_OP_MD);
1759 err = sky2_rx_start(sky2);
1760 sky2_write32(hw, B0_IMSK, hw->intr_mask);
1765 gma_write16(hw, sky2->port, GM_GP_CTRL, ctl);
1767 netif_poll_enable(hw->dev[0]);
1768 netif_wake_queue(dev);
1775 * Receive one packet.
1776 * For small packets or errors, just reuse existing skb.
1777 * For larger packets, get new buffer.
1779 static struct sk_buff *sky2_receive(struct sky2_port *sky2,
1780 u16 length, u32 status)
1782 struct ring_info *re = sky2->rx_ring + sky2->rx_next;
1783 struct sk_buff *skb = NULL;
1785 if (unlikely(netif_msg_rx_status(sky2)))
1786 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
1787 sky2->netdev->name, sky2->rx_next, status, length);
1789 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
1790 prefetch(sky2->rx_ring + sky2->rx_next);
1792 if (status & GMR_FS_ANY_ERR)
1795 if (!(status & GMR_FS_RX_OK))
1798 if ((status >> 16) != length || length > sky2->rx_bufsize)
1801 if (length < copybreak) {
1802 skb = alloc_skb(length + 2, GFP_ATOMIC);
1806 skb_reserve(skb, 2);
1807 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->mapaddr,
1808 length, PCI_DMA_FROMDEVICE);
1809 memcpy(skb->data, re->skb->data, length);
1810 skb->ip_summed = re->skb->ip_summed;
1811 skb->csum = re->skb->csum;
1812 pci_dma_sync_single_for_device(sky2->hw->pdev, re->mapaddr,
1813 length, PCI_DMA_FROMDEVICE);
1815 struct sk_buff *nskb;
1817 nskb = sky2_alloc_skb(sky2->rx_bufsize, GFP_ATOMIC);
1823 pci_unmap_single(sky2->hw->pdev, re->mapaddr,
1824 sky2->rx_bufsize, PCI_DMA_FROMDEVICE);
1825 prefetch(skb->data);
1827 re->mapaddr = pci_map_single(sky2->hw->pdev, nskb->data,
1828 sky2->rx_bufsize, PCI_DMA_FROMDEVICE);
1831 skb_put(skb, length);
1833 re->skb->ip_summed = CHECKSUM_NONE;
1834 sky2_rx_add(sky2, re->mapaddr);
1836 /* Tell receiver about new buffers. */
1837 sky2_put_idx(sky2->hw, rxqaddr[sky2->port], sky2->rx_put,
1838 &sky2->rx_last_put, RX_LE_SIZE);
1843 ++sky2->net_stats.rx_over_errors;
1847 ++sky2->net_stats.rx_errors;
1849 if (netif_msg_rx_err(sky2) && net_ratelimit())
1850 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
1851 sky2->netdev->name, status, length);
1853 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
1854 sky2->net_stats.rx_length_errors++;
1855 if (status & GMR_FS_FRAGMENT)
1856 sky2->net_stats.rx_frame_errors++;
1857 if (status & GMR_FS_CRC_ERR)
1858 sky2->net_stats.rx_crc_errors++;
1859 if (status & GMR_FS_RX_FF_OV)
1860 sky2->net_stats.rx_fifo_errors++;
1866 * Check for transmit complete
1868 #define TX_NO_STATUS 0xffff
1870 static void sky2_tx_check(struct sky2_hw *hw, int port, u16 last)
1872 if (last != TX_NO_STATUS) {
1873 struct net_device *dev = hw->dev[port];
1874 if (dev && netif_running(dev)) {
1875 struct sky2_port *sky2 = netdev_priv(dev);
1877 spin_lock(&sky2->tx_lock);
1878 sky2_tx_complete(sky2, last);
1879 spin_unlock(&sky2->tx_lock);
1885 * Both ports share the same status interrupt, therefore there is only
1888 static int sky2_poll(struct net_device *dev0, int *budget)
1890 struct sky2_hw *hw = ((struct sky2_port *) netdev_priv(dev0))->hw;
1891 unsigned int to_do = min(dev0->quota, *budget);
1892 unsigned int work_done = 0;
1894 u16 tx_done[2] = { TX_NO_STATUS, TX_NO_STATUS };
1896 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
1899 * Kick the STAT_LEV_TIMER_CTRL timer.
1900 * This fixes my hangs on Yukon-EC (0xb6) rev 1.
1901 * The if clause is there to start the timer only if it has been
1902 * configured correctly and not been disabled via ethtool.
1904 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_START) {
1905 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
1906 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
1909 hwidx = sky2_read16(hw, STAT_PUT_IDX);
1910 BUG_ON(hwidx >= STATUS_RING_SIZE);
1913 while (hwidx != hw->st_idx) {
1914 struct sky2_status_le *le = hw->st_le + hw->st_idx;
1915 struct net_device *dev;
1916 struct sky2_port *sky2;
1917 struct sk_buff *skb;
1921 le = hw->st_le + hw->st_idx;
1922 hw->st_idx = (hw->st_idx + 1) % STATUS_RING_SIZE;
1923 prefetch(hw->st_le + hw->st_idx);
1925 BUG_ON(le->link >= 2);
1926 dev = hw->dev[le->link];
1927 if (dev == NULL || !netif_running(dev))
1930 sky2 = netdev_priv(dev);
1931 status = le32_to_cpu(le->status);
1932 length = le16_to_cpu(le->length);
1934 switch (le->opcode & ~HW_OWNER) {
1936 skb = sky2_receive(sky2, length, status);
1941 skb->protocol = eth_type_trans(skb, dev);
1942 dev->last_rx = jiffies;
1944 #ifdef SKY2_VLAN_TAG_USED
1945 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
1946 vlan_hwaccel_receive_skb(skb,
1948 be16_to_cpu(sky2->rx_tag));
1951 netif_receive_skb(skb);
1953 if (++work_done >= to_do)
1957 #ifdef SKY2_VLAN_TAG_USED
1959 sky2->rx_tag = length;
1963 sky2->rx_tag = length;
1967 skb = sky2->rx_ring[sky2->rx_next].skb;
1968 skb->ip_summed = CHECKSUM_HW;
1969 skb->csum = le16_to_cpu(status);
1973 /* TX index reports status for both ports */
1974 tx_done[0] = status & 0xffff;
1975 tx_done[1] = ((status >> 24) & 0xff)
1976 | (u16)(length & 0xf) << 8;
1980 if (net_ratelimit())
1981 printk(KERN_WARNING PFX
1982 "unknown status opcode 0x%x\n", le->opcode);
1988 sky2_tx_check(hw, 0, tx_done[0]);
1989 sky2_tx_check(hw, 1, tx_done[1]);
1991 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_START) {
1992 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
1993 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
1996 if (likely(work_done < to_do)) {
1997 netif_rx_complete(dev0);
1998 hw->intr_mask |= Y2_IS_STAT_BMU;
1999 sky2_write32(hw, B0_IMSK, hw->intr_mask);
2002 *budget -= work_done;
2003 dev0->quota -= work_done;
2008 static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2010 struct net_device *dev = hw->dev[port];
2012 if (net_ratelimit())
2013 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
2016 if (status & Y2_IS_PAR_RD1) {
2017 if (net_ratelimit())
2018 printk(KERN_ERR PFX "%s: ram data read parity error\n",
2021 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2024 if (status & Y2_IS_PAR_WR1) {
2025 if (net_ratelimit())
2026 printk(KERN_ERR PFX "%s: ram data write parity error\n",
2029 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2032 if (status & Y2_IS_PAR_MAC1) {
2033 if (net_ratelimit())
2034 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
2035 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2038 if (status & Y2_IS_PAR_RX1) {
2039 if (net_ratelimit())
2040 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
2041 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2044 if (status & Y2_IS_TCP_TXA1) {
2045 if (net_ratelimit())
2046 printk(KERN_ERR PFX "%s: TCP segmentation error\n",
2048 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2052 static void sky2_hw_intr(struct sky2_hw *hw)
2054 u32 status = sky2_read32(hw, B0_HWE_ISRC);
2056 if (status & Y2_IS_TIST_OV)
2057 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2059 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
2062 pci_read_config_word(hw->pdev, PCI_STATUS, &pci_err);
2063 if (net_ratelimit())
2064 printk(KERN_ERR PFX "%s: pci hw error (0x%x)\n",
2065 pci_name(hw->pdev), pci_err);
2067 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2068 pci_write_config_word(hw->pdev, PCI_STATUS,
2069 pci_err | PCI_STATUS_ERROR_BITS);
2070 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2073 if (status & Y2_IS_PCI_EXP) {
2074 /* PCI-Express uncorrectable Error occurred */
2077 pci_read_config_dword(hw->pdev, PEX_UNC_ERR_STAT, &pex_err);
2079 if (net_ratelimit())
2080 printk(KERN_ERR PFX "%s: pci express error (0x%x)\n",
2081 pci_name(hw->pdev), pex_err);
2083 /* clear the interrupt */
2084 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2085 pci_write_config_dword(hw->pdev, PEX_UNC_ERR_STAT,
2087 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2089 if (pex_err & PEX_FATAL_ERRORS) {
2090 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2091 hwmsk &= ~Y2_IS_PCI_EXP;
2092 sky2_write32(hw, B0_HWE_IMSK, hwmsk);
2096 if (status & Y2_HWE_L1_MASK)
2097 sky2_hw_error(hw, 0, status);
2099 if (status & Y2_HWE_L1_MASK)
2100 sky2_hw_error(hw, 1, status);
2103 static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2105 struct net_device *dev = hw->dev[port];
2106 struct sky2_port *sky2 = netdev_priv(dev);
2107 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2109 if (netif_msg_intr(sky2))
2110 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
2113 if (status & GM_IS_RX_FF_OR) {
2114 ++sky2->net_stats.rx_fifo_errors;
2115 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2118 if (status & GM_IS_TX_FF_UR) {
2119 ++sky2->net_stats.tx_fifo_errors;
2120 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2124 static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
2126 struct net_device *dev = hw->dev[port];
2127 struct sky2_port *sky2 = netdev_priv(dev);
2129 hw->intr_mask &= ~(port == 0 ? Y2_IS_IRQ_PHY1 : Y2_IS_IRQ_PHY2);
2130 sky2_write32(hw, B0_IMSK, hw->intr_mask);
2131 schedule_work(&sky2->phy_task);
2134 static irqreturn_t sky2_intr(int irq, void *dev_id, struct pt_regs *regs)
2136 struct sky2_hw *hw = dev_id;
2137 struct net_device *dev0 = hw->dev[0];
2140 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2141 if (status == 0 || status == ~0)
2144 if (status & Y2_IS_HW_ERR)
2147 /* Do NAPI for Rx and Tx status */
2148 if (status & Y2_IS_STAT_BMU) {
2149 hw->intr_mask &= ~Y2_IS_STAT_BMU;
2150 sky2_write32(hw, B0_IMSK, hw->intr_mask);
2152 if (likely(__netif_rx_schedule_prep(dev0))) {
2153 prefetch(&hw->st_le[hw->st_idx]);
2154 __netif_rx_schedule(dev0);
2158 if (status & Y2_IS_IRQ_PHY1)
2159 sky2_phy_intr(hw, 0);
2161 if (status & Y2_IS_IRQ_PHY2)
2162 sky2_phy_intr(hw, 1);
2164 if (status & Y2_IS_IRQ_MAC1)
2165 sky2_mac_intr(hw, 0);
2167 if (status & Y2_IS_IRQ_MAC2)
2168 sky2_mac_intr(hw, 1);
2170 sky2_write32(hw, B0_Y2_SP_ICR, 2);
2172 sky2_read32(hw, B0_IMSK);
2177 #ifdef CONFIG_NET_POLL_CONTROLLER
2178 static void sky2_netpoll(struct net_device *dev)
2180 struct sky2_port *sky2 = netdev_priv(dev);
2182 sky2_intr(sky2->hw->pdev->irq, sky2->hw, NULL);
2186 /* Chip internal frequency for clock calculations */
2187 static inline u32 sky2_mhz(const struct sky2_hw *hw)
2189 switch (hw->chip_id) {
2190 case CHIP_ID_YUKON_EC:
2191 case CHIP_ID_YUKON_EC_U:
2192 return 125; /* 125 Mhz */
2193 case CHIP_ID_YUKON_FE:
2194 return 100; /* 100 Mhz */
2195 default: /* YUKON_XL */
2196 return 156; /* 156 Mhz */
2200 static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
2202 return sky2_mhz(hw) * us;
2205 static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
2207 return clk / sky2_mhz(hw);
2211 static int sky2_reset(struct sky2_hw *hw)
2217 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2219 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
2220 if (hw->chip_id < CHIP_ID_YUKON_XL || hw->chip_id > CHIP_ID_YUKON_FE) {
2221 printk(KERN_ERR PFX "%s: unsupported chip type 0x%x\n",
2222 pci_name(hw->pdev), hw->chip_id);
2227 if (hw->chip_id <= CHIP_ID_YUKON_EC) {
2228 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
2229 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
2233 sky2_write8(hw, B0_CTST, CS_RST_SET);
2234 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2236 /* clear PCI errors, if any */
2237 err = pci_read_config_word(hw->pdev, PCI_STATUS, &status);
2241 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2242 err = pci_write_config_word(hw->pdev, PCI_STATUS,
2243 status | PCI_STATUS_ERROR_BITS);
2247 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
2249 /* clear any PEX errors */
2250 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP)) {
2251 err = pci_write_config_dword(hw->pdev, PEX_UNC_ERR_STAT,
2257 pmd_type = sky2_read8(hw, B2_PMD_TYP);
2258 hw->copper = !(pmd_type == 'L' || pmd_type == 'S');
2261 t8 = sky2_read8(hw, B2_Y2_HW_RES);
2262 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
2263 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
2266 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2268 sky2_set_power_state(hw, PCI_D0);
2270 for (i = 0; i < hw->ports; i++) {
2271 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2272 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
2275 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2277 /* Clear I2C IRQ noise */
2278 sky2_write32(hw, B2_I2C_IRQ, 1);
2280 /* turn off hardware timer (unused) */
2281 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
2282 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
2284 sky2_write8(hw, B0_Y2LED, LED_STAT_ON);
2286 /* Turn off descriptor polling */
2287 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
2289 /* Turn off receive timestamp */
2290 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
2291 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2293 /* enable the Tx Arbiters */
2294 for (i = 0; i < hw->ports; i++)
2295 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
2297 /* Initialize ram interface */
2298 for (i = 0; i < hw->ports; i++) {
2299 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
2301 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
2302 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
2303 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
2304 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
2305 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
2306 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
2307 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
2308 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
2309 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
2310 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
2311 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
2312 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
2315 sky2_write32(hw, B0_HWE_IMSK, Y2_HWE_ALL_MASK);
2317 for (i = 0; i < hw->ports; i++)
2318 sky2_phy_reset(hw, i);
2320 memset(hw->st_le, 0, STATUS_LE_BYTES);
2323 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
2324 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
2326 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
2327 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
2329 /* Set the list last index */
2330 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
2332 /* These status setup values are copied from SysKonnect's driver */
2334 /* WA for dev. #4.3 */
2335 sky2_write16(hw, STAT_TX_IDX_TH, 0xfff); /* Tx Threshold */
2337 /* set Status-FIFO watermark */
2338 sky2_write8(hw, STAT_FIFO_WM, 0x21); /* WA for dev. #4.18 */
2340 /* set Status-FIFO ISR watermark */
2341 sky2_write8(hw, STAT_FIFO_ISR_WM, 0x07); /* WA for dev. #4.18 */
2342 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 10000));
2344 sky2_write16(hw, STAT_TX_IDX_TH, 10);
2345 sky2_write8(hw, STAT_FIFO_WM, 16);
2347 /* set Status-FIFO ISR watermark */
2348 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
2349 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
2351 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
2353 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
2354 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 7));
2357 /* enable status unit */
2358 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
2360 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2361 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2362 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
2367 /* This is to catch a BIOS bug workaround where
2368 * mmconfig table doesn't have other buses.
2370 printk(KERN_ERR PFX "%s: can't access PCI config space\n",
2371 pci_name(hw->pdev));
2375 static u32 sky2_supported_modes(const struct sky2_hw *hw)
2379 modes = SUPPORTED_10baseT_Half
2380 | SUPPORTED_10baseT_Full
2381 | SUPPORTED_100baseT_Half
2382 | SUPPORTED_100baseT_Full
2383 | SUPPORTED_Autoneg | SUPPORTED_TP;
2385 if (hw->chip_id != CHIP_ID_YUKON_FE)
2386 modes |= SUPPORTED_1000baseT_Half
2387 | SUPPORTED_1000baseT_Full;
2389 modes = SUPPORTED_1000baseT_Full | SUPPORTED_FIBRE
2390 | SUPPORTED_Autoneg;
2394 static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2396 struct sky2_port *sky2 = netdev_priv(dev);
2397 struct sky2_hw *hw = sky2->hw;
2399 ecmd->transceiver = XCVR_INTERNAL;
2400 ecmd->supported = sky2_supported_modes(hw);
2401 ecmd->phy_address = PHY_ADDR_MARV;
2403 ecmd->supported = SUPPORTED_10baseT_Half
2404 | SUPPORTED_10baseT_Full
2405 | SUPPORTED_100baseT_Half
2406 | SUPPORTED_100baseT_Full
2407 | SUPPORTED_1000baseT_Half
2408 | SUPPORTED_1000baseT_Full
2409 | SUPPORTED_Autoneg | SUPPORTED_TP;
2410 ecmd->port = PORT_TP;
2412 ecmd->port = PORT_FIBRE;
2414 ecmd->advertising = sky2->advertising;
2415 ecmd->autoneg = sky2->autoneg;
2416 ecmd->speed = sky2->speed;
2417 ecmd->duplex = sky2->duplex;
2421 static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2423 struct sky2_port *sky2 = netdev_priv(dev);
2424 const struct sky2_hw *hw = sky2->hw;
2425 u32 supported = sky2_supported_modes(hw);
2427 if (ecmd->autoneg == AUTONEG_ENABLE) {
2428 ecmd->advertising = supported;
2434 switch (ecmd->speed) {
2436 if (ecmd->duplex == DUPLEX_FULL)
2437 setting = SUPPORTED_1000baseT_Full;
2438 else if (ecmd->duplex == DUPLEX_HALF)
2439 setting = SUPPORTED_1000baseT_Half;
2444 if (ecmd->duplex == DUPLEX_FULL)
2445 setting = SUPPORTED_100baseT_Full;
2446 else if (ecmd->duplex == DUPLEX_HALF)
2447 setting = SUPPORTED_100baseT_Half;
2453 if (ecmd->duplex == DUPLEX_FULL)
2454 setting = SUPPORTED_10baseT_Full;
2455 else if (ecmd->duplex == DUPLEX_HALF)
2456 setting = SUPPORTED_10baseT_Half;
2464 if ((setting & supported) == 0)
2467 sky2->speed = ecmd->speed;
2468 sky2->duplex = ecmd->duplex;
2471 sky2->autoneg = ecmd->autoneg;
2472 sky2->advertising = ecmd->advertising;
2474 if (netif_running(dev))
2475 sky2_phy_reinit(sky2);
2480 static void sky2_get_drvinfo(struct net_device *dev,
2481 struct ethtool_drvinfo *info)
2483 struct sky2_port *sky2 = netdev_priv(dev);
2485 strcpy(info->driver, DRV_NAME);
2486 strcpy(info->version, DRV_VERSION);
2487 strcpy(info->fw_version, "N/A");
2488 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
2491 static const struct sky2_stat {
2492 char name[ETH_GSTRING_LEN];
2495 { "tx_bytes", GM_TXO_OK_HI },
2496 { "rx_bytes", GM_RXO_OK_HI },
2497 { "tx_broadcast", GM_TXF_BC_OK },
2498 { "rx_broadcast", GM_RXF_BC_OK },
2499 { "tx_multicast", GM_TXF_MC_OK },
2500 { "rx_multicast", GM_RXF_MC_OK },
2501 { "tx_unicast", GM_TXF_UC_OK },
2502 { "rx_unicast", GM_RXF_UC_OK },
2503 { "tx_mac_pause", GM_TXF_MPAUSE },
2504 { "rx_mac_pause", GM_RXF_MPAUSE },
2505 { "collisions", GM_TXF_SNG_COL },
2506 { "late_collision",GM_TXF_LAT_COL },
2507 { "aborted", GM_TXF_ABO_COL },
2508 { "multi_collisions", GM_TXF_MUL_COL },
2509 { "fifo_underrun", GM_TXE_FIFO_UR },
2510 { "fifo_overflow", GM_RXE_FIFO_OV },
2511 { "rx_toolong", GM_RXF_LNG_ERR },
2512 { "rx_jabber", GM_RXF_JAB_PKT },
2513 { "rx_runt", GM_RXE_FRAG },
2514 { "rx_too_long", GM_RXF_LNG_ERR },
2515 { "rx_fcs_error", GM_RXF_FCS_ERR },
2518 static u32 sky2_get_rx_csum(struct net_device *dev)
2520 struct sky2_port *sky2 = netdev_priv(dev);
2522 return sky2->rx_csum;
2525 static int sky2_set_rx_csum(struct net_device *dev, u32 data)
2527 struct sky2_port *sky2 = netdev_priv(dev);
2529 sky2->rx_csum = data;
2531 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
2532 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
2537 static u32 sky2_get_msglevel(struct net_device *netdev)
2539 struct sky2_port *sky2 = netdev_priv(netdev);
2540 return sky2->msg_enable;
2543 static int sky2_nway_reset(struct net_device *dev)
2545 struct sky2_port *sky2 = netdev_priv(dev);
2547 if (sky2->autoneg != AUTONEG_ENABLE)
2550 sky2_phy_reinit(sky2);
2555 static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
2557 struct sky2_hw *hw = sky2->hw;
2558 unsigned port = sky2->port;
2561 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
2562 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
2563 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
2564 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
2566 for (i = 2; i < count; i++)
2567 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
2570 static void sky2_set_msglevel(struct net_device *netdev, u32 value)
2572 struct sky2_port *sky2 = netdev_priv(netdev);
2573 sky2->msg_enable = value;
2576 static int sky2_get_stats_count(struct net_device *dev)
2578 return ARRAY_SIZE(sky2_stats);
2581 static void sky2_get_ethtool_stats(struct net_device *dev,
2582 struct ethtool_stats *stats, u64 * data)
2584 struct sky2_port *sky2 = netdev_priv(dev);
2586 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
2589 static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
2593 switch (stringset) {
2595 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
2596 memcpy(data + i * ETH_GSTRING_LEN,
2597 sky2_stats[i].name, ETH_GSTRING_LEN);
2602 /* Use hardware MIB variables for critical path statistics and
2603 * transmit feedback not reported at interrupt.
2604 * Other errors are accounted for in interrupt handler.
2606 static struct net_device_stats *sky2_get_stats(struct net_device *dev)
2608 struct sky2_port *sky2 = netdev_priv(dev);
2611 sky2_phy_stats(sky2, data, ARRAY_SIZE(data));
2613 sky2->net_stats.tx_bytes = data[0];
2614 sky2->net_stats.rx_bytes = data[1];
2615 sky2->net_stats.tx_packets = data[2] + data[4] + data[6];
2616 sky2->net_stats.rx_packets = data[3] + data[5] + data[7];
2617 sky2->net_stats.multicast = data[5] + data[7];
2618 sky2->net_stats.collisions = data[10];
2619 sky2->net_stats.tx_aborted_errors = data[12];
2621 return &sky2->net_stats;
2624 static int sky2_set_mac_address(struct net_device *dev, void *p)
2626 struct sky2_port *sky2 = netdev_priv(dev);
2627 struct sky2_hw *hw = sky2->hw;
2628 unsigned port = sky2->port;
2629 const struct sockaddr *addr = p;
2631 if (!is_valid_ether_addr(addr->sa_data))
2632 return -EADDRNOTAVAIL;
2634 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
2635 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
2636 dev->dev_addr, ETH_ALEN);
2637 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
2638 dev->dev_addr, ETH_ALEN);
2640 /* virtual address for data */
2641 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
2643 /* physical address: used for pause frames */
2644 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
2649 static void sky2_set_multicast(struct net_device *dev)
2651 struct sky2_port *sky2 = netdev_priv(dev);
2652 struct sky2_hw *hw = sky2->hw;
2653 unsigned port = sky2->port;
2654 struct dev_mc_list *list = dev->mc_list;
2658 memset(filter, 0, sizeof(filter));
2660 reg = gma_read16(hw, port, GM_RX_CTRL);
2661 reg |= GM_RXCR_UCF_ENA;
2663 if (dev->flags & IFF_PROMISC) /* promiscuous */
2664 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
2665 else if ((dev->flags & IFF_ALLMULTI) || dev->mc_count > 16) /* all multicast */
2666 memset(filter, 0xff, sizeof(filter));
2667 else if (dev->mc_count == 0) /* no multicast */
2668 reg &= ~GM_RXCR_MCF_ENA;
2671 reg |= GM_RXCR_MCF_ENA;
2673 for (i = 0; list && i < dev->mc_count; i++, list = list->next) {
2674 u32 bit = ether_crc(ETH_ALEN, list->dmi_addr) & 0x3f;
2675 filter[bit / 8] |= 1 << (bit % 8);
2679 gma_write16(hw, port, GM_MC_ADDR_H1,
2680 (u16) filter[0] | ((u16) filter[1] << 8));
2681 gma_write16(hw, port, GM_MC_ADDR_H2,
2682 (u16) filter[2] | ((u16) filter[3] << 8));
2683 gma_write16(hw, port, GM_MC_ADDR_H3,
2684 (u16) filter[4] | ((u16) filter[5] << 8));
2685 gma_write16(hw, port, GM_MC_ADDR_H4,
2686 (u16) filter[6] | ((u16) filter[7] << 8));
2688 gma_write16(hw, port, GM_RX_CTRL, reg);
2691 /* Can have one global because blinking is controlled by
2692 * ethtool and that is always under RTNL mutex
2694 static void sky2_led(struct sky2_hw *hw, unsigned port, int on)
2698 switch (hw->chip_id) {
2699 case CHIP_ID_YUKON_XL:
2700 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2701 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2702 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
2703 on ? (PHY_M_LEDC_LOS_CTRL(1) |
2704 PHY_M_LEDC_INIT_CTRL(7) |
2705 PHY_M_LEDC_STA1_CTRL(7) |
2706 PHY_M_LEDC_STA0_CTRL(7))
2709 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2713 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
2714 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
2715 on ? PHY_M_LED_MO_DUP(MO_LED_ON) |
2716 PHY_M_LED_MO_10(MO_LED_ON) |
2717 PHY_M_LED_MO_100(MO_LED_ON) |
2718 PHY_M_LED_MO_1000(MO_LED_ON) |
2719 PHY_M_LED_MO_RX(MO_LED_ON)
2720 : PHY_M_LED_MO_DUP(MO_LED_OFF) |
2721 PHY_M_LED_MO_10(MO_LED_OFF) |
2722 PHY_M_LED_MO_100(MO_LED_OFF) |
2723 PHY_M_LED_MO_1000(MO_LED_OFF) |
2724 PHY_M_LED_MO_RX(MO_LED_OFF));
2729 /* blink LED's for finding board */
2730 static int sky2_phys_id(struct net_device *dev, u32 data)
2732 struct sky2_port *sky2 = netdev_priv(dev);
2733 struct sky2_hw *hw = sky2->hw;
2734 unsigned port = sky2->port;
2735 u16 ledctrl, ledover = 0;
2740 if (!data || data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ))
2741 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT);
2745 /* save initial values */
2746 down(&sky2->phy_sema);
2747 if (hw->chip_id == CHIP_ID_YUKON_XL) {
2748 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2749 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2750 ledctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
2751 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2753 ledctrl = gm_phy_read(hw, port, PHY_MARV_LED_CTRL);
2754 ledover = gm_phy_read(hw, port, PHY_MARV_LED_OVER);
2758 while (!interrupted && ms > 0) {
2759 sky2_led(hw, port, onoff);
2762 up(&sky2->phy_sema);
2763 interrupted = msleep_interruptible(250);
2764 down(&sky2->phy_sema);
2769 /* resume regularly scheduled programming */
2770 if (hw->chip_id == CHIP_ID_YUKON_XL) {
2771 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2772 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2773 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ledctrl);
2774 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2776 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
2777 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
2779 up(&sky2->phy_sema);
2784 static void sky2_get_pauseparam(struct net_device *dev,
2785 struct ethtool_pauseparam *ecmd)
2787 struct sky2_port *sky2 = netdev_priv(dev);
2789 ecmd->tx_pause = sky2->tx_pause;
2790 ecmd->rx_pause = sky2->rx_pause;
2791 ecmd->autoneg = sky2->autoneg;
2794 static int sky2_set_pauseparam(struct net_device *dev,
2795 struct ethtool_pauseparam *ecmd)
2797 struct sky2_port *sky2 = netdev_priv(dev);
2800 sky2->autoneg = ecmd->autoneg;
2801 sky2->tx_pause = ecmd->tx_pause != 0;
2802 sky2->rx_pause = ecmd->rx_pause != 0;
2804 sky2_phy_reinit(sky2);
2810 static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2812 struct sky2_port *sky2 = netdev_priv(dev);
2814 wol->supported = WAKE_MAGIC;
2815 wol->wolopts = sky2->wol ? WAKE_MAGIC : 0;
2818 static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2820 struct sky2_port *sky2 = netdev_priv(dev);
2821 struct sky2_hw *hw = sky2->hw;
2823 if (wol->wolopts != WAKE_MAGIC && wol->wolopts != 0)
2826 sky2->wol = wol->wolopts == WAKE_MAGIC;
2829 memcpy_toio(hw->regs + WOL_MAC_ADDR, dev->dev_addr, ETH_ALEN);
2831 sky2_write16(hw, WOL_CTRL_STAT,
2832 WOL_CTL_ENA_PME_ON_MAGIC_PKT |
2833 WOL_CTL_ENA_MAGIC_PKT_UNIT);
2835 sky2_write16(hw, WOL_CTRL_STAT, WOL_CTL_DEFAULT);
2841 static int sky2_get_coalesce(struct net_device *dev,
2842 struct ethtool_coalesce *ecmd)
2844 struct sky2_port *sky2 = netdev_priv(dev);
2845 struct sky2_hw *hw = sky2->hw;
2847 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
2848 ecmd->tx_coalesce_usecs = 0;
2850 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
2851 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
2853 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
2855 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
2856 ecmd->rx_coalesce_usecs = 0;
2858 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
2859 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
2861 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
2863 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
2864 ecmd->rx_coalesce_usecs_irq = 0;
2866 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
2867 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
2870 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
2875 /* Note: this affect both ports */
2876 static int sky2_set_coalesce(struct net_device *dev,
2877 struct ethtool_coalesce *ecmd)
2879 struct sky2_port *sky2 = netdev_priv(dev);
2880 struct sky2_hw *hw = sky2->hw;
2881 const u32 tmin = sky2_clk2us(hw, 1);
2882 const u32 tmax = 5000;
2884 if (ecmd->tx_coalesce_usecs != 0 &&
2885 (ecmd->tx_coalesce_usecs < tmin || ecmd->tx_coalesce_usecs > tmax))
2888 if (ecmd->rx_coalesce_usecs != 0 &&
2889 (ecmd->rx_coalesce_usecs < tmin || ecmd->rx_coalesce_usecs > tmax))
2892 if (ecmd->rx_coalesce_usecs_irq != 0 &&
2893 (ecmd->rx_coalesce_usecs_irq < tmin || ecmd->rx_coalesce_usecs_irq > tmax))
2896 if (ecmd->tx_max_coalesced_frames >= TX_RING_SIZE-1)
2898 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
2900 if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING)
2903 if (ecmd->tx_coalesce_usecs == 0)
2904 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
2906 sky2_write32(hw, STAT_TX_TIMER_INI,
2907 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
2908 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2910 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
2912 if (ecmd->rx_coalesce_usecs == 0)
2913 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
2915 sky2_write32(hw, STAT_LEV_TIMER_INI,
2916 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
2917 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2919 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
2921 if (ecmd->rx_coalesce_usecs_irq == 0)
2922 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
2924 sky2_write32(hw, STAT_ISR_TIMER_INI,
2925 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
2926 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
2928 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
2932 static void sky2_get_ringparam(struct net_device *dev,
2933 struct ethtool_ringparam *ering)
2935 struct sky2_port *sky2 = netdev_priv(dev);
2937 ering->rx_max_pending = RX_MAX_PENDING;
2938 ering->rx_mini_max_pending = 0;
2939 ering->rx_jumbo_max_pending = 0;
2940 ering->tx_max_pending = TX_RING_SIZE - 1;
2942 ering->rx_pending = sky2->rx_pending;
2943 ering->rx_mini_pending = 0;
2944 ering->rx_jumbo_pending = 0;
2945 ering->tx_pending = sky2->tx_pending;
2948 static int sky2_set_ringparam(struct net_device *dev,
2949 struct ethtool_ringparam *ering)
2951 struct sky2_port *sky2 = netdev_priv(dev);
2954 if (ering->rx_pending > RX_MAX_PENDING ||
2955 ering->rx_pending < 8 ||
2956 ering->tx_pending < MAX_SKB_TX_LE ||
2957 ering->tx_pending > TX_RING_SIZE - 1)
2960 if (netif_running(dev))
2963 sky2->rx_pending = ering->rx_pending;
2964 sky2->tx_pending = ering->tx_pending;
2966 if (netif_running(dev)) {
2971 sky2_set_multicast(dev);
2977 static int sky2_get_regs_len(struct net_device *dev)
2983 * Returns copy of control register region
2984 * Note: access to the RAM address register set will cause timeouts.
2986 static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
2989 const struct sky2_port *sky2 = netdev_priv(dev);
2990 const void __iomem *io = sky2->hw->regs;
2992 BUG_ON(regs->len < B3_RI_WTO_R1);
2994 memset(p, 0, regs->len);
2996 memcpy_fromio(p, io, B3_RAM_ADDR);
2998 memcpy_fromio(p + B3_RI_WTO_R1,
3000 regs->len - B3_RI_WTO_R1);
3003 static struct ethtool_ops sky2_ethtool_ops = {
3004 .get_settings = sky2_get_settings,
3005 .set_settings = sky2_set_settings,
3006 .get_drvinfo = sky2_get_drvinfo,
3007 .get_msglevel = sky2_get_msglevel,
3008 .set_msglevel = sky2_set_msglevel,
3009 .nway_reset = sky2_nway_reset,
3010 .get_regs_len = sky2_get_regs_len,
3011 .get_regs = sky2_get_regs,
3012 .get_link = ethtool_op_get_link,
3013 .get_sg = ethtool_op_get_sg,
3014 .set_sg = ethtool_op_set_sg,
3015 .get_tx_csum = ethtool_op_get_tx_csum,
3016 .set_tx_csum = ethtool_op_set_tx_csum,
3017 .get_tso = ethtool_op_get_tso,
3018 .set_tso = ethtool_op_set_tso,
3019 .get_rx_csum = sky2_get_rx_csum,
3020 .set_rx_csum = sky2_set_rx_csum,
3021 .get_strings = sky2_get_strings,
3022 .get_coalesce = sky2_get_coalesce,
3023 .set_coalesce = sky2_set_coalesce,
3024 .get_ringparam = sky2_get_ringparam,
3025 .set_ringparam = sky2_set_ringparam,
3026 .get_pauseparam = sky2_get_pauseparam,
3027 .set_pauseparam = sky2_set_pauseparam,
3029 .get_wol = sky2_get_wol,
3030 .set_wol = sky2_set_wol,
3032 .phys_id = sky2_phys_id,
3033 .get_stats_count = sky2_get_stats_count,
3034 .get_ethtool_stats = sky2_get_ethtool_stats,
3035 .get_perm_addr = ethtool_op_get_perm_addr,
3038 /* Initialize network device */
3039 static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
3040 unsigned port, int highmem)
3042 struct sky2_port *sky2;
3043 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
3046 printk(KERN_ERR "sky2 etherdev alloc failed");
3050 SET_MODULE_OWNER(dev);
3051 SET_NETDEV_DEV(dev, &hw->pdev->dev);
3052 dev->irq = hw->pdev->irq;
3053 dev->open = sky2_up;
3054 dev->stop = sky2_down;
3055 dev->do_ioctl = sky2_ioctl;
3056 dev->hard_start_xmit = sky2_xmit_frame;
3057 dev->get_stats = sky2_get_stats;
3058 dev->set_multicast_list = sky2_set_multicast;
3059 dev->set_mac_address = sky2_set_mac_address;
3060 dev->change_mtu = sky2_change_mtu;
3061 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
3062 dev->tx_timeout = sky2_tx_timeout;
3063 dev->watchdog_timeo = TX_WATCHDOG;
3065 dev->poll = sky2_poll;
3066 dev->weight = NAPI_WEIGHT;
3067 #ifdef CONFIG_NET_POLL_CONTROLLER
3068 dev->poll_controller = sky2_netpoll;
3071 sky2 = netdev_priv(dev);
3074 sky2->msg_enable = netif_msg_init(debug, default_msg);
3076 spin_lock_init(&sky2->tx_lock);
3077 /* Auto speed and flow control */
3078 sky2->autoneg = AUTONEG_ENABLE;
3083 sky2->advertising = sky2_supported_modes(hw);
3085 /* Receive checksum disabled for Yukon XL
3086 * because of observed problems with incorrect
3087 * values when multiple packets are received in one interrupt
3089 sky2->rx_csum = (hw->chip_id != CHIP_ID_YUKON_XL);
3091 INIT_WORK(&sky2->phy_task, sky2_phy_task, sky2);
3092 init_MUTEX(&sky2->phy_sema);
3093 sky2->tx_pending = TX_DEF_PENDING;
3094 sky2->rx_pending = is_ec_a1(hw) ? 8 : RX_DEF_PENDING;
3095 sky2->rx_bufsize = sky2_buf_size(ETH_DATA_LEN);
3097 hw->dev[port] = dev;
3101 dev->features |= NETIF_F_LLTX;
3102 if (hw->chip_id != CHIP_ID_YUKON_EC_U)
3103 dev->features |= NETIF_F_TSO;
3105 dev->features |= NETIF_F_HIGHDMA;
3106 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
3108 #ifdef SKY2_VLAN_TAG_USED
3109 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3110 dev->vlan_rx_register = sky2_vlan_rx_register;
3111 dev->vlan_rx_kill_vid = sky2_vlan_rx_kill_vid;
3114 /* read the mac address */
3115 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
3116 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
3118 /* device is off until link detection */
3119 netif_carrier_off(dev);
3120 netif_stop_queue(dev);
3125 static void __devinit sky2_show_addr(struct net_device *dev)
3127 const struct sky2_port *sky2 = netdev_priv(dev);
3129 if (netif_msg_probe(sky2))
3130 printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
3132 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
3133 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
3136 /* Handle software interrupt used during MSI test */
3137 static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id,
3138 struct pt_regs *regs)
3140 struct sky2_hw *hw = dev_id;
3141 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
3146 if (status & Y2_IS_IRQ_SW) {
3147 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
3150 sky2_write32(hw, B0_Y2_SP_ICR, 2);
3152 sky2_read32(hw, B0_IMSK);
3156 /* Test interrupt path by forcing a a software IRQ */
3157 static int __devinit sky2_test_msi(struct sky2_hw *hw)
3159 struct pci_dev *pdev = hw->pdev;
3162 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
3164 err = request_irq(pdev->irq, sky2_test_intr, SA_SHIRQ, DRV_NAME, hw);
3166 printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
3167 pci_name(pdev), pdev->irq);
3171 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
3174 for (i = 0; i < 10; i++) {
3182 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
3184 sky2_write32(hw, B0_IMSK, 0);
3186 free_irq(pdev->irq, hw);
3191 static int __devinit sky2_probe(struct pci_dev *pdev,
3192 const struct pci_device_id *ent)
3194 struct net_device *dev, *dev1 = NULL;
3196 int err, pm_cap, using_dac = 0;
3198 err = pci_enable_device(pdev);
3200 printk(KERN_ERR PFX "%s cannot enable PCI device\n",
3205 err = pci_request_regions(pdev, DRV_NAME);
3207 printk(KERN_ERR PFX "%s cannot obtain PCI resources\n",
3212 pci_set_master(pdev);
3214 /* Find power-management capability. */
3215 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
3217 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
3220 goto err_out_free_regions;
3223 if (sizeof(dma_addr_t) > sizeof(u32) &&
3224 !(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK))) {
3226 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
3228 printk(KERN_ERR PFX "%s unable to obtain 64 bit DMA "
3229 "for consistent allocations\n", pci_name(pdev));
3230 goto err_out_free_regions;
3234 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3236 printk(KERN_ERR PFX "%s no usable DMA configuration\n",
3238 goto err_out_free_regions;
3243 /* byte swap descriptors in hardware */
3247 pci_read_config_dword(pdev, PCI_DEV_REG2, ®);
3248 reg |= PCI_REV_DESC;
3249 pci_write_config_dword(pdev, PCI_DEV_REG2, reg);
3254 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
3256 printk(KERN_ERR PFX "%s: cannot allocate hardware struct\n",
3258 goto err_out_free_regions;
3263 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
3265 printk(KERN_ERR PFX "%s: cannot map device registers\n",
3267 goto err_out_free_hw;
3269 hw->pm_cap = pm_cap;
3271 /* ring for status responses */
3272 hw->st_le = pci_alloc_consistent(hw->pdev, STATUS_LE_BYTES,
3275 goto err_out_iounmap;
3277 err = sky2_reset(hw);
3279 goto err_out_iounmap;
3281 printk(KERN_INFO PFX "v%s addr 0x%lx irq %d Yukon-%s (0x%x) rev %d\n",
3282 DRV_VERSION, pci_resource_start(pdev, 0), pdev->irq,
3283 yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
3284 hw->chip_id, hw->chip_rev);
3286 dev = sky2_init_netdev(hw, 0, using_dac);
3288 goto err_out_free_pci;
3290 err = register_netdev(dev);
3292 printk(KERN_ERR PFX "%s: cannot register net device\n",
3294 goto err_out_free_netdev;
3297 sky2_show_addr(dev);
3299 if (hw->ports > 1 && (dev1 = sky2_init_netdev(hw, 1, using_dac))) {
3300 if (register_netdev(dev1) == 0)
3301 sky2_show_addr(dev1);
3303 /* Failure to register second port need not be fatal */
3304 printk(KERN_WARNING PFX
3305 "register of second port failed\n");
3311 if (!disable_msi && pci_enable_msi(pdev) == 0) {
3312 err = sky2_test_msi(hw);
3313 if (err == -EOPNOTSUPP) {
3314 /* MSI test failed, go back to INTx mode */
3315 printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
3316 "switching to INTx mode. Please report this failure to "
3317 "the PCI maintainer and include system chipset information.\n",
3319 pci_disable_msi(pdev);
3322 goto err_out_unregister;
3325 err = request_irq(pdev->irq, sky2_intr, SA_SHIRQ | SA_SAMPLE_RANDOM,
3328 printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
3329 pci_name(pdev), pdev->irq);
3330 goto err_out_unregister;
3333 hw->intr_mask = Y2_IS_BASE;
3334 sky2_write32(hw, B0_IMSK, hw->intr_mask);
3336 pci_set_drvdata(pdev, hw);
3342 pci_disable_msi(pdev);
3344 unregister_netdev(dev1);
3347 unregister_netdev(dev);
3348 err_out_free_netdev:
3351 sky2_write8(hw, B0_CTST, CS_RST_SET);
3352 pci_free_consistent(hw->pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
3357 err_out_free_regions:
3358 pci_release_regions(pdev);
3359 pci_disable_device(pdev);
3364 static void __devexit sky2_remove(struct pci_dev *pdev)
3366 struct sky2_hw *hw = pci_get_drvdata(pdev);
3367 struct net_device *dev0, *dev1;
3375 unregister_netdev(dev1);
3376 unregister_netdev(dev0);
3378 sky2_write32(hw, B0_IMSK, 0);
3379 sky2_set_power_state(hw, PCI_D3hot);
3380 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
3381 sky2_write8(hw, B0_CTST, CS_RST_SET);
3382 sky2_read8(hw, B0_CTST);
3384 free_irq(pdev->irq, hw);
3386 pci_disable_msi(pdev);
3387 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
3388 pci_release_regions(pdev);
3389 pci_disable_device(pdev);
3397 pci_set_drvdata(pdev, NULL);
3401 static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
3403 struct sky2_hw *hw = pci_get_drvdata(pdev);
3406 for (i = 0; i < 2; i++) {
3407 struct net_device *dev = hw->dev[i];
3410 if (!netif_running(dev))
3414 netif_device_detach(dev);
3418 return sky2_set_power_state(hw, pci_choose_state(pdev, state));
3421 static int sky2_resume(struct pci_dev *pdev)
3423 struct sky2_hw *hw = pci_get_drvdata(pdev);
3426 pci_restore_state(pdev);
3427 pci_enable_wake(pdev, PCI_D0, 0);
3428 err = sky2_set_power_state(hw, PCI_D0);
3432 err = sky2_reset(hw);
3436 for (i = 0; i < 2; i++) {
3437 struct net_device *dev = hw->dev[i];
3438 if (dev && netif_running(dev)) {
3439 netif_device_attach(dev);
3442 printk(KERN_ERR PFX "%s: could not up: %d\n",
3454 static struct pci_driver sky2_driver = {
3456 .id_table = sky2_id_table,
3457 .probe = sky2_probe,
3458 .remove = __devexit_p(sky2_remove),
3460 .suspend = sky2_suspend,
3461 .resume = sky2_resume,
3465 static int __init sky2_init_module(void)
3467 return pci_register_driver(&sky2_driver);
3470 static void __exit sky2_cleanup_module(void)
3472 pci_unregister_driver(&sky2_driver);
3475 module_init(sky2_init_module);
3476 module_exit(sky2_cleanup_module);
3478 MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
3479 MODULE_AUTHOR("Stephen Hemminger <shemminger@osdl.org>");
3480 MODULE_LICENSE("GPL");
3481 MODULE_VERSION(DRV_VERSION);