2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 #include <linux/crc32.h>
26 #include <linux/kernel.h>
27 #include <linux/version.h>
28 #include <linux/module.h>
29 #include <linux/netdevice.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/etherdevice.h>
32 #include <linux/ethtool.h>
33 #include <linux/pci.h>
36 #include <linux/tcp.h>
38 #include <linux/delay.h>
39 #include <linux/workqueue.h>
40 #include <linux/if_vlan.h>
41 #include <linux/prefetch.h>
42 #include <linux/debugfs.h>
43 #include <linux/mii.h>
47 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
48 #define SKY2_VLAN_TAG_USED 1
53 #define DRV_NAME "sky2"
54 #define DRV_VERSION "1.18"
55 #define PFX DRV_NAME " "
58 * The Yukon II chipset takes 64 bit command blocks (called list elements)
59 * that are organized into three (receive, transmit, status) different rings
63 #define RX_LE_SIZE 1024
64 #define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
65 #define RX_MAX_PENDING (RX_LE_SIZE/6 - 2)
66 #define RX_DEF_PENDING RX_MAX_PENDING
67 #define RX_SKB_ALIGN 8
69 #define TX_RING_SIZE 512
70 #define TX_DEF_PENDING (TX_RING_SIZE - 1)
71 #define TX_MIN_PENDING 64
72 #define MAX_SKB_TX_LE (4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS)
74 #define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
75 #define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
76 #define TX_WATCHDOG (5 * HZ)
77 #define NAPI_WEIGHT 64
78 #define PHY_RETRIES 1000
80 #define SKY2_EEPROM_MAGIC 0x9955aabb
83 #define RING_NEXT(x,s) (((x)+1) & ((s)-1))
85 static const u32 default_msg =
86 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
87 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
88 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
90 static int debug = -1; /* defaults above */
91 module_param(debug, int, 0);
92 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
94 static int copybreak __read_mostly = 128;
95 module_param(copybreak, int, 0);
96 MODULE_PARM_DESC(copybreak, "Receive copy threshold");
98 static int disable_msi = 0;
99 module_param(disable_msi, int, 0);
100 MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
102 static const struct pci_device_id sky2_id_table[] = {
103 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, /* SK-9Sxx */
104 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */
105 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */
106 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */
107 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B02) }, /* DGE-560SX */
108 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B03) }, /* DGE-550T */
109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, /* 88E8021 */
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, /* 88E8022 */
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, /* 88E8061 */
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) }, /* 88E8062 */
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) }, /* 88E8021 */
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) }, /* 88E8022 */
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) }, /* 88E8061 */
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) }, /* 88E8062 */
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, /* 88E8035 */
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, /* 88E8036 */
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, /* 88E8038 */
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) }, /* 88E8039 */
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4354) }, /* 88E8040 */
122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4356) }, /* 88EC033 */
123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x435A) }, /* 88E8048 */
124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, /* 88E8052 */
125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, /* 88E8050 */
126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, /* 88E8053 */
127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, /* 88E8055 */
128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) }, /* 88E8056 */
129 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4365) }, /* 88E8070 */
130 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) }, /* 88EC036 */
131 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) }, /* 88EC032 */
132 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) }, /* 88EC034 */
133 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) }, /* 88EC042 */
134 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436A) }, /* 88E8058 */
135 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436B) }, /* 88E8071 */
139 MODULE_DEVICE_TABLE(pci, sky2_id_table);
141 /* Avoid conditionals by using array */
142 static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
143 static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
144 static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
146 /* This driver supports yukon2 chipset only */
147 static const char *yukon2_name[] = {
149 "EC Ultra", /* 0xb4 */
150 "Extreme", /* 0xb5 */
156 static void sky2_set_multicast(struct net_device *dev);
158 /* Access to external PHY */
159 static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
163 gma_write16(hw, port, GM_SMI_DATA, val);
164 gma_write16(hw, port, GM_SMI_CTRL,
165 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
167 for (i = 0; i < PHY_RETRIES; i++) {
168 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
173 printk(KERN_WARNING PFX "%s: phy write timeout\n", hw->dev[port]->name);
177 static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
181 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
182 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
184 for (i = 0; i < PHY_RETRIES; i++) {
185 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL) {
186 *val = gma_read16(hw, port, GM_SMI_DATA);
196 static u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
200 if (__gm_phy_read(hw, port, reg, &v) != 0)
201 printk(KERN_WARNING PFX "%s: phy read timeout\n", hw->dev[port]->name);
206 static void sky2_power_on(struct sky2_hw *hw)
208 /* switch power to VCC (WA for VAUX problem) */
209 sky2_write8(hw, B0_POWER_CTRL,
210 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
212 /* disable Core Clock Division, */
213 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
215 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
216 /* enable bits are inverted */
217 sky2_write8(hw, B2_Y2_CLK_GATE,
218 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
219 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
220 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
222 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
224 if (hw->flags & SKY2_HW_ADV_POWER_CTL) {
227 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
229 reg = sky2_pci_read32(hw, PCI_DEV_REG4);
230 /* set all bits to 0 except bits 15..12 and 8 */
231 reg &= P_ASPM_CONTROL_MSK;
232 sky2_pci_write32(hw, PCI_DEV_REG4, reg);
234 reg = sky2_pci_read32(hw, PCI_DEV_REG5);
235 /* set all bits to 0 except bits 28 & 27 */
236 reg &= P_CTL_TIM_VMAIN_AV_MSK;
237 sky2_pci_write32(hw, PCI_DEV_REG5, reg);
239 sky2_pci_write32(hw, PCI_CFG_REG_1, 0);
241 /* Enable workaround for dev 4.107 on Yukon-Ultra & Extreme */
242 reg = sky2_read32(hw, B2_GP_IO);
243 reg |= GLB_GPIO_STAT_RACE_DIS;
244 sky2_write32(hw, B2_GP_IO, reg);
246 sky2_read32(hw, B2_GP_IO);
250 static void sky2_power_aux(struct sky2_hw *hw)
252 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
253 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
255 /* enable bits are inverted */
256 sky2_write8(hw, B2_Y2_CLK_GATE,
257 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
258 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
259 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
261 /* switch power to VAUX */
262 if (sky2_read16(hw, B0_CTST) & Y2_VAUX_AVAIL)
263 sky2_write8(hw, B0_POWER_CTRL,
264 (PC_VAUX_ENA | PC_VCC_ENA |
265 PC_VAUX_ON | PC_VCC_OFF));
268 static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
272 /* disable all GMAC IRQ's */
273 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
274 /* disable PHY IRQs */
275 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
277 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
278 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
279 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
280 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
282 reg = gma_read16(hw, port, GM_RX_CTRL);
283 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
284 gma_write16(hw, port, GM_RX_CTRL, reg);
287 /* flow control to advertise bits */
288 static const u16 copper_fc_adv[] = {
290 [FC_TX] = PHY_M_AN_ASP,
291 [FC_RX] = PHY_M_AN_PC,
292 [FC_BOTH] = PHY_M_AN_PC | PHY_M_AN_ASP,
295 /* flow control to advertise bits when using 1000BaseX */
296 static const u16 fiber_fc_adv[] = {
297 [FC_BOTH] = PHY_M_P_BOTH_MD_X,
298 [FC_TX] = PHY_M_P_ASYM_MD_X,
299 [FC_RX] = PHY_M_P_SYM_MD_X,
300 [FC_NONE] = PHY_M_P_NO_PAUSE_X,
303 /* flow control to GMA disable bits */
304 static const u16 gm_fc_disable[] = {
305 [FC_NONE] = GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS,
306 [FC_TX] = GM_GPCR_FC_RX_DIS,
307 [FC_RX] = GM_GPCR_FC_TX_DIS,
312 static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
314 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
315 u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg;
317 if (sky2->autoneg == AUTONEG_ENABLE &&
318 !(hw->flags & SKY2_HW_NEWER_PHY)) {
319 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
321 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
323 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
325 /* on PHY 88E1040 Rev.D0 (and newer) downshift control changed */
326 if (hw->chip_id == CHIP_ID_YUKON_EC)
327 /* set downshift counter to 3x and enable downshift */
328 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
330 /* set master & slave downshift counter to 1x */
331 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
333 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
336 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
337 if (sky2_is_copper(hw)) {
338 if (!(hw->flags & SKY2_HW_GIGABIT)) {
339 /* enable automatic crossover */
340 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
342 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
343 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
346 /* Enable Class A driver for FE+ A0 */
347 spec = gm_phy_read(hw, port, PHY_MARV_FE_SPEC_2);
348 spec |= PHY_M_FESC_SEL_CL_A;
349 gm_phy_write(hw, port, PHY_MARV_FE_SPEC_2, spec);
352 /* disable energy detect */
353 ctrl &= ~PHY_M_PC_EN_DET_MSK;
355 /* enable automatic crossover */
356 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
358 /* downshift on PHY 88E1112 and 88E1149 is changed */
359 if (sky2->autoneg == AUTONEG_ENABLE
360 && (hw->flags & SKY2_HW_NEWER_PHY)) {
361 /* set downshift counter to 3x and enable downshift */
362 ctrl &= ~PHY_M_PC_DSC_MSK;
363 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
367 /* workaround for deviation #4.88 (CRC errors) */
368 /* disable Automatic Crossover */
370 ctrl &= ~PHY_M_PC_MDIX_MSK;
373 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
375 /* special setup for PHY 88E1112 Fiber */
376 if (hw->chip_id == CHIP_ID_YUKON_XL && (hw->flags & SKY2_HW_FIBRE_PHY)) {
377 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
379 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
380 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
381 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
382 ctrl &= ~PHY_M_MAC_MD_MSK;
383 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
384 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
386 if (hw->pmd_type == 'P') {
387 /* select page 1 to access Fiber registers */
388 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
390 /* for SFP-module set SIGDET polarity to low */
391 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
392 ctrl |= PHY_M_FIB_SIGD_POL;
393 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
396 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
404 if (sky2->autoneg == AUTONEG_ENABLE) {
405 if (sky2_is_copper(hw)) {
406 if (sky2->advertising & ADVERTISED_1000baseT_Full)
407 ct1000 |= PHY_M_1000C_AFD;
408 if (sky2->advertising & ADVERTISED_1000baseT_Half)
409 ct1000 |= PHY_M_1000C_AHD;
410 if (sky2->advertising & ADVERTISED_100baseT_Full)
411 adv |= PHY_M_AN_100_FD;
412 if (sky2->advertising & ADVERTISED_100baseT_Half)
413 adv |= PHY_M_AN_100_HD;
414 if (sky2->advertising & ADVERTISED_10baseT_Full)
415 adv |= PHY_M_AN_10_FD;
416 if (sky2->advertising & ADVERTISED_10baseT_Half)
417 adv |= PHY_M_AN_10_HD;
419 adv |= copper_fc_adv[sky2->flow_mode];
420 } else { /* special defines for FIBER (88E1040S only) */
421 if (sky2->advertising & ADVERTISED_1000baseT_Full)
422 adv |= PHY_M_AN_1000X_AFD;
423 if (sky2->advertising & ADVERTISED_1000baseT_Half)
424 adv |= PHY_M_AN_1000X_AHD;
426 adv |= fiber_fc_adv[sky2->flow_mode];
429 /* Restart Auto-negotiation */
430 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
432 /* forced speed/duplex settings */
433 ct1000 = PHY_M_1000C_MSE;
435 /* Disable auto update for duplex flow control and speed */
436 reg |= GM_GPCR_AU_ALL_DIS;
438 switch (sky2->speed) {
440 ctrl |= PHY_CT_SP1000;
441 reg |= GM_GPCR_SPEED_1000;
444 ctrl |= PHY_CT_SP100;
445 reg |= GM_GPCR_SPEED_100;
449 if (sky2->duplex == DUPLEX_FULL) {
450 reg |= GM_GPCR_DUP_FULL;
451 ctrl |= PHY_CT_DUP_MD;
452 } else if (sky2->speed < SPEED_1000)
453 sky2->flow_mode = FC_NONE;
456 reg |= gm_fc_disable[sky2->flow_mode];
458 /* Forward pause packets to GMAC? */
459 if (sky2->flow_mode & FC_RX)
460 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
462 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
465 gma_write16(hw, port, GM_GP_CTRL, reg);
467 if (hw->flags & SKY2_HW_GIGABIT)
468 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
470 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
471 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
473 /* Setup Phy LED's */
474 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
477 switch (hw->chip_id) {
478 case CHIP_ID_YUKON_FE:
479 /* on 88E3082 these bits are at 11..9 (shifted left) */
480 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
482 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
484 /* delete ACT LED control bits */
485 ctrl &= ~PHY_M_FELP_LED1_MSK;
486 /* change ACT LED control to blink mode */
487 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
488 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
491 case CHIP_ID_YUKON_FE_P:
492 /* Enable Link Partner Next Page */
493 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
494 ctrl |= PHY_M_PC_ENA_LIP_NP;
496 /* disable Energy Detect and enable scrambler */
497 ctrl &= ~(PHY_M_PC_ENA_ENE_DT | PHY_M_PC_DIS_SCRAMB);
498 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
500 /* set LED2 -> ACT, LED1 -> LINK, LED0 -> SPEED */
501 ctrl = PHY_M_FELP_LED2_CTRL(LED_PAR_CTRL_ACT_BL) |
502 PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_LINK) |
503 PHY_M_FELP_LED0_CTRL(LED_PAR_CTRL_SPEED);
505 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
508 case CHIP_ID_YUKON_XL:
509 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
511 /* select page 3 to access LED control register */
512 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
514 /* set LED Function Control register */
515 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
516 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
517 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
518 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
519 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
521 /* set Polarity Control register */
522 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
523 (PHY_M_POLC_LS1_P_MIX(4) |
524 PHY_M_POLC_IS0_P_MIX(4) |
525 PHY_M_POLC_LOS_CTRL(2) |
526 PHY_M_POLC_INIT_CTRL(2) |
527 PHY_M_POLC_STA1_CTRL(2) |
528 PHY_M_POLC_STA0_CTRL(2)));
530 /* restore page register */
531 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
534 case CHIP_ID_YUKON_EC_U:
535 case CHIP_ID_YUKON_EX:
536 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
538 /* select page 3 to access LED control register */
539 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
541 /* set LED Function Control register */
542 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
543 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
544 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
545 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
546 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
548 /* set Blink Rate in LED Timer Control Register */
549 gm_phy_write(hw, port, PHY_MARV_INT_MASK,
550 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
551 /* restore page register */
552 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
556 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
557 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
558 /* turn off the Rx LED (LED_RX) */
559 ledover &= ~PHY_M_LED_MO_RX;
562 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
563 hw->chip_rev == CHIP_REV_YU_EC_U_A1) {
564 /* apply fixes in PHY AFE */
565 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
567 /* increase differential signal amplitude in 10BASE-T */
568 gm_phy_write(hw, port, 0x18, 0xaa99);
569 gm_phy_write(hw, port, 0x17, 0x2011);
571 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
572 gm_phy_write(hw, port, 0x18, 0xa204);
573 gm_phy_write(hw, port, 0x17, 0x2002);
575 /* set page register to 0 */
576 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
577 } else if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
578 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
579 /* apply workaround for integrated resistors calibration */
580 gm_phy_write(hw, port, PHY_MARV_PAGE_ADDR, 17);
581 gm_phy_write(hw, port, PHY_MARV_PAGE_DATA, 0x3f60);
582 } else if (hw->chip_id != CHIP_ID_YUKON_EX) {
583 /* no effect on Yukon-XL */
584 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
586 if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
587 /* turn on 100 Mbps LED (LED_LINK100) */
588 ledover |= PHY_M_LED_MO_100;
592 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
596 /* Enable phy interrupt on auto-negotiation complete (or link up) */
597 if (sky2->autoneg == AUTONEG_ENABLE)
598 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
600 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
603 static void sky2_phy_power(struct sky2_hw *hw, unsigned port, int onoff)
606 static const u32 phy_power[]
607 = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
609 /* looks like this XL is back asswards .. */
610 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
613 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
614 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
616 /* Turn off phy power saving */
617 reg1 &= ~phy_power[port];
619 reg1 |= phy_power[port];
621 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
622 sky2_pci_read32(hw, PCI_DEV_REG1);
623 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
627 /* Force a renegotiation */
628 static void sky2_phy_reinit(struct sky2_port *sky2)
630 spin_lock_bh(&sky2->phy_lock);
631 sky2_phy_init(sky2->hw, sky2->port);
632 spin_unlock_bh(&sky2->phy_lock);
635 /* Put device in state to listen for Wake On Lan */
636 static void sky2_wol_init(struct sky2_port *sky2)
638 struct sky2_hw *hw = sky2->hw;
639 unsigned port = sky2->port;
640 enum flow_control save_mode;
644 /* Bring hardware out of reset */
645 sky2_write16(hw, B0_CTST, CS_RST_CLR);
646 sky2_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
648 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
649 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
652 * sky2_reset will re-enable on resume
654 save_mode = sky2->flow_mode;
655 ctrl = sky2->advertising;
657 sky2->advertising &= ~(ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full);
658 sky2->flow_mode = FC_NONE;
659 sky2_phy_power(hw, port, 1);
660 sky2_phy_reinit(sky2);
662 sky2->flow_mode = save_mode;
663 sky2->advertising = ctrl;
665 /* Set GMAC to no flow control and auto update for speed/duplex */
666 gma_write16(hw, port, GM_GP_CTRL,
667 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
668 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
670 /* Set WOL address */
671 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
672 sky2->netdev->dev_addr, ETH_ALEN);
674 /* Turn on appropriate WOL control bits */
675 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
677 if (sky2->wol & WAKE_PHY)
678 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
680 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
682 if (sky2->wol & WAKE_MAGIC)
683 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
685 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;;
687 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
688 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
690 /* Turn on legacy PCI-Express PME mode */
691 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
692 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
693 reg1 |= PCI_Y2_PME_LEGACY;
694 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
695 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
698 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
702 static void sky2_set_tx_stfwd(struct sky2_hw *hw, unsigned port)
704 struct net_device *dev = hw->dev[port];
706 if (dev->mtu <= ETH_DATA_LEN)
707 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
708 TX_JUMBO_DIS | TX_STFW_ENA);
710 else if (hw->chip_id != CHIP_ID_YUKON_EC_U)
711 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
712 TX_STFW_ENA | TX_JUMBO_ENA);
714 /* set Tx GMAC FIFO Almost Empty Threshold */
715 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR),
716 (ECU_JUMBO_WM << 16) | ECU_AE_THR);
718 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
719 TX_JUMBO_ENA | TX_STFW_DIS);
721 /* Can't do offload because of lack of store/forward */
722 dev->features &= ~(NETIF_F_TSO | NETIF_F_SG | NETIF_F_ALL_CSUM);
726 static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
728 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
732 const u8 *addr = hw->dev[port]->dev_addr;
734 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
735 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
737 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
739 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
740 /* WA DEV_472 -- looks like crossed wires on port 2 */
741 /* clear GMAC 1 Control reset */
742 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
744 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
745 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
746 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
747 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
748 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
751 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
753 /* Enable Transmit FIFO Underrun */
754 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
756 spin_lock_bh(&sky2->phy_lock);
757 sky2_phy_init(hw, port);
758 spin_unlock_bh(&sky2->phy_lock);
761 reg = gma_read16(hw, port, GM_PHY_ADDR);
762 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
764 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
765 gma_read16(hw, port, i);
766 gma_write16(hw, port, GM_PHY_ADDR, reg);
768 /* transmit control */
769 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
771 /* receive control reg: unicast + multicast + no FCS */
772 gma_write16(hw, port, GM_RX_CTRL,
773 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
775 /* transmit flow control */
776 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
778 /* transmit parameter */
779 gma_write16(hw, port, GM_TX_PARAM,
780 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
781 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
782 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
783 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
785 /* serial mode register */
786 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
787 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
789 if (hw->dev[port]->mtu > ETH_DATA_LEN)
790 reg |= GM_SMOD_JUMBO_ENA;
792 gma_write16(hw, port, GM_SERIAL_MODE, reg);
794 /* virtual address for data */
795 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
797 /* physical address: used for pause frames */
798 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
800 /* ignore counter overflows */
801 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
802 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
803 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
805 /* Configure Rx MAC FIFO */
806 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
807 rx_reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
808 if (hw->chip_id == CHIP_ID_YUKON_EX ||
809 hw->chip_id == CHIP_ID_YUKON_FE_P)
810 rx_reg |= GMF_RX_OVER_ON;
812 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), rx_reg);
814 /* Flush Rx MAC FIFO on any flow control or error */
815 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
817 /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */
818 reg = RX_GMF_FL_THR_DEF + 1;
819 /* Another magic mystery workaround from sk98lin */
820 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
821 hw->chip_rev == CHIP_REV_YU_FE2_A0)
823 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), reg);
825 /* Configure Tx MAC FIFO */
826 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
827 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
829 /* On chips without ram buffer, pause is controled by MAC level */
830 if (sky2_read8(hw, B2_E_0) == 0) {
831 sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8);
832 sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
834 sky2_set_tx_stfwd(hw, port);
839 /* Assign Ram Buffer allocation to queue */
840 static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 space)
844 /* convert from K bytes to qwords used for hw register */
847 end = start + space - 1;
849 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
850 sky2_write32(hw, RB_ADDR(q, RB_START), start);
851 sky2_write32(hw, RB_ADDR(q, RB_END), end);
852 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
853 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
855 if (q == Q_R1 || q == Q_R2) {
856 u32 tp = space - space/4;
858 /* On receive queue's set the thresholds
859 * give receiver priority when > 3/4 full
860 * send pause when down to 2K
862 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
863 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
866 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
867 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
869 /* Enable store & forward on Tx queue's because
870 * Tx FIFO is only 1K on Yukon
872 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
875 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
876 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
879 /* Setup Bus Memory Interface */
880 static void sky2_qset(struct sky2_hw *hw, u16 q)
882 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
883 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
884 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
885 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
888 /* Setup prefetch unit registers. This is the interface between
889 * hardware and driver list elements
891 static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
894 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
895 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
896 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32);
897 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr);
898 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
899 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
901 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
904 static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2)
906 struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod;
908 sky2->tx_prod = RING_NEXT(sky2->tx_prod, TX_RING_SIZE);
913 static inline struct tx_ring_info *tx_le_re(struct sky2_port *sky2,
914 struct sky2_tx_le *le)
916 return sky2->tx_ring + (le - sky2->tx_le);
919 /* Update chip's next pointer */
920 static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
922 /* Make sure write' to descriptors are complete before we tell hardware */
924 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
926 /* Synchronize I/O on since next processor may write to tail */
931 static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
933 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
934 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
939 /* Build description to hardware for one receive segment */
940 static void sky2_rx_add(struct sky2_port *sky2, u8 op,
941 dma_addr_t map, unsigned len)
943 struct sky2_rx_le *le;
944 u32 hi = upper_32_bits(map);
946 if (sky2->rx_addr64 != hi) {
947 le = sky2_next_rx(sky2);
948 le->addr = cpu_to_le32(hi);
949 le->opcode = OP_ADDR64 | HW_OWNER;
950 sky2->rx_addr64 = upper_32_bits(map + len);
953 le = sky2_next_rx(sky2);
954 le->addr = cpu_to_le32((u32) map);
955 le->length = cpu_to_le16(len);
956 le->opcode = op | HW_OWNER;
959 /* Build description to hardware for one possibly fragmented skb */
960 static void sky2_rx_submit(struct sky2_port *sky2,
961 const struct rx_ring_info *re)
965 sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size);
967 for (i = 0; i < skb_shinfo(re->skb)->nr_frags; i++)
968 sky2_rx_add(sky2, OP_BUFFER, re->frag_addr[i], PAGE_SIZE);
972 static void sky2_rx_map_skb(struct pci_dev *pdev, struct rx_ring_info *re,
975 struct sk_buff *skb = re->skb;
978 re->data_addr = pci_map_single(pdev, skb->data, size, PCI_DMA_FROMDEVICE);
979 pci_unmap_len_set(re, data_size, size);
981 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
982 re->frag_addr[i] = pci_map_page(pdev,
983 skb_shinfo(skb)->frags[i].page,
984 skb_shinfo(skb)->frags[i].page_offset,
985 skb_shinfo(skb)->frags[i].size,
989 static void sky2_rx_unmap_skb(struct pci_dev *pdev, struct rx_ring_info *re)
991 struct sk_buff *skb = re->skb;
994 pci_unmap_single(pdev, re->data_addr, pci_unmap_len(re, data_size),
997 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
998 pci_unmap_page(pdev, re->frag_addr[i],
999 skb_shinfo(skb)->frags[i].size,
1000 PCI_DMA_FROMDEVICE);
1003 /* Tell chip where to start receive checksum.
1004 * Actually has two checksums, but set both same to avoid possible byte
1007 static void rx_set_checksum(struct sky2_port *sky2)
1009 struct sky2_rx_le *le = sky2_next_rx(sky2);
1011 le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN);
1013 le->opcode = OP_TCPSTART | HW_OWNER;
1015 sky2_write32(sky2->hw,
1016 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
1017 sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
1021 * The RX Stop command will not work for Yukon-2 if the BMU does not
1022 * reach the end of packet and since we can't make sure that we have
1023 * incoming data, we must reset the BMU while it is not doing a DMA
1024 * transfer. Since it is possible that the RX path is still active,
1025 * the RX RAM buffer will be stopped first, so any possible incoming
1026 * data will not trigger a DMA. After the RAM buffer is stopped, the
1027 * BMU is polled until any DMA in progress is ended and only then it
1030 static void sky2_rx_stop(struct sky2_port *sky2)
1032 struct sky2_hw *hw = sky2->hw;
1033 unsigned rxq = rxqaddr[sky2->port];
1036 /* disable the RAM Buffer receive queue */
1037 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
1039 for (i = 0; i < 0xffff; i++)
1040 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
1041 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
1044 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
1045 sky2->netdev->name);
1047 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
1049 /* reset the Rx prefetch unit */
1050 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
1054 /* Clean out receive buffer area, assumes receiver hardware stopped */
1055 static void sky2_rx_clean(struct sky2_port *sky2)
1059 memset(sky2->rx_le, 0, RX_LE_BYTES);
1060 for (i = 0; i < sky2->rx_pending; i++) {
1061 struct rx_ring_info *re = sky2->rx_ring + i;
1064 sky2_rx_unmap_skb(sky2->hw->pdev, re);
1071 /* Basic MII support */
1072 static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1074 struct mii_ioctl_data *data = if_mii(ifr);
1075 struct sky2_port *sky2 = netdev_priv(dev);
1076 struct sky2_hw *hw = sky2->hw;
1077 int err = -EOPNOTSUPP;
1079 if (!netif_running(dev))
1080 return -ENODEV; /* Phy still in reset */
1084 data->phy_id = PHY_ADDR_MARV;
1090 spin_lock_bh(&sky2->phy_lock);
1091 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
1092 spin_unlock_bh(&sky2->phy_lock);
1094 data->val_out = val;
1099 if (!capable(CAP_NET_ADMIN))
1102 spin_lock_bh(&sky2->phy_lock);
1103 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
1105 spin_unlock_bh(&sky2->phy_lock);
1111 #ifdef SKY2_VLAN_TAG_USED
1112 static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
1114 struct sky2_port *sky2 = netdev_priv(dev);
1115 struct sky2_hw *hw = sky2->hw;
1116 u16 port = sky2->port;
1118 netif_tx_lock_bh(dev);
1119 netif_poll_disable(sky2->hw->dev[0]);
1123 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1125 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1128 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1130 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1134 netif_poll_enable(sky2->hw->dev[0]);
1135 netif_tx_unlock_bh(dev);
1140 * Allocate an skb for receiving. If the MTU is large enough
1141 * make the skb non-linear with a fragment list of pages.
1143 * It appears the hardware has a bug in the FIFO logic that
1144 * cause it to hang if the FIFO gets overrun and the receive buffer
1145 * is not 64 byte aligned. The buffer returned from netdev_alloc_skb is
1146 * aligned except if slab debugging is enabled.
1148 static struct sk_buff *sky2_rx_alloc(struct sky2_port *sky2)
1150 struct sk_buff *skb;
1154 skb = netdev_alloc_skb(sky2->netdev, sky2->rx_data_size + RX_SKB_ALIGN);
1158 p = (unsigned long) skb->data;
1159 skb_reserve(skb, ALIGN(p, RX_SKB_ALIGN) - p);
1161 for (i = 0; i < sky2->rx_nfrags; i++) {
1162 struct page *page = alloc_page(GFP_ATOMIC);
1166 skb_fill_page_desc(skb, i, page, 0, PAGE_SIZE);
1176 static inline void sky2_rx_update(struct sky2_port *sky2, unsigned rxq)
1178 sky2_put_idx(sky2->hw, rxq, sky2->rx_put);
1182 * Allocate and setup receiver buffer pool.
1183 * Normal case this ends up creating one list element for skb
1184 * in the receive ring. Worst case if using large MTU and each
1185 * allocation falls on a different 64 bit region, that results
1186 * in 6 list elements per ring entry.
1187 * One element is used for checksum enable/disable, and one
1188 * extra to avoid wrap.
1190 static int sky2_rx_start(struct sky2_port *sky2)
1192 struct sky2_hw *hw = sky2->hw;
1193 struct rx_ring_info *re;
1194 unsigned rxq = rxqaddr[sky2->port];
1195 unsigned i, size, space, thresh;
1197 sky2->rx_put = sky2->rx_next = 0;
1200 /* On PCI express lowering the watermark gives better performance */
1201 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
1202 sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX);
1204 /* These chips have no ram buffer?
1205 * MAC Rx RAM Read is controlled by hardware */
1206 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
1207 (hw->chip_rev == CHIP_REV_YU_EC_U_A1
1208 || hw->chip_rev == CHIP_REV_YU_EC_U_B0))
1209 sky2_write32(hw, Q_ADDR(rxq, Q_TEST), F_M_RX_RAM_DIS);
1211 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
1213 if (!(hw->flags & SKY2_HW_NEW_LE))
1214 rx_set_checksum(sky2);
1216 /* Space needed for frame data + headers rounded up */
1217 size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8);
1219 /* Stopping point for hardware truncation */
1220 thresh = (size - 8) / sizeof(u32);
1222 /* Account for overhead of skb - to avoid order > 0 allocation */
1223 space = SKB_DATA_ALIGN(size) + NET_SKB_PAD
1224 + sizeof(struct skb_shared_info);
1226 sky2->rx_nfrags = space >> PAGE_SHIFT;
1227 BUG_ON(sky2->rx_nfrags > ARRAY_SIZE(re->frag_addr));
1229 if (sky2->rx_nfrags != 0) {
1230 /* Compute residue after pages */
1231 space = sky2->rx_nfrags << PAGE_SHIFT;
1238 /* Optimize to handle small packets and headers */
1239 if (size < copybreak)
1241 if (size < ETH_HLEN)
1244 sky2->rx_data_size = size;
1247 for (i = 0; i < sky2->rx_pending; i++) {
1248 re = sky2->rx_ring + i;
1250 re->skb = sky2_rx_alloc(sky2);
1254 sky2_rx_map_skb(hw->pdev, re, sky2->rx_data_size);
1255 sky2_rx_submit(sky2, re);
1259 * The receiver hangs if it receives frames larger than the
1260 * packet buffer. As a workaround, truncate oversize frames, but
1261 * the register is limited to 9 bits, so if you do frames > 2052
1262 * you better get the MTU right!
1265 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
1267 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
1268 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1271 /* Tell chip about available buffers */
1272 sky2_rx_update(sky2, rxq);
1275 sky2_rx_clean(sky2);
1279 /* Bring up network interface. */
1280 static int sky2_up(struct net_device *dev)
1282 struct sky2_port *sky2 = netdev_priv(dev);
1283 struct sky2_hw *hw = sky2->hw;
1284 unsigned port = sky2->port;
1286 int cap, err = -ENOMEM;
1287 struct net_device *otherdev = hw->dev[sky2->port^1];
1290 * On dual port PCI-X card, there is an problem where status
1291 * can be received out of order due to split transactions
1293 if (otherdev && netif_running(otherdev) &&
1294 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
1295 struct sky2_port *osky2 = netdev_priv(otherdev);
1298 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
1299 cmd &= ~PCI_X_CMD_MAX_SPLIT;
1300 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd);
1306 if (netif_msg_ifup(sky2))
1307 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
1309 netif_carrier_off(dev);
1311 /* must be power of 2 */
1312 sky2->tx_le = pci_alloc_consistent(hw->pdev,
1314 sizeof(struct sky2_tx_le),
1319 sky2->tx_ring = kcalloc(TX_RING_SIZE, sizeof(struct tx_ring_info),
1323 sky2->tx_prod = sky2->tx_cons = 0;
1325 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1329 memset(sky2->rx_le, 0, RX_LE_BYTES);
1331 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct rx_ring_info),
1336 sky2_phy_power(hw, port, 1);
1338 sky2_mac_init(hw, port);
1340 /* Register is number of 4K blocks on internal RAM buffer. */
1341 ramsize = sky2_read8(hw, B2_E_0) * 4;
1345 pr_debug(PFX "%s: ram buffer %dK\n", dev->name, ramsize);
1347 rxspace = ramsize / 2;
1349 rxspace = 8 + (2*(ramsize - 16))/3;
1351 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1352 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
1354 /* Make sure SyncQ is disabled */
1355 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1359 sky2_qset(hw, txqaddr[port]);
1361 /* This is copied from sk98lin 10.0.5.3; no one tells me about erratta's */
1362 if (hw->chip_id == CHIP_ID_YUKON_EX && hw->chip_rev == CHIP_REV_YU_EX_B0)
1363 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_TEST), F_TX_CHK_AUTO_OFF);
1365 /* Set almost empty threshold */
1366 if (hw->chip_id == CHIP_ID_YUKON_EC_U
1367 && hw->chip_rev == CHIP_REV_YU_EC_U_A0)
1368 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), ECU_TXFF_LEV);
1370 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1373 err = sky2_rx_start(sky2);
1377 /* Enable interrupts from phy/mac for port */
1378 imask = sky2_read32(hw, B0_IMSK);
1379 imask |= portirq_msk[port];
1380 sky2_write32(hw, B0_IMSK, imask);
1386 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1387 sky2->rx_le, sky2->rx_le_map);
1391 pci_free_consistent(hw->pdev,
1392 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1393 sky2->tx_le, sky2->tx_le_map);
1396 kfree(sky2->tx_ring);
1397 kfree(sky2->rx_ring);
1399 sky2->tx_ring = NULL;
1400 sky2->rx_ring = NULL;
1404 /* Modular subtraction in ring */
1405 static inline int tx_dist(unsigned tail, unsigned head)
1407 return (head - tail) & (TX_RING_SIZE - 1);
1410 /* Number of list elements available for next tx */
1411 static inline int tx_avail(const struct sky2_port *sky2)
1413 return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod);
1416 /* Estimate of number of transmit list elements required */
1417 static unsigned tx_le_req(const struct sk_buff *skb)
1421 count = sizeof(dma_addr_t) / sizeof(u32);
1422 count += skb_shinfo(skb)->nr_frags * count;
1424 if (skb_is_gso(skb))
1427 if (skb->ip_summed == CHECKSUM_PARTIAL)
1434 * Put one packet in ring for transmit.
1435 * A single packet can generate multiple list elements, and
1436 * the number of ring elements will probably be less than the number
1437 * of list elements used.
1439 static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
1441 struct sky2_port *sky2 = netdev_priv(dev);
1442 struct sky2_hw *hw = sky2->hw;
1443 struct sky2_tx_le *le = NULL;
1444 struct tx_ring_info *re;
1451 if (unlikely(tx_avail(sky2) < tx_le_req(skb)))
1452 return NETDEV_TX_BUSY;
1454 if (unlikely(netif_msg_tx_queued(sky2)))
1455 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
1456 dev->name, sky2->tx_prod, skb->len);
1458 len = skb_headlen(skb);
1459 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
1460 addr64 = upper_32_bits(mapping);
1462 /* Send high bits if changed or crosses boundary */
1463 if (addr64 != sky2->tx_addr64 ||
1464 upper_32_bits(mapping + len) != sky2->tx_addr64) {
1465 le = get_tx_le(sky2);
1466 le->addr = cpu_to_le32(addr64);
1467 le->opcode = OP_ADDR64 | HW_OWNER;
1468 sky2->tx_addr64 = upper_32_bits(mapping + len);
1471 /* Check for TCP Segmentation Offload */
1472 mss = skb_shinfo(skb)->gso_size;
1475 if (!(hw->flags & SKY2_HW_NEW_LE))
1476 mss += ETH_HLEN + ip_hdrlen(skb) + tcp_hdrlen(skb);
1478 if (mss != sky2->tx_last_mss) {
1479 le = get_tx_le(sky2);
1480 le->addr = cpu_to_le32(mss);
1482 if (hw->flags & SKY2_HW_NEW_LE)
1483 le->opcode = OP_MSS | HW_OWNER;
1485 le->opcode = OP_LRGLEN | HW_OWNER;
1486 sky2->tx_last_mss = mss;
1491 #ifdef SKY2_VLAN_TAG_USED
1492 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1493 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1495 le = get_tx_le(sky2);
1497 le->opcode = OP_VLAN|HW_OWNER;
1499 le->opcode |= OP_VLAN;
1500 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1505 /* Handle TCP checksum offload */
1506 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1507 /* On Yukon EX (some versions) encoding change. */
1508 if (hw->flags & SKY2_HW_AUTO_TX_SUM)
1509 ctrl |= CALSUM; /* auto checksum */
1511 const unsigned offset = skb_transport_offset(skb);
1514 tcpsum = offset << 16; /* sum start */
1515 tcpsum |= offset + skb->csum_offset; /* sum write */
1517 ctrl |= CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1518 if (ip_hdr(skb)->protocol == IPPROTO_UDP)
1521 if (tcpsum != sky2->tx_tcpsum) {
1522 sky2->tx_tcpsum = tcpsum;
1524 le = get_tx_le(sky2);
1525 le->addr = cpu_to_le32(tcpsum);
1526 le->length = 0; /* initial checksum value */
1527 le->ctrl = 1; /* one packet */
1528 le->opcode = OP_TCPLISW | HW_OWNER;
1533 le = get_tx_le(sky2);
1534 le->addr = cpu_to_le32((u32) mapping);
1535 le->length = cpu_to_le16(len);
1537 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
1539 re = tx_le_re(sky2, le);
1541 pci_unmap_addr_set(re, mapaddr, mapping);
1542 pci_unmap_len_set(re, maplen, len);
1544 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1545 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1547 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1548 frag->size, PCI_DMA_TODEVICE);
1549 addr64 = upper_32_bits(mapping);
1550 if (addr64 != sky2->tx_addr64) {
1551 le = get_tx_le(sky2);
1552 le->addr = cpu_to_le32(addr64);
1554 le->opcode = OP_ADDR64 | HW_OWNER;
1555 sky2->tx_addr64 = addr64;
1558 le = get_tx_le(sky2);
1559 le->addr = cpu_to_le32((u32) mapping);
1560 le->length = cpu_to_le16(frag->size);
1562 le->opcode = OP_BUFFER | HW_OWNER;
1564 re = tx_le_re(sky2, le);
1566 pci_unmap_addr_set(re, mapaddr, mapping);
1567 pci_unmap_len_set(re, maplen, frag->size);
1572 if (tx_avail(sky2) <= MAX_SKB_TX_LE)
1573 netif_stop_queue(dev);
1575 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
1577 dev->trans_start = jiffies;
1578 return NETDEV_TX_OK;
1582 * Free ring elements from starting at tx_cons until "done"
1584 * NB: the hardware will tell us about partial completion of multi-part
1585 * buffers so make sure not to free skb to early.
1587 static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
1589 struct net_device *dev = sky2->netdev;
1590 struct pci_dev *pdev = sky2->hw->pdev;
1593 BUG_ON(done >= TX_RING_SIZE);
1595 for (idx = sky2->tx_cons; idx != done;
1596 idx = RING_NEXT(idx, TX_RING_SIZE)) {
1597 struct sky2_tx_le *le = sky2->tx_le + idx;
1598 struct tx_ring_info *re = sky2->tx_ring + idx;
1600 switch(le->opcode & ~HW_OWNER) {
1603 pci_unmap_single(pdev,
1604 pci_unmap_addr(re, mapaddr),
1605 pci_unmap_len(re, maplen),
1609 pci_unmap_page(pdev, pci_unmap_addr(re, mapaddr),
1610 pci_unmap_len(re, maplen),
1615 if (le->ctrl & EOP) {
1616 if (unlikely(netif_msg_tx_done(sky2)))
1617 printk(KERN_DEBUG "%s: tx done %u\n",
1620 sky2->net_stats.tx_packets++;
1621 sky2->net_stats.tx_bytes += re->skb->len;
1623 dev_kfree_skb_any(re->skb);
1624 sky2->tx_next = RING_NEXT(idx, TX_RING_SIZE);
1628 sky2->tx_cons = idx;
1631 if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
1632 netif_wake_queue(dev);
1635 /* Cleanup all untransmitted buffers, assume transmitter not running */
1636 static void sky2_tx_clean(struct net_device *dev)
1638 struct sky2_port *sky2 = netdev_priv(dev);
1640 netif_tx_lock_bh(dev);
1641 sky2_tx_complete(sky2, sky2->tx_prod);
1642 netif_tx_unlock_bh(dev);
1645 /* Network shutdown */
1646 static int sky2_down(struct net_device *dev)
1648 struct sky2_port *sky2 = netdev_priv(dev);
1649 struct sky2_hw *hw = sky2->hw;
1650 unsigned port = sky2->port;
1654 /* Never really got started! */
1658 if (netif_msg_ifdown(sky2))
1659 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1661 /* Stop more packets from being queued */
1662 netif_stop_queue(dev);
1664 /* Disable port IRQ */
1665 imask = sky2_read32(hw, B0_IMSK);
1666 imask &= ~portirq_msk[port];
1667 sky2_write32(hw, B0_IMSK, imask);
1669 sky2_gmac_reset(hw, port);
1671 /* Stop transmitter */
1672 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1673 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1675 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
1676 RB_RST_SET | RB_DIS_OP_MD);
1678 ctrl = gma_read16(hw, port, GM_GP_CTRL);
1679 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
1680 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1682 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1684 /* Workaround shared GMAC reset */
1685 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
1686 && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
1687 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1689 /* Disable Force Sync bit and Enable Alloc bit */
1690 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1691 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1693 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1694 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1695 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1697 /* Reset the PCI FIFO of the async Tx queue */
1698 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1699 BMU_RST_SET | BMU_FIFO_RST);
1701 /* Reset the Tx prefetch units */
1702 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1705 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1709 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1710 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1712 sky2_phy_power(hw, port, 0);
1714 netif_carrier_off(dev);
1716 /* turn off LED's */
1717 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
1719 synchronize_irq(hw->pdev->irq);
1722 sky2_rx_clean(sky2);
1724 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1725 sky2->rx_le, sky2->rx_le_map);
1726 kfree(sky2->rx_ring);
1728 pci_free_consistent(hw->pdev,
1729 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1730 sky2->tx_le, sky2->tx_le_map);
1731 kfree(sky2->tx_ring);
1736 sky2->rx_ring = NULL;
1737 sky2->tx_ring = NULL;
1742 static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1744 if (hw->flags & SKY2_HW_FIBRE_PHY)
1747 if (!(hw->flags & SKY2_HW_GIGABIT)) {
1748 if (aux & PHY_M_PS_SPEED_100)
1754 switch (aux & PHY_M_PS_SPEED_MSK) {
1755 case PHY_M_PS_SPEED_1000:
1757 case PHY_M_PS_SPEED_100:
1764 static void sky2_link_up(struct sky2_port *sky2)
1766 struct sky2_hw *hw = sky2->hw;
1767 unsigned port = sky2->port;
1769 static const char *fc_name[] = {
1777 reg = gma_read16(hw, port, GM_GP_CTRL);
1778 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1779 gma_write16(hw, port, GM_GP_CTRL, reg);
1781 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1783 netif_carrier_on(sky2->netdev);
1785 mod_timer(&hw->watchdog_timer, jiffies + 1);
1787 /* Turn on link LED */
1788 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
1789 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
1791 if (hw->flags & SKY2_HW_NEWER_PHY) {
1792 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
1793 u16 led = PHY_M_LEDC_LOS_CTRL(1); /* link active */
1795 switch(sky2->speed) {
1797 led |= PHY_M_LEDC_INIT_CTRL(7);
1801 led |= PHY_M_LEDC_STA1_CTRL(7);
1805 led |= PHY_M_LEDC_STA0_CTRL(7);
1809 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
1810 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, led);
1811 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
1814 if (netif_msg_link(sky2))
1815 printk(KERN_INFO PFX
1816 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
1817 sky2->netdev->name, sky2->speed,
1818 sky2->duplex == DUPLEX_FULL ? "full" : "half",
1819 fc_name[sky2->flow_status]);
1822 static void sky2_link_down(struct sky2_port *sky2)
1824 struct sky2_hw *hw = sky2->hw;
1825 unsigned port = sky2->port;
1828 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1830 reg = gma_read16(hw, port, GM_GP_CTRL);
1831 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1832 gma_write16(hw, port, GM_GP_CTRL, reg);
1834 netif_carrier_off(sky2->netdev);
1836 /* Turn on link LED */
1837 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
1839 if (netif_msg_link(sky2))
1840 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
1842 sky2_phy_init(hw, port);
1845 static enum flow_control sky2_flow(int rx, int tx)
1848 return tx ? FC_BOTH : FC_RX;
1850 return tx ? FC_TX : FC_NONE;
1853 static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
1855 struct sky2_hw *hw = sky2->hw;
1856 unsigned port = sky2->port;
1859 advert = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
1860 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
1861 if (lpa & PHY_M_AN_RF) {
1862 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
1866 if (!(aux & PHY_M_PS_SPDUP_RES)) {
1867 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
1868 sky2->netdev->name);
1872 sky2->speed = sky2_phy_speed(hw, aux);
1873 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1875 /* Since the pause result bits seem to in different positions on
1876 * different chips. look at registers.
1878 if (hw->flags & SKY2_HW_FIBRE_PHY) {
1879 /* Shift for bits in fiber PHY */
1880 advert &= ~(ADVERTISE_PAUSE_CAP|ADVERTISE_PAUSE_ASYM);
1881 lpa &= ~(LPA_PAUSE_CAP|LPA_PAUSE_ASYM);
1883 if (advert & ADVERTISE_1000XPAUSE)
1884 advert |= ADVERTISE_PAUSE_CAP;
1885 if (advert & ADVERTISE_1000XPSE_ASYM)
1886 advert |= ADVERTISE_PAUSE_ASYM;
1887 if (lpa & LPA_1000XPAUSE)
1888 lpa |= LPA_PAUSE_CAP;
1889 if (lpa & LPA_1000XPAUSE_ASYM)
1890 lpa |= LPA_PAUSE_ASYM;
1893 sky2->flow_status = FC_NONE;
1894 if (advert & ADVERTISE_PAUSE_CAP) {
1895 if (lpa & LPA_PAUSE_CAP)
1896 sky2->flow_status = FC_BOTH;
1897 else if (advert & ADVERTISE_PAUSE_ASYM)
1898 sky2->flow_status = FC_RX;
1899 } else if (advert & ADVERTISE_PAUSE_ASYM) {
1900 if ((lpa & LPA_PAUSE_CAP) && (lpa & LPA_PAUSE_ASYM))
1901 sky2->flow_status = FC_TX;
1904 if (sky2->duplex == DUPLEX_HALF && sky2->speed < SPEED_1000
1905 && !(hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX))
1906 sky2->flow_status = FC_NONE;
1908 if (sky2->flow_status & FC_TX)
1909 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
1911 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1916 /* Interrupt from PHY */
1917 static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
1919 struct net_device *dev = hw->dev[port];
1920 struct sky2_port *sky2 = netdev_priv(dev);
1921 u16 istatus, phystat;
1923 if (!netif_running(dev))
1926 spin_lock(&sky2->phy_lock);
1927 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
1928 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
1930 if (netif_msg_intr(sky2))
1931 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
1932 sky2->netdev->name, istatus, phystat);
1934 if (sky2->autoneg == AUTONEG_ENABLE && (istatus & PHY_M_IS_AN_COMPL)) {
1935 if (sky2_autoneg_done(sky2, phystat) == 0)
1940 if (istatus & PHY_M_IS_LSP_CHANGE)
1941 sky2->speed = sky2_phy_speed(hw, phystat);
1943 if (istatus & PHY_M_IS_DUP_CHANGE)
1945 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1947 if (istatus & PHY_M_IS_LST_CHANGE) {
1948 if (phystat & PHY_M_PS_LINK_UP)
1951 sky2_link_down(sky2);
1954 spin_unlock(&sky2->phy_lock);
1957 /* Transmit timeout is only called if we are running, carrier is up
1958 * and tx queue is full (stopped).
1960 static void sky2_tx_timeout(struct net_device *dev)
1962 struct sky2_port *sky2 = netdev_priv(dev);
1963 struct sky2_hw *hw = sky2->hw;
1965 if (netif_msg_timer(sky2))
1966 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
1968 printk(KERN_DEBUG PFX "%s: transmit ring %u .. %u report=%u done=%u\n",
1969 dev->name, sky2->tx_cons, sky2->tx_prod,
1970 sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
1971 sky2_read16(hw, Q_ADDR(txqaddr[sky2->port], Q_DONE)));
1973 /* can't restart safely under softirq */
1974 schedule_work(&hw->restart_work);
1977 static int sky2_change_mtu(struct net_device *dev, int new_mtu)
1979 struct sky2_port *sky2 = netdev_priv(dev);
1980 struct sky2_hw *hw = sky2->hw;
1981 unsigned port = sky2->port;
1986 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
1989 if (new_mtu > ETH_DATA_LEN &&
1990 (hw->chip_id == CHIP_ID_YUKON_FE ||
1991 hw->chip_id == CHIP_ID_YUKON_FE_P))
1994 if (!netif_running(dev)) {
1999 imask = sky2_read32(hw, B0_IMSK);
2000 sky2_write32(hw, B0_IMSK, 0);
2002 dev->trans_start = jiffies; /* prevent tx timeout */
2003 netif_stop_queue(dev);
2004 netif_poll_disable(hw->dev[0]);
2006 synchronize_irq(hw->pdev->irq);
2008 if (sky2_read8(hw, B2_E_0) == 0)
2009 sky2_set_tx_stfwd(hw, port);
2011 ctl = gma_read16(hw, port, GM_GP_CTRL);
2012 gma_write16(hw, port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
2014 sky2_rx_clean(sky2);
2018 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
2019 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
2021 if (dev->mtu > ETH_DATA_LEN)
2022 mode |= GM_SMOD_JUMBO_ENA;
2024 gma_write16(hw, port, GM_SERIAL_MODE, mode);
2026 sky2_write8(hw, RB_ADDR(rxqaddr[port], RB_CTRL), RB_ENA_OP_MD);
2028 err = sky2_rx_start(sky2);
2029 sky2_write32(hw, B0_IMSK, imask);
2034 gma_write16(hw, port, GM_GP_CTRL, ctl);
2036 netif_poll_enable(hw->dev[0]);
2037 netif_wake_queue(dev);
2043 /* For small just reuse existing skb for next receive */
2044 static struct sk_buff *receive_copy(struct sky2_port *sky2,
2045 const struct rx_ring_info *re,
2048 struct sk_buff *skb;
2050 skb = netdev_alloc_skb(sky2->netdev, length + 2);
2052 skb_reserve(skb, 2);
2053 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->data_addr,
2054 length, PCI_DMA_FROMDEVICE);
2055 skb_copy_from_linear_data(re->skb, skb->data, length);
2056 skb->ip_summed = re->skb->ip_summed;
2057 skb->csum = re->skb->csum;
2058 pci_dma_sync_single_for_device(sky2->hw->pdev, re->data_addr,
2059 length, PCI_DMA_FROMDEVICE);
2060 re->skb->ip_summed = CHECKSUM_NONE;
2061 skb_put(skb, length);
2066 /* Adjust length of skb with fragments to match received data */
2067 static void skb_put_frags(struct sk_buff *skb, unsigned int hdr_space,
2068 unsigned int length)
2073 /* put header into skb */
2074 size = min(length, hdr_space);
2079 num_frags = skb_shinfo(skb)->nr_frags;
2080 for (i = 0; i < num_frags; i++) {
2081 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2084 /* don't need this page */
2085 __free_page(frag->page);
2086 --skb_shinfo(skb)->nr_frags;
2088 size = min(length, (unsigned) PAGE_SIZE);
2091 skb->data_len += size;
2092 skb->truesize += size;
2099 /* Normal packet - take skb from ring element and put in a new one */
2100 static struct sk_buff *receive_new(struct sky2_port *sky2,
2101 struct rx_ring_info *re,
2102 unsigned int length)
2104 struct sk_buff *skb, *nskb;
2105 unsigned hdr_space = sky2->rx_data_size;
2107 /* Don't be tricky about reusing pages (yet) */
2108 nskb = sky2_rx_alloc(sky2);
2109 if (unlikely(!nskb))
2113 sky2_rx_unmap_skb(sky2->hw->pdev, re);
2115 prefetch(skb->data);
2117 sky2_rx_map_skb(sky2->hw->pdev, re, hdr_space);
2119 if (skb_shinfo(skb)->nr_frags)
2120 skb_put_frags(skb, hdr_space, length);
2122 skb_put(skb, length);
2127 * Receive one packet.
2128 * For larger packets, get new buffer.
2130 static struct sk_buff *sky2_receive(struct net_device *dev,
2131 u16 length, u32 status)
2133 struct sky2_port *sky2 = netdev_priv(dev);
2134 struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next;
2135 struct sk_buff *skb = NULL;
2136 u16 count = (status & GMR_FS_LEN) >> 16;
2138 #ifdef SKY2_VLAN_TAG_USED
2139 /* Account for vlan tag */
2140 if (sky2->vlgrp && (status & GMR_FS_VLAN))
2144 if (unlikely(netif_msg_rx_status(sky2)))
2145 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
2146 dev->name, sky2->rx_next, status, length);
2148 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
2149 prefetch(sky2->rx_ring + sky2->rx_next);
2151 if (length < ETH_ZLEN || length > sky2->rx_data_size)
2154 /* This chip has hardware problems that generates bogus status.
2155 * So do only marginal checking and expect higher level protocols
2156 * to handle crap frames.
2158 if (sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
2159 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0 &&
2163 if (status & GMR_FS_ANY_ERR)
2166 if (!(status & GMR_FS_RX_OK))
2169 /* if length reported by DMA does not match PHY, packet was truncated */
2170 if (length != count)
2174 if (length < copybreak)
2175 skb = receive_copy(sky2, re, length);
2177 skb = receive_new(sky2, re, length);
2179 sky2_rx_submit(sky2, re);
2184 /* Truncation of overlength packets
2185 causes PHY length to not match MAC length */
2186 ++sky2->net_stats.rx_length_errors;
2187 if (netif_msg_rx_err(sky2) && net_ratelimit())
2188 pr_info(PFX "%s: rx length error: status %#x length %d\n",
2189 dev->name, status, length);
2193 ++sky2->net_stats.rx_errors;
2194 if (status & GMR_FS_RX_FF_OV) {
2195 sky2->net_stats.rx_over_errors++;
2199 if (netif_msg_rx_err(sky2) && net_ratelimit())
2200 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
2201 dev->name, status, length);
2203 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
2204 sky2->net_stats.rx_length_errors++;
2205 if (status & GMR_FS_FRAGMENT)
2206 sky2->net_stats.rx_frame_errors++;
2207 if (status & GMR_FS_CRC_ERR)
2208 sky2->net_stats.rx_crc_errors++;
2213 /* Transmit complete */
2214 static inline void sky2_tx_done(struct net_device *dev, u16 last)
2216 struct sky2_port *sky2 = netdev_priv(dev);
2218 if (netif_running(dev)) {
2220 sky2_tx_complete(sky2, last);
2221 netif_tx_unlock(dev);
2225 /* Process status response ring */
2226 static int sky2_status_intr(struct sky2_hw *hw, int to_do)
2229 unsigned rx[2] = { 0, 0 };
2230 u16 hwidx = sky2_read16(hw, STAT_PUT_IDX);
2234 while (hw->st_idx != hwidx) {
2235 struct sky2_port *sky2;
2236 struct sky2_status_le *le = hw->st_le + hw->st_idx;
2237 unsigned port = le->css & CSS_LINK_BIT;
2238 struct net_device *dev;
2239 struct sk_buff *skb;
2243 hw->st_idx = RING_NEXT(hw->st_idx, STATUS_RING_SIZE);
2245 dev = hw->dev[port];
2246 sky2 = netdev_priv(dev);
2247 length = le16_to_cpu(le->length);
2248 status = le32_to_cpu(le->status);
2250 switch (le->opcode & ~HW_OWNER) {
2253 skb = sky2_receive(dev, length, status);
2254 if (unlikely(!skb)) {
2255 sky2->net_stats.rx_dropped++;
2259 /* This chip reports checksum status differently */
2260 if (hw->flags & SKY2_HW_NEW_LE) {
2261 if (sky2->rx_csum &&
2262 (le->css & (CSS_ISIPV4 | CSS_ISIPV6)) &&
2263 (le->css & CSS_TCPUDPCSOK))
2264 skb->ip_summed = CHECKSUM_UNNECESSARY;
2266 skb->ip_summed = CHECKSUM_NONE;
2269 skb->protocol = eth_type_trans(skb, dev);
2270 sky2->net_stats.rx_packets++;
2271 sky2->net_stats.rx_bytes += skb->len;
2272 dev->last_rx = jiffies;
2274 #ifdef SKY2_VLAN_TAG_USED
2275 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
2276 vlan_hwaccel_receive_skb(skb,
2278 be16_to_cpu(sky2->rx_tag));
2281 netif_receive_skb(skb);
2283 /* Stop after net poll weight */
2284 if (++work_done >= to_do)
2288 #ifdef SKY2_VLAN_TAG_USED
2290 sky2->rx_tag = length;
2294 sky2->rx_tag = length;
2301 /* If this happens then driver assuming wrong format */
2302 if (unlikely(hw->flags & SKY2_HW_NEW_LE)) {
2303 if (net_ratelimit())
2304 printk(KERN_NOTICE "%s: unexpected"
2305 " checksum status\n",
2310 /* Both checksum counters are programmed to start at
2311 * the same offset, so unless there is a problem they
2312 * should match. This failure is an early indication that
2313 * hardware receive checksumming won't work.
2315 if (likely(status >> 16 == (status & 0xffff))) {
2316 skb = sky2->rx_ring[sky2->rx_next].skb;
2317 skb->ip_summed = CHECKSUM_COMPLETE;
2318 skb->csum = status & 0xffff;
2320 printk(KERN_NOTICE PFX "%s: hardware receive "
2321 "checksum problem (status = %#x)\n",
2324 sky2_write32(sky2->hw,
2325 Q_ADDR(rxqaddr[port], Q_CSR),
2331 /* TX index reports status for both ports */
2332 BUILD_BUG_ON(TX_RING_SIZE > 0x1000);
2333 sky2_tx_done(hw->dev[0], status & 0xfff);
2335 sky2_tx_done(hw->dev[1],
2336 ((status >> 24) & 0xff)
2337 | (u16)(length & 0xf) << 8);
2341 if (net_ratelimit())
2342 printk(KERN_WARNING PFX
2343 "unknown status opcode 0x%x\n", le->opcode);
2347 /* Fully processed status ring so clear irq */
2348 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
2352 sky2_rx_update(netdev_priv(hw->dev[0]), Q_R1);
2355 sky2_rx_update(netdev_priv(hw->dev[1]), Q_R2);
2360 static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2362 struct net_device *dev = hw->dev[port];
2364 if (net_ratelimit())
2365 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
2368 if (status & Y2_IS_PAR_RD1) {
2369 if (net_ratelimit())
2370 printk(KERN_ERR PFX "%s: ram data read parity error\n",
2373 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2376 if (status & Y2_IS_PAR_WR1) {
2377 if (net_ratelimit())
2378 printk(KERN_ERR PFX "%s: ram data write parity error\n",
2381 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2384 if (status & Y2_IS_PAR_MAC1) {
2385 if (net_ratelimit())
2386 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
2387 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2390 if (status & Y2_IS_PAR_RX1) {
2391 if (net_ratelimit())
2392 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
2393 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2396 if (status & Y2_IS_TCP_TXA1) {
2397 if (net_ratelimit())
2398 printk(KERN_ERR PFX "%s: TCP segmentation error\n",
2400 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2404 static void sky2_hw_intr(struct sky2_hw *hw)
2406 u32 status = sky2_read32(hw, B0_HWE_ISRC);
2408 if (status & Y2_IS_TIST_OV)
2409 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2411 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
2414 pci_err = sky2_pci_read16(hw, PCI_STATUS);
2415 if (net_ratelimit())
2416 dev_err(&hw->pdev->dev, "PCI hardware error (0x%x)\n",
2419 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2420 sky2_pci_write16(hw, PCI_STATUS,
2421 pci_err | PCI_STATUS_ERROR_BITS);
2422 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2425 if (status & Y2_IS_PCI_EXP) {
2426 /* PCI-Express uncorrectable Error occurred */
2429 pex_err = sky2_pci_read32(hw, PEX_UNC_ERR_STAT);
2431 if (net_ratelimit())
2432 dev_err(&hw->pdev->dev, "PCI Express error (0x%x)\n",
2435 /* clear the interrupt */
2436 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2437 sky2_pci_write32(hw, PEX_UNC_ERR_STAT,
2439 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2441 if (pex_err & PEX_FATAL_ERRORS) {
2442 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2443 hwmsk &= ~Y2_IS_PCI_EXP;
2444 sky2_write32(hw, B0_HWE_IMSK, hwmsk);
2448 if (status & Y2_HWE_L1_MASK)
2449 sky2_hw_error(hw, 0, status);
2451 if (status & Y2_HWE_L1_MASK)
2452 sky2_hw_error(hw, 1, status);
2455 static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2457 struct net_device *dev = hw->dev[port];
2458 struct sky2_port *sky2 = netdev_priv(dev);
2459 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2461 if (netif_msg_intr(sky2))
2462 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
2465 if (status & GM_IS_RX_CO_OV)
2466 gma_read16(hw, port, GM_RX_IRQ_SRC);
2468 if (status & GM_IS_TX_CO_OV)
2469 gma_read16(hw, port, GM_TX_IRQ_SRC);
2471 if (status & GM_IS_RX_FF_OR) {
2472 ++sky2->net_stats.rx_fifo_errors;
2473 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2476 if (status & GM_IS_TX_FF_UR) {
2477 ++sky2->net_stats.tx_fifo_errors;
2478 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2482 /* This should never happen it is a bug. */
2483 static void sky2_le_error(struct sky2_hw *hw, unsigned port,
2484 u16 q, unsigned ring_size)
2486 struct net_device *dev = hw->dev[port];
2487 struct sky2_port *sky2 = netdev_priv(dev);
2489 const u64 *le = (q == Q_R1 || q == Q_R2)
2490 ? (u64 *) sky2->rx_le : (u64 *) sky2->tx_le;
2492 idx = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));
2493 printk(KERN_ERR PFX "%s: descriptor error q=%#x get=%u [%llx] put=%u\n",
2494 dev->name, (unsigned) q, idx, (unsigned long long) le[idx],
2495 (unsigned) sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX)));
2497 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_IRQ_CHK);
2500 static int sky2_rx_hung(struct net_device *dev)
2502 struct sky2_port *sky2 = netdev_priv(dev);
2503 struct sky2_hw *hw = sky2->hw;
2504 unsigned port = sky2->port;
2505 unsigned rxq = rxqaddr[port];
2506 u32 mac_rp = sky2_read32(hw, SK_REG(port, RX_GMF_RP));
2507 u8 mac_lev = sky2_read8(hw, SK_REG(port, RX_GMF_RLEV));
2508 u8 fifo_rp = sky2_read8(hw, Q_ADDR(rxq, Q_RP));
2509 u8 fifo_lev = sky2_read8(hw, Q_ADDR(rxq, Q_RL));
2511 /* If idle and MAC or PCI is stuck */
2512 if (sky2->check.last == dev->last_rx &&
2513 ((mac_rp == sky2->check.mac_rp &&
2514 mac_lev != 0 && mac_lev >= sky2->check.mac_lev) ||
2515 /* Check if the PCI RX hang */
2516 (fifo_rp == sky2->check.fifo_rp &&
2517 fifo_lev != 0 && fifo_lev >= sky2->check.fifo_lev))) {
2518 printk(KERN_DEBUG PFX "%s: hung mac %d:%d fifo %d (%d:%d)\n",
2519 dev->name, mac_lev, mac_rp, fifo_lev, fifo_rp,
2520 sky2_read8(hw, Q_ADDR(rxq, Q_WP)));
2523 sky2->check.last = dev->last_rx;
2524 sky2->check.mac_rp = mac_rp;
2525 sky2->check.mac_lev = mac_lev;
2526 sky2->check.fifo_rp = fifo_rp;
2527 sky2->check.fifo_lev = fifo_lev;
2532 static void sky2_watchdog(unsigned long arg)
2534 struct sky2_hw *hw = (struct sky2_hw *) arg;
2535 struct net_device *dev;
2537 /* Check for lost IRQ once a second */
2538 if (sky2_read32(hw, B0_ISRC)) {
2540 if (__netif_rx_schedule_prep(dev))
2541 __netif_rx_schedule(dev);
2545 for (i = 0; i < hw->ports; i++) {
2547 if (!netif_running(dev))
2551 /* For chips with Rx FIFO, check if stuck */
2552 if ((hw->flags & SKY2_HW_FIFO_HANG_CHECK) &&
2553 sky2_rx_hung(dev)) {
2554 pr_info(PFX "%s: receiver hang detected\n",
2556 schedule_work(&hw->restart_work);
2565 mod_timer(&hw->watchdog_timer, round_jiffies(jiffies + HZ));
2568 /* Hardware/software error handling */
2569 static void sky2_err_intr(struct sky2_hw *hw, u32 status)
2571 if (net_ratelimit())
2572 dev_warn(&hw->pdev->dev, "error interrupt status=%#x\n", status);
2574 if (status & Y2_IS_HW_ERR)
2577 if (status & Y2_IS_IRQ_MAC1)
2578 sky2_mac_intr(hw, 0);
2580 if (status & Y2_IS_IRQ_MAC2)
2581 sky2_mac_intr(hw, 1);
2583 if (status & Y2_IS_CHK_RX1)
2584 sky2_le_error(hw, 0, Q_R1, RX_LE_SIZE);
2586 if (status & Y2_IS_CHK_RX2)
2587 sky2_le_error(hw, 1, Q_R2, RX_LE_SIZE);
2589 if (status & Y2_IS_CHK_TXA1)
2590 sky2_le_error(hw, 0, Q_XA1, TX_RING_SIZE);
2592 if (status & Y2_IS_CHK_TXA2)
2593 sky2_le_error(hw, 1, Q_XA2, TX_RING_SIZE);
2596 static int sky2_poll(struct net_device *dev0, int *budget)
2598 struct sky2_hw *hw = ((struct sky2_port *) netdev_priv(dev0))->hw;
2600 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
2602 if (unlikely(status & Y2_IS_ERROR))
2603 sky2_err_intr(hw, status);
2605 if (status & Y2_IS_IRQ_PHY1)
2606 sky2_phy_intr(hw, 0);
2608 if (status & Y2_IS_IRQ_PHY2)
2609 sky2_phy_intr(hw, 1);
2611 work_done = sky2_status_intr(hw, min(dev0->quota, *budget));
2612 *budget -= work_done;
2613 dev0->quota -= work_done;
2616 if (hw->st_idx != sky2_read16(hw, STAT_PUT_IDX))
2619 /* Bug/Errata workaround?
2620 * Need to kick the TX irq moderation timer.
2622 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_START) {
2623 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
2624 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2626 netif_rx_complete(dev0);
2628 sky2_read32(hw, B0_Y2_SP_LISR);
2632 static irqreturn_t sky2_intr(int irq, void *dev_id)
2634 struct sky2_hw *hw = dev_id;
2635 struct net_device *dev0 = hw->dev[0];
2638 /* Reading this mask interrupts as side effect */
2639 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2640 if (status == 0 || status == ~0)
2643 prefetch(&hw->st_le[hw->st_idx]);
2644 if (likely(__netif_rx_schedule_prep(dev0)))
2645 __netif_rx_schedule(dev0);
2650 #ifdef CONFIG_NET_POLL_CONTROLLER
2651 static void sky2_netpoll(struct net_device *dev)
2653 struct sky2_port *sky2 = netdev_priv(dev);
2654 struct net_device *dev0 = sky2->hw->dev[0];
2656 if (netif_running(dev) && __netif_rx_schedule_prep(dev0))
2657 __netif_rx_schedule(dev0);
2661 /* Chip internal frequency for clock calculations */
2662 static u32 sky2_mhz(const struct sky2_hw *hw)
2664 switch (hw->chip_id) {
2665 case CHIP_ID_YUKON_EC:
2666 case CHIP_ID_YUKON_EC_U:
2667 case CHIP_ID_YUKON_EX:
2670 case CHIP_ID_YUKON_FE:
2673 case CHIP_ID_YUKON_FE_P:
2676 case CHIP_ID_YUKON_XL:
2684 static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
2686 return sky2_mhz(hw) * us;
2689 static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
2691 return clk / sky2_mhz(hw);
2695 static int __devinit sky2_init(struct sky2_hw *hw)
2699 /* Enable all clocks */
2700 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
2702 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2704 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
2705 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2707 switch(hw->chip_id) {
2708 case CHIP_ID_YUKON_XL:
2709 hw->flags = SKY2_HW_GIGABIT
2710 | SKY2_HW_NEWER_PHY;
2711 if (hw->chip_rev < 3)
2712 hw->flags |= SKY2_HW_FIFO_HANG_CHECK;
2716 case CHIP_ID_YUKON_EC_U:
2717 hw->flags = SKY2_HW_GIGABIT
2719 | SKY2_HW_ADV_POWER_CTL;
2722 case CHIP_ID_YUKON_EX:
2723 hw->flags = SKY2_HW_GIGABIT
2726 | SKY2_HW_ADV_POWER_CTL;
2728 /* New transmit checksum */
2729 if (hw->chip_rev != CHIP_REV_YU_EX_B0)
2730 hw->flags |= SKY2_HW_AUTO_TX_SUM;
2733 case CHIP_ID_YUKON_EC:
2734 /* This rev is really old, and requires untested workarounds */
2735 if (hw->chip_rev == CHIP_REV_YU_EC_A1) {
2736 dev_err(&hw->pdev->dev, "unsupported revision Yukon-EC rev A1\n");
2739 hw->flags = SKY2_HW_GIGABIT | SKY2_HW_FIFO_HANG_CHECK;
2742 case CHIP_ID_YUKON_FE:
2745 case CHIP_ID_YUKON_FE_P:
2746 hw->flags = SKY2_HW_NEWER_PHY
2748 | SKY2_HW_AUTO_TX_SUM
2749 | SKY2_HW_ADV_POWER_CTL;
2752 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
2757 hw->pmd_type = sky2_read8(hw, B2_PMD_TYP);
2758 if (hw->pmd_type == 'L' || hw->pmd_type == 'S' || hw->pmd_type == 'P')
2759 hw->flags |= SKY2_HW_FIBRE_PHY;
2763 t8 = sky2_read8(hw, B2_Y2_HW_RES);
2764 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
2765 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
2772 static void sky2_reset(struct sky2_hw *hw)
2778 if (hw->chip_id == CHIP_ID_YUKON_EX) {
2779 status = sky2_read16(hw, HCU_CCSR);
2780 status &= ~(HCU_CCSR_AHB_RST | HCU_CCSR_CPU_RST_MODE |
2781 HCU_CCSR_UC_STATE_MSK);
2782 sky2_write16(hw, HCU_CCSR, status);
2784 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
2785 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
2788 sky2_write8(hw, B0_CTST, CS_RST_SET);
2789 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2791 /* clear PCI errors, if any */
2792 status = sky2_pci_read16(hw, PCI_STATUS);
2794 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2795 sky2_pci_write16(hw, PCI_STATUS, status | PCI_STATUS_ERROR_BITS);
2798 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
2800 /* clear any PEX errors */
2801 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
2802 sky2_pci_write32(hw, PEX_UNC_ERR_STAT, 0xffffffffUL);
2807 for (i = 0; i < hw->ports; i++) {
2808 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2809 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
2811 if (hw->chip_id == CHIP_ID_YUKON_EX)
2812 sky2_write16(hw, SK_REG(i, GMAC_CTRL),
2813 GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON
2817 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2819 /* Clear I2C IRQ noise */
2820 sky2_write32(hw, B2_I2C_IRQ, 1);
2822 /* turn off hardware timer (unused) */
2823 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
2824 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
2826 sky2_write8(hw, B0_Y2LED, LED_STAT_ON);
2828 /* Turn off descriptor polling */
2829 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
2831 /* Turn off receive timestamp */
2832 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
2833 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2835 /* enable the Tx Arbiters */
2836 for (i = 0; i < hw->ports; i++)
2837 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
2839 /* Initialize ram interface */
2840 for (i = 0; i < hw->ports; i++) {
2841 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
2843 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
2844 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
2845 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
2846 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
2847 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
2848 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
2849 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
2850 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
2851 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
2852 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
2853 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
2854 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
2857 sky2_write32(hw, B0_HWE_IMSK, Y2_HWE_ALL_MASK);
2859 for (i = 0; i < hw->ports; i++)
2860 sky2_gmac_reset(hw, i);
2862 memset(hw->st_le, 0, STATUS_LE_BYTES);
2865 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
2866 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
2868 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
2869 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
2871 /* Set the list last index */
2872 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
2874 sky2_write16(hw, STAT_TX_IDX_TH, 10);
2875 sky2_write8(hw, STAT_FIFO_WM, 16);
2877 /* set Status-FIFO ISR watermark */
2878 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
2879 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
2881 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
2883 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
2884 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
2885 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
2887 /* enable status unit */
2888 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
2890 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2891 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2892 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
2895 static void sky2_restart(struct work_struct *work)
2897 struct sky2_hw *hw = container_of(work, struct sky2_hw, restart_work);
2898 struct net_device *dev;
2902 sky2_write32(hw, B0_IMSK, 0);
2903 sky2_read32(hw, B0_IMSK);
2905 netif_poll_disable(hw->dev[0]);
2907 for (i = 0; i < hw->ports; i++) {
2909 if (netif_running(dev))
2914 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
2915 netif_poll_enable(hw->dev[0]);
2917 for (i = 0; i < hw->ports; i++) {
2919 if (netif_running(dev)) {
2922 printk(KERN_INFO PFX "%s: could not restart %d\n",
2932 static inline u8 sky2_wol_supported(const struct sky2_hw *hw)
2934 return sky2_is_copper(hw) ? (WAKE_PHY | WAKE_MAGIC) : 0;
2937 static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2939 const struct sky2_port *sky2 = netdev_priv(dev);
2941 wol->supported = sky2_wol_supported(sky2->hw);
2942 wol->wolopts = sky2->wol;
2945 static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2947 struct sky2_port *sky2 = netdev_priv(dev);
2948 struct sky2_hw *hw = sky2->hw;
2950 if (wol->wolopts & ~sky2_wol_supported(sky2->hw))
2953 sky2->wol = wol->wolopts;
2955 if (hw->chip_id == CHIP_ID_YUKON_EC_U ||
2956 hw->chip_id == CHIP_ID_YUKON_EX ||
2957 hw->chip_id == CHIP_ID_YUKON_FE_P)
2958 sky2_write32(hw, B0_CTST, sky2->wol
2959 ? Y2_HW_WOL_ON : Y2_HW_WOL_OFF);
2961 if (!netif_running(dev))
2962 sky2_wol_init(sky2);
2966 static u32 sky2_supported_modes(const struct sky2_hw *hw)
2968 if (sky2_is_copper(hw)) {
2969 u32 modes = SUPPORTED_10baseT_Half
2970 | SUPPORTED_10baseT_Full
2971 | SUPPORTED_100baseT_Half
2972 | SUPPORTED_100baseT_Full
2973 | SUPPORTED_Autoneg | SUPPORTED_TP;
2975 if (hw->flags & SKY2_HW_GIGABIT)
2976 modes |= SUPPORTED_1000baseT_Half
2977 | SUPPORTED_1000baseT_Full;
2980 return SUPPORTED_1000baseT_Half
2981 | SUPPORTED_1000baseT_Full
2986 static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2988 struct sky2_port *sky2 = netdev_priv(dev);
2989 struct sky2_hw *hw = sky2->hw;
2991 ecmd->transceiver = XCVR_INTERNAL;
2992 ecmd->supported = sky2_supported_modes(hw);
2993 ecmd->phy_address = PHY_ADDR_MARV;
2994 if (sky2_is_copper(hw)) {
2995 ecmd->port = PORT_TP;
2996 ecmd->speed = sky2->speed;
2998 ecmd->speed = SPEED_1000;
2999 ecmd->port = PORT_FIBRE;
3002 ecmd->advertising = sky2->advertising;
3003 ecmd->autoneg = sky2->autoneg;
3004 ecmd->duplex = sky2->duplex;
3008 static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3010 struct sky2_port *sky2 = netdev_priv(dev);
3011 const struct sky2_hw *hw = sky2->hw;
3012 u32 supported = sky2_supported_modes(hw);
3014 if (ecmd->autoneg == AUTONEG_ENABLE) {
3015 ecmd->advertising = supported;
3021 switch (ecmd->speed) {
3023 if (ecmd->duplex == DUPLEX_FULL)
3024 setting = SUPPORTED_1000baseT_Full;
3025 else if (ecmd->duplex == DUPLEX_HALF)
3026 setting = SUPPORTED_1000baseT_Half;
3031 if (ecmd->duplex == DUPLEX_FULL)
3032 setting = SUPPORTED_100baseT_Full;
3033 else if (ecmd->duplex == DUPLEX_HALF)
3034 setting = SUPPORTED_100baseT_Half;
3040 if (ecmd->duplex == DUPLEX_FULL)
3041 setting = SUPPORTED_10baseT_Full;
3042 else if (ecmd->duplex == DUPLEX_HALF)
3043 setting = SUPPORTED_10baseT_Half;
3051 if ((setting & supported) == 0)
3054 sky2->speed = ecmd->speed;
3055 sky2->duplex = ecmd->duplex;
3058 sky2->autoneg = ecmd->autoneg;
3059 sky2->advertising = ecmd->advertising;
3061 if (netif_running(dev)) {
3062 sky2_phy_reinit(sky2);
3063 sky2_set_multicast(dev);
3069 static void sky2_get_drvinfo(struct net_device *dev,
3070 struct ethtool_drvinfo *info)
3072 struct sky2_port *sky2 = netdev_priv(dev);
3074 strcpy(info->driver, DRV_NAME);
3075 strcpy(info->version, DRV_VERSION);
3076 strcpy(info->fw_version, "N/A");
3077 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
3080 static const struct sky2_stat {
3081 char name[ETH_GSTRING_LEN];
3084 { "tx_bytes", GM_TXO_OK_HI },
3085 { "rx_bytes", GM_RXO_OK_HI },
3086 { "tx_broadcast", GM_TXF_BC_OK },
3087 { "rx_broadcast", GM_RXF_BC_OK },
3088 { "tx_multicast", GM_TXF_MC_OK },
3089 { "rx_multicast", GM_RXF_MC_OK },
3090 { "tx_unicast", GM_TXF_UC_OK },
3091 { "rx_unicast", GM_RXF_UC_OK },
3092 { "tx_mac_pause", GM_TXF_MPAUSE },
3093 { "rx_mac_pause", GM_RXF_MPAUSE },
3094 { "collisions", GM_TXF_COL },
3095 { "late_collision",GM_TXF_LAT_COL },
3096 { "aborted", GM_TXF_ABO_COL },
3097 { "single_collisions", GM_TXF_SNG_COL },
3098 { "multi_collisions", GM_TXF_MUL_COL },
3100 { "rx_short", GM_RXF_SHT },
3101 { "rx_runt", GM_RXE_FRAG },
3102 { "rx_64_byte_packets", GM_RXF_64B },
3103 { "rx_65_to_127_byte_packets", GM_RXF_127B },
3104 { "rx_128_to_255_byte_packets", GM_RXF_255B },
3105 { "rx_256_to_511_byte_packets", GM_RXF_511B },
3106 { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
3107 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
3108 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
3109 { "rx_too_long", GM_RXF_LNG_ERR },
3110 { "rx_fifo_overflow", GM_RXE_FIFO_OV },
3111 { "rx_jabber", GM_RXF_JAB_PKT },
3112 { "rx_fcs_error", GM_RXF_FCS_ERR },
3114 { "tx_64_byte_packets", GM_TXF_64B },
3115 { "tx_65_to_127_byte_packets", GM_TXF_127B },
3116 { "tx_128_to_255_byte_packets", GM_TXF_255B },
3117 { "tx_256_to_511_byte_packets", GM_TXF_511B },
3118 { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
3119 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
3120 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
3121 { "tx_fifo_underrun", GM_TXE_FIFO_UR },
3124 static u32 sky2_get_rx_csum(struct net_device *dev)
3126 struct sky2_port *sky2 = netdev_priv(dev);
3128 return sky2->rx_csum;
3131 static int sky2_set_rx_csum(struct net_device *dev, u32 data)
3133 struct sky2_port *sky2 = netdev_priv(dev);
3135 sky2->rx_csum = data;
3137 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
3138 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
3143 static u32 sky2_get_msglevel(struct net_device *netdev)
3145 struct sky2_port *sky2 = netdev_priv(netdev);
3146 return sky2->msg_enable;
3149 static int sky2_nway_reset(struct net_device *dev)
3151 struct sky2_port *sky2 = netdev_priv(dev);
3153 if (!netif_running(dev) || sky2->autoneg != AUTONEG_ENABLE)
3156 sky2_phy_reinit(sky2);
3157 sky2_set_multicast(dev);
3162 static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
3164 struct sky2_hw *hw = sky2->hw;
3165 unsigned port = sky2->port;
3168 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
3169 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
3170 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
3171 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
3173 for (i = 2; i < count; i++)
3174 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
3177 static void sky2_set_msglevel(struct net_device *netdev, u32 value)
3179 struct sky2_port *sky2 = netdev_priv(netdev);
3180 sky2->msg_enable = value;
3183 static int sky2_get_stats_count(struct net_device *dev)
3185 return ARRAY_SIZE(sky2_stats);
3188 static void sky2_get_ethtool_stats(struct net_device *dev,
3189 struct ethtool_stats *stats, u64 * data)
3191 struct sky2_port *sky2 = netdev_priv(dev);
3193 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
3196 static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
3200 switch (stringset) {
3202 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
3203 memcpy(data + i * ETH_GSTRING_LEN,
3204 sky2_stats[i].name, ETH_GSTRING_LEN);
3209 static struct net_device_stats *sky2_get_stats(struct net_device *dev)
3211 struct sky2_port *sky2 = netdev_priv(dev);
3212 return &sky2->net_stats;
3215 static int sky2_set_mac_address(struct net_device *dev, void *p)
3217 struct sky2_port *sky2 = netdev_priv(dev);
3218 struct sky2_hw *hw = sky2->hw;
3219 unsigned port = sky2->port;
3220 const struct sockaddr *addr = p;
3222 if (!is_valid_ether_addr(addr->sa_data))
3223 return -EADDRNOTAVAIL;
3225 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
3226 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
3227 dev->dev_addr, ETH_ALEN);
3228 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
3229 dev->dev_addr, ETH_ALEN);
3231 /* virtual address for data */
3232 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3234 /* physical address: used for pause frames */
3235 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
3240 static void inline sky2_add_filter(u8 filter[8], const u8 *addr)
3244 bit = ether_crc(ETH_ALEN, addr) & 63;
3245 filter[bit >> 3] |= 1 << (bit & 7);
3248 static void sky2_set_multicast(struct net_device *dev)
3250 struct sky2_port *sky2 = netdev_priv(dev);
3251 struct sky2_hw *hw = sky2->hw;
3252 unsigned port = sky2->port;
3253 struct dev_mc_list *list = dev->mc_list;
3257 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
3259 rx_pause = (sky2->flow_status == FC_RX || sky2->flow_status == FC_BOTH);
3260 memset(filter, 0, sizeof(filter));
3262 reg = gma_read16(hw, port, GM_RX_CTRL);
3263 reg |= GM_RXCR_UCF_ENA;
3265 if (dev->flags & IFF_PROMISC) /* promiscuous */
3266 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
3267 else if (dev->flags & IFF_ALLMULTI)
3268 memset(filter, 0xff, sizeof(filter));
3269 else if (dev->mc_count == 0 && !rx_pause)
3270 reg &= ~GM_RXCR_MCF_ENA;
3273 reg |= GM_RXCR_MCF_ENA;
3276 sky2_add_filter(filter, pause_mc_addr);
3278 for (i = 0; list && i < dev->mc_count; i++, list = list->next)
3279 sky2_add_filter(filter, list->dmi_addr);
3282 gma_write16(hw, port, GM_MC_ADDR_H1,
3283 (u16) filter[0] | ((u16) filter[1] << 8));
3284 gma_write16(hw, port, GM_MC_ADDR_H2,
3285 (u16) filter[2] | ((u16) filter[3] << 8));
3286 gma_write16(hw, port, GM_MC_ADDR_H3,
3287 (u16) filter[4] | ((u16) filter[5] << 8));
3288 gma_write16(hw, port, GM_MC_ADDR_H4,
3289 (u16) filter[6] | ((u16) filter[7] << 8));
3291 gma_write16(hw, port, GM_RX_CTRL, reg);
3294 /* Can have one global because blinking is controlled by
3295 * ethtool and that is always under RTNL mutex
3297 static void sky2_led(struct sky2_hw *hw, unsigned port, int on)
3301 switch (hw->chip_id) {
3302 case CHIP_ID_YUKON_XL:
3303 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3304 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3305 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3306 on ? (PHY_M_LEDC_LOS_CTRL(1) |
3307 PHY_M_LEDC_INIT_CTRL(7) |
3308 PHY_M_LEDC_STA1_CTRL(7) |
3309 PHY_M_LEDC_STA0_CTRL(7))
3312 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3316 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
3317 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
3318 on ? PHY_M_LED_ALL : 0);
3322 /* blink LED's for finding board */
3323 static int sky2_phys_id(struct net_device *dev, u32 data)
3325 struct sky2_port *sky2 = netdev_priv(dev);
3326 struct sky2_hw *hw = sky2->hw;
3327 unsigned port = sky2->port;
3328 u16 ledctrl, ledover = 0;
3333 if (!data || data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ))
3334 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT);
3338 /* save initial values */
3339 spin_lock_bh(&sky2->phy_lock);
3340 if (hw->chip_id == CHIP_ID_YUKON_XL) {
3341 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3342 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3343 ledctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
3344 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3346 ledctrl = gm_phy_read(hw, port, PHY_MARV_LED_CTRL);
3347 ledover = gm_phy_read(hw, port, PHY_MARV_LED_OVER);
3351 while (!interrupted && ms > 0) {
3352 sky2_led(hw, port, onoff);
3355 spin_unlock_bh(&sky2->phy_lock);
3356 interrupted = msleep_interruptible(250);
3357 spin_lock_bh(&sky2->phy_lock);
3362 /* resume regularly scheduled programming */
3363 if (hw->chip_id == CHIP_ID_YUKON_XL) {
3364 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3365 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3366 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ledctrl);
3367 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3369 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
3370 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
3372 spin_unlock_bh(&sky2->phy_lock);
3377 static void sky2_get_pauseparam(struct net_device *dev,
3378 struct ethtool_pauseparam *ecmd)
3380 struct sky2_port *sky2 = netdev_priv(dev);
3382 switch (sky2->flow_mode) {
3384 ecmd->tx_pause = ecmd->rx_pause = 0;
3387 ecmd->tx_pause = 1, ecmd->rx_pause = 0;
3390 ecmd->tx_pause = 0, ecmd->rx_pause = 1;
3393 ecmd->tx_pause = ecmd->rx_pause = 1;
3396 ecmd->autoneg = sky2->autoneg;
3399 static int sky2_set_pauseparam(struct net_device *dev,
3400 struct ethtool_pauseparam *ecmd)
3402 struct sky2_port *sky2 = netdev_priv(dev);
3404 sky2->autoneg = ecmd->autoneg;
3405 sky2->flow_mode = sky2_flow(ecmd->rx_pause, ecmd->tx_pause);
3407 if (netif_running(dev))
3408 sky2_phy_reinit(sky2);
3413 static int sky2_get_coalesce(struct net_device *dev,
3414 struct ethtool_coalesce *ecmd)
3416 struct sky2_port *sky2 = netdev_priv(dev);
3417 struct sky2_hw *hw = sky2->hw;
3419 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
3420 ecmd->tx_coalesce_usecs = 0;
3422 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
3423 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
3425 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
3427 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
3428 ecmd->rx_coalesce_usecs = 0;
3430 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
3431 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
3433 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
3435 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
3436 ecmd->rx_coalesce_usecs_irq = 0;
3438 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
3439 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
3442 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
3447 /* Note: this affect both ports */
3448 static int sky2_set_coalesce(struct net_device *dev,
3449 struct ethtool_coalesce *ecmd)
3451 struct sky2_port *sky2 = netdev_priv(dev);
3452 struct sky2_hw *hw = sky2->hw;
3453 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
3455 if (ecmd->tx_coalesce_usecs > tmax ||
3456 ecmd->rx_coalesce_usecs > tmax ||
3457 ecmd->rx_coalesce_usecs_irq > tmax)
3460 if (ecmd->tx_max_coalesced_frames >= TX_RING_SIZE-1)
3462 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
3464 if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING)
3467 if (ecmd->tx_coalesce_usecs == 0)
3468 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
3470 sky2_write32(hw, STAT_TX_TIMER_INI,
3471 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
3472 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3474 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
3476 if (ecmd->rx_coalesce_usecs == 0)
3477 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
3479 sky2_write32(hw, STAT_LEV_TIMER_INI,
3480 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
3481 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3483 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
3485 if (ecmd->rx_coalesce_usecs_irq == 0)
3486 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
3488 sky2_write32(hw, STAT_ISR_TIMER_INI,
3489 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
3490 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3492 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
3496 static void sky2_get_ringparam(struct net_device *dev,
3497 struct ethtool_ringparam *ering)
3499 struct sky2_port *sky2 = netdev_priv(dev);
3501 ering->rx_max_pending = RX_MAX_PENDING;
3502 ering->rx_mini_max_pending = 0;
3503 ering->rx_jumbo_max_pending = 0;
3504 ering->tx_max_pending = TX_RING_SIZE - 1;
3506 ering->rx_pending = sky2->rx_pending;
3507 ering->rx_mini_pending = 0;
3508 ering->rx_jumbo_pending = 0;
3509 ering->tx_pending = sky2->tx_pending;
3512 static int sky2_set_ringparam(struct net_device *dev,
3513 struct ethtool_ringparam *ering)
3515 struct sky2_port *sky2 = netdev_priv(dev);
3518 if (ering->rx_pending > RX_MAX_PENDING ||
3519 ering->rx_pending < 8 ||
3520 ering->tx_pending < MAX_SKB_TX_LE ||
3521 ering->tx_pending > TX_RING_SIZE - 1)
3524 if (netif_running(dev))
3527 sky2->rx_pending = ering->rx_pending;
3528 sky2->tx_pending = ering->tx_pending;
3530 if (netif_running(dev)) {
3535 sky2_set_multicast(dev);
3541 static int sky2_get_regs_len(struct net_device *dev)
3547 * Returns copy of control register region
3548 * Note: ethtool_get_regs always provides full size (16k) buffer
3550 static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
3553 const struct sky2_port *sky2 = netdev_priv(dev);
3554 const void __iomem *io = sky2->hw->regs;
3557 memset(p, 0, regs->len);
3559 memcpy_fromio(p, io, B3_RAM_ADDR);
3561 /* skip diagnostic ram region */
3562 memcpy_fromio(p + B3_RI_WTO_R1, io + B3_RI_WTO_R1, 0x2000 - B3_RI_WTO_R1);
3564 /* copy GMAC registers */
3565 memcpy_fromio(p + BASE_GMAC_1, io + BASE_GMAC_1, 0x1000);
3566 if (sky2->hw->ports > 1)
3567 memcpy_fromio(p + BASE_GMAC_2, io + BASE_GMAC_2, 0x1000);
3571 /* In order to do Jumbo packets on these chips, need to turn off the
3572 * transmit store/forward. Therefore checksum offload won't work.
3574 static int no_tx_offload(struct net_device *dev)
3576 const struct sky2_port *sky2 = netdev_priv(dev);
3577 const struct sky2_hw *hw = sky2->hw;
3579 return dev->mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_EC_U;
3582 static int sky2_set_tx_csum(struct net_device *dev, u32 data)
3584 if (data && no_tx_offload(dev))
3587 return ethtool_op_set_tx_csum(dev, data);
3591 static int sky2_set_tso(struct net_device *dev, u32 data)
3593 if (data && no_tx_offload(dev))
3596 return ethtool_op_set_tso(dev, data);
3599 static int sky2_get_eeprom_len(struct net_device *dev)
3601 struct sky2_port *sky2 = netdev_priv(dev);
3604 reg2 = sky2_pci_read32(sky2->hw, PCI_DEV_REG2);
3605 return 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
3608 static u32 sky2_vpd_read(struct sky2_hw *hw, int cap, u16 offset)
3610 sky2_pci_write16(hw, cap + PCI_VPD_ADDR, offset);
3612 while (!(sky2_pci_read16(hw, cap + PCI_VPD_ADDR) & PCI_VPD_ADDR_F))
3614 return sky2_pci_read32(hw, cap + PCI_VPD_DATA);
3617 static void sky2_vpd_write(struct sky2_hw *hw, int cap, u16 offset, u32 val)
3619 sky2_pci_write32(hw, cap + PCI_VPD_DATA, val);
3620 sky2_pci_write16(hw, cap + PCI_VPD_ADDR, offset | PCI_VPD_ADDR_F);
3623 } while (sky2_pci_read16(hw, cap + PCI_VPD_ADDR) & PCI_VPD_ADDR_F);
3626 static int sky2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
3629 struct sky2_port *sky2 = netdev_priv(dev);
3630 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
3631 int length = eeprom->len;
3632 u16 offset = eeprom->offset;
3637 eeprom->magic = SKY2_EEPROM_MAGIC;
3639 while (length > 0) {
3640 u32 val = sky2_vpd_read(sky2->hw, cap, offset);
3641 int n = min_t(int, length, sizeof(val));
3643 memcpy(data, &val, n);
3651 static int sky2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
3654 struct sky2_port *sky2 = netdev_priv(dev);
3655 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
3656 int length = eeprom->len;
3657 u16 offset = eeprom->offset;
3662 if (eeprom->magic != SKY2_EEPROM_MAGIC)
3665 while (length > 0) {
3667 int n = min_t(int, length, sizeof(val));
3669 if (n < sizeof(val))
3670 val = sky2_vpd_read(sky2->hw, cap, offset);
3671 memcpy(&val, data, n);
3673 sky2_vpd_write(sky2->hw, cap, offset, val);
3683 static const struct ethtool_ops sky2_ethtool_ops = {
3684 .get_settings = sky2_get_settings,
3685 .set_settings = sky2_set_settings,
3686 .get_drvinfo = sky2_get_drvinfo,
3687 .get_wol = sky2_get_wol,
3688 .set_wol = sky2_set_wol,
3689 .get_msglevel = sky2_get_msglevel,
3690 .set_msglevel = sky2_set_msglevel,
3691 .nway_reset = sky2_nway_reset,
3692 .get_regs_len = sky2_get_regs_len,
3693 .get_regs = sky2_get_regs,
3694 .get_link = ethtool_op_get_link,
3695 .get_eeprom_len = sky2_get_eeprom_len,
3696 .get_eeprom = sky2_get_eeprom,
3697 .set_eeprom = sky2_set_eeprom,
3698 .get_sg = ethtool_op_get_sg,
3699 .set_sg = ethtool_op_set_sg,
3700 .get_tx_csum = ethtool_op_get_tx_csum,
3701 .set_tx_csum = sky2_set_tx_csum,
3702 .get_tso = ethtool_op_get_tso,
3703 .set_tso = sky2_set_tso,
3704 .get_rx_csum = sky2_get_rx_csum,
3705 .set_rx_csum = sky2_set_rx_csum,
3706 .get_strings = sky2_get_strings,
3707 .get_coalesce = sky2_get_coalesce,
3708 .set_coalesce = sky2_set_coalesce,
3709 .get_ringparam = sky2_get_ringparam,
3710 .set_ringparam = sky2_set_ringparam,
3711 .get_pauseparam = sky2_get_pauseparam,
3712 .set_pauseparam = sky2_set_pauseparam,
3713 .phys_id = sky2_phys_id,
3714 .get_stats_count = sky2_get_stats_count,
3715 .get_ethtool_stats = sky2_get_ethtool_stats,
3718 #ifdef CONFIG_SKY2_DEBUG
3720 static struct dentry *sky2_debug;
3722 static int sky2_debug_show(struct seq_file *seq, void *v)
3724 struct net_device *dev = seq->private;
3725 const struct sky2_port *sky2 = netdev_priv(dev);
3726 const struct sky2_hw *hw = sky2->hw;
3727 unsigned port = sky2->port;
3731 if (!netif_running(dev))
3734 seq_printf(seq, "IRQ src=%x mask=%x control=%x\n",
3735 sky2_read32(hw, B0_ISRC),
3736 sky2_read32(hw, B0_IMSK),
3737 sky2_read32(hw, B0_Y2_SP_ICR));
3739 netif_poll_disable(hw->dev[0]);
3740 last = sky2_read16(hw, STAT_PUT_IDX);
3742 if (hw->st_idx == last)
3743 seq_puts(seq, "Status ring (empty)\n");
3745 seq_puts(seq, "Status ring\n");
3746 for (idx = hw->st_idx; idx != last && idx < STATUS_RING_SIZE;
3747 idx = RING_NEXT(idx, STATUS_RING_SIZE)) {
3748 const struct sky2_status_le *le = hw->st_le + idx;
3749 seq_printf(seq, "[%d] %#x %d %#x\n",
3750 idx, le->opcode, le->length, le->status);
3752 seq_puts(seq, "\n");
3755 seq_printf(seq, "Tx ring pending=%u...%u report=%d done=%d\n",
3756 sky2->tx_cons, sky2->tx_prod,
3757 sky2_read16(hw, port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
3758 sky2_read16(hw, Q_ADDR(txqaddr[port], Q_DONE)));
3760 /* Dump contents of tx ring */
3762 for (idx = sky2->tx_next; idx != sky2->tx_prod && idx < TX_RING_SIZE;
3763 idx = RING_NEXT(idx, TX_RING_SIZE)) {
3764 const struct sky2_tx_le *le = sky2->tx_le + idx;
3765 u32 a = le32_to_cpu(le->addr);
3768 seq_printf(seq, "%u:", idx);
3771 switch(le->opcode & ~HW_OWNER) {
3773 seq_printf(seq, " %#x:", a);
3776 seq_printf(seq, " mtu=%d", a);
3779 seq_printf(seq, " vlan=%d", be16_to_cpu(le->length));
3782 seq_printf(seq, " csum=%#x", a);
3785 seq_printf(seq, " tso=%#x(%d)", a, le16_to_cpu(le->length));
3788 seq_printf(seq, " %#x(%d)", a, le16_to_cpu(le->length));
3791 seq_printf(seq, " frag=%#x(%d)", a, le16_to_cpu(le->length));
3794 seq_printf(seq, " op=%#x,%#x(%d)", le->opcode,
3795 a, le16_to_cpu(le->length));
3798 if (le->ctrl & EOP) {
3799 seq_putc(seq, '\n');
3804 seq_printf(seq, "\nRx ring hw get=%d put=%d last=%d\n",
3805 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_GET_IDX)),
3806 last = sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_PUT_IDX)),
3807 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_LAST_IDX)));
3809 netif_poll_enable(hw->dev[0]);
3813 static int sky2_debug_open(struct inode *inode, struct file *file)
3815 return single_open(file, sky2_debug_show, inode->i_private);
3818 static const struct file_operations sky2_debug_fops = {
3819 .owner = THIS_MODULE,
3820 .open = sky2_debug_open,
3822 .llseek = seq_lseek,
3823 .release = single_release,
3827 * Use network device events to create/remove/rename
3828 * debugfs file entries
3830 static int sky2_device_event(struct notifier_block *unused,
3831 unsigned long event, void *ptr)
3833 struct net_device *dev = ptr;
3835 if (dev->open == sky2_up) {
3836 struct sky2_port *sky2 = netdev_priv(dev);
3839 case NETDEV_CHANGENAME:
3840 if (!netif_running(dev))
3844 case NETDEV_GOING_DOWN:
3845 if (sky2->debugfs) {
3846 printk(KERN_DEBUG PFX "%s: remove debugfs\n",
3848 debugfs_remove(sky2->debugfs);
3849 sky2->debugfs = NULL;
3852 if (event != NETDEV_CHANGENAME)
3854 /* fallthrough for changename */
3858 d = debugfs_create_file(dev->name, S_IRUGO,
3861 if (d == NULL || IS_ERR(d))
3862 printk(KERN_INFO PFX
3863 "%s: debugfs create failed\n",
3875 static struct notifier_block sky2_notifier = {
3876 .notifier_call = sky2_device_event,
3880 static __init void sky2_debug_init(void)
3884 ent = debugfs_create_dir("sky2", NULL);
3885 if (!ent || IS_ERR(ent))
3889 register_netdevice_notifier(&sky2_notifier);
3892 static __exit void sky2_debug_cleanup(void)
3895 unregister_netdevice_notifier(&sky2_notifier);
3896 debugfs_remove(sky2_debug);
3902 #define sky2_debug_init()
3903 #define sky2_debug_cleanup()
3907 /* Initialize network device */
3908 static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
3910 int highmem, int wol)
3912 struct sky2_port *sky2;
3913 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
3916 dev_err(&hw->pdev->dev, "etherdev alloc failed");
3920 SET_MODULE_OWNER(dev);
3921 SET_NETDEV_DEV(dev, &hw->pdev->dev);
3922 dev->irq = hw->pdev->irq;
3923 dev->open = sky2_up;
3924 dev->stop = sky2_down;
3925 dev->do_ioctl = sky2_ioctl;
3926 dev->hard_start_xmit = sky2_xmit_frame;
3927 dev->get_stats = sky2_get_stats;
3928 dev->set_multicast_list = sky2_set_multicast;
3929 dev->set_mac_address = sky2_set_mac_address;
3930 dev->change_mtu = sky2_change_mtu;
3931 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
3932 dev->tx_timeout = sky2_tx_timeout;
3933 dev->watchdog_timeo = TX_WATCHDOG;
3935 dev->poll = sky2_poll;
3936 dev->weight = NAPI_WEIGHT;
3937 #ifdef CONFIG_NET_POLL_CONTROLLER
3938 /* Network console (only works on port 0)
3939 * because netpoll makes assumptions about NAPI
3942 dev->poll_controller = sky2_netpoll;
3945 sky2 = netdev_priv(dev);
3948 sky2->msg_enable = netif_msg_init(debug, default_msg);
3950 /* Auto speed and flow control */
3951 sky2->autoneg = AUTONEG_ENABLE;
3952 sky2->flow_mode = FC_BOTH;
3956 sky2->advertising = sky2_supported_modes(hw);
3960 spin_lock_init(&sky2->phy_lock);
3961 sky2->tx_pending = TX_DEF_PENDING;
3962 sky2->rx_pending = RX_DEF_PENDING;
3964 hw->dev[port] = dev;
3968 dev->features |= NETIF_F_TSO | NETIF_F_IP_CSUM | NETIF_F_SG;
3970 dev->features |= NETIF_F_HIGHDMA;
3972 #ifdef SKY2_VLAN_TAG_USED
3973 /* The workaround for FE+ status conflicts with VLAN tag detection. */
3974 if (!(sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
3975 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0)) {
3976 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3977 dev->vlan_rx_register = sky2_vlan_rx_register;
3981 /* read the mac address */
3982 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
3983 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
3988 static void __devinit sky2_show_addr(struct net_device *dev)
3990 const struct sky2_port *sky2 = netdev_priv(dev);
3992 if (netif_msg_probe(sky2))
3993 printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
3995 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
3996 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
3999 /* Handle software interrupt used during MSI test */
4000 static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id)
4002 struct sky2_hw *hw = dev_id;
4003 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
4008 if (status & Y2_IS_IRQ_SW) {
4009 hw->flags |= SKY2_HW_USE_MSI;
4010 wake_up(&hw->msi_wait);
4011 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4013 sky2_write32(hw, B0_Y2_SP_ICR, 2);
4018 /* Test interrupt path by forcing a a software IRQ */
4019 static int __devinit sky2_test_msi(struct sky2_hw *hw)
4021 struct pci_dev *pdev = hw->pdev;
4024 init_waitqueue_head (&hw->msi_wait);
4026 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
4028 err = request_irq(pdev->irq, sky2_test_intr, 0, DRV_NAME, hw);
4030 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
4034 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
4035 sky2_read8(hw, B0_CTST);
4037 wait_event_timeout(hw->msi_wait, (hw->flags & SKY2_HW_USE_MSI), HZ/10);
4039 if (!(hw->flags & SKY2_HW_USE_MSI)) {
4040 /* MSI test failed, go back to INTx mode */
4041 dev_info(&pdev->dev, "No interrupt generated using MSI, "
4042 "switching to INTx mode.\n");
4045 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4048 sky2_write32(hw, B0_IMSK, 0);
4049 sky2_read32(hw, B0_IMSK);
4051 free_irq(pdev->irq, hw);
4056 static int __devinit pci_wake_enabled(struct pci_dev *dev)
4058 int pm = pci_find_capability(dev, PCI_CAP_ID_PM);
4063 if (pci_read_config_word(dev, pm + PCI_PM_CTRL, &value))
4065 return value & PCI_PM_CTRL_PME_ENABLE;
4068 static int __devinit sky2_probe(struct pci_dev *pdev,
4069 const struct pci_device_id *ent)
4071 struct net_device *dev;
4073 int err, using_dac = 0, wol_default;
4075 err = pci_enable_device(pdev);
4077 dev_err(&pdev->dev, "cannot enable PCI device\n");
4081 err = pci_request_regions(pdev, DRV_NAME);
4083 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
4084 goto err_out_disable;
4087 pci_set_master(pdev);
4089 if (sizeof(dma_addr_t) > sizeof(u32) &&
4090 !(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK))) {
4092 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
4094 dev_err(&pdev->dev, "unable to obtain 64 bit DMA "
4095 "for consistent allocations\n");
4096 goto err_out_free_regions;
4099 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
4101 dev_err(&pdev->dev, "no usable DMA configuration\n");
4102 goto err_out_free_regions;
4106 wol_default = pci_wake_enabled(pdev) ? WAKE_MAGIC : 0;
4109 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
4111 dev_err(&pdev->dev, "cannot allocate hardware struct\n");
4112 goto err_out_free_regions;
4117 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
4119 dev_err(&pdev->dev, "cannot map device registers\n");
4120 goto err_out_free_hw;
4124 /* The sk98lin vendor driver uses hardware byte swapping but
4125 * this driver uses software swapping.
4129 reg = sky2_pci_read32(hw, PCI_DEV_REG2);
4130 reg &= ~PCI_REV_DESC;
4131 sky2_pci_write32(hw, PCI_DEV_REG2, reg);
4135 /* ring for status responses */
4136 hw->st_le = pci_alloc_consistent(hw->pdev, STATUS_LE_BYTES,
4139 goto err_out_iounmap;
4141 err = sky2_init(hw);
4143 goto err_out_iounmap;
4145 dev_info(&pdev->dev, "v%s addr 0x%llx irq %d Yukon-%s (0x%x) rev %d\n",
4146 DRV_VERSION, (unsigned long long)pci_resource_start(pdev, 0),
4147 pdev->irq, yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
4148 hw->chip_id, hw->chip_rev);
4152 dev = sky2_init_netdev(hw, 0, using_dac, wol_default);
4155 goto err_out_free_pci;
4158 if (!disable_msi && pci_enable_msi(pdev) == 0) {
4159 err = sky2_test_msi(hw);
4160 if (err == -EOPNOTSUPP)
4161 pci_disable_msi(pdev);
4163 goto err_out_free_netdev;
4166 err = register_netdev(dev);
4168 dev_err(&pdev->dev, "cannot register net device\n");
4169 goto err_out_free_netdev;
4172 err = request_irq(pdev->irq, sky2_intr,
4173 (hw->flags & SKY2_HW_USE_MSI) ? 0 : IRQF_SHARED,
4176 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
4177 goto err_out_unregister;
4179 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
4181 sky2_show_addr(dev);
4183 if (hw->ports > 1) {
4184 struct net_device *dev1;
4186 dev1 = sky2_init_netdev(hw, 1, using_dac, wol_default);
4188 dev_warn(&pdev->dev, "allocation for second device failed\n");
4189 else if ((err = register_netdev(dev1))) {
4190 dev_warn(&pdev->dev,
4191 "register of second port failed (%d)\n", err);
4195 sky2_show_addr(dev1);
4198 setup_timer(&hw->watchdog_timer, sky2_watchdog, (unsigned long) hw);
4199 INIT_WORK(&hw->restart_work, sky2_restart);
4201 pci_set_drvdata(pdev, hw);
4206 if (hw->flags & SKY2_HW_USE_MSI)
4207 pci_disable_msi(pdev);
4208 unregister_netdev(dev);
4209 err_out_free_netdev:
4212 sky2_write8(hw, B0_CTST, CS_RST_SET);
4213 pci_free_consistent(hw->pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
4218 err_out_free_regions:
4219 pci_release_regions(pdev);
4221 pci_disable_device(pdev);
4223 pci_set_drvdata(pdev, NULL);
4227 static void __devexit sky2_remove(struct pci_dev *pdev)
4229 struct sky2_hw *hw = pci_get_drvdata(pdev);
4230 struct net_device *dev0, *dev1;
4235 del_timer_sync(&hw->watchdog_timer);
4237 flush_scheduled_work();
4239 sky2_write32(hw, B0_IMSK, 0);
4240 synchronize_irq(hw->pdev->irq);
4245 unregister_netdev(dev1);
4246 unregister_netdev(dev0);
4250 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
4251 sky2_write8(hw, B0_CTST, CS_RST_SET);
4252 sky2_read8(hw, B0_CTST);
4254 free_irq(pdev->irq, hw);
4255 if (hw->flags & SKY2_HW_USE_MSI)
4256 pci_disable_msi(pdev);
4257 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
4258 pci_release_regions(pdev);
4259 pci_disable_device(pdev);
4267 pci_set_drvdata(pdev, NULL);
4271 static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
4273 struct sky2_hw *hw = pci_get_drvdata(pdev);
4279 netif_poll_disable(hw->dev[0]);
4281 for (i = 0; i < hw->ports; i++) {
4282 struct net_device *dev = hw->dev[i];
4283 struct sky2_port *sky2 = netdev_priv(dev);
4285 if (netif_running(dev))
4289 sky2_wol_init(sky2);
4294 sky2_write32(hw, B0_IMSK, 0);
4297 pci_save_state(pdev);
4298 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
4299 pci_set_power_state(pdev, pci_choose_state(pdev, state));
4304 static int sky2_resume(struct pci_dev *pdev)
4306 struct sky2_hw *hw = pci_get_drvdata(pdev);
4312 err = pci_set_power_state(pdev, PCI_D0);
4316 err = pci_restore_state(pdev);
4320 pci_enable_wake(pdev, PCI_D0, 0);
4322 /* Re-enable all clocks */
4323 if (hw->chip_id == CHIP_ID_YUKON_EX ||
4324 hw->chip_id == CHIP_ID_YUKON_EC_U ||
4325 hw->chip_id == CHIP_ID_YUKON_FE_P)
4326 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
4330 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
4332 for (i = 0; i < hw->ports; i++) {
4333 struct net_device *dev = hw->dev[i];
4334 if (netif_running(dev)) {
4337 printk(KERN_ERR PFX "%s: could not up: %d\n",
4343 sky2_set_multicast(dev);
4347 netif_poll_enable(hw->dev[0]);
4351 dev_err(&pdev->dev, "resume failed (%d)\n", err);
4352 pci_disable_device(pdev);
4357 static void sky2_shutdown(struct pci_dev *pdev)
4359 struct sky2_hw *hw = pci_get_drvdata(pdev);
4365 netif_poll_disable(hw->dev[0]);
4367 for (i = 0; i < hw->ports; i++) {
4368 struct net_device *dev = hw->dev[i];
4369 struct sky2_port *sky2 = netdev_priv(dev);
4373 sky2_wol_init(sky2);
4380 pci_enable_wake(pdev, PCI_D3hot, wol);
4381 pci_enable_wake(pdev, PCI_D3cold, wol);
4383 pci_disable_device(pdev);
4384 pci_set_power_state(pdev, PCI_D3hot);
4388 static struct pci_driver sky2_driver = {
4390 .id_table = sky2_id_table,
4391 .probe = sky2_probe,
4392 .remove = __devexit_p(sky2_remove),
4394 .suspend = sky2_suspend,
4395 .resume = sky2_resume,
4397 .shutdown = sky2_shutdown,
4400 static int __init sky2_init_module(void)
4403 return pci_register_driver(&sky2_driver);
4406 static void __exit sky2_cleanup_module(void)
4408 pci_unregister_driver(&sky2_driver);
4409 sky2_debug_cleanup();
4412 module_init(sky2_init_module);
4413 module_exit(sky2_cleanup_module);
4415 MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
4416 MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
4417 MODULE_LICENSE("GPL");
4418 MODULE_VERSION(DRV_VERSION);