1 /***************************************************************************
3 * Copyright (C) 2007,2008 SMSC
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 ***************************************************************************
22 #include <linux/kernel.h>
23 #include <linux/netdevice.h>
24 #include <linux/phy.h>
25 #include <linux/pci.h>
26 #include <linux/if_vlan.h>
27 #include <linux/dma-mapping.h>
28 #include <linux/crc32.h>
29 #include <asm/unaligned.h>
32 #define DRV_NAME "smsc9420"
33 #define PFX DRV_NAME ": "
34 #define DRV_MDIONAME "smsc9420-mdio"
35 #define DRV_DESCRIPTION "SMSC LAN9420 driver"
36 #define DRV_VERSION "1.01"
38 MODULE_LICENSE("GPL");
39 MODULE_VERSION(DRV_VERSION);
41 struct smsc9420_dma_desc {
48 struct smsc9420_ring_info {
53 struct smsc9420_pdata {
54 void __iomem *base_addr;
56 struct net_device *dev;
58 struct smsc9420_dma_desc *rx_ring;
59 struct smsc9420_dma_desc *tx_ring;
60 struct smsc9420_ring_info *tx_buffers;
61 struct smsc9420_ring_info *rx_buffers;
62 dma_addr_t rx_dma_addr;
63 dma_addr_t tx_dma_addr;
64 int tx_ring_head, tx_ring_tail;
65 int rx_ring_head, rx_ring_tail;
70 struct napi_struct napi;
72 bool software_irq_signal;
76 struct phy_device *phy_dev;
77 struct mii_bus *mii_bus;
78 int phy_irq[PHY_MAX_ADDR];
83 static const struct pci_device_id smsc9420_id_table[] = {
84 { PCI_VENDOR_ID_9420, PCI_DEVICE_ID_9420, PCI_ANY_ID, PCI_ANY_ID, },
88 MODULE_DEVICE_TABLE(pci, smsc9420_id_table);
90 #define SMSC_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK)
92 static uint smsc_debug;
93 static uint debug = -1;
94 module_param(debug, uint, 0);
95 MODULE_PARM_DESC(debug, "debug level");
97 #define smsc_dbg(TYPE, f, a...) \
98 do { if ((pd)->msg_enable & NETIF_MSG_##TYPE) \
99 printk(KERN_DEBUG PFX f "\n", ## a); \
102 #define smsc_info(TYPE, f, a...) \
103 do { if ((pd)->msg_enable & NETIF_MSG_##TYPE) \
104 printk(KERN_INFO PFX f "\n", ## a); \
107 #define smsc_warn(TYPE, f, a...) \
108 do { if ((pd)->msg_enable & NETIF_MSG_##TYPE) \
109 printk(KERN_WARNING PFX f "\n", ## a); \
112 static inline u32 smsc9420_reg_read(struct smsc9420_pdata *pd, u32 offset)
114 return ioread32(pd->base_addr + offset);
118 smsc9420_reg_write(struct smsc9420_pdata *pd, u32 offset, u32 value)
120 iowrite32(value, pd->base_addr + offset);
123 static inline void smsc9420_pci_flush_write(struct smsc9420_pdata *pd)
125 /* to ensure PCI write completion, we must perform a PCI read */
126 smsc9420_reg_read(pd, ID_REV);
129 static int smsc9420_mii_read(struct mii_bus *bus, int phyaddr, int regidx)
131 struct smsc9420_pdata *pd = (struct smsc9420_pdata *)bus->priv;
136 spin_lock_irqsave(&pd->phy_lock, flags);
138 /* confirm MII not busy */
139 if ((smsc9420_reg_read(pd, MII_ACCESS) & MII_ACCESS_MII_BUSY_)) {
140 smsc_warn(DRV, "MII is busy???");
144 /* set the address, index & direction (read from PHY) */
145 addr = ((phyaddr & 0x1F) << 11) | ((regidx & 0x1F) << 6) |
146 MII_ACCESS_MII_READ_;
147 smsc9420_reg_write(pd, MII_ACCESS, addr);
149 /* wait for read to complete with 50us timeout */
150 for (i = 0; i < 5; i++) {
151 if (!(smsc9420_reg_read(pd, MII_ACCESS) &
152 MII_ACCESS_MII_BUSY_)) {
153 reg = (u16)smsc9420_reg_read(pd, MII_DATA);
159 smsc_warn(DRV, "MII busy timeout!");
162 spin_unlock_irqrestore(&pd->phy_lock, flags);
166 static int smsc9420_mii_write(struct mii_bus *bus, int phyaddr, int regidx,
169 struct smsc9420_pdata *pd = (struct smsc9420_pdata *)bus->priv;
174 spin_lock_irqsave(&pd->phy_lock, flags);
176 /* confirm MII not busy */
177 if ((smsc9420_reg_read(pd, MII_ACCESS) & MII_ACCESS_MII_BUSY_)) {
178 smsc_warn(DRV, "MII is busy???");
182 /* put the data to write in the MAC */
183 smsc9420_reg_write(pd, MII_DATA, (u32)val);
185 /* set the address, index & direction (write to PHY) */
186 addr = ((phyaddr & 0x1F) << 11) | ((regidx & 0x1F) << 6) |
187 MII_ACCESS_MII_WRITE_;
188 smsc9420_reg_write(pd, MII_ACCESS, addr);
190 /* wait for write to complete with 50us timeout */
191 for (i = 0; i < 5; i++) {
192 if (!(smsc9420_reg_read(pd, MII_ACCESS) &
193 MII_ACCESS_MII_BUSY_)) {
200 smsc_warn(DRV, "MII busy timeout!");
203 spin_unlock_irqrestore(&pd->phy_lock, flags);
207 /* Returns hash bit number for given MAC address
209 * 01 00 5E 00 00 01 -> returns bit number 31 */
210 static u32 smsc9420_hash(u8 addr[ETH_ALEN])
212 return (ether_crc(ETH_ALEN, addr) >> 26) & 0x3f;
215 static int smsc9420_eeprom_reload(struct smsc9420_pdata *pd)
217 int timeout = 100000;
221 if (smsc9420_reg_read(pd, E2P_CMD) & E2P_CMD_EPC_BUSY_) {
222 smsc_dbg(DRV, "smsc9420_eeprom_reload: Eeprom busy");
226 smsc9420_reg_write(pd, E2P_CMD,
227 (E2P_CMD_EPC_BUSY_ | E2P_CMD_EPC_CMD_RELOAD_));
231 if (!(smsc9420_reg_read(pd, E2P_CMD) & E2P_CMD_EPC_BUSY_))
235 smsc_warn(DRV, "smsc9420_eeprom_reload: Eeprom timed out");
239 /* Standard ioctls for mii-tool */
240 static int smsc9420_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
242 struct smsc9420_pdata *pd = netdev_priv(dev);
244 if (!netif_running(dev) || !pd->phy_dev)
247 return phy_mii_ioctl(pd->phy_dev, if_mii(ifr), cmd);
250 static int smsc9420_ethtool_get_settings(struct net_device *dev,
251 struct ethtool_cmd *cmd)
253 struct smsc9420_pdata *pd = netdev_priv(dev);
257 return phy_ethtool_gset(pd->phy_dev, cmd);
260 static int smsc9420_ethtool_set_settings(struct net_device *dev,
261 struct ethtool_cmd *cmd)
263 struct smsc9420_pdata *pd = netdev_priv(dev);
265 return phy_ethtool_sset(pd->phy_dev, cmd);
268 static void smsc9420_ethtool_get_drvinfo(struct net_device *netdev,
269 struct ethtool_drvinfo *drvinfo)
271 struct smsc9420_pdata *pd = netdev_priv(netdev);
273 strcpy(drvinfo->driver, DRV_NAME);
274 strcpy(drvinfo->bus_info, pci_name(pd->pdev));
275 strcpy(drvinfo->version, DRV_VERSION);
278 static u32 smsc9420_ethtool_get_msglevel(struct net_device *netdev)
280 struct smsc9420_pdata *pd = netdev_priv(netdev);
281 return pd->msg_enable;
284 static void smsc9420_ethtool_set_msglevel(struct net_device *netdev, u32 data)
286 struct smsc9420_pdata *pd = netdev_priv(netdev);
287 pd->msg_enable = data;
290 static int smsc9420_ethtool_nway_reset(struct net_device *netdev)
292 struct smsc9420_pdata *pd = netdev_priv(netdev);
293 return phy_start_aneg(pd->phy_dev);
296 static void smsc9420_eeprom_enable_access(struct smsc9420_pdata *pd)
298 unsigned int temp = smsc9420_reg_read(pd, GPIO_CFG);
299 temp &= ~GPIO_CFG_EEPR_EN_;
300 smsc9420_reg_write(pd, GPIO_CFG, temp);
304 static int smsc9420_eeprom_send_cmd(struct smsc9420_pdata *pd, u32 op)
309 smsc_dbg(HW, "op 0x%08x", op);
310 if (smsc9420_reg_read(pd, E2P_CMD) & E2P_CMD_EPC_BUSY_) {
311 smsc_warn(HW, "Busy at start");
315 e2cmd = op | E2P_CMD_EPC_BUSY_;
316 smsc9420_reg_write(pd, E2P_CMD, e2cmd);
320 e2cmd = smsc9420_reg_read(pd, E2P_CMD);
321 } while ((e2cmd & E2P_CMD_EPC_BUSY_) && (timeout--));
324 smsc_info(HW, "TIMED OUT");
328 if (e2cmd & E2P_CMD_EPC_TIMEOUT_) {
329 smsc_info(HW, "Error occured during eeprom operation");
336 static int smsc9420_eeprom_read_location(struct smsc9420_pdata *pd,
337 u8 address, u8 *data)
339 u32 op = E2P_CMD_EPC_CMD_READ_ | address;
342 smsc_dbg(HW, "address 0x%x", address);
343 ret = smsc9420_eeprom_send_cmd(pd, op);
346 data[address] = smsc9420_reg_read(pd, E2P_DATA);
351 static int smsc9420_eeprom_write_location(struct smsc9420_pdata *pd,
354 u32 op = E2P_CMD_EPC_CMD_ERASE_ | address;
357 smsc_dbg(HW, "address 0x%x, data 0x%x", address, data);
358 ret = smsc9420_eeprom_send_cmd(pd, op);
361 op = E2P_CMD_EPC_CMD_WRITE_ | address;
362 smsc9420_reg_write(pd, E2P_DATA, (u32)data);
363 ret = smsc9420_eeprom_send_cmd(pd, op);
369 static int smsc9420_ethtool_get_eeprom_len(struct net_device *dev)
371 return SMSC9420_EEPROM_SIZE;
374 static int smsc9420_ethtool_get_eeprom(struct net_device *dev,
375 struct ethtool_eeprom *eeprom, u8 *data)
377 struct smsc9420_pdata *pd = netdev_priv(dev);
378 u8 eeprom_data[SMSC9420_EEPROM_SIZE];
381 smsc9420_eeprom_enable_access(pd);
383 len = min(eeprom->len, SMSC9420_EEPROM_SIZE);
384 for (i = 0; i < len; i++) {
385 int ret = smsc9420_eeprom_read_location(pd, i, eeprom_data);
392 memcpy(data, &eeprom_data[eeprom->offset], len);
397 static int smsc9420_ethtool_set_eeprom(struct net_device *dev,
398 struct ethtool_eeprom *eeprom, u8 *data)
400 struct smsc9420_pdata *pd = netdev_priv(dev);
403 smsc9420_eeprom_enable_access(pd);
404 smsc9420_eeprom_send_cmd(pd, E2P_CMD_EPC_CMD_EWEN_);
405 ret = smsc9420_eeprom_write_location(pd, eeprom->offset, *data);
406 smsc9420_eeprom_send_cmd(pd, E2P_CMD_EPC_CMD_EWDS_);
408 /* Single byte write, according to man page */
414 static const struct ethtool_ops smsc9420_ethtool_ops = {
415 .get_settings = smsc9420_ethtool_get_settings,
416 .set_settings = smsc9420_ethtool_set_settings,
417 .get_drvinfo = smsc9420_ethtool_get_drvinfo,
418 .get_msglevel = smsc9420_ethtool_get_msglevel,
419 .set_msglevel = smsc9420_ethtool_set_msglevel,
420 .nway_reset = smsc9420_ethtool_nway_reset,
421 .get_link = ethtool_op_get_link,
422 .get_eeprom_len = smsc9420_ethtool_get_eeprom_len,
423 .get_eeprom = smsc9420_ethtool_get_eeprom,
424 .set_eeprom = smsc9420_ethtool_set_eeprom,
427 /* Sets the device MAC address to dev_addr */
428 static void smsc9420_set_mac_address(struct net_device *dev)
430 struct smsc9420_pdata *pd = netdev_priv(dev);
431 u8 *dev_addr = dev->dev_addr;
432 u32 mac_high16 = (dev_addr[5] << 8) | dev_addr[4];
433 u32 mac_low32 = (dev_addr[3] << 24) | (dev_addr[2] << 16) |
434 (dev_addr[1] << 8) | dev_addr[0];
436 smsc9420_reg_write(pd, ADDRH, mac_high16);
437 smsc9420_reg_write(pd, ADDRL, mac_low32);
440 static void smsc9420_check_mac_address(struct net_device *dev)
442 struct smsc9420_pdata *pd = netdev_priv(dev);
444 /* Check if mac address has been specified when bringing interface up */
445 if (is_valid_ether_addr(dev->dev_addr)) {
446 smsc9420_set_mac_address(dev);
447 smsc_dbg(PROBE, "MAC Address is specified by configuration");
449 /* Try reading mac address from device. if EEPROM is present
450 * it will already have been set */
451 u32 mac_high16 = smsc9420_reg_read(pd, ADDRH);
452 u32 mac_low32 = smsc9420_reg_read(pd, ADDRL);
453 dev->dev_addr[0] = (u8)(mac_low32);
454 dev->dev_addr[1] = (u8)(mac_low32 >> 8);
455 dev->dev_addr[2] = (u8)(mac_low32 >> 16);
456 dev->dev_addr[3] = (u8)(mac_low32 >> 24);
457 dev->dev_addr[4] = (u8)(mac_high16);
458 dev->dev_addr[5] = (u8)(mac_high16 >> 8);
460 if (is_valid_ether_addr(dev->dev_addr)) {
461 /* eeprom values are valid so use them */
462 smsc_dbg(PROBE, "Mac Address is read from EEPROM");
464 /* eeprom values are invalid, generate random MAC */
465 random_ether_addr(dev->dev_addr);
466 smsc9420_set_mac_address(dev);
468 "MAC Address is set to random_ether_addr");
473 static void smsc9420_stop_tx(struct smsc9420_pdata *pd)
475 u32 dmac_control, mac_cr, dma_intr_ena;
478 /* disable TX DMAC */
479 dmac_control = smsc9420_reg_read(pd, DMAC_CONTROL);
480 dmac_control &= (~DMAC_CONTROL_ST_);
481 smsc9420_reg_write(pd, DMAC_CONTROL, dmac_control);
483 /* Wait max 10ms for transmit process to stop */
485 if (smsc9420_reg_read(pd, DMAC_STATUS) & DMAC_STS_TS_)
491 smsc_warn(IFDOWN, "TX DMAC failed to stop");
493 /* ACK Tx DMAC stop bit */
494 smsc9420_reg_write(pd, DMAC_STATUS, DMAC_STS_TXPS_);
496 /* mask TX DMAC interrupts */
497 dma_intr_ena = smsc9420_reg_read(pd, DMAC_INTR_ENA);
498 dma_intr_ena &= ~(DMAC_INTR_ENA_TX_);
499 smsc9420_reg_write(pd, DMAC_INTR_ENA, dma_intr_ena);
500 smsc9420_pci_flush_write(pd);
503 mac_cr = smsc9420_reg_read(pd, MAC_CR) & (~MAC_CR_TXEN_);
504 smsc9420_reg_write(pd, MAC_CR, mac_cr);
505 smsc9420_pci_flush_write(pd);
508 static void smsc9420_free_tx_ring(struct smsc9420_pdata *pd)
512 BUG_ON(!pd->tx_ring);
517 for (i = 0; i < TX_RING_SIZE; i++) {
518 struct sk_buff *skb = pd->tx_buffers[i].skb;
521 BUG_ON(!pd->tx_buffers[i].mapping);
522 pci_unmap_single(pd->pdev, pd->tx_buffers[i].mapping,
523 skb->len, PCI_DMA_TODEVICE);
524 dev_kfree_skb_any(skb);
527 pd->tx_ring[i].status = 0;
528 pd->tx_ring[i].length = 0;
529 pd->tx_ring[i].buffer1 = 0;
530 pd->tx_ring[i].buffer2 = 0;
534 kfree(pd->tx_buffers);
535 pd->tx_buffers = NULL;
537 pd->tx_ring_head = 0;
538 pd->tx_ring_tail = 0;
541 static void smsc9420_free_rx_ring(struct smsc9420_pdata *pd)
545 BUG_ON(!pd->rx_ring);
550 for (i = 0; i < RX_RING_SIZE; i++) {
551 if (pd->rx_buffers[i].skb)
552 dev_kfree_skb_any(pd->rx_buffers[i].skb);
554 if (pd->rx_buffers[i].mapping)
555 pci_unmap_single(pd->pdev, pd->rx_buffers[i].mapping,
556 PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
558 pd->rx_ring[i].status = 0;
559 pd->rx_ring[i].length = 0;
560 pd->rx_ring[i].buffer1 = 0;
561 pd->rx_ring[i].buffer2 = 0;
565 kfree(pd->rx_buffers);
566 pd->rx_buffers = NULL;
568 pd->rx_ring_head = 0;
569 pd->rx_ring_tail = 0;
572 static void smsc9420_stop_rx(struct smsc9420_pdata *pd)
575 u32 mac_cr, dmac_control, dma_intr_ena;
577 /* mask RX DMAC interrupts */
578 dma_intr_ena = smsc9420_reg_read(pd, DMAC_INTR_ENA);
579 dma_intr_ena &= (~DMAC_INTR_ENA_RX_);
580 smsc9420_reg_write(pd, DMAC_INTR_ENA, dma_intr_ena);
581 smsc9420_pci_flush_write(pd);
583 /* stop RX MAC prior to stoping DMA */
584 mac_cr = smsc9420_reg_read(pd, MAC_CR) & (~MAC_CR_RXEN_);
585 smsc9420_reg_write(pd, MAC_CR, mac_cr);
586 smsc9420_pci_flush_write(pd);
589 dmac_control = smsc9420_reg_read(pd, DMAC_CONTROL);
590 dmac_control &= (~DMAC_CONTROL_SR_);
591 smsc9420_reg_write(pd, DMAC_CONTROL, dmac_control);
592 smsc9420_pci_flush_write(pd);
594 /* wait up to 10ms for receive to stop */
596 if (smsc9420_reg_read(pd, DMAC_STATUS) & DMAC_STS_RS_)
602 smsc_warn(IFDOWN, "RX DMAC did not stop! timeout.");
604 /* ACK the Rx DMAC stop bit */
605 smsc9420_reg_write(pd, DMAC_STATUS, DMAC_STS_RXPS_);
608 static irqreturn_t smsc9420_isr(int irq, void *dev_id)
610 struct smsc9420_pdata *pd = dev_id;
611 u32 int_cfg, int_sts, int_ctl;
612 irqreturn_t ret = IRQ_NONE;
616 BUG_ON(!pd->base_addr);
618 int_cfg = smsc9420_reg_read(pd, INT_CFG);
620 /* check if it's our interrupt */
621 if ((int_cfg & (INT_CFG_IRQ_EN_ | INT_CFG_IRQ_INT_)) !=
622 (INT_CFG_IRQ_EN_ | INT_CFG_IRQ_INT_))
625 int_sts = smsc9420_reg_read(pd, INT_STAT);
627 if (likely(INT_STAT_DMAC_INT_ & int_sts)) {
628 u32 status = smsc9420_reg_read(pd, DMAC_STATUS);
629 u32 ints_to_clear = 0;
631 if (status & DMAC_STS_TX_) {
632 ints_to_clear |= (DMAC_STS_TX_ | DMAC_STS_NIS_);
633 netif_wake_queue(pd->dev);
636 if (status & DMAC_STS_RX_) {
637 /* mask RX DMAC interrupts */
638 u32 dma_intr_ena = smsc9420_reg_read(pd, DMAC_INTR_ENA);
639 dma_intr_ena &= (~DMAC_INTR_ENA_RX_);
640 smsc9420_reg_write(pd, DMAC_INTR_ENA, dma_intr_ena);
641 smsc9420_pci_flush_write(pd);
643 ints_to_clear |= (DMAC_STS_RX_ | DMAC_STS_NIS_);
644 netif_rx_schedule(pd->dev, &pd->napi);
648 smsc9420_reg_write(pd, DMAC_STATUS, ints_to_clear);
653 if (unlikely(INT_STAT_SW_INT_ & int_sts)) {
654 /* mask software interrupt */
655 spin_lock_irqsave(&pd->int_lock, flags);
656 int_ctl = smsc9420_reg_read(pd, INT_CTL);
657 int_ctl &= (~INT_CTL_SW_INT_EN_);
658 smsc9420_reg_write(pd, INT_CTL, int_ctl);
659 spin_unlock_irqrestore(&pd->int_lock, flags);
661 smsc9420_reg_write(pd, INT_STAT, INT_STAT_SW_INT_);
662 pd->software_irq_signal = true;
668 /* to ensure PCI write completion, we must perform a PCI read */
669 smsc9420_pci_flush_write(pd);
674 #ifdef CONFIG_NET_POLL_CONTROLLER
675 static void smsc9420_poll_controller(struct net_device *dev)
677 disable_irq(dev->irq);
678 smsc9420_isr(0, dev);
679 enable_irq(dev->irq);
681 #endif /* CONFIG_NET_POLL_CONTROLLER */
683 static void smsc9420_dmac_soft_reset(struct smsc9420_pdata *pd)
685 smsc9420_reg_write(pd, BUS_MODE, BUS_MODE_SWR_);
686 smsc9420_reg_read(pd, BUS_MODE);
688 if (smsc9420_reg_read(pd, BUS_MODE) & BUS_MODE_SWR_)
689 smsc_warn(DRV, "Software reset not cleared");
692 static int smsc9420_stop(struct net_device *dev)
694 struct smsc9420_pdata *pd = netdev_priv(dev);
699 BUG_ON(!pd->phy_dev);
701 /* disable master interrupt */
702 spin_lock_irqsave(&pd->int_lock, flags);
703 int_cfg = smsc9420_reg_read(pd, INT_CFG) & (~INT_CFG_IRQ_EN_);
704 smsc9420_reg_write(pd, INT_CFG, int_cfg);
705 spin_unlock_irqrestore(&pd->int_lock, flags);
707 netif_tx_disable(dev);
708 napi_disable(&pd->napi);
710 smsc9420_stop_tx(pd);
711 smsc9420_free_tx_ring(pd);
713 smsc9420_stop_rx(pd);
714 smsc9420_free_rx_ring(pd);
716 free_irq(dev->irq, pd);
718 smsc9420_dmac_soft_reset(pd);
720 phy_stop(pd->phy_dev);
722 phy_disconnect(pd->phy_dev);
724 mdiobus_unregister(pd->mii_bus);
725 mdiobus_free(pd->mii_bus);
730 static void smsc9420_rx_count_stats(struct net_device *dev, u32 desc_status)
732 if (unlikely(desc_status & RDES0_ERROR_SUMMARY_)) {
733 dev->stats.rx_errors++;
734 if (desc_status & RDES0_DESCRIPTOR_ERROR_)
735 dev->stats.rx_over_errors++;
736 else if (desc_status & (RDES0_FRAME_TOO_LONG_ |
737 RDES0_RUNT_FRAME_ | RDES0_COLLISION_SEEN_))
738 dev->stats.rx_frame_errors++;
739 else if (desc_status & RDES0_CRC_ERROR_)
740 dev->stats.rx_crc_errors++;
743 if (unlikely(desc_status & RDES0_LENGTH_ERROR_))
744 dev->stats.rx_length_errors++;
746 if (unlikely(!((desc_status & RDES0_LAST_DESCRIPTOR_) &&
747 (desc_status & RDES0_FIRST_DESCRIPTOR_))))
748 dev->stats.rx_length_errors++;
750 if (desc_status & RDES0_MULTICAST_FRAME_)
751 dev->stats.multicast++;
754 static void smsc9420_rx_handoff(struct smsc9420_pdata *pd, const int index,
757 struct net_device *dev = pd->dev;
759 u16 packet_length = (status & RDES0_FRAME_LENGTH_MASK_)
760 >> RDES0_FRAME_LENGTH_SHFT_;
762 /* remove crc from packet lendth */
768 dev->stats.rx_packets++;
769 dev->stats.rx_bytes += packet_length;
771 pci_unmap_single(pd->pdev, pd->rx_buffers[index].mapping,
772 PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
773 pd->rx_buffers[index].mapping = 0;
775 skb = pd->rx_buffers[index].skb;
776 pd->rx_buffers[index].skb = NULL;
779 u16 hw_csum = get_unaligned_le16(skb_tail_pointer(skb) +
780 NET_IP_ALIGN + packet_length + 4);
781 put_unaligned_le16(cpu_to_le16(hw_csum), &skb->csum);
782 skb->ip_summed = CHECKSUM_COMPLETE;
785 skb_reserve(skb, NET_IP_ALIGN);
786 skb_put(skb, packet_length);
788 skb->protocol = eth_type_trans(skb, dev);
790 netif_receive_skb(skb);
791 dev->last_rx = jiffies;
794 static int smsc9420_alloc_rx_buffer(struct smsc9420_pdata *pd, int index)
796 struct sk_buff *skb = netdev_alloc_skb(pd->dev, PKT_BUF_SZ);
799 BUG_ON(pd->rx_buffers[index].skb);
800 BUG_ON(pd->rx_buffers[index].mapping);
802 if (unlikely(!skb)) {
803 smsc_warn(RX_ERR, "Failed to allocate new skb!");
809 mapping = pci_map_single(pd->pdev, skb_tail_pointer(skb),
810 PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
811 if (pci_dma_mapping_error(pd->pdev, mapping)) {
812 dev_kfree_skb_any(skb);
813 smsc_warn(RX_ERR, "pci_map_single failed!");
817 pd->rx_buffers[index].skb = skb;
818 pd->rx_buffers[index].mapping = mapping;
819 pd->rx_ring[index].buffer1 = mapping + NET_IP_ALIGN;
820 pd->rx_ring[index].status = RDES0_OWN_;
826 static void smsc9420_alloc_new_rx_buffers(struct smsc9420_pdata *pd)
828 while (pd->rx_ring_tail != pd->rx_ring_head) {
829 if (smsc9420_alloc_rx_buffer(pd, pd->rx_ring_tail))
832 pd->rx_ring_tail = (pd->rx_ring_tail + 1) % RX_RING_SIZE;
836 static int smsc9420_rx_poll(struct napi_struct *napi, int budget)
838 struct smsc9420_pdata *pd =
839 container_of(napi, struct smsc9420_pdata, napi);
840 struct net_device *dev = pd->dev;
841 u32 drop_frame_cnt, dma_intr_ena, status;
844 for (work_done = 0; work_done < budget; work_done++) {
846 status = pd->rx_ring[pd->rx_ring_head].status;
848 /* stop if DMAC owns this dma descriptor */
849 if (status & RDES0_OWN_)
852 smsc9420_rx_count_stats(dev, status);
853 smsc9420_rx_handoff(pd, pd->rx_ring_head, status);
854 pd->rx_ring_head = (pd->rx_ring_head + 1) % RX_RING_SIZE;
855 smsc9420_alloc_new_rx_buffers(pd);
858 drop_frame_cnt = smsc9420_reg_read(pd, MISS_FRAME_CNTR);
859 dev->stats.rx_dropped +=
860 (drop_frame_cnt & 0xFFFF) + ((drop_frame_cnt >> 17) & 0x3FF);
863 smsc9420_reg_write(pd, RX_POLL_DEMAND, 1);
864 smsc9420_pci_flush_write(pd);
866 if (work_done < budget) {
867 netif_rx_complete(dev, &pd->napi);
869 /* re-enable RX DMA interrupts */
870 dma_intr_ena = smsc9420_reg_read(pd, DMAC_INTR_ENA);
871 dma_intr_ena |= (DMAC_INTR_ENA_RX_ | DMAC_INTR_ENA_NIS_);
872 smsc9420_reg_write(pd, DMAC_INTR_ENA, dma_intr_ena);
873 smsc9420_pci_flush_write(pd);
879 smsc9420_tx_update_stats(struct net_device *dev, u32 status, u32 length)
881 if (unlikely(status & TDES0_ERROR_SUMMARY_)) {
882 dev->stats.tx_errors++;
883 if (status & (TDES0_EXCESSIVE_DEFERRAL_ |
884 TDES0_EXCESSIVE_COLLISIONS_))
885 dev->stats.tx_aborted_errors++;
887 if (status & (TDES0_LOSS_OF_CARRIER_ | TDES0_NO_CARRIER_))
888 dev->stats.tx_carrier_errors++;
890 dev->stats.tx_packets++;
891 dev->stats.tx_bytes += (length & 0x7FF);
894 if (unlikely(status & TDES0_EXCESSIVE_COLLISIONS_)) {
895 dev->stats.collisions += 16;
897 dev->stats.collisions +=
898 (status & TDES0_COLLISION_COUNT_MASK_) >>
899 TDES0_COLLISION_COUNT_SHFT_;
902 if (unlikely(status & TDES0_HEARTBEAT_FAIL_))
903 dev->stats.tx_heartbeat_errors++;
906 /* Check for completed dma transfers, update stats and free skbs */
907 static void smsc9420_complete_tx(struct net_device *dev)
909 struct smsc9420_pdata *pd = netdev_priv(dev);
911 while (pd->tx_ring_tail != pd->tx_ring_head) {
912 int index = pd->tx_ring_tail;
916 status = pd->tx_ring[index].status;
917 length = pd->tx_ring[index].length;
919 /* Check if DMA still owns this descriptor */
920 if (unlikely(TDES0_OWN_ & status))
923 smsc9420_tx_update_stats(dev, status, length);
925 BUG_ON(!pd->tx_buffers[index].skb);
926 BUG_ON(!pd->tx_buffers[index].mapping);
928 pci_unmap_single(pd->pdev, pd->tx_buffers[index].mapping,
929 pd->tx_buffers[index].skb->len, PCI_DMA_TODEVICE);
930 pd->tx_buffers[index].mapping = 0;
932 dev_kfree_skb_any(pd->tx_buffers[index].skb);
933 pd->tx_buffers[index].skb = NULL;
935 pd->tx_ring[index].buffer1 = 0;
938 pd->tx_ring_tail = (pd->tx_ring_tail + 1) % TX_RING_SIZE;
942 static int smsc9420_hard_start_xmit(struct sk_buff *skb, struct net_device *dev)
944 struct smsc9420_pdata *pd = netdev_priv(dev);
946 int index = pd->tx_ring_head;
948 bool about_to_take_last_desc =
949 (((pd->tx_ring_head + 2) % TX_RING_SIZE) == pd->tx_ring_tail);
951 smsc9420_complete_tx(dev);
954 BUG_ON(pd->tx_ring[index].status & TDES0_OWN_);
955 BUG_ON(pd->tx_buffers[index].skb);
956 BUG_ON(pd->tx_buffers[index].mapping);
958 mapping = pci_map_single(pd->pdev, skb->data,
959 skb->len, PCI_DMA_TODEVICE);
960 if (pci_dma_mapping_error(pd->pdev, mapping)) {
961 smsc_warn(TX_ERR, "pci_map_single failed, dropping packet");
962 return NETDEV_TX_BUSY;
965 pd->tx_buffers[index].skb = skb;
966 pd->tx_buffers[index].mapping = mapping;
968 tmp_desc1 = (TDES1_LS_ | ((u32)skb->len & 0x7FF));
969 if (unlikely(about_to_take_last_desc)) {
970 tmp_desc1 |= TDES1_IC_;
971 netif_stop_queue(pd->dev);
974 /* check if we are at the last descriptor and need to set EOR */
975 if (unlikely(index == (TX_RING_SIZE - 1)))
976 tmp_desc1 |= TDES1_TER_;
978 pd->tx_ring[index].buffer1 = mapping;
979 pd->tx_ring[index].length = tmp_desc1;
983 pd->tx_ring_head = (pd->tx_ring_head + 1) % TX_RING_SIZE;
985 /* assign ownership to DMAC */
986 pd->tx_ring[index].status = TDES0_OWN_;
990 smsc9420_reg_write(pd, TX_POLL_DEMAND, 1);
991 smsc9420_pci_flush_write(pd);
993 dev->trans_start = jiffies;
998 static struct net_device_stats *smsc9420_get_stats(struct net_device *dev)
1000 struct smsc9420_pdata *pd = netdev_priv(dev);
1001 u32 counter = smsc9420_reg_read(pd, MISS_FRAME_CNTR);
1002 dev->stats.rx_dropped +=
1003 (counter & 0x0000FFFF) + ((counter >> 17) & 0x000003FF);
1007 static void smsc9420_set_multicast_list(struct net_device *dev)
1009 struct smsc9420_pdata *pd = netdev_priv(dev);
1010 u32 mac_cr = smsc9420_reg_read(pd, MAC_CR);
1012 if (dev->flags & IFF_PROMISC) {
1013 smsc_dbg(HW, "Promiscuous Mode Enabled");
1014 mac_cr |= MAC_CR_PRMS_;
1015 mac_cr &= (~MAC_CR_MCPAS_);
1016 mac_cr &= (~MAC_CR_HPFILT_);
1017 } else if (dev->flags & IFF_ALLMULTI) {
1018 smsc_dbg(HW, "Receive all Multicast Enabled");
1019 mac_cr &= (~MAC_CR_PRMS_);
1020 mac_cr |= MAC_CR_MCPAS_;
1021 mac_cr &= (~MAC_CR_HPFILT_);
1022 } else if (dev->mc_count > 0) {
1023 struct dev_mc_list *mc_list = dev->mc_list;
1024 u32 hash_lo = 0, hash_hi = 0;
1026 smsc_dbg(HW, "Multicast filter enabled");
1028 u32 bit_num = smsc9420_hash(mc_list->dmi_addr);
1029 u32 mask = 1 << (bit_num & 0x1F);
1036 mc_list = mc_list->next;
1038 smsc9420_reg_write(pd, HASHH, hash_hi);
1039 smsc9420_reg_write(pd, HASHL, hash_lo);
1041 mac_cr &= (~MAC_CR_PRMS_);
1042 mac_cr &= (~MAC_CR_MCPAS_);
1043 mac_cr |= MAC_CR_HPFILT_;
1045 smsc_dbg(HW, "Receive own packets only.");
1046 smsc9420_reg_write(pd, HASHH, 0);
1047 smsc9420_reg_write(pd, HASHL, 0);
1049 mac_cr &= (~MAC_CR_PRMS_);
1050 mac_cr &= (~MAC_CR_MCPAS_);
1051 mac_cr &= (~MAC_CR_HPFILT_);
1054 smsc9420_reg_write(pd, MAC_CR, mac_cr);
1055 smsc9420_pci_flush_write(pd);
1058 static u8 smsc9420_resolve_flowctrl_fulldplx(u16 lcladv, u16 rmtadv)
1062 if (lcladv & ADVERTISE_PAUSE_CAP) {
1063 if (lcladv & ADVERTISE_PAUSE_ASYM) {
1064 if (rmtadv & LPA_PAUSE_CAP)
1065 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1066 else if (rmtadv & LPA_PAUSE_ASYM)
1069 if (rmtadv & LPA_PAUSE_CAP)
1070 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1072 } else if (lcladv & ADVERTISE_PAUSE_ASYM) {
1073 if ((rmtadv & LPA_PAUSE_CAP) && (rmtadv & LPA_PAUSE_ASYM))
1080 static void smsc9420_phy_update_flowcontrol(struct smsc9420_pdata *pd)
1082 struct phy_device *phy_dev = pd->phy_dev;
1085 if (phy_dev->duplex == DUPLEX_FULL) {
1086 u16 lcladv = phy_read(phy_dev, MII_ADVERTISE);
1087 u16 rmtadv = phy_read(phy_dev, MII_LPA);
1088 u8 cap = smsc9420_resolve_flowctrl_fulldplx(lcladv, rmtadv);
1090 if (cap & FLOW_CTRL_RX)
1095 smsc_info(LINK, "rx pause %s, tx pause %s",
1096 (cap & FLOW_CTRL_RX ? "enabled" : "disabled"),
1097 (cap & FLOW_CTRL_TX ? "enabled" : "disabled"));
1099 smsc_info(LINK, "half duplex");
1103 smsc9420_reg_write(pd, FLOW, flow);
1106 /* Update link mode if anything has changed. Called periodically when the
1107 * PHY is in polling mode, even if nothing has changed. */
1108 static void smsc9420_phy_adjust_link(struct net_device *dev)
1110 struct smsc9420_pdata *pd = netdev_priv(dev);
1111 struct phy_device *phy_dev = pd->phy_dev;
1114 if (phy_dev->duplex != pd->last_duplex) {
1115 u32 mac_cr = smsc9420_reg_read(pd, MAC_CR);
1116 if (phy_dev->duplex) {
1117 smsc_dbg(LINK, "full duplex mode");
1118 mac_cr |= MAC_CR_FDPX_;
1120 smsc_dbg(LINK, "half duplex mode");
1121 mac_cr &= ~MAC_CR_FDPX_;
1123 smsc9420_reg_write(pd, MAC_CR, mac_cr);
1125 smsc9420_phy_update_flowcontrol(pd);
1126 pd->last_duplex = phy_dev->duplex;
1129 carrier = netif_carrier_ok(dev);
1130 if (carrier != pd->last_carrier) {
1132 smsc_dbg(LINK, "carrier OK");
1134 smsc_dbg(LINK, "no carrier");
1135 pd->last_carrier = carrier;
1139 static int smsc9420_mii_probe(struct net_device *dev)
1141 struct smsc9420_pdata *pd = netdev_priv(dev);
1142 struct phy_device *phydev = NULL;
1144 BUG_ON(pd->phy_dev);
1146 /* Device only supports internal PHY at address 1 */
1147 if (!pd->mii_bus->phy_map[1]) {
1148 pr_err("%s: no PHY found at address 1\n", dev->name);
1152 phydev = pd->mii_bus->phy_map[1];
1153 smsc_info(PROBE, "PHY addr %d, phy_id 0x%08X", phydev->addr,
1156 phydev = phy_connect(dev, phydev->dev.bus_id,
1157 &smsc9420_phy_adjust_link, 0, PHY_INTERFACE_MODE_MII);
1159 if (IS_ERR(phydev)) {
1160 pr_err("%s: Could not attach to PHY\n", dev->name);
1161 return PTR_ERR(phydev);
1164 pr_info("%s: attached PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n",
1165 dev->name, phydev->drv->name, phydev->dev.bus_id, phydev->irq);
1167 /* mask with MAC supported features */
1168 phydev->supported &= (PHY_BASIC_FEATURES | SUPPORTED_Pause |
1169 SUPPORTED_Asym_Pause);
1170 phydev->advertising = phydev->supported;
1172 pd->phy_dev = phydev;
1173 pd->last_duplex = -1;
1174 pd->last_carrier = -1;
1179 static int smsc9420_mii_init(struct net_device *dev)
1181 struct smsc9420_pdata *pd = netdev_priv(dev);
1182 int err = -ENXIO, i;
1184 pd->mii_bus = mdiobus_alloc();
1189 pd->mii_bus->name = DRV_MDIONAME;
1190 snprintf(pd->mii_bus->id, MII_BUS_ID_SIZE, "%x",
1191 (pd->pdev->bus->number << 8) | pd->pdev->devfn);
1192 pd->mii_bus->priv = pd;
1193 pd->mii_bus->read = smsc9420_mii_read;
1194 pd->mii_bus->write = smsc9420_mii_write;
1195 pd->mii_bus->irq = pd->phy_irq;
1196 for (i = 0; i < PHY_MAX_ADDR; ++i)
1197 pd->mii_bus->irq[i] = PHY_POLL;
1199 /* Mask all PHYs except ID 1 (internal) */
1200 pd->mii_bus->phy_mask = ~(1 << 1);
1202 if (mdiobus_register(pd->mii_bus)) {
1203 smsc_warn(PROBE, "Error registering mii bus");
1204 goto err_out_free_bus_2;
1207 if (smsc9420_mii_probe(dev) < 0) {
1208 smsc_warn(PROBE, "Error probing mii bus");
1209 goto err_out_unregister_bus_3;
1214 err_out_unregister_bus_3:
1215 mdiobus_unregister(pd->mii_bus);
1217 mdiobus_free(pd->mii_bus);
1222 static int smsc9420_alloc_tx_ring(struct smsc9420_pdata *pd)
1226 BUG_ON(!pd->tx_ring);
1228 pd->tx_buffers = kmalloc((sizeof(struct smsc9420_ring_info) *
1229 TX_RING_SIZE), GFP_KERNEL);
1230 if (!pd->tx_buffers) {
1231 smsc_warn(IFUP, "Failed to allocated tx_buffers");
1235 /* Initialize the TX Ring */
1236 for (i = 0; i < TX_RING_SIZE; i++) {
1237 pd->tx_buffers[i].skb = NULL;
1238 pd->tx_buffers[i].mapping = 0;
1239 pd->tx_ring[i].status = 0;
1240 pd->tx_ring[i].length = 0;
1241 pd->tx_ring[i].buffer1 = 0;
1242 pd->tx_ring[i].buffer2 = 0;
1244 pd->tx_ring[TX_RING_SIZE - 1].length = TDES1_TER_;
1247 pd->tx_ring_head = 0;
1248 pd->tx_ring_tail = 0;
1250 smsc9420_reg_write(pd, TX_BASE_ADDR, pd->tx_dma_addr);
1251 smsc9420_pci_flush_write(pd);
1256 static int smsc9420_alloc_rx_ring(struct smsc9420_pdata *pd)
1260 BUG_ON(!pd->rx_ring);
1262 pd->rx_buffers = kmalloc((sizeof(struct smsc9420_ring_info) *
1263 RX_RING_SIZE), GFP_KERNEL);
1264 if (pd->rx_buffers == NULL) {
1265 smsc_warn(IFUP, "Failed to allocated rx_buffers");
1269 /* initialize the rx ring */
1270 for (i = 0; i < RX_RING_SIZE; i++) {
1271 pd->rx_ring[i].status = 0;
1272 pd->rx_ring[i].length = PKT_BUF_SZ;
1273 pd->rx_ring[i].buffer2 = 0;
1274 pd->rx_buffers[i].skb = NULL;
1275 pd->rx_buffers[i].mapping = 0;
1277 pd->rx_ring[RX_RING_SIZE - 1].length = (PKT_BUF_SZ | RDES1_RER_);
1279 /* now allocate the entire ring of skbs */
1280 for (i = 0; i < RX_RING_SIZE; i++) {
1281 if (smsc9420_alloc_rx_buffer(pd, i)) {
1282 smsc_warn(IFUP, "failed to allocate rx skb %d", i);
1283 goto out_free_rx_skbs;
1287 pd->rx_ring_head = 0;
1288 pd->rx_ring_tail = 0;
1290 smsc9420_reg_write(pd, VLAN1, ETH_P_8021Q);
1291 smsc_dbg(IFUP, "VLAN1 = 0x%08x", smsc9420_reg_read(pd, VLAN1));
1295 u32 coe = smsc9420_reg_read(pd, COE_CR) | RX_COE_EN;
1296 smsc9420_reg_write(pd, COE_CR, coe);
1297 smsc_dbg(IFUP, "COE_CR = 0x%08x", coe);
1300 smsc9420_reg_write(pd, RX_BASE_ADDR, pd->rx_dma_addr);
1301 smsc9420_pci_flush_write(pd);
1306 smsc9420_free_rx_ring(pd);
1311 static int smsc9420_open(struct net_device *dev)
1313 struct smsc9420_pdata *pd;
1314 u32 bus_mode, mac_cr, dmac_control, int_cfg, dma_intr_ena, int_ctl;
1315 unsigned long flags;
1316 int result = 0, timeout;
1319 pd = netdev_priv(dev);
1322 if (!is_valid_ether_addr(dev->dev_addr)) {
1323 smsc_warn(IFUP, "dev_addr is not a valid MAC address");
1324 result = -EADDRNOTAVAIL;
1328 netif_carrier_off(dev);
1330 /* disable, mask and acknowlege all interrupts */
1331 spin_lock_irqsave(&pd->int_lock, flags);
1332 int_cfg = smsc9420_reg_read(pd, INT_CFG) & (~INT_CFG_IRQ_EN_);
1333 smsc9420_reg_write(pd, INT_CFG, int_cfg);
1334 smsc9420_reg_write(pd, INT_CTL, 0);
1335 spin_unlock_irqrestore(&pd->int_lock, flags);
1336 smsc9420_reg_write(pd, DMAC_INTR_ENA, 0);
1337 smsc9420_reg_write(pd, INT_STAT, 0xFFFFFFFF);
1338 smsc9420_pci_flush_write(pd);
1340 if (request_irq(dev->irq, smsc9420_isr, IRQF_SHARED | IRQF_DISABLED,
1342 smsc_warn(IFUP, "Unable to use IRQ = %d", dev->irq);
1347 smsc9420_dmac_soft_reset(pd);
1349 /* make sure MAC_CR is sane */
1350 smsc9420_reg_write(pd, MAC_CR, 0);
1352 smsc9420_set_mac_address(dev);
1354 /* Configure GPIO pins to drive LEDs */
1355 smsc9420_reg_write(pd, GPIO_CFG,
1356 (GPIO_CFG_LED_3_ | GPIO_CFG_LED_2_ | GPIO_CFG_LED_1_));
1358 bus_mode = BUS_MODE_DMA_BURST_LENGTH_16;
1361 bus_mode |= BUS_MODE_DBO_;
1364 smsc9420_reg_write(pd, BUS_MODE, bus_mode);
1366 smsc9420_pci_flush_write(pd);
1368 /* set bus master bridge arbitration priority for Rx and TX DMA */
1369 smsc9420_reg_write(pd, BUS_CFG, BUS_CFG_RXTXWEIGHT_4_1);
1371 smsc9420_reg_write(pd, DMAC_CONTROL,
1372 (DMAC_CONTROL_SF_ | DMAC_CONTROL_OSF_));
1374 smsc9420_pci_flush_write(pd);
1376 /* test the IRQ connection to the ISR */
1377 smsc_dbg(IFUP, "Testing ISR using IRQ %d", dev->irq);
1379 spin_lock_irqsave(&pd->int_lock, flags);
1380 /* configure interrupt deassertion timer and enable interrupts */
1381 int_cfg = smsc9420_reg_read(pd, INT_CFG) | INT_CFG_IRQ_EN_;
1382 int_cfg &= ~(INT_CFG_INT_DEAS_MASK);
1383 int_cfg |= (INT_DEAS_TIME & INT_CFG_INT_DEAS_MASK);
1384 smsc9420_reg_write(pd, INT_CFG, int_cfg);
1386 /* unmask software interrupt */
1387 int_ctl = smsc9420_reg_read(pd, INT_CTL) | INT_CTL_SW_INT_EN_;
1388 smsc9420_reg_write(pd, INT_CTL, int_ctl);
1389 spin_unlock_irqrestore(&pd->int_lock, flags);
1390 smsc9420_pci_flush_write(pd);
1393 pd->software_irq_signal = false;
1396 if (pd->software_irq_signal)
1401 /* disable interrupts */
1402 spin_lock_irqsave(&pd->int_lock, flags);
1403 int_cfg = smsc9420_reg_read(pd, INT_CFG) & (~INT_CFG_IRQ_EN_);
1404 smsc9420_reg_write(pd, INT_CFG, int_cfg);
1405 spin_unlock_irqrestore(&pd->int_lock, flags);
1407 if (!pd->software_irq_signal) {
1408 smsc_warn(IFUP, "ISR failed signaling test");
1410 goto out_free_irq_1;
1413 smsc_dbg(IFUP, "ISR passed test using IRQ %d", dev->irq);
1415 result = smsc9420_alloc_tx_ring(pd);
1417 smsc_warn(IFUP, "Failed to Initialize tx dma ring");
1419 goto out_free_irq_1;
1422 result = smsc9420_alloc_rx_ring(pd);
1424 smsc_warn(IFUP, "Failed to Initialize rx dma ring");
1426 goto out_free_tx_ring_2;
1429 result = smsc9420_mii_init(dev);
1431 smsc_warn(IFUP, "Failed to initialize Phy");
1433 goto out_free_rx_ring_3;
1436 /* Bring the PHY up */
1437 phy_start(pd->phy_dev);
1439 napi_enable(&pd->napi);
1441 /* start tx and rx */
1442 mac_cr = smsc9420_reg_read(pd, MAC_CR) | MAC_CR_TXEN_ | MAC_CR_RXEN_;
1443 smsc9420_reg_write(pd, MAC_CR, mac_cr);
1445 dmac_control = smsc9420_reg_read(pd, DMAC_CONTROL);
1446 dmac_control |= DMAC_CONTROL_ST_ | DMAC_CONTROL_SR_;
1447 smsc9420_reg_write(pd, DMAC_CONTROL, dmac_control);
1448 smsc9420_pci_flush_write(pd);
1450 dma_intr_ena = smsc9420_reg_read(pd, DMAC_INTR_ENA);
1452 (DMAC_INTR_ENA_TX_ | DMAC_INTR_ENA_RX_ | DMAC_INTR_ENA_NIS_);
1453 smsc9420_reg_write(pd, DMAC_INTR_ENA, dma_intr_ena);
1454 smsc9420_pci_flush_write(pd);
1456 netif_wake_queue(dev);
1458 smsc9420_reg_write(pd, RX_POLL_DEMAND, 1);
1460 /* enable interrupts */
1461 spin_lock_irqsave(&pd->int_lock, flags);
1462 int_cfg = smsc9420_reg_read(pd, INT_CFG) | INT_CFG_IRQ_EN_;
1463 smsc9420_reg_write(pd, INT_CFG, int_cfg);
1464 spin_unlock_irqrestore(&pd->int_lock, flags);
1469 smsc9420_free_rx_ring(pd);
1471 smsc9420_free_tx_ring(pd);
1473 free_irq(dev->irq, pd);
1480 static int smsc9420_suspend(struct pci_dev *pdev, pm_message_t state)
1482 struct net_device *dev = pci_get_drvdata(pdev);
1483 struct smsc9420_pdata *pd = netdev_priv(dev);
1487 /* disable interrupts */
1488 spin_lock_irqsave(&pd->int_lock, flags);
1489 int_cfg = smsc9420_reg_read(pd, INT_CFG) & (~INT_CFG_IRQ_EN_);
1490 smsc9420_reg_write(pd, INT_CFG, int_cfg);
1491 spin_unlock_irqrestore(&pd->int_lock, flags);
1493 if (netif_running(dev)) {
1494 netif_tx_disable(dev);
1495 smsc9420_stop_tx(pd);
1496 smsc9420_free_tx_ring(pd);
1498 napi_disable(&pd->napi);
1499 smsc9420_stop_rx(pd);
1500 smsc9420_free_rx_ring(pd);
1502 free_irq(dev->irq, pd);
1504 netif_device_detach(dev);
1507 pci_save_state(pdev);
1508 pci_enable_wake(pdev, pci_choose_state(pdev, state), 0);
1509 pci_disable_device(pdev);
1510 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1515 static int smsc9420_resume(struct pci_dev *pdev)
1517 struct net_device *dev = pci_get_drvdata(pdev);
1518 struct smsc9420_pdata *pd = netdev_priv(dev);
1521 pci_set_power_state(pdev, PCI_D0);
1522 pci_restore_state(pdev);
1524 err = pci_enable_device(pdev);
1528 pci_set_master(pdev);
1530 err = pci_enable_wake(pdev, 0, 0);
1532 smsc_warn(IFUP, "pci_enable_wake failed: %d", err);
1534 if (netif_running(dev)) {
1535 err = smsc9420_open(dev);
1536 netif_device_attach(dev);
1541 #endif /* CONFIG_PM */
1543 static const struct net_device_ops smsc9420_netdev_ops = {
1544 .ndo_open = smsc9420_open,
1545 .ndo_stop = smsc9420_stop,
1546 .ndo_start_xmit = smsc9420_hard_start_xmit,
1547 .ndo_get_stats = smsc9420_get_stats,
1548 .ndo_set_multicast_list = smsc9420_set_multicast_list,
1549 .ndo_do_ioctl = smsc9420_do_ioctl,
1550 .ndo_validate_addr = eth_validate_addr,
1551 #ifdef CONFIG_NET_POLL_CONTROLLER
1552 .ndo_poll_controller = smsc9420_poll_controller,
1553 #endif /* CONFIG_NET_POLL_CONTROLLER */
1556 static int __devinit
1557 smsc9420_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1559 struct net_device *dev;
1560 struct smsc9420_pdata *pd;
1561 void __iomem *virt_addr;
1565 printk(KERN_INFO DRV_DESCRIPTION " version " DRV_VERSION "\n");
1567 /* First do the PCI initialisation */
1568 result = pci_enable_device(pdev);
1569 if (unlikely(result)) {
1570 printk(KERN_ERR "Cannot enable smsc9420\n");
1574 pci_set_master(pdev);
1576 dev = alloc_etherdev(sizeof(*pd));
1578 printk(KERN_ERR "ether device alloc failed\n");
1579 goto out_disable_pci_device_1;
1582 SET_NETDEV_DEV(dev, &pdev->dev);
1584 if (!(pci_resource_flags(pdev, SMSC_BAR) & IORESOURCE_MEM)) {
1585 printk(KERN_ERR "Cannot find PCI device base address\n");
1586 goto out_free_netdev_2;
1589 if ((pci_request_regions(pdev, DRV_NAME))) {
1590 printk(KERN_ERR "Cannot obtain PCI resources, aborting.\n");
1591 goto out_free_netdev_2;
1594 if (pci_set_dma_mask(pdev, DMA_32BIT_MASK)) {
1595 printk(KERN_ERR "No usable DMA configuration, aborting.\n");
1596 goto out_free_regions_3;
1599 virt_addr = ioremap(pci_resource_start(pdev, SMSC_BAR),
1600 pci_resource_len(pdev, SMSC_BAR));
1602 printk(KERN_ERR "Cannot map device registers, aborting.\n");
1603 goto out_free_regions_3;
1606 /* registers are double mapped with 0 offset for LE and 0x200 for BE */
1607 virt_addr += LAN9420_CPSR_ENDIAN_OFFSET;
1609 dev->base_addr = (ulong)virt_addr;
1611 pd = netdev_priv(dev);
1613 /* pci descriptors are created in the PCI consistent area */
1614 pd->rx_ring = pci_alloc_consistent(pdev,
1615 sizeof(struct smsc9420_dma_desc) * RX_RING_SIZE +
1616 sizeof(struct smsc9420_dma_desc) * TX_RING_SIZE,
1622 /* descriptors are aligned due to the nature of pci_alloc_consistent */
1623 pd->tx_ring = (struct smsc9420_dma_desc *)
1624 (pd->rx_ring + RX_RING_SIZE);
1625 pd->tx_dma_addr = pd->rx_dma_addr +
1626 sizeof(struct smsc9420_dma_desc) * RX_RING_SIZE;
1630 pd->base_addr = virt_addr;
1631 pd->msg_enable = smsc_debug;
1634 smsc_dbg(PROBE, "lan_base=0x%08lx", (ulong)virt_addr);
1636 id_rev = smsc9420_reg_read(pd, ID_REV);
1637 switch (id_rev & 0xFFFF0000) {
1639 smsc_info(PROBE, "LAN9420 identified, ID_REV=0x%08X", id_rev);
1642 smsc_warn(PROBE, "LAN9420 NOT identified");
1643 smsc_warn(PROBE, "ID_REV=0x%08X", id_rev);
1644 goto out_free_dmadesc_5;
1647 smsc9420_dmac_soft_reset(pd);
1648 smsc9420_eeprom_reload(pd);
1649 smsc9420_check_mac_address(dev);
1651 dev->netdev_ops = &smsc9420_netdev_ops;
1652 dev->ethtool_ops = &smsc9420_ethtool_ops;
1653 dev->irq = pdev->irq;
1655 netif_napi_add(dev, &pd->napi, smsc9420_rx_poll, NAPI_WEIGHT);
1657 result = register_netdev(dev);
1659 smsc_warn(PROBE, "error %i registering device", result);
1660 goto out_free_dmadesc_5;
1663 pci_set_drvdata(pdev, dev);
1665 spin_lock_init(&pd->int_lock);
1666 spin_lock_init(&pd->phy_lock);
1668 dev_info(&dev->dev, "MAC Address: %pM\n", dev->dev_addr);
1673 pci_free_consistent(pdev, sizeof(struct smsc9420_dma_desc) *
1674 (RX_RING_SIZE + TX_RING_SIZE), pd->rx_ring, pd->rx_dma_addr);
1676 iounmap(virt_addr - LAN9420_CPSR_ENDIAN_OFFSET);
1678 pci_release_regions(pdev);
1681 out_disable_pci_device_1:
1682 pci_disable_device(pdev);
1687 static void __devexit smsc9420_remove(struct pci_dev *pdev)
1689 struct net_device *dev;
1690 struct smsc9420_pdata *pd;
1692 dev = pci_get_drvdata(pdev);
1696 pci_set_drvdata(pdev, NULL);
1698 pd = netdev_priv(dev);
1699 unregister_netdev(dev);
1701 /* tx_buffers and rx_buffers are freed in stop */
1702 BUG_ON(pd->tx_buffers);
1703 BUG_ON(pd->rx_buffers);
1705 BUG_ON(!pd->tx_ring);
1706 BUG_ON(!pd->rx_ring);
1708 pci_free_consistent(pdev, sizeof(struct smsc9420_dma_desc) *
1709 (RX_RING_SIZE + TX_RING_SIZE), pd->rx_ring, pd->rx_dma_addr);
1711 iounmap(pd->base_addr - LAN9420_CPSR_ENDIAN_OFFSET);
1712 pci_release_regions(pdev);
1714 pci_disable_device(pdev);
1717 static struct pci_driver smsc9420_driver = {
1719 .id_table = smsc9420_id_table,
1720 .probe = smsc9420_probe,
1721 .remove = __devexit_p(smsc9420_remove),
1723 .suspend = smsc9420_suspend,
1724 .resume = smsc9420_resume,
1725 #endif /* CONFIG_PM */
1728 static int __init smsc9420_init_module(void)
1730 smsc_debug = netif_msg_init(debug, SMSC_MSG_DEFAULT);
1732 return pci_register_driver(&smsc9420_driver);
1735 static void __exit smsc9420_exit_module(void)
1737 pci_unregister_driver(&smsc9420_driver);
1740 module_init(smsc9420_init_module);
1741 module_exit(smsc9420_exit_module);