drivers/net/tg3.c

   1 /*
   2  * tg3.c: Broadcom Tigon3 ethernet driver.
   3  *
   4  * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
   5  * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
   6  * Copyright (C) 2004 Sun Microsystems Inc.
   7  * Copyright (C) 2005-2007 Broadcom Corporation.
   8  *
   9  * Firmware is:
  10  *      Derived from proprietary unpublished source code,
  11  *      Copyright (C) 2000-2003 Broadcom Corporation.
  12  *
  13  *      Permission is hereby granted for the distribution of this firmware
  14  *      data in hexadecimal or equivalent format, provided this copyright
  15  *      notice is accompanying it.
  16  */
  17
  18
  19 #include <linux/module.h>
  20 #include <linux/moduleparam.h>
  21 #include <linux/kernel.h>
  22 #include <linux/types.h>
  23 #include <linux/compiler.h>
  24 #include <linux/slab.h>
  25 #include <linux/delay.h>
  26 #include <linux/in.h>
  27 #include <linux/init.h>
  28 #include <linux/ioport.h>
  29 #include <linux/pci.h>
  30 #include <linux/netdevice.h>
  31 #include <linux/etherdevice.h>
  32 #include <linux/skbuff.h>
  33 #include <linux/ethtool.h>
  34 #include <linux/mii.h>
  35 #include <linux/if_vlan.h>
  36 #include <linux/ip.h>
  37 #include <linux/tcp.h>
  38 #include <linux/workqueue.h>
  39 #include <linux/prefetch.h>
  40 #include <linux/dma-mapping.h>
  41
  42 #include <net/checksum.h>
  43 #include <net/ip.h>
  44
  45 #include <asm/system.h>
  46 #include <asm/io.h>
  47 #include <asm/byteorder.h>
  48 #include <asm/uaccess.h>
  49
  50 #ifdef CONFIG_SPARC
  51 #include <asm/idprom.h>
  52 #include <asm/prom.h>
  53 #endif
  54
  55 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
  56 #define TG3_VLAN_TAG_USED 1
  57 #else
  58 #define TG3_VLAN_TAG_USED 0
  59 #endif
  60
  61 #define TG3_TSO_SUPPORT 1
  62
  63 #include "tg3.h"
  64
  65 #define DRV_MODULE_NAME         "tg3"
  66 #define PFX DRV_MODULE_NAME     ": "
  67 #define DRV_MODULE_VERSION      "3.92"
  68 #define DRV_MODULE_RELDATE      "May 2, 2008"
  69
  70 #define TG3_DEF_MAC_MODE        0
  71 #define TG3_DEF_RX_MODE         0
  72 #define TG3_DEF_TX_MODE         0
  73 #define TG3_DEF_MSG_ENABLE        \
  74         (NETIF_MSG_DRV          | \
  75          NETIF_MSG_PROBE        | \
  76          NETIF_MSG_LINK         | \
  77          NETIF_MSG_TIMER        | \
  78          NETIF_MSG_IFDOWN       | \
  79          NETIF_MSG_IFUP         | \
  80          NETIF_MSG_RX_ERR       | \
  81          NETIF_MSG_TX_ERR)
  82
  83 /* length of time before we decide the hardware is borked,
  84  * and dev->tx_timeout() should be called to fix the problem
  85  */
  86 #define TG3_TX_TIMEOUT                  (5 * HZ)
  87
  88 /* hardware minimum and maximum for a single frame's data payload */
  89 #define TG3_MIN_MTU                     60
  90 #define TG3_MAX_MTU(tp) \
  91         ((tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) ? 9000 : 1500)
  92
  93 /* These numbers seem to be hard coded in the NIC firmware somehow.
  94  * You can't change the ring sizes, but you can change where you place
  95  * them in the NIC onboard memory.
  96  */
  97 #define TG3_RX_RING_SIZE                512
  98 #define TG3_DEF_RX_RING_PENDING         200
  99 #define TG3_RX_JUMBO_RING_SIZE          256
 100 #define TG3_DEF_RX_JUMBO_RING_PENDING   100
 101
 102 /* Do not place this n-ring entries value into the tp struct itself,
 103  * we really want to expose these constants to GCC so that modulo et
 104  * al.  operations are done with shifts and masks instead of with
 105  * hw multiply/modulo instructions.  Another solution would be to
 106  * replace things like '% foo' with '& (foo - 1)'.
 107  */
 108 #define TG3_RX_RCB_RING_SIZE(tp)        \
 109         ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ?  512 : 1024)
 110
 111 #define TG3_TX_RING_SIZE                512
 112 #define TG3_DEF_TX_RING_PENDING         (TG3_TX_RING_SIZE - 1)
 113
 114 #define TG3_RX_RING_BYTES       (sizeof(struct tg3_rx_buffer_desc) * \
 115                                  TG3_RX_RING_SIZE)
 116 #define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
 117                                  TG3_RX_JUMBO_RING_SIZE)
 118 #define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
 119                                    TG3_RX_RCB_RING_SIZE(tp))
 120 #define TG3_TX_RING_BYTES       (sizeof(struct tg3_tx_buffer_desc) * \
 121                                  TG3_TX_RING_SIZE)
 122 #define NEXT_TX(N)              (((N) + 1) & (TG3_TX_RING_SIZE - 1))
 123
 124 #define RX_PKT_BUF_SZ           (1536 + tp->rx_offset + 64)
 125 #define RX_JUMBO_PKT_BUF_SZ     (9046 + tp->rx_offset + 64)
 126
 127 /* minimum number of free TX descriptors required to wake up TX process */
 128 #define TG3_TX_WAKEUP_THRESH(tp)                ((tp)->tx_pending / 4)
 129
 130 /* number of ETHTOOL_GSTATS u64's */
 131 #define TG3_NUM_STATS           (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
 132
 133 #define TG3_NUM_TEST            6
 134
 135 static char version[] __devinitdata =
 136         DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
 137
 138 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
 139 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
 140 MODULE_LICENSE("GPL");
 141 MODULE_VERSION(DRV_MODULE_VERSION);
 142
 143 static int tg3_debug = -1;      /* -1 == use TG3_DEF_MSG_ENABLE as value */
 144 module_param(tg3_debug, int, 0);
 145 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
 146
 147 static struct pci_device_id tg3_pci_tbl[] = {
 148         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
 149         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
 150         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
 151         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
 152         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
 153         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
 154         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
 155         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
 156         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
 157         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
 158         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
 159         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
 160         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
 161         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
 162         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
 163         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
 164         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
 165         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
 166         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
 167         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
 168         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
 169         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
 170         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720)},
 171         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
 172         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
 173         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
 174         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
 175         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M)},
 176         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
 177         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
 178         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
 179         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
 180         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
 181         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
 182         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
 183         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
 184         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
 185         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
 186         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
 187         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
 188         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
 189         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
 190         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
 191         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
 192         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
 193         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
 194         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
 195         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
 196         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
 197         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
 198         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
 199         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
 200         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
 201         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
 202         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
 203         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
 204         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
 205         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
 206         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
 207         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
 208         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
 209         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
 210         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
 211         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
 212         {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
 213         {}
 214 };
 215
 216 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
 217
 218 static const struct {
 219         const char string[ETH_GSTRING_LEN];
 220 } ethtool_stats_keys[TG3_NUM_STATS] = {
 221         { "rx_octets" },
 222         { "rx_fragments" },
 223         { "rx_ucast_packets" },
 224         { "rx_mcast_packets" },
 225         { "rx_bcast_packets" },
 226         { "rx_fcs_errors" },
 227         { "rx_align_errors" },
 228         { "rx_xon_pause_rcvd" },
 229         { "rx_xoff_pause_rcvd" },
 230         { "rx_mac_ctrl_rcvd" },
 231         { "rx_xoff_entered" },
 232         { "rx_frame_too_long_errors" },
 233         { "rx_jabbers" },
 234         { "rx_undersize_packets" },
 235         { "rx_in_length_errors" },
 236         { "rx_out_length_errors" },
 237         { "rx_64_or_less_octet_packets" },
 238         { "rx_65_to_127_octet_packets" },
 239         { "rx_128_to_255_octet_packets" },
 240         { "rx_256_to_511_octet_packets" },
 241         { "rx_512_to_1023_octet_packets" },
 242         { "rx_1024_to_1522_octet_packets" },
 243         { "rx_1523_to_2047_octet_packets" },
 244         { "rx_2048_to_4095_octet_packets" },
 245         { "rx_4096_to_8191_octet_packets" },
 246         { "rx_8192_to_9022_octet_packets" },
 247
 248         { "tx_octets" },
 249         { "tx_collisions" },
 250
 251         { "tx_xon_sent" },
 252         { "tx_xoff_sent" },
 253         { "tx_flow_control" },
 254         { "tx_mac_errors" },
 255         { "tx_single_collisions" },
 256         { "tx_mult_collisions" },
 257         { "tx_deferred" },
 258         { "tx_excessive_collisions" },
 259         { "tx_late_collisions" },
 260         { "tx_collide_2times" },
 261         { "tx_collide_3times" },
 262         { "tx_collide_4times" },
 263         { "tx_collide_5times" },
 264         { "tx_collide_6times" },
 265         { "tx_collide_7times" },
 266         { "tx_collide_8times" },
 267         { "tx_collide_9times" },
 268         { "tx_collide_10times" },
 269         { "tx_collide_11times" },
 270         { "tx_collide_12times" },
 271         { "tx_collide_13times" },
 272         { "tx_collide_14times" },
 273         { "tx_collide_15times" },
 274         { "tx_ucast_packets" },
 275         { "tx_mcast_packets" },
 276         { "tx_bcast_packets" },
 277         { "tx_carrier_sense_errors" },
 278         { "tx_discards" },
 279         { "tx_errors" },
 280
 281         { "dma_writeq_full" },
 282         { "dma_write_prioq_full" },
 283         { "rxbds_empty" },
 284         { "rx_discards" },
 285         { "rx_errors" },
 286         { "rx_threshold_hit" },
 287
 288         { "dma_readq_full" },
 289         { "dma_read_prioq_full" },
 290         { "tx_comp_queue_full" },
 291
 292         { "ring_set_send_prod_index" },
 293         { "ring_status_update" },
 294         { "nic_irqs" },
 295         { "nic_avoided_irqs" },
 296         { "nic_tx_threshold_hit" }
 297 };
 298
 299 static const struct {
 300         const char string[ETH_GSTRING_LEN];
 301 } ethtool_test_keys[TG3_NUM_TEST] = {
 302         { "nvram test     (online) " },
 303         { "link test      (online) " },
 304         { "register test  (offline)" },
 305         { "memory test    (offline)" },
 306         { "loopback test  (offline)" },
 307         { "interrupt test (offline)" },
 308 };
 309
 310 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
 311 {
 312         writel(val, tp->regs + off);
 313 }
 314
 315 static u32 tg3_read32(struct tg3 *tp, u32 off)
 316 {
 317         return (readl(tp->regs + off));
 318 }
 319
 320 static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
 321 {
 322         writel(val, tp->aperegs + off);
 323 }
 324
 325 static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
 326 {
 327         return (readl(tp->aperegs + off));
 328 }
 329
 330 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
 331 {
 332         unsigned long flags;
 333
 334         spin_lock_irqsave(&tp->indirect_lock, flags);
 335         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
 336         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 337         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 338 }
 339
 340 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
 341 {
 342         writel(val, tp->regs + off);
 343         readl(tp->regs + off);
 344 }
 345
 346 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
 347 {
 348         unsigned long flags;
 349         u32 val;
 350
 351         spin_lock_irqsave(&tp->indirect_lock, flags);
 352         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
 353         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
 354         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 355         return val;
 356 }
 357
 358 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
 359 {
 360         unsigned long flags;
 361
 362         if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
 363                 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
 364                                        TG3_64BIT_REG_LOW, val);
 365                 return;
 366         }
 367         if (off == (MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW)) {
 368                 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
 369                                        TG3_64BIT_REG_LOW, val);
 370                 return;
 371         }
 372
 373         spin_lock_irqsave(&tp->indirect_lock, flags);
 374         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
 375         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 376         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 377
 378         /* In indirect mode when disabling interrupts, we also need
 379          * to clear the interrupt bit in the GRC local ctrl register.
 380          */
 381         if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
 382             (val == 0x1)) {
 383                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
 384                                        tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
 385         }
 386 }
 387
 388 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
 389 {
 390         unsigned long flags;
 391         u32 val;
 392
 393         spin_lock_irqsave(&tp->indirect_lock, flags);
 394         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
 395         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
 396         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 397         return val;
 398 }
 399
 400 /* usec_wait specifies the wait time in usec when writing to certain registers
 401  * where it is unsafe to read back the register without some delay.
 402  * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
 403  * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
 404  */
 405 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
 406 {
 407         if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
 408             (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
 409                 /* Non-posted methods */
 410                 tp->write32(tp, off, val);
 411         else {
 412                 /* Posted method */
 413                 tg3_write32(tp, off, val);
 414                 if (usec_wait)
 415                         udelay(usec_wait);
 416                 tp->read32(tp, off);
 417         }
 418         /* Wait again after the read for the posted method to guarantee that
 419          * the wait time is met.
 420          */
 421         if (usec_wait)
 422                 udelay(usec_wait);
 423 }
 424
 425 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
 426 {
 427         tp->write32_mbox(tp, off, val);
 428         if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
 429             !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
 430                 tp->read32_mbox(tp, off);
 431 }
 432
 433 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
 434 {
 435         void __iomem *mbox = tp->regs + off;
 436         writel(val, mbox);
 437         if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
 438                 writel(val, mbox);
 439         if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
 440                 readl(mbox);
 441 }
 442
 443 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
 444 {
 445         return (readl(tp->regs + off + GRCMBOX_BASE));
 446 }
 447
 448 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
 449 {
 450         writel(val, tp->regs + off + GRCMBOX_BASE);
 451 }
 452
 453 #define tw32_mailbox(reg, val)  tp->write32_mbox(tp, reg, val)
 454 #define tw32_mailbox_f(reg, val)        tw32_mailbox_flush(tp, (reg), (val))
 455 #define tw32_rx_mbox(reg, val)  tp->write32_rx_mbox(tp, reg, val)
 456 #define tw32_tx_mbox(reg, val)  tp->write32_tx_mbox(tp, reg, val)
 457 #define tr32_mailbox(reg)       tp->read32_mbox(tp, reg)
 458
 459 #define tw32(reg,val)           tp->write32(tp, reg, val)
 460 #define tw32_f(reg,val)         _tw32_flush(tp,(reg),(val), 0)
 461 #define tw32_wait_f(reg,val,us) _tw32_flush(tp,(reg),(val), (us))
 462 #define tr32(reg)               tp->read32(tp, reg)
 463
 464 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
 465 {
 466         unsigned long flags;
 467
 468         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
 469             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
 470                 return;
 471
 472         spin_lock_irqsave(&tp->indirect_lock, flags);
 473         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
 474                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 475                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 476
 477                 /* Always leave this as zero. */
 478                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 479         } else {
 480                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
 481                 tw32_f(TG3PCI_MEM_WIN_DATA, val);
 482
 483                 /* Always leave this as zero. */
 484                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
 485         }
 486         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 487 }
 488
 489 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
 490 {
 491         unsigned long flags;
 492
 493         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
 494             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
 495                 *val = 0;
 496                 return;
 497         }
 498
 499         spin_lock_irqsave(&tp->indirect_lock, flags);
 500         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
 501                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 502                 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 503
 504                 /* Always leave this as zero. */
 505                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 506         } else {
 507                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
 508                 *val = tr32(TG3PCI_MEM_WIN_DATA);
 509
 510                 /* Always leave this as zero. */
 511                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
 512         }
 513         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 514 }
 515
 516 static void tg3_ape_lock_init(struct tg3 *tp)
 517 {
 518         int i;
 519
 520         /* Make sure the driver hasn't any stale locks. */
 521         for (i = 0; i < 8; i++)
 522                 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + 4 * i,
 523                                 APE_LOCK_GRANT_DRIVER);
 524 }
 525
 526 static int tg3_ape_lock(struct tg3 *tp, int locknum)
 527 {
 528         int i, off;
 529         int ret = 0;
 530         u32 status;
 531
 532         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
 533                 return 0;
 534
 535         switch (locknum) {
 536                 case TG3_APE_LOCK_MEM:
 537                         break;
 538                 default:
 539                         return -EINVAL;
 540         }
 541
 542         off = 4 * locknum;
 543
 544         tg3_ape_write32(tp, TG3_APE_LOCK_REQ + off, APE_LOCK_REQ_DRIVER);
 545
 546         /* Wait for up to 1 millisecond to acquire lock. */
 547         for (i = 0; i < 100; i++) {
 548                 status = tg3_ape_read32(tp, TG3_APE_LOCK_GRANT + off);
 549                 if (status == APE_LOCK_GRANT_DRIVER)
 550                         break;
 551                 udelay(10);
 552         }
 553
 554         if (status != APE_LOCK_GRANT_DRIVER) {
 555                 /* Revoke the lock request. */
 556                 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off,
 557                                 APE_LOCK_GRANT_DRIVER);
 558
 559                 ret = -EBUSY;
 560         }
 561
 562         return ret;
 563 }
 564
 565 static void tg3_ape_unlock(struct tg3 *tp, int locknum)
 566 {
 567         int off;
 568
 569         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
 570                 return;
 571
 572         switch (locknum) {
 573                 case TG3_APE_LOCK_MEM:
 574                         break;
 575                 default:
 576                         return;
 577         }
 578
 579         off = 4 * locknum;
 580         tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off, APE_LOCK_GRANT_DRIVER);
 581 }
 582
 583 static void tg3_disable_ints(struct tg3 *tp)
 584 {
 585         tw32(TG3PCI_MISC_HOST_CTRL,
 586              (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
 587         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
 588 }
 589
 590 static inline void tg3_cond_int(struct tg3 *tp)
 591 {
 592         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
 593             (tp->hw_status->status & SD_STATUS_UPDATED))
 594                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
 595         else
 596                 tw32(HOSTCC_MODE, tp->coalesce_mode |
 597                      (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
 598 }
 599
 600 static void tg3_enable_ints(struct tg3 *tp)
 601 {
 602         tp->irq_sync = 0;
 603         wmb();
 604
 605         tw32(TG3PCI_MISC_HOST_CTRL,
 606              (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
 607         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
 608                        (tp->last_tag << 24));
 609         if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
 610                 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
 611                                (tp->last_tag << 24));
 612         tg3_cond_int(tp);
 613 }
 614
 615 static inline unsigned int tg3_has_work(struct tg3 *tp)
 616 {
 617         struct tg3_hw_status *sblk = tp->hw_status;
 618         unsigned int work_exists = 0;
 619
 620         /* check for phy events */
 621         if (!(tp->tg3_flags &
 622               (TG3_FLAG_USE_LINKCHG_REG |
 623                TG3_FLAG_POLL_SERDES))) {
 624                 if (sblk->status & SD_STATUS_LINK_CHG)
 625                         work_exists = 1;
 626         }
 627         /* check for RX/TX work to do */
 628         if (sblk->idx[0].tx_consumer != tp->tx_cons ||
 629             sblk->idx[0].rx_producer != tp->rx_rcb_ptr)
 630                 work_exists = 1;
 631
 632         return work_exists;
 633 }
 634
 635 /* tg3_restart_ints
 636  *  similar to tg3_enable_ints, but it accurately determines whether there
 637  *  is new work pending and can return without flushing the PIO write
 638  *  which reenables interrupts
 639  */
 640 static void tg3_restart_ints(struct tg3 *tp)
 641 {
 642         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
 643                      tp->last_tag << 24);
 644         mmiowb();
 645
 646         /* When doing tagged status, this work check is unnecessary.
 647          * The last_tag we write above tells the chip which piece of
 648          * work we've completed.
 649          */
 650         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
 651             tg3_has_work(tp))
 652                 tw32(HOSTCC_MODE, tp->coalesce_mode |
 653                      (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
 654 }
 655
 656 static inline void tg3_netif_stop(struct tg3 *tp)
 657 {
 658         tp->dev->trans_start = jiffies; /* prevent tx timeout */
 659         napi_disable(&tp->napi);
 660         netif_tx_disable(tp->dev);
 661 }
 662
 663 static inline void tg3_netif_start(struct tg3 *tp)
 664 {
 665         netif_wake_queue(tp->dev);
 666         /* NOTE: unconditional netif_wake_queue is only appropriate
 667          * so long as all callers are assured to have free tx slots
 668          * (such as after tg3_init_hw)
 669          */
 670         napi_enable(&tp->napi);
 671         tp->hw_status->status |= SD_STATUS_UPDATED;
 672         tg3_enable_ints(tp);
 673 }
 674
 675 static void tg3_switch_clocks(struct tg3 *tp)
 676 {
 677         u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
 678         u32 orig_clock_ctrl;
 679
 680         if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
 681             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
 682                 return;
 683
 684         orig_clock_ctrl = clock_ctrl;
 685         clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
 686                        CLOCK_CTRL_CLKRUN_OENABLE |
 687                        0x1f);
 688         tp->pci_clock_ctrl = clock_ctrl;
 689
 690         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
 691                 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
 692                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
 693                                     clock_ctrl | CLOCK_CTRL_625_CORE, 40);
 694                 }
 695         } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
 696                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
 697                             clock_ctrl |
 698                             (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
 699                             40);
 700                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
 701                             clock_ctrl | (CLOCK_CTRL_ALTCLK),
 702                             40);
 703         }
 704         tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
 705 }
 706
 707 #define PHY_BUSY_LOOPS  5000
 708
 709 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
 710 {
 711         u32 frame_val;
 712         unsigned int loops;
 713         int ret;
 714
 715         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 716                 tw32_f(MAC_MI_MODE,
 717                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
 718                 udelay(80);
 719         }
 720
 721         *val = 0x0;
 722
 723         frame_val  = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
 724                       MI_COM_PHY_ADDR_MASK);
 725         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 726                       MI_COM_REG_ADDR_MASK);
 727         frame_val |= (MI_COM_CMD_READ | MI_COM_START);
 728
 729         tw32_f(MAC_MI_COM, frame_val);
 730
 731         loops = PHY_BUSY_LOOPS;
 732         while (loops != 0) {
 733                 udelay(10);
 734                 frame_val = tr32(MAC_MI_COM);
 735
 736                 if ((frame_val & MI_COM_BUSY) == 0) {
 737                         udelay(5);
 738                         frame_val = tr32(MAC_MI_COM);
 739                         break;
 740                 }
 741                 loops -= 1;
 742         }
 743
 744         ret = -EBUSY;
 745         if (loops != 0) {
 746                 *val = frame_val & MI_COM_DATA_MASK;
 747                 ret = 0;
 748         }
 749
 750         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 751                 tw32_f(MAC_MI_MODE, tp->mi_mode);
 752                 udelay(80);
 753         }
 754
 755         return ret;
 756 }
 757
 758 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
 759 {
 760         u32 frame_val;
 761         unsigned int loops;
 762         int ret;
 763
 764         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 &&
 765             (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
 766                 return 0;
 767
 768         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 769                 tw32_f(MAC_MI_MODE,
 770                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
 771                 udelay(80);
 772         }
 773
 774         frame_val  = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
 775                       MI_COM_PHY_ADDR_MASK);
 776         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 777                       MI_COM_REG_ADDR_MASK);
 778         frame_val |= (val & MI_COM_DATA_MASK);
 779         frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
 780
 781         tw32_f(MAC_MI_COM, frame_val);
 782
 783         loops = PHY_BUSY_LOOPS;
 784         while (loops != 0) {
 785                 udelay(10);
 786                 frame_val = tr32(MAC_MI_COM);
 787                 if ((frame_val & MI_COM_BUSY) == 0) {
 788                         udelay(5);
 789                         frame_val = tr32(MAC_MI_COM);
 790                         break;
 791                 }
 792                 loops -= 1;
 793         }
 794
 795         ret = -EBUSY;
 796         if (loops != 0)
 797                 ret = 0;
 798
 799         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 800                 tw32_f(MAC_MI_MODE, tp->mi_mode);
 801                 udelay(80);
 802         }
 803
 804         return ret;
 805 }
 806
 807 static void tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
 808 {
 809         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
 810         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
 811 }
 812
 813 static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
 814 {
 815         u32 phy;
 816
 817         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
 818             (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
 819                 return;
 820
 821         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
 822                 u32 ephy;
 823
 824                 if (!tg3_readphy(tp, MII_TG3_EPHY_TEST, &ephy)) {
 825                         tg3_writephy(tp, MII_TG3_EPHY_TEST,
 826                                      ephy | MII_TG3_EPHY_SHADOW_EN);
 827                         if (!tg3_readphy(tp, MII_TG3_EPHYTST_MISCCTRL, &phy)) {
 828                                 if (enable)
 829                                         phy |= MII_TG3_EPHYTST_MISCCTRL_MDIX;
 830                                 else
 831                                         phy &= ~MII_TG3_EPHYTST_MISCCTRL_MDIX;
 832                                 tg3_writephy(tp, MII_TG3_EPHYTST_MISCCTRL, phy);
 833                         }
 834                         tg3_writephy(tp, MII_TG3_EPHY_TEST, ephy);
 835                 }
 836         } else {
 837                 phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
 838                       MII_TG3_AUXCTL_SHDWSEL_MISC;
 839                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
 840                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
 841                         if (enable)
 842                                 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
 843                         else
 844                                 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
 845                         phy |= MII_TG3_AUXCTL_MISC_WREN;
 846                         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
 847                 }
 848         }
 849 }
 850
 851 static void tg3_phy_set_wirespeed(struct tg3 *tp)
 852 {
 853         u32 val;
 854
 855         if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
 856                 return;
 857
 858         if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
 859             !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
 860                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
 861                              (val | (1 << 15) | (1 << 4)));
 862 }
 863
 864 static int tg3_bmcr_reset(struct tg3 *tp)
 865 {
 866         u32 phy_control;
 867         int limit, err;
 868
 869         /* OK, reset it, and poll the BMCR_RESET bit until it
 870          * clears or we time out.
 871          */
 872         phy_control = BMCR_RESET;
 873         err = tg3_writephy(tp, MII_BMCR, phy_control);
 874         if (err != 0)
 875                 return -EBUSY;
 876
 877         limit = 5000;
 878         while (limit--) {
 879                 err = tg3_readphy(tp, MII_BMCR, &phy_control);
 880                 if (err != 0)
 881                         return -EBUSY;
 882
 883                 if ((phy_control & BMCR_RESET) == 0) {
 884                         udelay(40);
 885                         break;
 886                 }
 887                 udelay(10);
 888         }
 889         if (limit <= 0)
 890                 return -EBUSY;
 891
 892         return 0;
 893 }
 894
 895 static void tg3_phy_apply_otp(struct tg3 *tp)
 896 {
 897         u32 otp, phy;
 898
 899         if (!tp->phy_otp)
 900                 return;
 901
 902         otp = tp->phy_otp;
 903
 904         /* Enable SM_DSP clock and tx 6dB coding. */
 905         phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
 906               MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
 907               MII_TG3_AUXCTL_ACTL_TX_6DB;
 908         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
 909
 910         phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
 911         phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
 912         tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
 913
 914         phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
 915               ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
 916         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
 917
 918         phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
 919         phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
 920         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
 921
 922         phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
 923         tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
 924
 925         phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
 926         tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
 927
 928         phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
 929               ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
 930         tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
 931
 932         /* Turn off SM_DSP clock. */
 933         phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
 934               MII_TG3_AUXCTL_ACTL_TX_6DB;
 935         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
 936 }
 937
 938 static int tg3_wait_macro_done(struct tg3 *tp)
 939 {
 940         int limit = 100;
 941
 942         while (limit--) {
 943                 u32 tmp32;
 944
 945                 if (!tg3_readphy(tp, 0x16, &tmp32)) {
 946                         if ((tmp32 & 0x1000) == 0)
 947                                 break;
 948                 }
 949         }
 950         if (limit <= 0)
 951                 return -EBUSY;
 952
 953         return 0;
 954 }
 955
 956 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
 957 {
 958         static const u32 test_pat[4][6] = {
 959         { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
 960         { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
 961         { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
 962         { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
 963         };
 964         int chan;
 965
 966         for (chan = 0; chan < 4; chan++) {
 967                 int i;
 968
 969                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
 970                              (chan * 0x2000) | 0x0200);
 971                 tg3_writephy(tp, 0x16, 0x0002);
 972
 973                 for (i = 0; i < 6; i++)
 974                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
 975                                      test_pat[chan][i]);
 976
 977                 tg3_writephy(tp, 0x16, 0x0202);
 978                 if (tg3_wait_macro_done(tp)) {
 979                         *resetp = 1;
 980                         return -EBUSY;
 981                 }
 982
 983                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
 984                              (chan * 0x2000) | 0x0200);
 985                 tg3_writephy(tp, 0x16, 0x0082);
 986                 if (tg3_wait_macro_done(tp)) {
 987                         *resetp = 1;
 988                         return -EBUSY;
 989                 }
 990
 991                 tg3_writephy(tp, 0x16, 0x0802);
 992                 if (tg3_wait_macro_done(tp)) {
 993                         *resetp = 1;
 994                         return -EBUSY;
 995                 }
 996
 997                 for (i = 0; i < 6; i += 2) {
 998                         u32 low, high;
 999
1000                         if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
1001                             tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
1002                             tg3_wait_macro_done(tp)) {
1003                                 *resetp = 1;
1004                                 return -EBUSY;
1005                         }
1006                         low &= 0x7fff;
1007                         high &= 0x000f;
1008                         if (low != test_pat[chan][i] ||
1009                             high != test_pat[chan][i+1]) {
1010                                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
1011                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
1012                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
1013
1014                                 return -EBUSY;
1015                         }
1016                 }
1017         }
1018
1019         return 0;
1020 }
1021
1022 static int tg3_phy_reset_chanpat(struct tg3 *tp)
1023 {
1024         int chan;
1025
1026         for (chan = 0; chan < 4; chan++) {
1027                 int i;
1028
1029                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1030                              (chan * 0x2000) | 0x0200);
1031                 tg3_writephy(tp, 0x16, 0x0002);
1032                 for (i = 0; i < 6; i++)
1033                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
1034                 tg3_writephy(tp, 0x16, 0x0202);
1035                 if (tg3_wait_macro_done(tp))
1036                         return -EBUSY;
1037         }
1038
1039         return 0;
1040 }
1041
1042 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
1043 {
1044         u32 reg32, phy9_orig;
1045         int retries, do_phy_reset, err;
1046
1047         retries = 10;
1048         do_phy_reset = 1;
1049         do {
1050                 if (do_phy_reset) {
1051                         err = tg3_bmcr_reset(tp);
1052                         if (err)
1053                                 return err;
1054                         do_phy_reset = 0;
1055                 }
1056
1057                 /* Disable transmitter and interrupt.  */
1058                 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
1059                         continue;
1060
1061                 reg32 |= 0x3000;
1062                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1063
1064                 /* Set full-duplex, 1000 mbps.  */
1065                 tg3_writephy(tp, MII_BMCR,
1066                              BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
1067
1068                 /* Set to master mode.  */
1069                 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
1070                         continue;
1071
1072                 tg3_writephy(tp, MII_TG3_CTRL,
1073                              (MII_TG3_CTRL_AS_MASTER |
1074                               MII_TG3_CTRL_ENABLE_AS_MASTER));
1075
1076                 /* Enable SM_DSP_CLOCK and 6dB.  */
1077                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1078
1079                 /* Block the PHY control access.  */
1080                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1081                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
1082
1083                 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
1084                 if (!err)
1085                         break;
1086         } while (--retries);
1087
1088         err = tg3_phy_reset_chanpat(tp);
1089         if (err)
1090                 return err;
1091
1092         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1093         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
1094
1095         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
1096         tg3_writephy(tp, 0x16, 0x0000);
1097
1098         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1099             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1100                 /* Set Extended packet length bit for jumbo frames */
1101                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
1102         }
1103         else {
1104                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1105         }
1106
1107         tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
1108
1109         if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
1110                 reg32 &= ~0x3000;
1111                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1112         } else if (!err)
1113                 err = -EBUSY;
1114
1115         return err;
1116 }
1117
1118 static void tg3_link_report(struct tg3 *);
1119
1120 /* This will reset the tigon3 PHY if there is no valid
1121  * link unless the FORCE argument is non-zero.
1122  */
1123 static int tg3_phy_reset(struct tg3 *tp)
1124 {
1125         u32 cpmuctrl;
1126         u32 phy_status;
1127         int err;
1128
1129         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1130                 u32 val;
1131
1132                 val = tr32(GRC_MISC_CFG);
1133                 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
1134                 udelay(40);
1135         }
1136         err  = tg3_readphy(tp, MII_BMSR, &phy_status);
1137         err |= tg3_readphy(tp, MII_BMSR, &phy_status);
1138         if (err != 0)
1139                 return -EBUSY;
1140
1141         if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
1142                 netif_carrier_off(tp->dev);
1143                 tg3_link_report(tp);
1144         }
1145
1146         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1147             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1148             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1149                 err = tg3_phy_reset_5703_4_5(tp);
1150                 if (err)
1151                         return err;
1152                 goto out;
1153         }
1154
1155         cpmuctrl = 0;
1156         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
1157             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
1158                 cpmuctrl = tr32(TG3_CPMU_CTRL);
1159                 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
1160                         tw32(TG3_CPMU_CTRL,
1161                              cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
1162         }
1163
1164         err = tg3_bmcr_reset(tp);
1165         if (err)
1166                 return err;
1167
1168         if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
1169                 u32 phy;
1170
1171                 phy = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
1172                 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, phy);
1173
1174                 tw32(TG3_CPMU_CTRL, cpmuctrl);
1175         }
1176
1177         if (tp->tg3_flags3 & TG3_FLG3_5761_5784_AX_FIXES) {
1178                 u32 val;
1179
1180                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
1181                 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
1182                     CPMU_LSPD_1000MB_MACCLK_12_5) {
1183                         val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
1184                         udelay(40);
1185                         tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
1186                 }
1187
1188                 /* Disable GPHY autopowerdown. */
1189                 tg3_writephy(tp, MII_TG3_MISC_SHDW,
1190                              MII_TG3_MISC_SHDW_WREN |
1191                              MII_TG3_MISC_SHDW_APD_SEL |
1192                              MII_TG3_MISC_SHDW_APD_WKTM_84MS);
1193         }
1194
1195         tg3_phy_apply_otp(tp);
1196
1197 out:
1198         if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
1199                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1200                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1201                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
1202                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1203                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
1204                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1205         }
1206         if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
1207                 tg3_writephy(tp, 0x1c, 0x8d68);
1208                 tg3_writephy(tp, 0x1c, 0x8d68);
1209         }
1210         if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
1211                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1212                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1213                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
1214                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1215                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
1216                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
1217                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
1218                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1219         }
1220         else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
1221                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1222                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1223                 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADJUST_TRIM) {
1224                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
1225                         tg3_writephy(tp, MII_TG3_TEST1,
1226                                      MII_TG3_TEST1_TRIM_EN | 0x4);
1227                 } else
1228                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
1229                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1230         }
1231         /* Set Extended packet length bit (bit 14) on all chips that */
1232         /* support jumbo frames */
1233         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1234                 /* Cannot do read-modify-write on 5401 */
1235                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
1236         } else if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
1237                 u32 phy_reg;
1238
1239                 /* Set bit 14 with read-modify-write to preserve other bits */
1240                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
1241                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
1242                         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
1243         }
1244
1245         /* Set phy register 0x10 bit 0 to high fifo elasticity to support
1246          * jumbo frames transmission.
1247          */
1248         if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
1249                 u32 phy_reg;
1250
1251                 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
1252                     tg3_writephy(tp, MII_TG3_EXT_CTRL,
1253                                  phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
1254         }
1255
1256         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1257                 /* adjust output voltage */
1258                 tg3_writephy(tp, MII_TG3_EPHY_PTEST, 0x12);
1259         }
1260
1261         tg3_phy_toggle_automdix(tp, 1);
1262         tg3_phy_set_wirespeed(tp);
1263         return 0;
1264 }
1265
1266 static void tg3_frob_aux_power(struct tg3 *tp)
1267 {
1268         struct tg3 *tp_peer = tp;
1269
1270         if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0)
1271                 return;
1272
1273         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
1274             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
1275                 struct net_device *dev_peer;
1276
1277                 dev_peer = pci_get_drvdata(tp->pdev_peer);
1278                 /* remove_one() may have been run on the peer. */
1279                 if (!dev_peer)
1280                         tp_peer = tp;
1281                 else
1282                         tp_peer = netdev_priv(dev_peer);
1283         }
1284
1285         if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
1286             (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
1287             (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
1288             (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
1289                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1290                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1291                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1292                                     (GRC_LCLCTRL_GPIO_OE0 |
1293                                      GRC_LCLCTRL_GPIO_OE1 |
1294                                      GRC_LCLCTRL_GPIO_OE2 |
1295                                      GRC_LCLCTRL_GPIO_OUTPUT0 |
1296                                      GRC_LCLCTRL_GPIO_OUTPUT1),
1297                                     100);
1298                 } else {
1299                         u32 no_gpio2;
1300                         u32 grc_local_ctrl = 0;
1301
1302                         if (tp_peer != tp &&
1303                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
1304                                 return;
1305
1306                         /* Workaround to prevent overdrawing Amps. */
1307                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
1308                             ASIC_REV_5714) {
1309                                 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
1310                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1311                                             grc_local_ctrl, 100);
1312                         }
1313
1314                         /* On 5753 and variants, GPIO2 cannot be used. */
1315                         no_gpio2 = tp->nic_sram_data_cfg &
1316                                     NIC_SRAM_DATA_CFG_NO_GPIO2;
1317
1318                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
1319                                          GRC_LCLCTRL_GPIO_OE1 |
1320                                          GRC_LCLCTRL_GPIO_OE2 |
1321                                          GRC_LCLCTRL_GPIO_OUTPUT1 |
1322                                          GRC_LCLCTRL_GPIO_OUTPUT2;
1323                         if (no_gpio2) {
1324                                 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
1325                                                     GRC_LCLCTRL_GPIO_OUTPUT2);
1326                         }
1327                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1328                                                     grc_local_ctrl, 100);
1329
1330                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
1331
1332                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1333                                                     grc_local_ctrl, 100);
1334
1335                         if (!no_gpio2) {
1336                                 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
1337                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1338                                             grc_local_ctrl, 100);
1339                         }
1340                 }
1341         } else {
1342                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
1343                     GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
1344                         if (tp_peer != tp &&
1345                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
1346                                 return;
1347
1348                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1349                                     (GRC_LCLCTRL_GPIO_OE1 |
1350                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1351
1352                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1353                                     GRC_LCLCTRL_GPIO_OE1, 100);
1354
1355                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1356                                     (GRC_LCLCTRL_GPIO_OE1 |
1357                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1358                 }
1359         }
1360 }
1361
1362 static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
1363 {
1364         if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
1365                 return 1;
1366         else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411) {
1367                 if (speed != SPEED_10)
1368                         return 1;
1369         } else if (speed == SPEED_10)
1370                 return 1;
1371
1372         return 0;
1373 }
1374
1375 static int tg3_setup_phy(struct tg3 *, int);
1376
1377 #define RESET_KIND_SHUTDOWN     0
1378 #define RESET_KIND_INIT         1
1379 #define RESET_KIND_SUSPEND      2
1380
1381 static void tg3_write_sig_post_reset(struct tg3 *, int);
1382 static int tg3_halt_cpu(struct tg3 *, u32);
1383 static int tg3_nvram_lock(struct tg3 *);
1384 static void tg3_nvram_unlock(struct tg3 *);
1385
1386 static void tg3_power_down_phy(struct tg3 *tp)
1387 {
1388         u32 val;
1389
1390         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
1391                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1392                         u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
1393                         u32 serdes_cfg = tr32(MAC_SERDES_CFG);
1394
1395                         sg_dig_ctrl |=
1396                                 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
1397                         tw32(SG_DIG_CTRL, sg_dig_ctrl);
1398                         tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
1399                 }
1400                 return;
1401         }
1402
1403         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1404                 tg3_bmcr_reset(tp);
1405                 val = tr32(GRC_MISC_CFG);
1406                 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
1407                 udelay(40);
1408                 return;
1409         } else {
1410                 tg3_writephy(tp, MII_TG3_EXT_CTRL,
1411                              MII_TG3_EXT_CTRL_FORCE_LED_OFF);
1412                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x01b2);
1413         }
1414
1415         /* The PHY should not be powered down on some chips because
1416          * of bugs.
1417          */
1418         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1419             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1420             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
1421              (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
1422                 return;
1423
1424         if (tp->tg3_flags3 & TG3_FLG3_5761_5784_AX_FIXES) {
1425                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
1426                 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
1427                 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
1428                 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
1429         }
1430
1431         tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
1432 }
1433
1434 static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
1435 {
1436         u32 misc_host_ctrl;
1437         u16 power_control, power_caps;
1438         int pm = tp->pm_cap;
1439
1440         /* Make sure register accesses (indirect or otherwise)
1441          * will function correctly.
1442          */
1443         pci_write_config_dword(tp->pdev,
1444                                TG3PCI_MISC_HOST_CTRL,
1445                                tp->misc_host_ctrl);
1446
1447         pci_read_config_word(tp->pdev,
1448                              pm + PCI_PM_CTRL,
1449                              &power_control);
1450         power_control |= PCI_PM_CTRL_PME_STATUS;
1451         power_control &= ~(PCI_PM_CTRL_STATE_MASK);
1452         switch (state) {
1453         case PCI_D0:
1454                 power_control |= 0;
1455                 pci_write_config_word(tp->pdev,
1456                                       pm + PCI_PM_CTRL,
1457                                       power_control);
1458                 udelay(100);    /* Delay after power state change */
1459
1460                 /* Switch out of Vaux if it is a NIC */
1461                 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
1462                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
1463
1464                 return 0;
1465
1466         case PCI_D1:
1467                 power_control |= 1;
1468                 break;
1469
1470         case PCI_D2:
1471                 power_control |= 2;
1472                 break;
1473
1474         case PCI_D3hot:
1475                 power_control |= 3;
1476                 break;
1477
1478         default:
1479                 printk(KERN_WARNING PFX "%s: Invalid power state (%d) "
1480                        "requested.\n",
1481                        tp->dev->name, state);
1482                 return -EINVAL;
1483         }
1484
1485         power_control |= PCI_PM_CTRL_PME_ENABLE;
1486
1487         misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
1488         tw32(TG3PCI_MISC_HOST_CTRL,
1489              misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
1490
1491         if (tp->link_config.phy_is_low_power == 0) {
1492                 tp->link_config.phy_is_low_power = 1;
1493                 tp->link_config.orig_speed = tp->link_config.speed;
1494                 tp->link_config.orig_duplex = tp->link_config.duplex;
1495                 tp->link_config.orig_autoneg = tp->link_config.autoneg;
1496         }
1497
1498         if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
1499                 tp->link_config.speed = SPEED_10;
1500                 tp->link_config.duplex = DUPLEX_HALF;
1501                 tp->link_config.autoneg = AUTONEG_ENABLE;
1502                 tg3_setup_phy(tp, 0);
1503         }
1504
1505         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1506                 u32 val;
1507
1508                 val = tr32(GRC_VCPU_EXT_CTRL);
1509                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
1510         } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
1511                 int i;
1512                 u32 val;
1513
1514                 for (i = 0; i < 200; i++) {
1515                         tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
1516                         if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
1517                                 break;
1518                         msleep(1);
1519                 }
1520         }
1521         if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
1522                 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
1523                                                      WOL_DRV_STATE_SHUTDOWN |
1524                                                      WOL_DRV_WOL |
1525                                                      WOL_SET_MAGIC_PKT);
1526
1527         pci_read_config_word(tp->pdev, pm + PCI_PM_PMC, &power_caps);
1528
1529         if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE) {
1530                 u32 mac_mode;
1531
1532                 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
1533                         tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
1534                         udelay(40);
1535
1536                         if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
1537                                 mac_mode = MAC_MODE_PORT_MODE_GMII;
1538                         else
1539                                 mac_mode = MAC_MODE_PORT_MODE_MII;
1540
1541                         mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
1542                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
1543                             ASIC_REV_5700) {
1544                                 u32 speed = (tp->tg3_flags &
1545                                              TG3_FLAG_WOL_SPEED_100MB) ?
1546                                              SPEED_100 : SPEED_10;
1547                                 if (tg3_5700_link_polarity(tp, speed))
1548                                         mac_mode |= MAC_MODE_LINK_POLARITY;
1549                                 else
1550                                         mac_mode &= ~MAC_MODE_LINK_POLARITY;
1551                         }
1552                 } else {
1553                         mac_mode = MAC_MODE_PORT_MODE_TBI;
1554                 }
1555
1556                 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
1557                         tw32(MAC_LED_CTRL, tp->led_ctrl);
1558
1559                 if (((power_caps & PCI_PM_CAP_PME_D3cold) &&
1560                      (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)))
1561                         mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
1562
1563                 tw32_f(MAC_MODE, mac_mode);
1564                 udelay(100);
1565
1566                 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
1567                 udelay(10);
1568         }
1569
1570         if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
1571             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1572              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
1573                 u32 base_val;
1574
1575                 base_val = tp->pci_clock_ctrl;
1576                 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
1577                              CLOCK_CTRL_TXCLK_DISABLE);
1578
1579                 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
1580                             CLOCK_CTRL_PWRDOWN_PLL133, 40);
1581         } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1582                    (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
1583                    (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
1584                 /* do nothing */
1585         } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
1586                      (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
1587                 u32 newbits1, newbits2;
1588
1589                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1590                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1591                         newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
1592                                     CLOCK_CTRL_TXCLK_DISABLE |
1593                                     CLOCK_CTRL_ALTCLK);
1594                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
1595                 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
1596                         newbits1 = CLOCK_CTRL_625_CORE;
1597                         newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
1598                 } else {
1599                         newbits1 = CLOCK_CTRL_ALTCLK;
1600                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
1601                 }
1602
1603                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
1604                             40);
1605
1606                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
1607                             40);
1608
1609                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
1610                         u32 newbits3;
1611
1612                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1613                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1614                                 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
1615                                             CLOCK_CTRL_TXCLK_DISABLE |
1616                                             CLOCK_CTRL_44MHZ_CORE);
1617                         } else {
1618                                 newbits3 = CLOCK_CTRL_44MHZ_CORE;
1619                         }
1620
1621                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
1622                                     tp->pci_clock_ctrl | newbits3, 40);
1623                 }
1624         }
1625
1626         if (!(tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
1627             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
1628             !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
1629                 tg3_power_down_phy(tp);
1630
1631         tg3_frob_aux_power(tp);
1632
1633         /* Workaround for unstable PLL clock */
1634         if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
1635             (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
1636                 u32 val = tr32(0x7d00);
1637
1638                 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
1639                 tw32(0x7d00, val);
1640                 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
1641                         int err;
1642
1643                         err = tg3_nvram_lock(tp);
1644                         tg3_halt_cpu(tp, RX_CPU_BASE);
1645                         if (!err)
1646                                 tg3_nvram_unlock(tp);
1647                 }
1648         }
1649
1650         tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
1651
1652         /* Finally, set the new power state. */
1653         pci_write_config_word(tp->pdev, pm + PCI_PM_CTRL, power_control);
1654         udelay(100);    /* Delay after power state change */
1655
1656         return 0;
1657 }
1658
1659 /* tp->lock is held. */
1660 static void tg3_wait_for_event_ack(struct tg3 *tp)
1661 {
1662         int i;
1663
1664         /* Wait for up to 2.5 milliseconds */
1665         for (i = 0; i < 250000; i++) {
1666                 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1667                         break;
1668                 udelay(10);
1669         }
1670 }
1671
1672 /* tp->lock is held. */
1673 static void tg3_ump_link_report(struct tg3 *tp)
1674 {
1675         u32 reg;
1676         u32 val;
1677
1678         if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1679             !(tp->tg3_flags  & TG3_FLAG_ENABLE_ASF))
1680                 return;
1681
1682         tg3_wait_for_event_ack(tp);
1683
1684         tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1685
1686         tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1687
1688         val = 0;
1689         if (!tg3_readphy(tp, MII_BMCR, &reg))
1690                 val = reg << 16;
1691         if (!tg3_readphy(tp, MII_BMSR, &reg))
1692                 val |= (reg & 0xffff);
1693         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
1694
1695         val = 0;
1696         if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
1697                 val = reg << 16;
1698         if (!tg3_readphy(tp, MII_LPA, &reg))
1699                 val |= (reg & 0xffff);
1700         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
1701
1702         val = 0;
1703         if (!(tp->tg3_flags2 & TG3_FLG2_MII_SERDES)) {
1704                 if (!tg3_readphy(tp, MII_CTRL1000, &reg))
1705                         val = reg << 16;
1706                 if (!tg3_readphy(tp, MII_STAT1000, &reg))
1707                         val |= (reg & 0xffff);
1708         }
1709         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
1710
1711         if (!tg3_readphy(tp, MII_PHYADDR, &reg))
1712                 val = reg << 16;
1713         else
1714                 val = 0;
1715         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
1716
1717         val = tr32(GRC_RX_CPU_EVENT);
1718         val |= GRC_RX_CPU_DRIVER_EVENT;
1719         tw32_f(GRC_RX_CPU_EVENT, val);
1720 }
1721
1722 static void tg3_link_report(struct tg3 *tp)
1723 {
1724         if (!netif_carrier_ok(tp->dev)) {
1725                 if (netif_msg_link(tp))
1726                         printk(KERN_INFO PFX "%s: Link is down.\n",
1727                                tp->dev->name);
1728                 tg3_ump_link_report(tp);
1729         } else if (netif_msg_link(tp)) {
1730                 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
1731                        tp->dev->name,
1732                        (tp->link_config.active_speed == SPEED_1000 ?
1733                         1000 :
1734                         (tp->link_config.active_speed == SPEED_100 ?
1735                          100 : 10)),
1736                        (tp->link_config.active_duplex == DUPLEX_FULL ?
1737                         "full" : "half"));
1738
1739                 printk(KERN_INFO PFX
1740                        "%s: Flow control is %s for TX and %s for RX.\n",
1741                        tp->dev->name,
1742                        (tp->link_config.active_flowctrl & TG3_FLOW_CTRL_TX) ?
1743                        "on" : "off",
1744                        (tp->link_config.active_flowctrl & TG3_FLOW_CTRL_RX) ?
1745                        "on" : "off");
1746                 tg3_ump_link_report(tp);
1747         }
1748 }
1749
1750 static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
1751 {
1752         u16 miireg;
1753
1754         if ((flow_ctrl & TG3_FLOW_CTRL_TX) && (flow_ctrl & TG3_FLOW_CTRL_RX))
1755                 miireg = ADVERTISE_PAUSE_CAP;
1756         else if (flow_ctrl & TG3_FLOW_CTRL_TX)
1757                 miireg = ADVERTISE_PAUSE_ASYM;
1758         else if (flow_ctrl & TG3_FLOW_CTRL_RX)
1759                 miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1760         else
1761                 miireg = 0;
1762
1763         return miireg;
1764 }
1765
1766 static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1767 {
1768         u16 miireg;
1769
1770         if ((flow_ctrl & TG3_FLOW_CTRL_TX) && (flow_ctrl & TG3_FLOW_CTRL_RX))
1771                 miireg = ADVERTISE_1000XPAUSE;
1772         else if (flow_ctrl & TG3_FLOW_CTRL_TX)
1773                 miireg = ADVERTISE_1000XPSE_ASYM;
1774         else if (flow_ctrl & TG3_FLOW_CTRL_RX)
1775                 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1776         else
1777                 miireg = 0;
1778
1779         return miireg;
1780 }
1781
1782 static u8 tg3_resolve_flowctrl_1000T(u16 lcladv, u16 rmtadv)
1783 {
1784         u8 cap = 0;
1785
1786         if (lcladv & ADVERTISE_PAUSE_CAP) {
1787                 if (lcladv & ADVERTISE_PAUSE_ASYM) {
1788                         if (rmtadv & LPA_PAUSE_CAP)
1789                                 cap = TG3_FLOW_CTRL_TX | TG3_FLOW_CTRL_RX;
1790                         else if (rmtadv & LPA_PAUSE_ASYM)
1791                                 cap = TG3_FLOW_CTRL_RX;
1792                 } else {
1793                         if (rmtadv & LPA_PAUSE_CAP)
1794                                 cap = TG3_FLOW_CTRL_TX | TG3_FLOW_CTRL_RX;
1795                 }
1796         } else if (lcladv & ADVERTISE_PAUSE_ASYM) {
1797                 if ((rmtadv & LPA_PAUSE_CAP) && (rmtadv & LPA_PAUSE_ASYM))
1798                         cap = TG3_FLOW_CTRL_TX;
1799         }
1800
1801         return cap;
1802 }
1803
1804 static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1805 {
1806         u8 cap = 0;
1807
1808         if (lcladv & ADVERTISE_1000XPAUSE) {
1809                 if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1810                         if (rmtadv & LPA_1000XPAUSE)
1811                                 cap = TG3_FLOW_CTRL_TX | TG3_FLOW_CTRL_RX;
1812                         else if (rmtadv & LPA_1000XPAUSE_ASYM)
1813                                 cap = TG3_FLOW_CTRL_RX;
1814                 } else {
1815                         if (rmtadv & LPA_1000XPAUSE)
1816                                 cap = TG3_FLOW_CTRL_TX | TG3_FLOW_CTRL_RX;
1817                 }
1818         } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1819                 if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
1820                         cap = TG3_FLOW_CTRL_TX;
1821         }
1822
1823         return cap;
1824 }
1825
1826 static void tg3_setup_flow_control(struct tg3 *tp, u32 local_adv, u32 remote_adv)
1827 {
1828         u8 new_tg3_flags = 0;
1829         u32 old_rx_mode = tp->rx_mode;
1830         u32 old_tx_mode = tp->tx_mode;
1831
1832         if (tp->link_config.autoneg == AUTONEG_ENABLE &&
1833             (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) {
1834                 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
1835                         new_tg3_flags = tg3_resolve_flowctrl_1000X(local_adv,
1836                                                                    remote_adv);
1837                 else
1838                         new_tg3_flags = tg3_resolve_flowctrl_1000T(local_adv,
1839                                                                    remote_adv);
1840         } else {
1841                 new_tg3_flags = tp->link_config.flowctrl;
1842         }
1843
1844         tp->link_config.active_flowctrl = new_tg3_flags;
1845
1846         if (new_tg3_flags & TG3_FLOW_CTRL_RX)
1847                 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1848         else
1849                 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1850
1851         if (old_rx_mode != tp->rx_mode) {
1852                 tw32_f(MAC_RX_MODE, tp->rx_mode);
1853         }
1854
1855         if (new_tg3_flags & TG3_FLOW_CTRL_TX)
1856                 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1857         else
1858                 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1859
1860         if (old_tx_mode != tp->tx_mode) {
1861                 tw32_f(MAC_TX_MODE, tp->tx_mode);
1862         }
1863 }
1864
1865 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
1866 {
1867         switch (val & MII_TG3_AUX_STAT_SPDMASK) {
1868         case MII_TG3_AUX_STAT_10HALF:
1869                 *speed = SPEED_10;
1870                 *duplex = DUPLEX_HALF;
1871                 break;
1872
1873         case MII_TG3_AUX_STAT_10FULL:
1874                 *speed = SPEED_10;
1875                 *duplex = DUPLEX_FULL;
1876                 break;
1877
1878         case MII_TG3_AUX_STAT_100HALF:
1879                 *speed = SPEED_100;
1880                 *duplex = DUPLEX_HALF;
1881                 break;
1882
1883         case MII_TG3_AUX_STAT_100FULL:
1884                 *speed = SPEED_100;
1885                 *duplex = DUPLEX_FULL;
1886                 break;
1887
1888         case MII_TG3_AUX_STAT_1000HALF:
1889                 *speed = SPEED_1000;
1890                 *duplex = DUPLEX_HALF;
1891                 break;
1892
1893         case MII_TG3_AUX_STAT_1000FULL:
1894                 *speed = SPEED_1000;
1895                 *duplex = DUPLEX_FULL;
1896                 break;
1897
1898         default:
1899                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1900                         *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
1901                                  SPEED_10;
1902                         *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
1903                                   DUPLEX_HALF;
1904                         break;
1905                 }
1906                 *speed = SPEED_INVALID;
1907                 *duplex = DUPLEX_INVALID;
1908                 break;
1909         }
1910 }
1911
1912 static void tg3_phy_copper_begin(struct tg3 *tp)
1913 {
1914         u32 new_adv;
1915         int i;
1916
1917         if (tp->link_config.phy_is_low_power) {
1918                 /* Entering low power mode.  Disable gigabit and
1919                  * 100baseT advertisements.
1920                  */
1921                 tg3_writephy(tp, MII_TG3_CTRL, 0);
1922
1923                 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
1924                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
1925                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
1926                         new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
1927
1928                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1929         } else if (tp->link_config.speed == SPEED_INVALID) {
1930                 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
1931                         tp->link_config.advertising &=
1932                                 ~(ADVERTISED_1000baseT_Half |
1933                                   ADVERTISED_1000baseT_Full);
1934
1935                 new_adv = ADVERTISE_CSMA;
1936                 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
1937                         new_adv |= ADVERTISE_10HALF;
1938                 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
1939                         new_adv |= ADVERTISE_10FULL;
1940                 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
1941                         new_adv |= ADVERTISE_100HALF;
1942                 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
1943                         new_adv |= ADVERTISE_100FULL;
1944
1945                 new_adv |= tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
1946
1947                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1948
1949                 if (tp->link_config.advertising &
1950                     (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
1951                         new_adv = 0;
1952                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
1953                                 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
1954                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
1955                                 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
1956                         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
1957                             (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1958                              tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
1959                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
1960                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
1961                         tg3_writephy(tp, MII_TG3_CTRL, new_adv);
1962                 } else {
1963                         tg3_writephy(tp, MII_TG3_CTRL, 0);
1964                 }
1965         } else {
1966                 new_adv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
1967                 new_adv |= ADVERTISE_CSMA;
1968
1969                 /* Asking for a specific link mode. */
1970                 if (tp->link_config.speed == SPEED_1000) {
1971                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
1972
1973                         if (tp->link_config.duplex == DUPLEX_FULL)
1974                                 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
1975                         else
1976                                 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
1977                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1978                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
1979                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
1980                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
1981                 } else {
1982                         if (tp->link_config.speed == SPEED_100) {
1983                                 if (tp->link_config.duplex == DUPLEX_FULL)
1984                                         new_adv |= ADVERTISE_100FULL;
1985                                 else
1986                                         new_adv |= ADVERTISE_100HALF;
1987                         } else {
1988                                 if (tp->link_config.duplex == DUPLEX_FULL)
1989                                         new_adv |= ADVERTISE_10FULL;
1990                                 else
1991                                         new_adv |= ADVERTISE_10HALF;
1992                         }
1993                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
1994
1995                         new_adv = 0;
1996                 }
1997
1998                 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
1999         }
2000
2001         if (tp->link_config.autoneg == AUTONEG_DISABLE &&
2002             tp->link_config.speed != SPEED_INVALID) {
2003                 u32 bmcr, orig_bmcr;
2004
2005                 tp->link_config.active_speed = tp->link_config.speed;
2006                 tp->link_config.active_duplex = tp->link_config.duplex;
2007
2008                 bmcr = 0;
2009                 switch (tp->link_config.speed) {
2010                 default:
2011                 case SPEED_10:
2012                         break;
2013
2014                 case SPEED_100:
2015                         bmcr |= BMCR_SPEED100;
2016                         break;
2017
2018                 case SPEED_1000:
2019                         bmcr |= TG3_BMCR_SPEED1000;
2020                         break;
2021                 }
2022
2023                 if (tp->link_config.duplex == DUPLEX_FULL)
2024                         bmcr |= BMCR_FULLDPLX;
2025
2026                 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
2027                     (bmcr != orig_bmcr)) {
2028                         tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
2029                         for (i = 0; i < 1500; i++) {
2030                                 u32 tmp;
2031
2032                                 udelay(10);
2033                                 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
2034                                     tg3_readphy(tp, MII_BMSR, &tmp))
2035                                         continue;
2036                                 if (!(tmp & BMSR_LSTATUS)) {
2037                                         udelay(40);
2038                                         break;
2039                                 }
2040                         }
2041                         tg3_writephy(tp, MII_BMCR, bmcr);
2042                         udelay(40);
2043                 }
2044         } else {
2045                 tg3_writephy(tp, MII_BMCR,
2046                              BMCR_ANENABLE | BMCR_ANRESTART);
2047         }
2048 }
2049
2050 static int tg3_init_5401phy_dsp(struct tg3 *tp)
2051 {
2052         int err;
2053
2054         /* Turn off tap power management. */
2055         /* Set Extended packet length bit */
2056         err  = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2057
2058         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
2059         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
2060
2061         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
2062         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
2063
2064         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2065         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
2066
2067         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2068         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
2069
2070         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
2071         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
2072
2073         udelay(40);
2074
2075         return err;
2076 }
2077
2078 static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
2079 {
2080         u32 adv_reg, all_mask = 0;
2081
2082         if (mask & ADVERTISED_10baseT_Half)
2083                 all_mask |= ADVERTISE_10HALF;
2084         if (mask & ADVERTISED_10baseT_Full)
2085                 all_mask |= ADVERTISE_10FULL;
2086         if (mask & ADVERTISED_100baseT_Half)
2087                 all_mask |= ADVERTISE_100HALF;
2088         if (mask & ADVERTISED_100baseT_Full)
2089                 all_mask |= ADVERTISE_100FULL;
2090
2091         if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
2092                 return 0;
2093
2094         if ((adv_reg & all_mask) != all_mask)
2095                 return 0;
2096         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
2097                 u32 tg3_ctrl;
2098
2099                 all_mask = 0;
2100                 if (mask & ADVERTISED_1000baseT_Half)
2101                         all_mask |= ADVERTISE_1000HALF;
2102                 if (mask & ADVERTISED_1000baseT_Full)
2103                         all_mask |= ADVERTISE_1000FULL;
2104
2105                 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
2106                         return 0;
2107
2108                 if ((tg3_ctrl & all_mask) != all_mask)
2109                         return 0;
2110         }
2111         return 1;
2112 }
2113
2114 static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
2115 {
2116         u32 curadv, reqadv;
2117
2118         if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
2119                 return 1;
2120
2121         curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2122         reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2123
2124         if (tp->link_config.active_duplex == DUPLEX_FULL) {
2125                 if (curadv != reqadv)
2126                         return 0;
2127
2128                 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)
2129                         tg3_readphy(tp, MII_LPA, rmtadv);
2130         } else {
2131                 /* Reprogram the advertisement register, even if it
2132                  * does not affect the current link.  If the link
2133                  * gets renegotiated in the future, we can save an
2134                  * additional renegotiation cycle by advertising
2135                  * it correctly in the first place.
2136                  */
2137                 if (curadv != reqadv) {
2138                         *lcladv &= ~(ADVERTISE_PAUSE_CAP |
2139                                      ADVERTISE_PAUSE_ASYM);
2140                         tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
2141                 }
2142         }
2143
2144         return 1;
2145 }
2146
2147 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
2148 {
2149         int current_link_up;
2150         u32 bmsr, dummy;
2151         u32 lcl_adv, rmt_adv;
2152         u16 current_speed;
2153         u8 current_duplex;
2154         int i, err;
2155
2156         tw32(MAC_EVENT, 0);
2157
2158         tw32_f(MAC_STATUS,
2159              (MAC_STATUS_SYNC_CHANGED |
2160               MAC_STATUS_CFG_CHANGED |
2161               MAC_STATUS_MI_COMPLETION |
2162               MAC_STATUS_LNKSTATE_CHANGED));
2163         udelay(40);
2164
2165         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
2166                 tw32_f(MAC_MI_MODE,
2167                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
2168                 udelay(80);
2169         }
2170
2171         tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
2172
2173         /* Some third-party PHYs need to be reset on link going
2174          * down.
2175          */
2176         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2177              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2178              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
2179             netif_carrier_ok(tp->dev)) {
2180                 tg3_readphy(tp, MII_BMSR, &bmsr);
2181                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
2182                     !(bmsr & BMSR_LSTATUS))
2183                         force_reset = 1;
2184         }
2185         if (force_reset)
2186                 tg3_phy_reset(tp);
2187
2188         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
2189                 tg3_readphy(tp, MII_BMSR, &bmsr);
2190                 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
2191                     !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
2192                         bmsr = 0;
2193
2194                 if (!(bmsr & BMSR_LSTATUS)) {
2195                         err = tg3_init_5401phy_dsp(tp);
2196                         if (err)
2197                                 return err;
2198
2199                         tg3_readphy(tp, MII_BMSR, &bmsr);
2200                         for (i = 0; i < 1000; i++) {
2201                                 udelay(10);
2202                                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
2203                                     (bmsr & BMSR_LSTATUS)) {
2204                                         udelay(40);
2205                                         break;
2206                                 }
2207                         }
2208
2209                         if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 &&
2210                             !(bmsr & BMSR_LSTATUS) &&
2211                             tp->link_config.active_speed == SPEED_1000) {
2212                                 err = tg3_phy_reset(tp);
2213                                 if (!err)
2214                                         err = tg3_init_5401phy_dsp(tp);
2215                                 if (err)
2216                                         return err;
2217                         }
2218                 }
2219         } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2220                    tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
2221                 /* 5701 {A0,B0} CRC bug workaround */
2222                 tg3_writephy(tp, 0x15, 0x0a75);
2223                 tg3_writephy(tp, 0x1c, 0x8c68);
2224                 tg3_writephy(tp, 0x1c, 0x8d68);
2225                 tg3_writephy(tp, 0x1c, 0x8c68);
2226         }
2227
2228         /* Clear pending interrupts... */
2229         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
2230         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
2231
2232         if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
2233                 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
2234         else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)
2235                 tg3_writephy(tp, MII_TG3_IMASK, ~0);
2236
2237         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2238             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2239                 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
2240                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
2241                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
2242                 else
2243                         tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
2244         }
2245
2246         current_link_up = 0;
2247         current_speed = SPEED_INVALID;
2248         current_duplex = DUPLEX_INVALID;
2249
2250         if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
2251                 u32 val;
2252
2253                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
2254                 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
2255                 if (!(val & (1 << 10))) {
2256                         val |= (1 << 10);
2257                         tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
2258                         goto relink;
2259                 }
2260         }
2261
2262         bmsr = 0;
2263         for (i = 0; i < 100; i++) {
2264                 tg3_readphy(tp, MII_BMSR, &bmsr);
2265                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
2266                     (bmsr & BMSR_LSTATUS))
2267                         break;
2268                 udelay(40);
2269         }
2270
2271         if (bmsr & BMSR_LSTATUS) {
2272                 u32 aux_stat, bmcr;
2273
2274                 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
2275                 for (i = 0; i < 2000; i++) {
2276                         udelay(10);
2277                         if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
2278                             aux_stat)
2279                                 break;
2280                 }
2281
2282                 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
2283                                              &current_speed,
2284                                              &current_duplex);
2285
2286                 bmcr = 0;
2287                 for (i = 0; i < 200; i++) {
2288                         tg3_readphy(tp, MII_BMCR, &bmcr);
2289                         if (tg3_readphy(tp, MII_BMCR, &bmcr))
2290                                 continue;
2291                         if (bmcr && bmcr != 0x7fff)
2292                                 break;
2293                         udelay(10);
2294                 }
2295
2296                 lcl_adv = 0;
2297                 rmt_adv = 0;
2298
2299                 tp->link_config.active_speed = current_speed;
2300                 tp->link_config.active_duplex = current_duplex;
2301
2302                 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2303                         if ((bmcr & BMCR_ANENABLE) &&
2304                             tg3_copper_is_advertising_all(tp,
2305                                                 tp->link_config.advertising)) {
2306                                 if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv,
2307                                                                   &rmt_adv))
2308                                         current_link_up = 1;
2309                         }
2310                 } else {
2311                         if (!(bmcr & BMCR_ANENABLE) &&
2312                             tp->link_config.speed == current_speed &&
2313                             tp->link_config.duplex == current_duplex &&
2314                             tp->link_config.flowctrl ==
2315                             tp->link_config.active_flowctrl) {
2316                                 current_link_up = 1;
2317                         }
2318                 }
2319
2320                 if (current_link_up == 1 &&
2321                     tp->link_config.active_duplex == DUPLEX_FULL)
2322                         tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
2323         }
2324
2325 relink:
2326         if (current_link_up == 0 || tp->link_config.phy_is_low_power) {
2327                 u32 tmp;
2328
2329                 tg3_phy_copper_begin(tp);
2330
2331                 tg3_readphy(tp, MII_BMSR, &tmp);
2332                 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
2333                     (tmp & BMSR_LSTATUS))
2334                         current_link_up = 1;
2335         }
2336
2337         tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
2338         if (current_link_up == 1) {
2339                 if (tp->link_config.active_speed == SPEED_100 ||
2340                     tp->link_config.active_speed == SPEED_10)
2341                         tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
2342                 else
2343                         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
2344         } else
2345                 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
2346
2347         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
2348         if (tp->link_config.active_duplex == DUPLEX_HALF)
2349                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
2350
2351         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
2352                 if (current_link_up == 1 &&
2353                     tg3_5700_link_polarity(tp, tp->link_config.active_speed))
2354                         tp->mac_mode |= MAC_MODE_LINK_POLARITY;
2355                 else
2356                         tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
2357         }
2358
2359         /* ??? Without this setting Netgear GA302T PHY does not
2360          * ??? send/receive packets...
2361          */
2362         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 &&
2363             tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
2364                 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
2365                 tw32_f(MAC_MI_MODE, tp->mi_mode);
2366                 udelay(80);
2367         }
2368
2369         tw32_f(MAC_MODE, tp->mac_mode);
2370         udelay(40);
2371
2372         if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
2373                 /* Polled via timer. */
2374                 tw32_f(MAC_EVENT, 0);
2375         } else {
2376                 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2377         }
2378         udelay(40);
2379
2380         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
2381             current_link_up == 1 &&
2382             tp->link_config.active_speed == SPEED_1000 &&
2383             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
2384              (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
2385                 udelay(120);
2386                 tw32_f(MAC_STATUS,
2387                      (MAC_STATUS_SYNC_CHANGED |
2388                       MAC_STATUS_CFG_CHANGED));
2389                 udelay(40);
2390                 tg3_write_mem(tp,
2391                               NIC_SRAM_FIRMWARE_MBOX,
2392                               NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
2393         }
2394
2395         if (current_link_up != netif_carrier_ok(tp->dev)) {
2396                 if (current_link_up)
2397                         netif_carrier_on(tp->dev);
2398                 else
2399                         netif_carrier_off(tp->dev);
2400                 tg3_link_report(tp);
2401         }
2402
2403         return 0;
2404 }
2405
2406 struct tg3_fiber_aneginfo {
2407         int state;
2408 #define ANEG_STATE_UNKNOWN              0
2409 #define ANEG_STATE_AN_ENABLE            1
2410 #define ANEG_STATE_RESTART_INIT         2
2411 #define ANEG_STATE_RESTART              3
2412 #define ANEG_STATE_DISABLE_LINK_OK      4
2413 #define ANEG_STATE_ABILITY_DETECT_INIT  5
2414 #define ANEG_STATE_ABILITY_DETECT       6
2415 #define ANEG_STATE_ACK_DETECT_INIT      7
2416 #define ANEG_STATE_ACK_DETECT           8
2417 #define ANEG_STATE_COMPLETE_ACK_INIT    9
2418 #define ANEG_STATE_COMPLETE_ACK         10
2419 #define ANEG_STATE_IDLE_DETECT_INIT     11
2420 #define ANEG_STATE_IDLE_DETECT          12
2421 #define ANEG_STATE_LINK_OK              13
2422 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT  14
2423 #define ANEG_STATE_NEXT_PAGE_WAIT       15
2424
2425         u32 flags;
2426 #define MR_AN_ENABLE            0x00000001
2427 #define MR_RESTART_AN           0x00000002
2428 #define MR_AN_COMPLETE          0x00000004
2429 #define MR_PAGE_RX              0x00000008
2430 #define MR_NP_LOADED            0x00000010
2431 #define MR_TOGGLE_TX            0x00000020
2432 #define MR_LP_ADV_FULL_DUPLEX   0x00000040
2433 #define MR_LP_ADV_HALF_DUPLEX   0x00000080
2434 #define MR_LP_ADV_SYM_PAUSE     0x00000100
2435 #define MR_LP_ADV_ASYM_PAUSE    0x00000200
2436 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
2437 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
2438 #define MR_LP_ADV_NEXT_PAGE     0x00001000
2439 #define MR_TOGGLE_RX            0x00002000
2440 #define MR_NP_RX                0x00004000
2441
2442 #define MR_LINK_OK              0x80000000
2443
2444         unsigned long link_time, cur_time;
2445
2446         u32 ability_match_cfg;
2447         int ability_match_count;
2448
2449         char ability_match, idle_match, ack_match;
2450
2451         u32 txconfig, rxconfig;
2452 #define ANEG_CFG_NP             0x00000080
2453 #define ANEG_CFG_ACK            0x00000040
2454 #define ANEG_CFG_RF2            0x00000020
2455 #define ANEG_CFG_RF1            0x00000010
2456 #define ANEG_CFG_PS2            0x00000001
2457 #define ANEG_CFG_PS1            0x00008000
2458 #define ANEG_CFG_HD             0x00004000
2459 #define ANEG_CFG_FD             0x00002000
2460 #define ANEG_CFG_INVAL          0x00001f06
2461
2462 };
2463 #define ANEG_OK         0
2464 #define ANEG_DONE       1
2465 #define ANEG_TIMER_ENAB 2
2466 #define ANEG_FAILED     -1
2467
2468 #define ANEG_STATE_SETTLE_TIME  10000
2469
2470 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
2471                                    struct tg3_fiber_aneginfo *ap)
2472 {
2473         u16 flowctrl;
2474         unsigned long delta;
2475         u32 rx_cfg_reg;
2476         int ret;
2477
2478         if (ap->state == ANEG_STATE_UNKNOWN) {
2479                 ap->rxconfig = 0;
2480                 ap->link_time = 0;
2481                 ap->cur_time = 0;
2482                 ap->ability_match_cfg = 0;
2483                 ap->ability_match_count = 0;
2484                 ap->ability_match = 0;
2485                 ap->idle_match = 0;
2486                 ap->ack_match = 0;
2487         }
2488         ap->cur_time++;
2489
2490         if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
2491                 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
2492
2493                 if (rx_cfg_reg != ap->ability_match_cfg) {
2494                         ap->ability_match_cfg = rx_cfg_reg;
2495                         ap->ability_match = 0;
2496                         ap->ability_match_count = 0;
2497                 } else {
2498                         if (++ap->ability_match_count > 1) {
2499                                 ap->ability_match = 1;
2500                                 ap->ability_match_cfg = rx_cfg_reg;
2501                         }
2502                 }
2503                 if (rx_cfg_reg & ANEG_CFG_ACK)
2504                         ap->ack_match = 1;
2505                 else
2506                         ap->ack_match = 0;
2507
2508                 ap->idle_match = 0;
2509         } else {
2510                 ap->idle_match = 1;
2511                 ap->ability_match_cfg = 0;
2512                 ap->ability_match_count = 0;
2513                 ap->ability_match = 0;
2514                 ap->ack_match = 0;
2515
2516                 rx_cfg_reg = 0;
2517         }
2518
2519         ap->rxconfig = rx_cfg_reg;
2520         ret = ANEG_OK;
2521
2522         switch(ap->state) {
2523         case ANEG_STATE_UNKNOWN:
2524                 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
2525                         ap->state = ANEG_STATE_AN_ENABLE;
2526
2527                 /* fallthru */
2528         case ANEG_STATE_AN_ENABLE:
2529                 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
2530                 if (ap->flags & MR_AN_ENABLE) {
2531                         ap->link_time = 0;
2532                         ap->cur_time = 0;
2533                         ap->ability_match_cfg = 0;
2534                         ap->ability_match_count = 0;
2535                         ap->ability_match = 0;
2536                         ap->idle_match = 0;
2537                         ap->ack_match = 0;
2538
2539                         ap->state = ANEG_STATE_RESTART_INIT;
2540                 } else {
2541                         ap->state = ANEG_STATE_DISABLE_LINK_OK;
2542                 }
2543                 break;
2544
2545         case ANEG_STATE_RESTART_INIT:
2546                 ap->link_time = ap->cur_time;
2547                 ap->flags &= ~(MR_NP_LOADED);
2548                 ap->txconfig = 0;
2549                 tw32(MAC_TX_AUTO_NEG, 0);
2550                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2551                 tw32_f(MAC_MODE, tp->mac_mode);
2552                 udelay(40);
2553
2554                 ret = ANEG_TIMER_ENAB;
2555                 ap->state = ANEG_STATE_RESTART;
2556
2557                 /* fallthru */
2558         case ANEG_STATE_RESTART:
2559                 delta = ap->cur_time - ap->link_time;
2560                 if (delta > ANEG_STATE_SETTLE_TIME) {
2561                         ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
2562                 } else {
2563                         ret = ANEG_TIMER_ENAB;
2564                 }
2565                 break;
2566
2567         case ANEG_STATE_DISABLE_LINK_OK:
2568                 ret = ANEG_DONE;
2569                 break;
2570
2571         case ANEG_STATE_ABILITY_DETECT_INIT:
2572                 ap->flags &= ~(MR_TOGGLE_TX);
2573                 ap->txconfig = ANEG_CFG_FD;
2574                 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
2575                 if (flowctrl & ADVERTISE_1000XPAUSE)
2576                         ap->txconfig |= ANEG_CFG_PS1;
2577                 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
2578                         ap->txconfig |= ANEG_CFG_PS2;
2579                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
2580                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2581                 tw32_f(MAC_MODE, tp->mac_mode);
2582                 udelay(40);
2583
2584                 ap->state = ANEG_STATE_ABILITY_DETECT;
2585                 break;
2586
2587         case ANEG_STATE_ABILITY_DETECT:
2588                 if (ap->ability_match != 0 && ap->rxconfig != 0) {
2589                         ap->state = ANEG_STATE_ACK_DETECT_INIT;
2590                 }
2591                 break;
2592
2593         case ANEG_STATE_ACK_DETECT_INIT:
2594                 ap->txconfig |= ANEG_CFG_ACK;
2595                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
2596                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2597                 tw32_f(MAC_MODE, tp->mac_mode);
2598                 udelay(40);
2599
2600                 ap->state = ANEG_STATE_ACK_DETECT;
2601
2602                 /* fallthru */
2603         case ANEG_STATE_ACK_DETECT:
2604                 if (ap->ack_match != 0) {
2605                         if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
2606                             (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
2607                                 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
2608                         } else {
2609                                 ap->state = ANEG_STATE_AN_ENABLE;
2610                         }
2611                 } else if (ap->ability_match != 0 &&
2612                            ap->rxconfig == 0) {
2613                         ap->state = ANEG_STATE_AN_ENABLE;
2614                 }
2615                 break;
2616
2617         case ANEG_STATE_COMPLETE_ACK_INIT:
2618                 if (ap->rxconfig & ANEG_CFG_INVAL) {
2619                         ret = ANEG_FAILED;
2620                         break;
2621                 }
2622                 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
2623                                MR_LP_ADV_HALF_DUPLEX |
2624                                MR_LP_ADV_SYM_PAUSE |
2625                                MR_LP_ADV_ASYM_PAUSE |
2626                                MR_LP_ADV_REMOTE_FAULT1 |
2627                                MR_LP_ADV_REMOTE_FAULT2 |
2628                                MR_LP_ADV_NEXT_PAGE |
2629                                MR_TOGGLE_RX |
2630                                MR_NP_RX);
2631                 if (ap->rxconfig & ANEG_CFG_FD)
2632                         ap->flags |= MR_LP_ADV_FULL_DUPLEX;
2633                 if (ap->rxconfig & ANEG_CFG_HD)
2634                         ap->flags |= MR_LP_ADV_HALF_DUPLEX;
2635                 if (ap->rxconfig & ANEG_CFG_PS1)
2636                         ap->flags |= MR_LP_ADV_SYM_PAUSE;
2637                 if (ap->rxconfig & ANEG_CFG_PS2)
2638                         ap->flags |= MR_LP_ADV_ASYM_PAUSE;
2639                 if (ap->rxconfig & ANEG_CFG_RF1)
2640                         ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
2641                 if (ap->rxconfig & ANEG_CFG_RF2)
2642                         ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
2643                 if (ap->rxconfig & ANEG_CFG_NP)
2644                         ap->flags |= MR_LP_ADV_NEXT_PAGE;
2645
2646                 ap->link_time = ap->cur_time;
2647
2648                 ap->flags ^= (MR_TOGGLE_TX);
2649                 if (ap->rxconfig & 0x0008)
2650                         ap->flags |= MR_TOGGLE_RX;
2651                 if (ap->rxconfig & ANEG_CFG_NP)
2652                         ap->flags |= MR_NP_RX;
2653                 ap->flags |= MR_PAGE_RX;
2654
2655                 ap->state = ANEG_STATE_COMPLETE_ACK;
2656                 ret = ANEG_TIMER_ENAB;
2657                 break;
2658
2659         case ANEG_STATE_COMPLETE_ACK:
2660                 if (ap->ability_match != 0 &&
2661                     ap->rxconfig == 0) {
2662                         ap->state = ANEG_STATE_AN_ENABLE;
2663                         break;
2664                 }
2665                 delta = ap->cur_time - ap->link_time;
2666                 if (delta > ANEG_STATE_SETTLE_TIME) {
2667                         if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
2668                                 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
2669                         } else {
2670                                 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
2671                                     !(ap->flags & MR_NP_RX)) {
2672                                         ap->state = ANEG_STATE_IDLE_DETECT_INIT;
2673                                 } else {
2674                                         ret = ANEG_FAILED;
2675                                 }
2676                         }
2677                 }
2678                 break;
2679
2680         case ANEG_STATE_IDLE_DETECT_INIT:
2681                 ap->link_time = ap->cur_time;
2682                 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
2683                 tw32_f(MAC_MODE, tp->mac_mode);
2684                 udelay(40);
2685
2686                 ap->state = ANEG_STATE_IDLE_DETECT;
2687                 ret = ANEG_TIMER_ENAB;
2688                 break;
2689
2690         case ANEG_STATE_IDLE_DETECT:
2691                 if (ap->ability_match != 0 &&
2692                     ap->rxconfig == 0) {
2693                         ap->state = ANEG_STATE_AN_ENABLE;
2694                         break;
2695                 }
2696                 delta = ap->cur_time - ap->link_time;
2697                 if (delta > ANEG_STATE_SETTLE_TIME) {
2698                         /* XXX another gem from the Broadcom driver :( */
2699                         ap->state = ANEG_STATE_LINK_OK;
2700                 }
2701                 break;
2702
2703         case ANEG_STATE_LINK_OK:
2704                 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
2705                 ret = ANEG_DONE;
2706                 break;
2707
2708         case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
2709                 /* ??? unimplemented */
2710                 break;
2711
2712         case ANEG_STATE_NEXT_PAGE_WAIT:
2713                 /* ??? unimplemented */
2714                 break;
2715
2716         default:
2717                 ret = ANEG_FAILED;
2718                 break;
2719         }
2720
2721         return ret;
2722 }
2723
2724 static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
2725 {
2726         int res = 0;
2727         struct tg3_fiber_aneginfo aninfo;
2728         int status = ANEG_FAILED;
2729         unsigned int tick;
2730         u32 tmp;
2731
2732         tw32_f(MAC_TX_AUTO_NEG, 0);
2733
2734         tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
2735         tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
2736         udelay(40);
2737
2738         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
2739         udelay(40);
2740
2741         memset(&aninfo, 0, sizeof(aninfo));
2742         aninfo.flags |= MR_AN_ENABLE;
2743         aninfo.state = ANEG_STATE_UNKNOWN;
2744         aninfo.cur_time = 0;
2745         tick = 0;
2746         while (++tick < 195000) {
2747                 status = tg3_fiber_aneg_smachine(tp, &aninfo);
2748                 if (status == ANEG_DONE || status == ANEG_FAILED)
2749                         break;
2750
2751                 udelay(1);
2752         }
2753
2754         tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
2755         tw32_f(MAC_MODE, tp->mac_mode);
2756         udelay(40);
2757
2758         *txflags = aninfo.txconfig;
2759         *rxflags = aninfo.flags;
2760
2761         if (status == ANEG_DONE &&
2762             (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
2763                              MR_LP_ADV_FULL_DUPLEX)))
2764                 res = 1;
2765
2766         return res;
2767 }
2768
2769 static void tg3_init_bcm8002(struct tg3 *tp)
2770 {
2771         u32 mac_status = tr32(MAC_STATUS);
2772         int i;
2773
2774         /* Reset when initting first time or we have a link. */
2775         if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
2776             !(mac_status & MAC_STATUS_PCS_SYNCED))
2777                 return;
2778
2779         /* Set PLL lock range. */
2780         tg3_writephy(tp, 0x16, 0x8007);
2781
2782         /* SW reset */
2783         tg3_writephy(tp, MII_BMCR, BMCR_RESET);
2784
2785         /* Wait for reset to complete. */
2786         /* XXX schedule_timeout() ... */
2787         for (i = 0; i < 500; i++)
2788                 udelay(10);
2789
2790         /* Config mode; select PMA/Ch 1 regs. */
2791         tg3_writephy(tp, 0x10, 0x8411);
2792
2793         /* Enable auto-lock and comdet, select txclk for tx. */
2794         tg3_writephy(tp, 0x11, 0x0a10);
2795
2796         tg3_writephy(tp, 0x18, 0x00a0);
2797         tg3_writephy(tp, 0x16, 0x41ff);
2798
2799         /* Assert and deassert POR. */
2800         tg3_writephy(tp, 0x13, 0x0400);
2801         udelay(40);
2802         tg3_writephy(tp, 0x13, 0x0000);
2803
2804         tg3_writephy(tp, 0x11, 0x0a50);
2805         udelay(40);
2806         tg3_writephy(tp, 0x11, 0x0a10);
2807
2808         /* Wait for signal to stabilize */
2809         /* XXX schedule_timeout() ... */
2810         for (i = 0; i < 15000; i++)
2811                 udelay(10);
2812
2813         /* Deselect the channel register so we can read the PHYID
2814          * later.
2815          */
2816         tg3_writephy(tp, 0x10, 0x8011);
2817 }
2818
2819 static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
2820 {
2821         u16 flowctrl;
2822         u32 sg_dig_ctrl, sg_dig_status;
2823         u32 serdes_cfg, expected_sg_dig_ctrl;
2824         int workaround, port_a;
2825         int current_link_up;
2826
2827         serdes_cfg = 0;
2828         expected_sg_dig_ctrl = 0;
2829         workaround = 0;
2830         port_a = 1;
2831         current_link_up = 0;
2832
2833         if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
2834             tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
2835                 workaround = 1;
2836                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
2837                         port_a = 0;
2838
2839                 /* preserve bits 0-11,13,14 for signal pre-emphasis */
2840                 /* preserve bits 20-23 for voltage regulator */
2841                 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
2842         }
2843
2844         sg_dig_ctrl = tr32(SG_DIG_CTRL);
2845
2846         if (tp->link_config.autoneg != AUTONEG_ENABLE) {
2847                 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
2848                         if (workaround) {
2849                                 u32 val = serdes_cfg;
2850
2851                                 if (port_a)
2852                                         val |= 0xc010000;
2853                                 else
2854                                         val |= 0x4010000;
2855                                 tw32_f(MAC_SERDES_CFG, val);
2856                         }
2857
2858                         tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
2859                 }
2860                 if (mac_status & MAC_STATUS_PCS_SYNCED) {
2861                         tg3_setup_flow_control(tp, 0, 0);
2862                         current_link_up = 1;
2863                 }
2864                 goto out;
2865         }
2866
2867         /* Want auto-negotiation.  */
2868         expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
2869
2870         flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
2871         if (flowctrl & ADVERTISE_1000XPAUSE)
2872                 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
2873         if (flowctrl & ADVERTISE_1000XPSE_ASYM)
2874                 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
2875
2876         if (sg_dig_ctrl != expected_sg_dig_ctrl) {
2877                 if ((tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT) &&
2878                     tp->serdes_counter &&
2879                     ((mac_status & (MAC_STATUS_PCS_SYNCED |
2880                                     MAC_STATUS_RCVD_CFG)) ==
2881                      MAC_STATUS_PCS_SYNCED)) {
2882                         tp->serdes_counter--;
2883                         current_link_up = 1;
2884                         goto out;
2885                 }
2886 restart_autoneg:
2887                 if (workaround)
2888                         tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
2889                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
2890                 udelay(5);
2891                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
2892
2893                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
2894                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2895         } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
2896                                  MAC_STATUS_SIGNAL_DET)) {
2897                 sg_dig_status = tr32(SG_DIG_STATUS);
2898                 mac_status = tr32(MAC_STATUS);
2899
2900                 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
2901                     (mac_status & MAC_STATUS_PCS_SYNCED)) {
2902                         u32 local_adv = 0, remote_adv = 0;
2903
2904                         if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
2905                                 local_adv |= ADVERTISE_1000XPAUSE;
2906                         if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
2907                                 local_adv |= ADVERTISE_1000XPSE_ASYM;
2908
2909                         if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
2910                                 remote_adv |= LPA_1000XPAUSE;
2911                         if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
2912                                 remote_adv |= LPA_1000XPAUSE_ASYM;
2913
2914                         tg3_setup_flow_control(tp, local_adv, remote_adv);
2915                         current_link_up = 1;
2916                         tp->serdes_counter = 0;
2917                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2918                 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
2919                         if (tp->serdes_counter)
2920                                 tp->serdes_counter--;
2921                         else {
2922                                 if (workaround) {
2923                                         u32 val = serdes_cfg;
2924
2925                                         if (port_a)
2926                                                 val |= 0xc010000;
2927                                         else
2928                                                 val |= 0x4010000;
2929
2930                                         tw32_f(MAC_SERDES_CFG, val);
2931                                 }
2932
2933                                 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
2934                                 udelay(40);
2935
2936                                 /* Link parallel detection - link is up */
2937                                 /* only if we have PCS_SYNC and not */
2938                                 /* receiving config code words */
2939                                 mac_status = tr32(MAC_STATUS);
2940                                 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
2941                                     !(mac_status & MAC_STATUS_RCVD_CFG)) {
2942                                         tg3_setup_flow_control(tp, 0, 0);
2943                                         current_link_up = 1;
2944                                         tp->tg3_flags2 |=
2945                                                 TG3_FLG2_PARALLEL_DETECT;
2946                                         tp->serdes_counter =
2947                                                 SERDES_PARALLEL_DET_TIMEOUT;
2948                                 } else
2949                                         goto restart_autoneg;
2950                         }
2951                 }
2952         } else {
2953                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
2954                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2955         }
2956
2957 out:
2958         return current_link_up;
2959 }
2960
2961 static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
2962 {
2963         int current_link_up = 0;
2964
2965         if (!(mac_status & MAC_STATUS_PCS_SYNCED))
2966                 goto out;
2967
2968         if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2969                 u32 txflags, rxflags;
2970                 int i;
2971
2972                 if (fiber_autoneg(tp, &txflags, &rxflags)) {
2973                         u32 local_adv = 0, remote_adv = 0;
2974
2975                         if (txflags & ANEG_CFG_PS1)
2976                                 local_adv |= ADVERTISE_1000XPAUSE;
2977                         if (txflags & ANEG_CFG_PS2)
2978                                 local_adv |= ADVERTISE_1000XPSE_ASYM;
2979
2980                         if (rxflags & MR_LP_ADV_SYM_PAUSE)
2981                                 remote_adv |= LPA_1000XPAUSE;
2982                         if (rxflags & MR_LP_ADV_ASYM_PAUSE)
2983                                 remote_adv |= LPA_1000XPAUSE_ASYM;
2984
2985                         tg3_setup_flow_control(tp, local_adv, remote_adv);
2986
2987                         current_link_up = 1;
2988                 }
2989                 for (i = 0; i < 30; i++) {
2990                         udelay(20);
2991                         tw32_f(MAC_STATUS,
2992                                (MAC_STATUS_SYNC_CHANGED |
2993                                 MAC_STATUS_CFG_CHANGED));
2994                         udelay(40);
2995                         if ((tr32(MAC_STATUS) &
2996                              (MAC_STATUS_SYNC_CHANGED |
2997                               MAC_STATUS_CFG_CHANGED)) == 0)
2998                                 break;
2999                 }
3000
3001                 mac_status = tr32(MAC_STATUS);
3002                 if (current_link_up == 0 &&
3003                     (mac_status & MAC_STATUS_PCS_SYNCED) &&
3004                     !(mac_status & MAC_STATUS_RCVD_CFG))
3005                         current_link_up = 1;
3006         } else {
3007                 tg3_setup_flow_control(tp, 0, 0);
3008
3009                 /* Forcing 1000FD link up. */
3010                 current_link_up = 1;
3011
3012                 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
3013                 udelay(40);
3014
3015                 tw32_f(MAC_MODE, tp->mac_mode);
3016                 udelay(40);
3017         }
3018
3019 out:
3020         return current_link_up;
3021 }
3022
3023 static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
3024 {
3025         u32 orig_pause_cfg;
3026         u16 orig_active_speed;
3027         u8 orig_active_duplex;
3028         u32 mac_status;
3029         int current_link_up;
3030         int i;
3031
3032         orig_pause_cfg = tp->link_config.active_flowctrl;
3033         orig_active_speed = tp->link_config.active_speed;
3034         orig_active_duplex = tp->link_config.active_duplex;
3035
3036         if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
3037             netif_carrier_ok(tp->dev) &&
3038             (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
3039                 mac_status = tr32(MAC_STATUS);
3040                 mac_status &= (MAC_STATUS_PCS_SYNCED |
3041                                MAC_STATUS_SIGNAL_DET |
3042                                MAC_STATUS_CFG_CHANGED |
3043                                MAC_STATUS_RCVD_CFG);
3044                 if (mac_status == (MAC_STATUS_PCS_SYNCED |
3045                                    MAC_STATUS_SIGNAL_DET)) {
3046                         tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3047                                             MAC_STATUS_CFG_CHANGED));
3048                         return 0;
3049                 }
3050         }
3051
3052         tw32_f(MAC_TX_AUTO_NEG, 0);
3053
3054         tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
3055         tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
3056         tw32_f(MAC_MODE, tp->mac_mode);
3057         udelay(40);
3058
3059         if (tp->phy_id == PHY_ID_BCM8002)
3060                 tg3_init_bcm8002(tp);
3061
3062         /* Enable link change event even when serdes polling.  */
3063         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3064         udelay(40);
3065
3066         current_link_up = 0;
3067         mac_status = tr32(MAC_STATUS);
3068
3069         if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
3070                 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
3071         else
3072                 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
3073
3074         tp->hw_status->status =
3075                 (SD_STATUS_UPDATED |
3076                  (tp->hw_status->status & ~SD_STATUS_LINK_CHG));
3077
3078         for (i = 0; i < 100; i++) {
3079                 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3080                                     MAC_STATUS_CFG_CHANGED));
3081                 udelay(5);
3082                 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
3083                                          MAC_STATUS_CFG_CHANGED |
3084                                          MAC_STATUS_LNKSTATE_CHANGED)) == 0)
3085                         break;
3086         }
3087
3088         mac_status = tr32(MAC_STATUS);
3089         if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
3090                 current_link_up = 0;
3091                 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
3092                     tp->serdes_counter == 0) {
3093                         tw32_f(MAC_MODE, (tp->mac_mode |
3094                                           MAC_MODE_SEND_CONFIGS));
3095                         udelay(1);
3096                         tw32_f(MAC_MODE, tp->mac_mode);
3097                 }
3098         }
3099
3100         if (current_link_up == 1) {
3101                 tp->link_config.active_speed = SPEED_1000;
3102                 tp->link_config.active_duplex = DUPLEX_FULL;
3103                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
3104                                     LED_CTRL_LNKLED_OVERRIDE |
3105                                     LED_CTRL_1000MBPS_ON));
3106         } else {
3107                 tp->link_config.active_speed = SPEED_INVALID;
3108                 tp->link_config.active_duplex = DUPLEX_INVALID;
3109                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
3110                                     LED_CTRL_LNKLED_OVERRIDE |
3111                                     LED_CTRL_TRAFFIC_OVERRIDE));
3112         }
3113
3114         if (current_link_up != netif_carrier_ok(tp->dev)) {
3115                 if (current_link_up)
3116                         netif_carrier_on(tp->dev);
3117                 else
3118                         netif_carrier_off(tp->dev);
3119                 tg3_link_report(tp);
3120         } else {
3121                 u32 now_pause_cfg = tp->link_config.active_flowctrl;
3122                 if (orig_pause_cfg != now_pause_cfg ||
3123                     orig_active_speed != tp->link_config.active_speed ||
3124                     orig_active_duplex != tp->link_config.active_duplex)
3125                         tg3_link_report(tp);
3126         }
3127
3128         return 0;
3129 }
3130
3131 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
3132 {
3133         int current_link_up, err = 0;
3134         u32 bmsr, bmcr;
3135         u16 current_speed;
3136         u8 current_duplex;
3137         u32 local_adv, remote_adv;
3138
3139         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3140         tw32_f(MAC_MODE, tp->mac_mode);
3141         udelay(40);
3142
3143         tw32(MAC_EVENT, 0);
3144
3145         tw32_f(MAC_STATUS,
3146              (MAC_STATUS_SYNC_CHANGED |
3147               MAC_STATUS_CFG_CHANGED |
3148               MAC_STATUS_MI_COMPLETION |
3149               MAC_STATUS_LNKSTATE_CHANGED));
3150         udelay(40);
3151
3152         if (force_reset)
3153                 tg3_phy_reset(tp);
3154
3155         current_link_up = 0;
3156         current_speed = SPEED_INVALID;
3157         current_duplex = DUPLEX_INVALID;
3158
3159         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
3160         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
3161         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
3162                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
3163                         bmsr |= BMSR_LSTATUS;
3164                 else
3165                         bmsr &= ~BMSR_LSTATUS;
3166         }
3167
3168         err |= tg3_readphy(tp, MII_BMCR, &bmcr);
3169
3170         if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
3171             (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT) &&
3172              tp->link_config.flowctrl == tp->link_config.active_flowctrl) {
3173                 /* do nothing, just check for link up at the end */
3174         } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3175                 u32 adv, new_adv;
3176
3177                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
3178                 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
3179                                   ADVERTISE_1000XPAUSE |
3180                                   ADVERTISE_1000XPSE_ASYM |
3181                                   ADVERTISE_SLCT);
3182
3183                 new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3184
3185                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
3186                         new_adv |= ADVERTISE_1000XHALF;
3187                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
3188                         new_adv |= ADVERTISE_1000XFULL;
3189
3190                 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
3191                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
3192                         bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
3193                         tg3_writephy(tp, MII_BMCR, bmcr);
3194
3195                         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3196                         tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
3197                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3198
3199                         return err;
3200                 }
3201         } else {
3202                 u32 new_bmcr;
3203
3204                 bmcr &= ~BMCR_SPEED1000;
3205                 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
3206
3207                 if (tp->link_config.duplex == DUPLEX_FULL)
3208                         new_bmcr |= BMCR_FULLDPLX;
3209
3210                 if (new_bmcr != bmcr) {
3211                         /* BMCR_SPEED1000 is a reserved bit that needs
3212                          * to be set on write.
3213                          */
3214                         new_bmcr |= BMCR_SPEED1000;
3215
3216                         /* Force a linkdown */
3217                         if (netif_carrier_ok(tp->dev)) {
3218                                 u32 adv;
3219
3220                                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
3221                                 adv &= ~(ADVERTISE_1000XFULL |
3222                                          ADVERTISE_1000XHALF |
3223                                          ADVERTISE_SLCT);
3224                                 tg3_writephy(tp, MII_ADVERTISE, adv);
3225                                 tg3_writephy(tp, MII_BMCR, bmcr |
3226                                                            BMCR_ANRESTART |
3227                                                            BMCR_ANENABLE);
3228                                 udelay(10);
3229                                 netif_carrier_off(tp->dev);
3230                         }
3231                         tg3_writephy(tp, MII_BMCR, new_bmcr);
3232                         bmcr = new_bmcr;
3233                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
3234                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
3235                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
3236                             ASIC_REV_5714) {
3237                                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
3238                                         bmsr |= BMSR_LSTATUS;
3239                                 else
3240                                         bmsr &= ~BMSR_LSTATUS;
3241                         }
3242                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3243                 }
3244         }
3245
3246         if (bmsr & BMSR_LSTATUS) {
3247                 current_speed = SPEED_1000;
3248                 current_link_up = 1;
3249                 if (bmcr & BMCR_FULLDPLX)
3250                         current_duplex = DUPLEX_FULL;
3251                 else
3252                         current_duplex = DUPLEX_HALF;
3253
3254                 local_adv = 0;
3255                 remote_adv = 0;
3256
3257                 if (bmcr & BMCR_ANENABLE) {
3258                         u32 common;
3259
3260                         err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
3261                         err |= tg3_readphy(tp, MII_LPA, &remote_adv);
3262                         common = local_adv & remote_adv;
3263                         if (common & (ADVERTISE_1000XHALF |
3264                                       ADVERTISE_1000XFULL)) {
3265                                 if (common & ADVERTISE_1000XFULL)
3266                                         current_duplex = DUPLEX_FULL;
3267                                 else
3268                                         current_duplex = DUPLEX_HALF;
3269                         }
3270                         else
3271                                 current_link_up = 0;
3272                 }
3273         }
3274
3275         if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
3276                 tg3_setup_flow_control(tp, local_adv, remote_adv);
3277
3278         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
3279         if (tp->link_config.active_duplex == DUPLEX_HALF)
3280                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
3281
3282         tw32_f(MAC_MODE, tp->mac_mode);
3283         udelay(40);
3284
3285         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3286
3287         tp->link_config.active_speed = current_speed;
3288         tp->link_config.active_duplex = current_duplex;
3289
3290         if (current_link_up != netif_carrier_ok(tp->dev)) {
3291                 if (current_link_up)
3292                         netif_carrier_on(tp->dev);
3293                 else {
3294                         netif_carrier_off(tp->dev);
3295                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3296                 }
3297                 tg3_link_report(tp);
3298         }
3299         return err;
3300 }
3301
3302 static void tg3_serdes_parallel_detect(struct tg3 *tp)
3303 {
3304         if (tp->serdes_counter) {
3305                 /* Give autoneg time to complete. */
3306                 tp->serdes_counter--;
3307                 return;
3308         }
3309         if (!netif_carrier_ok(tp->dev) &&
3310             (tp->link_config.autoneg == AUTONEG_ENABLE)) {
3311                 u32 bmcr;
3312
3313                 tg3_readphy(tp, MII_BMCR, &bmcr);
3314                 if (bmcr & BMCR_ANENABLE) {
3315                         u32 phy1, phy2;
3316
3317                         /* Select shadow register 0x1f */
3318                         tg3_writephy(tp, 0x1c, 0x7c00);
3319                         tg3_readphy(tp, 0x1c, &phy1);
3320
3321                         /* Select expansion interrupt status register */
3322                         tg3_writephy(tp, 0x17, 0x0f01);
3323                         tg3_readphy(tp, 0x15, &phy2);
3324                         tg3_readphy(tp, 0x15, &phy2);
3325
3326                         if ((phy1 & 0x10) && !(phy2 & 0x20)) {
3327                                 /* We have signal detect and not receiving
3328                                  * config code words, link is up by parallel
3329                                  * detection.
3330                                  */
3331
3332                                 bmcr &= ~BMCR_ANENABLE;
3333                                 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
3334                                 tg3_writephy(tp, MII_BMCR, bmcr);
3335                                 tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
3336                         }
3337                 }
3338         }
3339         else if (netif_carrier_ok(tp->dev) &&
3340                  (tp->link_config.autoneg == AUTONEG_ENABLE) &&
3341                  (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
3342                 u32 phy2;
3343
3344                 /* Select expansion interrupt status register */
3345                 tg3_writephy(tp, 0x17, 0x0f01);
3346                 tg3_readphy(tp, 0x15, &phy2);
3347                 if (phy2 & 0x20) {
3348                         u32 bmcr;
3349
3350                         /* Config code words received, turn on autoneg. */
3351                         tg3_readphy(tp, MII_BMCR, &bmcr);
3352                         tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
3353
3354                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3355
3356                 }
3357         }
3358 }
3359
3360 static int tg3_setup_phy(struct tg3 *tp, int force_reset)
3361 {
3362         int err;
3363
3364         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
3365                 err = tg3_setup_fiber_phy(tp, force_reset);
3366         } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
3367                 err = tg3_setup_fiber_mii_phy(tp, force_reset);
3368         } else {
3369                 err = tg3_setup_copper_phy(tp, force_reset);
3370         }
3371
3372         if (tp->pci_chip_rev_id == CHIPREV_ID_5784_A0 ||
3373             tp->pci_chip_rev_id == CHIPREV_ID_5784_A1) {
3374                 u32 val, scale;
3375
3376                 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
3377                 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
3378                         scale = 65;
3379                 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
3380                         scale = 6;
3381                 else
3382                         scale = 12;
3383
3384                 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
3385                 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
3386                 tw32(GRC_MISC_CFG, val);
3387         }
3388
3389         if (tp->link_config.active_speed == SPEED_1000 &&
3390             tp->link_config.active_duplex == DUPLEX_HALF)
3391                 tw32(MAC_TX_LENGTHS,
3392                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
3393                       (6 << TX_LENGTHS_IPG_SHIFT) |
3394                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
3395         else
3396                 tw32(MAC_TX_LENGTHS,
3397                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
3398                       (6 << TX_LENGTHS_IPG_SHIFT) |
3399                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
3400
3401         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
3402                 if (netif_carrier_ok(tp->dev)) {
3403                         tw32(HOSTCC_STAT_COAL_TICKS,
3404                              tp->coal.stats_block_coalesce_usecs);
3405                 } else {
3406                         tw32(HOSTCC_STAT_COAL_TICKS, 0);
3407                 }
3408         }
3409
3410         if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
3411                 u32 val = tr32(PCIE_PWR_MGMT_THRESH);
3412                 if (!netif_carrier_ok(tp->dev))
3413                         val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
3414                               tp->pwrmgmt_thresh;
3415                 else
3416                         val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
3417                 tw32(PCIE_PWR_MGMT_THRESH, val);
3418         }
3419
3420         return err;
3421 }
3422
3423 /* This is called whenever we suspect that the system chipset is re-
3424  * ordering the sequence of MMIO to the tx send mailbox. The symptom
3425  * is bogus tx completions. We try to recover by setting the
3426  * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
3427  * in the workqueue.
3428  */
3429 static void tg3_tx_recover(struct tg3 *tp)
3430 {
3431         BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
3432                tp->write32_tx_mbox == tg3_write_indirect_mbox);
3433
3434         printk(KERN_WARNING PFX "%s: The system may be re-ordering memory-"
3435                "mapped I/O cycles to the network device, attempting to "
3436                "recover. Please report the problem to the driver maintainer "
3437                "and include system chipset information.\n", tp->dev->name);
3438
3439         spin_lock(&tp->lock);
3440         tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
3441         spin_unlock(&tp->lock);
3442 }
3443
3444 static inline u32 tg3_tx_avail(struct tg3 *tp)
3445 {
3446         smp_mb();
3447         return (tp->tx_pending -
3448                 ((tp->tx_prod - tp->tx_cons) & (TG3_TX_RING_SIZE - 1)));
3449 }
3450
3451 /* Tigon3 never reports partial packet sends.  So we do not
3452  * need special logic to handle SKBs that have not had all
3453  * of their frags sent yet, like SunGEM does.
3454  */
3455 static void tg3_tx(struct tg3 *tp)
3456 {
3457         u32 hw_idx = tp->hw_status->idx[0].tx_consumer;
3458         u32 sw_idx = tp->tx_cons;
3459
3460         while (sw_idx != hw_idx) {
3461                 struct tx_ring_info *ri = &tp->tx_buffers[sw_idx];
3462                 struct sk_buff *skb = ri->skb;
3463                 int i, tx_bug = 0;
3464
3465                 if (unlikely(skb == NULL)) {
3466                         tg3_tx_recover(tp);
3467                         return;
3468                 }
3469
3470                 pci_unmap_single(tp->pdev,
3471                                  pci_unmap_addr(ri, mapping),
3472                                  skb_headlen(skb),
3473                                  PCI_DMA_TODEVICE);
3474
3475                 ri->skb = NULL;
3476
3477                 sw_idx = NEXT_TX(sw_idx);
3478
3479                 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
3480                         ri = &tp->tx_buffers[sw_idx];
3481                         if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
3482                                 tx_bug = 1;
3483
3484                         pci_unmap_page(tp->pdev,
3485                                        pci_unmap_addr(ri, mapping),
3486                                        skb_shinfo(skb)->frags[i].size,
3487                                        PCI_DMA_TODEVICE);
3488
3489                         sw_idx = NEXT_TX(sw_idx);
3490                 }
3491
3492                 dev_kfree_skb(skb);
3493
3494                 if (unlikely(tx_bug)) {
3495                         tg3_tx_recover(tp);
3496                         return;
3497                 }
3498         }
3499
3500         tp->tx_cons = sw_idx;
3501
3502         /* Need to make the tx_cons update visible to tg3_start_xmit()
3503          * before checking for netif_queue_stopped().  Without the
3504          * memory barrier, there is a small possibility that tg3_start_xmit()
3505          * will miss it and cause the queue to be stopped forever.
3506          */
3507         smp_mb();
3508
3509         if (unlikely(netif_queue_stopped(tp->dev) &&
3510                      (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp)))) {
3511                 netif_tx_lock(tp->dev);
3512                 if (netif_queue_stopped(tp->dev) &&
3513                     (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp)))
3514                         netif_wake_queue(tp->dev);
3515                 netif_tx_unlock(tp->dev);
3516         }
3517 }
3518
3519 /* Returns size of skb allocated or < 0 on error.
3520  *
3521  * We only need to fill in the address because the other members
3522  * of the RX descriptor are invariant, see tg3_init_rings.
3523  *
3524  * Note the purposeful assymetry of cpu vs. chip accesses.  For
3525  * posting buffers we only dirty the first cache line of the RX
3526  * descriptor (containing the address).  Whereas for the RX status
3527  * buffers the cpu only reads the last cacheline of the RX descriptor
3528  * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
3529  */
3530 static int tg3_alloc_rx_skb(struct tg3 *tp, u32 opaque_key,
3531                             int src_idx, u32 dest_idx_unmasked)
3532 {
3533         struct tg3_rx_buffer_desc *desc;
3534         struct ring_info *map, *src_map;
3535         struct sk_buff *skb;
3536         dma_addr_t mapping;
3537         int skb_size, dest_idx;
3538
3539         src_map = NULL;
3540         switch (opaque_key) {
3541         case RXD_OPAQUE_RING_STD:
3542                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
3543                 desc = &tp->rx_std[dest_idx];
3544                 map = &tp->rx_std_buffers[dest_idx];
3545                 if (src_idx >= 0)
3546                         src_map = &tp->rx_std_buffers[src_idx];
3547                 skb_size = tp->rx_pkt_buf_sz;
3548                 break;
3549
3550         case RXD_OPAQUE_RING_JUMBO:
3551                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
3552                 desc = &tp->rx_jumbo[dest_idx];
3553                 map = &tp->rx_jumbo_buffers[dest_idx];
3554                 if (src_idx >= 0)
3555                         src_map = &tp->rx_jumbo_buffers[src_idx];
3556                 skb_size = RX_JUMBO_PKT_BUF_SZ;
3557                 break;
3558
3559         default:
3560                 return -EINVAL;
3561         }
3562
3563         /* Do not overwrite any of the map or rp information
3564          * until we are sure we can commit to a new buffer.
3565          *
3566          * Callers depend upon this behavior and assume that
3567          * we leave everything unchanged if we fail.
3568          */
3569         skb = netdev_alloc_skb(tp->dev, skb_size);
3570         if (skb == NULL)
3571                 return -ENOMEM;
3572
3573         skb_reserve(skb, tp->rx_offset);
3574
3575         mapping = pci_map_single(tp->pdev, skb->data,
3576                                  skb_size - tp->rx_offset,
3577                                  PCI_DMA_FROMDEVICE);
3578
3579         map->skb = skb;
3580         pci_unmap_addr_set(map, mapping, mapping);
3581
3582         if (src_map != NULL)
3583                 src_map->skb = NULL;
3584
3585         desc->addr_hi = ((u64)mapping >> 32);
3586         desc->addr_lo = ((u64)mapping & 0xffffffff);
3587
3588         return skb_size;
3589 }
3590
3591 /* We only need to move over in the address because the other
3592  * members of the RX descriptor are invariant.  See notes above
3593  * tg3_alloc_rx_skb for full details.
3594  */
3595 static void tg3_recycle_rx(struct tg3 *tp, u32 opaque_key,
3596                            int src_idx, u32 dest_idx_unmasked)
3597 {
3598         struct tg3_rx_buffer_desc *src_desc, *dest_desc;
3599         struct ring_info *src_map, *dest_map;
3600         int dest_idx;
3601
3602         switch (opaque_key) {
3603         case RXD_OPAQUE_RING_STD:
3604                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
3605                 dest_desc = &tp->rx_std[dest_idx];
3606                 dest_map = &tp->rx_std_buffers[dest_idx];
3607                 src_desc = &tp->rx_std[src_idx];
3608                 src_map = &tp->rx_std_buffers[src_idx];
3609                 break;
3610
3611         case RXD_OPAQUE_RING_JUMBO:
3612                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
3613                 dest_desc = &tp->rx_jumbo[dest_idx];
3614                 dest_map = &tp->rx_jumbo_buffers[dest_idx];
3615                 src_desc = &tp->rx_jumbo[src_idx];
3616                 src_map = &tp->rx_jumbo_buffers[src_idx];
3617                 break;
3618
3619         default:
3620                 return;
3621         }
3622
3623         dest_map->skb = src_map->skb;
3624         pci_unmap_addr_set(dest_map, mapping,
3625                            pci_unmap_addr(src_map, mapping));
3626         dest_desc->addr_hi = src_desc->addr_hi;
3627         dest_desc->addr_lo = src_desc->addr_lo;
3628
3629         src_map->skb = NULL;
3630 }
3631
3632 #if TG3_VLAN_TAG_USED
3633 static int tg3_vlan_rx(struct tg3 *tp, struct sk_buff *skb, u16 vlan_tag)
3634 {
3635         return vlan_hwaccel_receive_skb(skb, tp->vlgrp, vlan_tag);
3636 }
3637 #endif
3638
3639 /* The RX ring scheme is composed of multiple rings which post fresh
3640  * buffers to the chip, and one special ring the chip uses to report
3641  * status back to the host.
3642  *
3643  * The special ring reports the status of received packets to the
3644  * host.  The chip does not write into the original descriptor the
3645  * RX buffer was obtained from.  The chip simply takes the original
3646  * descriptor as provided by the host, updates the status and length
3647  * field, then writes this into the next status ring entry.
3648  *
3649  * Each ring the host uses to post buffers to the chip is described
3650  * by a TG3_BDINFO entry in the chips SRAM area.  When a packet arrives,
3651  * it is first placed into the on-chip ram.  When the packet's length
3652  * is known, it walks down the TG3_BDINFO entries to select the ring.
3653  * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
3654  * which is within the range of the new packet's length is chosen.
3655  *
3656  * The "separate ring for rx status" scheme may sound queer, but it makes
3657  * sense from a cache coherency perspective.  If only the host writes
3658  * to the buffer post rings, and only the chip writes to the rx status
3659  * rings, then cache lines never move beyond shared-modified state.
3660  * If both the host and chip were to write into the same ring, cache line
3661  * eviction could occur since both entities want it in an exclusive state.
3662  */
3663 static int tg3_rx(struct tg3 *tp, int budget)
3664 {
3665         u32 work_mask, rx_std_posted = 0;
3666         u32 sw_idx = tp->rx_rcb_ptr;
3667         u16 hw_idx;
3668         int received;
3669
3670         hw_idx = tp->hw_status->idx[0].rx_producer;
3671         /*
3672          * We need to order the read of hw_idx and the read of
3673          * the opaque cookie.
3674          */
3675         rmb();
3676         work_mask = 0;
3677         received = 0;
3678         while (sw_idx != hw_idx && budget > 0) {
3679                 struct tg3_rx_buffer_desc *desc = &tp->rx_rcb[sw_idx];
3680                 unsigned int len;
3681                 struct sk_buff *skb;
3682                 dma_addr_t dma_addr;
3683                 u32 opaque_key, desc_idx, *post_ptr;
3684
3685                 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
3686                 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
3687                 if (opaque_key == RXD_OPAQUE_RING_STD) {
3688                         dma_addr = pci_unmap_addr(&tp->rx_std_buffers[desc_idx],
3689                                                   mapping);
3690                         skb = tp->rx_std_buffers[desc_idx].skb;
3691                         post_ptr = &tp->rx_std_ptr;
3692                         rx_std_posted++;
3693                 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
3694                         dma_addr = pci_unmap_addr(&tp->rx_jumbo_buffers[desc_idx],
3695                                                   mapping);
3696                         skb = tp->rx_jumbo_buffers[desc_idx].skb;
3697                         post_ptr = &tp->rx_jumbo_ptr;
3698                 }
3699                 else {
3700                         goto next_pkt_nopost;
3701                 }
3702
3703                 work_mask |= opaque_key;
3704
3705                 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
3706                     (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
3707                 drop_it:
3708                         tg3_recycle_rx(tp, opaque_key,
3709                                        desc_idx, *post_ptr);
3710                 drop_it_no_recycle:
3711                         /* Other statistics kept track of by card. */
3712                         tp->net_stats.rx_dropped++;
3713                         goto next_pkt;
3714                 }
3715
3716                 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4; /* omit crc */
3717
3718                 if (len > RX_COPY_THRESHOLD
3719                         && tp->rx_offset == 2
3720                         /* rx_offset != 2 iff this is a 5701 card running
3721                          * in PCI-X mode [see tg3_get_invariants()] */
3722                 ) {
3723                         int skb_size;
3724
3725                         skb_size = tg3_alloc_rx_skb(tp, opaque_key,
3726                                                     desc_idx, *post_ptr);
3727                         if (skb_size < 0)
3728                                 goto drop_it;
3729
3730                         pci_unmap_single(tp->pdev, dma_addr,
3731                                          skb_size - tp->rx_offset,
3732                                          PCI_DMA_FROMDEVICE);
3733
3734                         skb_put(skb, len);
3735                 } else {
3736                         struct sk_buff *copy_skb;
3737
3738                         tg3_recycle_rx(tp, opaque_key,
3739                                        desc_idx, *post_ptr);
3740
3741                         copy_skb = netdev_alloc_skb(tp->dev, len + 2);
3742                         if (copy_skb == NULL)
3743                                 goto drop_it_no_recycle;
3744
3745                         skb_reserve(copy_skb, 2);
3746                         skb_put(copy_skb, len);
3747                         pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
3748                         skb_copy_from_linear_data(skb, copy_skb->data, len);
3749                         pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
3750
3751                         /* We'll reuse the original ring buffer. */
3752                         skb = copy_skb;
3753                 }
3754
3755                 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
3756                     (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
3757                     (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
3758                       >> RXD_TCPCSUM_SHIFT) == 0xffff))
3759                         skb->ip_summed = CHECKSUM_UNNECESSARY;
3760                 else
3761                         skb->ip_summed = CHECKSUM_NONE;
3762
3763                 skb->protocol = eth_type_trans(skb, tp->dev);
3764 #if TG3_VLAN_TAG_USED
3765                 if (tp->vlgrp != NULL &&
3766                     desc->type_flags & RXD_FLAG_VLAN) {
3767                         tg3_vlan_rx(tp, skb,
3768                                     desc->err_vlan & RXD_VLAN_MASK);
3769                 } else
3770 #endif
3771                         netif_receive_skb(skb);
3772
3773                 tp->dev->last_rx = jiffies;
3774                 received++;
3775                 budget--;
3776
3777 next_pkt:
3778                 (*post_ptr)++;
3779
3780                 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
3781                         u32 idx = *post_ptr % TG3_RX_RING_SIZE;
3782
3783                         tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX +
3784                                      TG3_64BIT_REG_LOW, idx);
3785                         work_mask &= ~RXD_OPAQUE_RING_STD;
3786                         rx_std_posted = 0;
3787                 }
3788 next_pkt_nopost:
3789                 sw_idx++;
3790                 sw_idx &= (TG3_RX_RCB_RING_SIZE(tp) - 1);
3791
3792                 /* Refresh hw_idx to see if there is new work */
3793                 if (sw_idx == hw_idx) {
3794                         hw_idx = tp->hw_status->idx[0].rx_producer;
3795                         rmb();
3796                 }
3797         }
3798
3799         /* ACK the status ring. */
3800         tp->rx_rcb_ptr = sw_idx;
3801         tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, sw_idx);
3802
3803         /* Refill RX ring(s). */
3804         if (work_mask & RXD_OPAQUE_RING_STD) {
3805                 sw_idx = tp->rx_std_ptr % TG3_RX_RING_SIZE;
3806                 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
3807                              sw_idx);
3808         }
3809         if (work_mask & RXD_OPAQUE_RING_JUMBO) {
3810                 sw_idx = tp->rx_jumbo_ptr % TG3_RX_JUMBO_RING_SIZE;
3811                 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
3812                              sw_idx);
3813         }
3814         mmiowb();
3815
3816         return received;
3817 }
3818
3819 static int tg3_poll_work(struct tg3 *tp, int work_done, int budget)
3820 {
3821         struct tg3_hw_status *sblk = tp->hw_status;
3822
3823         /* handle link change and other phy events */
3824         if (!(tp->tg3_flags &
3825               (TG3_FLAG_USE_LINKCHG_REG |
3826                TG3_FLAG_POLL_SERDES))) {
3827                 if (sblk->status & SD_STATUS_LINK_CHG) {
3828                         sblk->status = SD_STATUS_UPDATED |
3829                                 (sblk->status & ~SD_STATUS_LINK_CHG);
3830                         spin_lock(&tp->lock);
3831                         tg3_setup_phy(tp, 0);
3832                         spin_unlock(&tp->lock);
3833                 }
3834         }
3835
3836         /* run TX completion thread */
3837         if (sblk->idx[0].tx_consumer != tp->tx_cons) {
3838                 tg3_tx(tp);
3839                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
3840                         return work_done;
3841         }
3842
3843         /* run RX thread, within the bounds set by NAPI.
3844          * All RX "locking" is done by ensuring outside
3845          * code synchronizes with tg3->napi.poll()
3846          */
3847         if (sblk->idx[0].rx_producer != tp->rx_rcb_ptr)
3848                 work_done += tg3_rx(tp, budget - work_done);
3849
3850         return work_done;
3851 }
3852
3853 static int tg3_poll(struct napi_struct *napi, int budget)
3854 {
3855         struct tg3 *tp = container_of(napi, struct tg3, napi);
3856         int work_done = 0;
3857         struct tg3_hw_status *sblk = tp->hw_status;
3858
3859         while (1) {
3860                 work_done = tg3_poll_work(tp, work_done, budget);
3861
3862                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
3863                         goto tx_recovery;
3864
3865                 if (unlikely(work_done >= budget))
3866                         break;
3867
3868                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
3869                         /* tp->last_tag is used in tg3_restart_ints() below
3870                          * to tell the hw how much work has been processed,
3871                          * so we must read it before checking for more work.
3872                          */
3873                         tp->last_tag = sblk->status_tag;
3874                         rmb();
3875                 } else
3876                         sblk->status &= ~SD_STATUS_UPDATED;
3877
3878                 if (likely(!tg3_has_work(tp))) {
3879                         netif_rx_complete(tp->dev, napi);
3880                         tg3_restart_ints(tp);
3881                         break;
3882                 }
3883         }
3884
3885         return work_done;
3886
3887 tx_recovery:
3888         /* work_done is guaranteed to be less than budget. */
3889         netif_rx_complete(tp->dev, napi);
3890         schedule_work(&tp->reset_task);
3891         return work_done;
3892 }
3893
3894 static void tg3_irq_quiesce(struct tg3 *tp)
3895 {
3896         BUG_ON(tp->irq_sync);
3897
3898         tp->irq_sync = 1;
3899         smp_mb();
3900
3901         synchronize_irq(tp->pdev->irq);
3902 }
3903
3904 static inline int tg3_irq_sync(struct tg3 *tp)
3905 {
3906         return tp->irq_sync;
3907 }
3908
3909 /* Fully shutdown all tg3 driver activity elsewhere in the system.
3910  * If irq_sync is non-zero, then the IRQ handler must be synchronized
3911  * with as well.  Most of the time, this is not necessary except when
3912  * shutting down the device.
3913  */
3914 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
3915 {
3916         spin_lock_bh(&tp->lock);
3917         if (irq_sync)
3918                 tg3_irq_quiesce(tp);
3919 }
3920
3921 static inline void tg3_full_unlock(struct tg3 *tp)
3922 {
3923         spin_unlock_bh(&tp->lock);
3924 }
3925
3926 /* One-shot MSI handler - Chip automatically disables interrupt
3927  * after sending MSI so driver doesn't have to do it.
3928  */
3929 static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
3930 {
3931         struct net_device *dev = dev_id;
3932         struct tg3 *tp = netdev_priv(dev);
3933
3934         prefetch(tp->hw_status);
3935         prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
3936
3937         if (likely(!tg3_irq_sync(tp)))
3938                 netif_rx_schedule(dev, &tp->napi);
3939
3940         return IRQ_HANDLED;
3941 }
3942
3943 /* MSI ISR - No need to check for interrupt sharing and no need to
3944  * flush status block and interrupt mailbox. PCI ordering rules
3945  * guarantee that MSI will arrive after the status block.
3946  */
3947 static irqreturn_t tg3_msi(int irq, void *dev_id)
3948 {
3949         struct net_device *dev = dev_id;
3950         struct tg3 *tp = netdev_priv(dev);
3951
3952         prefetch(tp->hw_status);
3953         prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
3954         /*
3955          * Writing any value to intr-mbox-0 clears PCI INTA# and
3956          * chip-internal interrupt pending events.
3957          * Writing non-zero to intr-mbox-0 additional tells the
3958          * NIC to stop sending us irqs, engaging "in-intr-handler"
3959          * event coalescing.
3960          */
3961         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
3962         if (likely(!tg3_irq_sync(tp)))
3963                 netif_rx_schedule(dev, &tp->napi);
3964
3965         return IRQ_RETVAL(1);
3966 }
3967
3968 static irqreturn_t tg3_interrupt(int irq, void *dev_id)
3969 {
3970         struct net_device *dev = dev_id;
3971         struct tg3 *tp = netdev_priv(dev);
3972         struct tg3_hw_status *sblk = tp->hw_status;
3973         unsigned int handled = 1;
3974
3975         /* In INTx mode, it is possible for the interrupt to arrive at
3976          * the CPU before the status block posted prior to the interrupt.
3977          * Reading the PCI State register will confirm whether the
3978          * interrupt is ours and will flush the status block.
3979          */
3980         if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
3981                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
3982                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
3983                         handled = 0;
3984                         goto out;
3985                 }
3986         }
3987
3988         /*
3989          * Writing any value to intr-mbox-0 clears PCI INTA# and
3990          * chip-internal interrupt pending events.
3991          * Writing non-zero to intr-mbox-0 additional tells the
3992          * NIC to stop sending us irqs, engaging "in-intr-handler"
3993          * event coalescing.
3994          *
3995          * Flush the mailbox to de-assert the IRQ immediately to prevent
3996          * spurious interrupts.  The flush impacts performance but
3997          * excessive spurious interrupts can be worse in some cases.
3998          */
3999         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
4000         if (tg3_irq_sync(tp))
4001                 goto out;
4002         sblk->status &= ~SD_STATUS_UPDATED;
4003         if (likely(tg3_has_work(tp))) {
4004                 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
4005                 netif_rx_schedule(dev, &tp->napi);
4006         } else {
4007                 /* No work, shared interrupt perhaps?  re-enable
4008                  * interrupts, and flush that PCI write
4009                  */
4010                 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
4011                                0x00000000);
4012         }
4013 out:
4014         return IRQ_RETVAL(handled);
4015 }
4016
4017 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
4018 {
4019         struct net_device *dev = dev_id;
4020         struct tg3 *tp = netdev_priv(dev);
4021         struct tg3_hw_status *sblk = tp->hw_status;
4022         unsigned int handled = 1;
4023
4024         /* In INTx mode, it is possible for the interrupt to arrive at
4025          * the CPU before the status block posted prior to the interrupt.
4026          * Reading the PCI State register will confirm whether the
4027          * interrupt is ours and will flush the status block.
4028          */
4029         if (unlikely(sblk->status_tag == tp->last_tag)) {
4030                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
4031                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4032                         handled = 0;
4033                         goto out;
4034                 }
4035         }
4036
4037         /*
4038          * writing any value to intr-mbox-0 clears PCI INTA# and
4039          * chip-internal interrupt pending events.
4040          * writing non-zero to intr-mbox-0 additional tells the
4041          * NIC to stop sending us irqs, engaging "in-intr-handler"
4042          * event coalescing.
4043          *
4044          * Flush the mailbox to de-assert the IRQ immediately to prevent
4045          * spurious interrupts.  The flush impacts performance but
4046          * excessive spurious interrupts can be worse in some cases.
4047          */
4048         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
4049         if (tg3_irq_sync(tp))
4050                 goto out;
4051         if (netif_rx_schedule_prep(dev, &tp->napi)) {
4052                 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
4053                 /* Update last_tag to mark that this status has been
4054                  * seen. Because interrupt may be shared, we may be
4055                  * racing with tg3_poll(), so only update last_tag
4056                  * if tg3_poll() is not scheduled.
4057                  */
4058                 tp->last_tag = sblk->status_tag;
4059                 __netif_rx_schedule(dev, &tp->napi);
4060         }
4061 out:
4062         return IRQ_RETVAL(handled);
4063 }
4064
4065 /* ISR for interrupt test */
4066 static irqreturn_t tg3_test_isr(int irq, void *dev_id)
4067 {
4068         struct net_device *dev = dev_id;
4069         struct tg3 *tp = netdev_priv(dev);
4070         struct tg3_hw_status *sblk = tp->hw_status;
4071
4072         if ((sblk->status & SD_STATUS_UPDATED) ||
4073             !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4074                 tg3_disable_ints(tp);
4075                 return IRQ_RETVAL(1);
4076         }
4077         return IRQ_RETVAL(0);
4078 }
4079
4080 static int tg3_init_hw(struct tg3 *, int);
4081 static int tg3_halt(struct tg3 *, int, int);
4082
4083 /* Restart hardware after configuration changes, self-test, etc.
4084  * Invoked with tp->lock held.
4085  */
4086 static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
4087         __releases(tp->lock)
4088         __acquires(tp->lock)
4089 {
4090         int err;
4091
4092         err = tg3_init_hw(tp, reset_phy);
4093         if (err) {
4094                 printk(KERN_ERR PFX "%s: Failed to re-initialize device, "
4095                        "aborting.\n", tp->dev->name);
4096                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
4097                 tg3_full_unlock(tp);
4098                 del_timer_sync(&tp->timer);
4099                 tp->irq_sync = 0;
4100                 napi_enable(&tp->napi);
4101                 dev_close(tp->dev);
4102                 tg3_full_lock(tp, 0);
4103         }
4104         return err;
4105 }
4106
4107 #ifdef CONFIG_NET_POLL_CONTROLLER
4108 static void tg3_poll_controller(struct net_device *dev)
4109 {
4110         struct tg3 *tp = netdev_priv(dev);
4111
4112         tg3_interrupt(tp->pdev->irq, dev);
4113 }
4114 #endif
4115
4116 static void tg3_reset_task(struct work_struct *work)
4117 {
4118         struct tg3 *tp = container_of(work, struct tg3, reset_task);
4119         unsigned int restart_timer;
4120
4121         tg3_full_lock(tp, 0);
4122
4123         if (!netif_running(tp->dev)) {
4124                 tg3_full_unlock(tp);
4125                 return;
4126         }
4127
4128         tg3_full_unlock(tp);
4129
4130         tg3_netif_stop(tp);
4131
4132         tg3_full_lock(tp, 1);
4133
4134         restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
4135         tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
4136
4137         if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
4138                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
4139                 tp->write32_rx_mbox = tg3_write_flush_reg32;
4140                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
4141                 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
4142         }
4143
4144         tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
4145         if (tg3_init_hw(tp, 1))
4146                 goto out;
4147
4148         tg3_netif_start(tp);
4149
4150         if (restart_timer)
4151                 mod_timer(&tp->timer, jiffies + 1);
4152
4153 out:
4154         tg3_full_unlock(tp);
4155 }
4156
4157 static void tg3_dump_short_state(struct tg3 *tp)
4158 {
4159         printk(KERN_ERR PFX "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
4160                tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
4161         printk(KERN_ERR PFX "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
4162                tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
4163 }
4164
4165 static void tg3_tx_timeout(struct net_device *dev)
4166 {
4167         struct tg3 *tp = netdev_priv(dev);
4168
4169         if (netif_msg_tx_err(tp)) {
4170                 printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
4171                        dev->name);
4172                 tg3_dump_short_state(tp);
4173         }
4174
4175         schedule_work(&tp->reset_task);
4176 }
4177
4178 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
4179 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
4180 {
4181         u32 base = (u32) mapping & 0xffffffff;
4182
4183         return ((base > 0xffffdcc0) &&
4184                 (base + len + 8 < base));
4185 }
4186
4187 /* Test for DMA addresses > 40-bit */
4188 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
4189                                           int len)
4190 {
4191 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
4192         if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
4193                 return (((u64) mapping + len) > DMA_40BIT_MASK);
4194         return 0;
4195 #else
4196         return 0;
4197 #endif
4198 }
4199
4200 static void tg3_set_txd(struct tg3 *, int, dma_addr_t, int, u32, u32);
4201
4202 /* Workaround 4GB and 40-bit hardware DMA bugs. */
4203 static int tigon3_dma_hwbug_workaround(struct tg3 *tp, struct sk_buff *skb,
4204                                        u32 last_plus_one, u32 *start,
4205                                        u32 base_flags, u32 mss)
4206 {
4207         struct sk_buff *new_skb;
4208         dma_addr_t new_addr = 0;
4209         u32 entry = *start;
4210         int i, ret = 0;
4211
4212         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
4213                 new_skb = skb_copy(skb, GFP_ATOMIC);
4214         else {
4215                 int more_headroom = 4 - ((unsigned long)skb->data & 3);
4216
4217                 new_skb = skb_copy_expand(skb,
4218                                           skb_headroom(skb) + more_headroom,
4219                                           skb_tailroom(skb), GFP_ATOMIC);
4220         }
4221
4222         if (!new_skb) {
4223                 ret = -1;
4224         } else {
4225                 /* New SKB is guaranteed to be linear. */
4226                 entry = *start;
4227                 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
4228                                           PCI_DMA_TODEVICE);
4229                 /* Make sure new skb does not cross any 4G boundaries.
4230                  * Drop the packet if it does.
4231                  */
4232                 if (tg3_4g_overflow_test(new_addr, new_skb->len)) {
4233                         ret = -1;
4234                         dev_kfree_skb(new_skb);
4235                         new_skb = NULL;
4236                 } else {
4237                         tg3_set_txd(tp, entry, new_addr, new_skb->len,
4238                                     base_flags, 1 | (mss << 1));
4239                         *start = NEXT_TX(entry);
4240                 }
4241         }
4242
4243         /* Now clean up the sw ring entries. */
4244         i = 0;
4245         while (entry != last_plus_one) {
4246                 int len;
4247
4248                 if (i == 0)
4249                         len = skb_headlen(skb);
4250                 else
4251                         len = skb_shinfo(skb)->frags[i-1].size;
4252                 pci_unmap_single(tp->pdev,
4253                                  pci_unmap_addr(&tp->tx_buffers[entry], mapping),
4254                                  len, PCI_DMA_TODEVICE);
4255                 if (i == 0) {
4256                         tp->tx_buffers[entry].skb = new_skb;
4257                         pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, new_addr);
4258                 } else {
4259                         tp->tx_buffers[entry].skb = NULL;
4260                 }
4261                 entry = NEXT_TX(entry);
4262                 i++;
4263         }
4264
4265         dev_kfree_skb(skb);
4266
4267         return ret;
4268 }
4269
4270 static void tg3_set_txd(struct tg3 *tp, int entry,
4271                         dma_addr_t mapping, int len, u32 flags,
4272                         u32 mss_and_is_end)
4273 {
4274         struct tg3_tx_buffer_desc *txd = &tp->tx_ring[entry];
4275         int is_end = (mss_and_is_end & 0x1);
4276         u32 mss = (mss_and_is_end >> 1);
4277         u32 vlan_tag = 0;
4278
4279         if (is_end)
4280                 flags |= TXD_FLAG_END;
4281         if (flags & TXD_FLAG_VLAN) {
4282                 vlan_tag = flags >> 16;
4283                 flags &= 0xffff;
4284         }
4285         vlan_tag |= (mss << TXD_MSS_SHIFT);
4286
4287         txd->addr_hi = ((u64) mapping >> 32);
4288         txd->addr_lo = ((u64) mapping & 0xffffffff);
4289         txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
4290         txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
4291 }
4292
4293 /* hard_start_xmit for devices that don't have any bugs and
4294  * support TG3_FLG2_HW_TSO_2 only.
4295  */
4296 static int tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
4297 {
4298         struct tg3 *tp = netdev_priv(dev);
4299         dma_addr_t mapping;
4300         u32 len, entry, base_flags, mss;
4301
4302         len = skb_headlen(skb);
4303
4304         /* We are running in BH disabled context with netif_tx_lock
4305          * and TX reclaim runs via tp->napi.poll inside of a software
4306          * interrupt.  Furthermore, IRQ processing runs lockless so we have
4307          * no IRQ context deadlocks to worry about either.  Rejoice!
4308          */
4309         if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
4310                 if (!netif_queue_stopped(dev)) {
4311                         netif_stop_queue(dev);
4312
4313                         /* This is a hard error, log it. */
4314                         printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
4315                                "queue awake!\n", dev->name);
4316                 }
4317                 return NETDEV_TX_BUSY;
4318         }
4319
4320         entry = tp->tx_prod;
4321         base_flags = 0;
4322         mss = 0;
4323         if ((mss = skb_shinfo(skb)->gso_size) != 0) {
4324                 int tcp_opt_len, ip_tcp_len;
4325
4326                 if (skb_header_cloned(skb) &&
4327                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
4328                         dev_kfree_skb(skb);
4329                         goto out_unlock;
4330                 }
4331
4332                 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
4333                         mss |= (skb_headlen(skb) - ETH_HLEN) << 9;
4334                 else {
4335                         struct iphdr *iph = ip_hdr(skb);
4336
4337                         tcp_opt_len = tcp_optlen(skb);
4338                         ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
4339
4340                         iph->check = 0;
4341                         iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
4342                         mss |= (ip_tcp_len + tcp_opt_len) << 9;
4343                 }
4344
4345                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
4346                                TXD_FLAG_CPU_POST_DMA);
4347
4348                 tcp_hdr(skb)->check = 0;
4349
4350         }
4351         else if (skb->ip_summed == CHECKSUM_PARTIAL)
4352                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
4353 #if TG3_VLAN_TAG_USED
4354         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
4355                 base_flags |= (TXD_FLAG_VLAN |
4356                                (vlan_tx_tag_get(skb) << 16));
4357 #endif
4358
4359         /* Queue skb data, a.k.a. the main skb fragment. */
4360         mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
4361
4362         tp->tx_buffers[entry].skb = skb;
4363         pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
4364
4365         tg3_set_txd(tp, entry, mapping, len, base_flags,
4366                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
4367
4368         entry = NEXT_TX(entry);
4369
4370         /* Now loop through additional data fragments, and queue them. */
4371         if (skb_shinfo(skb)->nr_frags > 0) {
4372                 unsigned int i, last;
4373
4374                 last = skb_shinfo(skb)->nr_frags - 1;
4375                 for (i = 0; i <= last; i++) {
4376                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
4377
4378                         len = frag->size;
4379                         mapping = pci_map_page(tp->pdev,
4380                                                frag->page,
4381                                                frag->page_offset,
4382                                                len, PCI_DMA_TODEVICE);
4383
4384                         tp->tx_buffers[entry].skb = NULL;
4385                         pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
4386
4387                         tg3_set_txd(tp, entry, mapping, len,
4388                                     base_flags, (i == last) | (mss << 1));
4389
4390                         entry = NEXT_TX(entry);
4391                 }
4392         }
4393
4394         /* Packets are ready, update Tx producer idx local and on card. */
4395         tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
4396
4397         tp->tx_prod = entry;
4398         if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
4399                 netif_stop_queue(dev);
4400                 if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp))
4401                         netif_wake_queue(tp->dev);
4402         }
4403
4404 out_unlock:
4405         mmiowb();
4406
4407         dev->trans_start = jiffies;
4408
4409         return NETDEV_TX_OK;
4410 }
4411
4412 static int tg3_start_xmit_dma_bug(struct sk_buff *, struct net_device *);
4413
4414 /* Use GSO to workaround a rare TSO bug that may be triggered when the
4415  * TSO header is greater than 80 bytes.
4416  */
4417 static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
4418 {
4419         struct sk_buff *segs, *nskb;
4420
4421         /* Estimate the number of fragments in the worst case */
4422         if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->gso_segs * 3))) {
4423                 netif_stop_queue(tp->dev);
4424                 if (tg3_tx_avail(tp) <= (skb_shinfo(skb)->gso_segs * 3))
4425                         return NETDEV_TX_BUSY;
4426
4427                 netif_wake_queue(tp->dev);
4428         }
4429
4430         segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
4431         if (IS_ERR(segs))
4432                 goto tg3_tso_bug_end;
4433
4434         do {
4435                 nskb = segs;
4436                 segs = segs->next;
4437                 nskb->next = NULL;
4438                 tg3_start_xmit_dma_bug(nskb, tp->dev);
4439         } while (segs);
4440
4441 tg3_tso_bug_end:
4442         dev_kfree_skb(skb);
4443
4444         return NETDEV_TX_OK;
4445 }
4446
4447 /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
4448  * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
4449  */
4450 static int tg3_start_xmit_dma_bug(struct sk_buff *skb, struct net_device *dev)
4451 {
4452         struct tg3 *tp = netdev_priv(dev);
4453         dma_addr_t mapping;
4454         u32 len, entry, base_flags, mss;
4455         int would_hit_hwbug;
4456
4457         len = skb_headlen(skb);
4458
4459         /* We are running in BH disabled context with netif_tx_lock
4460          * and TX reclaim runs via tp->napi.poll inside of a software
4461          * interrupt.  Furthermore, IRQ processing runs lockless so we have
4462          * no IRQ context deadlocks to worry about either.  Rejoice!
4463          */
4464         if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
4465                 if (!netif_queue_stopped(dev)) {
4466                         netif_stop_queue(dev);
4467
4468                         /* This is a hard error, log it. */
4469                         printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
4470                                "queue awake!\n", dev->name);
4471                 }
4472                 return NETDEV_TX_BUSY;
4473         }
4474
4475         entry = tp->tx_prod;
4476         base_flags = 0;
4477         if (skb->ip_summed == CHECKSUM_PARTIAL)
4478                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
4479         mss = 0;
4480         if ((mss = skb_shinfo(skb)->gso_size) != 0) {
4481                 struct iphdr *iph;
4482                 int tcp_opt_len, ip_tcp_len, hdr_len;
4483
4484                 if (skb_header_cloned(skb) &&
4485                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
4486                         dev_kfree_skb(skb);
4487                         goto out_unlock;
4488                 }
4489
4490                 tcp_opt_len = tcp_optlen(skb);
4491                 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
4492
4493                 hdr_len = ip_tcp_len + tcp_opt_len;
4494                 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
4495                              (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
4496                         return (tg3_tso_bug(tp, skb));
4497
4498                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
4499                                TXD_FLAG_CPU_POST_DMA);
4500
4501                 iph = ip_hdr(skb);
4502                 iph->check = 0;
4503                 iph->tot_len = htons(mss + hdr_len);
4504                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
4505                         tcp_hdr(skb)->check = 0;
4506                         base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
4507                 } else
4508                         tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
4509                                                                  iph->daddr, 0,
4510                                                                  IPPROTO_TCP,
4511                                                                  0);
4512
4513                 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
4514                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)) {
4515                         if (tcp_opt_len || iph->ihl > 5) {
4516                                 int tsflags;
4517
4518                                 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
4519                                 mss |= (tsflags << 11);
4520                         }
4521                 } else {
4522                         if (tcp_opt_len || iph->ihl > 5) {
4523                                 int tsflags;
4524
4525                                 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
4526                                 base_flags |= tsflags << 12;
4527                         }
4528                 }
4529         }
4530 #if TG3_VLAN_TAG_USED
4531         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
4532                 base_flags |= (TXD_FLAG_VLAN |
4533                                (vlan_tx_tag_get(skb) << 16));
4534 #endif
4535
4536         /* Queue skb data, a.k.a. the main skb fragment. */
4537         mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
4538
4539         tp->tx_buffers[entry].skb = skb;
4540         pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
4541
4542         would_hit_hwbug = 0;
4543
4544         if (tp->tg3_flags3 & TG3_FLG3_5701_DMA_BUG)
4545                 would_hit_hwbug = 1;
4546         else if (tg3_4g_overflow_test(mapping, len))
4547                 would_hit_hwbug = 1;
4548
4549         tg3_set_txd(tp, entry, mapping, len, base_flags,
4550                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
4551
4552         entry = NEXT_TX(entry);
4553
4554         /* Now loop through additional data fragments, and queue them. */
4555         if (skb_shinfo(skb)->nr_frags > 0) {
4556                 unsigned int i, last;
4557
4558                 last = skb_shinfo(skb)->nr_frags - 1;
4559                 for (i = 0; i <= last; i++) {
4560                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
4561
4562                         len = frag->size;
4563                         mapping = pci_map_page(tp->pdev,
4564                                                frag->page,
4565                                                frag->page_offset,
4566                                                len, PCI_DMA_TODEVICE);
4567
4568                         tp->tx_buffers[entry].skb = NULL;
4569                         pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
4570
4571                         if (tg3_4g_overflow_test(mapping, len))
4572                                 would_hit_hwbug = 1;
4573
4574                         if (tg3_40bit_overflow_test(tp, mapping, len))
4575                                 would_hit_hwbug = 1;
4576
4577                         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
4578                                 tg3_set_txd(tp, entry, mapping, len,
4579                                             base_flags, (i == last)|(mss << 1));
4580                         else
4581                                 tg3_set_txd(tp, entry, mapping, len,
4582                                             base_flags, (i == last));
4583
4584                         entry = NEXT_TX(entry);
4585                 }
4586         }
4587
4588         if (would_hit_hwbug) {
4589                 u32 last_plus_one = entry;
4590                 u32 start;
4591
4592                 start = entry - 1 - skb_shinfo(skb)->nr_frags;
4593                 start &= (TG3_TX_RING_SIZE - 1);
4594
4595                 /* If the workaround fails due to memory/mapping
4596                  * failure, silently drop this packet.
4597                  */
4598                 if (tigon3_dma_hwbug_workaround(tp, skb, last_plus_one,
4599                                                 &start, base_flags, mss))
4600                         goto out_unlock;
4601
4602                 entry = start;
4603         }
4604
4605         /* Packets are ready, update Tx producer idx local and on card. */
4606         tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
4607
4608         tp->tx_prod = entry;
4609         if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
4610                 netif_stop_queue(dev);
4611                 if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp))
4612                         netif_wake_queue(tp->dev);
4613         }
4614
4615 out_unlock:
4616         mmiowb();
4617
4618         dev->trans_start = jiffies;
4619
4620         return NETDEV_TX_OK;
4621 }
4622
4623 static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
4624                                int new_mtu)
4625 {
4626         dev->mtu = new_mtu;
4627
4628         if (new_mtu > ETH_DATA_LEN) {
4629                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
4630                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
4631                         ethtool_op_set_tso(dev, 0);
4632                 }
4633                 else
4634                         tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
4635         } else {
4636                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
4637                         tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
4638                 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
4639         }
4640 }
4641
4642 static int tg3_change_mtu(struct net_device *dev, int new_mtu)
4643 {
4644         struct tg3 *tp = netdev_priv(dev);
4645         int err;
4646
4647         if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
4648                 return -EINVAL;
4649
4650         if (!netif_running(dev)) {
4651                 /* We'll just catch it later when the
4652                  * device is up'd.
4653                  */
4654                 tg3_set_mtu(dev, tp, new_mtu);
4655                 return 0;
4656         }
4657
4658         tg3_netif_stop(tp);
4659
4660         tg3_full_lock(tp, 1);
4661
4662         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
4663
4664         tg3_set_mtu(dev, tp, new_mtu);
4665
4666         err = tg3_restart_hw(tp, 0);
4667
4668         if (!err)
4669                 tg3_netif_start(tp);
4670
4671         tg3_full_unlock(tp);
4672
4673         return err;
4674 }
4675
4676 /* Free up pending packets in all rx/tx rings.
4677  *
4678  * The chip has been shut down and the driver detached from
4679  * the networking, so no interrupts or new tx packets will
4680  * end up in the driver.  tp->{tx,}lock is not held and we are not
4681  * in an interrupt context and thus may sleep.
4682  */
4683 static void tg3_free_rings(struct tg3 *tp)
4684 {
4685         struct ring_info *rxp;
4686         int i;
4687
4688         for (i = 0; i < TG3_RX_RING_SIZE; i++) {
4689                 rxp = &tp->rx_std_buffers[i];
4690
4691                 if (rxp->skb == NULL)
4692                         continue;
4693                 pci_unmap_single(tp->pdev,
4694                                  pci_unmap_addr(rxp, mapping),
4695                                  tp->rx_pkt_buf_sz - tp->rx_offset,
4696                                  PCI_DMA_FROMDEVICE);
4697                 dev_kfree_skb_any(rxp->skb);
4698                 rxp->skb = NULL;
4699         }
4700
4701         for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
4702                 rxp = &tp->rx_jumbo_buffers[i];
4703
4704                 if (rxp->skb == NULL)
4705                         continue;
4706                 pci_unmap_single(tp->pdev,
4707                                  pci_unmap_addr(rxp, mapping),
4708                                  RX_JUMBO_PKT_BUF_SZ - tp->rx_offset,
4709                                  PCI_DMA_FROMDEVICE);
4710                 dev_kfree_skb_any(rxp->skb);
4711                 rxp->skb = NULL;
4712         }
4713
4714         for (i = 0; i < TG3_TX_RING_SIZE; ) {
4715                 struct tx_ring_info *txp;
4716                 struct sk_buff *skb;
4717                 int j;
4718
4719                 txp = &tp->tx_buffers[i];
4720                 skb = txp->skb;
4721
4722                 if (skb == NULL) {
4723                         i++;
4724                         continue;
4725                 }
4726
4727                 pci_unmap_single(tp->pdev,
4728                                  pci_unmap_addr(txp, mapping),
4729                                  skb_headlen(skb),
4730                                  PCI_DMA_TODEVICE);
4731                 txp->skb = NULL;
4732
4733                 i++;
4734
4735                 for (j = 0; j < skb_shinfo(skb)->nr_frags; j++) {
4736                         txp = &tp->tx_buffers[i & (TG3_TX_RING_SIZE - 1)];
4737                         pci_unmap_page(tp->pdev,
4738                                        pci_unmap_addr(txp, mapping),
4739                                        skb_shinfo(skb)->frags[j].size,
4740                                        PCI_DMA_TODEVICE);
4741                         i++;
4742                 }
4743
4744                 dev_kfree_skb_any(skb);
4745         }
4746 }
4747
4748 /* Initialize tx/rx rings for packet processing.
4749  *
4750  * The chip has been shut down and the driver detached from
4751  * the networking, so no interrupts or new tx packets will
4752  * end up in the driver.  tp->{tx,}lock are held and thus
4753  * we may not sleep.
4754  */
4755 static int tg3_init_rings(struct tg3 *tp)
4756 {
4757         u32 i;
4758
4759         /* Free up all the SKBs. */
4760         tg3_free_rings(tp);
4761
4762         /* Zero out all descriptors. */
4763         memset(tp->rx_std, 0, TG3_RX_RING_BYTES);
4764         memset(tp->rx_jumbo, 0, TG3_RX_JUMBO_RING_BYTES);
4765         memset(tp->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
4766         memset(tp->tx_ring, 0, TG3_TX_RING_BYTES);
4767
4768         tp->rx_pkt_buf_sz = RX_PKT_BUF_SZ;
4769         if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
4770             (tp->dev->mtu > ETH_DATA_LEN))
4771                 tp->rx_pkt_buf_sz = RX_JUMBO_PKT_BUF_SZ;
4772
4773         /* Initialize invariants of the rings, we only set this
4774          * stuff once.  This works because the card does not
4775          * write into the rx buffer posting rings.
4776          */
4777         for (i = 0; i < TG3_RX_RING_SIZE; i++) {
4778                 struct tg3_rx_buffer_desc *rxd;
4779
4780                 rxd = &tp->rx_std[i];
4781                 rxd->idx_len = (tp->rx_pkt_buf_sz - tp->rx_offset - 64)
4782                         << RXD_LEN_SHIFT;
4783                 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
4784                 rxd->opaque = (RXD_OPAQUE_RING_STD |
4785                                (i << RXD_OPAQUE_INDEX_SHIFT));
4786         }
4787
4788         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
4789                 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
4790                         struct tg3_rx_buffer_desc *rxd;
4791
4792                         rxd = &tp->rx_jumbo[i];
4793                         rxd->idx_len = (RX_JUMBO_PKT_BUF_SZ - tp->rx_offset - 64)
4794                                 << RXD_LEN_SHIFT;
4795                         rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
4796                                 RXD_FLAG_JUMBO;
4797                         rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
4798                                (i << RXD_OPAQUE_INDEX_SHIFT));
4799                 }
4800         }
4801
4802         /* Now allocate fresh SKBs for each rx ring. */
4803         for (i = 0; i < tp->rx_pending; i++) {
4804                 if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_STD, -1, i) < 0) {
4805                         printk(KERN_WARNING PFX
4806                                "%s: Using a smaller RX standard ring, "
4807                                "only %d out of %d buffers were allocated "
4808                                "successfully.\n",
4809                                tp->dev->name, i, tp->rx_pending);
4810                         if (i == 0)
4811                                 return -ENOMEM;
4812                         tp->rx_pending = i;
4813                         break;
4814                 }
4815         }
4816
4817         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
4818                 for (i = 0; i < tp->rx_jumbo_pending; i++) {
4819                         if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_JUMBO,
4820                                              -1, i) < 0) {
4821                                 printk(KERN_WARNING PFX
4822                                        "%s: Using a smaller RX jumbo ring, "
4823                                        "only %d out of %d buffers were "
4824                                        "allocated successfully.\n",
4825                                        tp->dev->name, i, tp->rx_jumbo_pending);
4826                                 if (i == 0) {
4827                                         tg3_free_rings(tp);
4828                                         return -ENOMEM;
4829                                 }
4830                                 tp->rx_jumbo_pending = i;
4831                                 break;
4832                         }
4833                 }
4834         }
4835         return 0;
4836 }
4837
4838 /*
4839  * Must not be invoked with interrupt sources disabled and
4840  * the hardware shutdown down.
4841  */
4842 static void tg3_free_consistent(struct tg3 *tp)
4843 {
4844         kfree(tp->rx_std_buffers);
4845         tp->rx_std_buffers = NULL;
4846         if (tp->rx_std) {
4847                 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
4848                                     tp->rx_std, tp->rx_std_mapping);
4849                 tp->rx_std = NULL;
4850         }
4851         if (tp->rx_jumbo) {
4852                 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
4853                                     tp->rx_jumbo, tp->rx_jumbo_mapping);
4854                 tp->rx_jumbo = NULL;
4855         }
4856         if (tp->rx_rcb) {
4857                 pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
4858                                     tp->rx_rcb, tp->rx_rcb_mapping);
4859                 tp->rx_rcb = NULL;
4860         }
4861         if (tp->tx_ring) {
4862                 pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
4863                         tp->tx_ring, tp->tx_desc_mapping);
4864                 tp->tx_ring = NULL;
4865         }
4866         if (tp->hw_status) {
4867                 pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
4868                                     tp->hw_status, tp->status_mapping);
4869                 tp->hw_status = NULL;
4870         }
4871         if (tp->hw_stats) {
4872                 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
4873                                     tp->hw_stats, tp->stats_mapping);
4874                 tp->hw_stats = NULL;
4875         }
4876 }
4877
4878 /*
4879  * Must not be invoked with interrupt sources disabled and
4880  * the hardware shutdown down.  Can sleep.
4881  */
4882 static int tg3_alloc_consistent(struct tg3 *tp)
4883 {
4884         tp->rx_std_buffers = kzalloc((sizeof(struct ring_info) *
4885                                       (TG3_RX_RING_SIZE +
4886                                        TG3_RX_JUMBO_RING_SIZE)) +
4887                                      (sizeof(struct tx_ring_info) *
4888                                       TG3_TX_RING_SIZE),
4889                                      GFP_KERNEL);
4890         if (!tp->rx_std_buffers)
4891                 return -ENOMEM;
4892
4893         tp->rx_jumbo_buffers = &tp->rx_std_buffers[TG3_RX_RING_SIZE];
4894         tp->tx_buffers = (struct tx_ring_info *)
4895                 &tp->rx_jumbo_buffers[TG3_RX_JUMBO_RING_SIZE];
4896
4897         tp->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
4898                                           &tp->rx_std_mapping);
4899         if (!tp->rx_std)
4900                 goto err_out;
4901
4902         tp->rx_jumbo = pci_alloc_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
4903                                             &tp->rx_jumbo_mapping);
4904
4905         if (!tp->rx_jumbo)
4906                 goto err_out;
4907
4908         tp->rx_rcb = pci_alloc_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
4909                                           &tp->rx_rcb_mapping);
4910         if (!tp->rx_rcb)
4911                 goto err_out;
4912
4913         tp->tx_ring = pci_alloc_consistent(tp->pdev, TG3_TX_RING_BYTES,
4914                                            &tp->tx_desc_mapping);
4915         if (!tp->tx_ring)
4916                 goto err_out;
4917
4918         tp->hw_status = pci_alloc_consistent(tp->pdev,
4919                                              TG3_HW_STATUS_SIZE,
4920                                              &tp->status_mapping);
4921         if (!tp->hw_status)
4922                 goto err_out;
4923
4924         tp->hw_stats = pci_alloc_consistent(tp->pdev,
4925                                             sizeof(struct tg3_hw_stats),
4926                                             &tp->stats_mapping);
4927         if (!tp->hw_stats)
4928                 goto err_out;
4929
4930         memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
4931         memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
4932
4933         return 0;
4934
4935 err_out:
4936         tg3_free_consistent(tp);
4937         return -ENOMEM;
4938 }
4939
4940 #define MAX_WAIT_CNT 1000
4941
4942 /* To stop a block, clear the enable bit and poll till it
4943  * clears.  tp->lock is held.
4944  */
4945 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
4946 {
4947         unsigned int i;
4948         u32 val;
4949
4950         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
4951                 switch (ofs) {
4952                 case RCVLSC_MODE:
4953                 case DMAC_MODE:
4954                 case MBFREE_MODE:
4955                 case BUFMGR_MODE:
4956                 case MEMARB_MODE:
4957                         /* We can't enable/disable these bits of the
4958                          * 5705/5750, just say success.
4959                          */
4960                         return 0;
4961
4962                 default:
4963                         break;
4964                 }
4965         }
4966
4967         val = tr32(ofs);
4968         val &= ~enable_bit;
4969         tw32_f(ofs, val);
4970
4971         for (i = 0; i < MAX_WAIT_CNT; i++) {
4972                 udelay(100);
4973                 val = tr32(ofs);
4974                 if ((val & enable_bit) == 0)
4975                         break;
4976         }
4977
4978         if (i == MAX_WAIT_CNT && !silent) {
4979                 printk(KERN_ERR PFX "tg3_stop_block timed out, "
4980                        "ofs=%lx enable_bit=%x\n",
4981                        ofs, enable_bit);
4982                 return -ENODEV;
4983         }
4984
4985         return 0;
4986 }
4987
4988 /* tp->lock is held. */
4989 static int tg3_abort_hw(struct tg3 *tp, int silent)
4990 {
4991         int i, err;
4992
4993         tg3_disable_ints(tp);
4994
4995         tp->rx_mode &= ~RX_MODE_ENABLE;
4996         tw32_f(MAC_RX_MODE, tp->rx_mode);
4997         udelay(10);
4998
4999         err  = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
5000         err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
5001         err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
5002         err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
5003         err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
5004         err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
5005
5006         err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
5007         err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
5008         err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
5009         err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
5010         err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
5011         err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
5012         err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
5013
5014         tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
5015         tw32_f(MAC_MODE, tp->mac_mode);
5016         udelay(40);
5017
5018         tp->tx_mode &= ~TX_MODE_ENABLE;
5019         tw32_f(MAC_TX_MODE, tp->tx_mode);
5020
5021         for (i = 0; i < MAX_WAIT_CNT; i++) {
5022                 udelay(100);
5023                 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
5024                         break;
5025         }
5026         if (i >= MAX_WAIT_CNT) {
5027                 printk(KERN_ERR PFX "tg3_abort_hw timed out for %s, "
5028                        "TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n",
5029                        tp->dev->name, tr32(MAC_TX_MODE));
5030                 err |= -ENODEV;
5031         }
5032
5033         err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
5034         err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
5035         err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
5036
5037         tw32(FTQ_RESET, 0xffffffff);
5038         tw32(FTQ_RESET, 0x00000000);
5039
5040         err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
5041         err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
5042
5043         if (tp->hw_status)
5044                 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
5045         if (tp->hw_stats)
5046                 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
5047
5048         return err;
5049 }
5050
5051 /* tp->lock is held. */
5052 static int tg3_nvram_lock(struct tg3 *tp)
5053 {
5054         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
5055                 int i;
5056
5057                 if (tp->nvram_lock_cnt == 0) {
5058                         tw32(NVRAM_SWARB, SWARB_REQ_SET1);
5059                         for (i = 0; i < 8000; i++) {
5060                                 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
5061                                         break;
5062                                 udelay(20);
5063                         }
5064                         if (i == 8000) {
5065                                 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
5066                                 return -ENODEV;
5067                         }
5068                 }
5069                 tp->nvram_lock_cnt++;
5070         }
5071         return 0;
5072 }
5073
5074 /* tp->lock is held. */
5075 static void tg3_nvram_unlock(struct tg3 *tp)
5076 {
5077         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
5078                 if (tp->nvram_lock_cnt > 0)
5079                         tp->nvram_lock_cnt--;
5080                 if (tp->nvram_lock_cnt == 0)
5081                         tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
5082         }
5083 }
5084
5085 /* tp->lock is held. */
5086 static void tg3_enable_nvram_access(struct tg3 *tp)
5087 {
5088         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
5089             !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
5090                 u32 nvaccess = tr32(NVRAM_ACCESS);
5091
5092                 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
5093         }
5094 }
5095
5096 /* tp->lock is held. */
5097 static void tg3_disable_nvram_access(struct tg3 *tp)
5098 {
5099         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
5100             !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
5101                 u32 nvaccess = tr32(NVRAM_ACCESS);
5102
5103                 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
5104         }
5105 }
5106
5107 static void tg3_ape_send_event(struct tg3 *tp, u32 event)
5108 {
5109         int i;
5110         u32 apedata;
5111
5112         apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
5113         if (apedata != APE_SEG_SIG_MAGIC)
5114                 return;
5115
5116         apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
5117         if (apedata != APE_FW_STATUS_READY)
5118                 return;
5119
5120         /* Wait for up to 1 millisecond for APE to service previous event. */
5121         for (i = 0; i < 10; i++) {
5122                 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
5123                         return;
5124
5125                 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
5126
5127                 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
5128                         tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
5129                                         event | APE_EVENT_STATUS_EVENT_PENDING);
5130
5131                 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
5132
5133                 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
5134                         break;
5135
5136                 udelay(100);
5137         }
5138
5139         if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
5140                 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
5141 }
5142
5143 static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
5144 {
5145         u32 event;
5146         u32 apedata;
5147
5148         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
5149                 return;
5150
5151         switch (kind) {
5152                 case RESET_KIND_INIT:
5153                         tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
5154                                         APE_HOST_SEG_SIG_MAGIC);
5155                         tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
5156                                         APE_HOST_SEG_LEN_MAGIC);
5157                         apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
5158                         tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
5159                         tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
5160                                         APE_HOST_DRIVER_ID_MAGIC);
5161                         tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
5162                                         APE_HOST_BEHAV_NO_PHYLOCK);
5163
5164                         event = APE_EVENT_STATUS_STATE_START;
5165                         break;
5166                 case RESET_KIND_SHUTDOWN:
5167                         event = APE_EVENT_STATUS_STATE_UNLOAD;
5168                         break;
5169                 case RESET_KIND_SUSPEND:
5170                         event = APE_EVENT_STATUS_STATE_SUSPEND;
5171                         break;
5172                 default:
5173                         return;
5174         }
5175
5176         event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
5177
5178         tg3_ape_send_event(tp, event);
5179 }
5180
5181 /* tp->lock is held. */
5182 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
5183 {
5184         tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
5185                       NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
5186
5187         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
5188                 switch (kind) {
5189                 case RESET_KIND_INIT:
5190                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5191                                       DRV_STATE_START);
5192                         break;
5193
5194                 case RESET_KIND_SHUTDOWN:
5195                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5196                                       DRV_STATE_UNLOAD);
5197                         break;
5198
5199                 case RESET_KIND_SUSPEND:
5200                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5201                                       DRV_STATE_SUSPEND);
5202                         break;
5203
5204                 default:
5205                         break;
5206                 }
5207         }
5208
5209         if (kind == RESET_KIND_INIT ||
5210             kind == RESET_KIND_SUSPEND)
5211                 tg3_ape_driver_state_change(tp, kind);
5212 }
5213
5214 /* tp->lock is held. */
5215 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
5216 {
5217         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
5218                 switch (kind) {
5219                 case RESET_KIND_INIT:
5220                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5221                                       DRV_STATE_START_DONE);
5222                         break;
5223
5224                 case RESET_KIND_SHUTDOWN:
5225                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5226                                       DRV_STATE_UNLOAD_DONE);
5227                         break;
5228
5229                 default:
5230                         break;
5231                 }
5232         }
5233
5234         if (kind == RESET_KIND_SHUTDOWN)
5235                 tg3_ape_driver_state_change(tp, kind);
5236 }
5237
5238 /* tp->lock is held. */
5239 static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
5240 {
5241         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
5242                 switch (kind) {
5243                 case RESET_KIND_INIT:
5244                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5245                                       DRV_STATE_START);
5246                         break;
5247
5248                 case RESET_KIND_SHUTDOWN:
5249                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5250                                       DRV_STATE_UNLOAD);
5251                         break;
5252
5253                 case RESET_KIND_SUSPEND:
5254                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5255                                       DRV_STATE_SUSPEND);
5256                         break;
5257
5258                 default:
5259                         break;
5260                 }
5261         }
5262 }
5263
5264 static int tg3_poll_fw(struct tg3 *tp)
5265 {
5266         int i;
5267         u32 val;
5268
5269         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
5270                 /* Wait up to 20ms for init done. */
5271                 for (i = 0; i < 200; i++) {
5272                         if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
5273                                 return 0;
5274                         udelay(100);
5275                 }
5276                 return -ENODEV;
5277         }
5278
5279         /* Wait for firmware initialization to complete. */
5280         for (i = 0; i < 100000; i++) {
5281                 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
5282                 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
5283                         break;
5284                 udelay(10);
5285         }
5286
5287         /* Chip might not be fitted with firmware.  Some Sun onboard
5288          * parts are configured like that.  So don't signal the timeout
5289          * of the above loop as an error, but do report the lack of
5290          * running firmware once.
5291          */
5292         if (i >= 100000 &&
5293             !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
5294                 tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
5295
5296                 printk(KERN_INFO PFX "%s: No firmware running.\n",
5297                        tp->dev->name);
5298         }
5299
5300         return 0;
5301 }
5302
5303 /* Save PCI command register before chip reset */
5304 static void tg3_save_pci_state(struct tg3 *tp)
5305 {
5306         pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
5307 }
5308
5309 /* Restore PCI state after chip reset */
5310 static void tg3_restore_pci_state(struct tg3 *tp)
5311 {
5312         u32 val;
5313
5314         /* Re-enable indirect register accesses. */
5315         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
5316                                tp->misc_host_ctrl);
5317
5318         /* Set MAX PCI retry to zero. */
5319         val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
5320         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
5321             (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
5322                 val |= PCISTATE_RETRY_SAME_DMA;
5323         /* Allow reads and writes to the APE register and memory space. */
5324         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
5325                 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
5326                        PCISTATE_ALLOW_APE_SHMEM_WR;
5327         pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
5328
5329         pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
5330
5331         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
5332                 pcie_set_readrq(tp->pdev, 4096);
5333         else {
5334                 pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
5335                                       tp->pci_cacheline_sz);
5336                 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
5337                                       tp->pci_lat_timer);
5338         }
5339
5340         /* Make sure PCI-X relaxed ordering bit is clear. */
5341         if (tp->pcix_cap) {
5342                 u16 pcix_cmd;
5343
5344                 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
5345                                      &pcix_cmd);
5346                 pcix_cmd &= ~PCI_X_CMD_ERO;
5347                 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
5348                                       pcix_cmd);
5349         }
5350
5351         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
5352
5353                 /* Chip reset on 5780 will reset MSI enable bit,
5354                  * so need to restore it.
5355                  */
5356                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
5357                         u16 ctrl;
5358
5359                         pci_read_config_word(tp->pdev,
5360                                              tp->msi_cap + PCI_MSI_FLAGS,
5361                                              &ctrl);
5362                         pci_write_config_word(tp->pdev,
5363                                               tp->msi_cap + PCI_MSI_FLAGS,
5364                                               ctrl | PCI_MSI_FLAGS_ENABLE);
5365                         val = tr32(MSGINT_MODE);
5366                         tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
5367                 }
5368         }
5369 }
5370
5371 static void tg3_stop_fw(struct tg3 *);
5372
5373 /* tp->lock is held. */
5374 static int tg3_chip_reset(struct tg3 *tp)
5375 {
5376         u32 val;
5377         void (*write_op)(struct tg3 *, u32, u32);
5378         int err;
5379
5380         tg3_nvram_lock(tp);
5381
5382         /* No matching tg3_nvram_unlock() after this because
5383          * chip reset below will undo the nvram lock.
5384          */
5385         tp->nvram_lock_cnt = 0;
5386
5387         /* GRC_MISC_CFG core clock reset will clear the memory
5388          * enable bit in PCI register 4 and the MSI enable bit
5389          * on some chips, so we save relevant registers here.
5390          */
5391         tg3_save_pci_state(tp);
5392
5393         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
5394             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
5395             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
5396             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
5397             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
5398                 tw32(GRC_FASTBOOT_PC, 0);
5399
5400         /*
5401          * We must avoid the readl() that normally takes place.
5402          * It locks machines, causes machine checks, and other
5403          * fun things.  So, temporarily disable the 5701
5404          * hardware workaround, while we do the reset.
5405          */
5406         write_op = tp->write32;
5407         if (write_op == tg3_write_flush_reg32)
5408                 tp->write32 = tg3_write32;
5409
5410         /* Prevent the irq handler from reading or writing PCI registers
5411          * during chip reset when the memory enable bit in the PCI command
5412          * register may be cleared.  The chip does not generate interrupt
5413          * at this time, but the irq handler may still be called due to irq
5414          * sharing or irqpoll.
5415          */
5416         tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING;
5417         if (tp->hw_status) {
5418                 tp->hw_status->status = 0;
5419                 tp->hw_status->status_tag = 0;
5420         }
5421         tp->last_tag = 0;
5422         smp_mb();
5423         synchronize_irq(tp->pdev->irq);
5424
5425         /* do the reset */
5426         val = GRC_MISC_CFG_CORECLK_RESET;
5427
5428         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
5429                 if (tr32(0x7e2c) == 0x60) {
5430                         tw32(0x7e2c, 0x20);
5431                 }
5432                 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
5433                         tw32(GRC_MISC_CFG, (1 << 29));
5434                         val |= (1 << 29);
5435                 }
5436         }
5437
5438         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
5439                 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
5440                 tw32(GRC_VCPU_EXT_CTRL,
5441                      tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
5442         }
5443
5444         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
5445                 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
5446         tw32(GRC_MISC_CFG, val);
5447
5448         /* restore 5701 hardware bug workaround write method */
5449         tp->write32 = write_op;
5450
5451         /* Unfortunately, we have to delay before the PCI read back.
5452          * Some 575X chips even will not respond to a PCI cfg access
5453          * when the reset command is given to the chip.
5454          *
5455          * How do these hardware designers expect things to work
5456          * properly if the PCI write is posted for a long period
5457          * of time?  It is always necessary to have some method by
5458          * which a register read back can occur to push the write
5459          * out which does the reset.
5460          *
5461          * For most tg3 variants the trick below was working.
5462          * Ho hum...
5463          */
5464         udelay(120);
5465
5466         /* Flush PCI posted writes.  The normal MMIO registers
5467          * are inaccessible at this time so this is the only
5468          * way to make this reliably (actually, this is no longer
5469          * the case, see above).  I tried to use indirect
5470          * register read/write but this upset some 5701 variants.
5471          */
5472         pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
5473
5474         udelay(120);
5475
5476         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
5477                 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
5478                         int i;
5479                         u32 cfg_val;
5480
5481                         /* Wait for link training to complete.  */
5482                         for (i = 0; i < 5000; i++)
5483                                 udelay(100);
5484
5485                         pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
5486                         pci_write_config_dword(tp->pdev, 0xc4,
5487                                                cfg_val | (1 << 15));
5488                 }
5489                 /* Set PCIE max payload size and clear error status.  */
5490                 pci_write_config_dword(tp->pdev, 0xd8, 0xf5000);
5491         }
5492
5493         tg3_restore_pci_state(tp);
5494
5495         tp->tg3_flags &= ~TG3_FLAG_CHIP_RESETTING;
5496
5497         val = 0;
5498         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
5499                 val = tr32(MEMARB_MODE);
5500         tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
5501
5502         if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
5503                 tg3_stop_fw(tp);
5504                 tw32(0x5000, 0x400);
5505         }
5506
5507         tw32(GRC_MODE, tp->grc_mode);
5508
5509         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
5510                 val = tr32(0xc4);
5511
5512                 tw32(0xc4, val | (1 << 15));
5513         }
5514
5515         if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
5516             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
5517                 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
5518                 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
5519                         tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
5520                 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
5521         }
5522
5523         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
5524                 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
5525                 tw32_f(MAC_MODE, tp->mac_mode);
5526         } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
5527                 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
5528                 tw32_f(MAC_MODE, tp->mac_mode);
5529         } else
5530                 tw32_f(MAC_MODE, 0);
5531         udelay(40);
5532
5533         err = tg3_poll_fw(tp);
5534         if (err)
5535                 return err;
5536
5537         if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
5538             tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
5539                 val = tr32(0x7c00);
5540
5541                 tw32(0x7c00, val | (1 << 25));
5542         }
5543
5544         /* Reprobe ASF enable state.  */
5545         tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
5546         tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
5547         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
5548         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
5549                 u32 nic_cfg;
5550
5551                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
5552                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
5553                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
5554                         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
5555                                 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
5556                 }
5557         }
5558
5559         return 0;
5560 }
5561
5562 /* tp->lock is held. */
5563 static void tg3_stop_fw(struct tg3 *tp)
5564 {
5565         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
5566            !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
5567                 u32 val;
5568
5569                 /* Wait for RX cpu to ACK the previous event. */
5570                 tg3_wait_for_event_ack(tp);
5571
5572                 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
5573                 val = tr32(GRC_RX_CPU_EVENT);
5574                 val |= GRC_RX_CPU_DRIVER_EVENT;
5575                 tw32(GRC_RX_CPU_EVENT, val);
5576
5577                 /* Wait for RX cpu to ACK this event. */
5578                 tg3_wait_for_event_ack(tp);
5579         }
5580 }
5581
5582 /* tp->lock is held. */
5583 static int tg3_halt(struct tg3 *tp, int kind, int silent)
5584 {
5585         int err;
5586
5587         tg3_stop_fw(tp);
5588
5589         tg3_write_sig_pre_reset(tp, kind);
5590
5591         tg3_abort_hw(tp, silent);
5592         err = tg3_chip_reset(tp);
5593
5594         tg3_write_sig_legacy(tp, kind);
5595         tg3_write_sig_post_reset(tp, kind);
5596
5597         if (err)
5598                 return err;
5599
5600         return 0;
5601 }
5602
5603 #define TG3_FW_RELEASE_MAJOR    0x0
5604 #define TG3_FW_RELASE_MINOR     0x0
5605 #define TG3_FW_RELEASE_FIX      0x0
5606 #define TG3_FW_START_ADDR       0x08000000
5607 #define TG3_FW_TEXT_ADDR        0x08000000
5608 #define TG3_FW_TEXT_LEN         0x9c0
5609 #define TG3_FW_RODATA_ADDR      0x080009c0
5610 #define TG3_FW_RODATA_LEN       0x60
5611 #define TG3_FW_DATA_ADDR        0x08000a40
5612 #define TG3_FW_DATA_LEN         0x20
5613 #define TG3_FW_SBSS_ADDR        0x08000a60
5614 #define TG3_FW_SBSS_LEN         0xc
5615 #define TG3_FW_BSS_ADDR         0x08000a70
5616 #define TG3_FW_BSS_LEN          0x10
5617
5618 static const u32 tg3FwText[(TG3_FW_TEXT_LEN / sizeof(u32)) + 1] = {
5619         0x00000000, 0x10000003, 0x00000000, 0x0000000d, 0x0000000d, 0x3c1d0800,
5620         0x37bd3ffc, 0x03a0f021, 0x3c100800, 0x26100000, 0x0e000018, 0x00000000,
5621         0x0000000d, 0x3c1d0800, 0x37bd3ffc, 0x03a0f021, 0x3c100800, 0x26100034,
5622         0x0e00021c, 0x00000000, 0x0000000d, 0x00000000, 0x00000000, 0x00000000,
5623         0x27bdffe0, 0x3c1cc000, 0xafbf0018, 0xaf80680c, 0x0e00004c, 0x241b2105,
5624         0x97850000, 0x97870002, 0x9782002c, 0x9783002e, 0x3c040800, 0x248409c0,
5625         0xafa00014, 0x00021400, 0x00621825, 0x00052c00, 0xafa30010, 0x8f860010,
5626         0x00e52825, 0x0e000060, 0x24070102, 0x3c02ac00, 0x34420100, 0x3c03ac01,
5627         0x34630100, 0xaf820490, 0x3c02ffff, 0xaf820494, 0xaf830498, 0xaf82049c,
5628         0x24020001, 0xaf825ce0, 0x0e00003f, 0xaf825d00, 0x0e000140, 0x00000000,
5629         0x8fbf0018, 0x03e00008, 0x27bd0020, 0x2402ffff, 0xaf825404, 0x8f835400,
5630         0x34630400, 0xaf835400, 0xaf825404, 0x3c020800, 0x24420034, 0xaf82541c,
5631         0x03e00008, 0xaf805400, 0x00000000, 0x00000000, 0x3c020800, 0x34423000,
5632         0x3c030800, 0x34633000, 0x3c040800, 0x348437ff, 0x3c010800, 0xac220a64,
5633         0x24020040, 0x3c010800, 0xac220a68, 0x3c010800, 0xac200a60, 0xac600000,
5634         0x24630004, 0x0083102b, 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000,
5635         0x00804821, 0x8faa0010, 0x3c020800, 0x8c420a60, 0x3c040800, 0x8c840a68,
5636         0x8fab0014, 0x24430001, 0x0044102b, 0x3c010800, 0xac230a60, 0x14400003,
5637         0x00004021, 0x3c010800, 0xac200a60, 0x3c020800, 0x8c420a60, 0x3c030800,
5638         0x8c630a64, 0x91240000, 0x00021140, 0x00431021, 0x00481021, 0x25080001,
5639         0xa0440000, 0x29020008, 0x1440fff4, 0x25290001, 0x3c020800, 0x8c420a60,
5640         0x3c030800, 0x8c630a64, 0x8f84680c, 0x00021140, 0x00431021, 0xac440008,
5641         0xac45000c, 0xac460010, 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c,
5642         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5643         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5644         0, 0, 0, 0, 0, 0,
5645         0x02000008, 0x00000000, 0x0a0001e3, 0x3c0a0001, 0x0a0001e3, 0x3c0a0002,
5646         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5647         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5648         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5649         0x0a0001e3, 0x3c0a0007, 0x0a0001e3, 0x3c0a0008, 0x0a0001e3, 0x3c0a0009,
5650         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a000b,
5651         0x0a0001e3, 0x3c0a000c, 0x0a0001e3, 0x3c0a000d, 0x0a0001e3, 0x00000000,
5652         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a000e, 0x0a0001e3, 0x00000000,
5653         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5654         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5655         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a0013, 0x0a0001e3, 0x3c0a0014,
5656         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5657         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5658         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5659         0x27bdffe0, 0x00001821, 0x00001021, 0xafbf0018, 0xafb10014, 0xafb00010,
5660         0x3c010800, 0x00220821, 0xac200a70, 0x3c010800, 0x00220821, 0xac200a74,
5661         0x3c010800, 0x00220821, 0xac200a78, 0x24630001, 0x1860fff5, 0x2442000c,
5662         0x24110001, 0x8f906810, 0x32020004, 0x14400005, 0x24040001, 0x3c020800,
5663         0x8c420a78, 0x18400003, 0x00002021, 0x0e000182, 0x00000000, 0x32020001,
5664         0x10400003, 0x00000000, 0x0e000169, 0x00000000, 0x0a000153, 0xaf915028,
5665         0x8fbf0018, 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0020, 0x3c050800,
5666         0x8ca50a70, 0x3c060800, 0x8cc60a80, 0x3c070800, 0x8ce70a78, 0x27bdffe0,
5667         0x3c040800, 0x248409d0, 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014,
5668         0x0e00017b, 0x00002021, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x24020001,
5669         0x8f836810, 0x00821004, 0x00021027, 0x00621824, 0x03e00008, 0xaf836810,
5670         0x27bdffd8, 0xafbf0024, 0x1080002e, 0xafb00020, 0x8f825cec, 0xafa20018,
5671         0x8f825cec, 0x3c100800, 0x26100a78, 0xafa2001c, 0x34028000, 0xaf825cec,
5672         0x8e020000, 0x18400016, 0x00000000, 0x3c020800, 0x94420a74, 0x8fa3001c,
5673         0x000221c0, 0xac830004, 0x8fa2001c, 0x3c010800, 0x0e000201, 0xac220a74,
5674         0x10400005, 0x00000000, 0x8e020000, 0x24420001, 0x0a0001df, 0xae020000,
5675         0x3c020800, 0x8c420a70, 0x00021c02, 0x000321c0, 0x0a0001c5, 0xafa2001c,
5676         0x0e000201, 0x00000000, 0x1040001f, 0x00000000, 0x8e020000, 0x8fa3001c,
5677         0x24420001, 0x3c010800, 0xac230a70, 0x3c010800, 0xac230a74, 0x0a0001df,
5678         0xae020000, 0x3c100800, 0x26100a78, 0x8e020000, 0x18400028, 0x00000000,
5679         0x0e000201, 0x00000000, 0x14400024, 0x00000000, 0x8e020000, 0x3c030800,
5680         0x8c630a70, 0x2442ffff, 0xafa3001c, 0x18400006, 0xae020000, 0x00031402,
5681         0x000221c0, 0x8c820004, 0x3c010800, 0xac220a70, 0x97a2001e, 0x2442ff00,
5682         0x2c420300, 0x1440000b, 0x24024000, 0x3c040800, 0x248409dc, 0xafa00010,
5683         0xafa00014, 0x8fa6001c, 0x24050008, 0x0e000060, 0x00003821, 0x0a0001df,
5684         0x00000000, 0xaf825cf8, 0x3c020800, 0x8c420a40, 0x8fa3001c, 0x24420001,
5685         0xaf835cf8, 0x3c010800, 0xac220a40, 0x8fbf0024, 0x8fb00020, 0x03e00008,
5686         0x27bd0028, 0x27bdffe0, 0x3c040800, 0x248409e8, 0x00002821, 0x00003021,
5687         0x00003821, 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014, 0x8fbf0018,
5688         0x03e00008, 0x27bd0020, 0x8f82680c, 0x8f85680c, 0x00021827, 0x0003182b,
5689         0x00031823, 0x00431024, 0x00441021, 0x00a2282b, 0x10a00006, 0x00000000,
5690         0x00401821, 0x8f82680c, 0x0043102b, 0x1440fffd, 0x00000000, 0x03e00008,
5691         0x00000000, 0x3c040800, 0x8c840000, 0x3c030800, 0x8c630a40, 0x0064102b,
5692         0x54400002, 0x00831023, 0x00641023, 0x2c420008, 0x03e00008, 0x38420001,
5693         0x27bdffe0, 0x00802821, 0x3c040800, 0x24840a00, 0x00003021, 0x00003821,
5694         0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014, 0x0a000216, 0x00000000,
5695         0x8fbf0018, 0x03e00008, 0x27bd0020, 0x00000000, 0x27bdffe0, 0x3c1cc000,
5696         0xafbf0018, 0x0e00004c, 0xaf80680c, 0x3c040800, 0x24840a10, 0x03802821,
5697         0x00003021, 0x00003821, 0xafa00010, 0x0e000060, 0xafa00014, 0x2402ffff,
5698         0xaf825404, 0x3c0200aa, 0x0e000234, 0xaf825434, 0x8fbf0018, 0x03e00008,
5699         0x27bd0020, 0x00000000, 0x00000000, 0x00000000, 0x27bdffe8, 0xafb00010,
5700         0x24100001, 0xafbf0014, 0x3c01c003, 0xac200000, 0x8f826810, 0x30422000,
5701         0x10400003, 0x00000000, 0x0e000246, 0x00000000, 0x0a00023a, 0xaf905428,
5702         0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x27bdfff8, 0x8f845d0c,
5703         0x3c0200ff, 0x3c030800, 0x8c630a50, 0x3442fff8, 0x00821024, 0x1043001e,
5704         0x3c0500ff, 0x34a5fff8, 0x3c06c003, 0x3c074000, 0x00851824, 0x8c620010,
5705         0x3c010800, 0xac230a50, 0x30420008, 0x10400005, 0x00871025, 0x8cc20000,
5706         0x24420001, 0xacc20000, 0x00871025, 0xaf825d0c, 0x8fa20000, 0x24420001,
5707         0xafa20000, 0x8fa20000, 0x8fa20000, 0x24420001, 0xafa20000, 0x8fa20000,
5708         0x8f845d0c, 0x3c030800, 0x8c630a50, 0x00851024, 0x1443ffe8, 0x00851824,
5709         0x27bd0008, 0x03e00008, 0x00000000, 0x00000000, 0x00000000
5710 };
5711
5712 static const u32 tg3FwRodata[(TG3_FW_RODATA_LEN / sizeof(u32)) + 1] = {
5713         0x35373031, 0x726c7341, 0x00000000, 0x00000000, 0x53774576, 0x656e7430,
5714         0x00000000, 0x726c7045, 0x76656e74, 0x31000000, 0x556e6b6e, 0x45766e74,
5715         0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x66617461, 0x6c457272,
5716         0x00000000, 0x00000000, 0x4d61696e, 0x43707542, 0x00000000, 0x00000000,
5717         0x00000000
5718 };
5719
5720 #if 0 /* All zeros, don't eat up space with it. */
5721 u32 tg3FwData[(TG3_FW_DATA_LEN / sizeof(u32)) + 1] = {
5722         0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
5723         0x00000000, 0x00000000, 0x00000000, 0x00000000
5724 };
5725 #endif
5726
5727 #define RX_CPU_SCRATCH_BASE     0x30000
5728 #define RX_CPU_SCRATCH_SIZE     0x04000
5729 #define TX_CPU_SCRATCH_BASE     0x34000
5730 #define TX_CPU_SCRATCH_SIZE     0x04000
5731
5732 /* tp->lock is held. */
5733 static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
5734 {
5735         int i;
5736
5737         BUG_ON(offset == TX_CPU_BASE &&
5738             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
5739
5740         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
5741                 u32 val = tr32(GRC_VCPU_EXT_CTRL);
5742
5743                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
5744                 return 0;
5745         }
5746         if (offset == RX_CPU_BASE) {
5747                 for (i = 0; i < 10000; i++) {
5748                         tw32(offset + CPU_STATE, 0xffffffff);
5749                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
5750                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
5751                                 break;
5752                 }
5753
5754                 tw32(offset + CPU_STATE, 0xffffffff);
5755                 tw32_f(offset + CPU_MODE,  CPU_MODE_HALT);
5756                 udelay(10);
5757         } else {
5758                 for (i = 0; i < 10000; i++) {
5759                         tw32(offset + CPU_STATE, 0xffffffff);
5760                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
5761                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
5762                                 break;
5763                 }
5764         }
5765
5766         if (i >= 10000) {
5767                 printk(KERN_ERR PFX "tg3_reset_cpu timed out for %s, "
5768                        "and %s CPU\n",
5769                        tp->dev->name,
5770                        (offset == RX_CPU_BASE ? "RX" : "TX"));
5771                 return -ENODEV;
5772         }
5773
5774         /* Clear firmware's nvram arbitration. */
5775         if (tp->tg3_flags & TG3_FLAG_NVRAM)
5776                 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
5777         return 0;
5778 }
5779
5780 struct fw_info {
5781         unsigned int text_base;
5782         unsigned int text_len;
5783         const u32 *text_data;
5784         unsigned int rodata_base;
5785         unsigned int rodata_len;
5786         const u32 *rodata_data;
5787         unsigned int data_base;
5788         unsigned int data_len;
5789         const u32 *data_data;
5790 };
5791
5792 /* tp->lock is held. */
5793 static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
5794                                  int cpu_scratch_size, struct fw_info *info)
5795 {
5796         int err, lock_err, i;
5797         void (*write_op)(struct tg3 *, u32, u32);
5798
5799         if (cpu_base == TX_CPU_BASE &&
5800             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5801                 printk(KERN_ERR PFX "tg3_load_firmware_cpu: Trying to load "
5802                        "TX cpu firmware on %s which is 5705.\n",
5803                        tp->dev->name);
5804                 return -EINVAL;
5805         }
5806
5807         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
5808                 write_op = tg3_write_mem;
5809         else
5810                 write_op = tg3_write_indirect_reg32;
5811
5812         /* It is possible that bootcode is still loading at this point.
5813          * Get the nvram lock first before halting the cpu.
5814          */
5815         lock_err = tg3_nvram_lock(tp);
5816         err = tg3_halt_cpu(tp, cpu_base);
5817         if (!lock_err)
5818                 tg3_nvram_unlock(tp);
5819         if (err)
5820                 goto out;
5821
5822         for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
5823                 write_op(tp, cpu_scratch_base + i, 0);
5824         tw32(cpu_base + CPU_STATE, 0xffffffff);
5825         tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
5826         for (i = 0; i < (info->text_len / sizeof(u32)); i++)
5827                 write_op(tp, (cpu_scratch_base +
5828                               (info->text_base & 0xffff) +
5829                               (i * sizeof(u32))),
5830                          (info->text_data ?
5831                           info->text_data[i] : 0));
5832         for (i = 0; i < (info->rodata_len / sizeof(u32)); i++)
5833                 write_op(tp, (cpu_scratch_base +
5834                               (info->rodata_base & 0xffff) +
5835                               (i * sizeof(u32))),
5836                          (info->rodata_data ?
5837                           info->rodata_data[i] : 0));
5838         for (i = 0; i < (info->data_len / sizeof(u32)); i++)
5839                 write_op(tp, (cpu_scratch_base +
5840                               (info->data_base & 0xffff) +
5841                               (i * sizeof(u32))),
5842                          (info->data_data ?
5843                           info->data_data[i] : 0));
5844
5845         err = 0;
5846
5847 out:
5848         return err;
5849 }
5850
5851 /* tp->lock is held. */
5852 static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
5853 {
5854         struct fw_info info;
5855         int err, i;
5856
5857         info.text_base = TG3_FW_TEXT_ADDR;
5858         info.text_len = TG3_FW_TEXT_LEN;
5859         info.text_data = &tg3FwText[0];
5860         info.rodata_base = TG3_FW_RODATA_ADDR;
5861         info.rodata_len = TG3_FW_RODATA_LEN;
5862         info.rodata_data = &tg3FwRodata[0];
5863         info.data_base = TG3_FW_DATA_ADDR;
5864         info.data_len = TG3_FW_DATA_LEN;
5865         info.data_data = NULL;
5866
5867         err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
5868                                     RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
5869                                     &info);
5870         if (err)
5871                 return err;
5872
5873         err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
5874                                     TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
5875                                     &info);
5876         if (err)
5877                 return err;
5878
5879         /* Now startup only the RX cpu. */
5880         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
5881         tw32_f(RX_CPU_BASE + CPU_PC,    TG3_FW_TEXT_ADDR);
5882
5883         for (i = 0; i < 5; i++) {
5884                 if (tr32(RX_CPU_BASE + CPU_PC) == TG3_FW_TEXT_ADDR)
5885                         break;
5886                 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
5887                 tw32(RX_CPU_BASE + CPU_MODE,  CPU_MODE_HALT);
5888                 tw32_f(RX_CPU_BASE + CPU_PC,    TG3_FW_TEXT_ADDR);
5889                 udelay(1000);
5890         }
5891         if (i >= 5) {
5892                 printk(KERN_ERR PFX "tg3_load_firmware fails for %s "
5893                        "to set RX CPU PC, is %08x should be %08x\n",
5894                        tp->dev->name, tr32(RX_CPU_BASE + CPU_PC),
5895                        TG3_FW_TEXT_ADDR);
5896                 return -ENODEV;
5897         }
5898         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
5899         tw32_f(RX_CPU_BASE + CPU_MODE,  0x00000000);
5900
5901         return 0;
5902 }
5903
5904
5905 #define TG3_TSO_FW_RELEASE_MAJOR        0x1
5906 #define TG3_TSO_FW_RELASE_MINOR         0x6
5907 #define TG3_TSO_FW_RELEASE_FIX          0x0
5908 #define TG3_TSO_FW_START_ADDR           0x08000000
5909 #define TG3_TSO_FW_TEXT_ADDR            0x08000000
5910 #define TG3_TSO_FW_TEXT_LEN             0x1aa0
5911 #define TG3_TSO_FW_RODATA_ADDR          0x08001aa0
5912 #define TG3_TSO_FW_RODATA_LEN           0x60
5913 #define TG3_TSO_FW_DATA_ADDR            0x08001b20
5914 #define TG3_TSO_FW_DATA_LEN             0x30
5915 #define TG3_TSO_FW_SBSS_ADDR            0x08001b50
5916 #define TG3_TSO_FW_SBSS_LEN             0x2c
5917 #define TG3_TSO_FW_BSS_ADDR             0x08001b80
5918 #define TG3_TSO_FW_BSS_LEN              0x894
5919
5920 static const u32 tg3TsoFwText[(TG3_TSO_FW_TEXT_LEN / 4) + 1] = {
5921         0x0e000003, 0x00000000, 0x08001b24, 0x00000000, 0x10000003, 0x00000000,
5922         0x0000000d, 0x0000000d, 0x3c1d0800, 0x37bd4000, 0x03a0f021, 0x3c100800,
5923         0x26100000, 0x0e000010, 0x00000000, 0x0000000d, 0x27bdffe0, 0x3c04fefe,
5924         0xafbf0018, 0x0e0005d8, 0x34840002, 0x0e000668, 0x00000000, 0x3c030800,
5925         0x90631b68, 0x24020002, 0x3c040800, 0x24841aac, 0x14620003, 0x24050001,
5926         0x3c040800, 0x24841aa0, 0x24060006, 0x00003821, 0xafa00010, 0x0e00067c,
5927         0xafa00014, 0x8f625c50, 0x34420001, 0xaf625c50, 0x8f625c90, 0x34420001,
5928         0xaf625c90, 0x2402ffff, 0x0e000034, 0xaf625404, 0x8fbf0018, 0x03e00008,
5929         0x27bd0020, 0x00000000, 0x00000000, 0x00000000, 0x27bdffe0, 0xafbf001c,
5930         0xafb20018, 0xafb10014, 0x0e00005b, 0xafb00010, 0x24120002, 0x24110001,
5931         0x8f706820, 0x32020100, 0x10400003, 0x00000000, 0x0e0000bb, 0x00000000,
5932         0x8f706820, 0x32022000, 0x10400004, 0x32020001, 0x0e0001f0, 0x24040001,
5933         0x32020001, 0x10400003, 0x00000000, 0x0e0000a3, 0x00000000, 0x3c020800,
5934         0x90421b98, 0x14520003, 0x00000000, 0x0e0004c0, 0x00000000, 0x0a00003c,
5935         0xaf715028, 0x8fbf001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, 0x03e00008,
5936         0x27bd0020, 0x27bdffe0, 0x3c040800, 0x24841ac0, 0x00002821, 0x00003021,
5937         0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014, 0x3c040800,
5938         0x248423d8, 0xa4800000, 0x3c010800, 0xa0201b98, 0x3c010800, 0xac201b9c,
5939         0x3c010800, 0xac201ba0, 0x3c010800, 0xac201ba4, 0x3c010800, 0xac201bac,
5940         0x3c010800, 0xac201bb8, 0x3c010800, 0xac201bbc, 0x8f624434, 0x3c010800,
5941         0xac221b88, 0x8f624438, 0x3c010800, 0xac221b8c, 0x8f624410, 0xac80f7a8,
5942         0x3c010800, 0xac201b84, 0x3c010800, 0xac2023e0, 0x3c010800, 0xac2023c8,
5943         0x3c010800, 0xac2023cc, 0x3c010800, 0xac202400, 0x3c010800, 0xac221b90,
5944         0x8f620068, 0x24030007, 0x00021702, 0x10430005, 0x00000000, 0x8f620068,
5945         0x00021702, 0x14400004, 0x24020001, 0x3c010800, 0x0a000097, 0xac20240c,
5946         0xac820034, 0x3c040800, 0x24841acc, 0x3c050800, 0x8ca5240c, 0x00003021,
5947         0x00003821, 0xafa00010, 0x0e00067c, 0xafa00014, 0x8fbf0018, 0x03e00008,
5948         0x27bd0020, 0x27bdffe0, 0x3c040800, 0x24841ad8, 0x00002821, 0x00003021,
5949         0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014, 0x0e00005b,
5950         0x00000000, 0x0e0000b4, 0x00002021, 0x8fbf0018, 0x03e00008, 0x27bd0020,
5951         0x24020001, 0x8f636820, 0x00821004, 0x00021027, 0x00621824, 0x03e00008,
5952         0xaf636820, 0x27bdffd0, 0xafbf002c, 0xafb60028, 0xafb50024, 0xafb40020,
5953         0xafb3001c, 0xafb20018, 0xafb10014, 0xafb00010, 0x8f675c5c, 0x3c030800,
5954         0x24631bbc, 0x8c620000, 0x14470005, 0x3c0200ff, 0x3c020800, 0x90421b98,
5955         0x14400119, 0x3c0200ff, 0x3442fff8, 0x00e28824, 0xac670000, 0x00111902,
5956         0x306300ff, 0x30e20003, 0x000211c0, 0x00622825, 0x00a04021, 0x00071602,
5957         0x3c030800, 0x90631b98, 0x3044000f, 0x14600036, 0x00804821, 0x24020001,
5958         0x3c010800, 0xa0221b98, 0x00051100, 0x00821025, 0x3c010800, 0xac201b9c,
5959         0x3c010800, 0xac201ba0, 0x3c010800, 0xac201ba4, 0x3c010800, 0xac201bac,
5960         0x3c010800, 0xac201bb8, 0x3c010800, 0xac201bb0, 0x3c010800, 0xac201bb4,
5961         0x3c010800, 0xa42223d8, 0x9622000c, 0x30437fff, 0x3c010800, 0xa4222410,
5962         0x30428000, 0x3c010800, 0xa4231bc6, 0x10400005, 0x24020001, 0x3c010800,
5963         0xac2223f4, 0x0a000102, 0x2406003e, 0x24060036, 0x3c010800, 0xac2023f4,
5964         0x9622000a, 0x3c030800, 0x94631bc6, 0x3c010800, 0xac2023f0, 0x3c010800,
5965         0xac2023f8, 0x00021302, 0x00021080, 0x00c21021, 0x00621821, 0x3c010800,
5966         0xa42223d0, 0x3c010800, 0x0a000115, 0xa4231b96, 0x9622000c, 0x3c010800,
5967         0xa42223ec, 0x3c040800, 0x24841b9c, 0x8c820000, 0x00021100, 0x3c010800,
5968         0x00220821, 0xac311bc8, 0x8c820000, 0x00021100, 0x3c010800, 0x00220821,
5969         0xac271bcc, 0x8c820000, 0x25030001, 0x306601ff, 0x00021100, 0x3c010800,
5970         0x00220821, 0xac261bd0, 0x8c820000, 0x00021100, 0x3c010800, 0x00220821,
5971         0xac291bd4, 0x96230008, 0x3c020800, 0x8c421bac, 0x00432821, 0x3c010800,
5972         0xac251bac, 0x9622000a, 0x30420004, 0x14400018, 0x00061100, 0x8f630c14,
5973         0x3063000f, 0x2c620002, 0x1440000b, 0x3c02c000, 0x8f630c14, 0x3c020800,
5974         0x8c421b40, 0x3063000f, 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002,
5975         0x1040fff7, 0x3c02c000, 0x00e21825, 0xaf635c5c, 0x8f625c50, 0x30420002,
5976         0x10400014, 0x00000000, 0x0a000147, 0x00000000, 0x3c030800, 0x8c631b80,
5977         0x3c040800, 0x94841b94, 0x01221025, 0x3c010800, 0xa42223da, 0x24020001,
5978         0x3c010800, 0xac221bb8, 0x24630001, 0x0085202a, 0x3c010800, 0x10800003,
5979         0xac231b80, 0x3c010800, 0xa4251b94, 0x3c060800, 0x24c61b9c, 0x8cc20000,
5980         0x24420001, 0xacc20000, 0x28420080, 0x14400005, 0x00000000, 0x0e000656,
5981         0x24040002, 0x0a0001e6, 0x00000000, 0x3c020800, 0x8c421bb8, 0x10400078,
5982         0x24020001, 0x3c050800, 0x90a51b98, 0x14a20072, 0x00000000, 0x3c150800,
5983         0x96b51b96, 0x3c040800, 0x8c841bac, 0x32a3ffff, 0x0083102a, 0x1440006c,
5984         0x00000000, 0x14830003, 0x00000000, 0x3c010800, 0xac2523f0, 0x1060005c,
5985         0x00009021, 0x24d60004, 0x0060a021, 0x24d30014, 0x8ec20000, 0x00028100,
5986         0x3c110800, 0x02308821, 0x0e000625, 0x8e311bc8, 0x00402821, 0x10a00054,
5987         0x00000000, 0x9628000a, 0x31020040, 0x10400005, 0x2407180c, 0x8e22000c,
5988         0x2407188c, 0x00021400, 0xaca20018, 0x3c030800, 0x00701821, 0x8c631bd0,
5989         0x3c020800, 0x00501021, 0x8c421bd4, 0x00031d00, 0x00021400, 0x00621825,
5990         0xaca30014, 0x8ec30004, 0x96220008, 0x00432023, 0x3242ffff, 0x3083ffff,
5991         0x00431021, 0x0282102a, 0x14400002, 0x02b23023, 0x00803021, 0x8e620000,
5992         0x30c4ffff, 0x00441021, 0xae620000, 0x8e220000, 0xaca20000, 0x8e220004,
5993         0x8e63fff4, 0x00431021, 0xaca20004, 0xa4a6000e, 0x8e62fff4, 0x00441021,
5994         0xae62fff4, 0x96230008, 0x0043102a, 0x14400005, 0x02469021, 0x8e62fff0,
5995         0xae60fff4, 0x24420001, 0xae62fff0, 0xaca00008, 0x3242ffff, 0x14540008,
5996         0x24020305, 0x31020080, 0x54400001, 0x34e70010, 0x24020905, 0xa4a2000c,
5997         0x0a0001cb, 0x34e70020, 0xa4a2000c, 0x3c020800, 0x8c4223f0, 0x10400003,
5998         0x3c024b65, 0x0a0001d3, 0x34427654, 0x3c02b49a, 0x344289ab, 0xaca2001c,
5999         0x30e2ffff, 0xaca20010, 0x0e0005a2, 0x00a02021, 0x3242ffff, 0x0054102b,
6000         0x1440ffa9, 0x00000000, 0x24020002, 0x3c010800, 0x0a0001e6, 0xa0221b98,
6001         0x8ec2083c, 0x24420001, 0x0a0001e6, 0xaec2083c, 0x0e0004c0, 0x00000000,
6002         0x8fbf002c, 0x8fb60028, 0x8fb50024, 0x8fb40020, 0x8fb3001c, 0x8fb20018,
6003         0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0030, 0x27bdffd0, 0xafbf0028,
6004         0xafb30024, 0xafb20020, 0xafb1001c, 0xafb00018, 0x8f725c9c, 0x3c0200ff,
6005         0x3442fff8, 0x3c070800, 0x24e71bb4, 0x02428824, 0x9623000e, 0x8ce20000,
6006         0x00431021, 0xace20000, 0x8e220010, 0x30420020, 0x14400011, 0x00809821,
6007         0x0e00063b, 0x02202021, 0x3c02c000, 0x02421825, 0xaf635c9c, 0x8f625c90,
6008         0x30420002, 0x1040011e, 0x00000000, 0xaf635c9c, 0x8f625c90, 0x30420002,
6009         0x10400119, 0x00000000, 0x0a00020d, 0x00000000, 0x8e240008, 0x8e230014,
6010         0x00041402, 0x000231c0, 0x00031502, 0x304201ff, 0x2442ffff, 0x3042007f,
6011         0x00031942, 0x30637800, 0x00021100, 0x24424000, 0x00624821, 0x9522000a,
6012         0x3084ffff, 0x30420008, 0x104000b0, 0x000429c0, 0x3c020800, 0x8c422400,
6013         0x14400024, 0x24c50008, 0x94c20014, 0x3c010800, 0xa42223d0, 0x8cc40010,
6014         0x00041402, 0x3c010800, 0xa42223d2, 0x3c010800, 0xa42423d4, 0x94c2000e,
6015         0x3083ffff, 0x00431023, 0x3c010800, 0xac222408, 0x94c2001a, 0x3c010800,
6016         0xac262400, 0x3c010800, 0xac322404, 0x3c010800, 0xac2223fc, 0x3c02c000,
6017         0x02421825, 0xaf635c9c, 0x8f625c90, 0x30420002, 0x104000e5, 0x00000000,
6018         0xaf635c9c, 0x8f625c90, 0x30420002, 0x104000e0, 0x00000000, 0x0a000246,
6019         0x00000000, 0x94c2000e, 0x3c030800, 0x946323d4, 0x00434023, 0x3103ffff,
6020         0x2c620008, 0x1040001c, 0x00000000, 0x94c20014, 0x24420028, 0x00a22821,
6021         0x00031042, 0x1840000b, 0x00002021, 0x24e60848, 0x00403821, 0x94a30000,
6022         0x8cc20000, 0x24840001, 0x00431021, 0xacc20000, 0x0087102a, 0x1440fff9,
6023         0x24a50002, 0x31020001, 0x1040001f, 0x3c024000, 0x3c040800, 0x248423fc,
6024         0xa0a00001, 0x94a30000, 0x8c820000, 0x00431021, 0x0a000285, 0xac820000,
6025         0x8f626800, 0x3c030010, 0x00431024, 0x10400009, 0x00000000, 0x94c2001a,
6026         0x3c030800, 0x8c6323fc, 0x00431021, 0x3c010800, 0xac2223fc, 0x0a000286,
6027         0x3c024000, 0x94c2001a, 0x94c4001c, 0x3c030800, 0x8c6323fc, 0x00441023,
6028         0x00621821, 0x3c010800, 0xac2323fc, 0x3c024000, 0x02421825, 0xaf635c9c,
6029         0x8f625c90, 0x30420002, 0x1440fffc, 0x00000000, 0x9522000a, 0x30420010,
6030         0x1040009b, 0x00000000, 0x3c030800, 0x946323d4, 0x3c070800, 0x24e72400,
6031         0x8ce40000, 0x8f626800, 0x24630030, 0x00832821, 0x3c030010, 0x00431024,
6032         0x1440000a, 0x00000000, 0x94a20004, 0x3c040800, 0x8c842408, 0x3c030800,
6033         0x8c6323fc, 0x00441023, 0x00621821, 0x3c010800, 0xac2323fc, 0x3c040800,
6034         0x8c8423fc, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402, 0x00822021,
6035         0x00041027, 0xa4a20006, 0x3c030800, 0x8c632404, 0x3c0200ff, 0x3442fff8,
6036         0x00628824, 0x96220008, 0x24050001, 0x24034000, 0x000231c0, 0x00801021,
6037         0xa4c2001a, 0xa4c0001c, 0xace00000, 0x3c010800, 0xac251b60, 0xaf635cb8,
6038         0x8f625cb0, 0x30420002, 0x10400003, 0x00000000, 0x3c010800, 0xac201b60,
6039         0x8e220008, 0xaf625cb8, 0x8f625cb0, 0x30420002, 0x10400003, 0x00000000,
6040         0x3c010800, 0xac201b60, 0x3c020800, 0x8c421b60, 0x1040ffec, 0x00000000,
6041         0x3c040800, 0x0e00063b, 0x8c842404, 0x0a00032a, 0x00000000, 0x3c030800,
6042         0x90631b98, 0x24020002, 0x14620003, 0x3c034b65, 0x0a0002e1, 0x00008021,
6043         0x8e22001c, 0x34637654, 0x10430002, 0x24100002, 0x24100001, 0x00c02021,
6044         0x0e000350, 0x02003021, 0x24020003, 0x3c010800, 0xa0221b98, 0x24020002,
6045         0x1202000a, 0x24020001, 0x3c030800, 0x8c6323f0, 0x10620006, 0x00000000,
6046         0x3c020800, 0x944223d8, 0x00021400, 0x0a00031f, 0xae220014, 0x3c040800,
6047         0x248423da, 0x94820000, 0x00021400, 0xae220014, 0x3c020800, 0x8c421bbc,
6048         0x3c03c000, 0x3c010800, 0xa0201b98, 0x00431025, 0xaf625c5c, 0x8f625c50,
6049         0x30420002, 0x10400009, 0x00000000, 0x2484f7e2, 0x8c820000, 0x00431025,
6050         0xaf625c5c, 0x8f625c50, 0x30420002, 0x1440fffa, 0x00000000, 0x3c020800,
6051         0x24421b84, 0x8c430000, 0x24630001, 0xac430000, 0x8f630c14, 0x3063000f,
6052         0x2c620002, 0x1440000c, 0x3c024000, 0x8f630c14, 0x3c020800, 0x8c421b40,
6053         0x3063000f, 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002, 0x1040fff7,
6054         0x00000000, 0x3c024000, 0x02421825, 0xaf635c9c, 0x8f625c90, 0x30420002,
6055         0x1440fffc, 0x00000000, 0x12600003, 0x00000000, 0x0e0004c0, 0x00000000,
6056         0x8fbf0028, 0x8fb30024, 0x8fb20020, 0x8fb1001c, 0x8fb00018, 0x03e00008,
6057         0x27bd0030, 0x8f634450, 0x3c040800, 0x24841b88, 0x8c820000, 0x00031c02,
6058         0x0043102b, 0x14400007, 0x3c038000, 0x8c840004, 0x8f624450, 0x00021c02,
6059         0x0083102b, 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024,
6060         0x1440fffd, 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3c024000,
6061         0x00822025, 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00000000,
6062         0x03e00008, 0x00000000, 0x27bdffe0, 0x00805821, 0x14c00011, 0x256e0008,
6063         0x3c020800, 0x8c4223f4, 0x10400007, 0x24020016, 0x3c010800, 0xa42223d2,
6064         0x2402002a, 0x3c010800, 0x0a000364, 0xa42223d4, 0x8d670010, 0x00071402,
6065         0x3c010800, 0xa42223d2, 0x3c010800, 0xa42723d4, 0x3c040800, 0x948423d4,
6066         0x3c030800, 0x946323d2, 0x95cf0006, 0x3c020800, 0x944223d0, 0x00832023,
6067         0x01e2c023, 0x3065ffff, 0x24a20028, 0x01c24821, 0x3082ffff, 0x14c0001a,
6068         0x01226021, 0x9582000c, 0x3042003f, 0x3c010800, 0xa42223d6, 0x95820004,
6069         0x95830006, 0x3c010800, 0xac2023e4, 0x3c010800, 0xac2023e8, 0x00021400,
6070         0x00431025, 0x3c010800, 0xac221bc0, 0x95220004, 0x3c010800, 0xa4221bc4,
6071         0x95230002, 0x01e51023, 0x0043102a, 0x10400010, 0x24020001, 0x3c010800,
6072         0x0a000398, 0xac2223f8, 0x3c030800, 0x8c6323e8, 0x3c020800, 0x94421bc4,
6073         0x00431021, 0xa5220004, 0x3c020800, 0x94421bc0, 0xa5820004, 0x3c020800,
6074         0x8c421bc0, 0xa5820006, 0x3c020800, 0x8c4223f0, 0x3c0d0800, 0x8dad23e4,
6075         0x3c0a0800, 0x144000e5, 0x8d4a23e8, 0x3c020800, 0x94421bc4, 0x004a1821,
6076         0x3063ffff, 0x0062182b, 0x24020002, 0x10c2000d, 0x01435023, 0x3c020800,
6077         0x944223d6, 0x30420009, 0x10400008, 0x00000000, 0x9582000c, 0x3042fff6,
6078         0xa582000c, 0x3c020800, 0x944223d6, 0x30420009, 0x01a26823, 0x3c020800,
6079         0x8c4223f8, 0x1040004a, 0x01203821, 0x3c020800, 0x944223d2, 0x00004021,
6080         0xa520000a, 0x01e21023, 0xa5220002, 0x3082ffff, 0x00021042, 0x18400008,
6081         0x00003021, 0x00401821, 0x94e20000, 0x25080001, 0x00c23021, 0x0103102a,
6082         0x1440fffb, 0x24e70002, 0x00061c02, 0x30c2ffff, 0x00623021, 0x00061402,
6083         0x00c23021, 0x00c02821, 0x00061027, 0xa522000a, 0x00003021, 0x2527000c,
6084         0x00004021, 0x94e20000, 0x25080001, 0x00c23021, 0x2d020004, 0x1440fffb,
6085         0x24e70002, 0x95220002, 0x00004021, 0x91230009, 0x00442023, 0x01803821,
6086         0x3082ffff, 0xa4e00010, 0x00621821, 0x00021042, 0x18400010, 0x00c33021,
6087         0x00404821, 0x94e20000, 0x24e70002, 0x00c23021, 0x30e2007f, 0x14400006,
6088         0x25080001, 0x8d630000, 0x3c02007f, 0x3442ff80, 0x00625824, 0x25670008,
6089         0x0109102a, 0x1440fff3, 0x00000000, 0x30820001, 0x10400005, 0x00061c02,
6090         0xa0e00001, 0x94e20000, 0x00c23021, 0x00061c02, 0x30c2ffff, 0x00623021,
6091         0x00061402, 0x00c23021, 0x0a00047d, 0x30c6ffff, 0x24020002, 0x14c20081,
6092         0x00000000, 0x3c020800, 0x8c42240c, 0x14400007, 0x00000000, 0x3c020800,
6093         0x944223d2, 0x95230002, 0x01e21023, 0x10620077, 0x00000000, 0x3c020800,
6094         0x944223d2, 0x01e21023, 0xa5220002, 0x3c020800, 0x8c42240c, 0x1040001a,
6095         0x31e3ffff, 0x8dc70010, 0x3c020800, 0x94421b96, 0x00e04021, 0x00072c02,
6096         0x00aa2021, 0x00431023, 0x00823823, 0x00072402, 0x30e2ffff, 0x00823821,
6097         0x00071027, 0xa522000a, 0x3102ffff, 0x3c040800, 0x948423d4, 0x00453023,
6098         0x00e02821, 0x00641823, 0x006d1821, 0x00c33021, 0x00061c02, 0x30c2ffff,
6099         0x0a00047d, 0x00623021, 0x01203821, 0x00004021, 0x3082ffff, 0x00021042,
6100         0x18400008, 0x00003021, 0x00401821, 0x94e20000, 0x25080001, 0x00c23021,
6101         0x0103102a, 0x1440fffb, 0x24e70002, 0x00061c02, 0x30c2ffff, 0x00623021,
6102         0x00061402, 0x00c23021, 0x00c02821, 0x00061027, 0xa522000a, 0x00003021,
6103         0x2527000c, 0x00004021, 0x94e20000, 0x25080001, 0x00c23021, 0x2d020004,
6104         0x1440fffb, 0x24e70002, 0x95220002, 0x00004021, 0x91230009, 0x00442023,
6105         0x01803821, 0x3082ffff, 0xa4e00010, 0x3c040800, 0x948423d4, 0x00621821,
6106         0x00c33021, 0x00061c02, 0x30c2ffff, 0x00623021, 0x00061c02, 0x3c020800,
6107         0x944223d0, 0x00c34821, 0x00441023, 0x00021fc2, 0x00431021, 0x00021043,
6108         0x18400010, 0x00003021, 0x00402021, 0x94e20000, 0x24e70002, 0x00c23021,
6109         0x30e2007f, 0x14400006, 0x25080001, 0x8d630000, 0x3c02007f, 0x3442ff80,
6110         0x00625824, 0x25670008, 0x0104102a, 0x1440fff3, 0x00000000, 0x3c020800,
6111         0x944223ec, 0x00c23021, 0x3122ffff, 0x00c23021, 0x00061c02, 0x30c2ffff,
6112         0x00623021, 0x00061402, 0x00c23021, 0x00c04021, 0x00061027, 0xa5820010,
6113         0xadc00014, 0x0a00049d, 0xadc00000, 0x8dc70010, 0x00e04021, 0x11400007,
6114         0x00072c02, 0x00aa3021, 0x00061402, 0x30c3ffff, 0x00433021, 0x00061402,
6115         0x00c22821, 0x00051027, 0xa522000a, 0x3c030800, 0x946323d4, 0x3102ffff,
6116         0x01e21021, 0x00433023, 0x00cd3021, 0x00061c02, 0x30c2ffff, 0x00623021,
6117         0x00061402, 0x00c23021, 0x00c04021, 0x00061027, 0xa5820010, 0x3102ffff,
6118         0x00051c00, 0x00431025, 0xadc20010, 0x3c020800, 0x8c4223f4, 0x10400005,
6119         0x2de205eb, 0x14400002, 0x25e2fff2, 0x34028870, 0xa5c20034, 0x3c030800,
6120         0x246323e8, 0x8c620000, 0x24420001, 0xac620000, 0x3c040800, 0x8c8423e4,
6121         0x3c020800, 0x8c421bc0, 0x3303ffff, 0x00832021, 0x00431821, 0x0062102b,
6122         0x3c010800, 0xac2423e4, 0x10400003, 0x2482ffff, 0x3c010800, 0xac2223e4,
6123         0x3c010800, 0xac231bc0, 0x03e00008, 0x27bd0020, 0x27bdffb8, 0x3c050800,
6124         0x24a51b96, 0xafbf0044, 0xafbe0040, 0xafb7003c, 0xafb60038, 0xafb50034,
6125         0xafb40030, 0xafb3002c, 0xafb20028, 0xafb10024, 0xafb00020, 0x94a90000,
6126         0x3c020800, 0x944223d0, 0x3c030800, 0x8c631bb0, 0x3c040800, 0x8c841bac,
6127         0x01221023, 0x0064182a, 0xa7a9001e, 0x106000be, 0xa7a20016, 0x24be0022,
6128         0x97b6001e, 0x24b3001a, 0x24b70016, 0x8fc20000, 0x14400008, 0x00000000,
6129         0x8fc2fff8, 0x97a30016, 0x8fc4fff4, 0x00431021, 0x0082202a, 0x148000b0,
6130         0x00000000, 0x97d50818, 0x32a2ffff, 0x104000a3, 0x00009021, 0x0040a021,
6131         0x00008821, 0x0e000625, 0x00000000, 0x00403021, 0x14c00007, 0x00000000,
6132         0x3c020800, 0x8c4223dc, 0x24420001, 0x3c010800, 0x0a000596, 0xac2223dc,
6133         0x3c100800, 0x02118021, 0x8e101bc8, 0x9608000a, 0x31020040, 0x10400005,
6134         0x2407180c, 0x8e02000c, 0x2407188c, 0x00021400, 0xacc20018, 0x31020080,
6135         0x54400001, 0x34e70010, 0x3c020800, 0x00511021, 0x8c421bd0, 0x3c030800,
6136         0x00711821, 0x8c631bd4, 0x00021500, 0x00031c00, 0x00431025, 0xacc20014,
6137         0x96040008, 0x3242ffff, 0x00821021, 0x0282102a, 0x14400002, 0x02b22823,
6138         0x00802821, 0x8e020000, 0x02459021, 0xacc20000, 0x8e020004, 0x00c02021,
6139         0x26310010, 0xac820004, 0x30e2ffff, 0xac800008, 0xa485000e, 0xac820010,
6140         0x24020305, 0x0e0005a2, 0xa482000c, 0x3242ffff, 0x0054102b, 0x1440ffc5,
6141         0x3242ffff, 0x0a00058e, 0x00000000, 0x8e620000, 0x8e63fffc, 0x0043102a,
6142         0x10400067, 0x00000000, 0x8e62fff0, 0x00028900, 0x3c100800, 0x02118021,
6143         0x0e000625, 0x8e101bc8, 0x00403021, 0x14c00005, 0x00000000, 0x8e62082c,
6144         0x24420001, 0x0a000596, 0xae62082c, 0x9608000a, 0x31020040, 0x10400005,
6145         0x2407180c, 0x8e02000c, 0x2407188c, 0x00021400, 0xacc20018, 0x3c020800,
6146         0x00511021, 0x8c421bd0, 0x3c030800, 0x00711821, 0x8c631bd4, 0x00021500,
6147         0x00031c00, 0x00431025, 0xacc20014, 0x8e63fff4, 0x96020008, 0x00432023,
6148         0x3242ffff, 0x3083ffff, 0x00431021, 0x02c2102a, 0x10400003, 0x00802821,
6149         0x97a9001e, 0x01322823, 0x8e620000, 0x30a4ffff, 0x00441021, 0xae620000,
6150         0xa4c5000e, 0x8e020000, 0xacc20000, 0x8e020004, 0x8e63fff4, 0x00431021,
6151         0xacc20004, 0x8e63fff4, 0x96020008, 0x00641821, 0x0062102a, 0x14400006,
6152         0x02459021, 0x8e62fff0, 0xae60fff4, 0x24420001, 0x0a000571, 0xae62fff0,
6153         0xae63fff4, 0xacc00008, 0x3242ffff, 0x10560003, 0x31020004, 0x10400006,
6154         0x24020305, 0x31020080, 0x54400001, 0x34e70010, 0x34e70020, 0x24020905,
6155         0xa4c2000c, 0x8ee30000, 0x8ee20004, 0x14620007, 0x3c02b49a, 0x8ee20860,
6156         0x54400001, 0x34e70400, 0x3c024b65, 0x0a000588, 0x34427654, 0x344289ab,
6157         0xacc2001c, 0x30e2ffff, 0xacc20010, 0x0e0005a2, 0x00c02021, 0x3242ffff,
6158         0x0056102b, 0x1440ff9b, 0x00000000, 0x8e620000, 0x8e63fffc, 0x0043102a,
6159         0x1440ff48, 0x00000000, 0x8fbf0044, 0x8fbe0040, 0x8fb7003c, 0x8fb60038,
6160         0x8fb50034, 0x8fb40030, 0x8fb3002c, 0x8fb20028, 0x8fb10024, 0x8fb00020,
6161         0x03e00008, 0x27bd0048, 0x27bdffe8, 0xafbf0014, 0xafb00010, 0x8f624450,
6162         0x8f634410, 0x0a0005b1, 0x00808021, 0x8f626820, 0x30422000, 0x10400003,
6163         0x00000000, 0x0e0001f0, 0x00002021, 0x8f624450, 0x8f634410, 0x3042ffff,
6164         0x0043102b, 0x1440fff5, 0x00000000, 0x8f630c14, 0x3063000f, 0x2c620002,
6165         0x1440000b, 0x00000000, 0x8f630c14, 0x3c020800, 0x8c421b40, 0x3063000f,
6166         0x24420001, 0x3c010800, 0xac221b40, 0x2c620002, 0x1040fff7, 0x00000000,
6167         0xaf705c18, 0x8f625c10, 0x30420002, 0x10400009, 0x00000000, 0x8f626820,
6168         0x30422000, 0x1040fff8, 0x00000000, 0x0e0001f0, 0x00002021, 0x0a0005c4,
6169         0x00000000, 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x00000000,
6170         0x00000000, 0x00000000, 0x27bdffe8, 0x3c1bc000, 0xafbf0014, 0xafb00010,
6171         0xaf60680c, 0x8f626804, 0x34420082, 0xaf626804, 0x8f634000, 0x24020b50,
6172         0x3c010800, 0xac221b54, 0x24020b78, 0x3c010800, 0xac221b64, 0x34630002,
6173         0xaf634000, 0x0e000605, 0x00808021, 0x3c010800, 0xa0221b68, 0x304200ff,
6174         0x24030002, 0x14430005, 0x00000000, 0x3c020800, 0x8c421b54, 0x0a0005f8,
6175         0xac5000c0, 0x3c020800, 0x8c421b54, 0xac5000bc, 0x8f624434, 0x8f634438,
6176         0x8f644410, 0x3c010800, 0xac221b5c, 0x3c010800, 0xac231b6c, 0x3c010800,
6177         0xac241b58, 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x3c040800,
6178         0x8c870000, 0x3c03aa55, 0x3463aa55, 0x3c06c003, 0xac830000, 0x8cc20000,
6179         0x14430007, 0x24050002, 0x3c0355aa, 0x346355aa, 0xac830000, 0x8cc20000,
6180         0x50430001, 0x24050001, 0x3c020800, 0xac470000, 0x03e00008, 0x00a01021,
6181         0x27bdfff8, 0x18800009, 0x00002821, 0x8f63680c, 0x8f62680c, 0x1043fffe,
6182         0x00000000, 0x24a50001, 0x00a4102a, 0x1440fff9, 0x00000000, 0x03e00008,
6183         0x27bd0008, 0x8f634450, 0x3c020800, 0x8c421b5c, 0x00031c02, 0x0043102b,
6184         0x14400008, 0x3c038000, 0x3c040800, 0x8c841b6c, 0x8f624450, 0x00021c02,
6185         0x0083102b, 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024,
6186         0x1440fffd, 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3082ffff,
6187         0x2442e000, 0x2c422001, 0x14400003, 0x3c024000, 0x0a000648, 0x2402ffff,
6188         0x00822025, 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00001021,
6189         0x03e00008, 0x00000000, 0x8f624450, 0x3c030800, 0x8c631b58, 0x0a000651,
6190         0x3042ffff, 0x8f624450, 0x3042ffff, 0x0043102b, 0x1440fffc, 0x00000000,
6191         0x03e00008, 0x00000000, 0x27bdffe0, 0x00802821, 0x3c040800, 0x24841af0,
6192         0x00003021, 0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014,
6193         0x0a000660, 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x00000000,
6194         0x00000000, 0x00000000, 0x3c020800, 0x34423000, 0x3c030800, 0x34633000,
6195         0x3c040800, 0x348437ff, 0x3c010800, 0xac221b74, 0x24020040, 0x3c010800,
6196         0xac221b78, 0x3c010800, 0xac201b70, 0xac600000, 0x24630004, 0x0083102b,
6197         0x5040fffd, 0xac600000, 0x03e00008, 0x00000000, 0x00804821, 0x8faa0010,
6198         0x3c020800, 0x8c421b70, 0x3c040800, 0x8c841b78, 0x8fab0014, 0x24430001,
6199         0x0044102b, 0x3c010800, 0xac231b70, 0x14400003, 0x00004021, 0x3c010800,
6200         0xac201b70, 0x3c020800, 0x8c421b70, 0x3c030800, 0x8c631b74, 0x91240000,
6201         0x00021140, 0x00431021, 0x00481021, 0x25080001, 0xa0440000, 0x29020008,
6202         0x1440fff4, 0x25290001, 0x3c020800, 0x8c421b70, 0x3c030800, 0x8c631b74,
6203         0x8f64680c, 0x00021140, 0x00431021, 0xac440008, 0xac45000c, 0xac460010,
6204         0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c, 0x00000000, 0x00000000,
6205 };
6206
6207 static const u32 tg3TsoFwRodata[] = {
6208         0x4d61696e, 0x43707542, 0x00000000, 0x4d61696e, 0x43707541, 0x00000000,
6209         0x00000000, 0x00000000, 0x73746b6f, 0x66666c64, 0x496e0000, 0x73746b6f,
6210         0x66662a2a, 0x00000000, 0x53774576, 0x656e7430, 0x00000000, 0x00000000,
6211         0x00000000, 0x00000000, 0x66617461, 0x6c457272, 0x00000000, 0x00000000,
6212         0x00000000,
6213 };
6214
6215 static const u32 tg3TsoFwData[] = {
6216         0x00000000, 0x73746b6f, 0x66666c64, 0x5f76312e, 0x362e3000, 0x00000000,
6217         0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
6218         0x00000000,
6219 };
6220
6221 /* 5705 needs a special version of the TSO firmware.  */
6222 #define TG3_TSO5_FW_RELEASE_MAJOR       0x1
6223 #define TG3_TSO5_FW_RELASE_MINOR        0x2
6224 #define TG3_TSO5_FW_RELEASE_FIX         0x0
6225 #define TG3_TSO5_FW_START_ADDR          0x00010000
6226 #define TG3_TSO5_FW_TEXT_ADDR           0x00010000
6227 #define TG3_TSO5_FW_TEXT_LEN            0xe90
6228 #define TG3_TSO5_FW_RODATA_ADDR         0x00010e90
6229 #define TG3_TSO5_FW_RODATA_LEN          0x50
6230 #define TG3_TSO5_FW_DATA_ADDR           0x00010f00
6231 #define TG3_TSO5_FW_DATA_LEN            0x20
6232 #define TG3_TSO5_FW_SBSS_ADDR           0x00010f20
6233 #define TG3_TSO5_FW_SBSS_LEN            0x28
6234 #define TG3_TSO5_FW_BSS_ADDR            0x00010f50
6235 #define TG3_TSO5_FW_BSS_LEN             0x88
6236
6237 static const u32 tg3Tso5FwText[(TG3_TSO5_FW_TEXT_LEN / 4) + 1] = {
6238         0x0c004003, 0x00000000, 0x00010f04, 0x00000000, 0x10000003, 0x00000000,
6239         0x0000000d, 0x0000000d, 0x3c1d0001, 0x37bde000, 0x03a0f021, 0x3c100001,
6240         0x26100000, 0x0c004010, 0x00000000, 0x0000000d, 0x27bdffe0, 0x3c04fefe,
6241         0xafbf0018, 0x0c0042e8, 0x34840002, 0x0c004364, 0x00000000, 0x3c030001,
6242         0x90630f34, 0x24020002, 0x3c040001, 0x24840e9c, 0x14620003, 0x24050001,
6243         0x3c040001, 0x24840e90, 0x24060002, 0x00003821, 0xafa00010, 0x0c004378,
6244         0xafa00014, 0x0c00402c, 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020,
6245         0x00000000, 0x00000000, 0x27bdffe0, 0xafbf001c, 0xafb20018, 0xafb10014,
6246         0x0c0042d4, 0xafb00010, 0x3c128000, 0x24110001, 0x8f706810, 0x32020400,
6247         0x10400007, 0x00000000, 0x8f641008, 0x00921024, 0x14400003, 0x00000000,
6248         0x0c004064, 0x00000000, 0x3c020001, 0x90420f56, 0x10510003, 0x32020200,
6249         0x1040fff1, 0x00000000, 0x0c0041b4, 0x00000000, 0x08004034, 0x00000000,
6250         0x8fbf001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0020,
6251         0x27bdffe0, 0x3c040001, 0x24840eb0, 0x00002821, 0x00003021, 0x00003821,
6252         0xafbf0018, 0xafa00010, 0x0c004378, 0xafa00014, 0x0000d021, 0x24020130,
6253         0xaf625000, 0x3c010001, 0xa4200f50, 0x3c010001, 0xa0200f57, 0x8fbf0018,
6254         0x03e00008, 0x27bd0020, 0x00000000, 0x00000000, 0x3c030001, 0x24630f60,
6255         0x90620000, 0x27bdfff0, 0x14400003, 0x0080c021, 0x08004073, 0x00004821,
6256         0x3c022000, 0x03021024, 0x10400003, 0x24090002, 0x08004073, 0xa0600000,
6257         0x24090001, 0x00181040, 0x30431f80, 0x346f8008, 0x1520004b, 0x25eb0028,
6258         0x3c040001, 0x00832021, 0x8c848010, 0x3c050001, 0x24a50f7a, 0x00041402,
6259         0xa0a20000, 0x3c010001, 0xa0240f7b, 0x3c020001, 0x00431021, 0x94428014,
6260         0x3c010001, 0xa0220f7c, 0x3c0c0001, 0x01836021, 0x8d8c8018, 0x304200ff,
6261         0x24420008, 0x000220c3, 0x24020001, 0x3c010001, 0xa0220f60, 0x0124102b,
6262         0x1040000c, 0x00003821, 0x24a6000e, 0x01602821, 0x8ca20000, 0x8ca30004,
6263         0x24a50008, 0x24e70001, 0xacc20000, 0xacc30004, 0x00e4102b, 0x1440fff8,
6264         0x24c60008, 0x00003821, 0x3c080001, 0x25080f7b, 0x91060000, 0x3c020001,
6265         0x90420f7c, 0x2503000d, 0x00c32821, 0x00461023, 0x00021fc2, 0x00431021,
6266         0x00021043, 0x1840000c, 0x00002021, 0x91020001, 0x00461023, 0x00021fc2,
6267         0x00431021, 0x00021843, 0x94a20000, 0x24e70001, 0x00822021, 0x00e3102a,
6268         0x1440fffb, 0x24a50002, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402,
6269         0x00822021, 0x3c02ffff, 0x01821024, 0x3083ffff, 0x00431025, 0x3c010001,
6270         0x080040fa, 0xac220f80, 0x3c050001, 0x24a50f7c, 0x90a20000, 0x3c0c0001,
6271         0x01836021, 0x8d8c8018, 0x000220c2, 0x1080000e, 0x00003821, 0x01603021,
6272         0x24a5000c, 0x8ca20000, 0x8ca30004, 0x24a50008, 0x24e70001, 0xacc20000,
6273         0xacc30004, 0x00e4102b, 0x1440fff8, 0x24c60008, 0x3c050001, 0x24a50f7c,
6274         0x90a20000, 0x30430007, 0x24020004, 0x10620011, 0x28620005, 0x10400005,
6275         0x24020002, 0x10620008, 0x000710c0, 0x080040fa, 0x00000000, 0x24020006,
6276         0x1062000e, 0x000710c0, 0x080040fa, 0x00000000, 0x00a21821, 0x9463000c,
6277         0x004b1021, 0x080040fa, 0xa4430000, 0x000710c0, 0x00a21821, 0x8c63000c,
6278         0x004b1021, 0x080040fa, 0xac430000, 0x00a21821, 0x8c63000c, 0x004b2021,
6279         0x00a21021, 0xac830000, 0x94420010, 0xa4820004, 0x95e70006, 0x3c020001,
6280         0x90420f7c, 0x3c030001, 0x90630f7a, 0x00e2c823, 0x3c020001, 0x90420f7b,
6281         0x24630028, 0x01e34021, 0x24420028, 0x15200012, 0x01e23021, 0x94c2000c,
6282         0x3c010001, 0xa4220f78, 0x94c20004, 0x94c30006, 0x3c010001, 0xa4200f76,
6283         0x3c010001, 0xa4200f72, 0x00021400, 0x00431025, 0x3c010001, 0xac220f6c,
6284         0x95020004, 0x3c010001, 0x08004124, 0xa4220f70, 0x3c020001, 0x94420f70,
6285         0x3c030001, 0x94630f72, 0x00431021, 0xa5020004, 0x3c020001, 0x94420f6c,
6286         0xa4c20004, 0x3c020001, 0x8c420f6c, 0xa4c20006, 0x3c040001, 0x94840f72,
6287         0x3c020001, 0x94420f70, 0x3c0a0001, 0x954a0f76, 0x00441821, 0x3063ffff,
6288         0x0062182a, 0x24020002, 0x1122000b, 0x00832023, 0x3c030001, 0x94630f78,
6289         0x30620009, 0x10400006, 0x3062fff6, 0xa4c2000c, 0x3c020001, 0x94420f78,
6290         0x30420009, 0x01425023, 0x24020001, 0x1122001b, 0x29220002, 0x50400005,
6291         0x24020002, 0x11200007, 0x31a2ffff, 0x08004197, 0x00000000, 0x1122001d,
6292         0x24020016, 0x08004197, 0x31a2ffff, 0x3c0e0001, 0x95ce0f80, 0x10800005,
6293         0x01806821, 0x01c42021, 0x00041c02, 0x3082ffff, 0x00627021, 0x000e1027,
6294         0xa502000a, 0x3c030001, 0x90630f7b, 0x31a2ffff, 0x00e21021, 0x0800418d,
6295         0x00432023, 0x3c020001, 0x94420f80, 0x00442021, 0x00041c02, 0x3082ffff,
6296         0x00622021, 0x00807021, 0x00041027, 0x08004185, 0xa502000a, 0x3c050001,
6297         0x24a50f7a, 0x90a30000, 0x14620002, 0x24e2fff2, 0xa5e20034, 0x90a20000,
6298         0x00e21023, 0xa5020002, 0x3c030001, 0x94630f80, 0x3c020001, 0x94420f5a,
6299         0x30e5ffff, 0x00641821, 0x00451023, 0x00622023, 0x00041c02, 0x3082ffff,
6300         0x00622021, 0x00041027, 0xa502000a, 0x3c030001, 0x90630f7c, 0x24620001,
6301         0x14a20005, 0x00807021, 0x01631021, 0x90420000, 0x08004185, 0x00026200,
6302         0x24620002, 0x14a20003, 0x306200fe, 0x004b1021, 0x944c0000, 0x3c020001,
6303         0x94420f82, 0x3183ffff, 0x3c040001, 0x90840f7b, 0x00431021, 0x00e21021,
6304         0x00442023, 0x008a2021, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402,
6305         0x00822021, 0x00806821, 0x00041027, 0xa4c20010, 0x31a2ffff, 0x000e1c00,
6306         0x00431025, 0x3c040001, 0x24840f72, 0xade20010, 0x94820000, 0x3c050001,
6307         0x94a50f76, 0x3c030001, 0x8c630f6c, 0x24420001, 0x00b92821, 0xa4820000,
6308         0x3322ffff, 0x00622021, 0x0083182b, 0x3c010001, 0xa4250f76, 0x10600003,
6309         0x24a2ffff, 0x3c010001, 0xa4220f76, 0x3c024000, 0x03021025, 0x3c010001,
6310         0xac240f6c, 0xaf621008, 0x03e00008, 0x27bd0010, 0x3c030001, 0x90630f56,
6311         0x27bdffe8, 0x24020001, 0xafbf0014, 0x10620026, 0xafb00010, 0x8f620cf4,
6312         0x2442ffff, 0x3042007f, 0x00021100, 0x8c434000, 0x3c010001, 0xac230f64,
6313         0x8c434008, 0x24444000, 0x8c5c4004, 0x30620040, 0x14400002, 0x24020088,
6314         0x24020008, 0x3c010001, 0xa4220f68, 0x30620004, 0x10400005, 0x24020001,
6315         0x3c010001, 0xa0220f57, 0x080041d5, 0x00031402, 0x3c010001, 0xa0200f57,
6316         0x00031402, 0x3c010001, 0xa4220f54, 0x9483000c, 0x24020001, 0x3c010001,
6317         0xa4200f50, 0x3c010001, 0xa0220f56, 0x3c010001, 0xa4230f62, 0x24020001,
6318         0x1342001e, 0x00000000, 0x13400005, 0x24020003, 0x13420067, 0x00000000,
6319         0x080042cf, 0x00000000, 0x3c020001, 0x94420f62, 0x241a0001, 0x3c010001,
6320         0xa4200f5e, 0x3c010001, 0xa4200f52, 0x304407ff, 0x00021bc2, 0x00031823,
6321         0x3063003e, 0x34630036, 0x00021242, 0x3042003c, 0x00621821, 0x3c010001,
6322         0xa4240f58, 0x00832021, 0x24630030, 0x3c010001, 0xa4240f5a, 0x3c010001,
6323         0xa4230f5c, 0x3c060001, 0x24c60f52, 0x94c50000, 0x94c30002, 0x3c040001,
6324         0x94840f5a, 0x00651021, 0x0044102a, 0x10400013, 0x3c108000, 0x00a31021,
6325         0xa4c20000, 0x3c02a000, 0xaf620cf4, 0x3c010001, 0xa0200f56, 0x8f641008,
6326         0x00901024, 0x14400003, 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4,
6327         0x00501024, 0x104000b7, 0x00000000, 0x0800420f, 0x00000000, 0x3c030001,
6328         0x94630f50, 0x00851023, 0xa4c40000, 0x00621821, 0x3042ffff, 0x3c010001,
6329         0xa4230f50, 0xaf620ce8, 0x3c020001, 0x94420f68, 0x34420024, 0xaf620cec,
6330         0x94c30002, 0x3c020001, 0x94420f50, 0x14620012, 0x3c028000, 0x3c108000,
6331         0x3c02a000, 0xaf620cf4, 0x3c010001, 0xa0200f56, 0x8f641008, 0x00901024,
6332         0x14400003, 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4, 0x00501024,
6333         0x1440fff7, 0x00000000, 0x080042cf, 0x241a0003, 0xaf620cf4, 0x3c108000,
6334         0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064, 0x00000000,
6335         0x8f620cf4, 0x00501024, 0x1440fff7, 0x00000000, 0x080042cf, 0x241a0003,
6336         0x3c070001, 0x24e70f50, 0x94e20000, 0x03821021, 0xaf620ce0, 0x3c020001,
6337         0x8c420f64, 0xaf620ce4, 0x3c050001, 0x94a50f54, 0x94e30000, 0x3c040001,
6338         0x94840f58, 0x3c020001, 0x94420f5e, 0x00a32823, 0x00822023, 0x30a6ffff,
6339         0x3083ffff, 0x00c3102b, 0x14400043, 0x00000000, 0x3c020001, 0x94420f5c,
6340         0x00021400, 0x00621025, 0xaf620ce8, 0x94e20000, 0x3c030001, 0x94630f54,
6341         0x00441021, 0xa4e20000, 0x3042ffff, 0x14430021, 0x3c020008, 0x3c020001,
6342         0x90420f57, 0x10400006, 0x3c03000c, 0x3c020001, 0x94420f68, 0x34630624,
6343         0x0800427c, 0x0000d021, 0x3c020001, 0x94420f68, 0x3c030008, 0x34630624,
6344         0x00431025, 0xaf620cec, 0x3c108000, 0x3c02a000, 0xaf620cf4, 0x3c010001,
6345         0xa0200f56, 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064,
6346         0x00000000, 0x8f620cf4, 0x00501024, 0x10400015, 0x00000000, 0x08004283,
6347         0x00000000, 0x3c030001, 0x94630f68, 0x34420624, 0x3c108000, 0x00621825,
6348         0x3c028000, 0xaf630cec, 0xaf620cf4, 0x8f641008, 0x00901024, 0x14400003,
6349         0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4, 0x00501024, 0x1440fff7,
6350         0x00000000, 0x3c010001, 0x080042cf, 0xa4200f5e, 0x3c020001, 0x94420f5c,
6351         0x00021400, 0x00c21025, 0xaf620ce8, 0x3c020001, 0x90420f57, 0x10400009,
6352         0x3c03000c, 0x3c020001, 0x94420f68, 0x34630624, 0x0000d021, 0x00431025,
6353         0xaf620cec, 0x080042c1, 0x3c108000, 0x3c020001, 0x94420f68, 0x3c030008,
6354         0x34630604, 0x00431025, 0xaf620cec, 0x3c020001, 0x94420f5e, 0x00451021,
6355         0x3c010001, 0xa4220f5e, 0x3c108000, 0x3c02a000, 0xaf620cf4, 0x3c010001,
6356         0xa0200f56, 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064,
6357         0x00000000, 0x8f620cf4, 0x00501024, 0x1440fff7, 0x00000000, 0x8fbf0014,
6358         0x8fb00010, 0x03e00008, 0x27bd0018, 0x00000000, 0x27bdffe0, 0x3c040001,
6359         0x24840ec0, 0x00002821, 0x00003021, 0x00003821, 0xafbf0018, 0xafa00010,
6360         0x0c004378, 0xafa00014, 0x0000d021, 0x24020130, 0xaf625000, 0x3c010001,
6361         0xa4200f50, 0x3c010001, 0xa0200f57, 0x8fbf0018, 0x03e00008, 0x27bd0020,
6362         0x27bdffe8, 0x3c1bc000, 0xafbf0014, 0xafb00010, 0xaf60680c, 0x8f626804,
6363         0x34420082, 0xaf626804, 0x8f634000, 0x24020b50, 0x3c010001, 0xac220f20,
6364         0x24020b78, 0x3c010001, 0xac220f30, 0x34630002, 0xaf634000, 0x0c004315,
6365         0x00808021, 0x3c010001, 0xa0220f34, 0x304200ff, 0x24030002, 0x14430005,
6366         0x00000000, 0x3c020001, 0x8c420f20, 0x08004308, 0xac5000c0, 0x3c020001,
6367         0x8c420f20, 0xac5000bc, 0x8f624434, 0x8f634438, 0x8f644410, 0x3c010001,
6368         0xac220f28, 0x3c010001, 0xac230f38, 0x3c010001, 0xac240f24, 0x8fbf0014,
6369         0x8fb00010, 0x03e00008, 0x27bd0018, 0x03e00008, 0x24020001, 0x27bdfff8,
6370         0x18800009, 0x00002821, 0x8f63680c, 0x8f62680c, 0x1043fffe, 0x00000000,
6371         0x24a50001, 0x00a4102a, 0x1440fff9, 0x00000000, 0x03e00008, 0x27bd0008,
6372         0x8f634450, 0x3c020001, 0x8c420f28, 0x00031c02, 0x0043102b, 0x14400008,
6373         0x3c038000, 0x3c040001, 0x8c840f38, 0x8f624450, 0x00021c02, 0x0083102b,
6374         0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024, 0x1440fffd,
6375         0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3082ffff, 0x2442e000,
6376         0x2c422001, 0x14400003, 0x3c024000, 0x08004347, 0x2402ffff, 0x00822025,
6377         0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00001021, 0x03e00008,
6378         0x00000000, 0x8f624450, 0x3c030001, 0x8c630f24, 0x08004350, 0x3042ffff,
6379         0x8f624450, 0x3042ffff, 0x0043102b, 0x1440fffc, 0x00000000, 0x03e00008,
6380         0x00000000, 0x27bdffe0, 0x00802821, 0x3c040001, 0x24840ed0, 0x00003021,
6381         0x00003821, 0xafbf0018, 0xafa00010, 0x0c004378, 0xafa00014, 0x0800435f,
6382         0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x3c020001, 0x3442d600,
6383         0x3c030001, 0x3463d600, 0x3c040001, 0x3484ddff, 0x3c010001, 0xac220f40,
6384         0x24020040, 0x3c010001, 0xac220f44, 0x3c010001, 0xac200f3c, 0xac600000,
6385         0x24630004, 0x0083102b, 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000,
6386         0x00804821, 0x8faa0010, 0x3c020001, 0x8c420f3c, 0x3c040001, 0x8c840f44,
6387         0x8fab0014, 0x24430001, 0x0044102b, 0x3c010001, 0xac230f3c, 0x14400003,
6388         0x00004021, 0x3c010001, 0xac200f3c, 0x3c020001, 0x8c420f3c, 0x3c030001,
6389         0x8c630f40, 0x91240000, 0x00021140, 0x00431021, 0x00481021, 0x25080001,
6390         0xa0440000, 0x29020008, 0x1440fff4, 0x25290001, 0x3c020001, 0x8c420f3c,
6391         0x3c030001, 0x8c630f40, 0x8f64680c, 0x00021140, 0x00431021, 0xac440008,
6392         0xac45000c, 0xac460010, 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c,
6393         0x00000000, 0x00000000, 0x00000000,
6394 };
6395
6396 static const u32 tg3Tso5FwRodata[(TG3_TSO5_FW_RODATA_LEN / 4) + 1] = {
6397         0x4d61696e, 0x43707542, 0x00000000, 0x4d61696e, 0x43707541, 0x00000000,
6398         0x00000000, 0x00000000, 0x73746b6f, 0x66666c64, 0x00000000, 0x00000000,
6399         0x73746b6f, 0x66666c64, 0x00000000, 0x00000000, 0x66617461, 0x6c457272,
6400         0x00000000, 0x00000000, 0x00000000,
6401 };
6402
6403 static const u32 tg3Tso5FwData[(TG3_TSO5_FW_DATA_LEN / 4) + 1] = {
6404         0x00000000, 0x73746b6f, 0x66666c64, 0x5f76312e, 0x322e3000, 0x00000000,
6405         0x00000000, 0x00000000, 0x00000000,
6406 };
6407
6408 /* tp->lock is held. */
6409 static int tg3_load_tso_firmware(struct tg3 *tp)
6410 {
6411         struct fw_info info;
6412         unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
6413         int err, i;
6414
6415         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
6416                 return 0;
6417
6418         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
6419                 info.text_base = TG3_TSO5_FW_TEXT_ADDR;
6420                 info.text_len = TG3_TSO5_FW_TEXT_LEN;
6421                 info.text_data = &tg3Tso5FwText[0];
6422                 info.rodata_base = TG3_TSO5_FW_RODATA_ADDR;
6423                 info.rodata_len = TG3_TSO5_FW_RODATA_LEN;
6424                 info.rodata_data = &tg3Tso5FwRodata[0];
6425                 info.data_base = TG3_TSO5_FW_DATA_ADDR;
6426                 info.data_len = TG3_TSO5_FW_DATA_LEN;
6427                 info.data_data = &tg3Tso5FwData[0];
6428                 cpu_base = RX_CPU_BASE;
6429                 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
6430                 cpu_scratch_size = (info.text_len +
6431                                     info.rodata_len +
6432                                     info.data_len +
6433                                     TG3_TSO5_FW_SBSS_LEN +
6434                                     TG3_TSO5_FW_BSS_LEN);
6435         } else {
6436                 info.text_base = TG3_TSO_FW_TEXT_ADDR;
6437                 info.text_len = TG3_TSO_FW_TEXT_LEN;
6438                 info.text_data = &tg3TsoFwText[0];
6439                 info.rodata_base = TG3_TSO_FW_RODATA_ADDR;
6440                 info.rodata_len = TG3_TSO_FW_RODATA_LEN;
6441                 info.rodata_data = &tg3TsoFwRodata[0];
6442                 info.data_base = TG3_TSO_FW_DATA_ADDR;
6443                 info.data_len = TG3_TSO_FW_DATA_LEN;
6444                 info.data_data = &tg3TsoFwData[0];
6445                 cpu_base = TX_CPU_BASE;
6446                 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
6447                 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
6448         }
6449
6450         err = tg3_load_firmware_cpu(tp, cpu_base,
6451                                     cpu_scratch_base, cpu_scratch_size,
6452                                     &info);
6453         if (err)
6454                 return err;
6455
6456         /* Now startup the cpu. */
6457         tw32(cpu_base + CPU_STATE, 0xffffffff);
6458         tw32_f(cpu_base + CPU_PC,    info.text_base);
6459
6460         for (i = 0; i < 5; i++) {
6461                 if (tr32(cpu_base + CPU_PC) == info.text_base)
6462                         break;
6463                 tw32(cpu_base + CPU_STATE, 0xffffffff);
6464                 tw32(cpu_base + CPU_MODE,  CPU_MODE_HALT);
6465                 tw32_f(cpu_base + CPU_PC,    info.text_base);
6466                 udelay(1000);
6467         }
6468         if (i >= 5) {
6469                 printk(KERN_ERR PFX "tg3_load_tso_firmware fails for %s "
6470                        "to set CPU PC, is %08x should be %08x\n",
6471                        tp->dev->name, tr32(cpu_base + CPU_PC),
6472                        info.text_base);
6473                 return -ENODEV;
6474         }
6475         tw32(cpu_base + CPU_STATE, 0xffffffff);
6476         tw32_f(cpu_base + CPU_MODE,  0x00000000);
6477         return 0;
6478 }
6479
6480
6481 /* tp->lock is held. */
6482 static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
6483 {
6484         u32 addr_high, addr_low;
6485         int i;
6486
6487         addr_high = ((tp->dev->dev_addr[0] << 8) |
6488                      tp->dev->dev_addr[1]);
6489         addr_low = ((tp->dev->dev_addr[2] << 24) |
6490                     (tp->dev->dev_addr[3] << 16) |
6491                     (tp->dev->dev_addr[4] <<  8) |
6492                     (tp->dev->dev_addr[5] <<  0));
6493         for (i = 0; i < 4; i++) {
6494                 if (i == 1 && skip_mac_1)
6495                         continue;
6496                 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
6497                 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
6498         }
6499
6500         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
6501             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
6502                 for (i = 0; i < 12; i++) {
6503                         tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
6504                         tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
6505                 }
6506         }
6507
6508         addr_high = (tp->dev->dev_addr[0] +
6509                      tp->dev->dev_addr[1] +
6510                      tp->dev->dev_addr[2] +
6511                      tp->dev->dev_addr[3] +
6512                      tp->dev->dev_addr[4] +
6513                      tp->dev->dev_addr[5]) &
6514                 TX_BACKOFF_SEED_MASK;
6515         tw32(MAC_TX_BACKOFF_SEED, addr_high);
6516 }
6517
6518 static int tg3_set_mac_addr(struct net_device *dev, void *p)
6519 {
6520         struct tg3 *tp = netdev_priv(dev);
6521         struct sockaddr *addr = p;
6522         int err = 0, skip_mac_1 = 0;
6523
6524         if (!is_valid_ether_addr(addr->sa_data))
6525                 return -EINVAL;
6526
6527         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
6528
6529         if (!netif_running(dev))
6530                 return 0;
6531
6532         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6533                 u32 addr0_high, addr0_low, addr1_high, addr1_low;
6534
6535                 addr0_high = tr32(MAC_ADDR_0_HIGH);
6536                 addr0_low = tr32(MAC_ADDR_0_LOW);
6537                 addr1_high = tr32(MAC_ADDR_1_HIGH);
6538                 addr1_low = tr32(MAC_ADDR_1_LOW);
6539
6540                 /* Skip MAC addr 1 if ASF is using it. */
6541                 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
6542                     !(addr1_high == 0 && addr1_low == 0))
6543                         skip_mac_1 = 1;
6544         }
6545         spin_lock_bh(&tp->lock);
6546         __tg3_set_mac_addr(tp, skip_mac_1);
6547         spin_unlock_bh(&tp->lock);
6548
6549         return err;
6550 }
6551
6552 /* tp->lock is held. */
6553 static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
6554                            dma_addr_t mapping, u32 maxlen_flags,
6555                            u32 nic_addr)
6556 {
6557         tg3_write_mem(tp,
6558                       (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
6559                       ((u64) mapping >> 32));
6560         tg3_write_mem(tp,
6561                       (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
6562                       ((u64) mapping & 0xffffffff));
6563         tg3_write_mem(tp,
6564                       (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
6565                        maxlen_flags);
6566
6567         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6568                 tg3_write_mem(tp,
6569                               (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
6570                               nic_addr);
6571 }
6572
6573 static void __tg3_set_rx_mode(struct net_device *);
6574 static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
6575 {
6576         tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
6577         tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
6578         tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
6579         tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
6580         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6581                 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
6582                 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
6583         }
6584         tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
6585         tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
6586         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6587                 u32 val = ec->stats_block_coalesce_usecs;
6588
6589                 if (!netif_carrier_ok(tp->dev))
6590                         val = 0;
6591
6592                 tw32(HOSTCC_STAT_COAL_TICKS, val);
6593         }
6594 }
6595
6596 /* tp->lock is held. */
6597 static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
6598 {
6599         u32 val, rdmac_mode;
6600         int i, err, limit;
6601
6602         tg3_disable_ints(tp);
6603
6604         tg3_stop_fw(tp);
6605
6606         tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
6607
6608         if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) {
6609                 tg3_abort_hw(tp, 1);
6610         }
6611
6612         if (reset_phy)
6613                 tg3_phy_reset(tp);
6614
6615         err = tg3_chip_reset(tp);
6616         if (err)
6617                 return err;
6618
6619         tg3_write_sig_legacy(tp, RESET_KIND_INIT);
6620
6621         if (tp->pci_chip_rev_id == CHIPREV_ID_5784_A0 ||
6622             tp->pci_chip_rev_id == CHIPREV_ID_5784_A1) {
6623                 val = tr32(TG3_CPMU_CTRL);
6624                 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
6625                 tw32(TG3_CPMU_CTRL, val);
6626
6627                 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
6628                 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
6629                 val |= CPMU_LSPD_10MB_MACCLK_6_25;
6630                 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
6631
6632                 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
6633                 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
6634                 val |= CPMU_LNK_AWARE_MACCLK_6_25;
6635                 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
6636
6637                 val = tr32(TG3_CPMU_HST_ACC);
6638                 val &= ~CPMU_HST_ACC_MACCLK_MASK;
6639                 val |= CPMU_HST_ACC_MACCLK_6_25;
6640                 tw32(TG3_CPMU_HST_ACC, val);
6641         }
6642
6643         /* This works around an issue with Athlon chipsets on
6644          * B3 tigon3 silicon.  This bit has no effect on any
6645          * other revision.  But do not set this on PCI Express
6646          * chips and don't even touch the clocks if the CPMU is present.
6647          */
6648         if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)) {
6649                 if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
6650                         tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
6651                 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
6652         }
6653
6654         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6655             (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
6656                 val = tr32(TG3PCI_PCISTATE);
6657                 val |= PCISTATE_RETRY_SAME_DMA;
6658                 tw32(TG3PCI_PCISTATE, val);
6659         }
6660
6661         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
6662                 /* Allow reads and writes to the
6663                  * APE register and memory space.
6664                  */
6665                 val = tr32(TG3PCI_PCISTATE);
6666                 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
6667                        PCISTATE_ALLOW_APE_SHMEM_WR;
6668                 tw32(TG3PCI_PCISTATE, val);
6669         }
6670
6671         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
6672                 /* Enable some hw fixes.  */
6673                 val = tr32(TG3PCI_MSI_DATA);
6674                 val |= (1 << 26) | (1 << 28) | (1 << 29);
6675                 tw32(TG3PCI_MSI_DATA, val);
6676         }
6677
6678         /* Descriptor ring init may make accesses to the
6679          * NIC SRAM area to setup the TX descriptors, so we
6680          * can only do this after the hardware has been
6681          * successfully reset.
6682          */
6683         err = tg3_init_rings(tp);
6684         if (err)
6685                 return err;
6686
6687         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
6688             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) {
6689                 /* This value is determined during the probe time DMA
6690                  * engine test, tg3_test_dma.
6691                  */
6692                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
6693         }
6694
6695         tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
6696                           GRC_MODE_4X_NIC_SEND_RINGS |
6697                           GRC_MODE_NO_TX_PHDR_CSUM |
6698                           GRC_MODE_NO_RX_PHDR_CSUM);
6699         tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
6700
6701         /* Pseudo-header checksum is done by hardware logic and not
6702          * the offload processers, so make the chip do the pseudo-
6703          * header checksums on receive.  For transmit it is more
6704          * convenient to do the pseudo-header checksum in software
6705          * as Linux does that on transmit for us in all cases.
6706          */
6707         tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
6708
6709         tw32(GRC_MODE,
6710              tp->grc_mode |
6711              (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
6712
6713         /* Setup the timer prescalar register.  Clock is always 66Mhz. */
6714         val = tr32(GRC_MISC_CFG);
6715         val &= ~0xff;
6716         val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
6717         tw32(GRC_MISC_CFG, val);
6718
6719         /* Initialize MBUF/DESC pool. */
6720         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
6721                 /* Do nothing.  */
6722         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
6723                 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
6724                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
6725                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
6726                 else
6727                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
6728                 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
6729                 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
6730         }
6731         else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
6732                 int fw_len;
6733
6734                 fw_len = (TG3_TSO5_FW_TEXT_LEN +
6735                           TG3_TSO5_FW_RODATA_LEN +
6736                           TG3_TSO5_FW_DATA_LEN +
6737                           TG3_TSO5_FW_SBSS_LEN +
6738                           TG3_TSO5_FW_BSS_LEN);
6739                 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
6740                 tw32(BUFMGR_MB_POOL_ADDR,
6741                      NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
6742                 tw32(BUFMGR_MB_POOL_SIZE,
6743                      NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
6744         }
6745
6746         if (tp->dev->mtu <= ETH_DATA_LEN) {
6747                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
6748                      tp->bufmgr_config.mbuf_read_dma_low_water);
6749                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
6750                      tp->bufmgr_config.mbuf_mac_rx_low_water);
6751                 tw32(BUFMGR_MB_HIGH_WATER,
6752                      tp->bufmgr_config.mbuf_high_water);
6753         } else {
6754                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
6755                      tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
6756                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
6757                      tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
6758                 tw32(BUFMGR_MB_HIGH_WATER,
6759                      tp->bufmgr_config.mbuf_high_water_jumbo);
6760         }
6761         tw32(BUFMGR_DMA_LOW_WATER,
6762              tp->bufmgr_config.dma_low_water);
6763         tw32(BUFMGR_DMA_HIGH_WATER,
6764              tp->bufmgr_config.dma_high_water);
6765
6766         tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
6767         for (i = 0; i < 2000; i++) {
6768                 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
6769                         break;
6770                 udelay(10);
6771         }
6772         if (i >= 2000) {
6773                 printk(KERN_ERR PFX "tg3_reset_hw cannot enable BUFMGR for %s.\n",
6774                        tp->dev->name);
6775                 return -ENODEV;
6776         }
6777
6778         /* Setup replenish threshold. */
6779         val = tp->rx_pending / 8;
6780         if (val == 0)
6781                 val = 1;
6782         else if (val > tp->rx_std_max_post)
6783                 val = tp->rx_std_max_post;
6784         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6785                 if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
6786                         tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
6787
6788                 if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2))
6789                         val = TG3_RX_INTERNAL_RING_SZ_5906 / 2;
6790         }
6791
6792         tw32(RCVBDI_STD_THRESH, val);
6793
6794         /* Initialize TG3_BDINFO's at:
6795          *  RCVDBDI_STD_BD:     standard eth size rx ring
6796          *  RCVDBDI_JUMBO_BD:   jumbo frame rx ring
6797          *  RCVDBDI_MINI_BD:    small frame rx ring (??? does not work)
6798          *
6799          * like so:
6800          *  TG3_BDINFO_HOST_ADDR:       high/low parts of DMA address of ring
6801          *  TG3_BDINFO_MAXLEN_FLAGS:    (rx max buffer size << 16) |
6802          *                              ring attribute flags
6803          *  TG3_BDINFO_NIC_ADDR:        location of descriptors in nic SRAM
6804          *
6805          * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
6806          * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
6807          *
6808          * The size of each ring is fixed in the firmware, but the location is
6809          * configurable.
6810          */
6811         tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
6812              ((u64) tp->rx_std_mapping >> 32));
6813         tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
6814              ((u64) tp->rx_std_mapping & 0xffffffff));
6815         tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
6816              NIC_SRAM_RX_BUFFER_DESC);
6817
6818         /* Don't even try to program the JUMBO/MINI buffer descriptor
6819          * configs on 5705.
6820          */
6821         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
6822                 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
6823                      RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT);
6824         } else {
6825                 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
6826                      RX_STD_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
6827
6828                 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
6829                      BDINFO_FLAGS_DISABLED);
6830
6831                 /* Setup replenish threshold. */
6832                 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
6833
6834                 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
6835                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
6836                              ((u64) tp->rx_jumbo_mapping >> 32));
6837                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
6838                              ((u64) tp->rx_jumbo_mapping & 0xffffffff));
6839                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
6840                              RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
6841                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
6842                              NIC_SRAM_RX_JUMBO_BUFFER_DESC);
6843                 } else {
6844                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
6845                              BDINFO_FLAGS_DISABLED);
6846                 }
6847
6848         }
6849
6850         /* There is only one send ring on 5705/5750, no need to explicitly
6851          * disable the others.
6852          */
6853         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6854                 /* Clear out send RCB ring in SRAM. */
6855                 for (i = NIC_SRAM_SEND_RCB; i < NIC_SRAM_RCV_RET_RCB; i += TG3_BDINFO_SIZE)
6856                         tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
6857                                       BDINFO_FLAGS_DISABLED);
6858         }
6859
6860         tp->tx_prod = 0;
6861         tp->tx_cons = 0;
6862         tw32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
6863         tw32_tx_mbox(MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
6864
6865         tg3_set_bdinfo(tp, NIC_SRAM_SEND_RCB,
6866                        tp->tx_desc_mapping,
6867                        (TG3_TX_RING_SIZE <<
6868                         BDINFO_FLAGS_MAXLEN_SHIFT),
6869                        NIC_SRAM_TX_BUFFER_DESC);
6870
6871         /* There is only one receive return ring on 5705/5750, no need
6872          * to explicitly disable the others.
6873          */
6874         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6875                 for (i = NIC_SRAM_RCV_RET_RCB; i < NIC_SRAM_STATS_BLK;
6876                      i += TG3_BDINFO_SIZE) {
6877                         tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
6878                                       BDINFO_FLAGS_DISABLED);
6879                 }
6880         }
6881
6882         tp->rx_rcb_ptr = 0;
6883         tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, 0);
6884
6885         tg3_set_bdinfo(tp, NIC_SRAM_RCV_RET_RCB,
6886                        tp->rx_rcb_mapping,
6887                        (TG3_RX_RCB_RING_SIZE(tp) <<
6888                         BDINFO_FLAGS_MAXLEN_SHIFT),
6889                        0);
6890
6891         tp->rx_std_ptr = tp->rx_pending;
6892         tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
6893                      tp->rx_std_ptr);
6894
6895         tp->rx_jumbo_ptr = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
6896                                                 tp->rx_jumbo_pending : 0;
6897         tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
6898                      tp->rx_jumbo_ptr);
6899
6900         /* Initialize MAC address and backoff seed. */
6901         __tg3_set_mac_addr(tp, 0);
6902
6903         /* MTU + ethernet header + FCS + optional VLAN tag */
6904         tw32(MAC_RX_MTU_SIZE, tp->dev->mtu + ETH_HLEN + 8);
6905
6906         /* The slot time is changed by tg3_setup_phy if we
6907          * run at gigabit with half duplex.
6908          */
6909         tw32(MAC_TX_LENGTHS,
6910              (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
6911              (6 << TX_LENGTHS_IPG_SHIFT) |
6912              (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
6913
6914         /* Receive rules. */
6915         tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
6916         tw32(RCVLPC_CONFIG, 0x0181);
6917
6918         /* Calculate RDMAC_MODE setting early, we need it to determine
6919          * the RCVLPC_STATE_ENABLE mask.
6920          */
6921         rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
6922                       RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
6923                       RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
6924                       RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
6925                       RDMAC_MODE_LNGREAD_ENAB);
6926
6927         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784)
6928                 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
6929                               RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
6930                               RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
6931
6932         /* If statement applies to 5705 and 5750 PCI devices only */
6933         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
6934              tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
6935             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
6936                 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
6937                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
6938                         rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
6939                 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
6940                            !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
6941                         rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
6942                 }
6943         }
6944
6945         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
6946                 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
6947
6948         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
6949                 rdmac_mode |= (1 << 27);
6950
6951         /* Receive/send statistics. */
6952         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
6953                 val = tr32(RCVLPC_STATS_ENABLE);
6954                 val &= ~RCVLPC_STATSENAB_DACK_FIX;
6955                 tw32(RCVLPC_STATS_ENABLE, val);
6956         } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
6957                    (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
6958                 val = tr32(RCVLPC_STATS_ENABLE);
6959                 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
6960                 tw32(RCVLPC_STATS_ENABLE, val);
6961         } else {
6962                 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
6963         }
6964         tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
6965         tw32(SNDDATAI_STATSENAB, 0xffffff);
6966         tw32(SNDDATAI_STATSCTRL,
6967              (SNDDATAI_SCTRL_ENABLE |
6968               SNDDATAI_SCTRL_FASTUPD));
6969
6970         /* Setup host coalescing engine. */
6971         tw32(HOSTCC_MODE, 0);
6972         for (i = 0; i < 2000; i++) {
6973                 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
6974                         break;
6975                 udelay(10);
6976         }
6977
6978         __tg3_set_coalesce(tp, &tp->coal);
6979
6980         /* set status block DMA address */
6981         tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
6982              ((u64) tp->status_mapping >> 32));
6983         tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
6984              ((u64) tp->status_mapping & 0xffffffff));
6985
6986         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6987                 /* Status/statistics block address.  See tg3_timer,
6988                  * the tg3_periodic_fetch_stats call there, and
6989                  * tg3_get_stats to see how this works for 5705/5750 chips.
6990                  */
6991                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
6992                      ((u64) tp->stats_mapping >> 32));
6993                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
6994                      ((u64) tp->stats_mapping & 0xffffffff));
6995                 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
6996                 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
6997         }
6998
6999         tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
7000
7001         tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
7002         tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
7003         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7004                 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
7005
7006         /* Clear statistics/status block in chip, and status block in ram. */
7007         for (i = NIC_SRAM_STATS_BLK;
7008              i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
7009              i += sizeof(u32)) {
7010                 tg3_write_mem(tp, i, 0);
7011                 udelay(40);
7012         }
7013         memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
7014
7015         if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
7016                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
7017                 /* reset to prevent losing 1st rx packet intermittently */
7018                 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
7019                 udelay(10);
7020         }
7021
7022         tp->mac_mode = MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
7023                 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
7024         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
7025             !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7026             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
7027                 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
7028         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
7029         udelay(40);
7030
7031         /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
7032          * If TG3_FLG2_IS_NIC is zero, we should read the
7033          * register to preserve the GPIO settings for LOMs. The GPIOs,
7034          * whether used as inputs or outputs, are set by boot code after
7035          * reset.
7036          */
7037         if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) {
7038                 u32 gpio_mask;
7039
7040                 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
7041                             GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
7042                             GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
7043
7044                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
7045                         gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
7046                                      GRC_LCLCTRL_GPIO_OUTPUT3;
7047
7048                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
7049                         gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
7050
7051                 tp->grc_local_ctrl &= ~gpio_mask;
7052                 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
7053
7054                 /* GPIO1 must be driven high for eeprom write protect */
7055                 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)
7056                         tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
7057                                                GRC_LCLCTRL_GPIO_OUTPUT1);
7058         }
7059         tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
7060         udelay(100);
7061
7062         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0);
7063         tp->last_tag = 0;
7064
7065         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7066                 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
7067                 udelay(40);
7068         }
7069
7070         val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
7071                WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
7072                WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
7073                WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
7074                WDMAC_MODE_LNGREAD_ENAB);
7075
7076         /* If statement applies to 5705 and 5750 PCI devices only */
7077         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
7078              tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
7079             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
7080                 if ((tp->tg3_flags & TG3_FLG2_TSO_CAPABLE) &&
7081                     (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
7082                      tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
7083                         /* nothing */
7084                 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
7085                            !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
7086                            !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
7087                         val |= WDMAC_MODE_RX_ACCEL;
7088                 }
7089         }
7090
7091         /* Enable host coalescing bug fix */
7092         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755) ||
7093             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787) ||
7094             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784) ||
7095             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761))
7096                 val |= (1 << 29);
7097
7098         tw32_f(WDMAC_MODE, val);
7099         udelay(40);
7100
7101         if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
7102                 u16 pcix_cmd;
7103
7104                 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7105                                      &pcix_cmd);
7106                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
7107                         pcix_cmd &= ~PCI_X_CMD_MAX_READ;
7108                         pcix_cmd |= PCI_X_CMD_READ_2K;
7109                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
7110                         pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
7111                         pcix_cmd |= PCI_X_CMD_READ_2K;
7112                 }
7113                 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7114                                       pcix_cmd);
7115         }
7116
7117         tw32_f(RDMAC_MODE, rdmac_mode);
7118         udelay(40);
7119
7120         tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
7121         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7122                 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
7123
7124         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
7125                 tw32(SNDDATAC_MODE,
7126                      SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
7127         else
7128                 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
7129
7130         tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
7131         tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
7132         tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
7133         tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
7134         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7135                 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
7136         tw32(SNDBDI_MODE, SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE);
7137         tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
7138
7139         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
7140                 err = tg3_load_5701_a0_firmware_fix(tp);
7141                 if (err)
7142                         return err;
7143         }
7144
7145         if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
7146                 err = tg3_load_tso_firmware(tp);
7147                 if (err)
7148                         return err;
7149         }
7150
7151         tp->tx_mode = TX_MODE_ENABLE;
7152         tw32_f(MAC_TX_MODE, tp->tx_mode);
7153         udelay(100);
7154
7155         tp->rx_mode = RX_MODE_ENABLE;
7156         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
7157             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
7158                 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
7159
7160         tw32_f(MAC_RX_MODE, tp->rx_mode);
7161         udelay(10);
7162
7163         if (tp->link_config.phy_is_low_power) {
7164                 tp->link_config.phy_is_low_power = 0;
7165                 tp->link_config.speed = tp->link_config.orig_speed;
7166                 tp->link_config.duplex = tp->link_config.orig_duplex;
7167                 tp->link_config.autoneg = tp->link_config.orig_autoneg;
7168         }
7169
7170         tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
7171         tw32_f(MAC_MI_MODE, tp->mi_mode);
7172         udelay(80);
7173
7174         tw32(MAC_LED_CTRL, tp->led_ctrl);
7175
7176         tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
7177         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
7178                 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
7179                 udelay(10);
7180         }
7181         tw32_f(MAC_RX_MODE, tp->rx_mode);
7182         udelay(10);
7183
7184         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
7185                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
7186                         !(tp->tg3_flags2 & TG3_FLG2_SERDES_PREEMPHASIS)) {
7187                         /* Set drive transmission level to 1.2V  */
7188                         /* only if the signal pre-emphasis bit is not set  */
7189                         val = tr32(MAC_SERDES_CFG);
7190                         val &= 0xfffff000;
7191                         val |= 0x880;
7192                         tw32(MAC_SERDES_CFG, val);
7193                 }
7194                 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
7195                         tw32(MAC_SERDES_CFG, 0x616000);
7196         }
7197
7198         /* Prevent chip from dropping frames when flow control
7199          * is enabled.
7200          */
7201         tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, 2);
7202
7203         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
7204             (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
7205                 /* Use hardware link auto-negotiation */
7206                 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
7207         }
7208
7209         if ((tp->tg3_flags2 & TG3_FLG2_MII_SERDES) &&
7210             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
7211                 u32 tmp;
7212
7213                 tmp = tr32(SERDES_RX_CTRL);
7214                 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
7215                 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
7216                 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
7217                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
7218         }
7219
7220         err = tg3_setup_phy(tp, 0);
7221         if (err)
7222                 return err;
7223
7224         if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7225             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906) {
7226                 u32 tmp;
7227
7228                 /* Clear CRC stats. */
7229                 if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
7230                         tg3_writephy(tp, MII_TG3_TEST1,
7231                                      tmp | MII_TG3_TEST1_CRC_EN);
7232                         tg3_readphy(tp, 0x14, &tmp);
7233                 }
7234         }
7235
7236         __tg3_set_rx_mode(tp->dev);
7237
7238         /* Initialize receive rules. */
7239         tw32(MAC_RCV_RULE_0,  0xc2000000 & RCV_RULE_DISABLE_MASK);
7240         tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
7241         tw32(MAC_RCV_RULE_1,  0x86000004 & RCV_RULE_DISABLE_MASK);
7242         tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
7243
7244         if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
7245             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
7246                 limit = 8;
7247         else
7248                 limit = 16;
7249         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
7250                 limit -= 4;
7251         switch (limit) {
7252         case 16:
7253                 tw32(MAC_RCV_RULE_15,  0); tw32(MAC_RCV_VALUE_15,  0);
7254         case 15:
7255                 tw32(MAC_RCV_RULE_14,  0); tw32(MAC_RCV_VALUE_14,  0);
7256         case 14:
7257                 tw32(MAC_RCV_RULE_13,  0); tw32(MAC_RCV_VALUE_13,  0);
7258         case 13:
7259                 tw32(MAC_RCV_RULE_12,  0); tw32(MAC_RCV_VALUE_12,  0);
7260         case 12:
7261                 tw32(MAC_RCV_RULE_11,  0); tw32(MAC_RCV_VALUE_11,  0);
7262         case 11:
7263                 tw32(MAC_RCV_RULE_10,  0); tw32(MAC_RCV_VALUE_10,  0);
7264         case 10:
7265                 tw32(MAC_RCV_RULE_9,  0); tw32(MAC_RCV_VALUE_9,  0);
7266         case 9:
7267                 tw32(MAC_RCV_RULE_8,  0); tw32(MAC_RCV_VALUE_8,  0);
7268         case 8:
7269                 tw32(MAC_RCV_RULE_7,  0); tw32(MAC_RCV_VALUE_7,  0);
7270         case 7:
7271                 tw32(MAC_RCV_RULE_6,  0); tw32(MAC_RCV_VALUE_6,  0);
7272         case 6:
7273                 tw32(MAC_RCV_RULE_5,  0); tw32(MAC_RCV_VALUE_5,  0);
7274         case 5:
7275                 tw32(MAC_RCV_RULE_4,  0); tw32(MAC_RCV_VALUE_4,  0);
7276         case 4:
7277                 /* tw32(MAC_RCV_RULE_3,  0); tw32(MAC_RCV_VALUE_3,  0); */
7278         case 3:
7279                 /* tw32(MAC_RCV_RULE_2,  0); tw32(MAC_RCV_VALUE_2,  0); */
7280         case 2:
7281         case 1:
7282
7283         default:
7284                 break;
7285         }
7286
7287         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
7288                 /* Write our heartbeat update interval to APE. */
7289                 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
7290                                 APE_HOST_HEARTBEAT_INT_DISABLE);
7291
7292         tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
7293
7294         return 0;
7295 }
7296
7297 /* Called at device open time to get the chip ready for
7298  * packet processing.  Invoked with tp->lock held.
7299  */
7300 static int tg3_init_hw(struct tg3 *tp, int reset_phy)
7301 {
7302         int err;
7303
7304         /* Force the chip into D0. */
7305         err = tg3_set_power_state(tp, PCI_D0);
7306         if (err)
7307                 goto out;
7308
7309         tg3_switch_clocks(tp);
7310
7311         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
7312
7313         err = tg3_reset_hw(tp, reset_phy);
7314
7315 out:
7316         return err;
7317 }
7318
7319 #define TG3_STAT_ADD32(PSTAT, REG) \
7320 do {    u32 __val = tr32(REG); \
7321         (PSTAT)->low += __val; \
7322         if ((PSTAT)->low < __val) \
7323                 (PSTAT)->high += 1; \
7324 } while (0)
7325
7326 static void tg3_periodic_fetch_stats(struct tg3 *tp)
7327 {
7328         struct tg3_hw_stats *sp = tp->hw_stats;
7329
7330         if (!netif_carrier_ok(tp->dev))
7331                 return;
7332
7333         TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
7334         TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
7335         TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
7336         TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
7337         TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
7338         TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
7339         TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
7340         TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
7341         TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
7342         TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
7343         TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
7344         TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
7345         TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
7346
7347         TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
7348         TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
7349         TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
7350         TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
7351         TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
7352         TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
7353         TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
7354         TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
7355         TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
7356         TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
7357         TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
7358         TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
7359         TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
7360         TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
7361
7362         TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
7363         TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
7364         TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
7365 }
7366
7367 static void tg3_timer(unsigned long __opaque)
7368 {
7369         struct tg3 *tp = (struct tg3 *) __opaque;
7370
7371         if (tp->irq_sync)
7372                 goto restart_timer;
7373
7374         spin_lock(&tp->lock);
7375
7376         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
7377                 /* All of this garbage is because when using non-tagged
7378                  * IRQ status the mailbox/status_block protocol the chip
7379                  * uses with the cpu is race prone.
7380                  */
7381                 if (tp->hw_status->status & SD_STATUS_UPDATED) {
7382                         tw32(GRC_LOCAL_CTRL,
7383                              tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
7384                 } else {
7385                         tw32(HOSTCC_MODE, tp->coalesce_mode |
7386                              (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
7387                 }
7388
7389                 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
7390                         tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
7391                         spin_unlock(&tp->lock);
7392                         schedule_work(&tp->reset_task);
7393                         return;
7394                 }
7395         }
7396
7397         /* This part only runs once per second. */
7398         if (!--tp->timer_counter) {
7399                 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
7400                         tg3_periodic_fetch_stats(tp);
7401
7402                 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
7403                         u32 mac_stat;
7404                         int phy_event;
7405
7406                         mac_stat = tr32(MAC_STATUS);
7407
7408                         phy_event = 0;
7409                         if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) {
7410                                 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
7411                                         phy_event = 1;
7412                         } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
7413                                 phy_event = 1;
7414
7415                         if (phy_event)
7416                                 tg3_setup_phy(tp, 0);
7417                 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
7418                         u32 mac_stat = tr32(MAC_STATUS);
7419                         int need_setup = 0;
7420
7421                         if (netif_carrier_ok(tp->dev) &&
7422                             (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
7423                                 need_setup = 1;
7424                         }
7425                         if (! netif_carrier_ok(tp->dev) &&
7426                             (mac_stat & (MAC_STATUS_PCS_SYNCED |
7427                                          MAC_STATUS_SIGNAL_DET))) {
7428                                 need_setup = 1;
7429                         }
7430                         if (need_setup) {
7431                                 if (!tp->serdes_counter) {
7432                                         tw32_f(MAC_MODE,
7433                                              (tp->mac_mode &
7434                                               ~MAC_MODE_PORT_MODE_MASK));
7435                                         udelay(40);
7436                                         tw32_f(MAC_MODE, tp->mac_mode);
7437                                         udelay(40);
7438                                 }
7439                                 tg3_setup_phy(tp, 0);
7440                         }
7441                 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
7442                         tg3_serdes_parallel_detect(tp);
7443
7444                 tp->timer_counter = tp->timer_multiplier;
7445         }
7446
7447         /* Heartbeat is only sent once every 2 seconds.
7448          *
7449          * The heartbeat is to tell the ASF firmware that the host
7450          * driver is still alive.  In the event that the OS crashes,
7451          * ASF needs to reset the hardware to free up the FIFO space
7452          * that may be filled with rx packets destined for the host.
7453          * If the FIFO is full, ASF will no longer function properly.
7454          *
7455          * Unintended resets have been reported on real time kernels
7456          * where the timer doesn't run on time.  Netpoll will also have
7457          * same problem.
7458          *
7459          * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
7460          * to check the ring condition when the heartbeat is expiring
7461          * before doing the reset.  This will prevent most unintended
7462          * resets.
7463          */
7464         if (!--tp->asf_counter) {
7465                 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
7466                         u32 val;
7467
7468                         tg3_wait_for_event_ack(tp);
7469
7470                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
7471                                       FWCMD_NICDRV_ALIVE3);
7472                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
7473                         /* 5 seconds timeout */
7474                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, 5);
7475                         val = tr32(GRC_RX_CPU_EVENT);
7476                         val |= GRC_RX_CPU_DRIVER_EVENT;
7477                         tw32_f(GRC_RX_CPU_EVENT, val);
7478                 }
7479                 tp->asf_counter = tp->asf_multiplier;
7480         }
7481
7482         spin_unlock(&tp->lock);
7483
7484 restart_timer:
7485         tp->timer.expires = jiffies + tp->timer_offset;
7486         add_timer(&tp->timer);
7487 }
7488
7489 static int tg3_request_irq(struct tg3 *tp)
7490 {
7491         irq_handler_t fn;
7492         unsigned long flags;
7493         struct net_device *dev = tp->dev;
7494
7495         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7496                 fn = tg3_msi;
7497                 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
7498                         fn = tg3_msi_1shot;
7499                 flags = IRQF_SAMPLE_RANDOM;
7500         } else {
7501                 fn = tg3_interrupt;
7502                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
7503                         fn = tg3_interrupt_tagged;
7504                 flags = IRQF_SHARED | IRQF_SAMPLE_RANDOM;
7505         }
7506         return (request_irq(tp->pdev->irq, fn, flags, dev->name, dev));
7507 }
7508
7509 static int tg3_test_interrupt(struct tg3 *tp)
7510 {
7511         struct net_device *dev = tp->dev;
7512         int err, i, intr_ok = 0;
7513
7514         if (!netif_running(dev))
7515                 return -ENODEV;
7516
7517         tg3_disable_ints(tp);
7518
7519         free_irq(tp->pdev->irq, dev);
7520
7521         err = request_irq(tp->pdev->irq, tg3_test_isr,
7522                           IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, dev);
7523         if (err)
7524                 return err;
7525
7526         tp->hw_status->status &= ~SD_STATUS_UPDATED;
7527         tg3_enable_ints(tp);
7528
7529         tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
7530                HOSTCC_MODE_NOW);
7531
7532         for (i = 0; i < 5; i++) {
7533                 u32 int_mbox, misc_host_ctrl;
7534
7535                 int_mbox = tr32_mailbox(MAILBOX_INTERRUPT_0 +
7536                                         TG3_64BIT_REG_LOW);
7537                 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
7538
7539                 if ((int_mbox != 0) ||
7540                     (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
7541                         intr_ok = 1;
7542                         break;
7543                 }
7544
7545                 msleep(10);
7546         }
7547
7548         tg3_disable_ints(tp);
7549
7550         free_irq(tp->pdev->irq, dev);
7551
7552         err = tg3_request_irq(tp);
7553
7554         if (err)
7555                 return err;
7556
7557         if (intr_ok)
7558                 return 0;
7559
7560         return -EIO;
7561 }
7562
7563 /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
7564  * successfully restored
7565  */
7566 static int tg3_test_msi(struct tg3 *tp)
7567 {
7568         struct net_device *dev = tp->dev;
7569         int err;
7570         u16 pci_cmd;
7571
7572         if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
7573                 return 0;
7574
7575         /* Turn off SERR reporting in case MSI terminates with Master
7576          * Abort.
7577          */
7578         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
7579         pci_write_config_word(tp->pdev, PCI_COMMAND,
7580                               pci_cmd & ~PCI_COMMAND_SERR);
7581
7582         err = tg3_test_interrupt(tp);
7583
7584         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
7585
7586         if (!err)
7587                 return 0;
7588
7589         /* other failures */
7590         if (err != -EIO)
7591                 return err;
7592
7593         /* MSI test failed, go back to INTx mode */
7594         printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
7595                "switching to INTx mode. Please report this failure to "
7596                "the PCI maintainer and include system chipset information.\n",
7597                        tp->dev->name);
7598
7599         free_irq(tp->pdev->irq, dev);
7600         pci_disable_msi(tp->pdev);
7601
7602         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7603
7604         err = tg3_request_irq(tp);
7605         if (err)
7606                 return err;
7607
7608         /* Need to reset the chip because the MSI cycle may have terminated
7609          * with Master Abort.
7610          */
7611         tg3_full_lock(tp, 1);
7612
7613         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7614         err = tg3_init_hw(tp, 1);
7615
7616         tg3_full_unlock(tp);
7617
7618         if (err)
7619                 free_irq(tp->pdev->irq, dev);
7620
7621         return err;
7622 }
7623
7624 static int tg3_open(struct net_device *dev)
7625 {
7626         struct tg3 *tp = netdev_priv(dev);
7627         int err;
7628
7629         netif_carrier_off(tp->dev);
7630
7631         tg3_full_lock(tp, 0);
7632
7633         err = tg3_set_power_state(tp, PCI_D0);
7634         if (err) {
7635                 tg3_full_unlock(tp);
7636                 return err;
7637         }
7638
7639         tg3_disable_ints(tp);
7640         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
7641
7642         tg3_full_unlock(tp);
7643
7644         /* The placement of this call is tied
7645          * to the setup and use of Host TX descriptors.
7646          */
7647         err = tg3_alloc_consistent(tp);
7648         if (err)
7649                 return err;
7650
7651         if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSI) {
7652                 /* All MSI supporting chips should support tagged
7653                  * status.  Assert that this is the case.
7654                  */
7655                 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
7656                         printk(KERN_WARNING PFX "%s: MSI without TAGGED? "
7657                                "Not using MSI.\n", tp->dev->name);
7658                 } else if (pci_enable_msi(tp->pdev) == 0) {
7659                         u32 msi_mode;
7660
7661                         msi_mode = tr32(MSGINT_MODE);
7662                         tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
7663                         tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
7664                 }
7665         }
7666         err = tg3_request_irq(tp);
7667
7668         if (err) {
7669                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7670                         pci_disable_msi(tp->pdev);
7671                         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7672                 }
7673                 tg3_free_consistent(tp);
7674                 return err;
7675         }
7676
7677         napi_enable(&tp->napi);
7678
7679         tg3_full_lock(tp, 0);
7680
7681         err = tg3_init_hw(tp, 1);
7682         if (err) {
7683                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7684                 tg3_free_rings(tp);
7685         } else {
7686                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
7687                         tp->timer_offset = HZ;
7688                 else
7689                         tp->timer_offset = HZ / 10;
7690
7691                 BUG_ON(tp->timer_offset > HZ);
7692                 tp->timer_counter = tp->timer_multiplier =
7693                         (HZ / tp->timer_offset);
7694                 tp->asf_counter = tp->asf_multiplier =
7695                         ((HZ / tp->timer_offset) * 2);
7696
7697                 init_timer(&tp->timer);
7698                 tp->timer.expires = jiffies + tp->timer_offset;
7699                 tp->timer.data = (unsigned long) tp;
7700                 tp->timer.function = tg3_timer;
7701         }
7702
7703         tg3_full_unlock(tp);
7704
7705         if (err) {
7706                 napi_disable(&tp->napi);
7707                 free_irq(tp->pdev->irq, dev);
7708                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7709                         pci_disable_msi(tp->pdev);
7710                         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7711                 }
7712                 tg3_free_consistent(tp);
7713                 return err;
7714         }
7715
7716         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7717                 err = tg3_test_msi(tp);
7718
7719                 if (err) {
7720                         tg3_full_lock(tp, 0);
7721
7722                         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7723                                 pci_disable_msi(tp->pdev);
7724                                 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7725                         }
7726                         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7727                         tg3_free_rings(tp);
7728                         tg3_free_consistent(tp);
7729
7730                         tg3_full_unlock(tp);
7731
7732                         napi_disable(&tp->napi);
7733
7734                         return err;
7735                 }
7736
7737                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7738                         if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI) {
7739                                 u32 val = tr32(PCIE_TRANSACTION_CFG);
7740
7741                                 tw32(PCIE_TRANSACTION_CFG,
7742                                      val | PCIE_TRANS_CFG_1SHOT_MSI);
7743                         }
7744                 }
7745         }
7746
7747         tg3_full_lock(tp, 0);
7748
7749         add_timer(&tp->timer);
7750         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
7751         tg3_enable_ints(tp);
7752
7753         tg3_full_unlock(tp);
7754
7755         netif_start_queue(dev);
7756
7757         return 0;
7758 }
7759
7760 #if 0
7761 /*static*/ void tg3_dump_state(struct tg3 *tp)
7762 {
7763         u32 val32, val32_2, val32_3, val32_4, val32_5;
7764         u16 val16;
7765         int i;
7766
7767         pci_read_config_word(tp->pdev, PCI_STATUS, &val16);
7768         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, &val32);
7769         printk("DEBUG: PCI status [%04x] TG3PCI state[%08x]\n",
7770                val16, val32);
7771
7772         /* MAC block */
7773         printk("DEBUG: MAC_MODE[%08x] MAC_STATUS[%08x]\n",
7774                tr32(MAC_MODE), tr32(MAC_STATUS));
7775         printk("       MAC_EVENT[%08x] MAC_LED_CTRL[%08x]\n",
7776                tr32(MAC_EVENT), tr32(MAC_LED_CTRL));
7777         printk("DEBUG: MAC_TX_MODE[%08x] MAC_TX_STATUS[%08x]\n",
7778                tr32(MAC_TX_MODE), tr32(MAC_TX_STATUS));
7779         printk("       MAC_RX_MODE[%08x] MAC_RX_STATUS[%08x]\n",
7780                tr32(MAC_RX_MODE), tr32(MAC_RX_STATUS));
7781
7782         /* Send data initiator control block */
7783         printk("DEBUG: SNDDATAI_MODE[%08x] SNDDATAI_STATUS[%08x]\n",
7784                tr32(SNDDATAI_MODE), tr32(SNDDATAI_STATUS));
7785         printk("       SNDDATAI_STATSCTRL[%08x]\n",
7786                tr32(SNDDATAI_STATSCTRL));
7787
7788         /* Send data completion control block */
7789         printk("DEBUG: SNDDATAC_MODE[%08x]\n", tr32(SNDDATAC_MODE));
7790
7791         /* Send BD ring selector block */
7792         printk("DEBUG: SNDBDS_MODE[%08x] SNDBDS_STATUS[%08x]\n",
7793                tr32(SNDBDS_MODE), tr32(SNDBDS_STATUS));
7794
7795         /* Send BD initiator control block */
7796         printk("DEBUG: SNDBDI_MODE[%08x] SNDBDI_STATUS[%08x]\n",
7797                tr32(SNDBDI_MODE), tr32(SNDBDI_STATUS));
7798
7799         /* Send BD completion control block */
7800         printk("DEBUG: SNDBDC_MODE[%08x]\n", tr32(SNDBDC_MODE));
7801
7802         /* Receive list placement control block */
7803         printk("DEBUG: RCVLPC_MODE[%08x] RCVLPC_STATUS[%08x]\n",
7804                tr32(RCVLPC_MODE), tr32(RCVLPC_STATUS));
7805         printk("       RCVLPC_STATSCTRL[%08x]\n",
7806                tr32(RCVLPC_STATSCTRL));
7807
7808         /* Receive data and receive BD initiator control block */
7809         printk("DEBUG: RCVDBDI_MODE[%08x] RCVDBDI_STATUS[%08x]\n",
7810                tr32(RCVDBDI_MODE), tr32(RCVDBDI_STATUS));
7811
7812         /* Receive data completion control block */
7813         printk("DEBUG: RCVDCC_MODE[%08x]\n",
7814                tr32(RCVDCC_MODE));
7815
7816         /* Receive BD initiator control block */
7817         printk("DEBUG: RCVBDI_MODE[%08x] RCVBDI_STATUS[%08x]\n",
7818                tr32(RCVBDI_MODE), tr32(RCVBDI_STATUS));
7819
7820         /* Receive BD completion control block */
7821         printk("DEBUG: RCVCC_MODE[%08x] RCVCC_STATUS[%08x]\n",
7822                tr32(RCVCC_MODE), tr32(RCVCC_STATUS));
7823
7824         /* Receive list selector control block */
7825         printk("DEBUG: RCVLSC_MODE[%08x] RCVLSC_STATUS[%08x]\n",
7826                tr32(RCVLSC_MODE), tr32(RCVLSC_STATUS));
7827
7828         /* Mbuf cluster free block */
7829         printk("DEBUG: MBFREE_MODE[%08x] MBFREE_STATUS[%08x]\n",
7830                tr32(MBFREE_MODE), tr32(MBFREE_STATUS));
7831
7832         /* Host coalescing control block */
7833         printk("DEBUG: HOSTCC_MODE[%08x] HOSTCC_STATUS[%08x]\n",
7834                tr32(HOSTCC_MODE), tr32(HOSTCC_STATUS));
7835         printk("DEBUG: HOSTCC_STATS_BLK_HOST_ADDR[%08x%08x]\n",
7836                tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
7837                tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
7838         printk("DEBUG: HOSTCC_STATUS_BLK_HOST_ADDR[%08x%08x]\n",
7839                tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
7840                tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
7841         printk("DEBUG: HOSTCC_STATS_BLK_NIC_ADDR[%08x]\n",
7842                tr32(HOSTCC_STATS_BLK_NIC_ADDR));
7843         printk("DEBUG: HOSTCC_STATUS_BLK_NIC_ADDR[%08x]\n",
7844                tr32(HOSTCC_STATUS_BLK_NIC_ADDR));
7845
7846         /* Memory arbiter control block */
7847         printk("DEBUG: MEMARB_MODE[%08x] MEMARB_STATUS[%08x]\n",
7848                tr32(MEMARB_MODE), tr32(MEMARB_STATUS));
7849
7850         /* Buffer manager control block */
7851         printk("DEBUG: BUFMGR_MODE[%08x] BUFMGR_STATUS[%08x]\n",
7852                tr32(BUFMGR_MODE), tr32(BUFMGR_STATUS));
7853         printk("DEBUG: BUFMGR_MB_POOL_ADDR[%08x] BUFMGR_MB_POOL_SIZE[%08x]\n",
7854                tr32(BUFMGR_MB_POOL_ADDR), tr32(BUFMGR_MB_POOL_SIZE));
7855         printk("DEBUG: BUFMGR_DMA_DESC_POOL_ADDR[%08x] "
7856                "BUFMGR_DMA_DESC_POOL_SIZE[%08x]\n",
7857                tr32(BUFMGR_DMA_DESC_POOL_ADDR),
7858                tr32(BUFMGR_DMA_DESC_POOL_SIZE));
7859
7860         /* Read DMA control block */
7861         printk("DEBUG: RDMAC_MODE[%08x] RDMAC_STATUS[%08x]\n",
7862                tr32(RDMAC_MODE), tr32(RDMAC_STATUS));
7863
7864         /* Write DMA control block */
7865         printk("DEBUG: WDMAC_MODE[%08x] WDMAC_STATUS[%08x]\n",
7866                tr32(WDMAC_MODE), tr32(WDMAC_STATUS));
7867
7868         /* DMA completion block */
7869         printk("DEBUG: DMAC_MODE[%08x]\n",
7870                tr32(DMAC_MODE));
7871
7872         /* GRC block */
7873         printk("DEBUG: GRC_MODE[%08x] GRC_MISC_CFG[%08x]\n",
7874                tr32(GRC_MODE), tr32(GRC_MISC_CFG));
7875         printk("DEBUG: GRC_LOCAL_CTRL[%08x]\n",
7876                tr32(GRC_LOCAL_CTRL));
7877
7878         /* TG3_BDINFOs */
7879         printk("DEBUG: RCVDBDI_JUMBO_BD[%08x%08x:%08x:%08x]\n",
7880                tr32(RCVDBDI_JUMBO_BD + 0x0),
7881                tr32(RCVDBDI_JUMBO_BD + 0x4),
7882                tr32(RCVDBDI_JUMBO_BD + 0x8),
7883                tr32(RCVDBDI_JUMBO_BD + 0xc));
7884         printk("DEBUG: RCVDBDI_STD_BD[%08x%08x:%08x:%08x]\n",
7885                tr32(RCVDBDI_STD_BD + 0x0),
7886                tr32(RCVDBDI_STD_BD + 0x4),
7887                tr32(RCVDBDI_STD_BD + 0x8),
7888                tr32(RCVDBDI_STD_BD + 0xc));
7889         printk("DEBUG: RCVDBDI_MINI_BD[%08x%08x:%08x:%08x]\n",
7890                tr32(RCVDBDI_MINI_BD + 0x0),
7891                tr32(RCVDBDI_MINI_BD + 0x4),
7892                tr32(RCVDBDI_MINI_BD + 0x8),
7893                tr32(RCVDBDI_MINI_BD + 0xc));
7894
7895         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x0, &val32);
7896         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x4, &val32_2);
7897         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x8, &val32_3);
7898         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0xc, &val32_4);
7899         printk("DEBUG: SRAM_SEND_RCB_0[%08x%08x:%08x:%08x]\n",
7900                val32, val32_2, val32_3, val32_4);
7901
7902         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x0, &val32);
7903         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x4, &val32_2);
7904         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x8, &val32_3);
7905         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0xc, &val32_4);
7906         printk("DEBUG: SRAM_RCV_RET_RCB_0[%08x%08x:%08x:%08x]\n",
7907                val32, val32_2, val32_3, val32_4);
7908
7909         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x0, &val32);
7910         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x4, &val32_2);
7911         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x8, &val32_3);
7912         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0xc, &val32_4);
7913         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x10, &val32_5);
7914         printk("DEBUG: SRAM_STATUS_BLK[%08x:%08x:%08x:%08x:%08x]\n",
7915                val32, val32_2, val32_3, val32_4, val32_5);
7916
7917         /* SW status block */
7918         printk("DEBUG: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
7919                tp->hw_status->status,
7920                tp->hw_status->status_tag,
7921                tp->hw_status->rx_jumbo_consumer,
7922                tp->hw_status->rx_consumer,
7923                tp->hw_status->rx_mini_consumer,
7924                tp->hw_status->idx[0].rx_producer,
7925                tp->hw_status->idx[0].tx_consumer);
7926
7927         /* SW statistics block */
7928         printk("DEBUG: Host statistics block [%08x:%08x:%08x:%08x]\n",
7929                ((u32 *)tp->hw_stats)[0],
7930                ((u32 *)tp->hw_stats)[1],
7931                ((u32 *)tp->hw_stats)[2],
7932                ((u32 *)tp->hw_stats)[3]);
7933
7934         /* Mailboxes */
7935         printk("DEBUG: SNDHOST_PROD[%08x%08x] SNDNIC_PROD[%08x%08x]\n",
7936                tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x0),
7937                tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x4),
7938                tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x0),
7939                tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x4));
7940
7941         /* NIC side send descriptors. */
7942         for (i = 0; i < 6; i++) {
7943                 unsigned long txd;
7944
7945                 txd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_TX_BUFFER_DESC
7946                         + (i * sizeof(struct tg3_tx_buffer_desc));
7947                 printk("DEBUG: NIC TXD(%d)[%08x:%08x:%08x:%08x]\n",
7948                        i,
7949                        readl(txd + 0x0), readl(txd + 0x4),
7950                        readl(txd + 0x8), readl(txd + 0xc));
7951         }
7952
7953         /* NIC side RX descriptors. */
7954         for (i = 0; i < 6; i++) {
7955                 unsigned long rxd;
7956
7957                 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_BUFFER_DESC
7958                         + (i * sizeof(struct tg3_rx_buffer_desc));
7959                 printk("DEBUG: NIC RXD_STD(%d)[0][%08x:%08x:%08x:%08x]\n",
7960                        i,
7961                        readl(rxd + 0x0), readl(rxd + 0x4),
7962                        readl(rxd + 0x8), readl(rxd + 0xc));
7963                 rxd += (4 * sizeof(u32));
7964                 printk("DEBUG: NIC RXD_STD(%d)[1][%08x:%08x:%08x:%08x]\n",
7965                        i,
7966                        readl(rxd + 0x0), readl(rxd + 0x4),
7967                        readl(rxd + 0x8), readl(rxd + 0xc));
7968         }
7969
7970         for (i = 0; i < 6; i++) {
7971                 unsigned long rxd;
7972
7973                 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_JUMBO_BUFFER_DESC
7974                         + (i * sizeof(struct tg3_rx_buffer_desc));
7975                 printk("DEBUG: NIC RXD_JUMBO(%d)[0][%08x:%08x:%08x:%08x]\n",
7976                        i,
7977                        readl(rxd + 0x0), readl(rxd + 0x4),
7978                        readl(rxd + 0x8), readl(rxd + 0xc));
7979                 rxd += (4 * sizeof(u32));
7980                 printk("DEBUG: NIC RXD_JUMBO(%d)[1][%08x:%08x:%08x:%08x]\n",
7981                        i,
7982                        readl(rxd + 0x0), readl(rxd + 0x4),
7983                        readl(rxd + 0x8), readl(rxd + 0xc));
7984         }
7985 }
7986 #endif
7987
7988 static struct net_device_stats *tg3_get_stats(struct net_device *);
7989 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
7990
7991 static int tg3_close(struct net_device *dev)
7992 {
7993         struct tg3 *tp = netdev_priv(dev);
7994
7995         napi_disable(&tp->napi);
7996         cancel_work_sync(&tp->reset_task);
7997
7998         netif_stop_queue(dev);
7999
8000         del_timer_sync(&tp->timer);
8001
8002         tg3_full_lock(tp, 1);
8003 #if 0
8004         tg3_dump_state(tp);
8005 #endif
8006
8007         tg3_disable_ints(tp);
8008
8009         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8010         tg3_free_rings(tp);
8011         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
8012
8013         tg3_full_unlock(tp);
8014
8015         free_irq(tp->pdev->irq, dev);
8016         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
8017                 pci_disable_msi(tp->pdev);
8018                 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
8019         }
8020
8021         memcpy(&tp->net_stats_prev, tg3_get_stats(tp->dev),
8022                sizeof(tp->net_stats_prev));
8023         memcpy(&tp->estats_prev, tg3_get_estats(tp),
8024                sizeof(tp->estats_prev));
8025
8026         tg3_free_consistent(tp);
8027
8028         tg3_set_power_state(tp, PCI_D3hot);
8029
8030         netif_carrier_off(tp->dev);
8031
8032         return 0;
8033 }
8034
8035 static inline unsigned long get_stat64(tg3_stat64_t *val)
8036 {
8037         unsigned long ret;
8038
8039 #if (BITS_PER_LONG == 32)
8040         ret = val->low;
8041 #else
8042         ret = ((u64)val->high << 32) | ((u64)val->low);
8043 #endif
8044         return ret;
8045 }
8046
8047 static unsigned long calc_crc_errors(struct tg3 *tp)
8048 {
8049         struct tg3_hw_stats *hw_stats = tp->hw_stats;
8050
8051         if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
8052             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
8053              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
8054                 u32 val;
8055
8056                 spin_lock_bh(&tp->lock);
8057                 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
8058                         tg3_writephy(tp, MII_TG3_TEST1,
8059                                      val | MII_TG3_TEST1_CRC_EN);
8060                         tg3_readphy(tp, 0x14, &val);
8061                 } else
8062                         val = 0;
8063                 spin_unlock_bh(&tp->lock);
8064
8065                 tp->phy_crc_errors += val;
8066
8067                 return tp->phy_crc_errors;
8068         }
8069
8070         return get_stat64(&hw_stats->rx_fcs_errors);
8071 }
8072
8073 #define ESTAT_ADD(member) \
8074         estats->member =        old_estats->member + \
8075                                 get_stat64(&hw_stats->member)
8076
8077 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
8078 {
8079         struct tg3_ethtool_stats *estats = &tp->estats;
8080         struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
8081         struct tg3_hw_stats *hw_stats = tp->hw_stats;
8082
8083         if (!hw_stats)
8084                 return old_estats;
8085
8086         ESTAT_ADD(rx_octets);
8087         ESTAT_ADD(rx_fragments);
8088         ESTAT_ADD(rx_ucast_packets);
8089         ESTAT_ADD(rx_mcast_packets);
8090         ESTAT_ADD(rx_bcast_packets);
8091         ESTAT_ADD(rx_fcs_errors);
8092         ESTAT_ADD(rx_align_errors);
8093         ESTAT_ADD(rx_xon_pause_rcvd);
8094         ESTAT_ADD(rx_xoff_pause_rcvd);
8095         ESTAT_ADD(rx_mac_ctrl_rcvd);
8096         ESTAT_ADD(rx_xoff_entered);
8097         ESTAT_ADD(rx_frame_too_long_errors);
8098         ESTAT_ADD(rx_jabbers);
8099         ESTAT_ADD(rx_undersize_packets);
8100         ESTAT_ADD(rx_in_length_errors);
8101         ESTAT_ADD(rx_out_length_errors);
8102         ESTAT_ADD(rx_64_or_less_octet_packets);
8103         ESTAT_ADD(rx_65_to_127_octet_packets);
8104         ESTAT_ADD(rx_128_to_255_octet_packets);
8105         ESTAT_ADD(rx_256_to_511_octet_packets);
8106         ESTAT_ADD(rx_512_to_1023_octet_packets);
8107         ESTAT_ADD(rx_1024_to_1522_octet_packets);
8108         ESTAT_ADD(rx_1523_to_2047_octet_packets);
8109         ESTAT_ADD(rx_2048_to_4095_octet_packets);
8110         ESTAT_ADD(rx_4096_to_8191_octet_packets);
8111         ESTAT_ADD(rx_8192_to_9022_octet_packets);
8112
8113         ESTAT_ADD(tx_octets);
8114         ESTAT_ADD(tx_collisions);
8115         ESTAT_ADD(tx_xon_sent);
8116         ESTAT_ADD(tx_xoff_sent);
8117         ESTAT_ADD(tx_flow_control);
8118         ESTAT_ADD(tx_mac_errors);
8119         ESTAT_ADD(tx_single_collisions);
8120         ESTAT_ADD(tx_mult_collisions);
8121         ESTAT_ADD(tx_deferred);
8122         ESTAT_ADD(tx_excessive_collisions);
8123         ESTAT_ADD(tx_late_collisions);
8124         ESTAT_ADD(tx_collide_2times);
8125         ESTAT_ADD(tx_collide_3times);
8126         ESTAT_ADD(tx_collide_4times);
8127         ESTAT_ADD(tx_collide_5times);
8128         ESTAT_ADD(tx_collide_6times);
8129         ESTAT_ADD(tx_collide_7times);
8130         ESTAT_ADD(tx_collide_8times);
8131         ESTAT_ADD(tx_collide_9times);
8132         ESTAT_ADD(tx_collide_10times);
8133         ESTAT_ADD(tx_collide_11times);
8134         ESTAT_ADD(tx_collide_12times);
8135         ESTAT_ADD(tx_collide_13times);
8136         ESTAT_ADD(tx_collide_14times);
8137         ESTAT_ADD(tx_collide_15times);
8138         ESTAT_ADD(tx_ucast_packets);
8139         ESTAT_ADD(tx_mcast_packets);
8140         ESTAT_ADD(tx_bcast_packets);
8141         ESTAT_ADD(tx_carrier_sense_errors);
8142         ESTAT_ADD(tx_discards);
8143         ESTAT_ADD(tx_errors);
8144
8145         ESTAT_ADD(dma_writeq_full);
8146         ESTAT_ADD(dma_write_prioq_full);
8147         ESTAT_ADD(rxbds_empty);
8148         ESTAT_ADD(rx_discards);
8149         ESTAT_ADD(rx_errors);
8150         ESTAT_ADD(rx_threshold_hit);
8151
8152         ESTAT_ADD(dma_readq_full);
8153         ESTAT_ADD(dma_read_prioq_full);
8154         ESTAT_ADD(tx_comp_queue_full);
8155
8156         ESTAT_ADD(ring_set_send_prod_index);
8157         ESTAT_ADD(ring_status_update);
8158         ESTAT_ADD(nic_irqs);
8159         ESTAT_ADD(nic_avoided_irqs);
8160         ESTAT_ADD(nic_tx_threshold_hit);
8161
8162         return estats;
8163 }
8164
8165 static struct net_device_stats *tg3_get_stats(struct net_device *dev)
8166 {
8167         struct tg3 *tp = netdev_priv(dev);
8168         struct net_device_stats *stats = &tp->net_stats;
8169         struct net_device_stats *old_stats = &tp->net_stats_prev;
8170         struct tg3_hw_stats *hw_stats = tp->hw_stats;
8171
8172         if (!hw_stats)
8173                 return old_stats;
8174
8175         stats->rx_packets = old_stats->rx_packets +
8176                 get_stat64(&hw_stats->rx_ucast_packets) +
8177                 get_stat64(&hw_stats->rx_mcast_packets) +
8178                 get_stat64(&hw_stats->rx_bcast_packets);
8179
8180         stats->tx_packets = old_stats->tx_packets +
8181                 get_stat64(&hw_stats->tx_ucast_packets) +
8182                 get_stat64(&hw_stats->tx_mcast_packets) +
8183                 get_stat64(&hw_stats->tx_bcast_packets);
8184
8185         stats->rx_bytes = old_stats->rx_bytes +
8186                 get_stat64(&hw_stats->rx_octets);
8187         stats->tx_bytes = old_stats->tx_bytes +
8188                 get_stat64(&hw_stats->tx_octets);
8189
8190         stats->rx_errors = old_stats->rx_errors +
8191                 get_stat64(&hw_stats->rx_errors);
8192         stats->tx_errors = old_stats->tx_errors +
8193                 get_stat64(&hw_stats->tx_errors) +
8194                 get_stat64(&hw_stats->tx_mac_errors) +
8195                 get_stat64(&hw_stats->tx_carrier_sense_errors) +
8196                 get_stat64(&hw_stats->tx_discards);
8197
8198         stats->multicast = old_stats->multicast +
8199                 get_stat64(&hw_stats->rx_mcast_packets);
8200         stats->collisions = old_stats->collisions +
8201                 get_stat64(&hw_stats->tx_collisions);
8202
8203         stats->rx_length_errors = old_stats->rx_length_errors +
8204                 get_stat64(&hw_stats->rx_frame_too_long_errors) +
8205                 get_stat64(&hw_stats->rx_undersize_packets);
8206
8207         stats->rx_over_errors = old_stats->rx_over_errors +
8208                 get_stat64(&hw_stats->rxbds_empty);
8209         stats->rx_frame_errors = old_stats->rx_frame_errors +
8210                 get_stat64(&hw_stats->rx_align_errors);
8211         stats->tx_aborted_errors = old_stats->tx_aborted_errors +
8212                 get_stat64(&hw_stats->tx_discards);
8213         stats->tx_carrier_errors = old_stats->tx_carrier_errors +
8214                 get_stat64(&hw_stats->tx_carrier_sense_errors);
8215
8216         stats->rx_crc_errors = old_stats->rx_crc_errors +
8217                 calc_crc_errors(tp);
8218
8219         stats->rx_missed_errors = old_stats->rx_missed_errors +
8220                 get_stat64(&hw_stats->rx_discards);
8221
8222         return stats;
8223 }
8224
8225 static inline u32 calc_crc(unsigned char *buf, int len)
8226 {
8227         u32 reg;
8228         u32 tmp;
8229         int j, k;
8230
8231         reg = 0xffffffff;
8232
8233         for (j = 0; j < len; j++) {
8234                 reg ^= buf[j];
8235
8236                 for (k = 0; k < 8; k++) {
8237                         tmp = reg & 0x01;
8238
8239                         reg >>= 1;
8240
8241                         if (tmp) {
8242                                 reg ^= 0xedb88320;
8243                         }
8244                 }
8245         }
8246
8247         return ~reg;
8248 }
8249
8250 static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
8251 {
8252         /* accept or reject all multicast frames */
8253         tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
8254         tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
8255         tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
8256         tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
8257 }
8258
8259 static void __tg3_set_rx_mode(struct net_device *dev)
8260 {
8261         struct tg3 *tp = netdev_priv(dev);
8262         u32 rx_mode;
8263
8264         rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
8265                                   RX_MODE_KEEP_VLAN_TAG);
8266
8267         /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
8268          * flag clear.
8269          */
8270 #if TG3_VLAN_TAG_USED
8271         if (!tp->vlgrp &&
8272             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
8273                 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
8274 #else
8275         /* By definition, VLAN is disabled always in this
8276          * case.
8277          */
8278         if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
8279                 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
8280 #endif
8281
8282         if (dev->flags & IFF_PROMISC) {
8283                 /* Promiscuous mode. */
8284                 rx_mode |= RX_MODE_PROMISC;
8285         } else if (dev->flags & IFF_ALLMULTI) {
8286                 /* Accept all multicast. */
8287                 tg3_set_multi (tp, 1);
8288         } else if (dev->mc_count < 1) {
8289                 /* Reject all multicast. */
8290                 tg3_set_multi (tp, 0);
8291         } else {
8292                 /* Accept one or more multicast(s). */
8293                 struct dev_mc_list *mclist;
8294                 unsigned int i;
8295                 u32 mc_filter[4] = { 0, };
8296                 u32 regidx;
8297                 u32 bit;
8298                 u32 crc;
8299
8300                 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
8301                      i++, mclist = mclist->next) {
8302
8303                         crc = calc_crc (mclist->dmi_addr, ETH_ALEN);
8304                         bit = ~crc & 0x7f;
8305                         regidx = (bit & 0x60) >> 5;
8306                         bit &= 0x1f;
8307                         mc_filter[regidx] |= (1 << bit);
8308                 }
8309
8310                 tw32(MAC_HASH_REG_0, mc_filter[0]);
8311                 tw32(MAC_HASH_REG_1, mc_filter[1]);
8312                 tw32(MAC_HASH_REG_2, mc_filter[2]);
8313                 tw32(MAC_HASH_REG_3, mc_filter[3]);
8314         }
8315
8316         if (rx_mode != tp->rx_mode) {
8317                 tp->rx_mode = rx_mode;
8318                 tw32_f(MAC_RX_MODE, rx_mode);
8319                 udelay(10);
8320         }
8321 }
8322
8323 static void tg3_set_rx_mode(struct net_device *dev)
8324 {
8325         struct tg3 *tp = netdev_priv(dev);
8326
8327         if (!netif_running(dev))
8328                 return;
8329
8330         tg3_full_lock(tp, 0);
8331         __tg3_set_rx_mode(dev);
8332         tg3_full_unlock(tp);
8333 }
8334
8335 #define TG3_REGDUMP_LEN         (32 * 1024)
8336
8337 static int tg3_get_regs_len(struct net_device *dev)
8338 {
8339         return TG3_REGDUMP_LEN;
8340 }
8341
8342 static void tg3_get_regs(struct net_device *dev,
8343                 struct ethtool_regs *regs, void *_p)
8344 {
8345         u32 *p = _p;
8346         struct tg3 *tp = netdev_priv(dev);
8347         u8 *orig_p = _p;
8348         int i;
8349
8350         regs->version = 0;
8351
8352         memset(p, 0, TG3_REGDUMP_LEN);
8353
8354         if (tp->link_config.phy_is_low_power)
8355                 return;
8356
8357         tg3_full_lock(tp, 0);
8358
8359 #define __GET_REG32(reg)        (*(p)++ = tr32(reg))
8360 #define GET_REG32_LOOP(base,len)                \
8361 do {    p = (u32 *)(orig_p + (base));           \
8362         for (i = 0; i < len; i += 4)            \
8363                 __GET_REG32((base) + i);        \
8364 } while (0)
8365 #define GET_REG32_1(reg)                        \
8366 do {    p = (u32 *)(orig_p + (reg));            \
8367         __GET_REG32((reg));                     \
8368 } while (0)
8369
8370         GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
8371         GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
8372         GET_REG32_LOOP(MAC_MODE, 0x4f0);
8373         GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
8374         GET_REG32_1(SNDDATAC_MODE);
8375         GET_REG32_LOOP(SNDBDS_MODE, 0x80);
8376         GET_REG32_LOOP(SNDBDI_MODE, 0x48);
8377         GET_REG32_1(SNDBDC_MODE);
8378         GET_REG32_LOOP(RCVLPC_MODE, 0x20);
8379         GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
8380         GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
8381         GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
8382         GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
8383         GET_REG32_1(RCVDCC_MODE);
8384         GET_REG32_LOOP(RCVBDI_MODE, 0x20);
8385         GET_REG32_LOOP(RCVCC_MODE, 0x14);
8386         GET_REG32_LOOP(RCVLSC_MODE, 0x08);
8387         GET_REG32_1(MBFREE_MODE);
8388         GET_REG32_LOOP(HOSTCC_MODE, 0x100);
8389         GET_REG32_LOOP(MEMARB_MODE, 0x10);
8390         GET_REG32_LOOP(BUFMGR_MODE, 0x58);
8391         GET_REG32_LOOP(RDMAC_MODE, 0x08);
8392         GET_REG32_LOOP(WDMAC_MODE, 0x08);
8393         GET_REG32_1(RX_CPU_MODE);
8394         GET_REG32_1(RX_CPU_STATE);
8395         GET_REG32_1(RX_CPU_PGMCTR);
8396         GET_REG32_1(RX_CPU_HWBKPT);
8397         GET_REG32_1(TX_CPU_MODE);
8398         GET_REG32_1(TX_CPU_STATE);
8399         GET_REG32_1(TX_CPU_PGMCTR);
8400         GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
8401         GET_REG32_LOOP(FTQ_RESET, 0x120);
8402         GET_REG32_LOOP(MSGINT_MODE, 0x0c);
8403         GET_REG32_1(DMAC_MODE);
8404         GET_REG32_LOOP(GRC_MODE, 0x4c);
8405         if (tp->tg3_flags & TG3_FLAG_NVRAM)
8406                 GET_REG32_LOOP(NVRAM_CMD, 0x24);
8407
8408 #undef __GET_REG32
8409 #undef GET_REG32_LOOP
8410 #undef GET_REG32_1
8411
8412         tg3_full_unlock(tp);
8413 }
8414
8415 static int tg3_get_eeprom_len(struct net_device *dev)
8416 {
8417         struct tg3 *tp = netdev_priv(dev);
8418
8419         return tp->nvram_size;
8420 }
8421
8422 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val);
8423 static int tg3_nvram_read_le(struct tg3 *tp, u32 offset, __le32 *val);
8424 static int tg3_nvram_read_swab(struct tg3 *tp, u32 offset, u32 *val);
8425
8426 static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
8427 {
8428         struct tg3 *tp = netdev_priv(dev);
8429         int ret;
8430         u8  *pd;
8431         u32 i, offset, len, b_offset, b_count;
8432         __le32 val;
8433
8434         if (tp->link_config.phy_is_low_power)
8435                 return -EAGAIN;
8436
8437         offset = eeprom->offset;
8438         len = eeprom->len;
8439         eeprom->len = 0;
8440
8441         eeprom->magic = TG3_EEPROM_MAGIC;
8442
8443         if (offset & 3) {
8444                 /* adjustments to start on required 4 byte boundary */
8445                 b_offset = offset & 3;
8446                 b_count = 4 - b_offset;
8447                 if (b_count > len) {
8448                         /* i.e. offset=1 len=2 */
8449                         b_count = len;
8450                 }
8451                 ret = tg3_nvram_read_le(tp, offset-b_offset, &val);
8452                 if (ret)
8453                         return ret;
8454                 memcpy(data, ((char*)&val) + b_offset, b_count);
8455                 len -= b_count;
8456                 offset += b_count;
8457                 eeprom->len += b_count;
8458         }
8459
8460         /* read bytes upto the last 4 byte boundary */
8461         pd = &data[eeprom->len];
8462         for (i = 0; i < (len - (len & 3)); i += 4) {
8463                 ret = tg3_nvram_read_le(tp, offset + i, &val);
8464                 if (ret) {
8465                         eeprom->len += i;
8466                         return ret;
8467                 }
8468                 memcpy(pd + i, &val, 4);
8469         }
8470         eeprom->len += i;
8471
8472         if (len & 3) {
8473                 /* read last bytes not ending on 4 byte boundary */
8474                 pd = &data[eeprom->len];
8475                 b_count = len & 3;
8476                 b_offset = offset + len - b_count;
8477                 ret = tg3_nvram_read_le(tp, b_offset, &val);
8478                 if (ret)
8479                         return ret;
8480                 memcpy(pd, &val, b_count);
8481                 eeprom->len += b_count;
8482         }
8483         return 0;
8484 }
8485
8486 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
8487
8488 static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
8489 {
8490         struct tg3 *tp = netdev_priv(dev);
8491         int ret;
8492         u32 offset, len, b_offset, odd_len;
8493         u8 *buf;
8494         __le32 start, end;
8495
8496         if (tp->link_config.phy_is_low_power)
8497                 return -EAGAIN;
8498
8499         if (eeprom->magic != TG3_EEPROM_MAGIC)
8500                 return -EINVAL;
8501
8502         offset = eeprom->offset;
8503         len = eeprom->len;
8504
8505         if ((b_offset = (offset & 3))) {
8506                 /* adjustments to start on required 4 byte boundary */
8507                 ret = tg3_nvram_read_le(tp, offset-b_offset, &start);
8508                 if (ret)
8509                         return ret;
8510                 len += b_offset;
8511                 offset &= ~3;
8512                 if (len < 4)
8513                         len = 4;
8514         }
8515
8516         odd_len = 0;
8517         if (len & 3) {
8518                 /* adjustments to end on required 4 byte boundary */
8519                 odd_len = 1;
8520                 len = (len + 3) & ~3;
8521                 ret = tg3_nvram_read_le(tp, offset+len-4, &end);
8522                 if (ret)
8523                         return ret;
8524         }
8525
8526         buf = data;
8527         if (b_offset || odd_len) {
8528                 buf = kmalloc(len, GFP_KERNEL);
8529                 if (!buf)
8530                         return -ENOMEM;
8531                 if (b_offset)
8532                         memcpy(buf, &start, 4);
8533                 if (odd_len)
8534                         memcpy(buf+len-4, &end, 4);
8535                 memcpy(buf + b_offset, data, eeprom->len);
8536         }
8537
8538         ret = tg3_nvram_write_block(tp, offset, len, buf);
8539
8540         if (buf != data)
8541                 kfree(buf);
8542
8543         return ret;
8544 }
8545
8546 static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
8547 {
8548         struct tg3 *tp = netdev_priv(dev);
8549
8550         cmd->supported = (SUPPORTED_Autoneg);
8551
8552         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
8553                 cmd->supported |= (SUPPORTED_1000baseT_Half |
8554                                    SUPPORTED_1000baseT_Full);
8555
8556         if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
8557                 cmd->supported |= (SUPPORTED_100baseT_Half |
8558                                   SUPPORTED_100baseT_Full |
8559                                   SUPPORTED_10baseT_Half |
8560                                   SUPPORTED_10baseT_Full |
8561                                   SUPPORTED_TP);
8562                 cmd->port = PORT_TP;
8563         } else {
8564                 cmd->supported |= SUPPORTED_FIBRE;
8565                 cmd->port = PORT_FIBRE;
8566         }
8567
8568         cmd->advertising = tp->link_config.advertising;
8569         if (netif_running(dev)) {
8570                 cmd->speed = tp->link_config.active_speed;
8571                 cmd->duplex = tp->link_config.active_duplex;
8572         }
8573         cmd->phy_address = PHY_ADDR;
8574         cmd->transceiver = 0;
8575         cmd->autoneg = tp->link_config.autoneg;
8576         cmd->maxtxpkt = 0;
8577         cmd->maxrxpkt = 0;
8578         return 0;
8579 }
8580
8581 static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
8582 {
8583         struct tg3 *tp = netdev_priv(dev);
8584
8585         if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) {
8586                 /* These are the only valid advertisement bits allowed.  */
8587                 if (cmd->autoneg == AUTONEG_ENABLE &&
8588                     (cmd->advertising & ~(ADVERTISED_1000baseT_Half |
8589                                           ADVERTISED_1000baseT_Full |
8590                                           ADVERTISED_Autoneg |
8591                                           ADVERTISED_FIBRE)))
8592                         return -EINVAL;
8593                 /* Fiber can only do SPEED_1000.  */
8594                 else if ((cmd->autoneg != AUTONEG_ENABLE) &&
8595                          (cmd->speed != SPEED_1000))
8596                         return -EINVAL;
8597         /* Copper cannot force SPEED_1000.  */
8598         } else if ((cmd->autoneg != AUTONEG_ENABLE) &&
8599                    (cmd->speed == SPEED_1000))
8600                 return -EINVAL;
8601         else if ((cmd->speed == SPEED_1000) &&
8602                  (tp->tg3_flags2 & TG3_FLAG_10_100_ONLY))
8603                 return -EINVAL;
8604
8605         tg3_full_lock(tp, 0);
8606
8607         tp->link_config.autoneg = cmd->autoneg;
8608         if (cmd->autoneg == AUTONEG_ENABLE) {
8609                 tp->link_config.advertising = (cmd->advertising |
8610                                               ADVERTISED_Autoneg);
8611                 tp->link_config.speed = SPEED_INVALID;
8612                 tp->link_config.duplex = DUPLEX_INVALID;
8613         } else {
8614                 tp->link_config.advertising = 0;
8615                 tp->link_config.speed = cmd->speed;
8616                 tp->link_config.duplex = cmd->duplex;
8617         }
8618
8619         tp->link_config.orig_speed = tp->link_config.speed;
8620         tp->link_config.orig_duplex = tp->link_config.duplex;
8621         tp->link_config.orig_autoneg = tp->link_config.autoneg;
8622
8623         if (netif_running(dev))
8624                 tg3_setup_phy(tp, 1);
8625
8626         tg3_full_unlock(tp);
8627
8628         return 0;
8629 }
8630
8631 static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
8632 {
8633         struct tg3 *tp = netdev_priv(dev);
8634
8635         strcpy(info->driver, DRV_MODULE_NAME);
8636         strcpy(info->version, DRV_MODULE_VERSION);
8637         strcpy(info->fw_version, tp->fw_ver);
8638         strcpy(info->bus_info, pci_name(tp->pdev));
8639 }
8640
8641 static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
8642 {
8643         struct tg3 *tp = netdev_priv(dev);
8644
8645         if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
8646                 wol->supported = WAKE_MAGIC;
8647         else
8648                 wol->supported = 0;
8649         wol->wolopts = 0;
8650         if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)
8651                 wol->wolopts = WAKE_MAGIC;
8652         memset(&wol->sopass, 0, sizeof(wol->sopass));
8653 }
8654
8655 static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
8656 {
8657         struct tg3 *tp = netdev_priv(dev);
8658
8659         if (wol->wolopts & ~WAKE_MAGIC)
8660                 return -EINVAL;
8661         if ((wol->wolopts & WAKE_MAGIC) &&
8662             !(tp->tg3_flags & TG3_FLAG_WOL_CAP))
8663                 return -EINVAL;
8664
8665         spin_lock_bh(&tp->lock);
8666         if (wol->wolopts & WAKE_MAGIC)
8667                 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
8668         else
8669                 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
8670         spin_unlock_bh(&tp->lock);
8671
8672         return 0;
8673 }
8674
8675 static u32 tg3_get_msglevel(struct net_device *dev)
8676 {
8677         struct tg3 *tp = netdev_priv(dev);
8678         return tp->msg_enable;
8679 }
8680
8681 static void tg3_set_msglevel(struct net_device *dev, u32 value)
8682 {
8683         struct tg3 *tp = netdev_priv(dev);
8684         tp->msg_enable = value;
8685 }
8686
8687 static int tg3_set_tso(struct net_device *dev, u32 value)
8688 {
8689         struct tg3 *tp = netdev_priv(dev);
8690
8691         if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
8692                 if (value)
8693                         return -EINVAL;
8694                 return 0;
8695         }
8696         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) &&
8697             (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)) {
8698                 if (value) {
8699                         dev->features |= NETIF_F_TSO6;
8700                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
8701                                 dev->features |= NETIF_F_TSO_ECN;
8702                 } else
8703                         dev->features &= ~(NETIF_F_TSO6 | NETIF_F_TSO_ECN);
8704         }
8705         return ethtool_op_set_tso(dev, value);
8706 }
8707
8708 static int tg3_nway_reset(struct net_device *dev)
8709 {
8710         struct tg3 *tp = netdev_priv(dev);
8711         u32 bmcr;
8712         int r;
8713
8714         if (!netif_running(dev))
8715                 return -EAGAIN;
8716
8717         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
8718                 return -EINVAL;
8719
8720         spin_lock_bh(&tp->lock);
8721         r = -EINVAL;
8722         tg3_readphy(tp, MII_BMCR, &bmcr);
8723         if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
8724             ((bmcr & BMCR_ANENABLE) ||
8725              (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT))) {
8726                 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
8727                                            BMCR_ANENABLE);
8728                 r = 0;
8729         }
8730         spin_unlock_bh(&tp->lock);
8731
8732         return r;
8733 }
8734
8735 static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
8736 {
8737         struct tg3 *tp = netdev_priv(dev);
8738
8739         ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
8740         ering->rx_mini_max_pending = 0;
8741         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
8742                 ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
8743         else
8744                 ering->rx_jumbo_max_pending = 0;
8745
8746         ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
8747
8748         ering->rx_pending = tp->rx_pending;
8749         ering->rx_mini_pending = 0;
8750         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
8751                 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
8752         else
8753                 ering->rx_jumbo_pending = 0;
8754
8755         ering->tx_pending = tp->tx_pending;
8756 }
8757
8758 static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
8759 {
8760         struct tg3 *tp = netdev_priv(dev);
8761         int irq_sync = 0, err = 0;
8762
8763         if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
8764             (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
8765             (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
8766             (ering->tx_pending <= MAX_SKB_FRAGS) ||
8767             ((tp->tg3_flags2 & TG3_FLG2_TSO_BUG) &&
8768              (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
8769                 return -EINVAL;
8770
8771         if (netif_running(dev)) {
8772                 tg3_netif_stop(tp);
8773                 irq_sync = 1;
8774         }
8775
8776         tg3_full_lock(tp, irq_sync);
8777
8778         tp->rx_pending = ering->rx_pending;
8779
8780         if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
8781             tp->rx_pending > 63)
8782                 tp->rx_pending = 63;
8783         tp->rx_jumbo_pending = ering->rx_jumbo_pending;
8784         tp->tx_pending = ering->tx_pending;
8785
8786         if (netif_running(dev)) {
8787                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8788                 err = tg3_restart_hw(tp, 1);
8789                 if (!err)
8790                         tg3_netif_start(tp);
8791         }
8792
8793         tg3_full_unlock(tp);
8794
8795         return err;
8796 }
8797
8798 static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
8799 {
8800         struct tg3 *tp = netdev_priv(dev);
8801
8802         epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
8803
8804         if (tp->link_config.active_flowctrl & TG3_FLOW_CTRL_RX)
8805                 epause->rx_pause = 1;
8806         else
8807                 epause->rx_pause = 0;
8808
8809         if (tp->link_config.active_flowctrl & TG3_FLOW_CTRL_TX)
8810                 epause->tx_pause = 1;
8811         else
8812                 epause->tx_pause = 0;
8813 }
8814
8815 static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
8816 {
8817         struct tg3 *tp = netdev_priv(dev);
8818         int irq_sync = 0, err = 0;
8819
8820         if (netif_running(dev)) {
8821                 tg3_netif_stop(tp);
8822                 irq_sync = 1;
8823         }
8824
8825         tg3_full_lock(tp, irq_sync);
8826
8827         if (epause->autoneg)
8828                 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
8829         else
8830                 tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
8831         if (epause->rx_pause)
8832                 tp->link_config.flowctrl |= TG3_FLOW_CTRL_RX;
8833         else
8834                 tp->link_config.flowctrl &= ~TG3_FLOW_CTRL_RX;
8835         if (epause->tx_pause)
8836                 tp->link_config.flowctrl |= TG3_FLOW_CTRL_TX;
8837         else
8838                 tp->link_config.flowctrl &= ~TG3_FLOW_CTRL_TX;
8839
8840         if (netif_running(dev)) {
8841                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8842                 err = tg3_restart_hw(tp, 1);
8843                 if (!err)
8844                         tg3_netif_start(tp);
8845         }
8846
8847         tg3_full_unlock(tp);
8848
8849         return err;
8850 }
8851
8852 static u32 tg3_get_rx_csum(struct net_device *dev)
8853 {
8854         struct tg3 *tp = netdev_priv(dev);
8855         return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
8856 }
8857
8858 static int tg3_set_rx_csum(struct net_device *dev, u32 data)
8859 {
8860         struct tg3 *tp = netdev_priv(dev);
8861
8862         if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
8863                 if (data != 0)
8864                         return -EINVAL;
8865                 return 0;
8866         }
8867
8868         spin_lock_bh(&tp->lock);
8869         if (data)
8870                 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
8871         else
8872                 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
8873         spin_unlock_bh(&tp->lock);
8874
8875         return 0;
8876 }
8877
8878 static int tg3_set_tx_csum(struct net_device *dev, u32 data)
8879 {
8880         struct tg3 *tp = netdev_priv(dev);
8881
8882         if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
8883                 if (data != 0)
8884                         return -EINVAL;
8885                 return 0;
8886         }
8887
8888         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
8889             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
8890             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
8891             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
8892                 ethtool_op_set_tx_ipv6_csum(dev, data);
8893         else
8894                 ethtool_op_set_tx_csum(dev, data);
8895
8896         return 0;
8897 }
8898
8899 static int tg3_get_sset_count (struct net_device *dev, int sset)
8900 {
8901         switch (sset) {
8902         case ETH_SS_TEST:
8903                 return TG3_NUM_TEST;
8904         case ETH_SS_STATS:
8905                 return TG3_NUM_STATS;
8906         default:
8907                 return -EOPNOTSUPP;
8908         }
8909 }
8910
8911 static void tg3_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
8912 {
8913         switch (stringset) {
8914         case ETH_SS_STATS:
8915                 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
8916                 break;
8917         case ETH_SS_TEST:
8918                 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
8919                 break;
8920         default:
8921                 WARN_ON(1);     /* we need a WARN() */
8922                 break;
8923         }
8924 }
8925
8926 static int tg3_phys_id(struct net_device *dev, u32 data)
8927 {
8928         struct tg3 *tp = netdev_priv(dev);
8929         int i;
8930
8931         if (!netif_running(tp->dev))
8932                 return -EAGAIN;
8933
8934         if (data == 0)
8935                 data = UINT_MAX / 2;
8936
8937         for (i = 0; i < (data * 2); i++) {
8938                 if ((i % 2) == 0)
8939                         tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
8940                                            LED_CTRL_1000MBPS_ON |
8941                                            LED_CTRL_100MBPS_ON |
8942                                            LED_CTRL_10MBPS_ON |
8943                                            LED_CTRL_TRAFFIC_OVERRIDE |
8944                                            LED_CTRL_TRAFFIC_BLINK |
8945                                            LED_CTRL_TRAFFIC_LED);
8946
8947                 else
8948                         tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
8949                                            LED_CTRL_TRAFFIC_OVERRIDE);
8950
8951                 if (msleep_interruptible(500))
8952                         break;
8953         }
8954         tw32(MAC_LED_CTRL, tp->led_ctrl);
8955         return 0;
8956 }
8957
8958 static void tg3_get_ethtool_stats (struct net_device *dev,
8959                                    struct ethtool_stats *estats, u64 *tmp_stats)
8960 {
8961         struct tg3 *tp = netdev_priv(dev);
8962         memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
8963 }
8964
8965 #define NVRAM_TEST_SIZE 0x100
8966 #define NVRAM_SELFBOOT_FORMAT1_0_SIZE   0x14
8967 #define NVRAM_SELFBOOT_FORMAT1_2_SIZE   0x18
8968 #define NVRAM_SELFBOOT_FORMAT1_3_SIZE   0x1c
8969 #define NVRAM_SELFBOOT_HW_SIZE 0x20
8970 #define NVRAM_SELFBOOT_DATA_SIZE 0x1c
8971
8972 static int tg3_test_nvram(struct tg3 *tp)
8973 {
8974         u32 csum, magic;
8975         __le32 *buf;
8976         int i, j, k, err = 0, size;
8977
8978         if (tg3_nvram_read_swab(tp, 0, &magic) != 0)
8979                 return -EIO;
8980
8981         if (magic == TG3_EEPROM_MAGIC)
8982                 size = NVRAM_TEST_SIZE;
8983         else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
8984                 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
8985                     TG3_EEPROM_SB_FORMAT_1) {
8986                         switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
8987                         case TG3_EEPROM_SB_REVISION_0:
8988                                 size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
8989                                 break;
8990                         case TG3_EEPROM_SB_REVISION_2:
8991                                 size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
8992                                 break;
8993                         case TG3_EEPROM_SB_REVISION_3:
8994                                 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
8995                                 break;
8996                         default:
8997                                 return 0;
8998                         }
8999                 } else
9000                         return 0;
9001         } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
9002                 size = NVRAM_SELFBOOT_HW_SIZE;
9003         else
9004                 return -EIO;
9005
9006         buf = kmalloc(size, GFP_KERNEL);
9007         if (buf == NULL)
9008                 return -ENOMEM;
9009
9010         err = -EIO;
9011         for (i = 0, j = 0; i < size; i += 4, j++) {
9012                 if ((err = tg3_nvram_read_le(tp, i, &buf[j])) != 0)
9013                         break;
9014         }
9015         if (i < size)
9016                 goto out;
9017
9018         /* Selfboot format */
9019         magic = swab32(le32_to_cpu(buf[0]));
9020         if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
9021             TG3_EEPROM_MAGIC_FW) {
9022                 u8 *buf8 = (u8 *) buf, csum8 = 0;
9023
9024                 if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
9025                     TG3_EEPROM_SB_REVISION_2) {
9026                         /* For rev 2, the csum doesn't include the MBA. */
9027                         for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
9028                                 csum8 += buf8[i];
9029                         for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
9030                                 csum8 += buf8[i];
9031                 } else {
9032                         for (i = 0; i < size; i++)
9033                                 csum8 += buf8[i];
9034                 }
9035
9036                 if (csum8 == 0) {
9037                         err = 0;
9038                         goto out;
9039                 }
9040
9041                 err = -EIO;
9042                 goto out;
9043         }
9044
9045         if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
9046             TG3_EEPROM_MAGIC_HW) {
9047                 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
9048                 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
9049                 u8 *buf8 = (u8 *) buf;
9050
9051                 /* Separate the parity bits and the data bytes.  */
9052                 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
9053                         if ((i == 0) || (i == 8)) {
9054                                 int l;
9055                                 u8 msk;
9056
9057                                 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
9058                                         parity[k++] = buf8[i] & msk;
9059                                 i++;
9060                         }
9061                         else if (i == 16) {
9062                                 int l;
9063                                 u8 msk;
9064
9065                                 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
9066                                         parity[k++] = buf8[i] & msk;
9067                                 i++;
9068
9069                                 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
9070                                         parity[k++] = buf8[i] & msk;
9071                                 i++;
9072                         }
9073                         data[j++] = buf8[i];
9074                 }
9075
9076                 err = -EIO;
9077                 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
9078                         u8 hw8 = hweight8(data[i]);
9079
9080                         if ((hw8 & 0x1) && parity[i])
9081                                 goto out;
9082                         else if (!(hw8 & 0x1) && !parity[i])
9083                                 goto out;
9084                 }
9085                 err = 0;
9086                 goto out;
9087         }
9088
9089         /* Bootstrap checksum at offset 0x10 */
9090         csum = calc_crc((unsigned char *) buf, 0x10);
9091         if(csum != le32_to_cpu(buf[0x10/4]))
9092                 goto out;
9093
9094         /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
9095         csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
9096         if (csum != le32_to_cpu(buf[0xfc/4]))
9097                  goto out;
9098
9099         err = 0;
9100
9101 out:
9102         kfree(buf);
9103         return err;
9104 }
9105
9106 #define TG3_SERDES_TIMEOUT_SEC  2
9107 #define TG3_COPPER_TIMEOUT_SEC  6
9108
9109 static int tg3_test_link(struct tg3 *tp)
9110 {
9111         int i, max;
9112
9113         if (!netif_running(tp->dev))
9114                 return -ENODEV;
9115
9116         if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
9117                 max = TG3_SERDES_TIMEOUT_SEC;
9118         else
9119                 max = TG3_COPPER_TIMEOUT_SEC;
9120
9121         for (i = 0; i < max; i++) {
9122                 if (netif_carrier_ok(tp->dev))
9123                         return 0;
9124
9125                 if (msleep_interruptible(1000))
9126                         break;
9127         }
9128
9129         return -EIO;
9130 }
9131
9132 /* Only test the commonly used registers */
9133 static int tg3_test_registers(struct tg3 *tp)
9134 {
9135         int i, is_5705, is_5750;
9136         u32 offset, read_mask, write_mask, val, save_val, read_val;
9137         static struct {
9138                 u16 offset;
9139                 u16 flags;
9140 #define TG3_FL_5705     0x1
9141 #define TG3_FL_NOT_5705 0x2
9142 #define TG3_FL_NOT_5788 0x4
9143 #define TG3_FL_NOT_5750 0x8
9144                 u32 read_mask;
9145                 u32 write_mask;
9146         } reg_tbl[] = {
9147                 /* MAC Control Registers */
9148                 { MAC_MODE, TG3_FL_NOT_5705,
9149                         0x00000000, 0x00ef6f8c },
9150                 { MAC_MODE, TG3_FL_5705,
9151                         0x00000000, 0x01ef6b8c },
9152                 { MAC_STATUS, TG3_FL_NOT_5705,
9153                         0x03800107, 0x00000000 },
9154                 { MAC_STATUS, TG3_FL_5705,
9155                         0x03800100, 0x00000000 },
9156                 { MAC_ADDR_0_HIGH, 0x0000,
9157                         0x00000000, 0x0000ffff },
9158                 { MAC_ADDR_0_LOW, 0x0000,
9159                         0x00000000, 0xffffffff },
9160                 { MAC_RX_MTU_SIZE, 0x0000,
9161                         0x00000000, 0x0000ffff },
9162                 { MAC_TX_MODE, 0x0000,
9163                         0x00000000, 0x00000070 },
9164                 { MAC_TX_LENGTHS, 0x0000,
9165                         0x00000000, 0x00003fff },
9166                 { MAC_RX_MODE, TG3_FL_NOT_5705,
9167                         0x00000000, 0x000007fc },
9168                 { MAC_RX_MODE, TG3_FL_5705,
9169                         0x00000000, 0x000007dc },
9170                 { MAC_HASH_REG_0, 0x0000,
9171                         0x00000000, 0xffffffff },
9172                 { MAC_HASH_REG_1, 0x0000,
9173                         0x00000000, 0xffffffff },
9174                 { MAC_HASH_REG_2, 0x0000,
9175                         0x00000000, 0xffffffff },
9176                 { MAC_HASH_REG_3, 0x0000,
9177                         0x00000000, 0xffffffff },
9178
9179                 /* Receive Data and Receive BD Initiator Control Registers. */
9180                 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
9181                         0x00000000, 0xffffffff },
9182                 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
9183                         0x00000000, 0xffffffff },
9184                 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
9185                         0x00000000, 0x00000003 },
9186                 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
9187                         0x00000000, 0xffffffff },
9188                 { RCVDBDI_STD_BD+0, 0x0000,
9189                         0x00000000, 0xffffffff },
9190                 { RCVDBDI_STD_BD+4, 0x0000,
9191                         0x00000000, 0xffffffff },
9192                 { RCVDBDI_STD_BD+8, 0x0000,
9193                         0x00000000, 0xffff0002 },
9194                 { RCVDBDI_STD_BD+0xc, 0x0000,
9195                         0x00000000, 0xffffffff },
9196
9197                 /* Receive BD Initiator Control Registers. */
9198                 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
9199                         0x00000000, 0xffffffff },
9200                 { RCVBDI_STD_THRESH, TG3_FL_5705,
9201                         0x00000000, 0x000003ff },
9202                 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
9203                         0x00000000, 0xffffffff },
9204
9205                 /* Host Coalescing Control Registers. */
9206                 { HOSTCC_MODE, TG3_FL_NOT_5705,
9207                         0x00000000, 0x00000004 },
9208                 { HOSTCC_MODE, TG3_FL_5705,
9209                         0x00000000, 0x000000f6 },
9210                 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
9211                         0x00000000, 0xffffffff },
9212                 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
9213                         0x00000000, 0x000003ff },
9214                 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
9215                         0x00000000, 0xffffffff },
9216                 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
9217                         0x00000000, 0x000003ff },
9218                 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
9219                         0x00000000, 0xffffffff },
9220                 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
9221                         0x00000000, 0x000000ff },
9222                 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
9223                         0x00000000, 0xffffffff },
9224                 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
9225                         0x00000000, 0x000000ff },
9226                 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
9227                         0x00000000, 0xffffffff },
9228                 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
9229                         0x00000000, 0xffffffff },
9230                 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
9231                         0x00000000, 0xffffffff },
9232                 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
9233                         0x00000000, 0x000000ff },
9234                 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
9235                         0x00000000, 0xffffffff },
9236                 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
9237                         0x00000000, 0x000000ff },
9238                 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
9239                         0x00000000, 0xffffffff },
9240                 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
9241                         0x00000000, 0xffffffff },
9242                 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
9243                         0x00000000, 0xffffffff },
9244                 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
9245                         0x00000000, 0xffffffff },
9246                 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
9247                         0x00000000, 0xffffffff },
9248                 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
9249                         0xffffffff, 0x00000000 },
9250                 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
9251                         0xffffffff, 0x00000000 },
9252
9253                 /* Buffer Manager Control Registers. */
9254                 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
9255                         0x00000000, 0x007fff80 },
9256                 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
9257                         0x00000000, 0x007fffff },
9258                 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
9259                         0x00000000, 0x0000003f },
9260                 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
9261                         0x00000000, 0x000001ff },
9262                 { BUFMGR_MB_HIGH_WATER, 0x0000,
9263                         0x00000000, 0x000001ff },
9264                 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
9265                         0xffffffff, 0x00000000 },
9266                 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
9267                         0xffffffff, 0x00000000 },
9268
9269                 /* Mailbox Registers */
9270                 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
9271                         0x00000000, 0x000001ff },
9272                 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
9273                         0x00000000, 0x000001ff },
9274                 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
9275                         0x00000000, 0x000007ff },
9276                 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
9277                         0x00000000, 0x000001ff },
9278
9279                 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
9280         };
9281
9282         is_5705 = is_5750 = 0;
9283         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
9284                 is_5705 = 1;
9285                 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
9286                         is_5750 = 1;
9287         }
9288
9289         for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
9290                 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
9291                         continue;
9292
9293                 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
9294                         continue;
9295
9296                 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
9297                     (reg_tbl[i].flags & TG3_FL_NOT_5788))
9298                         continue;
9299
9300                 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
9301                         continue;
9302
9303                 offset = (u32) reg_tbl[i].offset;
9304                 read_mask = reg_tbl[i].read_mask;
9305                 write_mask = reg_tbl[i].write_mask;
9306
9307                 /* Save the original register content */
9308                 save_val = tr32(offset);
9309
9310                 /* Determine the read-only value. */
9311                 read_val = save_val & read_mask;
9312
9313                 /* Write zero to the register, then make sure the read-only bits
9314                  * are not changed and the read/write bits are all zeros.
9315                  */
9316                 tw32(offset, 0);
9317
9318                 val = tr32(offset);
9319
9320                 /* Test the read-only and read/write bits. */
9321                 if (((val & read_mask) != read_val) || (val & write_mask))
9322                         goto out;
9323
9324                 /* Write ones to all the bits defined by RdMask and WrMask, then
9325                  * make sure the read-only bits are not changed and the
9326                  * read/write bits are all ones.
9327                  */
9328                 tw32(offset, read_mask | write_mask);
9329
9330                 val = tr32(offset);
9331
9332                 /* Test the read-only bits. */
9333                 if ((val & read_mask) != read_val)
9334                         goto out;
9335
9336                 /* Test the read/write bits. */
9337                 if ((val & write_mask) != write_mask)
9338                         goto out;
9339
9340                 tw32(offset, save_val);
9341         }
9342
9343         return 0;
9344
9345 out:
9346         if (netif_msg_hw(tp))
9347                 printk(KERN_ERR PFX "Register test failed at offset %x\n",
9348                        offset);
9349         tw32(offset, save_val);
9350         return -EIO;
9351 }
9352
9353 static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
9354 {
9355         static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
9356         int i;
9357         u32 j;
9358
9359         for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
9360                 for (j = 0; j < len; j += 4) {
9361                         u32 val;
9362
9363                         tg3_write_mem(tp, offset + j, test_pattern[i]);
9364                         tg3_read_mem(tp, offset + j, &val);
9365                         if (val != test_pattern[i])
9366                                 return -EIO;
9367                 }
9368         }
9369         return 0;
9370 }
9371
9372 static int tg3_test_memory(struct tg3 *tp)
9373 {
9374         static struct mem_entry {
9375                 u32 offset;
9376                 u32 len;
9377         } mem_tbl_570x[] = {
9378                 { 0x00000000, 0x00b50},
9379                 { 0x00002000, 0x1c000},
9380                 { 0xffffffff, 0x00000}
9381         }, mem_tbl_5705[] = {
9382                 { 0x00000100, 0x0000c},
9383                 { 0x00000200, 0x00008},
9384                 { 0x00004000, 0x00800},
9385                 { 0x00006000, 0x01000},
9386                 { 0x00008000, 0x02000},
9387                 { 0x00010000, 0x0e000},
9388                 { 0xffffffff, 0x00000}
9389         }, mem_tbl_5755[] = {
9390                 { 0x00000200, 0x00008},
9391                 { 0x00004000, 0x00800},
9392                 { 0x00006000, 0x00800},
9393                 { 0x00008000, 0x02000},
9394                 { 0x00010000, 0x0c000},
9395                 { 0xffffffff, 0x00000}
9396         }, mem_tbl_5906[] = {
9397                 { 0x00000200, 0x00008},
9398                 { 0x00004000, 0x00400},
9399                 { 0x00006000, 0x00400},
9400                 { 0x00008000, 0x01000},
9401                 { 0x00010000, 0x01000},
9402                 { 0xffffffff, 0x00000}
9403         };
9404         struct mem_entry *mem_tbl;
9405         int err = 0;
9406         int i;
9407
9408         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
9409                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
9410                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
9411                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
9412                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
9413                         mem_tbl = mem_tbl_5755;
9414                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
9415                         mem_tbl = mem_tbl_5906;
9416                 else
9417                         mem_tbl = mem_tbl_5705;
9418         } else
9419                 mem_tbl = mem_tbl_570x;
9420
9421         for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
9422                 if ((err = tg3_do_mem_test(tp, mem_tbl[i].offset,
9423                     mem_tbl[i].len)) != 0)
9424                         break;
9425         }
9426
9427         return err;
9428 }
9429
9430 #define TG3_MAC_LOOPBACK        0
9431 #define TG3_PHY_LOOPBACK        1
9432
9433 static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
9434 {
9435         u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
9436         u32 desc_idx;
9437         struct sk_buff *skb, *rx_skb;
9438         u8 *tx_data;
9439         dma_addr_t map;
9440         int num_pkts, tx_len, rx_len, i, err;
9441         struct tg3_rx_buffer_desc *desc;
9442
9443         if (loopback_mode == TG3_MAC_LOOPBACK) {
9444                 /* HW errata - mac loopback fails in some cases on 5780.
9445                  * Normal traffic and PHY loopback are not affected by
9446                  * errata.
9447                  */
9448                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
9449                         return 0;
9450
9451                 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
9452                            MAC_MODE_PORT_INT_LPBACK;
9453                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
9454                         mac_mode |= MAC_MODE_LINK_POLARITY;
9455                 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
9456                         mac_mode |= MAC_MODE_PORT_MODE_MII;
9457                 else
9458                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
9459                 tw32(MAC_MODE, mac_mode);
9460         } else if (loopback_mode == TG3_PHY_LOOPBACK) {
9461                 u32 val;
9462
9463                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
9464                         u32 phytest;
9465
9466                         if (!tg3_readphy(tp, MII_TG3_EPHY_TEST, &phytest)) {
9467                                 u32 phy;
9468
9469                                 tg3_writephy(tp, MII_TG3_EPHY_TEST,
9470                                              phytest | MII_TG3_EPHY_SHADOW_EN);
9471                                 if (!tg3_readphy(tp, 0x1b, &phy))
9472                                         tg3_writephy(tp, 0x1b, phy & ~0x20);
9473                                 tg3_writephy(tp, MII_TG3_EPHY_TEST, phytest);
9474                         }
9475                         val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
9476                 } else
9477                         val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
9478
9479                 tg3_phy_toggle_automdix(tp, 0);
9480
9481                 tg3_writephy(tp, MII_BMCR, val);
9482                 udelay(40);
9483
9484                 mac_mode = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
9485                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
9486                         tg3_writephy(tp, MII_TG3_EPHY_PTEST, 0x1800);
9487                         mac_mode |= MAC_MODE_PORT_MODE_MII;
9488                 } else
9489                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
9490
9491                 /* reset to prevent losing 1st rx packet intermittently */
9492                 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
9493                         tw32_f(MAC_RX_MODE, RX_MODE_RESET);
9494                         udelay(10);
9495                         tw32_f(MAC_RX_MODE, tp->rx_mode);
9496                 }
9497                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
9498                         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)
9499                                 mac_mode &= ~MAC_MODE_LINK_POLARITY;
9500                         else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411)
9501                                 mac_mode |= MAC_MODE_LINK_POLARITY;
9502                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
9503                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
9504                 }
9505                 tw32(MAC_MODE, mac_mode);
9506         }
9507         else
9508                 return -EINVAL;
9509
9510         err = -EIO;
9511
9512         tx_len = 1514;
9513         skb = netdev_alloc_skb(tp->dev, tx_len);
9514         if (!skb)
9515                 return -ENOMEM;
9516
9517         tx_data = skb_put(skb, tx_len);
9518         memcpy(tx_data, tp->dev->dev_addr, 6);
9519         memset(tx_data + 6, 0x0, 8);
9520
9521         tw32(MAC_RX_MTU_SIZE, tx_len + 4);
9522
9523         for (i = 14; i < tx_len; i++)
9524                 tx_data[i] = (u8) (i & 0xff);
9525
9526         map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
9527
9528         tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
9529              HOSTCC_MODE_NOW);
9530
9531         udelay(10);
9532
9533         rx_start_idx = tp->hw_status->idx[0].rx_producer;
9534
9535         num_pkts = 0;
9536
9537         tg3_set_txd(tp, tp->tx_prod, map, tx_len, 0, 1);
9538
9539         tp->tx_prod++;
9540         num_pkts++;
9541
9542         tw32_tx_mbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW,
9543                      tp->tx_prod);
9544         tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW);
9545
9546         udelay(10);
9547
9548         /* 250 usec to allow enough time on some 10/100 Mbps devices.  */
9549         for (i = 0; i < 25; i++) {
9550                 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
9551                        HOSTCC_MODE_NOW);
9552
9553                 udelay(10);
9554
9555                 tx_idx = tp->hw_status->idx[0].tx_consumer;
9556                 rx_idx = tp->hw_status->idx[0].rx_producer;
9557                 if ((tx_idx == tp->tx_prod) &&
9558                     (rx_idx == (rx_start_idx + num_pkts)))
9559                         break;
9560         }
9561
9562         pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE);
9563         dev_kfree_skb(skb);
9564
9565         if (tx_idx != tp->tx_prod)
9566                 goto out;
9567
9568         if (rx_idx != rx_start_idx + num_pkts)
9569                 goto out;
9570
9571         desc = &tp->rx_rcb[rx_start_idx];
9572         desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
9573         opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
9574         if (opaque_key != RXD_OPAQUE_RING_STD)
9575                 goto out;
9576
9577         if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
9578             (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
9579                 goto out;
9580
9581         rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
9582         if (rx_len != tx_len)
9583                 goto out;
9584
9585         rx_skb = tp->rx_std_buffers[desc_idx].skb;
9586
9587         map = pci_unmap_addr(&tp->rx_std_buffers[desc_idx], mapping);
9588         pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
9589
9590         for (i = 14; i < tx_len; i++) {
9591                 if (*(rx_skb->data + i) != (u8) (i & 0xff))
9592                         goto out;
9593         }
9594         err = 0;
9595
9596         /* tg3_free_rings will unmap and free the rx_skb */
9597 out:
9598         return err;
9599 }
9600
9601 #define TG3_MAC_LOOPBACK_FAILED         1
9602 #define TG3_PHY_LOOPBACK_FAILED         2
9603 #define TG3_LOOPBACK_FAILED             (TG3_MAC_LOOPBACK_FAILED |      \
9604                                          TG3_PHY_LOOPBACK_FAILED)
9605
9606 static int tg3_test_loopback(struct tg3 *tp)
9607 {
9608         int err = 0;
9609         u32 cpmuctrl = 0;
9610
9611         if (!netif_running(tp->dev))
9612                 return TG3_LOOPBACK_FAILED;
9613
9614         err = tg3_reset_hw(tp, 1);
9615         if (err)
9616                 return TG3_LOOPBACK_FAILED;
9617
9618         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
9619             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
9620                 int i;
9621                 u32 status;
9622
9623                 tw32(TG3_CPMU_MUTEX_REQ, CPMU_MUTEX_REQ_DRIVER);
9624
9625                 /* Wait for up to 40 microseconds to acquire lock. */
9626                 for (i = 0; i < 4; i++) {
9627                         status = tr32(TG3_CPMU_MUTEX_GNT);
9628                         if (status == CPMU_MUTEX_GNT_DRIVER)
9629                                 break;
9630                         udelay(10);
9631                 }
9632
9633                 if (status != CPMU_MUTEX_GNT_DRIVER)
9634                         return TG3_LOOPBACK_FAILED;
9635
9636                 /* Turn off link-based power management. */
9637                 cpmuctrl = tr32(TG3_CPMU_CTRL);
9638                 tw32(TG3_CPMU_CTRL,
9639                      cpmuctrl & ~(CPMU_CTRL_LINK_SPEED_MODE |
9640                                   CPMU_CTRL_LINK_AWARE_MODE));
9641         }
9642
9643         if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
9644                 err |= TG3_MAC_LOOPBACK_FAILED;
9645
9646         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
9647             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
9648                 tw32(TG3_CPMU_CTRL, cpmuctrl);
9649
9650                 /* Release the mutex */
9651                 tw32(TG3_CPMU_MUTEX_GNT, CPMU_MUTEX_GNT_DRIVER);
9652         }
9653
9654         if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
9655                 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
9656                         err |= TG3_PHY_LOOPBACK_FAILED;
9657         }
9658
9659         return err;
9660 }
9661
9662 static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
9663                           u64 *data)
9664 {
9665         struct tg3 *tp = netdev_priv(dev);
9666
9667         if (tp->link_config.phy_is_low_power)
9668                 tg3_set_power_state(tp, PCI_D0);
9669
9670         memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
9671
9672         if (tg3_test_nvram(tp) != 0) {
9673                 etest->flags |= ETH_TEST_FL_FAILED;
9674                 data[0] = 1;
9675         }
9676         if (tg3_test_link(tp) != 0) {
9677                 etest->flags |= ETH_TEST_FL_FAILED;
9678                 data[1] = 1;
9679         }
9680         if (etest->flags & ETH_TEST_FL_OFFLINE) {
9681                 int err, irq_sync = 0;
9682
9683                 if (netif_running(dev)) {
9684                         tg3_netif_stop(tp);
9685                         irq_sync = 1;
9686                 }
9687
9688                 tg3_full_lock(tp, irq_sync);
9689
9690                 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
9691                 err = tg3_nvram_lock(tp);
9692                 tg3_halt_cpu(tp, RX_CPU_BASE);
9693                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
9694                         tg3_halt_cpu(tp, TX_CPU_BASE);
9695                 if (!err)
9696                         tg3_nvram_unlock(tp);
9697
9698                 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
9699                         tg3_phy_reset(tp);
9700
9701                 if (tg3_test_registers(tp) != 0) {
9702                         etest->flags |= ETH_TEST_FL_FAILED;
9703                         data[2] = 1;
9704                 }
9705                 if (tg3_test_memory(tp) != 0) {
9706                         etest->flags |= ETH_TEST_FL_FAILED;
9707                         data[3] = 1;
9708                 }
9709                 if ((data[4] = tg3_test_loopback(tp)) != 0)
9710                         etest->flags |= ETH_TEST_FL_FAILED;
9711
9712                 tg3_full_unlock(tp);
9713
9714                 if (tg3_test_interrupt(tp) != 0) {
9715                         etest->flags |= ETH_TEST_FL_FAILED;
9716                         data[5] = 1;
9717                 }
9718
9719                 tg3_full_lock(tp, 0);
9720
9721                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9722                 if (netif_running(dev)) {
9723                         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
9724                         if (!tg3_restart_hw(tp, 1))
9725                                 tg3_netif_start(tp);
9726                 }
9727
9728                 tg3_full_unlock(tp);
9729         }
9730         if (tp->link_config.phy_is_low_power)
9731                 tg3_set_power_state(tp, PCI_D3hot);
9732
9733 }
9734
9735 static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
9736 {
9737         struct mii_ioctl_data *data = if_mii(ifr);
9738         struct tg3 *tp = netdev_priv(dev);
9739         int err;
9740
9741         switch(cmd) {
9742         case SIOCGMIIPHY:
9743                 data->phy_id = PHY_ADDR;
9744
9745                 /* fallthru */
9746         case SIOCGMIIREG: {
9747                 u32 mii_regval;
9748
9749                 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
9750                         break;                  /* We have no PHY */
9751
9752                 if (tp->link_config.phy_is_low_power)
9753                         return -EAGAIN;
9754
9755                 spin_lock_bh(&tp->lock);
9756                 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
9757                 spin_unlock_bh(&tp->lock);
9758
9759                 data->val_out = mii_regval;
9760
9761                 return err;
9762         }
9763
9764         case SIOCSMIIREG:
9765                 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
9766                         break;                  /* We have no PHY */
9767
9768                 if (!capable(CAP_NET_ADMIN))
9769                         return -EPERM;
9770
9771                 if (tp->link_config.phy_is_low_power)
9772                         return -EAGAIN;
9773
9774                 spin_lock_bh(&tp->lock);
9775                 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
9776                 spin_unlock_bh(&tp->lock);
9777
9778                 return err;
9779
9780         default:
9781                 /* do nothing */
9782                 break;
9783         }
9784         return -EOPNOTSUPP;
9785 }
9786
9787 #if TG3_VLAN_TAG_USED
9788 static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
9789 {
9790         struct tg3 *tp = netdev_priv(dev);
9791
9792         if (netif_running(dev))
9793                 tg3_netif_stop(tp);
9794
9795         tg3_full_lock(tp, 0);
9796
9797         tp->vlgrp = grp;
9798
9799         /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
9800         __tg3_set_rx_mode(dev);
9801
9802         if (netif_running(dev))
9803                 tg3_netif_start(tp);
9804
9805         tg3_full_unlock(tp);
9806 }
9807 #endif
9808
9809 static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
9810 {
9811         struct tg3 *tp = netdev_priv(dev);
9812
9813         memcpy(ec, &tp->coal, sizeof(*ec));
9814         return 0;
9815 }
9816
9817 static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
9818 {
9819         struct tg3 *tp = netdev_priv(dev);
9820         u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
9821         u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
9822
9823         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
9824                 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
9825                 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
9826                 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
9827                 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
9828         }
9829
9830         if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
9831             (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
9832             (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
9833             (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
9834             (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
9835             (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
9836             (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
9837             (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
9838             (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
9839             (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
9840                 return -EINVAL;
9841
9842         /* No rx interrupts will be generated if both are zero */
9843         if ((ec->rx_coalesce_usecs == 0) &&
9844             (ec->rx_max_coalesced_frames == 0))
9845                 return -EINVAL;
9846
9847         /* No tx interrupts will be generated if both are zero */
9848         if ((ec->tx_coalesce_usecs == 0) &&
9849             (ec->tx_max_coalesced_frames == 0))
9850                 return -EINVAL;
9851
9852         /* Only copy relevant parameters, ignore all others. */
9853         tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
9854         tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
9855         tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
9856         tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
9857         tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
9858         tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
9859         tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
9860         tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
9861         tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
9862
9863         if (netif_running(dev)) {
9864                 tg3_full_lock(tp, 0);
9865                 __tg3_set_coalesce(tp, &tp->coal);
9866                 tg3_full_unlock(tp);
9867         }
9868         return 0;
9869 }
9870
9871 static const struct ethtool_ops tg3_ethtool_ops = {
9872         .get_settings           = tg3_get_settings,
9873         .set_settings           = tg3_set_settings,
9874         .get_drvinfo            = tg3_get_drvinfo,
9875         .get_regs_len           = tg3_get_regs_len,
9876         .get_regs               = tg3_get_regs,
9877         .get_wol                = tg3_get_wol,
9878         .set_wol                = tg3_set_wol,
9879         .get_msglevel           = tg3_get_msglevel,
9880         .set_msglevel           = tg3_set_msglevel,
9881         .nway_reset             = tg3_nway_reset,
9882         .get_link               = ethtool_op_get_link,
9883         .get_eeprom_len         = tg3_get_eeprom_len,
9884         .get_eeprom             = tg3_get_eeprom,
9885         .set_eeprom             = tg3_set_eeprom,
9886         .get_ringparam          = tg3_get_ringparam,
9887         .set_ringparam          = tg3_set_ringparam,
9888         .get_pauseparam         = tg3_get_pauseparam,
9889         .set_pauseparam         = tg3_set_pauseparam,
9890         .get_rx_csum            = tg3_get_rx_csum,
9891         .set_rx_csum            = tg3_set_rx_csum,
9892         .set_tx_csum            = tg3_set_tx_csum,
9893         .set_sg                 = ethtool_op_set_sg,
9894         .set_tso                = tg3_set_tso,
9895         .self_test              = tg3_self_test,
9896         .get_strings            = tg3_get_strings,
9897         .phys_id                = tg3_phys_id,
9898         .get_ethtool_stats      = tg3_get_ethtool_stats,
9899         .get_coalesce           = tg3_get_coalesce,
9900         .set_coalesce           = tg3_set_coalesce,
9901         .get_sset_count         = tg3_get_sset_count,
9902 };
9903
9904 static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
9905 {
9906         u32 cursize, val, magic;
9907
9908         tp->nvram_size = EEPROM_CHIP_SIZE;
9909
9910         if (tg3_nvram_read_swab(tp, 0, &magic) != 0)
9911                 return;
9912
9913         if ((magic != TG3_EEPROM_MAGIC) &&
9914             ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
9915             ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
9916                 return;
9917
9918         /*
9919          * Size the chip by reading offsets at increasing powers of two.
9920          * When we encounter our validation signature, we know the addressing
9921          * has wrapped around, and thus have our chip size.
9922          */
9923         cursize = 0x10;
9924
9925         while (cursize < tp->nvram_size) {
9926                 if (tg3_nvram_read_swab(tp, cursize, &val) != 0)
9927                         return;
9928
9929                 if (val == magic)
9930                         break;
9931
9932                 cursize <<= 1;
9933         }
9934
9935         tp->nvram_size = cursize;
9936 }
9937
9938 static void __devinit tg3_get_nvram_size(struct tg3 *tp)
9939 {
9940         u32 val;
9941
9942         if (tg3_nvram_read_swab(tp, 0, &val) != 0)
9943                 return;
9944
9945         /* Selfboot format */
9946         if (val != TG3_EEPROM_MAGIC) {
9947                 tg3_get_eeprom_size(tp);
9948                 return;
9949         }
9950
9951         if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
9952                 if (val != 0) {
9953                         tp->nvram_size = (val >> 16) * 1024;
9954                         return;
9955                 }
9956         }
9957         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
9958 }
9959
9960 static void __devinit tg3_get_nvram_info(struct tg3 *tp)
9961 {
9962         u32 nvcfg1;
9963
9964         nvcfg1 = tr32(NVRAM_CFG1);
9965         if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
9966                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
9967         }
9968         else {
9969                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
9970                 tw32(NVRAM_CFG1, nvcfg1);
9971         }
9972
9973         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
9974             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
9975                 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
9976                         case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
9977                                 tp->nvram_jedecnum = JEDEC_ATMEL;
9978                                 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
9979                                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9980                                 break;
9981                         case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
9982                                 tp->nvram_jedecnum = JEDEC_ATMEL;
9983                                 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
9984                                 break;
9985                         case FLASH_VENDOR_ATMEL_EEPROM:
9986                                 tp->nvram_jedecnum = JEDEC_ATMEL;
9987                                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
9988                                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9989                                 break;
9990                         case FLASH_VENDOR_ST:
9991                                 tp->nvram_jedecnum = JEDEC_ST;
9992                                 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
9993                                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9994                                 break;
9995                         case FLASH_VENDOR_SAIFUN:
9996                                 tp->nvram_jedecnum = JEDEC_SAIFUN;
9997                                 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
9998                                 break;
9999                         case FLASH_VENDOR_SST_SMALL:
10000                         case FLASH_VENDOR_SST_LARGE:
10001                                 tp->nvram_jedecnum = JEDEC_SST;
10002                                 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
10003                                 break;
10004                 }
10005         }
10006         else {
10007                 tp->nvram_jedecnum = JEDEC_ATMEL;
10008                 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
10009                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10010         }
10011 }
10012
10013 static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
10014 {
10015         u32 nvcfg1;
10016
10017         nvcfg1 = tr32(NVRAM_CFG1);
10018
10019         /* NVRAM protection for TPM */
10020         if (nvcfg1 & (1 << 27))
10021                 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
10022
10023         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10024                 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
10025                 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
10026                         tp->nvram_jedecnum = JEDEC_ATMEL;
10027                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10028                         break;
10029                 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
10030                         tp->nvram_jedecnum = JEDEC_ATMEL;
10031                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10032                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
10033                         break;
10034                 case FLASH_5752VENDOR_ST_M45PE10:
10035                 case FLASH_5752VENDOR_ST_M45PE20:
10036                 case FLASH_5752VENDOR_ST_M45PE40:
10037                         tp->nvram_jedecnum = JEDEC_ST;
10038                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10039                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
10040                         break;
10041         }
10042
10043         if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
10044                 switch (nvcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
10045                         case FLASH_5752PAGE_SIZE_256:
10046                                 tp->nvram_pagesize = 256;
10047                                 break;
10048                         case FLASH_5752PAGE_SIZE_512:
10049                                 tp->nvram_pagesize = 512;
10050                                 break;
10051                         case FLASH_5752PAGE_SIZE_1K:
10052                                 tp->nvram_pagesize = 1024;
10053                                 break;
10054                         case FLASH_5752PAGE_SIZE_2K:
10055                                 tp->nvram_pagesize = 2048;
10056                                 break;
10057                         case FLASH_5752PAGE_SIZE_4K:
10058                                 tp->nvram_pagesize = 4096;
10059                                 break;
10060                         case FLASH_5752PAGE_SIZE_264:
10061                                 tp->nvram_pagesize = 264;
10062                                 break;
10063                 }
10064         }
10065         else {
10066                 /* For eeprom, set pagesize to maximum eeprom size */
10067                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10068
10069                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10070                 tw32(NVRAM_CFG1, nvcfg1);
10071         }
10072 }
10073
10074 static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
10075 {
10076         u32 nvcfg1, protect = 0;
10077
10078         nvcfg1 = tr32(NVRAM_CFG1);
10079
10080         /* NVRAM protection for TPM */
10081         if (nvcfg1 & (1 << 27)) {
10082                 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
10083                 protect = 1;
10084         }
10085
10086         nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
10087         switch (nvcfg1) {
10088                 case FLASH_5755VENDOR_ATMEL_FLASH_1:
10089                 case FLASH_5755VENDOR_ATMEL_FLASH_2:
10090                 case FLASH_5755VENDOR_ATMEL_FLASH_3:
10091                 case FLASH_5755VENDOR_ATMEL_FLASH_5:
10092                         tp->nvram_jedecnum = JEDEC_ATMEL;
10093                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10094                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
10095                         tp->nvram_pagesize = 264;
10096                         if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
10097                             nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
10098                                 tp->nvram_size = (protect ? 0x3e200 :
10099                                                   TG3_NVRAM_SIZE_512KB);
10100                         else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
10101                                 tp->nvram_size = (protect ? 0x1f200 :
10102                                                   TG3_NVRAM_SIZE_256KB);
10103                         else
10104                                 tp->nvram_size = (protect ? 0x1f200 :
10105                                                   TG3_NVRAM_SIZE_128KB);
10106                         break;
10107                 case FLASH_5752VENDOR_ST_M45PE10:
10108                 case FLASH_5752VENDOR_ST_M45PE20:
10109                 case FLASH_5752VENDOR_ST_M45PE40:
10110                         tp->nvram_jedecnum = JEDEC_ST;
10111                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10112                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
10113                         tp->nvram_pagesize = 256;
10114                         if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
10115                                 tp->nvram_size = (protect ?
10116                                                   TG3_NVRAM_SIZE_64KB :
10117                                                   TG3_NVRAM_SIZE_128KB);
10118                         else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
10119                                 tp->nvram_size = (protect ?
10120                                                   TG3_NVRAM_SIZE_64KB :
10121                                                   TG3_NVRAM_SIZE_256KB);
10122                         else
10123                                 tp->nvram_size = (protect ?
10124                                                   TG3_NVRAM_SIZE_128KB :
10125                                                   TG3_NVRAM_SIZE_512KB);
10126                         break;
10127         }
10128 }
10129
10130 static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
10131 {
10132         u32 nvcfg1;
10133
10134         nvcfg1 = tr32(NVRAM_CFG1);
10135
10136         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10137                 case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
10138                 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
10139                 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
10140                 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
10141                         tp->nvram_jedecnum = JEDEC_ATMEL;
10142                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10143                         tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10144
10145                         nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10146                         tw32(NVRAM_CFG1, nvcfg1);
10147                         break;
10148                 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
10149                 case FLASH_5755VENDOR_ATMEL_FLASH_1:
10150                 case FLASH_5755VENDOR_ATMEL_FLASH_2:
10151                 case FLASH_5755VENDOR_ATMEL_FLASH_3:
10152                         tp->nvram_jedecnum = JEDEC_ATMEL;
10153                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10154                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
10155                         tp->nvram_pagesize = 264;
10156                         break;
10157                 case FLASH_5752VENDOR_ST_M45PE10:
10158                 case FLASH_5752VENDOR_ST_M45PE20:
10159                 case FLASH_5752VENDOR_ST_M45PE40:
10160                         tp->nvram_jedecnum = JEDEC_ST;
10161                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10162                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
10163                         tp->nvram_pagesize = 256;
10164                         break;
10165         }
10166 }
10167
10168 static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp)
10169 {
10170         u32 nvcfg1, protect = 0;
10171
10172         nvcfg1 = tr32(NVRAM_CFG1);
10173
10174         /* NVRAM protection for TPM */
10175         if (nvcfg1 & (1 << 27)) {
10176                 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
10177                 protect = 1;
10178         }
10179
10180         nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
10181         switch (nvcfg1) {
10182                 case FLASH_5761VENDOR_ATMEL_ADB021D:
10183                 case FLASH_5761VENDOR_ATMEL_ADB041D:
10184                 case FLASH_5761VENDOR_ATMEL_ADB081D:
10185                 case FLASH_5761VENDOR_ATMEL_ADB161D:
10186                 case FLASH_5761VENDOR_ATMEL_MDB021D:
10187                 case FLASH_5761VENDOR_ATMEL_MDB041D:
10188                 case FLASH_5761VENDOR_ATMEL_MDB081D:
10189                 case FLASH_5761VENDOR_ATMEL_MDB161D:
10190                         tp->nvram_jedecnum = JEDEC_ATMEL;
10191                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10192                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
10193                         tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10194                         tp->nvram_pagesize = 256;
10195                         break;
10196                 case FLASH_5761VENDOR_ST_A_M45PE20:
10197                 case FLASH_5761VENDOR_ST_A_M45PE40:
10198                 case FLASH_5761VENDOR_ST_A_M45PE80:
10199                 case FLASH_5761VENDOR_ST_A_M45PE16:
10200                 case FLASH_5761VENDOR_ST_M_M45PE20:
10201                 case FLASH_5761VENDOR_ST_M_M45PE40:
10202                 case FLASH_5761VENDOR_ST_M_M45PE80:
10203                 case FLASH_5761VENDOR_ST_M_M45PE16:
10204                         tp->nvram_jedecnum = JEDEC_ST;
10205                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10206                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
10207                         tp->nvram_pagesize = 256;
10208                         break;
10209         }
10210
10211         if (protect) {
10212                 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
10213         } else {
10214                 switch (nvcfg1) {
10215                         case FLASH_5761VENDOR_ATMEL_ADB161D:
10216                         case FLASH_5761VENDOR_ATMEL_MDB161D:
10217                         case FLASH_5761VENDOR_ST_A_M45PE16:
10218                         case FLASH_5761VENDOR_ST_M_M45PE16:
10219                                 tp->nvram_size = TG3_NVRAM_SIZE_2MB;
10220                                 break;
10221                         case FLASH_5761VENDOR_ATMEL_ADB081D:
10222                         case FLASH_5761VENDOR_ATMEL_MDB081D:
10223                         case FLASH_5761VENDOR_ST_A_M45PE80:
10224                         case FLASH_5761VENDOR_ST_M_M45PE80:
10225                                 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
10226                                 break;
10227                         case FLASH_5761VENDOR_ATMEL_ADB041D:
10228                         case FLASH_5761VENDOR_ATMEL_MDB041D:
10229                         case FLASH_5761VENDOR_ST_A_M45PE40:
10230                         case FLASH_5761VENDOR_ST_M_M45PE40:
10231                                 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
10232                                 break;
10233                         case FLASH_5761VENDOR_ATMEL_ADB021D:
10234                         case FLASH_5761VENDOR_ATMEL_MDB021D:
10235                         case FLASH_5761VENDOR_ST_A_M45PE20:
10236                         case FLASH_5761VENDOR_ST_M_M45PE20:
10237                                 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
10238                                 break;
10239                 }
10240         }
10241 }
10242
10243 static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
10244 {
10245         tp->nvram_jedecnum = JEDEC_ATMEL;
10246         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10247         tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10248 }
10249
10250 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
10251 static void __devinit tg3_nvram_init(struct tg3 *tp)
10252 {
10253         tw32_f(GRC_EEPROM_ADDR,
10254              (EEPROM_ADDR_FSM_RESET |
10255               (EEPROM_DEFAULT_CLOCK_PERIOD <<
10256                EEPROM_ADDR_CLKPERD_SHIFT)));
10257
10258         msleep(1);
10259
10260         /* Enable seeprom accesses. */
10261         tw32_f(GRC_LOCAL_CTRL,
10262              tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
10263         udelay(100);
10264
10265         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
10266             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
10267                 tp->tg3_flags |= TG3_FLAG_NVRAM;
10268
10269                 if (tg3_nvram_lock(tp)) {
10270                         printk(KERN_WARNING PFX "%s: Cannot get nvarm lock, "
10271                                "tg3_nvram_init failed.\n", tp->dev->name);
10272                         return;
10273                 }
10274                 tg3_enable_nvram_access(tp);
10275
10276                 tp->nvram_size = 0;
10277
10278                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
10279                         tg3_get_5752_nvram_info(tp);
10280                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
10281                         tg3_get_5755_nvram_info(tp);
10282                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
10283                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784)
10284                         tg3_get_5787_nvram_info(tp);
10285                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
10286                         tg3_get_5761_nvram_info(tp);
10287                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10288                         tg3_get_5906_nvram_info(tp);
10289                 else
10290                         tg3_get_nvram_info(tp);
10291
10292                 if (tp->nvram_size == 0)
10293                         tg3_get_nvram_size(tp);
10294
10295                 tg3_disable_nvram_access(tp);
10296                 tg3_nvram_unlock(tp);
10297
10298         } else {
10299                 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
10300
10301                 tg3_get_eeprom_size(tp);
10302         }
10303 }
10304
10305 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
10306                                         u32 offset, u32 *val)
10307 {
10308         u32 tmp;
10309         int i;
10310
10311         if (offset > EEPROM_ADDR_ADDR_MASK ||
10312             (offset % 4) != 0)
10313                 return -EINVAL;
10314
10315         tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
10316                                         EEPROM_ADDR_DEVID_MASK |
10317                                         EEPROM_ADDR_READ);
10318         tw32(GRC_EEPROM_ADDR,
10319              tmp |
10320              (0 << EEPROM_ADDR_DEVID_SHIFT) |
10321              ((offset << EEPROM_ADDR_ADDR_SHIFT) &
10322               EEPROM_ADDR_ADDR_MASK) |
10323              EEPROM_ADDR_READ | EEPROM_ADDR_START);
10324
10325         for (i = 0; i < 1000; i++) {
10326                 tmp = tr32(GRC_EEPROM_ADDR);
10327
10328                 if (tmp & EEPROM_ADDR_COMPLETE)
10329                         break;
10330                 msleep(1);
10331         }
10332         if (!(tmp & EEPROM_ADDR_COMPLETE))
10333                 return -EBUSY;
10334
10335         *val = tr32(GRC_EEPROM_DATA);
10336         return 0;
10337 }
10338
10339 #define NVRAM_CMD_TIMEOUT 10000
10340
10341 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
10342 {
10343         int i;
10344
10345         tw32(NVRAM_CMD, nvram_cmd);
10346         for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
10347                 udelay(10);
10348                 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
10349                         udelay(10);
10350                         break;
10351                 }
10352         }
10353         if (i == NVRAM_CMD_TIMEOUT) {
10354                 return -EBUSY;
10355         }
10356         return 0;
10357 }
10358
10359 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
10360 {
10361         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
10362             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
10363             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
10364            !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
10365             (tp->nvram_jedecnum == JEDEC_ATMEL))
10366
10367                 addr = ((addr / tp->nvram_pagesize) <<
10368                         ATMEL_AT45DB0X1B_PAGE_POS) +
10369                        (addr % tp->nvram_pagesize);
10370
10371         return addr;
10372 }
10373
10374 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
10375 {
10376         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
10377             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
10378             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
10379            !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
10380             (tp->nvram_jedecnum == JEDEC_ATMEL))
10381
10382                 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
10383                         tp->nvram_pagesize) +
10384                        (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
10385
10386         return addr;
10387 }
10388
10389 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
10390 {
10391         int ret;
10392
10393         if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
10394                 return tg3_nvram_read_using_eeprom(tp, offset, val);
10395
10396         offset = tg3_nvram_phys_addr(tp, offset);
10397
10398         if (offset > NVRAM_ADDR_MSK)
10399                 return -EINVAL;
10400
10401         ret = tg3_nvram_lock(tp);
10402         if (ret)
10403                 return ret;
10404
10405         tg3_enable_nvram_access(tp);
10406
10407         tw32(NVRAM_ADDR, offset);
10408         ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
10409                 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
10410
10411         if (ret == 0)
10412                 *val = swab32(tr32(NVRAM_RDDATA));
10413
10414         tg3_disable_nvram_access(tp);
10415
10416         tg3_nvram_unlock(tp);
10417
10418         return ret;
10419 }
10420
10421 static int tg3_nvram_read_le(struct tg3 *tp, u32 offset, __le32 *val)
10422 {
10423         u32 v;
10424         int res = tg3_nvram_read(tp, offset, &v);
10425         if (!res)
10426                 *val = cpu_to_le32(v);
10427         return res;
10428 }
10429
10430 static int tg3_nvram_read_swab(struct tg3 *tp, u32 offset, u32 *val)
10431 {
10432         int err;
10433         u32 tmp;
10434
10435         err = tg3_nvram_read(tp, offset, &tmp);
10436         *val = swab32(tmp);
10437         return err;
10438 }
10439
10440 static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
10441                                     u32 offset, u32 len, u8 *buf)
10442 {
10443         int i, j, rc = 0;
10444         u32 val;
10445
10446         for (i = 0; i < len; i += 4) {
10447                 u32 addr;
10448                 __le32 data;
10449
10450                 addr = offset + i;
10451
10452                 memcpy(&data, buf + i, 4);
10453
10454                 tw32(GRC_EEPROM_DATA, le32_to_cpu(data));
10455
10456                 val = tr32(GRC_EEPROM_ADDR);
10457                 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
10458
10459                 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
10460                         EEPROM_ADDR_READ);
10461                 tw32(GRC_EEPROM_ADDR, val |
10462                         (0 << EEPROM_ADDR_DEVID_SHIFT) |
10463                         (addr & EEPROM_ADDR_ADDR_MASK) |
10464                         EEPROM_ADDR_START |
10465                         EEPROM_ADDR_WRITE);
10466
10467                 for (j = 0; j < 1000; j++) {
10468                         val = tr32(GRC_EEPROM_ADDR);
10469
10470                         if (val & EEPROM_ADDR_COMPLETE)
10471                                 break;
10472                         msleep(1);
10473                 }
10474                 if (!(val & EEPROM_ADDR_COMPLETE)) {
10475                         rc = -EBUSY;
10476                         break;
10477                 }
10478         }
10479
10480         return rc;
10481 }
10482
10483 /* offset and length are dword aligned */
10484 static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
10485                 u8 *buf)
10486 {
10487         int ret = 0;
10488         u32 pagesize = tp->nvram_pagesize;
10489         u32 pagemask = pagesize - 1;
10490         u32 nvram_cmd;
10491         u8 *tmp;
10492
10493         tmp = kmalloc(pagesize, GFP_KERNEL);
10494         if (tmp == NULL)
10495                 return -ENOMEM;
10496
10497         while (len) {
10498                 int j;
10499                 u32 phy_addr, page_off, size;
10500
10501                 phy_addr = offset & ~pagemask;
10502
10503                 for (j = 0; j < pagesize; j += 4) {
10504                         if ((ret = tg3_nvram_read_le(tp, phy_addr + j,
10505                                                 (__le32 *) (tmp + j))))
10506                                 break;
10507                 }
10508                 if (ret)
10509                         break;
10510
10511                 page_off = offset & pagemask;
10512                 size = pagesize;
10513                 if (len < size)
10514                         size = len;
10515
10516                 len -= size;
10517
10518                 memcpy(tmp + page_off, buf, size);
10519
10520                 offset = offset + (pagesize - page_off);
10521
10522                 tg3_enable_nvram_access(tp);
10523
10524                 /*
10525                  * Before we can erase the flash page, we need
10526                  * to issue a special "write enable" command.
10527                  */
10528                 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
10529
10530                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
10531                         break;
10532
10533                 /* Erase the target page */
10534                 tw32(NVRAM_ADDR, phy_addr);
10535
10536                 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
10537                         NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
10538
10539                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
10540                         break;
10541
10542                 /* Issue another write enable to start the write. */
10543                 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
10544
10545                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
10546                         break;
10547
10548                 for (j = 0; j < pagesize; j += 4) {
10549                         __be32 data;
10550
10551                         data = *((__be32 *) (tmp + j));
10552                         /* swab32(le32_to_cpu(data)), actually */
10553                         tw32(NVRAM_WRDATA, be32_to_cpu(data));
10554
10555                         tw32(NVRAM_ADDR, phy_addr + j);
10556
10557                         nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
10558                                 NVRAM_CMD_WR;
10559
10560                         if (j == 0)
10561                                 nvram_cmd |= NVRAM_CMD_FIRST;
10562                         else if (j == (pagesize - 4))
10563                                 nvram_cmd |= NVRAM_CMD_LAST;
10564
10565                         if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
10566                                 break;
10567                 }
10568                 if (ret)
10569                         break;
10570         }
10571
10572         nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
10573         tg3_nvram_exec_cmd(tp, nvram_cmd);
10574
10575         kfree(tmp);
10576
10577         return ret;
10578 }
10579
10580 /* offset and length are dword aligned */
10581 static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
10582                 u8 *buf)
10583 {
10584         int i, ret = 0;
10585
10586         for (i = 0; i < len; i += 4, offset += 4) {
10587                 u32 page_off, phy_addr, nvram_cmd;
10588                 __be32 data;
10589
10590                 memcpy(&data, buf + i, 4);
10591                 tw32(NVRAM_WRDATA, be32_to_cpu(data));
10592
10593                 page_off = offset % tp->nvram_pagesize;
10594
10595                 phy_addr = tg3_nvram_phys_addr(tp, offset);
10596
10597                 tw32(NVRAM_ADDR, phy_addr);
10598
10599                 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
10600
10601                 if ((page_off == 0) || (i == 0))
10602                         nvram_cmd |= NVRAM_CMD_FIRST;
10603                 if (page_off == (tp->nvram_pagesize - 4))
10604                         nvram_cmd |= NVRAM_CMD_LAST;
10605
10606                 if (i == (len - 4))
10607                         nvram_cmd |= NVRAM_CMD_LAST;
10608
10609                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752) &&
10610                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5755) &&
10611                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5787) &&
10612                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784) &&
10613                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) &&
10614                     (tp->nvram_jedecnum == JEDEC_ST) &&
10615                     (nvram_cmd & NVRAM_CMD_FIRST)) {
10616
10617                         if ((ret = tg3_nvram_exec_cmd(tp,
10618                                 NVRAM_CMD_WREN | NVRAM_CMD_GO |
10619                                 NVRAM_CMD_DONE)))
10620
10621                                 break;
10622                 }
10623                 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
10624                         /* We always do complete word writes to eeprom. */
10625                         nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
10626                 }
10627
10628                 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
10629                         break;
10630         }
10631         return ret;
10632 }
10633
10634 /* offset and length are dword aligned */
10635 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
10636 {
10637         int ret;
10638
10639         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
10640                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
10641                        ~GRC_LCLCTRL_GPIO_OUTPUT1);
10642                 udelay(40);
10643         }
10644
10645         if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
10646                 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
10647         }
10648         else {
10649                 u32 grc_mode;
10650
10651                 ret = tg3_nvram_lock(tp);
10652                 if (ret)
10653                         return ret;
10654
10655                 tg3_enable_nvram_access(tp);
10656                 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
10657                     !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM))
10658                         tw32(NVRAM_WRITE1, 0x406);
10659
10660                 grc_mode = tr32(GRC_MODE);
10661                 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
10662
10663                 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
10664                         !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
10665
10666                         ret = tg3_nvram_write_block_buffered(tp, offset, len,
10667                                 buf);
10668                 }
10669                 else {
10670                         ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
10671                                 buf);
10672                 }
10673
10674                 grc_mode = tr32(GRC_MODE);
10675                 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
10676
10677                 tg3_disable_nvram_access(tp);
10678                 tg3_nvram_unlock(tp);
10679         }
10680
10681         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
10682                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
10683                 udelay(40);
10684         }
10685
10686         return ret;
10687 }
10688
10689 struct subsys_tbl_ent {
10690         u16 subsys_vendor, subsys_devid;
10691         u32 phy_id;
10692 };
10693
10694 static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
10695         /* Broadcom boards. */
10696         { PCI_VENDOR_ID_BROADCOM, 0x1644, PHY_ID_BCM5401 }, /* BCM95700A6 */
10697         { PCI_VENDOR_ID_BROADCOM, 0x0001, PHY_ID_BCM5701 }, /* BCM95701A5 */
10698         { PCI_VENDOR_ID_BROADCOM, 0x0002, PHY_ID_BCM8002 }, /* BCM95700T6 */
10699         { PCI_VENDOR_ID_BROADCOM, 0x0003, 0 },              /* BCM95700A9 */
10700         { PCI_VENDOR_ID_BROADCOM, 0x0005, PHY_ID_BCM5701 }, /* BCM95701T1 */
10701         { PCI_VENDOR_ID_BROADCOM, 0x0006, PHY_ID_BCM5701 }, /* BCM95701T8 */
10702         { PCI_VENDOR_ID_BROADCOM, 0x0007, 0 },              /* BCM95701A7 */
10703         { PCI_VENDOR_ID_BROADCOM, 0x0008, PHY_ID_BCM5701 }, /* BCM95701A10 */
10704         { PCI_VENDOR_ID_BROADCOM, 0x8008, PHY_ID_BCM5701 }, /* BCM95701A12 */
10705         { PCI_VENDOR_ID_BROADCOM, 0x0009, PHY_ID_BCM5703 }, /* BCM95703Ax1 */
10706         { PCI_VENDOR_ID_BROADCOM, 0x8009, PHY_ID_BCM5703 }, /* BCM95703Ax2 */
10707
10708         /* 3com boards. */
10709         { PCI_VENDOR_ID_3COM, 0x1000, PHY_ID_BCM5401 }, /* 3C996T */
10710         { PCI_VENDOR_ID_3COM, 0x1006, PHY_ID_BCM5701 }, /* 3C996BT */
10711         { PCI_VENDOR_ID_3COM, 0x1004, 0 },              /* 3C996SX */
10712         { PCI_VENDOR_ID_3COM, 0x1007, PHY_ID_BCM5701 }, /* 3C1000T */
10713         { PCI_VENDOR_ID_3COM, 0x1008, PHY_ID_BCM5701 }, /* 3C940BR01 */
10714
10715         /* DELL boards. */
10716         { PCI_VENDOR_ID_DELL, 0x00d1, PHY_ID_BCM5401 }, /* VIPER */
10717         { PCI_VENDOR_ID_DELL, 0x0106, PHY_ID_BCM5401 }, /* JAGUAR */
10718         { PCI_VENDOR_ID_DELL, 0x0109, PHY_ID_BCM5411 }, /* MERLOT */
10719         { PCI_VENDOR_ID_DELL, 0x010a, PHY_ID_BCM5411 }, /* SLIM_MERLOT */
10720
10721         /* Compaq boards. */
10722         { PCI_VENDOR_ID_COMPAQ, 0x007c, PHY_ID_BCM5701 }, /* BANSHEE */
10723         { PCI_VENDOR_ID_COMPAQ, 0x009a, PHY_ID_BCM5701 }, /* BANSHEE_2 */
10724         { PCI_VENDOR_ID_COMPAQ, 0x007d, 0 },              /* CHANGELING */
10725         { PCI_VENDOR_ID_COMPAQ, 0x0085, PHY_ID_BCM5701 }, /* NC7780 */
10726         { PCI_VENDOR_ID_COMPAQ, 0x0099, PHY_ID_BCM5701 }, /* NC7780_2 */
10727
10728         /* IBM boards. */
10729         { PCI_VENDOR_ID_IBM, 0x0281, 0 } /* IBM??? */
10730 };
10731
10732 static inline struct subsys_tbl_ent *lookup_by_subsys(struct tg3 *tp)
10733 {
10734         int i;
10735
10736         for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
10737                 if ((subsys_id_to_phy_id[i].subsys_vendor ==
10738                      tp->pdev->subsystem_vendor) &&
10739                     (subsys_id_to_phy_id[i].subsys_devid ==
10740                      tp->pdev->subsystem_device))
10741                         return &subsys_id_to_phy_id[i];
10742         }
10743         return NULL;
10744 }
10745
10746 static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
10747 {
10748         u32 val;
10749         u16 pmcsr;
10750
10751         /* On some early chips the SRAM cannot be accessed in D3hot state,
10752          * so need make sure we're in D0.
10753          */
10754         pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
10755         pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
10756         pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
10757         msleep(1);
10758
10759         /* Make sure register accesses (indirect or otherwise)
10760          * will function correctly.
10761          */
10762         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
10763                                tp->misc_host_ctrl);
10764
10765         /* The memory arbiter has to be enabled in order for SRAM accesses
10766          * to succeed.  Normally on powerup the tg3 chip firmware will make
10767          * sure it is enabled, but other entities such as system netboot
10768          * code might disable it.
10769          */
10770         val = tr32(MEMARB_MODE);
10771         tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
10772
10773         tp->phy_id = PHY_ID_INVALID;
10774         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
10775
10776         /* Assume an onboard device and WOL capable by default.  */
10777         tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT | TG3_FLAG_WOL_CAP;
10778
10779         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
10780                 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
10781                         tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
10782                         tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
10783                 }
10784                 val = tr32(VCPU_CFGSHDW);
10785                 if (val & VCPU_CFGSHDW_ASPM_DBNC)
10786                         tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
10787                 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
10788                     (val & VCPU_CFGSHDW_WOL_MAGPKT))
10789                         tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
10790                 return;
10791         }
10792
10793         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
10794         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
10795                 u32 nic_cfg, led_cfg;
10796                 u32 nic_phy_id, ver, cfg2 = 0, eeprom_phy_id;
10797                 int eeprom_phy_serdes = 0;
10798
10799                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
10800                 tp->nic_sram_data_cfg = nic_cfg;
10801
10802                 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
10803                 ver >>= NIC_SRAM_DATA_VER_SHIFT;
10804                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
10805                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
10806                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
10807                     (ver > 0) && (ver < 0x100))
10808                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
10809
10810                 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
10811                     NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
10812                         eeprom_phy_serdes = 1;
10813
10814                 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
10815                 if (nic_phy_id != 0) {
10816                         u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
10817                         u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
10818
10819                         eeprom_phy_id  = (id1 >> 16) << 10;
10820                         eeprom_phy_id |= (id2 & 0xfc00) << 16;
10821                         eeprom_phy_id |= (id2 & 0x03ff) <<  0;
10822                 } else
10823                         eeprom_phy_id = 0;
10824
10825                 tp->phy_id = eeprom_phy_id;
10826                 if (eeprom_phy_serdes) {
10827                         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
10828                                 tp->tg3_flags2 |= TG3_FLG2_MII_SERDES;
10829                         else
10830                                 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
10831                 }
10832
10833                 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
10834                         led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
10835                                     SHASTA_EXT_LED_MODE_MASK);
10836                 else
10837                         led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
10838
10839                 switch (led_cfg) {
10840                 default:
10841                 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
10842                         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
10843                         break;
10844
10845                 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
10846                         tp->led_ctrl = LED_CTRL_MODE_PHY_2;
10847                         break;
10848
10849                 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
10850                         tp->led_ctrl = LED_CTRL_MODE_MAC;
10851
10852                         /* Default to PHY_1_MODE if 0 (MAC_MODE) is
10853                          * read on some older 5700/5701 bootcode.
10854                          */
10855                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
10856                             ASIC_REV_5700 ||
10857                             GET_ASIC_REV(tp->pci_chip_rev_id) ==
10858                             ASIC_REV_5701)
10859                                 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
10860
10861                         break;
10862
10863                 case SHASTA_EXT_LED_SHARED:
10864                         tp->led_ctrl = LED_CTRL_MODE_SHARED;
10865                         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
10866                             tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
10867                                 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
10868                                                  LED_CTRL_MODE_PHY_2);
10869                         break;
10870
10871                 case SHASTA_EXT_LED_MAC:
10872                         tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
10873                         break;
10874
10875                 case SHASTA_EXT_LED_COMBO:
10876                         tp->led_ctrl = LED_CTRL_MODE_COMBO;
10877                         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
10878                                 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
10879                                                  LED_CTRL_MODE_PHY_2);
10880                         break;
10881
10882                 }
10883
10884                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
10885                      GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
10886                     tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
10887                         tp->led_ctrl = LED_CTRL_MODE_PHY_2;
10888
10889                 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX)
10890                         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
10891
10892                 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
10893                         tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
10894                         if ((tp->pdev->subsystem_vendor ==
10895                              PCI_VENDOR_ID_ARIMA) &&
10896                             (tp->pdev->subsystem_device == 0x205a ||
10897                              tp->pdev->subsystem_device == 0x2063))
10898                                 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
10899                 } else {
10900                         tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
10901                         tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
10902                 }
10903
10904                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
10905                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
10906                         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
10907                                 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
10908                 }
10909                 if (nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE)
10910                         tp->tg3_flags3 |= TG3_FLG3_ENABLE_APE;
10911                 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES &&
10912                     !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
10913                         tp->tg3_flags &= ~TG3_FLAG_WOL_CAP;
10914
10915                 if (tp->tg3_flags & TG3_FLAG_WOL_CAP &&
10916                     nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE)
10917                         tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
10918
10919                 if (cfg2 & (1 << 17))
10920                         tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING;
10921
10922                 /* serdes signal pre-emphasis in register 0x590 set by */
10923                 /* bootcode if bit 18 is set */
10924                 if (cfg2 & (1 << 18))
10925                         tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS;
10926
10927                 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
10928                         u32 cfg3;
10929
10930                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
10931                         if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
10932                                 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
10933                 }
10934         }
10935 }
10936
10937 static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
10938 {
10939         int i;
10940         u32 val;
10941
10942         tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
10943         tw32(OTP_CTRL, cmd);
10944
10945         /* Wait for up to 1 ms for command to execute. */
10946         for (i = 0; i < 100; i++) {
10947                 val = tr32(OTP_STATUS);
10948                 if (val & OTP_STATUS_CMD_DONE)
10949                         break;
10950                 udelay(10);
10951         }
10952
10953         return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
10954 }
10955
10956 /* Read the gphy configuration from the OTP region of the chip.  The gphy
10957  * configuration is a 32-bit value that straddles the alignment boundary.
10958  * We do two 32-bit reads and then shift and merge the results.
10959  */
10960 static u32 __devinit tg3_read_otp_phycfg(struct tg3 *tp)
10961 {
10962         u32 bhalf_otp, thalf_otp;
10963
10964         tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
10965
10966         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
10967                 return 0;
10968
10969         tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
10970
10971         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
10972                 return 0;
10973
10974         thalf_otp = tr32(OTP_READ_DATA);
10975
10976         tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
10977
10978         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
10979                 return 0;
10980
10981         bhalf_otp = tr32(OTP_READ_DATA);
10982
10983         return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
10984 }
10985
10986 static int __devinit tg3_phy_probe(struct tg3 *tp)
10987 {
10988         u32 hw_phy_id_1, hw_phy_id_2;
10989         u32 hw_phy_id, hw_phy_id_masked;
10990         int err;
10991
10992         /* Reading the PHY ID register can conflict with ASF
10993          * firwmare access to the PHY hardware.
10994          */
10995         err = 0;
10996         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
10997             (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
10998                 hw_phy_id = hw_phy_id_masked = PHY_ID_INVALID;
10999         } else {
11000                 /* Now read the physical PHY_ID from the chip and verify
11001                  * that it is sane.  If it doesn't look good, we fall back
11002                  * to either the hard-coded table based PHY_ID and failing
11003                  * that the value found in the eeprom area.
11004                  */
11005                 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
11006                 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
11007
11008                 hw_phy_id  = (hw_phy_id_1 & 0xffff) << 10;
11009                 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
11010                 hw_phy_id |= (hw_phy_id_2 & 0x03ff) <<  0;
11011
11012                 hw_phy_id_masked = hw_phy_id & PHY_ID_MASK;
11013         }
11014
11015         if (!err && KNOWN_PHY_ID(hw_phy_id_masked)) {
11016                 tp->phy_id = hw_phy_id;
11017                 if (hw_phy_id_masked == PHY_ID_BCM8002)
11018                         tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
11019                 else
11020                         tp->tg3_flags2 &= ~TG3_FLG2_PHY_SERDES;
11021         } else {
11022                 if (tp->phy_id != PHY_ID_INVALID) {
11023                         /* Do nothing, phy ID already set up in
11024                          * tg3_get_eeprom_hw_cfg().
11025                          */
11026                 } else {
11027                         struct subsys_tbl_ent *p;
11028
11029                         /* No eeprom signature?  Try the hardcoded
11030                          * subsys device table.
11031                          */
11032                         p = lookup_by_subsys(tp);
11033                         if (!p)
11034                                 return -ENODEV;
11035
11036                         tp->phy_id = p->phy_id;
11037                         if (!tp->phy_id ||
11038                             tp->phy_id == PHY_ID_BCM8002)
11039                                 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
11040                 }
11041         }
11042
11043         if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) &&
11044             !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) &&
11045             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
11046                 u32 bmsr, adv_reg, tg3_ctrl, mask;
11047
11048                 tg3_readphy(tp, MII_BMSR, &bmsr);
11049                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
11050                     (bmsr & BMSR_LSTATUS))
11051                         goto skip_phy_reset;
11052
11053                 err = tg3_phy_reset(tp);
11054                 if (err)
11055                         return err;
11056
11057                 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
11058                            ADVERTISE_100HALF | ADVERTISE_100FULL |
11059                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
11060                 tg3_ctrl = 0;
11061                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
11062                         tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
11063                                     MII_TG3_CTRL_ADV_1000_FULL);
11064                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
11065                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
11066                                 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
11067                                              MII_TG3_CTRL_ENABLE_AS_MASTER);
11068                 }
11069
11070                 mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
11071                         ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
11072                         ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
11073                 if (!tg3_copper_is_advertising_all(tp, mask)) {
11074                         tg3_writephy(tp, MII_ADVERTISE, adv_reg);
11075
11076                         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
11077                                 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
11078
11079                         tg3_writephy(tp, MII_BMCR,
11080                                      BMCR_ANENABLE | BMCR_ANRESTART);
11081                 }
11082                 tg3_phy_set_wirespeed(tp);
11083
11084                 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
11085                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
11086                         tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
11087         }
11088
11089 skip_phy_reset:
11090         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
11091                 err = tg3_init_5401phy_dsp(tp);
11092                 if (err)
11093                         return err;
11094         }
11095
11096         if (!err && ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)) {
11097                 err = tg3_init_5401phy_dsp(tp);
11098         }
11099
11100         if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
11101                 tp->link_config.advertising =
11102                         (ADVERTISED_1000baseT_Half |
11103                          ADVERTISED_1000baseT_Full |
11104                          ADVERTISED_Autoneg |
11105                          ADVERTISED_FIBRE);
11106         if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
11107                 tp->link_config.advertising &=
11108                         ~(ADVERTISED_1000baseT_Half |
11109                           ADVERTISED_1000baseT_Full);
11110
11111         return err;
11112 }
11113
11114 static void __devinit tg3_read_partno(struct tg3 *tp)
11115 {
11116         unsigned char vpd_data[256];
11117         unsigned int i;
11118         u32 magic;
11119
11120         if (tg3_nvram_read_swab(tp, 0x0, &magic))
11121                 goto out_not_found;
11122
11123         if (magic == TG3_EEPROM_MAGIC) {
11124                 for (i = 0; i < 256; i += 4) {
11125                         u32 tmp;
11126
11127                         if (tg3_nvram_read(tp, 0x100 + i, &tmp))
11128                                 goto out_not_found;
11129
11130                         vpd_data[i + 0] = ((tmp >>  0) & 0xff);
11131                         vpd_data[i + 1] = ((tmp >>  8) & 0xff);
11132                         vpd_data[i + 2] = ((tmp >> 16) & 0xff);
11133                         vpd_data[i + 3] = ((tmp >> 24) & 0xff);
11134                 }
11135         } else {
11136                 int vpd_cap;
11137
11138                 vpd_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_VPD);
11139                 for (i = 0; i < 256; i += 4) {
11140                         u32 tmp, j = 0;
11141                         __le32 v;
11142                         u16 tmp16;
11143
11144                         pci_write_config_word(tp->pdev, vpd_cap + PCI_VPD_ADDR,
11145                                               i);
11146                         while (j++ < 100) {
11147                                 pci_read_config_word(tp->pdev, vpd_cap +
11148                                                      PCI_VPD_ADDR, &tmp16);
11149                                 if (tmp16 & 0x8000)
11150                                         break;
11151                                 msleep(1);
11152                         }
11153                         if (!(tmp16 & 0x8000))
11154                                 goto out_not_found;
11155
11156                         pci_read_config_dword(tp->pdev, vpd_cap + PCI_VPD_DATA,
11157                                               &tmp);
11158                         v = cpu_to_le32(tmp);
11159                         memcpy(&vpd_data[i], &v, 4);
11160                 }
11161         }
11162
11163         /* Now parse and find the part number. */
11164         for (i = 0; i < 254; ) {
11165                 unsigned char val = vpd_data[i];
11166                 unsigned int block_end;
11167
11168                 if (val == 0x82 || val == 0x91) {
11169                         i = (i + 3 +
11170                              (vpd_data[i + 1] +
11171                               (vpd_data[i + 2] << 8)));
11172                         continue;
11173                 }
11174
11175                 if (val != 0x90)
11176                         goto out_not_found;
11177
11178                 block_end = (i + 3 +
11179                              (vpd_data[i + 1] +
11180                               (vpd_data[i + 2] << 8)));
11181                 i += 3;
11182
11183                 if (block_end > 256)
11184                         goto out_not_found;
11185
11186                 while (i < (block_end - 2)) {
11187                         if (vpd_data[i + 0] == 'P' &&
11188                             vpd_data[i + 1] == 'N') {
11189                                 int partno_len = vpd_data[i + 2];
11190
11191                                 i += 3;
11192                                 if (partno_len > 24 || (partno_len + i) > 256)
11193                                         goto out_not_found;
11194
11195                                 memcpy(tp->board_part_number,
11196                                        &vpd_data[i], partno_len);
11197
11198                                 /* Success. */
11199                                 return;
11200                         }
11201                         i += 3 + vpd_data[i + 2];
11202                 }
11203
11204                 /* Part number not found. */
11205                 goto out_not_found;
11206         }
11207
11208 out_not_found:
11209         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11210                 strcpy(tp->board_part_number, "BCM95906");
11211         else
11212                 strcpy(tp->board_part_number, "none");
11213 }
11214
11215 static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
11216 {
11217         u32 val;
11218
11219         if (tg3_nvram_read_swab(tp, offset, &val) ||
11220             (val & 0xfc000000) != 0x0c000000 ||
11221             tg3_nvram_read_swab(tp, offset + 4, &val) ||
11222             val != 0)
11223                 return 0;
11224
11225         return 1;
11226 }
11227
11228 static void __devinit tg3_read_fw_ver(struct tg3 *tp)
11229 {
11230         u32 val, offset, start;
11231         u32 ver_offset;
11232         int i, bcnt;
11233
11234         if (tg3_nvram_read_swab(tp, 0, &val))
11235                 return;
11236
11237         if (val != TG3_EEPROM_MAGIC)
11238                 return;
11239
11240         if (tg3_nvram_read_swab(tp, 0xc, &offset) ||
11241             tg3_nvram_read_swab(tp, 0x4, &start))
11242                 return;
11243
11244         offset = tg3_nvram_logical_addr(tp, offset);
11245
11246         if (!tg3_fw_img_is_valid(tp, offset) ||
11247             tg3_nvram_read_swab(tp, offset + 8, &ver_offset))
11248                 return;
11249
11250         offset = offset + ver_offset - start;
11251         for (i = 0; i < 16; i += 4) {
11252                 __le32 v;
11253                 if (tg3_nvram_read_le(tp, offset + i, &v))
11254                         return;
11255
11256                 memcpy(tp->fw_ver + i, &v, 4);
11257         }
11258
11259         if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
11260              (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
11261                 return;
11262
11263         for (offset = TG3_NVM_DIR_START;
11264              offset < TG3_NVM_DIR_END;
11265              offset += TG3_NVM_DIRENT_SIZE) {
11266                 if (tg3_nvram_read_swab(tp, offset, &val))
11267                         return;
11268
11269                 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
11270                         break;
11271         }
11272
11273         if (offset == TG3_NVM_DIR_END)
11274                 return;
11275
11276         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
11277                 start = 0x08000000;
11278         else if (tg3_nvram_read_swab(tp, offset - 4, &start))
11279                 return;
11280
11281         if (tg3_nvram_read_swab(tp, offset + 4, &offset) ||
11282             !tg3_fw_img_is_valid(tp, offset) ||
11283             tg3_nvram_read_swab(tp, offset + 8, &val))
11284                 return;
11285
11286         offset += val - start;
11287
11288         bcnt = strlen(tp->fw_ver);
11289
11290         tp->fw_ver[bcnt++] = ',';
11291         tp->fw_ver[bcnt++] = ' ';
11292
11293         for (i = 0; i < 4; i++) {
11294                 __le32 v;
11295                 if (tg3_nvram_read_le(tp, offset, &v))
11296                         return;
11297
11298                 offset += sizeof(v);
11299
11300                 if (bcnt > TG3_VER_SIZE - sizeof(v)) {
11301                         memcpy(&tp->fw_ver[bcnt], &v, TG3_VER_SIZE - bcnt);
11302                         break;
11303                 }
11304
11305                 memcpy(&tp->fw_ver[bcnt], &v, sizeof(v));
11306                 bcnt += sizeof(v);
11307         }
11308
11309         tp->fw_ver[TG3_VER_SIZE - 1] = 0;
11310 }
11311
11312 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *);
11313
11314 static int __devinit tg3_get_invariants(struct tg3 *tp)
11315 {
11316         static struct pci_device_id write_reorder_chipsets[] = {
11317                 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
11318                              PCI_DEVICE_ID_AMD_FE_GATE_700C) },
11319                 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
11320                              PCI_DEVICE_ID_AMD_8131_BRIDGE) },
11321                 { PCI_DEVICE(PCI_VENDOR_ID_VIA,
11322                              PCI_DEVICE_ID_VIA_8385_0) },
11323                 { },
11324         };
11325         u32 misc_ctrl_reg;
11326         u32 cacheline_sz_reg;
11327         u32 pci_state_reg, grc_misc_cfg;
11328         u32 val;
11329         u16 pci_cmd;
11330         int err, pcie_cap;
11331
11332         /* Force memory write invalidate off.  If we leave it on,
11333          * then on 5700_BX chips we have to enable a workaround.
11334          * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
11335          * to match the cacheline size.  The Broadcom driver have this
11336          * workaround but turns MWI off all the times so never uses
11337          * it.  This seems to suggest that the workaround is insufficient.
11338          */
11339         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
11340         pci_cmd &= ~PCI_COMMAND_INVALIDATE;
11341         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
11342
11343         /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
11344          * has the register indirect write enable bit set before
11345          * we try to access any of the MMIO registers.  It is also
11346          * critical that the PCI-X hw workaround situation is decided
11347          * before that as well.
11348          */
11349         pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
11350                               &misc_ctrl_reg);
11351
11352         tp->pci_chip_rev_id = (misc_ctrl_reg >>
11353                                MISC_HOST_CTRL_CHIPREV_SHIFT);
11354         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) {
11355                 u32 prod_id_asic_rev;
11356
11357                 pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV,
11358                                       &prod_id_asic_rev);
11359                 tp->pci_chip_rev_id = prod_id_asic_rev & PROD_ID_ASIC_REV_MASK;
11360         }
11361
11362         /* Wrong chip ID in 5752 A0. This code can be removed later
11363          * as A0 is not in production.
11364          */
11365         if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
11366                 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
11367
11368         /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
11369          * we need to disable memory and use config. cycles
11370          * only to access all registers. The 5702/03 chips
11371          * can mistakenly decode the special cycles from the
11372          * ICH chipsets as memory write cycles, causing corruption
11373          * of register and memory space. Only certain ICH bridges
11374          * will drive special cycles with non-zero data during the
11375          * address phase which can fall within the 5703's address
11376          * range. This is not an ICH bug as the PCI spec allows
11377          * non-zero address during special cycles. However, only
11378          * these ICH bridges are known to drive non-zero addresses
11379          * during special cycles.
11380          *
11381          * Since special cycles do not cross PCI bridges, we only
11382          * enable this workaround if the 5703 is on the secondary
11383          * bus of these ICH bridges.
11384          */
11385         if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
11386             (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
11387                 static struct tg3_dev_id {
11388                         u32     vendor;
11389                         u32     device;
11390                         u32     rev;
11391                 } ich_chipsets[] = {
11392                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
11393                           PCI_ANY_ID },
11394                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
11395                           PCI_ANY_ID },
11396                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
11397                           0xa },
11398                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
11399                           PCI_ANY_ID },
11400                         { },
11401                 };
11402                 struct tg3_dev_id *pci_id = &ich_chipsets[0];
11403                 struct pci_dev *bridge = NULL;
11404
11405                 while (pci_id->vendor != 0) {
11406                         bridge = pci_get_device(pci_id->vendor, pci_id->device,
11407                                                 bridge);
11408                         if (!bridge) {
11409                                 pci_id++;
11410                                 continue;
11411                         }
11412                         if (pci_id->rev != PCI_ANY_ID) {
11413                                 if (bridge->revision > pci_id->rev)
11414                                         continue;
11415                         }
11416                         if (bridge->subordinate &&
11417                             (bridge->subordinate->number ==
11418                              tp->pdev->bus->number)) {
11419
11420                                 tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
11421                                 pci_dev_put(bridge);
11422                                 break;
11423                         }
11424                 }
11425         }
11426
11427         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
11428                 static struct tg3_dev_id {
11429                         u32     vendor;
11430                         u32     device;
11431                 } bridge_chipsets[] = {
11432                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
11433                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
11434                         { },
11435                 };
11436                 struct tg3_dev_id *pci_id = &bridge_chipsets[0];
11437                 struct pci_dev *bridge = NULL;
11438
11439                 while (pci_id->vendor != 0) {
11440                         bridge = pci_get_device(pci_id->vendor,
11441                                                 pci_id->device,
11442                                                 bridge);
11443                         if (!bridge) {
11444                                 pci_id++;
11445                                 continue;
11446                         }
11447                         if (bridge->subordinate &&
11448                             (bridge->subordinate->number <=
11449                              tp->pdev->bus->number) &&
11450                             (bridge->subordinate->subordinate >=
11451                              tp->pdev->bus->number)) {
11452                                 tp->tg3_flags3 |= TG3_FLG3_5701_DMA_BUG;
11453                                 pci_dev_put(bridge);
11454                                 break;
11455                         }
11456                 }
11457         }
11458
11459         /* The EPB bridge inside 5714, 5715, and 5780 cannot support
11460          * DMA addresses > 40-bit. This bridge may have other additional
11461          * 57xx devices behind it in some 4-port NIC designs for example.
11462          * Any tg3 device found behind the bridge will also need the 40-bit
11463          * DMA workaround.
11464          */
11465         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
11466             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
11467                 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
11468                 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
11469                 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
11470         }
11471         else {
11472                 struct pci_dev *bridge = NULL;
11473
11474                 do {
11475                         bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
11476                                                 PCI_DEVICE_ID_SERVERWORKS_EPB,
11477                                                 bridge);
11478                         if (bridge && bridge->subordinate &&
11479                             (bridge->subordinate->number <=
11480                              tp->pdev->bus->number) &&
11481                             (bridge->subordinate->subordinate >=
11482                              tp->pdev->bus->number)) {
11483                                 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
11484                                 pci_dev_put(bridge);
11485                                 break;
11486                         }
11487                 } while (bridge);
11488         }
11489
11490         /* Initialize misc host control in PCI block. */
11491         tp->misc_host_ctrl |= (misc_ctrl_reg &
11492                                MISC_HOST_CTRL_CHIPREV);
11493         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
11494                                tp->misc_host_ctrl);
11495
11496         pci_read_config_dword(tp->pdev, TG3PCI_CACHELINESZ,
11497                               &cacheline_sz_reg);
11498
11499         tp->pci_cacheline_sz = (cacheline_sz_reg >>  0) & 0xff;
11500         tp->pci_lat_timer    = (cacheline_sz_reg >>  8) & 0xff;
11501         tp->pci_hdr_type     = (cacheline_sz_reg >> 16) & 0xff;
11502         tp->pci_bist         = (cacheline_sz_reg >> 24) & 0xff;
11503
11504         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
11505             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714))
11506                 tp->pdev_peer = tg3_find_peer(tp);
11507
11508         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
11509             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
11510             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
11511             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
11512             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
11513             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
11514             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
11515             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
11516                 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
11517
11518         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
11519             (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
11520                 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
11521
11522         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
11523                 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSI;
11524                 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX ||
11525                     GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX ||
11526                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 &&
11527                      tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 &&
11528                      tp->pdev_peer == tp->pdev))
11529                         tp->tg3_flags &= ~TG3_FLAG_SUPPORT_MSI;
11530
11531                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
11532                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
11533                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
11534                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
11535                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
11536                         tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
11537                         tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
11538                 } else {
11539                         tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 | TG3_FLG2_TSO_BUG;
11540                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
11541                                 ASIC_REV_5750 &&
11542                             tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
11543                                 tp->tg3_flags2 &= ~TG3_FLG2_TSO_BUG;
11544                 }
11545         }
11546
11547         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705 &&
11548             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5750 &&
11549             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
11550             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5755 &&
11551             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5787 &&
11552             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
11553             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761 &&
11554             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)
11555                 tp->tg3_flags2 |= TG3_FLG2_JUMBO_CAPABLE;
11556
11557         pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
11558         if (pcie_cap != 0) {
11559                 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
11560
11561                 pcie_set_readrq(tp->pdev, 4096);
11562
11563                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
11564                         u16 lnkctl;
11565
11566                         pci_read_config_word(tp->pdev,
11567                                              pcie_cap + PCI_EXP_LNKCTL,
11568                                              &lnkctl);
11569                         if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN)
11570                                 tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;
11571                 }
11572         }
11573
11574         /* If we have an AMD 762 or VIA K8T800 chipset, write
11575          * reordering to the mailbox registers done by the host
11576          * controller can cause major troubles.  We read back from
11577          * every mailbox register write to force the writes to be
11578          * posted to the chip in order.
11579          */
11580         if (pci_dev_present(write_reorder_chipsets) &&
11581             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
11582                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
11583
11584         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
11585             tp->pci_lat_timer < 64) {
11586                 tp->pci_lat_timer = 64;
11587
11588                 cacheline_sz_reg  = ((tp->pci_cacheline_sz & 0xff) <<  0);
11589                 cacheline_sz_reg |= ((tp->pci_lat_timer    & 0xff) <<  8);
11590                 cacheline_sz_reg |= ((tp->pci_hdr_type     & 0xff) << 16);
11591                 cacheline_sz_reg |= ((tp->pci_bist         & 0xff) << 24);
11592
11593                 pci_write_config_dword(tp->pdev, TG3PCI_CACHELINESZ,
11594                                        cacheline_sz_reg);
11595         }
11596
11597         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
11598             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
11599                 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
11600                 if (!tp->pcix_cap) {
11601                         printk(KERN_ERR PFX "Cannot find PCI-X "
11602                                             "capability, aborting.\n");
11603                         return -EIO;
11604                 }
11605         }
11606
11607         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
11608                               &pci_state_reg);
11609
11610         if (tp->pcix_cap && (pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0) {
11611                 tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
11612
11613                 /* If this is a 5700 BX chipset, and we are in PCI-X
11614                  * mode, enable register write workaround.
11615                  *
11616                  * The workaround is to use indirect register accesses
11617                  * for all chip writes not to mailbox registers.
11618                  */
11619                 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
11620                         u32 pm_reg;
11621
11622                         tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
11623
11624                         /* The chip can have it's power management PCI config
11625                          * space registers clobbered due to this bug.
11626                          * So explicitly force the chip into D0 here.
11627                          */
11628                         pci_read_config_dword(tp->pdev,
11629                                               tp->pm_cap + PCI_PM_CTRL,
11630                                               &pm_reg);
11631                         pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
11632                         pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
11633                         pci_write_config_dword(tp->pdev,
11634                                                tp->pm_cap + PCI_PM_CTRL,
11635                                                pm_reg);
11636
11637                         /* Also, force SERR#/PERR# in PCI command. */
11638                         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
11639                         pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
11640                         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
11641                 }
11642         }
11643
11644         /* 5700 BX chips need to have their TX producer index mailboxes
11645          * written twice to workaround a bug.
11646          */
11647         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX)
11648                 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
11649
11650         if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
11651                 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
11652         if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
11653                 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
11654
11655         /* Chip-specific fixup from Broadcom driver */
11656         if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
11657             (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
11658                 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
11659                 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
11660         }
11661
11662         /* Default fast path register access methods */
11663         tp->read32 = tg3_read32;
11664         tp->write32 = tg3_write32;
11665         tp->read32_mbox = tg3_read32;
11666         tp->write32_mbox = tg3_write32;
11667         tp->write32_tx_mbox = tg3_write32;
11668         tp->write32_rx_mbox = tg3_write32;
11669
11670         /* Various workaround register access methods */
11671         if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
11672                 tp->write32 = tg3_write_indirect_reg32;
11673         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
11674                  ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
11675                   tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) {
11676                 /*
11677                  * Back to back register writes can cause problems on these
11678                  * chips, the workaround is to read back all reg writes
11679                  * except those to mailbox regs.
11680                  *
11681                  * See tg3_write_indirect_reg32().
11682                  */
11683                 tp->write32 = tg3_write_flush_reg32;
11684         }
11685
11686
11687         if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
11688             (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
11689                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
11690                 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
11691                         tp->write32_rx_mbox = tg3_write_flush_reg32;
11692         }
11693
11694         if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
11695                 tp->read32 = tg3_read_indirect_reg32;
11696                 tp->write32 = tg3_write_indirect_reg32;
11697                 tp->read32_mbox = tg3_read_indirect_mbox;
11698                 tp->write32_mbox = tg3_write_indirect_mbox;
11699                 tp->write32_tx_mbox = tg3_write_indirect_mbox;
11700                 tp->write32_rx_mbox = tg3_write_indirect_mbox;
11701
11702                 iounmap(tp->regs);
11703                 tp->regs = NULL;
11704
11705                 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
11706                 pci_cmd &= ~PCI_COMMAND_MEMORY;
11707                 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
11708         }
11709         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
11710                 tp->read32_mbox = tg3_read32_mbox_5906;
11711                 tp->write32_mbox = tg3_write32_mbox_5906;
11712                 tp->write32_tx_mbox = tg3_write32_mbox_5906;
11713                 tp->write32_rx_mbox = tg3_write32_mbox_5906;
11714         }
11715
11716         if (tp->write32 == tg3_write_indirect_reg32 ||
11717             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
11718              (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
11719               GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
11720                 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
11721
11722         /* Get eeprom hw config before calling tg3_set_power_state().
11723          * In particular, the TG3_FLG2_IS_NIC flag must be
11724          * determined before calling tg3_set_power_state() so that
11725          * we know whether or not to switch out of Vaux power.
11726          * When the flag is set, it means that GPIO1 is used for eeprom
11727          * write protect and also implies that it is a LOM where GPIOs
11728          * are not used to switch power.
11729          */
11730         tg3_get_eeprom_hw_cfg(tp);
11731
11732         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
11733                 /* Allow reads and writes to the
11734                  * APE register and memory space.
11735                  */
11736                 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
11737                                  PCISTATE_ALLOW_APE_SHMEM_WR;
11738                 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
11739                                        pci_state_reg);
11740         }
11741
11742         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
11743             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
11744                 tp->tg3_flags |= TG3_FLAG_CPMU_PRESENT;
11745
11746                 if (tp->pci_chip_rev_id == CHIPREV_ID_5784_A0 ||
11747                     tp->pci_chip_rev_id == CHIPREV_ID_5784_A1 ||
11748                     tp->pci_chip_rev_id == CHIPREV_ID_5761_A0 ||
11749                     tp->pci_chip_rev_id == CHIPREV_ID_5761_A1)
11750                         tp->tg3_flags3 |= TG3_FLG3_5761_5784_AX_FIXES;
11751         }
11752
11753         /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
11754          * GPIO1 driven high will bring 5700's external PHY out of reset.
11755          * It is also used as eeprom write protect on LOMs.
11756          */
11757         tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
11758         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
11759             (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
11760                 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
11761                                        GRC_LCLCTRL_GPIO_OUTPUT1);
11762         /* Unused GPIO3 must be driven as output on 5752 because there
11763          * are no pull-up resistors on unused GPIO pins.
11764          */
11765         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
11766                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
11767
11768         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
11769                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
11770
11771         /* Force the chip into D0. */
11772         err = tg3_set_power_state(tp, PCI_D0);
11773         if (err) {
11774                 printk(KERN_ERR PFX "(%s) transition to D0 failed\n",
11775                        pci_name(tp->pdev));
11776                 return err;
11777         }
11778
11779         /* 5700 B0 chips do not support checksumming correctly due
11780          * to hardware bugs.
11781          */
11782         if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
11783                 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
11784
11785         /* Derive initial jumbo mode from MTU assigned in
11786          * ether_setup() via the alloc_etherdev() call
11787          */
11788         if (tp->dev->mtu > ETH_DATA_LEN &&
11789             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
11790                 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
11791
11792         /* Determine WakeOnLan speed to use. */
11793         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
11794             tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
11795             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
11796             tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
11797                 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
11798         } else {
11799                 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
11800         }
11801
11802         /* A few boards don't want Ethernet@WireSpeed phy feature */
11803         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
11804             ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
11805              (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
11806              (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
11807             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) ||
11808             (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
11809                 tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
11810
11811         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
11812             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
11813                 tp->tg3_flags2 |= TG3_FLG2_PHY_ADC_BUG;
11814         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
11815                 tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
11816
11817         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
11818                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
11819                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
11820                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
11821                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
11822                         if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
11823                             tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
11824                                 tp->tg3_flags2 |= TG3_FLG2_PHY_JITTER_BUG;
11825                         if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
11826                                 tp->tg3_flags2 |= TG3_FLG2_PHY_ADJUST_TRIM;
11827                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)
11828                         tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
11829         }
11830
11831         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
11832             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
11833                 tp->phy_otp = tg3_read_otp_phycfg(tp);
11834                 if (tp->phy_otp == 0)
11835                         tp->phy_otp = TG3_OTP_DEFAULT;
11836         }
11837
11838         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
11839             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
11840                 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
11841         else
11842                 tp->mi_mode = MAC_MI_MODE_BASE;
11843
11844         tp->coalesce_mode = 0;
11845         if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
11846             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
11847                 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
11848
11849         /* Initialize MAC MI mode, polling disabled. */
11850         tw32_f(MAC_MI_MODE, tp->mi_mode);
11851         udelay(80);
11852
11853         /* Initialize data/descriptor byte/word swapping. */
11854         val = tr32(GRC_MODE);
11855         val &= GRC_MODE_HOST_STACKUP;
11856         tw32(GRC_MODE, val | tp->grc_mode);
11857
11858         tg3_switch_clocks(tp);
11859
11860         /* Clear this out for sanity. */
11861         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
11862
11863         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
11864                               &pci_state_reg);
11865         if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
11866             (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
11867                 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
11868
11869                 if (chiprevid == CHIPREV_ID_5701_A0 ||
11870                     chiprevid == CHIPREV_ID_5701_B0 ||
11871                     chiprevid == CHIPREV_ID_5701_B2 ||
11872                     chiprevid == CHIPREV_ID_5701_B5) {
11873                         void __iomem *sram_base;
11874
11875                         /* Write some dummy words into the SRAM status block
11876                          * area, see if it reads back correctly.  If the return
11877                          * value is bad, force enable the PCIX workaround.
11878                          */
11879                         sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
11880
11881                         writel(0x00000000, sram_base);
11882                         writel(0x00000000, sram_base + 4);
11883                         writel(0xffffffff, sram_base + 4);
11884                         if (readl(sram_base) != 0x00000000)
11885                                 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
11886                 }
11887         }
11888
11889         udelay(50);
11890         tg3_nvram_init(tp);
11891
11892         grc_misc_cfg = tr32(GRC_MISC_CFG);
11893         grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
11894
11895         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
11896             (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
11897              grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
11898                 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
11899
11900         if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
11901             (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
11902                 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
11903         if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
11904                 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
11905                                       HOSTCC_MODE_CLRTICK_TXBD);
11906
11907                 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
11908                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
11909                                        tp->misc_host_ctrl);
11910         }
11911
11912         /* these are limited to 10/100 only */
11913         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
11914              (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
11915             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
11916              tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
11917              (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
11918               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
11919               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
11920             (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
11921              (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
11922               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
11923               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
11924             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11925                 tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
11926
11927         err = tg3_phy_probe(tp);
11928         if (err) {
11929                 printk(KERN_ERR PFX "(%s) phy probe failed, err %d\n",
11930                        pci_name(tp->pdev), err);
11931                 /* ... but do not return immediately ... */
11932         }
11933
11934         tg3_read_partno(tp);
11935         tg3_read_fw_ver(tp);
11936
11937         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
11938                 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
11939         } else {
11940                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
11941                         tp->tg3_flags |= TG3_FLAG_USE_MI_INTERRUPT;
11942                 else
11943                         tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
11944         }
11945
11946         /* 5700 {AX,BX} chips have a broken status block link
11947          * change bit implementation, so we must use the
11948          * status register in those cases.
11949          */
11950         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
11951                 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
11952         else
11953                 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
11954
11955         /* The led_ctrl is set during tg3_phy_probe, here we might
11956          * have to force the link status polling mechanism based
11957          * upon subsystem IDs.
11958          */
11959         if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
11960             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
11961             !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
11962                 tp->tg3_flags |= (TG3_FLAG_USE_MI_INTERRUPT |
11963                                   TG3_FLAG_USE_LINKCHG_REG);
11964         }
11965
11966         /* For all SERDES we poll the MAC status register. */
11967         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
11968                 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
11969         else
11970                 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
11971
11972         /* All chips before 5787 can get confused if TX buffers
11973          * straddle the 4GB address boundary in some cases.
11974          */
11975         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
11976             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
11977             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
11978             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
11979             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11980                 tp->dev->hard_start_xmit = tg3_start_xmit;
11981         else
11982                 tp->dev->hard_start_xmit = tg3_start_xmit_dma_bug;
11983
11984         tp->rx_offset = 2;
11985         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
11986             (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0)
11987                 tp->rx_offset = 0;
11988
11989         tp->rx_std_max_post = TG3_RX_RING_SIZE;
11990
11991         /* Increment the rx prod index on the rx std ring by at most
11992          * 8 for these chips to workaround hw errata.
11993          */
11994         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
11995             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
11996             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
11997                 tp->rx_std_max_post = 8;
11998
11999         if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND)
12000                 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
12001                                      PCIE_PWR_MGMT_L1_THRESH_MSK;
12002
12003         return err;
12004 }
12005
12006 #ifdef CONFIG_SPARC
12007 static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
12008 {
12009         struct net_device *dev = tp->dev;
12010         struct pci_dev *pdev = tp->pdev;
12011         struct device_node *dp = pci_device_to_OF_node(pdev);
12012         const unsigned char *addr;
12013         int len;
12014
12015         addr = of_get_property(dp, "local-mac-address", &len);
12016         if (addr && len == 6) {
12017                 memcpy(dev->dev_addr, addr, 6);
12018                 memcpy(dev->perm_addr, dev->dev_addr, 6);
12019                 return 0;
12020         }
12021         return -ENODEV;
12022 }
12023
12024 static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
12025 {
12026         struct net_device *dev = tp->dev;
12027
12028         memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
12029         memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
12030         return 0;
12031 }
12032 #endif
12033
12034 static int __devinit tg3_get_device_address(struct tg3 *tp)
12035 {
12036         struct net_device *dev = tp->dev;
12037         u32 hi, lo, mac_offset;
12038         int addr_ok = 0;
12039
12040 #ifdef CONFIG_SPARC
12041         if (!tg3_get_macaddr_sparc(tp))
12042                 return 0;
12043 #endif
12044
12045         mac_offset = 0x7c;
12046         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
12047             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
12048                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
12049                         mac_offset = 0xcc;
12050                 if (tg3_nvram_lock(tp))
12051                         tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
12052                 else
12053                         tg3_nvram_unlock(tp);
12054         }
12055         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12056                 mac_offset = 0x10;
12057
12058         /* First try to get it from MAC address mailbox. */
12059         tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
12060         if ((hi >> 16) == 0x484b) {
12061                 dev->dev_addr[0] = (hi >>  8) & 0xff;
12062                 dev->dev_addr[1] = (hi >>  0) & 0xff;
12063
12064                 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
12065                 dev->dev_addr[2] = (lo >> 24) & 0xff;
12066                 dev->dev_addr[3] = (lo >> 16) & 0xff;
12067                 dev->dev_addr[4] = (lo >>  8) & 0xff;
12068                 dev->dev_addr[5] = (lo >>  0) & 0xff;
12069
12070                 /* Some old bootcode may report a 0 MAC address in SRAM */
12071                 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
12072         }
12073         if (!addr_ok) {
12074                 /* Next, try NVRAM. */
12075                 if (!tg3_nvram_read(tp, mac_offset + 0, &hi) &&
12076                     !tg3_nvram_read(tp, mac_offset + 4, &lo)) {
12077                         dev->dev_addr[0] = ((hi >> 16) & 0xff);
12078                         dev->dev_addr[1] = ((hi >> 24) & 0xff);
12079                         dev->dev_addr[2] = ((lo >>  0) & 0xff);
12080                         dev->dev_addr[3] = ((lo >>  8) & 0xff);
12081                         dev->dev_addr[4] = ((lo >> 16) & 0xff);
12082                         dev->dev_addr[5] = ((lo >> 24) & 0xff);
12083                 }
12084                 /* Finally just fetch it out of the MAC control regs. */
12085                 else {
12086                         hi = tr32(MAC_ADDR_0_HIGH);
12087                         lo = tr32(MAC_ADDR_0_LOW);
12088
12089                         dev->dev_addr[5] = lo & 0xff;
12090                         dev->dev_addr[4] = (lo >> 8) & 0xff;
12091                         dev->dev_addr[3] = (lo >> 16) & 0xff;
12092                         dev->dev_addr[2] = (lo >> 24) & 0xff;
12093                         dev->dev_addr[1] = hi & 0xff;
12094                         dev->dev_addr[0] = (hi >> 8) & 0xff;
12095                 }
12096         }
12097
12098         if (!is_valid_ether_addr(&dev->dev_addr[0])) {
12099 #ifdef CONFIG_SPARC
12100                 if (!tg3_get_default_macaddr_sparc(tp))
12101                         return 0;
12102 #endif
12103                 return -EINVAL;
12104         }
12105         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
12106         return 0;
12107 }
12108
12109 #define BOUNDARY_SINGLE_CACHELINE       1
12110 #define BOUNDARY_MULTI_CACHELINE        2
12111
12112 static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
12113 {
12114         int cacheline_size;
12115         u8 byte;
12116         int goal;
12117
12118         pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
12119         if (byte == 0)
12120                 cacheline_size = 1024;
12121         else
12122                 cacheline_size = (int) byte * 4;
12123
12124         /* On 5703 and later chips, the boundary bits have no
12125          * effect.
12126          */
12127         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
12128             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
12129             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
12130                 goto out;
12131
12132 #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
12133         goal = BOUNDARY_MULTI_CACHELINE;
12134 #else
12135 #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
12136         goal = BOUNDARY_SINGLE_CACHELINE;
12137 #else
12138         goal = 0;
12139 #endif
12140 #endif
12141
12142         if (!goal)
12143                 goto out;
12144
12145         /* PCI controllers on most RISC systems tend to disconnect
12146          * when a device tries to burst across a cache-line boundary.
12147          * Therefore, letting tg3 do so just wastes PCI bandwidth.
12148          *
12149          * Unfortunately, for PCI-E there are only limited
12150          * write-side controls for this, and thus for reads
12151          * we will still get the disconnects.  We'll also waste
12152          * these PCI cycles for both read and write for chips
12153          * other than 5700 and 5701 which do not implement the
12154          * boundary bits.
12155          */
12156         if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
12157             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
12158                 switch (cacheline_size) {
12159                 case 16:
12160                 case 32:
12161                 case 64:
12162                 case 128:
12163                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
12164                                 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
12165                                         DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
12166                         } else {
12167                                 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
12168                                         DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
12169                         }
12170                         break;
12171
12172                 case 256:
12173                         val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
12174                                 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
12175                         break;
12176
12177                 default:
12178                         val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
12179                                 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
12180                         break;
12181                 }
12182         } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
12183                 switch (cacheline_size) {
12184                 case 16:
12185                 case 32:
12186                 case 64:
12187                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
12188                                 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
12189                                 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
12190                                 break;
12191                         }
12192                         /* fallthrough */
12193                 case 128:
12194                 default:
12195                         val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
12196                         val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
12197                         break;
12198                 }
12199         } else {
12200                 switch (cacheline_size) {
12201                 case 16:
12202                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
12203                                 val |= (DMA_RWCTRL_READ_BNDRY_16 |
12204                                         DMA_RWCTRL_WRITE_BNDRY_16);
12205                                 break;
12206                         }
12207                         /* fallthrough */
12208                 case 32:
12209                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
12210                                 val |= (DMA_RWCTRL_READ_BNDRY_32 |
12211                                         DMA_RWCTRL_WRITE_BNDRY_32);
12212                                 break;
12213                         }
12214                         /* fallthrough */
12215                 case 64:
12216                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
12217                                 val |= (DMA_RWCTRL_READ_BNDRY_64 |
12218                                         DMA_RWCTRL_WRITE_BNDRY_64);
12219                                 break;
12220                         }
12221                         /* fallthrough */
12222                 case 128:
12223                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
12224                                 val |= (DMA_RWCTRL_READ_BNDRY_128 |
12225                                         DMA_RWCTRL_WRITE_BNDRY_128);
12226                                 break;
12227                         }
12228                         /* fallthrough */
12229                 case 256:
12230                         val |= (DMA_RWCTRL_READ_BNDRY_256 |
12231                                 DMA_RWCTRL_WRITE_BNDRY_256);
12232                         break;
12233                 case 512:
12234                         val |= (DMA_RWCTRL_READ_BNDRY_512 |
12235                                 DMA_RWCTRL_WRITE_BNDRY_512);
12236                         break;
12237                 case 1024:
12238                 default:
12239                         val |= (DMA_RWCTRL_READ_BNDRY_1024 |
12240                                 DMA_RWCTRL_WRITE_BNDRY_1024);
12241                         break;
12242                 }
12243         }
12244
12245 out:
12246         return val;
12247 }
12248
12249 static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
12250 {
12251         struct tg3_internal_buffer_desc test_desc;
12252         u32 sram_dma_descs;
12253         int i, ret;
12254
12255         sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
12256
12257         tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
12258         tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
12259         tw32(RDMAC_STATUS, 0);
12260         tw32(WDMAC_STATUS, 0);
12261
12262         tw32(BUFMGR_MODE, 0);
12263         tw32(FTQ_RESET, 0);
12264
12265         test_desc.addr_hi = ((u64) buf_dma) >> 32;
12266         test_desc.addr_lo = buf_dma & 0xffffffff;
12267         test_desc.nic_mbuf = 0x00002100;
12268         test_desc.len = size;
12269
12270         /*
12271          * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
12272          * the *second* time the tg3 driver was getting loaded after an
12273          * initial scan.
12274          *
12275          * Broadcom tells me:
12276          *   ...the DMA engine is connected to the GRC block and a DMA
12277          *   reset may affect the GRC block in some unpredictable way...
12278          *   The behavior of resets to individual blocks has not been tested.
12279          *
12280          * Broadcom noted the GRC reset will also reset all sub-components.
12281          */
12282         if (to_device) {
12283                 test_desc.cqid_sqid = (13 << 8) | 2;
12284
12285                 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
12286                 udelay(40);
12287         } else {
12288                 test_desc.cqid_sqid = (16 << 8) | 7;
12289
12290                 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
12291                 udelay(40);
12292         }
12293         test_desc.flags = 0x00000005;
12294
12295         for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
12296                 u32 val;
12297
12298                 val = *(((u32 *)&test_desc) + i);
12299                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
12300                                        sram_dma_descs + (i * sizeof(u32)));
12301                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
12302         }
12303         pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
12304
12305         if (to_device) {
12306                 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
12307         } else {
12308                 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
12309         }
12310
12311         ret = -ENODEV;
12312         for (i = 0; i < 40; i++) {
12313                 u32 val;
12314
12315                 if (to_device)
12316                         val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
12317                 else
12318                         val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
12319                 if ((val & 0xffff) == sram_dma_descs) {
12320                         ret = 0;
12321                         break;
12322                 }
12323
12324                 udelay(100);
12325         }
12326
12327         return ret;
12328 }
12329
12330 #define TEST_BUFFER_SIZE        0x2000
12331
12332 static int __devinit tg3_test_dma(struct tg3 *tp)
12333 {
12334         dma_addr_t buf_dma;
12335         u32 *buf, saved_dma_rwctrl;
12336         int ret;
12337
12338         buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
12339         if (!buf) {
12340                 ret = -ENOMEM;
12341                 goto out_nofree;
12342         }
12343
12344         tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
12345                           (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
12346
12347         tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
12348
12349         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
12350                 /* DMA read watermark not used on PCIE */
12351                 tp->dma_rwctrl |= 0x00180000;
12352         } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
12353                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
12354                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
12355                         tp->dma_rwctrl |= 0x003f0000;
12356                 else
12357                         tp->dma_rwctrl |= 0x003f000f;
12358         } else {
12359                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
12360                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
12361                         u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
12362                         u32 read_water = 0x7;
12363
12364                         /* If the 5704 is behind the EPB bridge, we can
12365                          * do the less restrictive ONE_DMA workaround for
12366                          * better performance.
12367                          */
12368                         if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
12369                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
12370                                 tp->dma_rwctrl |= 0x8000;
12371                         else if (ccval == 0x6 || ccval == 0x7)
12372                                 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
12373
12374                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
12375                                 read_water = 4;
12376                         /* Set bit 23 to enable PCIX hw bug fix */
12377                         tp->dma_rwctrl |=
12378                                 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
12379                                 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
12380                                 (1 << 23);
12381                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
12382                         /* 5780 always in PCIX mode */
12383                         tp->dma_rwctrl |= 0x00144000;
12384                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
12385                         /* 5714 always in PCIX mode */
12386                         tp->dma_rwctrl |= 0x00148000;
12387                 } else {
12388                         tp->dma_rwctrl |= 0x001b000f;
12389                 }
12390         }
12391
12392         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
12393             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
12394                 tp->dma_rwctrl &= 0xfffffff0;
12395
12396         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12397             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
12398                 /* Remove this if it causes problems for some boards. */
12399                 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
12400
12401                 /* On 5700/5701 chips, we need to set this bit.
12402                  * Otherwise the chip will issue cacheline transactions
12403                  * to streamable DMA memory with not all the byte
12404                  * enables turned on.  This is an error on several
12405                  * RISC PCI controllers, in particular sparc64.
12406                  *
12407                  * On 5703/5704 chips, this bit has been reassigned
12408                  * a different meaning.  In particular, it is used
12409                  * on those chips to enable a PCI-X workaround.
12410                  */
12411                 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
12412         }
12413
12414         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
12415
12416 #if 0
12417         /* Unneeded, already done by tg3_get_invariants.  */
12418         tg3_switch_clocks(tp);
12419 #endif
12420
12421         ret = 0;
12422         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
12423             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
12424                 goto out;
12425
12426         /* It is best to perform DMA test with maximum write burst size
12427          * to expose the 5700/5701 write DMA bug.
12428          */
12429         saved_dma_rwctrl = tp->dma_rwctrl;
12430         tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
12431         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
12432
12433         while (1) {
12434                 u32 *p = buf, i;
12435
12436                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
12437                         p[i] = i;
12438
12439                 /* Send the buffer to the chip. */
12440                 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
12441                 if (ret) {
12442                         printk(KERN_ERR "tg3_test_dma() Write the buffer failed %d\n", ret);
12443                         break;
12444                 }
12445
12446 #if 0
12447                 /* validate data reached card RAM correctly. */
12448                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
12449                         u32 val;
12450                         tg3_read_mem(tp, 0x2100 + (i*4), &val);
12451                         if (le32_to_cpu(val) != p[i]) {
12452                                 printk(KERN_ERR "  tg3_test_dma()  Card buffer corrupted on write! (%d != %d)\n", val, i);
12453                                 /* ret = -ENODEV here? */
12454                         }
12455                         p[i] = 0;
12456                 }
12457 #endif
12458                 /* Now read it back. */
12459                 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
12460                 if (ret) {
12461                         printk(KERN_ERR "tg3_test_dma() Read the buffer failed %d\n", ret);
12462
12463                         break;
12464                 }
12465
12466                 /* Verify it. */
12467                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
12468                         if (p[i] == i)
12469                                 continue;
12470
12471                         if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
12472                             DMA_RWCTRL_WRITE_BNDRY_16) {
12473                                 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
12474                                 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
12475                                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
12476                                 break;
12477                         } else {
12478                                 printk(KERN_ERR "tg3_test_dma() buffer corrupted on read back! (%d != %d)\n", p[i], i);
12479                                 ret = -ENODEV;
12480                                 goto out;
12481                         }
12482                 }
12483
12484                 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
12485                         /* Success. */
12486                         ret = 0;
12487                         break;
12488                 }
12489         }
12490         if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
12491             DMA_RWCTRL_WRITE_BNDRY_16) {
12492                 static struct pci_device_id dma_wait_state_chipsets[] = {
12493                         { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
12494                                      PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
12495                         { },
12496                 };
12497
12498                 /* DMA test passed without adjusting DMA boundary,
12499                  * now look for chipsets that are known to expose the
12500                  * DMA bug without failing the test.
12501                  */
12502                 if (pci_dev_present(dma_wait_state_chipsets)) {
12503                         tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
12504                         tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
12505                 }
12506                 else
12507                         /* Safe to use the calculated DMA boundary. */
12508                         tp->dma_rwctrl = saved_dma_rwctrl;
12509
12510                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
12511         }
12512
12513 out:
12514         pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
12515 out_nofree:
12516         return ret;
12517 }
12518
12519 static void __devinit tg3_init_link_config(struct tg3 *tp)
12520 {
12521         tp->link_config.advertising =
12522                 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
12523                  ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
12524                  ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
12525                  ADVERTISED_Autoneg | ADVERTISED_MII);
12526         tp->link_config.speed = SPEED_INVALID;
12527         tp->link_config.duplex = DUPLEX_INVALID;
12528         tp->link_config.autoneg = AUTONEG_ENABLE;
12529         tp->link_config.active_speed = SPEED_INVALID;
12530         tp->link_config.active_duplex = DUPLEX_INVALID;
12531         tp->link_config.phy_is_low_power = 0;
12532         tp->link_config.orig_speed = SPEED_INVALID;
12533         tp->link_config.orig_duplex = DUPLEX_INVALID;
12534         tp->link_config.orig_autoneg = AUTONEG_INVALID;
12535 }
12536
12537 static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
12538 {
12539         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
12540                 tp->bufmgr_config.mbuf_read_dma_low_water =
12541                         DEFAULT_MB_RDMA_LOW_WATER_5705;
12542                 tp->bufmgr_config.mbuf_mac_rx_low_water =
12543                         DEFAULT_MB_MACRX_LOW_WATER_5705;
12544                 tp->bufmgr_config.mbuf_high_water =
12545                         DEFAULT_MB_HIGH_WATER_5705;
12546                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12547                         tp->bufmgr_config.mbuf_mac_rx_low_water =
12548                                 DEFAULT_MB_MACRX_LOW_WATER_5906;
12549                         tp->bufmgr_config.mbuf_high_water =
12550                                 DEFAULT_MB_HIGH_WATER_5906;
12551                 }
12552
12553                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
12554                         DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
12555                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
12556                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
12557                 tp->bufmgr_config.mbuf_high_water_jumbo =
12558                         DEFAULT_MB_HIGH_WATER_JUMBO_5780;
12559         } else {
12560                 tp->bufmgr_config.mbuf_read_dma_low_water =
12561                         DEFAULT_MB_RDMA_LOW_WATER;
12562                 tp->bufmgr_config.mbuf_mac_rx_low_water =
12563                         DEFAULT_MB_MACRX_LOW_WATER;
12564                 tp->bufmgr_config.mbuf_high_water =
12565                         DEFAULT_MB_HIGH_WATER;
12566
12567                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
12568                         DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
12569                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
12570                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
12571                 tp->bufmgr_config.mbuf_high_water_jumbo =
12572                         DEFAULT_MB_HIGH_WATER_JUMBO;
12573         }
12574
12575         tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
12576         tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
12577 }
12578
12579 static char * __devinit tg3_phy_string(struct tg3 *tp)
12580 {
12581         switch (tp->phy_id & PHY_ID_MASK) {
12582         case PHY_ID_BCM5400:    return "5400";
12583         case PHY_ID_BCM5401:    return "5401";
12584         case PHY_ID_BCM5411:    return "5411";
12585         case PHY_ID_BCM5701:    return "5701";
12586         case PHY_ID_BCM5703:    return "5703";
12587         case PHY_ID_BCM5704:    return "5704";
12588         case PHY_ID_BCM5705:    return "5705";
12589         case PHY_ID_BCM5750:    return "5750";
12590         case PHY_ID_BCM5752:    return "5752";
12591         case PHY_ID_BCM5714:    return "5714";
12592         case PHY_ID_BCM5780:    return "5780";
12593         case PHY_ID_BCM5755:    return "5755";
12594         case PHY_ID_BCM5787:    return "5787";
12595         case PHY_ID_BCM5784:    return "5784";
12596         case PHY_ID_BCM5756:    return "5722/5756";
12597         case PHY_ID_BCM5906:    return "5906";
12598         case PHY_ID_BCM5761:    return "5761";
12599         case PHY_ID_BCM8002:    return "8002/serdes";
12600         case 0:                 return "serdes";
12601         default:                return "unknown";
12602         }
12603 }
12604
12605 static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
12606 {
12607         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
12608                 strcpy(str, "PCI Express");
12609                 return str;
12610         } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
12611                 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
12612
12613                 strcpy(str, "PCIX:");
12614
12615                 if ((clock_ctrl == 7) ||
12616                     ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
12617                      GRC_MISC_CFG_BOARD_ID_5704CIOBE))
12618                         strcat(str, "133MHz");
12619                 else if (clock_ctrl == 0)
12620                         strcat(str, "33MHz");
12621                 else if (clock_ctrl == 2)
12622                         strcat(str, "50MHz");
12623                 else if (clock_ctrl == 4)
12624                         strcat(str, "66MHz");
12625                 else if (clock_ctrl == 6)
12626                         strcat(str, "100MHz");
12627         } else {
12628                 strcpy(str, "PCI:");
12629                 if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
12630                         strcat(str, "66MHz");
12631                 else
12632                         strcat(str, "33MHz");
12633         }
12634         if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
12635                 strcat(str, ":32-bit");
12636         else
12637                 strcat(str, ":64-bit");
12638         return str;
12639 }
12640
12641 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
12642 {
12643         struct pci_dev *peer;
12644         unsigned int func, devnr = tp->pdev->devfn & ~7;
12645
12646         for (func = 0; func < 8; func++) {
12647                 peer = pci_get_slot(tp->pdev->bus, devnr | func);
12648                 if (peer && peer != tp->pdev)
12649                         break;
12650                 pci_dev_put(peer);
12651         }
12652         /* 5704 can be configured in single-port mode, set peer to
12653          * tp->pdev in that case.
12654          */
12655         if (!peer) {
12656                 peer = tp->pdev;
12657                 return peer;
12658         }
12659
12660         /*
12661          * We don't need to keep the refcount elevated; there's no way
12662          * to remove one half of this device without removing the other
12663          */
12664         pci_dev_put(peer);
12665
12666         return peer;
12667 }
12668
12669 static void __devinit tg3_init_coal(struct tg3 *tp)
12670 {
12671         struct ethtool_coalesce *ec = &tp->coal;
12672
12673         memset(ec, 0, sizeof(*ec));
12674         ec->cmd = ETHTOOL_GCOALESCE;
12675         ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
12676         ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
12677         ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
12678         ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
12679         ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
12680         ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
12681         ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
12682         ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
12683         ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
12684
12685         if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
12686                                  HOSTCC_MODE_CLRTICK_TXBD)) {
12687                 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
12688                 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
12689                 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
12690                 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
12691         }
12692
12693         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
12694                 ec->rx_coalesce_usecs_irq = 0;
12695                 ec->tx_coalesce_usecs_irq = 0;
12696                 ec->stats_block_coalesce_usecs = 0;
12697         }
12698 }
12699
12700 static int __devinit tg3_init_one(struct pci_dev *pdev,
12701                                   const struct pci_device_id *ent)
12702 {
12703         static int tg3_version_printed = 0;
12704         resource_size_t tg3reg_base;
12705         unsigned long tg3reg_len;
12706         struct net_device *dev;
12707         struct tg3 *tp;
12708         int err, pm_cap;
12709         char str[40];
12710         u64 dma_mask, persist_dma_mask;
12711         DECLARE_MAC_BUF(mac);
12712
12713         if (tg3_version_printed++ == 0)
12714                 printk(KERN_INFO "%s", version);
12715
12716         err = pci_enable_device(pdev);
12717         if (err) {
12718                 printk(KERN_ERR PFX "Cannot enable PCI device, "
12719                        "aborting.\n");
12720                 return err;
12721         }
12722
12723         if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
12724                 printk(KERN_ERR PFX "Cannot find proper PCI device "
12725                        "base address, aborting.\n");
12726                 err = -ENODEV;
12727                 goto err_out_disable_pdev;
12728         }
12729
12730         err = pci_request_regions(pdev, DRV_MODULE_NAME);
12731         if (err) {
12732                 printk(KERN_ERR PFX "Cannot obtain PCI resources, "
12733                        "aborting.\n");
12734                 goto err_out_disable_pdev;
12735         }
12736
12737         pci_set_master(pdev);
12738
12739         /* Find power-management capability. */
12740         pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
12741         if (pm_cap == 0) {
12742                 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
12743                        "aborting.\n");
12744                 err = -EIO;
12745                 goto err_out_free_res;
12746         }
12747
12748         tg3reg_base = pci_resource_start(pdev, 0);
12749         tg3reg_len = pci_resource_len(pdev, 0);
12750
12751         dev = alloc_etherdev(sizeof(*tp));
12752         if (!dev) {
12753                 printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
12754                 err = -ENOMEM;
12755                 goto err_out_free_res;
12756         }
12757
12758         SET_NETDEV_DEV(dev, &pdev->dev);
12759
12760 #if TG3_VLAN_TAG_USED
12761         dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
12762         dev->vlan_rx_register = tg3_vlan_rx_register;
12763 #endif
12764
12765         tp = netdev_priv(dev);
12766         tp->pdev = pdev;
12767         tp->dev = dev;
12768         tp->pm_cap = pm_cap;
12769         tp->mac_mode = TG3_DEF_MAC_MODE;
12770         tp->rx_mode = TG3_DEF_RX_MODE;
12771         tp->tx_mode = TG3_DEF_TX_MODE;
12772
12773         if (tg3_debug > 0)
12774                 tp->msg_enable = tg3_debug;
12775         else
12776                 tp->msg_enable = TG3_DEF_MSG_ENABLE;
12777
12778         /* The word/byte swap controls here control register access byte
12779          * swapping.  DMA data byte swapping is controlled in the GRC_MODE
12780          * setting below.
12781          */
12782         tp->misc_host_ctrl =
12783                 MISC_HOST_CTRL_MASK_PCI_INT |
12784                 MISC_HOST_CTRL_WORD_SWAP |
12785                 MISC_HOST_CTRL_INDIR_ACCESS |
12786                 MISC_HOST_CTRL_PCISTATE_RW;
12787
12788         /* The NONFRM (non-frame) byte/word swap controls take effect
12789          * on descriptor entries, anything which isn't packet data.
12790          *
12791          * The StrongARM chips on the board (one for tx, one for rx)
12792          * are running in big-endian mode.
12793          */
12794         tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
12795                         GRC_MODE_WSWAP_NONFRM_DATA);
12796 #ifdef __BIG_ENDIAN
12797         tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
12798 #endif
12799         spin_lock_init(&tp->lock);
12800         spin_lock_init(&tp->indirect_lock);
12801         INIT_WORK(&tp->reset_task, tg3_reset_task);
12802
12803         tp->regs = ioremap_nocache(tg3reg_base, tg3reg_len);
12804         if (!tp->regs) {
12805                 printk(KERN_ERR PFX "Cannot map device registers, "
12806                        "aborting.\n");
12807                 err = -ENOMEM;
12808                 goto err_out_free_dev;
12809         }
12810
12811         tg3_init_link_config(tp);
12812
12813         tp->rx_pending = TG3_DEF_RX_RING_PENDING;
12814         tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
12815         tp->tx_pending = TG3_DEF_TX_RING_PENDING;
12816
12817         dev->open = tg3_open;
12818         dev->stop = tg3_close;
12819         dev->get_stats = tg3_get_stats;
12820         dev->set_multicast_list = tg3_set_rx_mode;
12821         dev->set_mac_address = tg3_set_mac_addr;
12822         dev->do_ioctl = tg3_ioctl;
12823         dev->tx_timeout = tg3_tx_timeout;
12824         netif_napi_add(dev, &tp->napi, tg3_poll, 64);
12825         dev->ethtool_ops = &tg3_ethtool_ops;
12826         dev->watchdog_timeo = TG3_TX_TIMEOUT;
12827         dev->change_mtu = tg3_change_mtu;
12828         dev->irq = pdev->irq;
12829 #ifdef CONFIG_NET_POLL_CONTROLLER
12830         dev->poll_controller = tg3_poll_controller;
12831 #endif
12832
12833         err = tg3_get_invariants(tp);
12834         if (err) {
12835                 printk(KERN_ERR PFX "Problem fetching invariants of chip, "
12836                        "aborting.\n");
12837                 goto err_out_iounmap;
12838         }
12839
12840         /* The EPB bridge inside 5714, 5715, and 5780 and any
12841          * device behind the EPB cannot support DMA addresses > 40-bit.
12842          * On 64-bit systems with IOMMU, use 40-bit dma_mask.
12843          * On 64-bit systems without IOMMU, use 64-bit dma_mask and
12844          * do DMA address check in tg3_start_xmit().
12845          */
12846         if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
12847                 persist_dma_mask = dma_mask = DMA_32BIT_MASK;
12848         else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
12849                 persist_dma_mask = dma_mask = DMA_40BIT_MASK;
12850 #ifdef CONFIG_HIGHMEM
12851                 dma_mask = DMA_64BIT_MASK;
12852 #endif
12853         } else
12854                 persist_dma_mask = dma_mask = DMA_64BIT_MASK;
12855
12856         /* Configure DMA attributes. */
12857         if (dma_mask > DMA_32BIT_MASK) {
12858                 err = pci_set_dma_mask(pdev, dma_mask);
12859                 if (!err) {
12860                         dev->features |= NETIF_F_HIGHDMA;
12861                         err = pci_set_consistent_dma_mask(pdev,
12862                                                           persist_dma_mask);
12863                         if (err < 0) {
12864                                 printk(KERN_ERR PFX "Unable to obtain 64 bit "
12865                                        "DMA for consistent allocations\n");
12866                                 goto err_out_iounmap;
12867                         }
12868                 }
12869         }
12870         if (err || dma_mask == DMA_32BIT_MASK) {
12871                 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
12872                 if (err) {
12873                         printk(KERN_ERR PFX "No usable DMA configuration, "
12874                                "aborting.\n");
12875                         goto err_out_iounmap;
12876                 }
12877         }
12878
12879         tg3_init_bufmgr_config(tp);
12880
12881         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
12882                 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
12883         }
12884         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12885             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
12886             tp->pci_chip_rev_id == CHIPREV_ID_5705_A0 ||
12887             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
12888             (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
12889                 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
12890         } else {
12891                 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE | TG3_FLG2_TSO_BUG;
12892         }
12893
12894         /* TSO is on by default on chips that support hardware TSO.
12895          * Firmware TSO on older chips gives lower performance, so it
12896          * is off by default, but can be enabled using ethtool.
12897          */
12898         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
12899                 dev->features |= NETIF_F_TSO;
12900                 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) &&
12901                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906))
12902                         dev->features |= NETIF_F_TSO6;
12903                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
12904                         dev->features |= NETIF_F_TSO_ECN;
12905         }
12906
12907
12908         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
12909             !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
12910             !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
12911                 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
12912                 tp->rx_pending = 63;
12913         }
12914
12915         err = tg3_get_device_address(tp);
12916         if (err) {
12917                 printk(KERN_ERR PFX "Could not obtain valid ethernet address, "
12918                        "aborting.\n");
12919                 goto err_out_iounmap;
12920         }
12921
12922         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
12923                 if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
12924                         printk(KERN_ERR PFX "Cannot find proper PCI device "
12925                                "base address for APE, aborting.\n");
12926                         err = -ENODEV;
12927                         goto err_out_iounmap;
12928                 }
12929
12930                 tg3reg_base = pci_resource_start(pdev, 2);
12931                 tg3reg_len = pci_resource_len(pdev, 2);
12932
12933                 tp->aperegs = ioremap_nocache(tg3reg_base, tg3reg_len);
12934                 if (!tp->aperegs) {
12935                         printk(KERN_ERR PFX "Cannot map APE registers, "
12936                                "aborting.\n");
12937                         err = -ENOMEM;
12938                         goto err_out_iounmap;
12939                 }
12940
12941                 tg3_ape_lock_init(tp);
12942         }
12943
12944         /*
12945          * Reset chip in case UNDI or EFI driver did not shutdown
12946          * DMA self test will enable WDMAC and we'll see (spurious)
12947          * pending DMA on the PCI bus at that point.
12948          */
12949         if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
12950             (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
12951                 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
12952                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
12953         }
12954
12955         err = tg3_test_dma(tp);
12956         if (err) {
12957                 printk(KERN_ERR PFX "DMA engine test failed, aborting.\n");
12958                 goto err_out_apeunmap;
12959         }
12960
12961         /* Tigon3 can do ipv4 only... and some chips have buggy
12962          * checksumming.
12963          */
12964         if ((tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) == 0) {
12965                 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
12966                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
12967                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
12968                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12969                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
12970                         dev->features |= NETIF_F_IPV6_CSUM;
12971
12972                 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
12973         } else
12974                 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
12975
12976         /* flow control autonegotiation is default behavior */
12977         tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
12978         tp->link_config.flowctrl = TG3_FLOW_CTRL_TX | TG3_FLOW_CTRL_RX;
12979
12980         tg3_init_coal(tp);
12981
12982         pci_set_drvdata(pdev, dev);
12983
12984         err = register_netdev(dev);
12985         if (err) {
12986                 printk(KERN_ERR PFX "Cannot register net device, "
12987                        "aborting.\n");
12988                 goto err_out_apeunmap;
12989         }
12990
12991         printk(KERN_INFO "%s: Tigon3 [partno(%s) rev %04x PHY(%s)] "
12992                "(%s) %s Ethernet %s\n",
12993                dev->name,
12994                tp->board_part_number,
12995                tp->pci_chip_rev_id,
12996                tg3_phy_string(tp),
12997                tg3_bus_string(tp, str),
12998                ((tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100Base-TX" :
12999                 ((tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) ? "1000Base-SX" :
13000                  "10/100/1000Base-T")),
13001                print_mac(mac, dev->dev_addr));
13002
13003         printk(KERN_INFO "%s: RXcsums[%d] LinkChgREG[%d] "
13004                "MIirq[%d] ASF[%d] WireSpeed[%d] TSOcap[%d]\n",
13005                dev->name,
13006                (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
13007                (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
13008                (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) != 0,
13009                (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
13010                (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0,
13011                (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
13012         printk(KERN_INFO "%s: dma_rwctrl[%08x] dma_mask[%d-bit]\n",
13013                dev->name, tp->dma_rwctrl,
13014                (pdev->dma_mask == DMA_32BIT_MASK) ? 32 :
13015                 (((u64) pdev->dma_mask == DMA_40BIT_MASK) ? 40 : 64));
13016
13017         return 0;
13018
13019 err_out_apeunmap:
13020         if (tp->aperegs) {
13021                 iounmap(tp->aperegs);
13022                 tp->aperegs = NULL;
13023         }
13024
13025 err_out_iounmap:
13026         if (tp->regs) {
13027                 iounmap(tp->regs);
13028                 tp->regs = NULL;
13029         }
13030
13031 err_out_free_dev:
13032         free_netdev(dev);
13033
13034 err_out_free_res:
13035         pci_release_regions(pdev);
13036
13037 err_out_disable_pdev:
13038         pci_disable_device(pdev);
13039         pci_set_drvdata(pdev, NULL);
13040         return err;
13041 }
13042
13043 static void __devexit tg3_remove_one(struct pci_dev *pdev)
13044 {
13045         struct net_device *dev = pci_get_drvdata(pdev);
13046
13047         if (dev) {
13048                 struct tg3 *tp = netdev_priv(dev);
13049
13050                 flush_scheduled_work();
13051                 unregister_netdev(dev);
13052                 if (tp->aperegs) {
13053                         iounmap(tp->aperegs);
13054                         tp->aperegs = NULL;
13055                 }
13056                 if (tp->regs) {
13057                         iounmap(tp->regs);
13058                         tp->regs = NULL;
13059                 }
13060                 free_netdev(dev);
13061                 pci_release_regions(pdev);
13062                 pci_disable_device(pdev);
13063                 pci_set_drvdata(pdev, NULL);
13064         }
13065 }
13066
13067 static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
13068 {
13069         struct net_device *dev = pci_get_drvdata(pdev);
13070         struct tg3 *tp = netdev_priv(dev);
13071         int err;
13072
13073         /* PCI register 4 needs to be saved whether netif_running() or not.
13074          * MSI address and data need to be saved if using MSI and
13075          * netif_running().
13076          */
13077         pci_save_state(pdev);
13078
13079         if (!netif_running(dev))
13080                 return 0;
13081
13082         flush_scheduled_work();
13083         tg3_netif_stop(tp);
13084
13085         del_timer_sync(&tp->timer);
13086
13087         tg3_full_lock(tp, 1);
13088         tg3_disable_ints(tp);
13089         tg3_full_unlock(tp);
13090
13091         netif_device_detach(dev);
13092
13093         tg3_full_lock(tp, 0);
13094         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
13095         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
13096         tg3_full_unlock(tp);
13097
13098         err = tg3_set_power_state(tp, pci_choose_state(pdev, state));
13099         if (err) {
13100                 tg3_full_lock(tp, 0);
13101
13102                 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
13103                 if (tg3_restart_hw(tp, 1))
13104                         goto out;
13105
13106                 tp->timer.expires = jiffies + tp->timer_offset;
13107                 add_timer(&tp->timer);
13108
13109                 netif_device_attach(dev);
13110                 tg3_netif_start(tp);
13111
13112 out:
13113                 tg3_full_unlock(tp);
13114         }
13115
13116         return err;
13117 }
13118
13119 static int tg3_resume(struct pci_dev *pdev)
13120 {
13121         struct net_device *dev = pci_get_drvdata(pdev);
13122         struct tg3 *tp = netdev_priv(dev);
13123         int err;
13124
13125         pci_restore_state(tp->pdev);
13126
13127         if (!netif_running(dev))
13128                 return 0;
13129
13130         err = tg3_set_power_state(tp, PCI_D0);
13131         if (err)
13132                 return err;
13133
13134         netif_device_attach(dev);
13135
13136         tg3_full_lock(tp, 0);
13137
13138         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
13139         err = tg3_restart_hw(tp, 1);
13140         if (err)
13141                 goto out;
13142
13143         tp->timer.expires = jiffies + tp->timer_offset;
13144         add_timer(&tp->timer);
13145
13146         tg3_netif_start(tp);
13147
13148 out:
13149         tg3_full_unlock(tp);
13150
13151         return err;
13152 }
13153
13154 static struct pci_driver tg3_driver = {
13155         .name           = DRV_MODULE_NAME,
13156         .id_table       = tg3_pci_tbl,
13157         .probe          = tg3_init_one,
13158         .remove         = __devexit_p(tg3_remove_one),
13159         .suspend        = tg3_suspend,
13160         .resume         = tg3_resume
13161 };
13162
13163 static int __init tg3_init(void)
13164 {
13165         return pci_register_driver(&tg3_driver);
13166 }
13167
13168 static void __exit tg3_cleanup(void)
13169 {
13170         pci_unregister_driver(&tg3_driver);
13171 }
13172
13173 module_init(tg3_init);
13174 module_exit(tg3_cleanup);