2 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
3 * Copyright (c) 2004-2005 Atheros Communications, Inc.
4 * Copyright (c) 2006 Devicescape Software, Inc.
5 * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com>
6 * Copyright (c) 2007 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu>
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer,
15 * without modification.
16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
17 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
18 * redistribution must be conditioned upon including a substantially
19 * similar Disclaimer requirement for further binary redistribution.
20 * 3. Neither the names of the above-listed copyright holders nor the names
21 * of any contributors may be used to endorse or promote products derived
22 * from this software without specific prior written permission.
24 * Alternatively, this software may be distributed under the terms of the
25 * GNU General Public License ("GPL") version 2 as published by the Free
26 * Software Foundation.
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
32 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
33 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
34 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
35 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
36 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
37 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
38 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
39 * THE POSSIBILITY OF SUCH DAMAGES.
43 #include <linux/module.h>
44 #include <linux/delay.h>
45 #include <linux/hardirq.h>
48 #include <linux/netdevice.h>
49 #include <linux/cache.h>
50 #include <linux/pci.h>
51 #include <linux/ethtool.h>
52 #include <linux/uaccess.h>
54 #include <net/ieee80211_radiotap.h>
56 #include <asm/unaligned.h>
62 static int ath5k_calinterval = 10; /* Calibrate PHY every 10 secs (TODO: Fixme) */
70 MODULE_AUTHOR("Jiri Slaby");
71 MODULE_AUTHOR("Nick Kossifidis");
72 MODULE_DESCRIPTION("Support for 5xxx series of Atheros 802.11 wireless LAN cards.");
73 MODULE_SUPPORTED_DEVICE("Atheros 5xxx WLAN cards");
74 MODULE_LICENSE("Dual BSD/GPL");
75 MODULE_VERSION("0.5.0 (EXPERIMENTAL)");
79 static struct pci_device_id ath5k_pci_id_table[] __devinitdata = {
80 { PCI_VDEVICE(ATHEROS, 0x0207), .driver_data = AR5K_AR5210 }, /* 5210 early */
81 { PCI_VDEVICE(ATHEROS, 0x0007), .driver_data = AR5K_AR5210 }, /* 5210 */
82 { PCI_VDEVICE(ATHEROS, 0x0011), .driver_data = AR5K_AR5211 }, /* 5311 - this is on AHB bus !*/
83 { PCI_VDEVICE(ATHEROS, 0x0012), .driver_data = AR5K_AR5211 }, /* 5211 */
84 { PCI_VDEVICE(ATHEROS, 0x0013), .driver_data = AR5K_AR5212 }, /* 5212 */
85 { PCI_VDEVICE(3COM_2, 0x0013), .driver_data = AR5K_AR5212 }, /* 3com 5212 */
86 { PCI_VDEVICE(3COM, 0x0013), .driver_data = AR5K_AR5212 }, /* 3com 3CRDAG675 5212 */
87 { PCI_VDEVICE(ATHEROS, 0x1014), .driver_data = AR5K_AR5212 }, /* IBM minipci 5212 */
88 { PCI_VDEVICE(ATHEROS, 0x0014), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
89 { PCI_VDEVICE(ATHEROS, 0x0015), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
90 { PCI_VDEVICE(ATHEROS, 0x0016), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
91 { PCI_VDEVICE(ATHEROS, 0x0017), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
92 { PCI_VDEVICE(ATHEROS, 0x0018), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
93 { PCI_VDEVICE(ATHEROS, 0x0019), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
94 { PCI_VDEVICE(ATHEROS, 0x001a), .driver_data = AR5K_AR5212 }, /* 2413 Griffin-lite */
95 { PCI_VDEVICE(ATHEROS, 0x001b), .driver_data = AR5K_AR5212 }, /* 5413 Eagle */
96 { PCI_VDEVICE(ATHEROS, 0x001c), .driver_data = AR5K_AR5212 }, /* 5424 Condor (PCI-E)*/
99 MODULE_DEVICE_TABLE(pci, ath5k_pci_id_table);
102 static struct ath5k_srev_name srev_names[] = {
103 { "5210", AR5K_VERSION_VER, AR5K_SREV_VER_AR5210 },
104 { "5311", AR5K_VERSION_VER, AR5K_SREV_VER_AR5311 },
105 { "5311A", AR5K_VERSION_VER, AR5K_SREV_VER_AR5311A },
106 { "5311B", AR5K_VERSION_VER, AR5K_SREV_VER_AR5311B },
107 { "5211", AR5K_VERSION_VER, AR5K_SREV_VER_AR5211 },
108 { "5212", AR5K_VERSION_VER, AR5K_SREV_VER_AR5212 },
109 { "5213", AR5K_VERSION_VER, AR5K_SREV_VER_AR5213 },
110 { "5213A", AR5K_VERSION_VER, AR5K_SREV_VER_AR5213A },
111 { "2413", AR5K_VERSION_VER, AR5K_SREV_VER_AR2413 },
112 { "2414", AR5K_VERSION_VER, AR5K_SREV_VER_AR2414 },
113 { "2424", AR5K_VERSION_VER, AR5K_SREV_VER_AR2424 },
114 { "5424", AR5K_VERSION_VER, AR5K_SREV_VER_AR5424 },
115 { "5413", AR5K_VERSION_VER, AR5K_SREV_VER_AR5413 },
116 { "5414", AR5K_VERSION_VER, AR5K_SREV_VER_AR5414 },
117 { "5416", AR5K_VERSION_VER, AR5K_SREV_VER_AR5416 },
118 { "5418", AR5K_VERSION_VER, AR5K_SREV_VER_AR5418 },
119 { "2425", AR5K_VERSION_VER, AR5K_SREV_VER_AR2425 },
120 { "xxxxx", AR5K_VERSION_VER, AR5K_SREV_UNKNOWN },
121 { "5110", AR5K_VERSION_RAD, AR5K_SREV_RAD_5110 },
122 { "5111", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111 },
123 { "2111", AR5K_VERSION_RAD, AR5K_SREV_RAD_2111 },
124 { "5112", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112 },
125 { "5112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112A },
126 { "2112", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112 },
127 { "2112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112A },
128 { "SChip", AR5K_VERSION_RAD, AR5K_SREV_RAD_SC0 },
129 { "SChip", AR5K_VERSION_RAD, AR5K_SREV_RAD_SC1 },
130 { "SChip", AR5K_VERSION_RAD, AR5K_SREV_RAD_SC2 },
131 { "5133", AR5K_VERSION_RAD, AR5K_SREV_RAD_5133 },
132 { "xxxxx", AR5K_VERSION_RAD, AR5K_SREV_UNKNOWN },
135 static struct ieee80211_rate ath5k_rates[] = {
137 .hw_value = ATH5K_RATE_CODE_1M, },
139 .hw_value = ATH5K_RATE_CODE_2M,
140 .hw_value_short = ATH5K_RATE_CODE_2M | AR5K_SET_SHORT_PREAMBLE,
141 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
143 .hw_value = ATH5K_RATE_CODE_5_5M,
144 .hw_value_short = ATH5K_RATE_CODE_5_5M | AR5K_SET_SHORT_PREAMBLE,
145 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
147 .hw_value = ATH5K_RATE_CODE_11M,
148 .hw_value_short = ATH5K_RATE_CODE_11M | AR5K_SET_SHORT_PREAMBLE,
149 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
151 .hw_value = ATH5K_RATE_CODE_6M,
154 .hw_value = ATH5K_RATE_CODE_9M,
157 .hw_value = ATH5K_RATE_CODE_12M,
160 .hw_value = ATH5K_RATE_CODE_18M,
163 .hw_value = ATH5K_RATE_CODE_24M,
166 .hw_value = ATH5K_RATE_CODE_36M,
169 .hw_value = ATH5K_RATE_CODE_48M,
172 .hw_value = ATH5K_RATE_CODE_54M,
178 * Prototypes - PCI stack related functions
180 static int __devinit ath5k_pci_probe(struct pci_dev *pdev,
181 const struct pci_device_id *id);
182 static void __devexit ath5k_pci_remove(struct pci_dev *pdev);
184 static int ath5k_pci_suspend(struct pci_dev *pdev,
186 static int ath5k_pci_resume(struct pci_dev *pdev);
188 #define ath5k_pci_suspend NULL
189 #define ath5k_pci_resume NULL
190 #endif /* CONFIG_PM */
192 static struct pci_driver ath5k_pci_driver = {
194 .id_table = ath5k_pci_id_table,
195 .probe = ath5k_pci_probe,
196 .remove = __devexit_p(ath5k_pci_remove),
197 .suspend = ath5k_pci_suspend,
198 .resume = ath5k_pci_resume,
204 * Prototypes - MAC 802.11 stack related functions
206 static int ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb);
207 static int ath5k_reset(struct ath5k_softc *sc, bool stop, bool change_channel);
208 static int ath5k_reset_wake(struct ath5k_softc *sc);
209 static int ath5k_start(struct ieee80211_hw *hw);
210 static void ath5k_stop(struct ieee80211_hw *hw);
211 static int ath5k_add_interface(struct ieee80211_hw *hw,
212 struct ieee80211_if_init_conf *conf);
213 static void ath5k_remove_interface(struct ieee80211_hw *hw,
214 struct ieee80211_if_init_conf *conf);
215 static int ath5k_config(struct ieee80211_hw *hw,
216 struct ieee80211_conf *conf);
217 static int ath5k_config_interface(struct ieee80211_hw *hw,
218 struct ieee80211_vif *vif,
219 struct ieee80211_if_conf *conf);
220 static void ath5k_configure_filter(struct ieee80211_hw *hw,
221 unsigned int changed_flags,
222 unsigned int *new_flags,
223 int mc_count, struct dev_mc_list *mclist);
224 static int ath5k_set_key(struct ieee80211_hw *hw,
225 enum set_key_cmd cmd,
226 const u8 *local_addr, const u8 *addr,
227 struct ieee80211_key_conf *key);
228 static int ath5k_get_stats(struct ieee80211_hw *hw,
229 struct ieee80211_low_level_stats *stats);
230 static int ath5k_get_tx_stats(struct ieee80211_hw *hw,
231 struct ieee80211_tx_queue_stats *stats);
232 static u64 ath5k_get_tsf(struct ieee80211_hw *hw);
233 static void ath5k_reset_tsf(struct ieee80211_hw *hw);
234 static int ath5k_beacon_update(struct ieee80211_hw *hw,
235 struct sk_buff *skb);
237 static struct ieee80211_ops ath5k_hw_ops = {
239 .start = ath5k_start,
241 .add_interface = ath5k_add_interface,
242 .remove_interface = ath5k_remove_interface,
243 .config = ath5k_config,
244 .config_interface = ath5k_config_interface,
245 .configure_filter = ath5k_configure_filter,
246 .set_key = ath5k_set_key,
247 .get_stats = ath5k_get_stats,
249 .get_tx_stats = ath5k_get_tx_stats,
250 .get_tsf = ath5k_get_tsf,
251 .reset_tsf = ath5k_reset_tsf,
255 * Prototypes - Internal functions
258 static int ath5k_attach(struct pci_dev *pdev,
259 struct ieee80211_hw *hw);
260 static void ath5k_detach(struct pci_dev *pdev,
261 struct ieee80211_hw *hw);
262 /* Channel/mode setup */
263 static inline short ath5k_ieee2mhz(short chan);
264 static unsigned int ath5k_copy_channels(struct ath5k_hw *ah,
265 struct ieee80211_channel *channels,
268 static int ath5k_setup_bands(struct ieee80211_hw *hw);
269 static int ath5k_chan_set(struct ath5k_softc *sc,
270 struct ieee80211_channel *chan);
271 static void ath5k_setcurmode(struct ath5k_softc *sc,
273 static void ath5k_mode_setup(struct ath5k_softc *sc);
275 /* Descriptor setup */
276 static int ath5k_desc_alloc(struct ath5k_softc *sc,
277 struct pci_dev *pdev);
278 static void ath5k_desc_free(struct ath5k_softc *sc,
279 struct pci_dev *pdev);
281 static int ath5k_rxbuf_setup(struct ath5k_softc *sc,
282 struct ath5k_buf *bf);
283 static int ath5k_txbuf_setup(struct ath5k_softc *sc,
284 struct ath5k_buf *bf);
285 static inline void ath5k_txbuf_free(struct ath5k_softc *sc,
286 struct ath5k_buf *bf)
291 pci_unmap_single(sc->pdev, bf->skbaddr, bf->skb->len,
293 dev_kfree_skb(bf->skb);
298 static struct ath5k_txq *ath5k_txq_setup(struct ath5k_softc *sc,
299 int qtype, int subtype);
300 static int ath5k_beaconq_setup(struct ath5k_hw *ah);
301 static int ath5k_beaconq_config(struct ath5k_softc *sc);
302 static void ath5k_txq_drainq(struct ath5k_softc *sc,
303 struct ath5k_txq *txq);
304 static void ath5k_txq_cleanup(struct ath5k_softc *sc);
305 static void ath5k_txq_release(struct ath5k_softc *sc);
307 static int ath5k_rx_start(struct ath5k_softc *sc);
308 static void ath5k_rx_stop(struct ath5k_softc *sc);
309 static unsigned int ath5k_rx_decrypted(struct ath5k_softc *sc,
310 struct ath5k_desc *ds,
312 struct ath5k_rx_status *rs);
313 static void ath5k_tasklet_rx(unsigned long data);
315 static void ath5k_tx_processq(struct ath5k_softc *sc,
316 struct ath5k_txq *txq);
317 static void ath5k_tasklet_tx(unsigned long data);
318 /* Beacon handling */
319 static int ath5k_beacon_setup(struct ath5k_softc *sc,
320 struct ath5k_buf *bf);
321 static void ath5k_beacon_send(struct ath5k_softc *sc);
322 static void ath5k_beacon_config(struct ath5k_softc *sc);
323 static void ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf);
325 static inline u64 ath5k_extend_tsf(struct ath5k_hw *ah, u32 rstamp)
327 u64 tsf = ath5k_hw_get_tsf64(ah);
329 if ((tsf & 0x7fff) < rstamp)
332 return (tsf & ~0x7fff) | rstamp;
335 /* Interrupt handling */
336 static int ath5k_init(struct ath5k_softc *sc);
337 static int ath5k_stop_locked(struct ath5k_softc *sc);
338 static int ath5k_stop_hw(struct ath5k_softc *sc);
339 static irqreturn_t ath5k_intr(int irq, void *dev_id);
340 static void ath5k_tasklet_reset(unsigned long data);
342 static void ath5k_calibrate(unsigned long data);
344 static int ath5k_init_leds(struct ath5k_softc *sc);
345 static void ath5k_led_enable(struct ath5k_softc *sc);
346 static void ath5k_led_off(struct ath5k_softc *sc);
347 static void ath5k_unregister_leds(struct ath5k_softc *sc);
350 * Module init/exit functions
359 ret = pci_register_driver(&ath5k_pci_driver);
361 printk(KERN_ERR "ath5k_pci: can't register pci driver\n");
371 pci_unregister_driver(&ath5k_pci_driver);
373 ath5k_debug_finish();
376 module_init(init_ath5k_pci);
377 module_exit(exit_ath5k_pci);
380 /********************\
381 * PCI Initialization *
382 \********************/
385 ath5k_chip_name(enum ath5k_srev_type type, u_int16_t val)
387 const char *name = "xxxxx";
390 for (i = 0; i < ARRAY_SIZE(srev_names); i++) {
391 if (srev_names[i].sr_type != type)
393 if ((val & 0xff) < srev_names[i + 1].sr_val) {
394 name = srev_names[i].sr_name;
403 ath5k_pci_probe(struct pci_dev *pdev,
404 const struct pci_device_id *id)
407 struct ath5k_softc *sc;
408 struct ieee80211_hw *hw;
412 ret = pci_enable_device(pdev);
414 dev_err(&pdev->dev, "can't enable device\n");
418 /* XXX 32-bit addressing only */
419 ret = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
421 dev_err(&pdev->dev, "32-bit DMA not available\n");
426 * Cache line size is used to size and align various
427 * structures used to communicate with the hardware.
429 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
432 * Linux 2.4.18 (at least) writes the cache line size
433 * register as a 16-bit wide register which is wrong.
434 * We must have this setup properly for rx buffer
435 * DMA to work so force a reasonable value here if it
438 csz = L1_CACHE_BYTES / sizeof(u32);
439 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
442 * The default setting of latency timer yields poor results,
443 * set it to the value used by other systems. It may be worth
444 * tweaking this setting more.
446 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
448 /* Enable bus mastering */
449 pci_set_master(pdev);
452 * Disable the RETRY_TIMEOUT register (0x41) to keep
453 * PCI Tx retries from interfering with C3 CPU state.
455 pci_write_config_byte(pdev, 0x41, 0);
457 ret = pci_request_region(pdev, 0, "ath5k");
459 dev_err(&pdev->dev, "cannot reserve PCI memory region\n");
463 mem = pci_iomap(pdev, 0, 0);
465 dev_err(&pdev->dev, "cannot remap PCI memory region\n") ;
471 * Allocate hw (mac80211 main struct)
472 * and hw->priv (driver private data)
474 hw = ieee80211_alloc_hw(sizeof(*sc), &ath5k_hw_ops);
476 dev_err(&pdev->dev, "cannot allocate ieee80211_hw\n");
481 dev_info(&pdev->dev, "registered as '%s'\n", wiphy_name(hw->wiphy));
483 /* Initialize driver private data */
484 SET_IEEE80211_DEV(hw, &pdev->dev);
485 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
486 IEEE80211_HW_SIGNAL_DBM |
487 IEEE80211_HW_NOISE_DBM;
488 hw->extra_tx_headroom = 2;
489 hw->channel_change_time = 5000;
494 ath5k_debug_init_device(sc);
497 * Mark the device as detached to avoid processing
498 * interrupts until setup is complete.
500 __set_bit(ATH_STAT_INVALID, sc->status);
502 sc->iobase = mem; /* So we can unmap it on detach */
503 sc->cachelsz = csz * sizeof(u32); /* convert to bytes */
504 sc->opmode = IEEE80211_IF_TYPE_STA;
505 mutex_init(&sc->lock);
506 spin_lock_init(&sc->rxbuflock);
507 spin_lock_init(&sc->txbuflock);
509 /* Set private data */
510 pci_set_drvdata(pdev, hw);
512 /* Setup interrupt handler */
513 ret = request_irq(pdev->irq, ath5k_intr, IRQF_SHARED, "ath", sc);
515 ATH5K_ERR(sc, "request_irq failed\n");
519 /* Initialize device */
520 sc->ah = ath5k_hw_attach(sc, id->driver_data);
521 if (IS_ERR(sc->ah)) {
522 ret = PTR_ERR(sc->ah);
526 /* Finish private driver data initialization */
527 ret = ath5k_attach(pdev, hw);
531 ATH5K_INFO(sc, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n",
532 ath5k_chip_name(AR5K_VERSION_VER,sc->ah->ah_mac_srev),
534 sc->ah->ah_phy_revision);
536 if (!sc->ah->ah_single_chip) {
537 /* Single chip radio (!RF5111) */
538 if (sc->ah->ah_radio_5ghz_revision &&
539 !sc->ah->ah_radio_2ghz_revision) {
540 /* No 5GHz support -> report 2GHz radio */
541 if (!test_bit(AR5K_MODE_11A,
542 sc->ah->ah_capabilities.cap_mode)) {
543 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
544 ath5k_chip_name(AR5K_VERSION_RAD,
545 sc->ah->ah_radio_5ghz_revision),
546 sc->ah->ah_radio_5ghz_revision);
547 /* No 2GHz support (5110 and some
548 * 5Ghz only cards) -> report 5Ghz radio */
549 } else if (!test_bit(AR5K_MODE_11B,
550 sc->ah->ah_capabilities.cap_mode)) {
551 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
552 ath5k_chip_name(AR5K_VERSION_RAD,
553 sc->ah->ah_radio_5ghz_revision),
554 sc->ah->ah_radio_5ghz_revision);
555 /* Multiband radio */
557 ATH5K_INFO(sc, "RF%s multiband radio found"
559 ath5k_chip_name(AR5K_VERSION_RAD,
560 sc->ah->ah_radio_5ghz_revision),
561 sc->ah->ah_radio_5ghz_revision);
564 /* Multi chip radio (RF5111 - RF2111) ->
565 * report both 2GHz/5GHz radios */
566 else if (sc->ah->ah_radio_5ghz_revision &&
567 sc->ah->ah_radio_2ghz_revision){
568 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
569 ath5k_chip_name(AR5K_VERSION_RAD,
570 sc->ah->ah_radio_5ghz_revision),
571 sc->ah->ah_radio_5ghz_revision);
572 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
573 ath5k_chip_name(AR5K_VERSION_RAD,
574 sc->ah->ah_radio_2ghz_revision),
575 sc->ah->ah_radio_2ghz_revision);
580 /* ready to process interrupts */
581 __clear_bit(ATH_STAT_INVALID, sc->status);
585 ath5k_hw_detach(sc->ah);
587 free_irq(pdev->irq, sc);
589 ieee80211_free_hw(hw);
591 pci_iounmap(pdev, mem);
593 pci_release_region(pdev, 0);
595 pci_disable_device(pdev);
600 static void __devexit
601 ath5k_pci_remove(struct pci_dev *pdev)
603 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
604 struct ath5k_softc *sc = hw->priv;
606 ath5k_debug_finish_device(sc);
607 ath5k_detach(pdev, hw);
608 ath5k_hw_detach(sc->ah);
609 free_irq(pdev->irq, sc);
610 pci_iounmap(pdev, sc->iobase);
611 pci_release_region(pdev, 0);
612 pci_disable_device(pdev);
613 ieee80211_free_hw(hw);
618 ath5k_pci_suspend(struct pci_dev *pdev, pm_message_t state)
620 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
621 struct ath5k_softc *sc = hw->priv;
627 free_irq(pdev->irq, sc);
628 pci_save_state(pdev);
629 pci_disable_device(pdev);
630 pci_set_power_state(pdev, PCI_D3hot);
636 ath5k_pci_resume(struct pci_dev *pdev)
638 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
639 struct ath5k_softc *sc = hw->priv;
640 struct ath5k_hw *ah = sc->ah;
643 pci_restore_state(pdev);
645 err = pci_enable_device(pdev);
650 * Suspend/Resume resets the PCI configuration space, so we have to
651 * re-disable the RETRY_TIMEOUT register (0x41) to keep
652 * PCI Tx retries from interfering with C3 CPU state
654 pci_write_config_byte(pdev, 0x41, 0);
656 err = request_irq(pdev->irq, ath5k_intr, IRQF_SHARED, "ath", sc);
658 ATH5K_ERR(sc, "request_irq failed\n");
662 err = ath5k_init(sc);
665 ath5k_led_enable(sc);
668 * Reset the key cache since some parts do not
669 * reset the contents on initial power up or resume.
671 * FIXME: This may need to be revisited when mac80211 becomes
672 * aware of suspend/resume.
674 for (i = 0; i < AR5K_KEYTABLE_SIZE; i++)
675 ath5k_hw_reset_key(ah, i);
679 free_irq(pdev->irq, sc);
681 pci_disable_device(pdev);
684 #endif /* CONFIG_PM */
687 /***********************\
688 * Driver Initialization *
689 \***********************/
692 ath5k_attach(struct pci_dev *pdev, struct ieee80211_hw *hw)
694 struct ath5k_softc *sc = hw->priv;
695 struct ath5k_hw *ah = sc->ah;
700 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "devid 0x%x\n", pdev->device);
703 * Check if the MAC has multi-rate retry support.
704 * We do this by trying to setup a fake extended
705 * descriptor. MAC's that don't have support will
706 * return false w/o doing anything. MAC's that do
707 * support it will return true w/o doing anything.
709 ret = ah->ah_setup_xtx_desc(ah, NULL, 0, 0, 0, 0, 0, 0);
713 __set_bit(ATH_STAT_MRRETRY, sc->status);
716 * Reset the key cache since some parts do not
717 * reset the contents on initial power up.
719 for (i = 0; i < AR5K_KEYTABLE_SIZE; i++)
720 ath5k_hw_reset_key(ah, i);
723 * Collect the channel list. The 802.11 layer
724 * is resposible for filtering this list based
725 * on settings like the phy mode and regulatory
726 * domain restrictions.
728 ret = ath5k_setup_bands(hw);
730 ATH5K_ERR(sc, "can't get channels\n");
734 /* NB: setup here so ath5k_rate_update is happy */
735 if (test_bit(AR5K_MODE_11A, ah->ah_modes))
736 ath5k_setcurmode(sc, AR5K_MODE_11A);
738 ath5k_setcurmode(sc, AR5K_MODE_11B);
741 * Allocate tx+rx descriptors and populate the lists.
743 ret = ath5k_desc_alloc(sc, pdev);
745 ATH5K_ERR(sc, "can't allocate descriptors\n");
750 * Allocate hardware transmit queues: one queue for
751 * beacon frames and one data queue for each QoS
752 * priority. Note that hw functions handle reseting
753 * these queues at the needed time.
755 ret = ath5k_beaconq_setup(ah);
757 ATH5K_ERR(sc, "can't setup a beacon xmit queue\n");
762 sc->txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BK);
763 if (IS_ERR(sc->txq)) {
764 ATH5K_ERR(sc, "can't setup xmit queue\n");
765 ret = PTR_ERR(sc->txq);
769 tasklet_init(&sc->rxtq, ath5k_tasklet_rx, (unsigned long)sc);
770 tasklet_init(&sc->txtq, ath5k_tasklet_tx, (unsigned long)sc);
771 tasklet_init(&sc->restq, ath5k_tasklet_reset, (unsigned long)sc);
772 setup_timer(&sc->calib_tim, ath5k_calibrate, (unsigned long)sc);
774 ath5k_hw_get_lladdr(ah, mac);
775 SET_IEEE80211_PERM_ADDR(hw, mac);
776 /* All MAC address bits matter for ACKs */
777 memset(sc->bssidmask, 0xff, ETH_ALEN);
778 ath5k_hw_set_bssid_mask(sc->ah, sc->bssidmask);
780 ret = ieee80211_register_hw(hw);
782 ATH5K_ERR(sc, "can't register ieee80211 hw\n");
790 ath5k_txq_release(sc);
792 ath5k_hw_release_tx_queue(ah, sc->bhalq);
794 ath5k_desc_free(sc, pdev);
800 ath5k_detach(struct pci_dev *pdev, struct ieee80211_hw *hw)
802 struct ath5k_softc *sc = hw->priv;
805 * NB: the order of these is important:
806 * o call the 802.11 layer before detaching ath5k_hw to
807 * insure callbacks into the driver to delete global
808 * key cache entries can be handled
809 * o reclaim the tx queue data structures after calling
810 * the 802.11 layer as we'll get called back to reclaim
811 * node state and potentially want to use them
812 * o to cleanup the tx queues the hal is called, so detach
814 * XXX: ??? detach ath5k_hw ???
815 * Other than that, it's straightforward...
817 ieee80211_unregister_hw(hw);
818 ath5k_desc_free(sc, pdev);
819 ath5k_txq_release(sc);
820 ath5k_hw_release_tx_queue(sc->ah, sc->bhalq);
821 ath5k_unregister_leds(sc);
824 * NB: can't reclaim these until after ieee80211_ifdetach
825 * returns because we'll get called back to reclaim node
826 * state and potentially want to use them.
833 /********************\
834 * Channel/mode setup *
835 \********************/
838 * Convert IEEE channel number to MHz frequency.
841 ath5k_ieee2mhz(short chan)
843 if (chan <= 14 || chan >= 27)
844 return ieee80211chan2mhz(chan);
846 return 2212 + chan * 20;
850 ath5k_copy_channels(struct ath5k_hw *ah,
851 struct ieee80211_channel *channels,
855 unsigned int i, count, size, chfreq, freq, ch;
857 if (!test_bit(mode, ah->ah_modes))
862 case AR5K_MODE_11A_TURBO:
863 /* 1..220, but 2GHz frequencies are filtered by check_channel */
865 chfreq = CHANNEL_5GHZ;
869 case AR5K_MODE_11G_TURBO:
871 chfreq = CHANNEL_2GHZ;
874 ATH5K_WARN(ah->ah_sc, "bad mode, not copying channels\n");
878 for (i = 0, count = 0; i < size && max > 0; i++) {
880 freq = ath5k_ieee2mhz(ch);
882 /* Check if channel is supported by the chipset */
883 if (!ath5k_channel_ok(ah, freq, chfreq))
886 /* Write channel info and increment counter */
887 channels[count].center_freq = freq;
888 channels[count].band = (chfreq == CHANNEL_2GHZ) ?
889 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
893 channels[count].hw_value = chfreq | CHANNEL_OFDM;
895 case AR5K_MODE_11A_TURBO:
896 case AR5K_MODE_11G_TURBO:
897 channels[count].hw_value = chfreq |
898 CHANNEL_OFDM | CHANNEL_TURBO;
901 channels[count].hw_value = CHANNEL_B;
912 ath5k_setup_rate_idx(struct ath5k_softc *sc, struct ieee80211_supported_band *b)
916 for (i = 0; i < AR5K_MAX_RATES; i++)
917 sc->rate_idx[b->band][i] = -1;
919 for (i = 0; i < b->n_bitrates; i++) {
920 sc->rate_idx[b->band][b->bitrates[i].hw_value] = i;
921 if (b->bitrates[i].hw_value_short)
922 sc->rate_idx[b->band][b->bitrates[i].hw_value_short] = i;
927 ath5k_setup_bands(struct ieee80211_hw *hw)
929 struct ath5k_softc *sc = hw->priv;
930 struct ath5k_hw *ah = sc->ah;
931 struct ieee80211_supported_band *sband;
932 int max_c, count_c = 0;
935 BUILD_BUG_ON(ARRAY_SIZE(sc->sbands) < IEEE80211_NUM_BANDS);
936 max_c = ARRAY_SIZE(sc->channels);
939 sband = &sc->sbands[IEEE80211_BAND_2GHZ];
940 sband->band = IEEE80211_BAND_2GHZ;
941 sband->bitrates = &sc->rates[IEEE80211_BAND_2GHZ][0];
943 if (test_bit(AR5K_MODE_11G, sc->ah->ah_capabilities.cap_mode)) {
945 memcpy(sband->bitrates, &ath5k_rates[0],
946 sizeof(struct ieee80211_rate) * 12);
947 sband->n_bitrates = 12;
949 sband->channels = sc->channels;
950 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
951 AR5K_MODE_11G, max_c);
953 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
954 count_c = sband->n_channels;
956 } else if (test_bit(AR5K_MODE_11B, sc->ah->ah_capabilities.cap_mode)) {
958 memcpy(sband->bitrates, &ath5k_rates[0],
959 sizeof(struct ieee80211_rate) * 4);
960 sband->n_bitrates = 4;
962 /* 5211 only supports B rates and uses 4bit rate codes
963 * (e.g normally we have 0x1B for 1M, but on 5211 we have 0x0B)
966 if (ah->ah_version == AR5K_AR5211) {
967 for (i = 0; i < 4; i++) {
968 sband->bitrates[i].hw_value =
969 sband->bitrates[i].hw_value & 0xF;
970 sband->bitrates[i].hw_value_short =
971 sband->bitrates[i].hw_value_short & 0xF;
975 sband->channels = sc->channels;
976 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
977 AR5K_MODE_11B, max_c);
979 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
980 count_c = sband->n_channels;
983 ath5k_setup_rate_idx(sc, sband);
985 /* 5GHz band, A mode */
986 if (test_bit(AR5K_MODE_11A, sc->ah->ah_capabilities.cap_mode)) {
987 sband = &sc->sbands[IEEE80211_BAND_5GHZ];
988 sband->band = IEEE80211_BAND_5GHZ;
989 sband->bitrates = &sc->rates[IEEE80211_BAND_5GHZ][0];
991 memcpy(sband->bitrates, &ath5k_rates[4],
992 sizeof(struct ieee80211_rate) * 8);
993 sband->n_bitrates = 8;
995 sband->channels = &sc->channels[count_c];
996 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
997 AR5K_MODE_11A, max_c);
999 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = sband;
1001 ath5k_setup_rate_idx(sc, sband);
1003 ath5k_debug_dump_bands(sc);
1009 * Set/change channels. If the channel is really being changed,
1010 * it's done by reseting the chip. To accomplish this we must
1011 * first cleanup any pending DMA, then restart stuff after a la
1015 ath5k_chan_set(struct ath5k_softc *sc, struct ieee80211_channel *chan)
1017 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "(%u MHz) -> (%u MHz)\n",
1018 sc->curchan->center_freq, chan->center_freq);
1020 if (chan->center_freq != sc->curchan->center_freq ||
1021 chan->hw_value != sc->curchan->hw_value) {
1024 sc->curband = &sc->sbands[chan->band];
1027 * To switch channels clear any pending DMA operations;
1028 * wait long enough for the RX fifo to drain, reset the
1029 * hardware at the new frequency, and then re-enable
1030 * the relevant bits of the h/w.
1032 return ath5k_reset(sc, true, true);
1039 ath5k_setcurmode(struct ath5k_softc *sc, unsigned int mode)
1043 if (mode == AR5K_MODE_11A) {
1044 sc->curband = &sc->sbands[IEEE80211_BAND_5GHZ];
1046 sc->curband = &sc->sbands[IEEE80211_BAND_2GHZ];
1051 ath5k_mode_setup(struct ath5k_softc *sc)
1053 struct ath5k_hw *ah = sc->ah;
1056 /* configure rx filter */
1057 rfilt = sc->filter_flags;
1058 ath5k_hw_set_rx_filter(ah, rfilt);
1060 if (ath5k_hw_hasbssidmask(ah))
1061 ath5k_hw_set_bssid_mask(ah, sc->bssidmask);
1063 /* configure operational mode */
1064 ath5k_hw_set_opmode(ah);
1066 ath5k_hw_set_mcast_filter(ah, 0, 0);
1067 ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "RX filter 0x%x\n", rfilt);
1071 ath5k_hw_to_driver_rix(struct ath5k_softc *sc, int hw_rix)
1073 WARN_ON(hw_rix < 0 || hw_rix > AR5K_MAX_RATES);
1074 return sc->rate_idx[sc->curband->band][hw_rix];
1082 ath5k_rxbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
1084 struct ath5k_hw *ah = sc->ah;
1085 struct sk_buff *skb = bf->skb;
1086 struct ath5k_desc *ds;
1088 if (likely(skb == NULL)) {
1092 * Allocate buffer with headroom_needed space for the
1093 * fake physical layer header at the start.
1095 skb = dev_alloc_skb(sc->rxbufsize + sc->cachelsz - 1);
1096 if (unlikely(skb == NULL)) {
1097 ATH5K_ERR(sc, "can't alloc skbuff of size %u\n",
1098 sc->rxbufsize + sc->cachelsz - 1);
1102 * Cache-line-align. This is important (for the
1103 * 5210 at least) as not doing so causes bogus data
1106 off = ((unsigned long)skb->data) % sc->cachelsz;
1108 skb_reserve(skb, sc->cachelsz - off);
1111 bf->skbaddr = pci_map_single(sc->pdev,
1112 skb->data, sc->rxbufsize, PCI_DMA_FROMDEVICE);
1113 if (unlikely(pci_dma_mapping_error(sc->pdev, bf->skbaddr))) {
1114 ATH5K_ERR(sc, "%s: DMA mapping failed\n", __func__);
1122 * Setup descriptors. For receive we always terminate
1123 * the descriptor list with a self-linked entry so we'll
1124 * not get overrun under high load (as can happen with a
1125 * 5212 when ANI processing enables PHY error frames).
1127 * To insure the last descriptor is self-linked we create
1128 * each descriptor as self-linked and add it to the end. As
1129 * each additional descriptor is added the previous self-linked
1130 * entry is ``fixed'' naturally. This should be safe even
1131 * if DMA is happening. When processing RX interrupts we
1132 * never remove/process the last, self-linked, entry on the
1133 * descriptor list. This insures the hardware always has
1134 * someplace to write a new frame.
1137 ds->ds_link = bf->daddr; /* link to self */
1138 ds->ds_data = bf->skbaddr;
1139 ath5k_hw_setup_rx_desc(ah, ds,
1140 skb_tailroom(skb), /* buffer size */
1143 if (sc->rxlink != NULL)
1144 *sc->rxlink = bf->daddr;
1145 sc->rxlink = &ds->ds_link;
1150 ath5k_txbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
1152 struct ath5k_hw *ah = sc->ah;
1153 struct ath5k_txq *txq = sc->txq;
1154 struct ath5k_desc *ds = bf->desc;
1155 struct sk_buff *skb = bf->skb;
1156 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1157 unsigned int pktlen, flags, keyidx = AR5K_TXKEYIX_INVALID;
1160 flags = AR5K_TXDESC_INTREQ | AR5K_TXDESC_CLRDMASK;
1162 /* XXX endianness */
1163 bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
1166 if (info->flags & IEEE80211_TX_CTL_NO_ACK)
1167 flags |= AR5K_TXDESC_NOACK;
1171 if (info->control.hw_key) {
1172 keyidx = info->control.hw_key->hw_key_idx;
1173 pktlen += info->control.icv_len;
1175 ret = ah->ah_setup_tx_desc(ah, ds, pktlen,
1176 ieee80211_get_hdrlen_from_skb(skb), AR5K_PKT_TYPE_NORMAL,
1177 (sc->power_level * 2),
1178 ieee80211_get_tx_rate(sc->hw, info)->hw_value,
1179 info->control.retry_limit, keyidx, 0, flags, 0, 0);
1184 ds->ds_data = bf->skbaddr;
1186 spin_lock_bh(&txq->lock);
1187 list_add_tail(&bf->list, &txq->q);
1188 sc->tx_stats[txq->qnum].len++;
1189 if (txq->link == NULL) /* is this first packet? */
1190 ath5k_hw_put_tx_buf(ah, txq->qnum, bf->daddr);
1191 else /* no, so only link it */
1192 *txq->link = bf->daddr;
1194 txq->link = &ds->ds_link;
1195 ath5k_hw_tx_start(ah, txq->qnum);
1197 spin_unlock_bh(&txq->lock);
1201 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
1205 /*******************\
1206 * Descriptors setup *
1207 \*******************/
1210 ath5k_desc_alloc(struct ath5k_softc *sc, struct pci_dev *pdev)
1212 struct ath5k_desc *ds;
1213 struct ath5k_buf *bf;
1218 /* allocate descriptors */
1219 sc->desc_len = sizeof(struct ath5k_desc) *
1220 (ATH_TXBUF + ATH_RXBUF + ATH_BCBUF + 1);
1221 sc->desc = pci_alloc_consistent(pdev, sc->desc_len, &sc->desc_daddr);
1222 if (sc->desc == NULL) {
1223 ATH5K_ERR(sc, "can't allocate descriptors\n");
1228 da = sc->desc_daddr;
1229 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "DMA map: %p (%zu) -> %llx\n",
1230 ds, sc->desc_len, (unsigned long long)sc->desc_daddr);
1232 bf = kcalloc(1 + ATH_TXBUF + ATH_RXBUF + ATH_BCBUF,
1233 sizeof(struct ath5k_buf), GFP_KERNEL);
1235 ATH5K_ERR(sc, "can't allocate bufptr\n");
1241 INIT_LIST_HEAD(&sc->rxbuf);
1242 for (i = 0; i < ATH_RXBUF; i++, bf++, ds++, da += sizeof(*ds)) {
1245 list_add_tail(&bf->list, &sc->rxbuf);
1248 INIT_LIST_HEAD(&sc->txbuf);
1249 sc->txbuf_len = ATH_TXBUF;
1250 for (i = 0; i < ATH_TXBUF; i++, bf++, ds++,
1251 da += sizeof(*ds)) {
1254 list_add_tail(&bf->list, &sc->txbuf);
1264 pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
1271 ath5k_desc_free(struct ath5k_softc *sc, struct pci_dev *pdev)
1273 struct ath5k_buf *bf;
1275 ath5k_txbuf_free(sc, sc->bbuf);
1276 list_for_each_entry(bf, &sc->txbuf, list)
1277 ath5k_txbuf_free(sc, bf);
1278 list_for_each_entry(bf, &sc->rxbuf, list)
1279 ath5k_txbuf_free(sc, bf);
1281 /* Free memory associated with all descriptors */
1282 pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
1296 static struct ath5k_txq *
1297 ath5k_txq_setup(struct ath5k_softc *sc,
1298 int qtype, int subtype)
1300 struct ath5k_hw *ah = sc->ah;
1301 struct ath5k_txq *txq;
1302 struct ath5k_txq_info qi = {
1303 .tqi_subtype = subtype,
1304 .tqi_aifs = AR5K_TXQ_USEDEFAULT,
1305 .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
1306 .tqi_cw_max = AR5K_TXQ_USEDEFAULT
1311 * Enable interrupts only for EOL and DESC conditions.
1312 * We mark tx descriptors to receive a DESC interrupt
1313 * when a tx queue gets deep; otherwise waiting for the
1314 * EOL to reap descriptors. Note that this is done to
1315 * reduce interrupt load and this only defers reaping
1316 * descriptors, never transmitting frames. Aside from
1317 * reducing interrupts this also permits more concurrency.
1318 * The only potential downside is if the tx queue backs
1319 * up in which case the top half of the kernel may backup
1320 * due to a lack of tx descriptors.
1322 qi.tqi_flags = AR5K_TXQ_FLAG_TXEOLINT_ENABLE |
1323 AR5K_TXQ_FLAG_TXDESCINT_ENABLE;
1324 qnum = ath5k_hw_setup_tx_queue(ah, qtype, &qi);
1327 * NB: don't print a message, this happens
1328 * normally on parts with too few tx queues
1330 return ERR_PTR(qnum);
1332 if (qnum >= ARRAY_SIZE(sc->txqs)) {
1333 ATH5K_ERR(sc, "hw qnum %u out of range, max %tu!\n",
1334 qnum, ARRAY_SIZE(sc->txqs));
1335 ath5k_hw_release_tx_queue(ah, qnum);
1336 return ERR_PTR(-EINVAL);
1338 txq = &sc->txqs[qnum];
1342 INIT_LIST_HEAD(&txq->q);
1343 spin_lock_init(&txq->lock);
1346 return &sc->txqs[qnum];
1350 ath5k_beaconq_setup(struct ath5k_hw *ah)
1352 struct ath5k_txq_info qi = {
1353 .tqi_aifs = AR5K_TXQ_USEDEFAULT,
1354 .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
1355 .tqi_cw_max = AR5K_TXQ_USEDEFAULT,
1356 /* NB: for dynamic turbo, don't enable any other interrupts */
1357 .tqi_flags = AR5K_TXQ_FLAG_TXDESCINT_ENABLE
1360 return ath5k_hw_setup_tx_queue(ah, AR5K_TX_QUEUE_BEACON, &qi);
1364 ath5k_beaconq_config(struct ath5k_softc *sc)
1366 struct ath5k_hw *ah = sc->ah;
1367 struct ath5k_txq_info qi;
1370 ret = ath5k_hw_get_tx_queueprops(ah, sc->bhalq, &qi);
1373 if (sc->opmode == IEEE80211_IF_TYPE_AP ||
1374 sc->opmode == IEEE80211_IF_TYPE_MESH_POINT) {
1376 * Always burst out beacon and CAB traffic
1377 * (aifs = cwmin = cwmax = 0)
1382 } else if (sc->opmode == IEEE80211_IF_TYPE_IBSS) {
1384 * Adhoc mode; backoff between 0 and (2 * cw_min).
1388 qi.tqi_cw_max = 2 * ah->ah_cw_min;
1391 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
1392 "beacon queueprops tqi_aifs:%d tqi_cw_min:%d tqi_cw_max:%d\n",
1393 qi.tqi_aifs, qi.tqi_cw_min, qi.tqi_cw_max);
1395 ret = ath5k_hw_setup_tx_queueprops(ah, sc->bhalq, &qi);
1397 ATH5K_ERR(sc, "%s: unable to update parameters for beacon "
1398 "hardware queue!\n", __func__);
1402 return ath5k_hw_reset_tx_queue(ah, sc->bhalq); /* push to h/w */;
1406 ath5k_txq_drainq(struct ath5k_softc *sc, struct ath5k_txq *txq)
1408 struct ath5k_buf *bf, *bf0;
1411 * NB: this assumes output has been stopped and
1412 * we do not need to block ath5k_tx_tasklet
1414 spin_lock_bh(&txq->lock);
1415 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
1416 ath5k_debug_printtxbuf(sc, bf);
1418 ath5k_txbuf_free(sc, bf);
1420 spin_lock_bh(&sc->txbuflock);
1421 sc->tx_stats[txq->qnum].len--;
1422 list_move_tail(&bf->list, &sc->txbuf);
1424 spin_unlock_bh(&sc->txbuflock);
1427 spin_unlock_bh(&txq->lock);
1431 * Drain the transmit queues and reclaim resources.
1434 ath5k_txq_cleanup(struct ath5k_softc *sc)
1436 struct ath5k_hw *ah = sc->ah;
1439 /* XXX return value */
1440 if (likely(!test_bit(ATH_STAT_INVALID, sc->status))) {
1441 /* don't touch the hardware if marked invalid */
1442 ath5k_hw_stop_tx_dma(ah, sc->bhalq);
1443 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "beacon queue %x\n",
1444 ath5k_hw_get_tx_buf(ah, sc->bhalq));
1445 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1446 if (sc->txqs[i].setup) {
1447 ath5k_hw_stop_tx_dma(ah, sc->txqs[i].qnum);
1448 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "txq [%u] %x, "
1451 ath5k_hw_get_tx_buf(ah,
1456 ieee80211_wake_queues(sc->hw); /* XXX move to callers */
1458 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1459 if (sc->txqs[i].setup)
1460 ath5k_txq_drainq(sc, &sc->txqs[i]);
1464 ath5k_txq_release(struct ath5k_softc *sc)
1466 struct ath5k_txq *txq = sc->txqs;
1469 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++, txq++)
1471 ath5k_hw_release_tx_queue(sc->ah, txq->qnum);
1484 * Enable the receive h/w following a reset.
1487 ath5k_rx_start(struct ath5k_softc *sc)
1489 struct ath5k_hw *ah = sc->ah;
1490 struct ath5k_buf *bf;
1493 sc->rxbufsize = roundup(IEEE80211_MAX_LEN, sc->cachelsz);
1495 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "cachelsz %u rxbufsize %u\n",
1496 sc->cachelsz, sc->rxbufsize);
1500 spin_lock_bh(&sc->rxbuflock);
1501 list_for_each_entry(bf, &sc->rxbuf, list) {
1502 ret = ath5k_rxbuf_setup(sc, bf);
1504 spin_unlock_bh(&sc->rxbuflock);
1508 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1509 spin_unlock_bh(&sc->rxbuflock);
1511 ath5k_hw_put_rx_buf(ah, bf->daddr);
1512 ath5k_hw_start_rx(ah); /* enable recv descriptors */
1513 ath5k_mode_setup(sc); /* set filters, etc. */
1514 ath5k_hw_start_rx_pcu(ah); /* re-enable PCU/DMA engine */
1522 * Disable the receive h/w in preparation for a reset.
1525 ath5k_rx_stop(struct ath5k_softc *sc)
1527 struct ath5k_hw *ah = sc->ah;
1529 ath5k_hw_stop_pcu_recv(ah); /* disable PCU */
1530 ath5k_hw_set_rx_filter(ah, 0); /* clear recv filter */
1531 ath5k_hw_stop_rx_dma(ah); /* disable DMA engine */
1533 ath5k_debug_printrxbuffs(sc, ah);
1535 sc->rxlink = NULL; /* just in case */
1539 ath5k_rx_decrypted(struct ath5k_softc *sc, struct ath5k_desc *ds,
1540 struct sk_buff *skb, struct ath5k_rx_status *rs)
1542 struct ieee80211_hdr *hdr = (void *)skb->data;
1543 unsigned int keyix, hlen;
1545 if (!(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1546 rs->rs_keyix != AR5K_RXKEYIX_INVALID)
1547 return RX_FLAG_DECRYPTED;
1549 /* Apparently when a default key is used to decrypt the packet
1550 the hw does not set the index used to decrypt. In such cases
1551 get the index from the packet. */
1552 hlen = ieee80211_hdrlen(hdr->frame_control);
1553 if (ieee80211_has_protected(hdr->frame_control) &&
1554 !(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1555 skb->len >= hlen + 4) {
1556 keyix = skb->data[hlen + 3] >> 6;
1558 if (test_bit(keyix, sc->keymap))
1559 return RX_FLAG_DECRYPTED;
1567 ath5k_check_ibss_tsf(struct ath5k_softc *sc, struct sk_buff *skb,
1568 struct ieee80211_rx_status *rxs)
1572 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
1574 if (ieee80211_is_beacon(mgmt->frame_control) &&
1575 le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS &&
1576 memcmp(mgmt->bssid, sc->ah->ah_bssid, ETH_ALEN) == 0) {
1578 * Received an IBSS beacon with the same BSSID. Hardware *must*
1579 * have updated the local TSF. We have to work around various
1580 * hardware bugs, though...
1582 tsf = ath5k_hw_get_tsf64(sc->ah);
1583 bc_tstamp = le64_to_cpu(mgmt->u.beacon.timestamp);
1584 hw_tu = TSF_TO_TU(tsf);
1586 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1587 "beacon %llx mactime %llx (diff %lld) tsf now %llx\n",
1588 (unsigned long long)bc_tstamp,
1589 (unsigned long long)rxs->mactime,
1590 (unsigned long long)(rxs->mactime - bc_tstamp),
1591 (unsigned long long)tsf);
1594 * Sometimes the HW will give us a wrong tstamp in the rx
1595 * status, causing the timestamp extension to go wrong.
1596 * (This seems to happen especially with beacon frames bigger
1597 * than 78 byte (incl. FCS))
1598 * But we know that the receive timestamp must be later than the
1599 * timestamp of the beacon since HW must have synced to that.
1601 * NOTE: here we assume mactime to be after the frame was
1602 * received, not like mac80211 which defines it at the start.
1604 if (bc_tstamp > rxs->mactime) {
1605 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1606 "fixing mactime from %llx to %llx\n",
1607 (unsigned long long)rxs->mactime,
1608 (unsigned long long)tsf);
1613 * Local TSF might have moved higher than our beacon timers,
1614 * in that case we have to update them to continue sending
1615 * beacons. This also takes care of synchronizing beacon sending
1616 * times with other stations.
1618 if (hw_tu >= sc->nexttbtt)
1619 ath5k_beacon_update_timers(sc, bc_tstamp);
1625 ath5k_tasklet_rx(unsigned long data)
1627 struct ieee80211_rx_status rxs = {};
1628 struct ath5k_rx_status rs = {};
1629 struct sk_buff *skb;
1630 struct ath5k_softc *sc = (void *)data;
1631 struct ath5k_buf *bf, *bf_last;
1632 struct ath5k_desc *ds;
1637 spin_lock(&sc->rxbuflock);
1638 if (list_empty(&sc->rxbuf)) {
1639 ATH5K_WARN(sc, "empty rx buf pool\n");
1642 bf_last = list_entry(sc->rxbuf.prev, struct ath5k_buf, list);
1646 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1647 BUG_ON(bf->skb == NULL);
1652 * last buffer must not be freed to ensure proper hardware
1653 * function. When the hardware finishes also a packet next to
1654 * it, we are sure, it doesn't use it anymore and we can go on.
1659 struct ath5k_buf *bf_next = list_entry(bf->list.next,
1660 struct ath5k_buf, list);
1661 ret = sc->ah->ah_proc_rx_desc(sc->ah, bf_next->desc,
1666 /* skip the overwritten one (even status is martian) */
1670 ret = sc->ah->ah_proc_rx_desc(sc->ah, ds, &rs);
1671 if (unlikely(ret == -EINPROGRESS))
1673 else if (unlikely(ret)) {
1674 ATH5K_ERR(sc, "error in processing rx descriptor\n");
1675 spin_unlock(&sc->rxbuflock);
1679 if (unlikely(rs.rs_more)) {
1680 ATH5K_WARN(sc, "unsupported jumbo\n");
1684 if (unlikely(rs.rs_status)) {
1685 if (rs.rs_status & AR5K_RXERR_PHY)
1687 if (rs.rs_status & AR5K_RXERR_DECRYPT) {
1689 * Decrypt error. If the error occurred
1690 * because there was no hardware key, then
1691 * let the frame through so the upper layers
1692 * can process it. This is necessary for 5210
1693 * parts which have no way to setup a ``clear''
1696 * XXX do key cache faulting
1698 if (rs.rs_keyix == AR5K_RXKEYIX_INVALID &&
1699 !(rs.rs_status & AR5K_RXERR_CRC))
1702 if (rs.rs_status & AR5K_RXERR_MIC) {
1703 rxs.flag |= RX_FLAG_MMIC_ERROR;
1707 /* let crypto-error packets fall through in MNTR */
1709 ~(AR5K_RXERR_DECRYPT|AR5K_RXERR_MIC)) ||
1710 sc->opmode != IEEE80211_IF_TYPE_MNTR)
1714 pci_unmap_single(sc->pdev, bf->skbaddr, sc->rxbufsize,
1715 PCI_DMA_FROMDEVICE);
1718 skb_put(skb, rs.rs_datalen);
1721 * the hardware adds a padding to 4 byte boundaries between
1722 * the header and the payload data if the header length is
1723 * not multiples of 4 - remove it
1725 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
1728 memmove(skb->data + pad, skb->data, hdrlen);
1733 * always extend the mac timestamp, since this information is
1734 * also needed for proper IBSS merging.
1736 * XXX: it might be too late to do it here, since rs_tstamp is
1737 * 15bit only. that means TSF extension has to be done within
1738 * 32768usec (about 32ms). it might be necessary to move this to
1739 * the interrupt handler, like it is done in madwifi.
1741 * Unfortunately we don't know when the hardware takes the rx
1742 * timestamp (beginning of phy frame, data frame, end of rx?).
1743 * The only thing we know is that it is hardware specific...
1744 * On AR5213 it seems the rx timestamp is at the end of the
1745 * frame, but i'm not sure.
1747 * NOTE: mac80211 defines mactime at the beginning of the first
1748 * data symbol. Since we don't have any time references it's
1749 * impossible to comply to that. This affects IBSS merge only
1750 * right now, so it's not too bad...
1752 rxs.mactime = ath5k_extend_tsf(sc->ah, rs.rs_tstamp);
1753 rxs.flag |= RX_FLAG_TSFT;
1755 rxs.freq = sc->curchan->center_freq;
1756 rxs.band = sc->curband->band;
1758 rxs.noise = sc->ah->ah_noise_floor;
1759 rxs.signal = rxs.noise + rs.rs_rssi;
1760 rxs.qual = rs.rs_rssi * 100 / 64;
1762 rxs.antenna = rs.rs_antenna;
1763 rxs.rate_idx = ath5k_hw_to_driver_rix(sc, rs.rs_rate);
1764 rxs.flag |= ath5k_rx_decrypted(sc, ds, skb, &rs);
1766 if (rxs.rate_idx >= 0 && rs.rs_rate ==
1767 sc->curband->bitrates[rxs.rate_idx].hw_value_short)
1768 rxs.flag |= RX_FLAG_SHORTPRE;
1770 ath5k_debug_dump_skb(sc, skb, "RX ", 0);
1772 /* check beacons in IBSS mode */
1773 if (sc->opmode == IEEE80211_IF_TYPE_IBSS)
1774 ath5k_check_ibss_tsf(sc, skb, &rxs);
1776 __ieee80211_rx(sc->hw, skb, &rxs);
1778 list_move_tail(&bf->list, &sc->rxbuf);
1779 } while (ath5k_rxbuf_setup(sc, bf) == 0);
1781 spin_unlock(&sc->rxbuflock);
1792 ath5k_tx_processq(struct ath5k_softc *sc, struct ath5k_txq *txq)
1794 struct ath5k_tx_status ts = {};
1795 struct ath5k_buf *bf, *bf0;
1796 struct ath5k_desc *ds;
1797 struct sk_buff *skb;
1798 struct ieee80211_tx_info *info;
1801 spin_lock(&txq->lock);
1802 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
1805 ret = sc->ah->ah_proc_tx_desc(sc->ah, ds, &ts);
1806 if (unlikely(ret == -EINPROGRESS))
1808 else if (unlikely(ret)) {
1809 ATH5K_ERR(sc, "error %d while processing queue %u\n",
1815 info = IEEE80211_SKB_CB(skb);
1818 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len,
1821 info->status.retry_count = ts.ts_shortretry + ts.ts_longretry / 6;
1822 if (unlikely(ts.ts_status)) {
1823 sc->ll_stats.dot11ACKFailureCount++;
1824 if (ts.ts_status & AR5K_TXERR_XRETRY)
1825 info->status.excessive_retries = 1;
1826 else if (ts.ts_status & AR5K_TXERR_FILT)
1827 info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
1829 info->flags |= IEEE80211_TX_STAT_ACK;
1830 info->status.ack_signal = ts.ts_rssi;
1833 ieee80211_tx_status(sc->hw, skb);
1834 sc->tx_stats[txq->qnum].count++;
1836 spin_lock(&sc->txbuflock);
1837 sc->tx_stats[txq->qnum].len--;
1838 list_move_tail(&bf->list, &sc->txbuf);
1840 spin_unlock(&sc->txbuflock);
1842 if (likely(list_empty(&txq->q)))
1844 spin_unlock(&txq->lock);
1845 if (sc->txbuf_len > ATH_TXBUF / 5)
1846 ieee80211_wake_queues(sc->hw);
1850 ath5k_tasklet_tx(unsigned long data)
1852 struct ath5k_softc *sc = (void *)data;
1854 ath5k_tx_processq(sc, sc->txq);
1863 * Setup the beacon frame for transmit.
1866 ath5k_beacon_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
1868 struct sk_buff *skb = bf->skb;
1869 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1870 struct ath5k_hw *ah = sc->ah;
1871 struct ath5k_desc *ds;
1872 int ret, antenna = 0;
1875 bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
1877 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "skb %p [data %p len %u] "
1878 "skbaddr %llx\n", skb, skb->data, skb->len,
1879 (unsigned long long)bf->skbaddr);
1880 if (pci_dma_mapping_error(sc->pdev, bf->skbaddr)) {
1881 ATH5K_ERR(sc, "beacon DMA mapping failed\n");
1887 flags = AR5K_TXDESC_NOACK;
1888 if (sc->opmode == IEEE80211_IF_TYPE_IBSS && ath5k_hw_hasveol(ah)) {
1889 ds->ds_link = bf->daddr; /* self-linked */
1890 flags |= AR5K_TXDESC_VEOL;
1892 * Let hardware handle antenna switching if txantenna is not set
1897 * Switch antenna every 4 beacons if txantenna is not set
1898 * XXX assumes two antennas
1901 antenna = sc->bsent & 4 ? 2 : 1;
1904 ds->ds_data = bf->skbaddr;
1905 ret = ah->ah_setup_tx_desc(ah, ds, skb->len,
1906 ieee80211_get_hdrlen_from_skb(skb),
1907 AR5K_PKT_TYPE_BEACON, (sc->power_level * 2),
1908 ieee80211_get_tx_rate(sc->hw, info)->hw_value,
1909 1, AR5K_TXKEYIX_INVALID,
1910 antenna, flags, 0, 0);
1916 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
1921 * Transmit a beacon frame at SWBA. Dynamic updates to the
1922 * frame contents are done as needed and the slot time is
1923 * also adjusted based on current state.
1925 * this is usually called from interrupt context (ath5k_intr())
1926 * but also from ath5k_beacon_config() in IBSS mode which in turn
1927 * can be called from a tasklet and user context
1930 ath5k_beacon_send(struct ath5k_softc *sc)
1932 struct ath5k_buf *bf = sc->bbuf;
1933 struct ath5k_hw *ah = sc->ah;
1935 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "in beacon_send\n");
1937 if (unlikely(bf->skb == NULL || sc->opmode == IEEE80211_IF_TYPE_STA ||
1938 sc->opmode == IEEE80211_IF_TYPE_MNTR)) {
1939 ATH5K_WARN(sc, "bf=%p bf_skb=%p\n", bf, bf ? bf->skb : NULL);
1943 * Check if the previous beacon has gone out. If
1944 * not don't don't try to post another, skip this
1945 * period and wait for the next. Missed beacons
1946 * indicate a problem and should not occur. If we
1947 * miss too many consecutive beacons reset the device.
1949 if (unlikely(ath5k_hw_num_tx_pending(ah, sc->bhalq) != 0)) {
1951 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
1952 "missed %u consecutive beacons\n", sc->bmisscount);
1953 if (sc->bmisscount > 3) { /* NB: 3 is a guess */
1954 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
1955 "stuck beacon time (%u missed)\n",
1957 tasklet_schedule(&sc->restq);
1961 if (unlikely(sc->bmisscount != 0)) {
1962 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
1963 "resume beacon xmit after %u misses\n",
1969 * Stop any current dma and put the new frame on the queue.
1970 * This should never fail since we check above that no frames
1971 * are still pending on the queue.
1973 if (unlikely(ath5k_hw_stop_tx_dma(ah, sc->bhalq))) {
1974 ATH5K_WARN(sc, "beacon queue %u didn't stop?\n", sc->bhalq);
1975 /* NB: hw still stops DMA, so proceed */
1978 ath5k_hw_put_tx_buf(ah, sc->bhalq, bf->daddr);
1979 ath5k_hw_tx_start(ah, sc->bhalq);
1980 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "TXDP[%u] = %llx (%p)\n",
1981 sc->bhalq, (unsigned long long)bf->daddr, bf->desc);
1988 * ath5k_beacon_update_timers - update beacon timers
1990 * @sc: struct ath5k_softc pointer we are operating on
1991 * @bc_tsf: the timestamp of the beacon. 0 to reset the TSF. -1 to perform a
1992 * beacon timer update based on the current HW TSF.
1994 * Calculate the next target beacon transmit time (TBTT) based on the timestamp
1995 * of a received beacon or the current local hardware TSF and write it to the
1996 * beacon timer registers.
1998 * This is called in a variety of situations, e.g. when a beacon is received,
1999 * when a TSF update has been detected, but also when an new IBSS is created or
2000 * when we otherwise know we have to update the timers, but we keep it in this
2001 * function to have it all together in one place.
2004 ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf)
2006 struct ath5k_hw *ah = sc->ah;
2007 u32 nexttbtt, intval, hw_tu, bc_tu;
2010 intval = sc->bintval & AR5K_BEACON_PERIOD;
2011 if (WARN_ON(!intval))
2014 /* beacon TSF converted to TU */
2015 bc_tu = TSF_TO_TU(bc_tsf);
2017 /* current TSF converted to TU */
2018 hw_tsf = ath5k_hw_get_tsf64(ah);
2019 hw_tu = TSF_TO_TU(hw_tsf);
2022 /* we use FUDGE to make sure the next TBTT is ahead of the current TU */
2025 * no beacons received, called internally.
2026 * just need to refresh timers based on HW TSF.
2028 nexttbtt = roundup(hw_tu + FUDGE, intval);
2029 } else if (bc_tsf == 0) {
2031 * no beacon received, probably called by ath5k_reset_tsf().
2032 * reset TSF to start with 0.
2035 intval |= AR5K_BEACON_RESET_TSF;
2036 } else if (bc_tsf > hw_tsf) {
2038 * beacon received, SW merge happend but HW TSF not yet updated.
2039 * not possible to reconfigure timers yet, but next time we
2040 * receive a beacon with the same BSSID, the hardware will
2041 * automatically update the TSF and then we need to reconfigure
2044 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2045 "need to wait for HW TSF sync\n");
2049 * most important case for beacon synchronization between STA.
2051 * beacon received and HW TSF has been already updated by HW.
2052 * update next TBTT based on the TSF of the beacon, but make
2053 * sure it is ahead of our local TSF timer.
2055 nexttbtt = bc_tu + roundup(hw_tu + FUDGE - bc_tu, intval);
2059 sc->nexttbtt = nexttbtt;
2061 intval |= AR5K_BEACON_ENA;
2062 ath5k_hw_init_beacon(ah, nexttbtt, intval);
2065 * debugging output last in order to preserve the time critical aspect
2069 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2070 "reconfigured timers based on HW TSF\n");
2071 else if (bc_tsf == 0)
2072 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2073 "reset HW TSF and timers\n");
2075 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2076 "updated timers based on beacon TSF\n");
2078 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2079 "bc_tsf %llx hw_tsf %llx bc_tu %u hw_tu %u nexttbtt %u\n",
2080 (unsigned long long) bc_tsf,
2081 (unsigned long long) hw_tsf, bc_tu, hw_tu, nexttbtt);
2082 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "intval %u %s %s\n",
2083 intval & AR5K_BEACON_PERIOD,
2084 intval & AR5K_BEACON_ENA ? "AR5K_BEACON_ENA" : "",
2085 intval & AR5K_BEACON_RESET_TSF ? "AR5K_BEACON_RESET_TSF" : "");
2090 * ath5k_beacon_config - Configure the beacon queues and interrupts
2092 * @sc: struct ath5k_softc pointer we are operating on
2094 * When operating in station mode we want to receive a BMISS interrupt when we
2095 * stop seeing beacons from the AP we've associated with so we can look for
2096 * another AP to associate with.
2098 * In IBSS mode we use a self-linked tx descriptor if possible. We enable SWBA
2099 * interrupts to detect TSF updates only.
2101 * AP mode is missing.
2104 ath5k_beacon_config(struct ath5k_softc *sc)
2106 struct ath5k_hw *ah = sc->ah;
2108 ath5k_hw_set_intr(ah, 0);
2110 sc->imask &= ~(AR5K_INT_BMISS | AR5K_INT_SWBA);
2112 if (sc->opmode == IEEE80211_IF_TYPE_STA) {
2113 sc->imask |= AR5K_INT_BMISS;
2114 } else if (sc->opmode == IEEE80211_IF_TYPE_IBSS) {
2116 * In IBSS mode we use a self-linked tx descriptor and let the
2117 * hardware send the beacons automatically. We have to load it
2119 * We use the SWBA interrupt only to keep track of the beacon
2120 * timers in order to detect automatic TSF updates.
2122 ath5k_beaconq_config(sc);
2124 sc->imask |= AR5K_INT_SWBA;
2126 if (ath5k_hw_hasveol(ah))
2127 ath5k_beacon_send(sc);
2131 ath5k_hw_set_intr(ah, sc->imask);
2135 /********************\
2136 * Interrupt handling *
2137 \********************/
2140 ath5k_init(struct ath5k_softc *sc)
2144 mutex_lock(&sc->lock);
2146 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mode %d\n", sc->opmode);
2149 * Stop anything previously setup. This is safe
2150 * no matter this is the first time through or not.
2152 ath5k_stop_locked(sc);
2155 * The basic interface to setting the hardware in a good
2156 * state is ``reset''. On return the hardware is known to
2157 * be powered up and with interrupts disabled. This must
2158 * be followed by initialization of the appropriate bits
2159 * and then setup of the interrupt mask.
2161 sc->curchan = sc->hw->conf.channel;
2162 sc->curband = &sc->sbands[sc->curchan->band];
2163 sc->imask = AR5K_INT_RX | AR5K_INT_TX | AR5K_INT_RXEOL |
2164 AR5K_INT_RXORN | AR5K_INT_FATAL | AR5K_INT_GLOBAL |
2166 ret = ath5k_reset(sc, false, false);
2170 /* Set ack to be sent at low bit-rates */
2171 ath5k_hw_set_ack_bitrate_high(sc->ah, false);
2173 mod_timer(&sc->calib_tim, round_jiffies(jiffies +
2174 msecs_to_jiffies(ath5k_calinterval * 1000)));
2179 mutex_unlock(&sc->lock);
2184 ath5k_stop_locked(struct ath5k_softc *sc)
2186 struct ath5k_hw *ah = sc->ah;
2188 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "invalid %u\n",
2189 test_bit(ATH_STAT_INVALID, sc->status));
2192 * Shutdown the hardware and driver:
2193 * stop output from above
2194 * disable interrupts
2196 * turn off the radio
2197 * clear transmit machinery
2198 * clear receive machinery
2199 * drain and release tx queues
2200 * reclaim beacon resources
2201 * power down hardware
2203 * Note that some of this work is not possible if the
2204 * hardware is gone (invalid).
2206 ieee80211_stop_queues(sc->hw);
2208 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
2210 ath5k_hw_set_intr(ah, 0);
2211 synchronize_irq(sc->pdev->irq);
2213 ath5k_txq_cleanup(sc);
2214 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
2216 ath5k_hw_phy_disable(ah);
2224 * Stop the device, grabbing the top-level lock to protect
2225 * against concurrent entry through ath5k_init (which can happen
2226 * if another thread does a system call and the thread doing the
2227 * stop is preempted).
2230 ath5k_stop_hw(struct ath5k_softc *sc)
2234 mutex_lock(&sc->lock);
2235 ret = ath5k_stop_locked(sc);
2236 if (ret == 0 && !test_bit(ATH_STAT_INVALID, sc->status)) {
2238 * Set the chip in full sleep mode. Note that we are
2239 * careful to do this only when bringing the interface
2240 * completely to a stop. When the chip is in this state
2241 * it must be carefully woken up or references to
2242 * registers in the PCI clock domain may freeze the bus
2243 * (and system). This varies by chip and is mostly an
2244 * issue with newer parts that go to sleep more quickly.
2246 if (sc->ah->ah_mac_srev >= 0x78) {
2249 * don't put newer MAC revisions > 7.8 to sleep because
2250 * of the above mentioned problems
2252 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mac version > 7.8, "
2253 "not putting device to sleep\n");
2255 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2256 "putting device to full sleep\n");
2257 ath5k_hw_set_power(sc->ah, AR5K_PM_FULL_SLEEP, true, 0);
2260 ath5k_txbuf_free(sc, sc->bbuf);
2262 mutex_unlock(&sc->lock);
2264 del_timer_sync(&sc->calib_tim);
2265 tasklet_kill(&sc->rxtq);
2266 tasklet_kill(&sc->txtq);
2267 tasklet_kill(&sc->restq);
2273 ath5k_intr(int irq, void *dev_id)
2275 struct ath5k_softc *sc = dev_id;
2276 struct ath5k_hw *ah = sc->ah;
2277 enum ath5k_int status;
2278 unsigned int counter = 1000;
2280 if (unlikely(test_bit(ATH_STAT_INVALID, sc->status) ||
2281 !ath5k_hw_is_intr_pending(ah)))
2286 * Figure out the reason(s) for the interrupt. Note
2287 * that get_isr returns a pseudo-ISR that may include
2288 * bits we haven't explicitly enabled so we mask the
2289 * value to insure we only process bits we requested.
2291 ath5k_hw_get_isr(ah, &status); /* NB: clears IRQ too */
2292 ATH5K_DBG(sc, ATH5K_DEBUG_INTR, "status 0x%x/0x%x\n",
2294 status &= sc->imask; /* discard unasked for bits */
2295 if (unlikely(status & AR5K_INT_FATAL)) {
2297 * Fatal errors are unrecoverable.
2298 * Typically these are caused by DMA errors.
2300 tasklet_schedule(&sc->restq);
2301 } else if (unlikely(status & AR5K_INT_RXORN)) {
2302 tasklet_schedule(&sc->restq);
2304 if (status & AR5K_INT_SWBA) {
2306 * Software beacon alert--time to send a beacon.
2307 * Handle beacon transmission directly; deferring
2308 * this is too slow to meet timing constraints
2311 * In IBSS mode we use this interrupt just to
2312 * keep track of the next TBTT (target beacon
2313 * transmission time) in order to detect wether
2314 * automatic TSF updates happened.
2316 if (sc->opmode == IEEE80211_IF_TYPE_IBSS) {
2317 /* XXX: only if VEOL suppported */
2318 u64 tsf = ath5k_hw_get_tsf64(ah);
2319 sc->nexttbtt += sc->bintval;
2320 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2321 "SWBA nexttbtt: %x hw_tu: %x "
2325 (unsigned long long) tsf);
2327 ath5k_beacon_send(sc);
2330 if (status & AR5K_INT_RXEOL) {
2332 * NB: the hardware should re-read the link when
2333 * RXE bit is written, but it doesn't work at
2334 * least on older hardware revs.
2338 if (status & AR5K_INT_TXURN) {
2339 /* bump tx trigger level */
2340 ath5k_hw_update_tx_triglevel(ah, true);
2342 if (status & AR5K_INT_RX)
2343 tasklet_schedule(&sc->rxtq);
2344 if (status & AR5K_INT_TX)
2345 tasklet_schedule(&sc->txtq);
2346 if (status & AR5K_INT_BMISS) {
2348 if (status & AR5K_INT_MIB) {
2350 * These stats are also used for ANI i think
2351 * so how about updating them more often ?
2353 ath5k_hw_update_mib_counters(ah, &sc->ll_stats);
2356 } while (ath5k_hw_is_intr_pending(ah) && counter-- > 0);
2358 if (unlikely(!counter))
2359 ATH5K_WARN(sc, "too many interrupts, giving up for now\n");
2365 ath5k_tasklet_reset(unsigned long data)
2367 struct ath5k_softc *sc = (void *)data;
2369 ath5k_reset_wake(sc);
2373 * Periodically recalibrate the PHY to account
2374 * for temperature/environment changes.
2377 ath5k_calibrate(unsigned long data)
2379 struct ath5k_softc *sc = (void *)data;
2380 struct ath5k_hw *ah = sc->ah;
2382 ATH5K_DBG(sc, ATH5K_DEBUG_CALIBRATE, "channel %u/%x\n",
2383 ieee80211_frequency_to_channel(sc->curchan->center_freq),
2384 sc->curchan->hw_value);
2386 if (ath5k_hw_get_rf_gain(ah) == AR5K_RFGAIN_NEED_CHANGE) {
2388 * Rfgain is out of bounds, reset the chip
2389 * to load new gain values.
2391 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "calibration, resetting\n");
2392 ath5k_reset_wake(sc);
2394 if (ath5k_hw_phy_calibrate(ah, sc->curchan))
2395 ATH5K_ERR(sc, "calibration of channel %u failed\n",
2396 ieee80211_frequency_to_channel(
2397 sc->curchan->center_freq));
2399 mod_timer(&sc->calib_tim, round_jiffies(jiffies +
2400 msecs_to_jiffies(ath5k_calinterval * 1000)));
2410 ath5k_led_enable(struct ath5k_softc *sc)
2412 if (test_bit(ATH_STAT_LEDSOFT, sc->status)) {
2413 ath5k_hw_set_gpio_output(sc->ah, sc->led_pin);
2419 ath5k_led_on(struct ath5k_softc *sc)
2421 if (!test_bit(ATH_STAT_LEDSOFT, sc->status))
2423 ath5k_hw_set_gpio(sc->ah, sc->led_pin, sc->led_on);
2427 ath5k_led_off(struct ath5k_softc *sc)
2429 if (!test_bit(ATH_STAT_LEDSOFT, sc->status))
2431 ath5k_hw_set_gpio(sc->ah, sc->led_pin, !sc->led_on);
2435 ath5k_led_brightness_set(struct led_classdev *led_dev,
2436 enum led_brightness brightness)
2438 struct ath5k_led *led = container_of(led_dev, struct ath5k_led,
2441 if (brightness == LED_OFF)
2442 ath5k_led_off(led->sc);
2444 ath5k_led_on(led->sc);
2448 ath5k_register_led(struct ath5k_softc *sc, struct ath5k_led *led,
2449 const char *name, char *trigger)
2454 strncpy(led->name, name, sizeof(led->name));
2455 led->led_dev.name = led->name;
2456 led->led_dev.default_trigger = trigger;
2457 led->led_dev.brightness_set = ath5k_led_brightness_set;
2459 err = led_classdev_register(&sc->pdev->dev, &led->led_dev);
2462 ATH5K_WARN(sc, "could not register LED %s\n", name);
2469 ath5k_unregister_led(struct ath5k_led *led)
2473 led_classdev_unregister(&led->led_dev);
2474 ath5k_led_off(led->sc);
2479 ath5k_unregister_leds(struct ath5k_softc *sc)
2481 ath5k_unregister_led(&sc->rx_led);
2482 ath5k_unregister_led(&sc->tx_led);
2487 ath5k_init_leds(struct ath5k_softc *sc)
2490 struct ieee80211_hw *hw = sc->hw;
2491 struct pci_dev *pdev = sc->pdev;
2492 char name[ATH5K_LED_MAX_NAME_LEN + 1];
2495 * Auto-enable soft led processing for IBM cards and for
2496 * 5211 minipci cards.
2498 if (pdev->device == PCI_DEVICE_ID_ATHEROS_AR5212_IBM ||
2499 pdev->device == PCI_DEVICE_ID_ATHEROS_AR5211) {
2500 __set_bit(ATH_STAT_LEDSOFT, sc->status);
2502 sc->led_on = 0; /* active low */
2504 /* Enable softled on PIN1 on HP Compaq nc6xx, nc4000 & nx5000 laptops */
2505 if (pdev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ) {
2506 __set_bit(ATH_STAT_LEDSOFT, sc->status);
2508 sc->led_on = 1; /* active high */
2510 if (!test_bit(ATH_STAT_LEDSOFT, sc->status))
2513 ath5k_led_enable(sc);
2515 snprintf(name, sizeof(name), "ath5k-%s::rx", wiphy_name(hw->wiphy));
2516 ret = ath5k_register_led(sc, &sc->rx_led, name,
2517 ieee80211_get_rx_led_name(hw));
2521 snprintf(name, sizeof(name), "ath5k-%s::tx", wiphy_name(hw->wiphy));
2522 ret = ath5k_register_led(sc, &sc->tx_led, name,
2523 ieee80211_get_tx_led_name(hw));
2529 /********************\
2530 * Mac80211 functions *
2531 \********************/
2534 ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
2536 struct ath5k_softc *sc = hw->priv;
2537 struct ath5k_buf *bf;
2538 unsigned long flags;
2542 ath5k_debug_dump_skb(sc, skb, "TX ", 1);
2544 if (sc->opmode == IEEE80211_IF_TYPE_MNTR)
2545 ATH5K_DBG(sc, ATH5K_DEBUG_XMIT, "tx in monitor (scan?)\n");
2548 * the hardware expects the header padded to 4 byte boundaries
2549 * if this is not the case we add the padding after the header
2551 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
2554 if (skb_headroom(skb) < pad) {
2555 ATH5K_ERR(sc, "tx hdrlen not %%4: %d not enough"
2556 " headroom to pad %d\n", hdrlen, pad);
2560 memmove(skb->data, skb->data+pad, hdrlen);
2563 spin_lock_irqsave(&sc->txbuflock, flags);
2564 if (list_empty(&sc->txbuf)) {
2565 ATH5K_ERR(sc, "no further txbuf available, dropping packet\n");
2566 spin_unlock_irqrestore(&sc->txbuflock, flags);
2567 ieee80211_stop_queue(hw, skb_get_queue_mapping(skb));
2570 bf = list_first_entry(&sc->txbuf, struct ath5k_buf, list);
2571 list_del(&bf->list);
2573 if (list_empty(&sc->txbuf))
2574 ieee80211_stop_queues(hw);
2575 spin_unlock_irqrestore(&sc->txbuflock, flags);
2579 if (ath5k_txbuf_setup(sc, bf)) {
2581 spin_lock_irqsave(&sc->txbuflock, flags);
2582 list_add_tail(&bf->list, &sc->txbuf);
2584 spin_unlock_irqrestore(&sc->txbuflock, flags);
2585 dev_kfree_skb_any(skb);
2593 ath5k_reset(struct ath5k_softc *sc, bool stop, bool change_channel)
2595 struct ath5k_hw *ah = sc->ah;
2598 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "resetting\n");
2601 ath5k_hw_set_intr(ah, 0);
2602 ath5k_txq_cleanup(sc);
2605 ret = ath5k_hw_reset(ah, sc->opmode, sc->curchan, true);
2607 ATH5K_ERR(sc, "can't reset hardware (%d)\n", ret);
2612 * This is needed only to setup initial state
2613 * but it's best done after a reset.
2615 ath5k_hw_set_txpower_limit(sc->ah, 0);
2617 ret = ath5k_rx_start(sc);
2619 ATH5K_ERR(sc, "can't start recv logic\n");
2624 * Change channels and update the h/w rate map if we're switching;
2625 * e.g. 11a to 11b/g.
2627 * We may be doing a reset in response to an ioctl that changes the
2628 * channel so update any state that might change as a result.
2632 /* ath5k_chan_change(sc, c); */
2634 ath5k_beacon_config(sc);
2635 /* intrs are enabled by ath5k_beacon_config */
2643 ath5k_reset_wake(struct ath5k_softc *sc)
2647 ret = ath5k_reset(sc, true, true);
2649 ieee80211_wake_queues(sc->hw);
2654 static int ath5k_start(struct ieee80211_hw *hw)
2656 return ath5k_init(hw->priv);
2659 static void ath5k_stop(struct ieee80211_hw *hw)
2661 ath5k_stop_hw(hw->priv);
2664 static int ath5k_add_interface(struct ieee80211_hw *hw,
2665 struct ieee80211_if_init_conf *conf)
2667 struct ath5k_softc *sc = hw->priv;
2670 mutex_lock(&sc->lock);
2676 sc->vif = conf->vif;
2678 switch (conf->type) {
2679 case IEEE80211_IF_TYPE_STA:
2680 case IEEE80211_IF_TYPE_IBSS:
2681 case IEEE80211_IF_TYPE_MNTR:
2682 sc->opmode = conf->type;
2690 mutex_unlock(&sc->lock);
2695 ath5k_remove_interface(struct ieee80211_hw *hw,
2696 struct ieee80211_if_init_conf *conf)
2698 struct ath5k_softc *sc = hw->priv;
2700 mutex_lock(&sc->lock);
2701 if (sc->vif != conf->vif)
2706 mutex_unlock(&sc->lock);
2710 * TODO: Phy disable/diversity etc
2713 ath5k_config(struct ieee80211_hw *hw,
2714 struct ieee80211_conf *conf)
2716 struct ath5k_softc *sc = hw->priv;
2718 sc->bintval = conf->beacon_int;
2719 sc->power_level = conf->power_level;
2721 return ath5k_chan_set(sc, conf->channel);
2725 ath5k_config_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
2726 struct ieee80211_if_conf *conf)
2728 struct ath5k_softc *sc = hw->priv;
2729 struct ath5k_hw *ah = sc->ah;
2732 /* Set to a reasonable value. Note that this will
2733 * be set to mac80211's value at ath5k_config(). */
2735 mutex_lock(&sc->lock);
2736 if (sc->vif != vif) {
2741 /* Cache for later use during resets */
2742 memcpy(ah->ah_bssid, conf->bssid, ETH_ALEN);
2743 /* XXX: assoc id is set to 0 for now, mac80211 doesn't have
2744 * a clean way of letting us retrieve this yet. */
2745 ath5k_hw_set_associd(ah, ah->ah_bssid, 0);
2749 if (conf->changed & IEEE80211_IFCC_BEACON &&
2750 vif->type == IEEE80211_IF_TYPE_IBSS) {
2751 struct sk_buff *beacon = ieee80211_beacon_get(hw, vif);
2756 /* call old handler for now */
2757 ath5k_beacon_update(hw, beacon);
2760 mutex_unlock(&sc->lock);
2762 return ath5k_reset_wake(sc);
2764 mutex_unlock(&sc->lock);
2768 #define SUPPORTED_FIF_FLAGS \
2769 FIF_PROMISC_IN_BSS | FIF_ALLMULTI | FIF_FCSFAIL | \
2770 FIF_PLCPFAIL | FIF_CONTROL | FIF_OTHER_BSS | \
2771 FIF_BCN_PRBRESP_PROMISC
2773 * o always accept unicast, broadcast, and multicast traffic
2774 * o multicast traffic for all BSSIDs will be enabled if mac80211
2776 * o maintain current state of phy ofdm or phy cck error reception.
2777 * If the hardware detects any of these type of errors then
2778 * ath5k_hw_get_rx_filter() will pass to us the respective
2779 * hardware filters to be able to receive these type of frames.
2780 * o probe request frames are accepted only when operating in
2781 * hostap, adhoc, or monitor modes
2782 * o enable promiscuous mode according to the interface state
2784 * - when operating in adhoc mode so the 802.11 layer creates
2785 * node table entries for peers,
2786 * - when operating in station mode for collecting rssi data when
2787 * the station is otherwise quiet, or
2790 static void ath5k_configure_filter(struct ieee80211_hw *hw,
2791 unsigned int changed_flags,
2792 unsigned int *new_flags,
2793 int mc_count, struct dev_mc_list *mclist)
2795 struct ath5k_softc *sc = hw->priv;
2796 struct ath5k_hw *ah = sc->ah;
2797 u32 mfilt[2], val, rfilt;
2804 /* Only deal with supported flags */
2805 changed_flags &= SUPPORTED_FIF_FLAGS;
2806 *new_flags &= SUPPORTED_FIF_FLAGS;
2808 /* If HW detects any phy or radar errors, leave those filters on.
2809 * Also, always enable Unicast, Broadcasts and Multicast
2810 * XXX: move unicast, bssid broadcasts and multicast to mac80211 */
2811 rfilt = (ath5k_hw_get_rx_filter(ah) & (AR5K_RX_FILTER_PHYERR)) |
2812 (AR5K_RX_FILTER_UCAST | AR5K_RX_FILTER_BCAST |
2813 AR5K_RX_FILTER_MCAST);
2815 if (changed_flags & (FIF_PROMISC_IN_BSS | FIF_OTHER_BSS)) {
2816 if (*new_flags & FIF_PROMISC_IN_BSS) {
2817 rfilt |= AR5K_RX_FILTER_PROM;
2818 __set_bit(ATH_STAT_PROMISC, sc->status);
2821 __clear_bit(ATH_STAT_PROMISC, sc->status);
2824 /* Note, AR5K_RX_FILTER_MCAST is already enabled */
2825 if (*new_flags & FIF_ALLMULTI) {
2829 for (i = 0; i < mc_count; i++) {
2832 /* calculate XOR of eight 6-bit values */
2833 val = get_unaligned_le32(mclist->dmi_addr + 0);
2834 pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
2835 val = get_unaligned_le32(mclist->dmi_addr + 3);
2836 pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
2838 mfilt[pos / 32] |= (1 << (pos % 32));
2839 /* XXX: we might be able to just do this instead,
2840 * but not sure, needs testing, if we do use this we'd
2841 * neet to inform below to not reset the mcast */
2842 /* ath5k_hw_set_mcast_filterindex(ah,
2843 * mclist->dmi_addr[5]); */
2844 mclist = mclist->next;
2848 /* This is the best we can do */
2849 if (*new_flags & (FIF_FCSFAIL | FIF_PLCPFAIL))
2850 rfilt |= AR5K_RX_FILTER_PHYERR;
2852 /* FIF_BCN_PRBRESP_PROMISC really means to enable beacons
2853 * and probes for any BSSID, this needs testing */
2854 if (*new_flags & FIF_BCN_PRBRESP_PROMISC)
2855 rfilt |= AR5K_RX_FILTER_BEACON | AR5K_RX_FILTER_PROBEREQ;
2857 /* FIF_CONTROL doc says that if FIF_PROMISC_IN_BSS is not
2858 * set we should only pass on control frames for this
2859 * station. This needs testing. I believe right now this
2860 * enables *all* control frames, which is OK.. but
2861 * but we should see if we can improve on granularity */
2862 if (*new_flags & FIF_CONTROL)
2863 rfilt |= AR5K_RX_FILTER_CONTROL;
2865 /* Additional settings per mode -- this is per ath5k */
2867 /* XXX move these to mac80211, and add a beacon IFF flag to mac80211 */
2869 if (sc->opmode == IEEE80211_IF_TYPE_MNTR)
2870 rfilt |= AR5K_RX_FILTER_CONTROL | AR5K_RX_FILTER_BEACON |
2871 AR5K_RX_FILTER_PROBEREQ | AR5K_RX_FILTER_PROM;
2872 if (sc->opmode != IEEE80211_IF_TYPE_STA)
2873 rfilt |= AR5K_RX_FILTER_PROBEREQ;
2874 if (sc->opmode != IEEE80211_IF_TYPE_AP &&
2875 sc->opmode != IEEE80211_IF_TYPE_MESH_POINT &&
2876 test_bit(ATH_STAT_PROMISC, sc->status))
2877 rfilt |= AR5K_RX_FILTER_PROM;
2878 if (sc->opmode == IEEE80211_IF_TYPE_STA ||
2879 sc->opmode == IEEE80211_IF_TYPE_IBSS) {
2880 rfilt |= AR5K_RX_FILTER_BEACON;
2884 ath5k_hw_set_rx_filter(ah,rfilt);
2886 /* Set multicast bits */
2887 ath5k_hw_set_mcast_filter(ah, mfilt[0], mfilt[1]);
2888 /* Set the cached hw filter flags, this will alter actually
2890 sc->filter_flags = rfilt;
2894 ath5k_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
2895 const u8 *local_addr, const u8 *addr,
2896 struct ieee80211_key_conf *key)
2898 struct ath5k_softc *sc = hw->priv;
2903 /* XXX: fix hardware encryption, its not working. For now
2904 * allow software encryption */
2914 mutex_lock(&sc->lock);
2918 ret = ath5k_hw_set_key(sc->ah, key->keyidx, key, addr);
2920 ATH5K_ERR(sc, "can't set the key\n");
2923 __set_bit(key->keyidx, sc->keymap);
2924 key->hw_key_idx = key->keyidx;
2927 ath5k_hw_reset_key(sc->ah, key->keyidx);
2928 __clear_bit(key->keyidx, sc->keymap);
2937 mutex_unlock(&sc->lock);
2942 ath5k_get_stats(struct ieee80211_hw *hw,
2943 struct ieee80211_low_level_stats *stats)
2945 struct ath5k_softc *sc = hw->priv;
2946 struct ath5k_hw *ah = sc->ah;
2949 ath5k_hw_update_mib_counters(ah, &sc->ll_stats);
2951 memcpy(stats, &sc->ll_stats, sizeof(sc->ll_stats));
2957 ath5k_get_tx_stats(struct ieee80211_hw *hw,
2958 struct ieee80211_tx_queue_stats *stats)
2960 struct ath5k_softc *sc = hw->priv;
2962 memcpy(stats, &sc->tx_stats, sizeof(sc->tx_stats));
2968 ath5k_get_tsf(struct ieee80211_hw *hw)
2970 struct ath5k_softc *sc = hw->priv;
2972 return ath5k_hw_get_tsf64(sc->ah);
2976 ath5k_reset_tsf(struct ieee80211_hw *hw)
2978 struct ath5k_softc *sc = hw->priv;
2981 * in IBSS mode we need to update the beacon timers too.
2982 * this will also reset the TSF if we call it with 0
2984 if (sc->opmode == IEEE80211_IF_TYPE_IBSS)
2985 ath5k_beacon_update_timers(sc, 0);
2987 ath5k_hw_reset_tsf(sc->ah);
2991 ath5k_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb)
2993 struct ath5k_softc *sc = hw->priv;
2996 ath5k_debug_dump_skb(sc, skb, "BC ", 1);
2998 if (sc->opmode != IEEE80211_IF_TYPE_IBSS) {
3003 ath5k_txbuf_free(sc, sc->bbuf);
3004 sc->bbuf->skb = skb;
3005 ret = ath5k_beacon_setup(sc, sc->bbuf);
3007 sc->bbuf->skb = NULL;
3009 ath5k_beacon_config(sc);