drivers/net/wireless/ath5k/phy.c

   1 /*
   2  * PHY functions
   3  *
   4  * Copyright (c) 2004, 2005, 2006, 2007 Reyk Floeter <reyk@openbsd.org>
   5  * Copyright (c) 2006, 2007 Nick Kossifidis <mickflemm@gmail.com>
   6  * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com>
   7  *
   8  * Permission to use, copy, modify, and distribute this software for any
   9  * purpose with or without fee is hereby granted, provided that the above
  10  * copyright notice and this permission notice appear in all copies.
  11  *
  12  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  13  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  14  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  15  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  16  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  17  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  18  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  19  *
  20  */
  21
  22 #include <linux/delay.h>
  23
  24 #include "ath5k.h"
  25 #include "reg.h"
  26 #include "base.h"
  27
  28 /* Struct to hold initial RF register values (RF Banks) */
  29 struct ath5k_ini_rf {
  30         u8      rf_bank;        /* check out ath5k_reg.h */
  31         u16     rf_register;    /* register address */
  32         u32     rf_value[5];    /* register value for different modes (above) */
  33 };
  34
  35 /*
  36  * Mode-specific RF Gain table (64bytes) for RF5111/5112
  37  * (RF5110 only comes with AR5210 and only supports a/turbo a mode so initial
  38  * RF Gain values are included in AR5K_AR5210_INI)
  39  */
  40 struct ath5k_ini_rfgain {
  41         u16     rfg_register;   /* RF Gain register address */
  42         u32     rfg_value[2];   /* [freq (see below)] */
  43 };
  44
  45 struct ath5k_gain_opt {
  46         u32                     go_default;
  47         u32                     go_steps_count;
  48         const struct ath5k_gain_opt_step        go_step[AR5K_GAIN_STEP_COUNT];
  49 };
  50
  51 /* RF5111 mode-specific init registers */
  52 static const struct ath5k_ini_rf rfregs_5111[] = {
  53         { 0, 0x989c,
  54         /*    mode a/XR   mode aTurbo mode b      mode g      mode gTurbo */
  55             { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
  56         { 0, 0x989c,
  57             { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
  58         { 0, 0x989c,
  59             { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
  60         { 0, 0x989c,
  61             { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
  62         { 0, 0x989c,
  63             { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
  64         { 0, 0x989c,
  65             { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
  66         { 0, 0x989c,
  67             { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
  68         { 0, 0x989c,
  69             { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
  70         { 0, 0x989c,
  71             { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
  72         { 0, 0x989c,
  73             { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
  74         { 0, 0x989c,
  75             { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
  76         { 0, 0x989c,
  77             { 0x00380000, 0x00380000, 0x00380000, 0x00380000, 0x00380000 } },
  78         { 0, 0x989c,
  79             { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
  80         { 0, 0x989c,
  81             { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
  82         { 0, 0x989c,
  83             { 0x00000000, 0x00000000, 0x000000c0, 0x00000080, 0x00000080 } },
  84         { 0, 0x989c,
  85             { 0x000400f9, 0x000400f9, 0x000400ff, 0x000400fd, 0x000400fd } },
  86         { 0, 0x98d4,
  87             { 0x00000000, 0x00000000, 0x00000004, 0x00000004, 0x00000004 } },
  88         { 1, 0x98d4,
  89             { 0x00000020, 0x00000020, 0x00000020, 0x00000020, 0x00000020 } },
  90         { 2, 0x98d4,
  91             { 0x00000010, 0x00000014, 0x00000010, 0x00000010, 0x00000014 } },
  92         { 3, 0x98d8,
  93             { 0x00601068, 0x00601068, 0x00601068, 0x00601068, 0x00601068 } },
  94         { 6, 0x989c,
  95             { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
  96         { 6, 0x989c,
  97             { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
  98         { 6, 0x989c,
  99             { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
 100         { 6, 0x989c,
 101             { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
 102         { 6, 0x989c,
 103             { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
 104         { 6, 0x989c,
 105             { 0x10000000, 0x10000000, 0x10000000, 0x10000000, 0x10000000 } },
 106         { 6, 0x989c,
 107             { 0x04000000, 0x04000000, 0x04000000, 0x04000000, 0x04000000 } },
 108         { 6, 0x989c,
 109             { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
 110         { 6, 0x989c,
 111             { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
 112         { 6, 0x989c,
 113             { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
 114         { 6, 0x989c,
 115             { 0x00000000, 0x00000000, 0x0a000000, 0x00000000, 0x00000000 } },
 116         { 6, 0x989c,
 117             { 0x003800c0, 0x00380080, 0x023800c0, 0x003800c0, 0x003800c0 } },
 118         { 6, 0x989c,
 119             { 0x00020006, 0x00020006, 0x00000006, 0x00020006, 0x00020006 } },
 120         { 6, 0x989c,
 121             { 0x00000089, 0x00000089, 0x00000089, 0x00000089, 0x00000089 } },
 122         { 6, 0x989c,
 123             { 0x000000a0, 0x000000a0, 0x000000a0, 0x000000a0, 0x000000a0 } },
 124         { 6, 0x989c,
 125             { 0x00040007, 0x00040007, 0x00040007, 0x00040007, 0x00040007 } },
 126         { 6, 0x98d4,
 127             { 0x0000001a, 0x0000001a, 0x0000001a, 0x0000001a, 0x0000001a } },
 128         { 7, 0x989c,
 129             { 0x00000040, 0x00000048, 0x00000040, 0x00000040, 0x00000040 } },
 130         { 7, 0x989c,
 131             { 0x00000010, 0x00000010, 0x00000010, 0x00000010, 0x00000010 } },
 132         { 7, 0x989c,
 133             { 0x00000008, 0x00000008, 0x00000008, 0x00000008, 0x00000008 } },
 134         { 7, 0x989c,
 135             { 0x0000004f, 0x0000004f, 0x0000004f, 0x0000004f, 0x0000004f } },
 136         { 7, 0x989c,
 137             { 0x000000f1, 0x000000f1, 0x00000061, 0x000000f1, 0x000000f1 } },
 138         { 7, 0x989c,
 139             { 0x0000904f, 0x0000904f, 0x0000904c, 0x0000904f, 0x0000904f } },
 140         { 7, 0x989c,
 141             { 0x0000125a, 0x0000125a, 0x0000129a, 0x0000125a, 0x0000125a } },
 142         { 7, 0x98cc,
 143             { 0x0000000e, 0x0000000e, 0x0000000f, 0x0000000e, 0x0000000e } },
 144 };
 145
 146 /* Initial RF Gain settings for RF5111 */
 147 static const struct ath5k_ini_rfgain rfgain_5111[] = {
 148         /*                            5Ghz      2Ghz    */
 149         { AR5K_RF_GAIN(0),      { 0x000001a9, 0x00000000 } },
 150         { AR5K_RF_GAIN(1),      { 0x000001e9, 0x00000040 } },
 151         { AR5K_RF_GAIN(2),      { 0x00000029, 0x00000080 } },
 152         { AR5K_RF_GAIN(3),      { 0x00000069, 0x00000150 } },
 153         { AR5K_RF_GAIN(4),      { 0x00000199, 0x00000190 } },
 154         { AR5K_RF_GAIN(5),      { 0x000001d9, 0x000001d0 } },
 155         { AR5K_RF_GAIN(6),      { 0x00000019, 0x00000010 } },
 156         { AR5K_RF_GAIN(7),      { 0x00000059, 0x00000044 } },
 157         { AR5K_RF_GAIN(8),      { 0x00000099, 0x00000084 } },
 158         { AR5K_RF_GAIN(9),      { 0x000001a5, 0x00000148 } },
 159         { AR5K_RF_GAIN(10),     { 0x000001e5, 0x00000188 } },
 160         { AR5K_RF_GAIN(11),     { 0x00000025, 0x000001c8 } },
 161         { AR5K_RF_GAIN(12),     { 0x000001c8, 0x00000014 } },
 162         { AR5K_RF_GAIN(13),     { 0x00000008, 0x00000042 } },
 163         { AR5K_RF_GAIN(14),     { 0x00000048, 0x00000082 } },
 164         { AR5K_RF_GAIN(15),     { 0x00000088, 0x00000178 } },
 165         { AR5K_RF_GAIN(16),     { 0x00000198, 0x000001b8 } },
 166         { AR5K_RF_GAIN(17),     { 0x000001d8, 0x000001f8 } },
 167         { AR5K_RF_GAIN(18),     { 0x00000018, 0x00000012 } },
 168         { AR5K_RF_GAIN(19),     { 0x00000058, 0x00000052 } },
 169         { AR5K_RF_GAIN(20),     { 0x00000098, 0x00000092 } },
 170         { AR5K_RF_GAIN(21),     { 0x000001a4, 0x0000017c } },
 171         { AR5K_RF_GAIN(22),     { 0x000001e4, 0x000001bc } },
 172         { AR5K_RF_GAIN(23),     { 0x00000024, 0x000001fc } },
 173         { AR5K_RF_GAIN(24),     { 0x00000064, 0x0000000a } },
 174         { AR5K_RF_GAIN(25),     { 0x000000a4, 0x0000004a } },
 175         { AR5K_RF_GAIN(26),     { 0x000000e4, 0x0000008a } },
 176         { AR5K_RF_GAIN(27),     { 0x0000010a, 0x0000015a } },
 177         { AR5K_RF_GAIN(28),     { 0x0000014a, 0x0000019a } },
 178         { AR5K_RF_GAIN(29),     { 0x0000018a, 0x000001da } },
 179         { AR5K_RF_GAIN(30),     { 0x000001ca, 0x0000000e } },
 180         { AR5K_RF_GAIN(31),     { 0x0000000a, 0x0000004e } },
 181         { AR5K_RF_GAIN(32),     { 0x0000004a, 0x0000008e } },
 182         { AR5K_RF_GAIN(33),     { 0x0000008a, 0x0000015e } },
 183         { AR5K_RF_GAIN(34),     { 0x000001ba, 0x0000019e } },
 184         { AR5K_RF_GAIN(35),     { 0x000001fa, 0x000001de } },
 185         { AR5K_RF_GAIN(36),     { 0x0000003a, 0x00000009 } },
 186         { AR5K_RF_GAIN(37),     { 0x0000007a, 0x00000049 } },
 187         { AR5K_RF_GAIN(38),     { 0x00000186, 0x00000089 } },
 188         { AR5K_RF_GAIN(39),     { 0x000001c6, 0x00000179 } },
 189         { AR5K_RF_GAIN(40),     { 0x00000006, 0x000001b9 } },
 190         { AR5K_RF_GAIN(41),     { 0x00000046, 0x000001f9 } },
 191         { AR5K_RF_GAIN(42),     { 0x00000086, 0x00000039 } },
 192         { AR5K_RF_GAIN(43),     { 0x000000c6, 0x00000079 } },
 193         { AR5K_RF_GAIN(44),     { 0x000000c6, 0x000000b9 } },
 194         { AR5K_RF_GAIN(45),     { 0x000000c6, 0x000001bd } },
 195         { AR5K_RF_GAIN(46),     { 0x000000c6, 0x000001fd } },
 196         { AR5K_RF_GAIN(47),     { 0x000000c6, 0x0000003d } },
 197         { AR5K_RF_GAIN(48),     { 0x000000c6, 0x0000007d } },
 198         { AR5K_RF_GAIN(49),     { 0x000000c6, 0x000000bd } },
 199         { AR5K_RF_GAIN(50),     { 0x000000c6, 0x000000fd } },
 200         { AR5K_RF_GAIN(51),     { 0x000000c6, 0x000000fd } },
 201         { AR5K_RF_GAIN(52),     { 0x000000c6, 0x000000fd } },
 202         { AR5K_RF_GAIN(53),     { 0x000000c6, 0x000000fd } },
 203         { AR5K_RF_GAIN(54),     { 0x000000c6, 0x000000fd } },
 204         { AR5K_RF_GAIN(55),     { 0x000000c6, 0x000000fd } },
 205         { AR5K_RF_GAIN(56),     { 0x000000c6, 0x000000fd } },
 206         { AR5K_RF_GAIN(57),     { 0x000000c6, 0x000000fd } },
 207         { AR5K_RF_GAIN(58),     { 0x000000c6, 0x000000fd } },
 208         { AR5K_RF_GAIN(59),     { 0x000000c6, 0x000000fd } },
 209         { AR5K_RF_GAIN(60),     { 0x000000c6, 0x000000fd } },
 210         { AR5K_RF_GAIN(61),     { 0x000000c6, 0x000000fd } },
 211         { AR5K_RF_GAIN(62),     { 0x000000c6, 0x000000fd } },
 212         { AR5K_RF_GAIN(63),     { 0x000000c6, 0x000000fd } },
 213 };
 214
 215 static const struct ath5k_gain_opt rfgain_opt_5111 = {
 216         4,
 217         9,
 218         {
 219                 { { 4, 1, 1, 1 }, 6 },
 220                 { { 4, 0, 1, 1 }, 4 },
 221                 { { 3, 1, 1, 1 }, 3 },
 222                 { { 4, 0, 0, 1 }, 1 },
 223                 { { 4, 1, 1, 0 }, 0 },
 224                 { { 4, 0, 1, 0 }, -2 },
 225                 { { 3, 1, 1, 0 }, -3 },
 226                 { { 4, 0, 0, 0 }, -4 },
 227                 { { 2, 1, 1, 0 }, -6 }
 228         }
 229 };
 230
 231 /* RF5112 mode-specific init registers */
 232 static const struct ath5k_ini_rf rfregs_5112[] = {
 233         { 1, 0x98d4,
 234         /*    mode a/XR   mode aTurbo mode b      mode g      mode gTurbo */
 235             { 0x00000020, 0x00000020, 0x00000020, 0x00000020, 0x00000020 } },
 236         { 2, 0x98d0,
 237             { 0x03060408, 0x03070408, 0x03060408, 0x03060408, 0x03070408 } },
 238         { 3, 0x98dc,
 239             { 0x00a0c0c0, 0x00a0c0c0, 0x00e0c0c0, 0x00e0c0c0, 0x00e0c0c0 } },
 240         { 6, 0x989c,
 241             { 0x00a00000, 0x00a00000, 0x00a00000, 0x00a00000, 0x00a00000 } },
 242         { 6, 0x989c,
 243             { 0x000a0000, 0x000a0000, 0x000a0000, 0x000a0000, 0x000a0000 } },
 244         { 6, 0x989c,
 245             { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
 246         { 6, 0x989c,
 247             { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
 248         { 6, 0x989c,
 249             { 0x00660000, 0x00660000, 0x00660000, 0x00660000, 0x00660000 } },
 250         { 6, 0x989c,
 251             { 0x00db0000, 0x00db0000, 0x00db0000, 0x00db0000, 0x00db0000 } },
 252         { 6, 0x989c,
 253             { 0x00f10000, 0x00f10000, 0x00f10000, 0x00f10000, 0x00f10000 } },
 254         { 6, 0x989c,
 255             { 0x00120000, 0x00120000, 0x00120000, 0x00120000, 0x00120000 } },
 256         { 6, 0x989c,
 257             { 0x00120000, 0x00120000, 0x00120000, 0x00120000, 0x00120000 } },
 258         { 6, 0x989c,
 259             { 0x00730000, 0x00730000, 0x00730000, 0x00730000, 0x00730000 } },
 260         { 6, 0x989c,
 261             { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
 262         { 6, 0x989c,
 263             { 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000 } },
 264         { 6, 0x989c,
 265             { 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000 } },
 266         { 6, 0x989c,
 267             { 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000 } },
 268         { 6, 0x989c,
 269             { 0x008b0000, 0x008b0000, 0x008b0000, 0x008b0000, 0x008b0000 } },
 270         { 6, 0x989c,
 271             { 0x00600000, 0x00600000, 0x00600000, 0x00600000, 0x00600000 } },
 272         { 6, 0x989c,
 273             { 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000 } },
 274         { 6, 0x989c,
 275             { 0x00840000, 0x00840000, 0x00840000, 0x00840000, 0x00840000 } },
 276         { 6, 0x989c,
 277             { 0x00640000, 0x00640000, 0x00640000, 0x00640000, 0x00640000 } },
 278         { 6, 0x989c,
 279             { 0x00200000, 0x00200000, 0x00200000, 0x00200000, 0x00200000 } },
 280         { 6, 0x989c,
 281             { 0x00240000, 0x00240000, 0x00240000, 0x00240000, 0x00240000 } },
 282         { 6, 0x989c,
 283             { 0x00250000, 0x00250000, 0x00250000, 0x00250000, 0x00250000 } },
 284         { 6, 0x989c,
 285             { 0x00110000, 0x00110000, 0x00110000, 0x00110000, 0x00110000 } },
 286         { 6, 0x989c,
 287             { 0x00110000, 0x00110000, 0x00110000, 0x00110000, 0x00110000 } },
 288         { 6, 0x989c,
 289             { 0x00510000, 0x00510000, 0x00510000, 0x00510000, 0x00510000 } },
 290         { 6, 0x989c,
 291             { 0x1c040000, 0x1c040000, 0x1c040000, 0x1c040000, 0x1c040000 } },
 292         { 6, 0x989c,
 293             { 0x000a0000, 0x000a0000, 0x000a0000, 0x000a0000, 0x000a0000 } },
 294         { 6, 0x989c,
 295             { 0x00a10000, 0x00a10000, 0x00a10000, 0x00a10000, 0x00a10000 } },
 296         { 6, 0x989c,
 297             { 0x00400000, 0x00400000, 0x00400000, 0x00400000, 0x00400000 } },
 298         { 6, 0x989c,
 299             { 0x03090000, 0x03090000, 0x03090000, 0x03090000, 0x03090000 } },
 300         { 6, 0x989c,
 301             { 0x06000000, 0x06000000, 0x06000000, 0x06000000, 0x06000000 } },
 302         { 6, 0x989c,
 303             { 0x000000b0, 0x000000b0, 0x000000a8, 0x000000a8, 0x000000a8 } },
 304         { 6, 0x989c,
 305             { 0x0000002e, 0x0000002e, 0x0000002e, 0x0000002e, 0x0000002e } },
 306         { 6, 0x989c,
 307             { 0x006c4a41, 0x006c4a41, 0x006c4af1, 0x006c4a61, 0x006c4a61 } },
 308         { 6, 0x989c,
 309             { 0x0050892a, 0x0050892a, 0x0050892b, 0x0050892b, 0x0050892b } },
 310         { 6, 0x989c,
 311             { 0x00842400, 0x00842400, 0x00842400, 0x00842400, 0x00842400 } },
 312         { 6, 0x989c,
 313             { 0x00c69200, 0x00c69200, 0x00c69200, 0x00c69200, 0x00c69200 } },
 314         { 6, 0x98d0,
 315             { 0x0002000c, 0x0002000c, 0x0002000c, 0x0002000c, 0x0002000c } },
 316         { 7, 0x989c,
 317             { 0x00000094, 0x00000094, 0x00000094, 0x00000094, 0x00000094 } },
 318         { 7, 0x989c,
 319             { 0x00000091, 0x00000091, 0x00000091, 0x00000091, 0x00000091 } },
 320         { 7, 0x989c,
 321             { 0x0000000a, 0x0000000a, 0x00000012, 0x00000012, 0x00000012 } },
 322         { 7, 0x989c,
 323             { 0x00000080, 0x00000080, 0x00000080, 0x00000080, 0x00000080 } },
 324         { 7, 0x989c,
 325             { 0x000000c1, 0x000000c1, 0x000000c1, 0x000000c1, 0x000000c1 } },
 326         { 7, 0x989c,
 327             { 0x00000060, 0x00000060, 0x00000060, 0x00000060, 0x00000060 } },
 328         { 7, 0x989c,
 329             { 0x000000f0, 0x000000f0, 0x000000f0, 0x000000f0, 0x000000f0 } },
 330         { 7, 0x989c,
 331             { 0x00000022, 0x00000022, 0x00000022, 0x00000022, 0x00000022 } },
 332         { 7, 0x989c,
 333             { 0x00000092, 0x00000092, 0x00000092, 0x00000092, 0x00000092 } },
 334         { 7, 0x989c,
 335             { 0x000000d4, 0x000000d4, 0x000000d4, 0x000000d4, 0x000000d4 } },
 336         { 7, 0x989c,
 337             { 0x000014cc, 0x000014cc, 0x000014cc, 0x000014cc, 0x000014cc } },
 338         { 7, 0x989c,
 339             { 0x0000048c, 0x0000048c, 0x0000048c, 0x0000048c, 0x0000048c } },
 340         { 7, 0x98c4,
 341             { 0x00000003, 0x00000003, 0x00000003, 0x00000003, 0x00000003 } },
 342 };
 343
 344 /* RF5112A mode-specific init registers */
 345 static const struct ath5k_ini_rf rfregs_5112a[] = {
 346         { 1, 0x98d4,
 347         /*    mode a/XR   mode aTurbo mode b      mode g      mode gTurbo */
 348             { 0x00000020, 0x00000020, 0x00000020, 0x00000020, 0x00000020 } },
 349         { 2, 0x98d0,
 350             { 0x03060408, 0x03070408, 0x03060408, 0x03060408, 0x03070408 } },
 351         { 3, 0x98dc,
 352             { 0x00a0c0c0, 0x00a0c0c0, 0x00e0c0c0, 0x00e0c0c0, 0x00e0c0c0 } },
 353         { 6, 0x989c,
 354             { 0x0f000000, 0x0f000000, 0x0f000000, 0x0f000000, 0x0f000000 } },
 355         { 6, 0x989c,
 356             { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
 357         { 6, 0x989c,
 358             { 0x00800000, 0x00800000, 0x00800000, 0x00800000, 0x00800000 } },
 359         { 6, 0x989c,
 360             { 0x002a0000, 0x002a0000, 0x002a0000, 0x002a0000, 0x002a0000 } },
 361         { 6, 0x989c,
 362             { 0x00010000, 0x00010000, 0x00010000, 0x00010000, 0x00010000 } },
 363         { 6, 0x989c,
 364             { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
 365         { 6, 0x989c,
 366             { 0x00180000, 0x00180000, 0x00180000, 0x00180000, 0x00180000 } },
 367         { 6, 0x989c,
 368             { 0x00600000, 0x00600000, 0x006e0000, 0x006e0000, 0x006e0000 } },
 369         { 6, 0x989c,
 370             { 0x00c70000, 0x00c70000, 0x00c70000, 0x00c70000, 0x00c70000 } },
 371         { 6, 0x989c,
 372             { 0x004b0000, 0x004b0000, 0x004b0000, 0x004b0000, 0x004b0000 } },
 373         { 6, 0x989c,
 374             { 0x04480000, 0x04480000, 0x04480000, 0x04480000, 0x04480000 } },
 375         { 6, 0x989c,
 376             { 0x00220000, 0x00220000, 0x00220000, 0x00220000, 0x00220000 } },
 377         { 6, 0x989c,
 378             { 0x00e40000, 0x00e40000, 0x00e40000, 0x00e40000, 0x00e40000 } },
 379         { 6, 0x989c,
 380             { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
 381         { 6, 0x989c,
 382             { 0x00fc0000, 0x00fc0000, 0x00fc0000, 0x00fc0000, 0x00fc0000 } },
 383         { 6, 0x989c,
 384             { 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000 } },
 385         { 6, 0x989c,
 386             { 0x043f0000, 0x043f0000, 0x043f0000, 0x043f0000, 0x043f0000 } },
 387         { 6, 0x989c,
 388             { 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000 } },
 389         { 6, 0x989c,
 390             { 0x00190000, 0x00190000, 0x00190000, 0x00190000, 0x00190000 } },
 391         { 6, 0x989c,
 392             { 0x00240000, 0x00240000, 0x00240000, 0x00240000, 0x00240000 } },
 393         { 6, 0x989c,
 394             { 0x00b40000, 0x00b40000, 0x00b40000, 0x00b40000, 0x00b40000 } },
 395         { 6, 0x989c,
 396             { 0x00990000, 0x00990000, 0x00990000, 0x00990000, 0x00990000 } },
 397         { 6, 0x989c,
 398             { 0x00500000, 0x00500000, 0x00500000, 0x00500000, 0x00500000 } },
 399         { 6, 0x989c,
 400             { 0x002a0000, 0x002a0000, 0x002a0000, 0x002a0000, 0x002a0000 } },
 401         { 6, 0x989c,
 402             { 0x00120000, 0x00120000, 0x00120000, 0x00120000, 0x00120000 } },
 403         { 6, 0x989c,
 404             { 0xc0320000, 0xc0320000, 0xc0320000, 0xc0320000, 0xc0320000 } },
 405         { 6, 0x989c,
 406             { 0x01740000, 0x01740000, 0x01740000, 0x01740000, 0x01740000 } },
 407         { 6, 0x989c,
 408             { 0x00110000, 0x00110000, 0x00110000, 0x00110000, 0x00110000 } },
 409         { 6, 0x989c,
 410             { 0x86280000, 0x86280000, 0x86280000, 0x86280000, 0x86280000 } },
 411         { 6, 0x989c,
 412             { 0x31840000, 0x31840000, 0x31840000, 0x31840000, 0x31840000 } },
 413         { 6, 0x989c,
 414             { 0x00020080, 0x00020080, 0x00020080, 0x00020080, 0x00020080 } },
 415         { 6, 0x989c,
 416             { 0x00080009, 0x00080009, 0x00080009, 0x00080009, 0x00080009 } },
 417         { 6, 0x989c,
 418             { 0x00000003, 0x00000003, 0x00000003, 0x00000003, 0x00000003 } },
 419         { 6, 0x989c,
 420             { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
 421         { 6, 0x989c,
 422             { 0x000000b2, 0x000000b2, 0x000000b2, 0x000000b2, 0x000000b2 } },
 423         { 6, 0x989c,
 424             { 0x00b02084, 0x00b02084, 0x00b02084, 0x00b02084, 0x00b02084 } },
 425         { 6, 0x989c,
 426             { 0x004125a4, 0x004125a4, 0x004125a4, 0x004125a4, 0x004125a4 } },
 427         { 6, 0x989c,
 428             { 0x00119220, 0x00119220, 0x00119220, 0x00119220, 0x00119220 } },
 429         { 6, 0x989c,
 430             { 0x001a4800, 0x001a4800, 0x001a4800, 0x001a4800, 0x001a4800 } },
 431         { 6, 0x98d8,
 432             { 0x000b0230, 0x000b0230, 0x000b0230, 0x000b0230, 0x000b0230 } },
 433         { 7, 0x989c,
 434             { 0x00000094, 0x00000094, 0x00000094, 0x00000094, 0x00000094 } },
 435         { 7, 0x989c,
 436             { 0x00000091, 0x00000091, 0x00000091, 0x00000091, 0x00000091 } },
 437         { 7, 0x989c,
 438             { 0x00000012, 0x00000012, 0x00000012, 0x00000012, 0x00000012 } },
 439         { 7, 0x989c,
 440             { 0x00000080, 0x00000080, 0x00000080, 0x00000080, 0x00000080 } },
 441         { 7, 0x989c,
 442             { 0x000000d9, 0x000000d9, 0x000000d9, 0x000000d9, 0x000000d9 } },
 443         { 7, 0x989c,
 444             { 0x00000060, 0x00000060, 0x00000060, 0x00000060, 0x00000060 } },
 445         { 7, 0x989c,
 446             { 0x000000f0, 0x000000f0, 0x000000f0, 0x000000f0, 0x000000f0 } },
 447         { 7, 0x989c,
 448             { 0x000000a2, 0x000000a2, 0x000000a2, 0x000000a2, 0x000000a2 } },
 449         { 7, 0x989c,
 450             { 0x00000052, 0x00000052, 0x00000052, 0x00000052, 0x00000052 } },
 451         { 7, 0x989c,
 452             { 0x000000d4, 0x000000d4, 0x000000d4, 0x000000d4, 0x000000d4 } },
 453         { 7, 0x989c,
 454             { 0x000014cc, 0x000014cc, 0x000014cc, 0x000014cc, 0x000014cc } },
 455         { 7, 0x989c,
 456             { 0x0000048c, 0x0000048c, 0x0000048c, 0x0000048c, 0x0000048c } },
 457         { 7, 0x98c4,
 458             { 0x00000003, 0x00000003, 0x00000003, 0x00000003, 0x00000003 } },
 459 };
 460
 461
 462 static const struct ath5k_ini_rf rfregs_2112a[] = {
 463         { 1, AR5K_RF_BUFFER_CONTROL_4,
 464         /*         mode b       mode g    mode gTurbo */
 465                 { 0x00000020, 0x00000020, 0x00000020 } },
 466         { 2, AR5K_RF_BUFFER_CONTROL_3,
 467                 { 0x03060408, 0x03060408, 0x03070408 } },
 468         { 3, AR5K_RF_BUFFER_CONTROL_6,
 469                 { 0x00e020c0, 0x00e020c0, 0x00e020c0 } },
 470         { 6, AR5K_RF_BUFFER,
 471                 { 0x0a000000, 0x0a000000, 0x0a000000 } },
 472         { 6, AR5K_RF_BUFFER,
 473                 { 0x00000000, 0x00000000, 0x00000000 } },
 474         { 6, AR5K_RF_BUFFER,
 475                 { 0x00800000, 0x00800000, 0x00800000 } },
 476         { 6, AR5K_RF_BUFFER,
 477                 { 0x002a0000, 0x002a0000, 0x002a0000 } },
 478         { 6, AR5K_RF_BUFFER,
 479                 { 0x00010000, 0x00010000, 0x00010000 } },
 480         { 6, AR5K_RF_BUFFER,
 481                 { 0x00000000, 0x00000000, 0x00000000 } },
 482         { 6, AR5K_RF_BUFFER,
 483                 { 0x00180000, 0x00180000, 0x00180000 } },
 484         { 6, AR5K_RF_BUFFER,
 485                 { 0x006e0000, 0x006e0000, 0x006e0000 } },
 486         { 6, AR5K_RF_BUFFER,
 487                 { 0x00c70000, 0x00c70000, 0x00c70000 } },
 488         { 6, AR5K_RF_BUFFER,
 489                 { 0x004b0000, 0x004b0000, 0x004b0000 } },
 490         { 6, AR5K_RF_BUFFER,
 491                 { 0x04480000, 0x04480000, 0x04480000 } },
 492         { 6, AR5K_RF_BUFFER,
 493                 { 0x002a0000, 0x002a0000, 0x002a0000 } },
 494         { 6, AR5K_RF_BUFFER,
 495                 { 0x00e40000, 0x00e40000, 0x00e40000 } },
 496         { 6, AR5K_RF_BUFFER,
 497                 { 0x00000000, 0x00000000, 0x00000000 } },
 498         { 6, AR5K_RF_BUFFER,
 499                 { 0x00fc0000, 0x00fc0000, 0x00fc0000 } },
 500         { 6, AR5K_RF_BUFFER,
 501                 { 0x00ff0000, 0x00ff0000, 0x00ff0000 } },
 502         { 6, AR5K_RF_BUFFER,
 503                 { 0x043f0000, 0x043f0000, 0x043f0000 } },
 504         { 6, AR5K_RF_BUFFER,
 505                 { 0x0c0c0000, 0x0c0c0000, 0x0c0c0000 } },
 506         { 6, AR5K_RF_BUFFER,
 507                 { 0x02190000, 0x02190000, 0x02190000 } },
 508         { 6, AR5K_RF_BUFFER,
 509                 { 0x00240000, 0x00240000, 0x00240000 } },
 510         { 6, AR5K_RF_BUFFER,
 511                 { 0x00b40000, 0x00b40000, 0x00b40000 } },
 512         { 6, AR5K_RF_BUFFER,
 513                 { 0x00990000, 0x00990000, 0x00990000 } },
 514         { 6, AR5K_RF_BUFFER,
 515                 { 0x00500000, 0x00500000, 0x00500000 } },
 516         { 6, AR5K_RF_BUFFER,
 517                 { 0x002a0000, 0x002a0000, 0x002a0000 } },
 518         { 6, AR5K_RF_BUFFER,
 519                 { 0x00120000, 0x00120000, 0x00120000 } },
 520         { 6, AR5K_RF_BUFFER,
 521                 { 0xc0320000, 0xc0320000, 0xc0320000 } },
 522         { 6, AR5K_RF_BUFFER,
 523                 { 0x01740000, 0x01740000, 0x01740000 } },
 524         { 6, AR5K_RF_BUFFER,
 525                 { 0x00110000, 0x00110000, 0x00110000 } },
 526         { 6, AR5K_RF_BUFFER,
 527                 { 0x86280000, 0x86280000, 0x86280000 } },
 528         { 6, AR5K_RF_BUFFER,
 529                 { 0x31840000, 0x31840000, 0x31840000 } },
 530         { 6, AR5K_RF_BUFFER,
 531                 { 0x00f20080, 0x00f20080, 0x00f20080 } },
 532         { 6, AR5K_RF_BUFFER,
 533                 { 0x00070019, 0x00070019, 0x00070019 } },
 534         { 6, AR5K_RF_BUFFER,
 535                 { 0x00000000, 0x00000000, 0x00000000 } },
 536         { 6, AR5K_RF_BUFFER,
 537                 { 0x00000000, 0x00000000, 0x00000000 } },
 538         { 6, AR5K_RF_BUFFER,
 539                 { 0x000000b2, 0x000000b2, 0x000000b2 } },
 540         { 6, AR5K_RF_BUFFER,
 541                 { 0x00b02184, 0x00b02184, 0x00b02184 } },
 542         { 6, AR5K_RF_BUFFER,
 543                 { 0x004125a4, 0x004125a4, 0x004125a4 } },
 544         { 6, AR5K_RF_BUFFER,
 545                 { 0x00119220, 0x00119220, 0x00119220 } },
 546         { 6, AR5K_RF_BUFFER,
 547                 { 0x001a4800, 0x001a4800, 0x001a4800 } },
 548         { 6, AR5K_RF_BUFFER_CONTROL_5,
 549                 { 0x000b0230, 0x000b0230, 0x000b0230 } },
 550         { 7, AR5K_RF_BUFFER,
 551                 { 0x00000094, 0x00000094, 0x00000094 } },
 552         { 7, AR5K_RF_BUFFER,
 553                 { 0x00000091, 0x00000091, 0x00000091 } },
 554         { 7, AR5K_RF_BUFFER,
 555                 { 0x00000012, 0x00000012, 0x00000012 } },
 556         { 7, AR5K_RF_BUFFER,
 557                 { 0x00000080, 0x00000080, 0x00000080 } },
 558         { 7, AR5K_RF_BUFFER,
 559                 { 0x000000d9, 0x000000d9, 0x000000d9 } },
 560         { 7, AR5K_RF_BUFFER,
 561                 { 0x00000060, 0x00000060, 0x00000060 } },
 562         { 7, AR5K_RF_BUFFER,
 563                 { 0x000000f0, 0x000000f0, 0x000000f0 } },
 564         { 7, AR5K_RF_BUFFER,
 565                 { 0x000000a2, 0x000000a2, 0x000000a2 } },
 566         { 7, AR5K_RF_BUFFER,
 567                 { 0x00000052, 0x00000052, 0x00000052 } },
 568         { 7, AR5K_RF_BUFFER,
 569                 { 0x000000d4, 0x000000d4, 0x000000d4 } },
 570         { 7, AR5K_RF_BUFFER,
 571                 { 0x000014cc, 0x000014cc, 0x000014cc } },
 572         { 7, AR5K_RF_BUFFER,
 573                 { 0x0000048c, 0x0000048c, 0x0000048c } },
 574         { 7, AR5K_RF_BUFFER_CONTROL_1,
 575                 { 0x00000003, 0x00000003, 0x00000003 } },
 576 };
 577
 578 /* RF5413/5414 mode-specific init registers */
 579 static const struct ath5k_ini_rf rfregs_5413[] = {
 580         { 1, 0x98d4,
 581         /*    mode a/XR   mode aTurbo mode b      mode g      mode gTurbo */
 582             { 0x00000020, 0x00000020, 0x00000020, 0x00000020, 0x00000020 } },
 583         { 2, 0x98d0,
 584             { 0x00000008, 0x00000008, 0x00000008, 0x00000008, 0x00000008 } },
 585         { 3, 0x98dc,
 586             { 0x00a000c0, 0x00a000c0, 0x00e000c0, 0x00e000c0, 0x00e000c0 } },
 587         { 6, 0x989c,
 588             { 0x33000000, 0x33000000, 0x33000000, 0x33000000, 0x33000000 } },
 589         { 6, 0x989c,
 590             { 0x01000000, 0x01000000, 0x01000000, 0x01000000, 0x01000000 } },
 591         { 6, 0x989c,
 592             { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
 593         { 6, 0x989c,
 594             { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
 595         { 6, 0x989c,
 596             { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
 597         { 6, 0x989c,
 598             { 0x1f000000, 0x1f000000, 0x1f000000, 0x1f000000, 0x1f000000 } },
 599         { 6, 0x989c,
 600             { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
 601         { 6, 0x989c,
 602             { 0x00b80000, 0x00b80000, 0x00b80000, 0x00b80000, 0x00b80000 } },
 603         { 6, 0x989c,
 604             { 0x00b70000, 0x00b70000, 0x00b70000, 0x00b70000, 0x00b70000 } },
 605         { 6, 0x989c,
 606             { 0x00840000, 0x00840000, 0x00840000, 0x00840000, 0x00840000 } },
 607         { 6, 0x989c,
 608             { 0x00980000, 0x00980000, 0x00980000, 0x00980000, 0x00980000 } },
 609         { 6, 0x989c,
 610             { 0x00c00000, 0x00c00000, 0x00c00000, 0x00c00000, 0x00c00000 } },
 611         { 6, 0x989c,
 612             { 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000 } },
 613         { 6, 0x989c,
 614             { 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000 } },
 615         { 6, 0x989c,
 616             { 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000 } },
 617         { 6, 0x989c,
 618             { 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000 } },
 619         { 6, 0x989c,
 620             { 0x00d70000, 0x00d70000, 0x00d70000, 0x00d70000, 0x00d70000 } },
 621         { 6, 0x989c,
 622             { 0x00610000, 0x00610000, 0x00610000, 0x00610000, 0x00610000 } },
 623         { 6, 0x989c,
 624             { 0x00fe0000, 0x00fe0000, 0x00fe0000, 0x00fe0000, 0x00fe0000 } },
 625         { 6, 0x989c,
 626             { 0x00de0000, 0x00de0000, 0x00de0000, 0x00de0000, 0x00de0000 } },
 627         { 6, 0x989c,
 628             { 0x007f0000, 0x007f0000, 0x007f0000, 0x007f0000, 0x007f0000 } },
 629         { 6, 0x989c,
 630             { 0x043d0000, 0x043d0000, 0x043d0000, 0x043d0000, 0x043d0000 } },
 631         { 6, 0x989c,
 632             { 0x00770000, 0x00770000, 0x00770000, 0x00770000, 0x00770000 } },
 633         { 6, 0x989c,
 634             { 0x00440000, 0x00440000, 0x00440000, 0x00440000, 0x00440000 } },
 635         { 6, 0x989c,
 636             { 0x00980000, 0x00980000, 0x00980000, 0x00980000, 0x00980000 } },
 637         { 6, 0x989c,
 638             { 0x00100080, 0x00100080, 0x00100080, 0x00100080, 0x00100080 } },
 639         { 6, 0x989c,
 640             { 0x0005c034, 0x0005c034, 0x0005c034, 0x0005c034, 0x0005c034 } },
 641         { 6, 0x989c,
 642             { 0x003100f0, 0x003100f0, 0x003100f0, 0x003100f0, 0x003100f0 } },
 643         { 6, 0x989c,
 644             { 0x000c011f, 0x000c011f, 0x000c011f, 0x000c011f, 0x000c011f } },
 645         { 6, 0x989c,
 646             { 0x00510040, 0x00510040, 0x005100a0, 0x005100a0, 0x005100a0 } },
 647         { 6, 0x989c,
 648             { 0x0050006a, 0x0050006a, 0x005000dd, 0x005000dd, 0x005000dd } },
 649         { 6, 0x989c,
 650             { 0x00000001, 0x00000001, 0x00000000, 0x00000000, 0x00000000 } },
 651         { 6, 0x989c,
 652             { 0x00004044, 0x00004044, 0x00004044, 0x00004044, 0x00004044 } },
 653         { 6, 0x989c,
 654             { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
 655         { 6, 0x989c,
 656             { 0x000060c0, 0x000060c0, 0x000060c0, 0x000060c0, 0x000060c0 } },
 657         { 6, 0x989c,
 658             { 0x00002c00, 0x00002c00, 0x00003600, 0x00003600, 0x00003600 } },
 659         { 6, 0x98c8,
 660             { 0x00000403, 0x00000403, 0x00040403, 0x00040403, 0x00040403 } },
 661         { 7, 0x989c,
 662             { 0x00006400, 0x00006400, 0x00006400, 0x00006400, 0x00006400 } },
 663         { 7, 0x989c,
 664             { 0x00000800, 0x00000800, 0x00000800, 0x00000800, 0x00000800 } },
 665         { 7, 0x98cc,
 666             { 0x0000000e, 0x0000000e, 0x0000000e, 0x0000000e, 0x0000000e } },
 667 };
 668
 669 /* RF2413/2414 mode-specific init registers */
 670 static const struct ath5k_ini_rf rfregs_2413[] = {
 671         { 1, AR5K_RF_BUFFER_CONTROL_4,
 672         /*         mode b      mode g     mode gTurbo */
 673                 { 0x00000020, 0x00000020, 0x00000020 } },
 674         { 2, AR5K_RF_BUFFER_CONTROL_3,
 675                 { 0x02001408, 0x02001408, 0x02001408 } },
 676         { 3, AR5K_RF_BUFFER_CONTROL_6,
 677                 { 0x00e020c0, 0x00e020c0, 0x00e020c0 } },
 678         { 6, AR5K_RF_BUFFER,
 679                 { 0xf0000000, 0xf0000000, 0xf0000000 } },
 680         { 6, AR5K_RF_BUFFER,
 681                 { 0x00000000, 0x00000000, 0x00000000 } },
 682         { 6, AR5K_RF_BUFFER,
 683                 { 0x03000000, 0x03000000, 0x03000000 } },
 684         { 6, AR5K_RF_BUFFER,
 685                 { 0x00000000, 0x00000000, 0x00000000 } },
 686         { 6, AR5K_RF_BUFFER,
 687                 { 0x00000000, 0x00000000, 0x00000000 } },
 688         { 6, AR5K_RF_BUFFER,
 689                 { 0x00000000, 0x00000000, 0x00000000 } },
 690         { 6, AR5K_RF_BUFFER,
 691                 { 0x00000000, 0x00000000, 0x00000000 } },
 692         { 6, AR5K_RF_BUFFER,
 693                 { 0x00000000, 0x00000000, 0x00000000 } },
 694         { 6, AR5K_RF_BUFFER,
 695                 { 0x40400000, 0x40400000, 0x40400000 } },
 696         { 6, AR5K_RF_BUFFER,
 697                 { 0x65050000, 0x65050000, 0x65050000 } },
 698         { 6, AR5K_RF_BUFFER,
 699                 { 0x00000000, 0x00000000, 0x00000000 } },
 700         { 6, AR5K_RF_BUFFER,
 701                 { 0x00000000, 0x00000000, 0x00000000 } },
 702         { 6, AR5K_RF_BUFFER,
 703                 { 0x00420000, 0x00420000, 0x00420000 } },
 704         { 6, AR5K_RF_BUFFER,
 705                 { 0x00b50000, 0x00b50000, 0x00b50000 } },
 706         { 6, AR5K_RF_BUFFER,
 707                 { 0x00030000, 0x00030000, 0x00030000 } },
 708         { 6, AR5K_RF_BUFFER,
 709                 { 0x00f70000, 0x00f70000, 0x00f70000 } },
 710         { 6, AR5K_RF_BUFFER,
 711                 { 0x009d0000, 0x009d0000, 0x009d0000 } },
 712         { 6, AR5K_RF_BUFFER,
 713                 { 0x00220000, 0x00220000, 0x00220000 } },
 714         { 6, AR5K_RF_BUFFER,
 715                 { 0x04220000, 0x04220000, 0x04220000 } },
 716         { 6, AR5K_RF_BUFFER,
 717                 { 0x00230018, 0x00230018, 0x00230018 } },
 718         { 6, AR5K_RF_BUFFER,
 719                 { 0x00280050, 0x00280050, 0x00280050 } },
 720         { 6, AR5K_RF_BUFFER,
 721                 { 0x005000c3, 0x005000c3, 0x005000c3 } },
 722         { 6, AR5K_RF_BUFFER,
 723                 { 0x0004007f, 0x0004007f, 0x0004007f } },
 724         { 6, AR5K_RF_BUFFER,
 725                 { 0x00000458, 0x00000458, 0x00000458 } },
 726         { 6, AR5K_RF_BUFFER,
 727                 { 0x00000000, 0x00000000, 0x00000000 } },
 728         { 6, AR5K_RF_BUFFER,
 729                 { 0x0000c000, 0x0000c000, 0x0000c000 } },
 730         { 6, AR5K_RF_BUFFER_CONTROL_5,
 731                 { 0x00400230, 0x00400230, 0x00400230 } },
 732         { 7, AR5K_RF_BUFFER,
 733                 { 0x00006400, 0x00006400, 0x00006400 } },
 734         { 7, AR5K_RF_BUFFER,
 735                 { 0x00000800, 0x00000800, 0x00000800 } },
 736         { 7, AR5K_RF_BUFFER_CONTROL_2,
 737                 { 0x0000000e, 0x0000000e, 0x0000000e } },
 738 };
 739
 740 /* RF2425 mode-specific init registers */
 741 static const struct ath5k_ini_rf rfregs_2425[] = {
 742         { 1, AR5K_RF_BUFFER_CONTROL_4,
 743         /*         mode g     mode gTurbo */
 744                 { 0x00000020, 0x00000020 } },
 745         { 2, AR5K_RF_BUFFER_CONTROL_3,
 746                 { 0x02001408, 0x02001408 } },
 747         { 3, AR5K_RF_BUFFER_CONTROL_6,
 748                 { 0x00e020c0, 0x00e020c0 } },
 749         { 6, AR5K_RF_BUFFER,
 750                 { 0x10000000, 0x10000000 } },
 751         { 6, AR5K_RF_BUFFER,
 752                 { 0x00000000, 0x00000000 } },
 753         { 6, AR5K_RF_BUFFER,
 754                 { 0x00000000, 0x00000000 } },
 755         { 6, AR5K_RF_BUFFER,
 756                 { 0x00000000, 0x00000000 } },
 757         { 6, AR5K_RF_BUFFER,
 758                 { 0x00000000, 0x00000000 } },
 759         { 6, AR5K_RF_BUFFER,
 760                 { 0x00000000, 0x00000000 } },
 761         { 6, AR5K_RF_BUFFER,
 762                 { 0x00000000, 0x00000000 } },
 763         { 6, AR5K_RF_BUFFER,
 764                 { 0x00000000, 0x00000000 } },
 765         { 6, AR5K_RF_BUFFER,
 766                 { 0x00000000, 0x00000000 } },
 767         { 6, AR5K_RF_BUFFER,
 768                 { 0x00000000, 0x00000000 } },
 769         { 6, AR5K_RF_BUFFER,
 770                 { 0x00000000, 0x00000000 } },
 771         { 6, AR5K_RF_BUFFER,
 772                 { 0x002a0000, 0x002a0000 } },
 773         { 6, AR5K_RF_BUFFER,
 774                 { 0x00000000, 0x00000000 } },
 775         { 6, AR5K_RF_BUFFER,
 776                 { 0x00000000, 0x00000000 } },
 777         { 6, AR5K_RF_BUFFER,
 778                 { 0x00100000, 0x00100000 } },
 779         { 6, AR5K_RF_BUFFER,
 780                 { 0x00020000, 0x00020000 } },
 781         { 6, AR5K_RF_BUFFER,
 782                 { 0x00730000, 0x00730000 } },
 783         { 6, AR5K_RF_BUFFER,
 784                 { 0x00f80000, 0x00f80000 } },
 785         { 6, AR5K_RF_BUFFER,
 786                 { 0x00e70000, 0x00e70000 } },
 787         { 6, AR5K_RF_BUFFER,
 788                 { 0x00140000, 0x00140000 } },
 789         { 6, AR5K_RF_BUFFER,
 790                 { 0x00910040, 0x00910040 } },
 791         { 6, AR5K_RF_BUFFER,
 792                 { 0x0007001a, 0x0007001a } },
 793         { 6, AR5K_RF_BUFFER,
 794                 { 0x00410000, 0x00410000 } },
 795         { 6, AR5K_RF_BUFFER,
 796                 { 0x00810060, 0x00810060 } },
 797         { 6, AR5K_RF_BUFFER,
 798                 { 0x00020803, 0x00020803 } },
 799         { 6, AR5K_RF_BUFFER,
 800                 { 0x00000000, 0x00000000 } },
 801         { 6, AR5K_RF_BUFFER,
 802                 { 0x00000000, 0x00000000 } },
 803         { 6, AR5K_RF_BUFFER,
 804                 { 0x00001660, 0x00001660 } },
 805         { 6, AR5K_RF_BUFFER,
 806                 { 0x00001688, 0x00001688 } },
 807         { 6, AR5K_RF_BUFFER_CONTROL_1,
 808                 { 0x00000001, 0x00000001 } },
 809         { 7, AR5K_RF_BUFFER,
 810                 { 0x00006400, 0x00006400 } },
 811         { 7, AR5K_RF_BUFFER,
 812                 { 0x00000800, 0x00000800 } },
 813         { 7, AR5K_RF_BUFFER_CONTROL_2,
 814                 { 0x0000000e, 0x0000000e } },
 815 };
 816
 817 /* Initial RF Gain settings for RF5112 */
 818 static const struct ath5k_ini_rfgain rfgain_5112[] = {
 819         /*                            5Ghz      2Ghz    */
 820         { AR5K_RF_GAIN(0),      { 0x00000007, 0x00000007 } },
 821         { AR5K_RF_GAIN(1),      { 0x00000047, 0x00000047 } },
 822         { AR5K_RF_GAIN(2),      { 0x00000087, 0x00000087 } },
 823         { AR5K_RF_GAIN(3),      { 0x000001a0, 0x000001a0 } },
 824         { AR5K_RF_GAIN(4),      { 0x000001e0, 0x000001e0 } },
 825         { AR5K_RF_GAIN(5),      { 0x00000020, 0x00000020 } },
 826         { AR5K_RF_GAIN(6),      { 0x00000060, 0x00000060 } },
 827         { AR5K_RF_GAIN(7),      { 0x000001a1, 0x000001a1 } },
 828         { AR5K_RF_GAIN(8),      { 0x000001e1, 0x000001e1 } },
 829         { AR5K_RF_GAIN(9),      { 0x00000021, 0x00000021 } },
 830         { AR5K_RF_GAIN(10),     { 0x00000061, 0x00000061 } },
 831         { AR5K_RF_GAIN(11),     { 0x00000162, 0x00000162 } },
 832         { AR5K_RF_GAIN(12),     { 0x000001a2, 0x000001a2 } },
 833         { AR5K_RF_GAIN(13),     { 0x000001e2, 0x000001e2 } },
 834         { AR5K_RF_GAIN(14),     { 0x00000022, 0x00000022 } },
 835         { AR5K_RF_GAIN(15),     { 0x00000062, 0x00000062 } },
 836         { AR5K_RF_GAIN(16),     { 0x00000163, 0x00000163 } },
 837         { AR5K_RF_GAIN(17),     { 0x000001a3, 0x000001a3 } },
 838         { AR5K_RF_GAIN(18),     { 0x000001e3, 0x000001e3 } },
 839         { AR5K_RF_GAIN(19),     { 0x00000023, 0x00000023 } },
 840         { AR5K_RF_GAIN(20),     { 0x00000063, 0x00000063 } },
 841         { AR5K_RF_GAIN(21),     { 0x00000184, 0x00000184 } },
 842         { AR5K_RF_GAIN(22),     { 0x000001c4, 0x000001c4 } },
 843         { AR5K_RF_GAIN(23),     { 0x00000004, 0x00000004 } },
 844         { AR5K_RF_GAIN(24),     { 0x000001ea, 0x0000000b } },
 845         { AR5K_RF_GAIN(25),     { 0x0000002a, 0x0000004b } },
 846         { AR5K_RF_GAIN(26),     { 0x0000006a, 0x0000008b } },
 847         { AR5K_RF_GAIN(27),     { 0x000000aa, 0x000001ac } },
 848         { AR5K_RF_GAIN(28),     { 0x000001ab, 0x000001ec } },
 849         { AR5K_RF_GAIN(29),     { 0x000001eb, 0x0000002c } },
 850         { AR5K_RF_GAIN(30),     { 0x0000002b, 0x00000012 } },
 851         { AR5K_RF_GAIN(31),     { 0x0000006b, 0x00000052 } },
 852         { AR5K_RF_GAIN(32),     { 0x000000ab, 0x00000092 } },
 853         { AR5K_RF_GAIN(33),     { 0x000001ac, 0x00000193 } },
 854         { AR5K_RF_GAIN(34),     { 0x000001ec, 0x000001d3 } },
 855         { AR5K_RF_GAIN(35),     { 0x0000002c, 0x00000013 } },
 856         { AR5K_RF_GAIN(36),     { 0x0000003a, 0x00000053 } },
 857         { AR5K_RF_GAIN(37),     { 0x0000007a, 0x00000093 } },
 858         { AR5K_RF_GAIN(38),     { 0x000000ba, 0x00000194 } },
 859         { AR5K_RF_GAIN(39),     { 0x000001bb, 0x000001d4 } },
 860         { AR5K_RF_GAIN(40),     { 0x000001fb, 0x00000014 } },
 861         { AR5K_RF_GAIN(41),     { 0x0000003b, 0x0000003a } },
 862         { AR5K_RF_GAIN(42),     { 0x0000007b, 0x0000007a } },
 863         { AR5K_RF_GAIN(43),     { 0x000000bb, 0x000000ba } },
 864         { AR5K_RF_GAIN(44),     { 0x000001bc, 0x000001bb } },
 865         { AR5K_RF_GAIN(45),     { 0x000001fc, 0x000001fb } },
 866         { AR5K_RF_GAIN(46),     { 0x0000003c, 0x0000003b } },
 867         { AR5K_RF_GAIN(47),     { 0x0000007c, 0x0000007b } },
 868         { AR5K_RF_GAIN(48),     { 0x000000bc, 0x000000bb } },
 869         { AR5K_RF_GAIN(49),     { 0x000000fc, 0x000001bc } },
 870         { AR5K_RF_GAIN(50),     { 0x000000fc, 0x000001fc } },
 871         { AR5K_RF_GAIN(51),     { 0x000000fc, 0x0000003c } },
 872         { AR5K_RF_GAIN(52),     { 0x000000fc, 0x0000007c } },
 873         { AR5K_RF_GAIN(53),     { 0x000000fc, 0x000000bc } },
 874         { AR5K_RF_GAIN(54),     { 0x000000fc, 0x000000fc } },
 875         { AR5K_RF_GAIN(55),     { 0x000000fc, 0x000000fc } },
 876         { AR5K_RF_GAIN(56),     { 0x000000fc, 0x000000fc } },
 877         { AR5K_RF_GAIN(57),     { 0x000000fc, 0x000000fc } },
 878         { AR5K_RF_GAIN(58),     { 0x000000fc, 0x000000fc } },
 879         { AR5K_RF_GAIN(59),     { 0x000000fc, 0x000000fc } },
 880         { AR5K_RF_GAIN(60),     { 0x000000fc, 0x000000fc } },
 881         { AR5K_RF_GAIN(61),     { 0x000000fc, 0x000000fc } },
 882         { AR5K_RF_GAIN(62),     { 0x000000fc, 0x000000fc } },
 883         { AR5K_RF_GAIN(63),     { 0x000000fc, 0x000000fc } },
 884 };
 885
 886 /* Initial RF Gain settings for RF5413 */
 887 static const struct ath5k_ini_rfgain rfgain_5413[] = {
 888         /*                            5Ghz      2Ghz    */
 889         { AR5K_RF_GAIN(0),      { 0x00000000, 0x00000000 } },
 890         { AR5K_RF_GAIN(1),      { 0x00000040, 0x00000040 } },
 891         { AR5K_RF_GAIN(2),      { 0x00000080, 0x00000080 } },
 892         { AR5K_RF_GAIN(3),      { 0x000001a1, 0x00000161 } },
 893         { AR5K_RF_GAIN(4),      { 0x000001e1, 0x000001a1 } },
 894         { AR5K_RF_GAIN(5),      { 0x00000021, 0x000001e1 } },
 895         { AR5K_RF_GAIN(6),      { 0x00000061, 0x00000021 } },
 896         { AR5K_RF_GAIN(7),      { 0x00000188, 0x00000061 } },
 897         { AR5K_RF_GAIN(8),      { 0x000001c8, 0x00000188 } },
 898         { AR5K_RF_GAIN(9),      { 0x00000008, 0x000001c8 } },
 899         { AR5K_RF_GAIN(10),     { 0x00000048, 0x00000008 } },
 900         { AR5K_RF_GAIN(11),     { 0x00000088, 0x00000048 } },
 901         { AR5K_RF_GAIN(12),     { 0x000001a9, 0x00000088 } },
 902         { AR5K_RF_GAIN(13),     { 0x000001e9, 0x00000169 } },
 903         { AR5K_RF_GAIN(14),     { 0x00000029, 0x000001a9 } },
 904         { AR5K_RF_GAIN(15),     { 0x00000069, 0x000001e9 } },
 905         { AR5K_RF_GAIN(16),     { 0x000001d0, 0x00000029 } },
 906         { AR5K_RF_GAIN(17),     { 0x00000010, 0x00000069 } },
 907         { AR5K_RF_GAIN(18),     { 0x00000050, 0x00000190 } },
 908         { AR5K_RF_GAIN(19),     { 0x00000090, 0x000001d0 } },
 909         { AR5K_RF_GAIN(20),     { 0x000001b1, 0x00000010 } },
 910         { AR5K_RF_GAIN(21),     { 0x000001f1, 0x00000050 } },
 911         { AR5K_RF_GAIN(22),     { 0x00000031, 0x00000090 } },
 912         { AR5K_RF_GAIN(23),     { 0x00000071, 0x00000171 } },
 913         { AR5K_RF_GAIN(24),     { 0x000001b8, 0x000001b1 } },
 914         { AR5K_RF_GAIN(25),     { 0x000001f8, 0x000001f1 } },
 915         { AR5K_RF_GAIN(26),     { 0x00000038, 0x00000031 } },
 916         { AR5K_RF_GAIN(27),     { 0x00000078, 0x00000071 } },
 917         { AR5K_RF_GAIN(28),     { 0x00000199, 0x00000198 } },
 918         { AR5K_RF_GAIN(29),     { 0x000001d9, 0x000001d8 } },
 919         { AR5K_RF_GAIN(30),     { 0x00000019, 0x00000018 } },
 920         { AR5K_RF_GAIN(31),     { 0x00000059, 0x00000058 } },
 921         { AR5K_RF_GAIN(32),     { 0x00000099, 0x00000098 } },
 922         { AR5K_RF_GAIN(33),     { 0x000000d9, 0x00000179 } },
 923         { AR5K_RF_GAIN(34),     { 0x000000f9, 0x000001b9 } },
 924         { AR5K_RF_GAIN(35),     { 0x000000f9, 0x000001f9 } },
 925         { AR5K_RF_GAIN(36),     { 0x000000f9, 0x00000039 } },
 926         { AR5K_RF_GAIN(37),     { 0x000000f9, 0x00000079 } },
 927         { AR5K_RF_GAIN(38),     { 0x000000f9, 0x000000b9 } },
 928         { AR5K_RF_GAIN(39),     { 0x000000f9, 0x000000f9 } },
 929         { AR5K_RF_GAIN(40),     { 0x000000f9, 0x000000f9 } },
 930         { AR5K_RF_GAIN(41),     { 0x000000f9, 0x000000f9 } },
 931         { AR5K_RF_GAIN(42),     { 0x000000f9, 0x000000f9 } },
 932         { AR5K_RF_GAIN(43),     { 0x000000f9, 0x000000f9 } },
 933         { AR5K_RF_GAIN(44),     { 0x000000f9, 0x000000f9 } },
 934         { AR5K_RF_GAIN(45),     { 0x000000f9, 0x000000f9 } },
 935         { AR5K_RF_GAIN(46),     { 0x000000f9, 0x000000f9 } },
 936         { AR5K_RF_GAIN(47),     { 0x000000f9, 0x000000f9 } },
 937         { AR5K_RF_GAIN(48),     { 0x000000f9, 0x000000f9 } },
 938         { AR5K_RF_GAIN(49),     { 0x000000f9, 0x000000f9 } },
 939         { AR5K_RF_GAIN(50),     { 0x000000f9, 0x000000f9 } },
 940         { AR5K_RF_GAIN(51),     { 0x000000f9, 0x000000f9 } },
 941         { AR5K_RF_GAIN(52),     { 0x000000f9, 0x000000f9 } },
 942         { AR5K_RF_GAIN(53),     { 0x000000f9, 0x000000f9 } },
 943         { AR5K_RF_GAIN(54),     { 0x000000f9, 0x000000f9 } },
 944         { AR5K_RF_GAIN(55),     { 0x000000f9, 0x000000f9 } },
 945         { AR5K_RF_GAIN(56),     { 0x000000f9, 0x000000f9 } },
 946         { AR5K_RF_GAIN(57),     { 0x000000f9, 0x000000f9 } },
 947         { AR5K_RF_GAIN(58),     { 0x000000f9, 0x000000f9 } },
 948         { AR5K_RF_GAIN(59),     { 0x000000f9, 0x000000f9 } },
 949         { AR5K_RF_GAIN(60),     { 0x000000f9, 0x000000f9 } },
 950         { AR5K_RF_GAIN(61),     { 0x000000f9, 0x000000f9 } },
 951         { AR5K_RF_GAIN(62),     { 0x000000f9, 0x000000f9 } },
 952         { AR5K_RF_GAIN(63),     { 0x000000f9, 0x000000f9 } },
 953 };
 954
 955 /* Initial RF Gain settings for RF2413 */
 956 static const struct ath5k_ini_rfgain rfgain_2413[] = {
 957         { AR5K_RF_GAIN(0), { 0x00000000 } },
 958         { AR5K_RF_GAIN(1), { 0x00000040 } },
 959         { AR5K_RF_GAIN(2), { 0x00000080 } },
 960         { AR5K_RF_GAIN(3), { 0x00000181 } },
 961         { AR5K_RF_GAIN(4), { 0x000001c1 } },
 962         { AR5K_RF_GAIN(5), { 0x00000001 } },
 963         { AR5K_RF_GAIN(6), { 0x00000041 } },
 964         { AR5K_RF_GAIN(7), { 0x00000081 } },
 965         { AR5K_RF_GAIN(8), { 0x00000168 } },
 966         { AR5K_RF_GAIN(9), { 0x000001a8 } },
 967         { AR5K_RF_GAIN(10), { 0x000001e8 } },
 968         { AR5K_RF_GAIN(11), { 0x00000028 } },
 969         { AR5K_RF_GAIN(12), { 0x00000068 } },
 970         { AR5K_RF_GAIN(13), { 0x00000189 } },
 971         { AR5K_RF_GAIN(14), { 0x000001c9 } },
 972         { AR5K_RF_GAIN(15), { 0x00000009 } },
 973         { AR5K_RF_GAIN(16), { 0x00000049 } },
 974         { AR5K_RF_GAIN(17), { 0x00000089 } },
 975         { AR5K_RF_GAIN(18), { 0x00000190 } },
 976         { AR5K_RF_GAIN(19), { 0x000001d0 } },
 977         { AR5K_RF_GAIN(20), { 0x00000010 } },
 978         { AR5K_RF_GAIN(21), { 0x00000050 } },
 979         { AR5K_RF_GAIN(22), { 0x00000090 } },
 980         { AR5K_RF_GAIN(23), { 0x00000191 } },
 981         { AR5K_RF_GAIN(24), { 0x000001d1 } },
 982         { AR5K_RF_GAIN(25), { 0x00000011 } },
 983         { AR5K_RF_GAIN(26), { 0x00000051 } },
 984         { AR5K_RF_GAIN(27), { 0x00000091 } },
 985         { AR5K_RF_GAIN(28), { 0x00000178 } },
 986         { AR5K_RF_GAIN(29), { 0x000001b8 } },
 987         { AR5K_RF_GAIN(30), { 0x000001f8 } },
 988         { AR5K_RF_GAIN(31), { 0x00000038 } },
 989         { AR5K_RF_GAIN(32), { 0x00000078 } },
 990         { AR5K_RF_GAIN(33), { 0x00000199 } },
 991         { AR5K_RF_GAIN(34), { 0x000001d9 } },
 992         { AR5K_RF_GAIN(35), { 0x00000019 } },
 993         { AR5K_RF_GAIN(36), { 0x00000059 } },
 994         { AR5K_RF_GAIN(37), { 0x00000099 } },
 995         { AR5K_RF_GAIN(38), { 0x000000d9 } },
 996         { AR5K_RF_GAIN(39), { 0x000000f9 } },
 997         { AR5K_RF_GAIN(40), { 0x000000f9 } },
 998         { AR5K_RF_GAIN(41), { 0x000000f9 } },
 999         { AR5K_RF_GAIN(42), { 0x000000f9 } },
1000         { AR5K_RF_GAIN(43), { 0x000000f9 } },
1001         { AR5K_RF_GAIN(44), { 0x000000f9 } },
1002         { AR5K_RF_GAIN(45), { 0x000000f9 } },
1003         { AR5K_RF_GAIN(46), { 0x000000f9 } },
1004         { AR5K_RF_GAIN(47), { 0x000000f9 } },
1005         { AR5K_RF_GAIN(48), { 0x000000f9 } },
1006         { AR5K_RF_GAIN(49), { 0x000000f9 } },
1007         { AR5K_RF_GAIN(50), { 0x000000f9 } },
1008         { AR5K_RF_GAIN(51), { 0x000000f9 } },
1009         { AR5K_RF_GAIN(52), { 0x000000f9 } },
1010         { AR5K_RF_GAIN(53), { 0x000000f9 } },
1011         { AR5K_RF_GAIN(54), { 0x000000f9 } },
1012         { AR5K_RF_GAIN(55), { 0x000000f9 } },
1013         { AR5K_RF_GAIN(56), { 0x000000f9 } },
1014         { AR5K_RF_GAIN(57), { 0x000000f9 } },
1015         { AR5K_RF_GAIN(58), { 0x000000f9 } },
1016         { AR5K_RF_GAIN(59), { 0x000000f9 } },
1017         { AR5K_RF_GAIN(60), { 0x000000f9 } },
1018         { AR5K_RF_GAIN(61), { 0x000000f9 } },
1019         { AR5K_RF_GAIN(62), { 0x000000f9 } },
1020         { AR5K_RF_GAIN(63), { 0x000000f9 } },
1021 };
1022
1023 static const struct ath5k_gain_opt rfgain_opt_5112 = {
1024         1,
1025         8,
1026         {
1027                 { { 3, 0, 0, 0, 0, 0, 0 }, 6 },
1028                 { { 2, 0, 0, 0, 0, 0, 0 }, 0 },
1029                 { { 1, 0, 0, 0, 0, 0, 0 }, -3 },
1030                 { { 0, 0, 0, 0, 0, 0, 0 }, -6 },
1031                 { { 0, 1, 1, 0, 0, 0, 0 }, -8 },
1032                 { { 0, 1, 1, 0, 1, 1, 0 }, -10 },
1033                 { { 0, 1, 0, 1, 1, 1, 0 }, -13 },
1034                 { { 0, 1, 0, 1, 1, 0, 1 }, -16 },
1035         }
1036 };
1037
1038 /*
1039  * Used to modify RF Banks before writing them to AR5K_RF_BUFFER
1040  */
1041 static unsigned int ath5k_hw_rfregs_op(u32 *rf, u32 offset, u32 reg, u32 bits,
1042                 u32 first, u32 col, bool set)
1043 {
1044         u32 mask, entry, last, data, shift, position;
1045         s32 left;
1046         int i;
1047
1048         data = 0;
1049
1050         if (rf == NULL)
1051                 /* should not happen */
1052                 return 0;
1053
1054         if (!(col <= 3 && bits <= 32 && first + bits <= 319)) {
1055                 ATH5K_PRINTF("invalid values at offset %u\n", offset);
1056                 return 0;
1057         }
1058
1059         entry = ((first - 1) / 8) + offset;
1060         position = (first - 1) % 8;
1061
1062         if (set)
1063                 data = ath5k_hw_bitswap(reg, bits);
1064
1065         for (i = shift = 0, left = bits; left > 0; position = 0, entry++, i++) {
1066                 last = (position + left > 8) ? 8 : position + left;
1067                 mask = (((1 << last) - 1) ^ ((1 << position) - 1)) << (col * 8);
1068
1069                 if (set) {
1070                         rf[entry] &= ~mask;
1071                         rf[entry] |= ((data << position) << (col * 8)) & mask;
1072                         data >>= (8 - position);
1073                 } else {
1074                         data = (((rf[entry] & mask) >> (col * 8)) >> position)
1075                                 << shift;
1076                         shift += last - position;
1077                 }
1078
1079                 left -= 8 - position;
1080         }
1081
1082         data = set ? 1 : ath5k_hw_bitswap(data, bits);
1083
1084         return data;
1085 }
1086
1087 static u32 ath5k_hw_rfregs_gainf_corr(struct ath5k_hw *ah)
1088 {
1089         u32 mix, step;
1090         u32 *rf;
1091
1092         if (ah->ah_rf_banks == NULL)
1093                 return 0;
1094
1095         rf = ah->ah_rf_banks;
1096         ah->ah_gain.g_f_corr = 0;
1097
1098         if (ath5k_hw_rfregs_op(rf, ah->ah_offset[7], 0, 1, 36, 0, false) != 1)
1099                 return 0;
1100
1101         step = ath5k_hw_rfregs_op(rf, ah->ah_offset[7], 0, 4, 32, 0, false);
1102         mix = ah->ah_gain.g_step->gos_param[0];
1103
1104         switch (mix) {
1105         case 3:
1106                 ah->ah_gain.g_f_corr = step * 2;
1107                 break;
1108         case 2:
1109                 ah->ah_gain.g_f_corr = (step - 5) * 2;
1110                 break;
1111         case 1:
1112                 ah->ah_gain.g_f_corr = step;
1113                 break;
1114         default:
1115                 ah->ah_gain.g_f_corr = 0;
1116                 break;
1117         }
1118
1119         return ah->ah_gain.g_f_corr;
1120 }
1121
1122 static bool ath5k_hw_rfregs_gain_readback(struct ath5k_hw *ah)
1123 {
1124         u32 step, mix, level[4];
1125         u32 *rf;
1126
1127         if (ah->ah_rf_banks == NULL)
1128                 return false;
1129
1130         rf = ah->ah_rf_banks;
1131
1132         if (ah->ah_radio == AR5K_RF5111) {
1133                 step = ath5k_hw_rfregs_op(rf, ah->ah_offset[7], 0, 6, 37, 0,
1134                                 false);
1135                 level[0] = 0;
1136                 level[1] = (step == 0x3f) ? 0x32 : step + 4;
1137                 level[2] = (step != 0x3f) ? 0x40 : level[0];
1138                 level[3] = level[2] + 0x32;
1139
1140                 ah->ah_gain.g_high = level[3] -
1141                         (step == 0x3f ? AR5K_GAIN_DYN_ADJUST_HI_MARGIN : -5);
1142                 ah->ah_gain.g_low = level[0] +
1143                         (step == 0x3f ? AR5K_GAIN_DYN_ADJUST_LO_MARGIN : 0);
1144         } else {
1145                 mix = ath5k_hw_rfregs_op(rf, ah->ah_offset[7], 0, 1, 36, 0,
1146                                 false);
1147                 level[0] = level[2] = 0;
1148
1149                 if (mix == 1) {
1150                         level[1] = level[3] = 83;
1151                 } else {
1152                         level[1] = level[3] = 107;
1153                         ah->ah_gain.g_high = 55;
1154                 }
1155         }
1156
1157         return (ah->ah_gain.g_current >= level[0] &&
1158                         ah->ah_gain.g_current <= level[1]) ||
1159                 (ah->ah_gain.g_current >= level[2] &&
1160                         ah->ah_gain.g_current <= level[3]);
1161 }
1162
1163 static s32 ath5k_hw_rfregs_gain_adjust(struct ath5k_hw *ah)
1164 {
1165         const struct ath5k_gain_opt *go;
1166         int ret = 0;
1167
1168         switch (ah->ah_radio) {
1169         case AR5K_RF5111:
1170                 go = &rfgain_opt_5111;
1171                 break;
1172         case AR5K_RF5112:
1173                 go = &rfgain_opt_5112;
1174                 break;
1175         default:
1176                 return 0;
1177         }
1178
1179         ah->ah_gain.g_step = &go->go_step[ah->ah_gain.g_step_idx];
1180
1181         if (ah->ah_gain.g_current >= ah->ah_gain.g_high) {
1182                 if (ah->ah_gain.g_step_idx == 0)
1183                         return -1;
1184                 for (ah->ah_gain.g_target = ah->ah_gain.g_current;
1185                                 ah->ah_gain.g_target >=  ah->ah_gain.g_high &&
1186                                 ah->ah_gain.g_step_idx > 0;
1187                                 ah->ah_gain.g_step =
1188                                         &go->go_step[ah->ah_gain.g_step_idx])
1189                         ah->ah_gain.g_target -= 2 *
1190                             (go->go_step[--(ah->ah_gain.g_step_idx)].gos_gain -
1191                             ah->ah_gain.g_step->gos_gain);
1192
1193                 ret = 1;
1194                 goto done;
1195         }
1196
1197         if (ah->ah_gain.g_current <= ah->ah_gain.g_low) {
1198                 if (ah->ah_gain.g_step_idx == (go->go_steps_count - 1))
1199                         return -2;
1200                 for (ah->ah_gain.g_target = ah->ah_gain.g_current;
1201                                 ah->ah_gain.g_target <= ah->ah_gain.g_low &&
1202                                 ah->ah_gain.g_step_idx < go->go_steps_count-1;
1203                                 ah->ah_gain.g_step =
1204                                         &go->go_step[ah->ah_gain.g_step_idx])
1205                         ah->ah_gain.g_target -= 2 *
1206                             (go->go_step[++ah->ah_gain.g_step_idx].gos_gain -
1207                             ah->ah_gain.g_step->gos_gain);
1208
1209                 ret = 2;
1210                 goto done;
1211         }
1212
1213 done:
1214         ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_CALIBRATE,
1215                 "ret %d, gain step %u, current gain %u, target gain %u\n",
1216                 ret, ah->ah_gain.g_step_idx, ah->ah_gain.g_current,
1217                 ah->ah_gain.g_target);
1218
1219         return ret;
1220 }
1221
1222 /*
1223  * Read EEPROM Calibration data, modify RF Banks and Initialize RF5111
1224  */
1225 static int ath5k_hw_rf5111_rfregs(struct ath5k_hw *ah,
1226                 struct ieee80211_channel *channel, unsigned int mode)
1227 {
1228         struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
1229         u32 *rf;
1230         const unsigned int rf_size = ARRAY_SIZE(rfregs_5111);
1231         unsigned int i;
1232         int obdb = -1, bank = -1;
1233         u32 ee_mode;
1234
1235         AR5K_ASSERT_ENTRY(mode, AR5K_MODE_MAX);
1236
1237         rf = ah->ah_rf_banks;
1238
1239         /* Copy values to modify them */
1240         for (i = 0; i < rf_size; i++) {
1241                 if (rfregs_5111[i].rf_bank >= AR5K_RF5111_INI_RF_MAX_BANKS) {
1242                         ATH5K_ERR(ah->ah_sc, "invalid bank\n");
1243                         return -EINVAL;
1244                 }
1245
1246                 if (bank != rfregs_5111[i].rf_bank) {
1247                         bank = rfregs_5111[i].rf_bank;
1248                         ah->ah_offset[bank] = i;
1249                 }
1250
1251                 rf[i] = rfregs_5111[i].rf_value[mode];
1252         }
1253
1254         /* Modify bank 0 */
1255         if (channel->hw_value & CHANNEL_2GHZ) {
1256                 if (channel->hw_value & CHANNEL_CCK)
1257                         ee_mode = AR5K_EEPROM_MODE_11B;
1258                 else
1259                         ee_mode = AR5K_EEPROM_MODE_11G;
1260                 obdb = 0;
1261
1262                 if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[0],
1263                                 ee->ee_ob[ee_mode][obdb], 3, 119, 0, true))
1264                         return -EINVAL;
1265
1266                 if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[0],
1267                                 ee->ee_ob[ee_mode][obdb], 3, 122, 0, true))
1268                         return -EINVAL;
1269
1270                 obdb = 1;
1271         /* Modify bank 6 */
1272         } else {
1273                 /* For 11a, Turbo and XR */
1274                 ee_mode = AR5K_EEPROM_MODE_11A;
1275                 obdb =   channel->center_freq >= 5725 ? 3 :
1276                         (channel->center_freq >= 5500 ? 2 :
1277                         (channel->center_freq >= 5260 ? 1 :
1278                          (channel->center_freq > 4000 ? 0 : -1)));
1279
1280                 if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[6],
1281                                 ee->ee_pwd_84, 1, 51, 3, true))
1282                         return -EINVAL;
1283
1284                 if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[6],
1285                                 ee->ee_pwd_90, 1, 45, 3, true))
1286                         return -EINVAL;
1287         }
1288
1289         if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[6],
1290                         !ee->ee_xpd[ee_mode], 1, 95, 0, true))
1291                 return -EINVAL;
1292
1293         if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[6],
1294                         ee->ee_x_gain[ee_mode], 4, 96, 0, true))
1295                 return -EINVAL;
1296
1297         if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[6], obdb >= 0 ?
1298                         ee->ee_ob[ee_mode][obdb] : 0, 3, 104, 0, true))
1299                 return -EINVAL;
1300
1301         if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[6], obdb >= 0 ?
1302                         ee->ee_db[ee_mode][obdb] : 0, 3, 107, 0, true))
1303                 return -EINVAL;
1304
1305         /* Modify bank 7 */
1306         if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[7],
1307                         ee->ee_i_gain[ee_mode], 6, 29, 0, true))
1308                 return -EINVAL;
1309
1310         if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[7],
1311                         ee->ee_xpd[ee_mode], 1, 4, 0, true))
1312                 return -EINVAL;
1313
1314         /* Write RF values */
1315         for (i = 0; i < rf_size; i++) {
1316                 AR5K_REG_WAIT(i);
1317                 ath5k_hw_reg_write(ah, rf[i], rfregs_5111[i].rf_register);
1318         }
1319
1320         return 0;
1321 }
1322
1323 /*
1324  * Read EEPROM Calibration data, modify RF Banks and Initialize RF5112
1325  */
1326 static int ath5k_hw_rf5112_rfregs(struct ath5k_hw *ah,
1327                 struct ieee80211_channel *channel, unsigned int mode)
1328 {
1329         const struct ath5k_ini_rf *rf_ini;
1330         struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
1331         u32 *rf;
1332         unsigned int rf_size, i;
1333         int obdb = -1, bank = -1;
1334         u32 ee_mode;
1335
1336         AR5K_ASSERT_ENTRY(mode, AR5K_MODE_MAX);
1337
1338         rf = ah->ah_rf_banks;
1339
1340         if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_2112A
1341                 && !test_bit(AR5K_MODE_11A, ah->ah_capabilities.cap_mode)) {
1342                 rf_ini = rfregs_2112a;
1343                 rf_size = ARRAY_SIZE(rfregs_5112a);
1344                 if (mode < 2) {
1345                         ATH5K_ERR(ah->ah_sc,"invalid channel mode: %i\n",mode);
1346                         return -EINVAL;
1347                 }
1348                 mode = mode - 2; /*no a/turboa modes for 2112*/
1349         } else if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A) {
1350                 rf_ini = rfregs_5112a;
1351                 rf_size = ARRAY_SIZE(rfregs_5112a);
1352         } else {
1353                 rf_ini = rfregs_5112;
1354                 rf_size = ARRAY_SIZE(rfregs_5112);
1355         }
1356
1357         /* Copy values to modify them */
1358         for (i = 0; i < rf_size; i++) {
1359                 if (rf_ini[i].rf_bank >= AR5K_RF5112_INI_RF_MAX_BANKS) {
1360                         ATH5K_ERR(ah->ah_sc, "invalid bank\n");
1361                         return -EINVAL;
1362                 }
1363
1364                 if (bank != rf_ini[i].rf_bank) {
1365                         bank = rf_ini[i].rf_bank;
1366                         ah->ah_offset[bank] = i;
1367                 }
1368
1369                 rf[i] = rf_ini[i].rf_value[mode];
1370         }
1371
1372         /* Modify bank 6 */
1373         if (channel->hw_value & CHANNEL_2GHZ) {
1374                 if (channel->hw_value & CHANNEL_OFDM)
1375                         ee_mode = AR5K_EEPROM_MODE_11G;
1376                 else
1377                         ee_mode = AR5K_EEPROM_MODE_11B;
1378                 obdb = 0;
1379
1380                 if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[6],
1381                                 ee->ee_ob[ee_mode][obdb], 3, 287, 0, true))
1382                         return -EINVAL;
1383
1384                 if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[6],
1385                                 ee->ee_ob[ee_mode][obdb], 3, 290, 0, true))
1386                         return -EINVAL;
1387         } else {
1388                 /* For 11a, Turbo and XR */
1389                 ee_mode = AR5K_EEPROM_MODE_11A;
1390                 obdb = channel->center_freq >= 5725 ? 3 :
1391                     (channel->center_freq >= 5500 ? 2 :
1392                         (channel->center_freq >= 5260 ? 1 :
1393                             (channel->center_freq > 4000 ? 0 : -1)));
1394
1395                 if (obdb == -1)
1396                         return -EINVAL;
1397
1398                 if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[6],
1399                                 ee->ee_ob[ee_mode][obdb], 3, 279, 0, true))
1400                         return -EINVAL;
1401
1402                 if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[6],
1403                                 ee->ee_ob[ee_mode][obdb], 3, 282, 0, true))
1404                         return -EINVAL;
1405         }
1406
1407         ath5k_hw_rfregs_op(rf, ah->ah_offset[6],
1408             ee->ee_x_gain[ee_mode], 2, 270, 0, true);
1409         ath5k_hw_rfregs_op(rf, ah->ah_offset[6],
1410             ee->ee_x_gain[ee_mode], 2, 257, 0, true);
1411
1412         if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[6],
1413                         ee->ee_xpd[ee_mode], 1, 302, 0, true))
1414                 return -EINVAL;
1415
1416         /* Modify bank 7 */
1417         if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[7],
1418                         ee->ee_i_gain[ee_mode], 6, 14, 0, true))
1419                 return -EINVAL;
1420
1421         /* Write RF values */
1422         for (i = 0; i < rf_size; i++)
1423                 ath5k_hw_reg_write(ah, rf[i], rf_ini[i].rf_register);
1424
1425         return 0;
1426 }
1427
1428 /*
1429  * Initialize RF5413/5414 and future chips
1430  * (until we come up with a better solution)
1431  */
1432 static int ath5k_hw_rf5413_rfregs(struct ath5k_hw *ah,
1433                 struct ieee80211_channel *channel, unsigned int mode)
1434 {
1435         const struct ath5k_ini_rf *rf_ini;
1436         u32 *rf;
1437         unsigned int rf_size, i;
1438         int bank = -1;
1439
1440         AR5K_ASSERT_ENTRY(mode, AR5K_MODE_MAX);
1441
1442         rf = ah->ah_rf_banks;
1443
1444         switch (ah->ah_radio) {
1445         case AR5K_RF5413:
1446                 rf_ini = rfregs_5413;
1447                 rf_size = ARRAY_SIZE(rfregs_5413);
1448                 break;
1449         case AR5K_RF2413:
1450                 rf_ini = rfregs_2413;
1451                 rf_size = ARRAY_SIZE(rfregs_2413);
1452
1453                 if (mode < 2) {
1454                         ATH5K_ERR(ah->ah_sc,
1455                                 "invalid channel mode: %i\n", mode);
1456                         return -EINVAL;
1457                 }
1458
1459                 mode = mode - 2;
1460                 break;
1461         case AR5K_RF2425:
1462                 rf_ini = rfregs_2425;
1463                 rf_size = ARRAY_SIZE(rfregs_2425);
1464
1465                 if (mode < 2) {
1466                         ATH5K_ERR(ah->ah_sc,
1467                                 "invalid channel mode: %i\n", mode);
1468                         return -EINVAL;
1469                 }
1470
1471                 /* Map b to g */
1472                 if (mode == 2)
1473                         mode = 0;
1474                 else
1475                         mode = mode - 3;
1476
1477                 break;
1478         default:
1479                 return -EINVAL;
1480         }
1481
1482         /* Copy values to modify them */
1483         for (i = 0; i < rf_size; i++) {
1484                 if (rf_ini[i].rf_bank >= AR5K_RF5112_INI_RF_MAX_BANKS) {
1485                         ATH5K_ERR(ah->ah_sc, "invalid bank\n");
1486                         return -EINVAL;
1487                 }
1488
1489                 if (bank != rf_ini[i].rf_bank) {
1490                         bank = rf_ini[i].rf_bank;
1491                         ah->ah_offset[bank] = i;
1492                 }
1493
1494                 rf[i] = rf_ini[i].rf_value[mode];
1495         }
1496
1497         /*
1498          * After compairing dumps from different cards
1499          * we get the same RF_BUFFER settings (diff returns
1500          * 0 lines). It seems that RF_BUFFER settings are static
1501          * and are written unmodified (no EEPROM stuff
1502          * is used because calibration data would be
1503          * different between different cards and would result
1504          * different RF_BUFFER settings)
1505          */
1506
1507         /* Write RF values */
1508         for (i = 0; i < rf_size; i++)
1509                 ath5k_hw_reg_write(ah, rf[i], rf_ini[i].rf_register);
1510
1511         return 0;
1512 }
1513
1514 /*
1515  * Initialize RF
1516  */
1517 int ath5k_hw_rfregs(struct ath5k_hw *ah, struct ieee80211_channel *channel,
1518                 unsigned int mode)
1519 {
1520         int (*func)(struct ath5k_hw *, struct ieee80211_channel *, unsigned int);
1521         int ret;
1522
1523         switch (ah->ah_radio) {
1524         case AR5K_RF5111:
1525                 ah->ah_rf_banks_size = sizeof(rfregs_5111);
1526                 func = ath5k_hw_rf5111_rfregs;
1527                 break;
1528         case AR5K_RF5112:
1529                 if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A)
1530                         ah->ah_rf_banks_size = sizeof(rfregs_5112a);
1531                 else
1532                         ah->ah_rf_banks_size = sizeof(rfregs_5112);
1533                 func = ath5k_hw_rf5112_rfregs;
1534                 break;
1535         case AR5K_RF5413:
1536                 ah->ah_rf_banks_size = sizeof(rfregs_5413);
1537                 func = ath5k_hw_rf5413_rfregs;
1538                 break;
1539         case AR5K_RF2413:
1540                 ah->ah_rf_banks_size = sizeof(rfregs_2413);
1541                 func = ath5k_hw_rf5413_rfregs;
1542                 break;
1543         case AR5K_RF2425:
1544                 ah->ah_rf_banks_size = sizeof(rfregs_2425);
1545                 func = ath5k_hw_rf5413_rfregs;
1546                 break;
1547         default:
1548                 return -EINVAL;
1549         }
1550
1551         if (ah->ah_rf_banks == NULL) {
1552                 /* XXX do extra checks? */
1553                 ah->ah_rf_banks = kmalloc(ah->ah_rf_banks_size, GFP_KERNEL);
1554                 if (ah->ah_rf_banks == NULL) {
1555                         ATH5K_ERR(ah->ah_sc, "out of memory\n");
1556                         return -ENOMEM;
1557                 }
1558         }
1559
1560         ret = func(ah, channel, mode);
1561         if (!ret)
1562                 ah->ah_rf_gain = AR5K_RFGAIN_INACTIVE;
1563
1564         return ret;
1565 }
1566
1567 int ath5k_hw_rfgain(struct ath5k_hw *ah, unsigned int freq)
1568 {
1569         const struct ath5k_ini_rfgain *ath5k_rfg;
1570         unsigned int i, size;
1571
1572         switch (ah->ah_radio) {
1573         case AR5K_RF5111:
1574                 ath5k_rfg = rfgain_5111;
1575                 size = ARRAY_SIZE(rfgain_5111);
1576                 break;
1577         case AR5K_RF5112:
1578                 ath5k_rfg = rfgain_5112;
1579                 size = ARRAY_SIZE(rfgain_5112);
1580                 break;
1581         case AR5K_RF5413:
1582                 ath5k_rfg = rfgain_5413;
1583                 size = ARRAY_SIZE(rfgain_5413);
1584                 break;
1585         case AR5K_RF2413:
1586                 ath5k_rfg = rfgain_2413;
1587                 size = ARRAY_SIZE(rfgain_2413);
1588                 freq = 0; /* only 2Ghz */
1589                 break;
1590         case AR5K_RF2425:
1591                 ath5k_rfg = rfgain_2413;
1592                 size = ARRAY_SIZE(rfgain_2413);
1593                 freq = 0; /* only 2Ghz */
1594                 break;
1595         default:
1596                 return -EINVAL;
1597         }
1598
1599         switch (freq) {
1600         case AR5K_INI_RFGAIN_2GHZ:
1601         case AR5K_INI_RFGAIN_5GHZ:
1602                 break;
1603         default:
1604                 return -EINVAL;
1605         }
1606
1607         for (i = 0; i < size; i++) {
1608                 AR5K_REG_WAIT(i);
1609                 ath5k_hw_reg_write(ah, ath5k_rfg[i].rfg_value[freq],
1610                         (u32)ath5k_rfg[i].rfg_register);
1611         }
1612
1613         return 0;
1614 }
1615
1616 enum ath5k_rfgain ath5k_hw_get_rf_gain(struct ath5k_hw *ah)
1617 {
1618         u32 data, type;
1619
1620         ATH5K_TRACE(ah->ah_sc);
1621
1622         if (ah->ah_rf_banks == NULL || !ah->ah_gain.g_active ||
1623                         ah->ah_version <= AR5K_AR5211)
1624                 return AR5K_RFGAIN_INACTIVE;
1625
1626         if (ah->ah_rf_gain != AR5K_RFGAIN_READ_REQUESTED)
1627                 goto done;
1628
1629         data = ath5k_hw_reg_read(ah, AR5K_PHY_PAPD_PROBE);
1630
1631         if (!(data & AR5K_PHY_PAPD_PROBE_TX_NEXT)) {
1632                 ah->ah_gain.g_current = data >> AR5K_PHY_PAPD_PROBE_GAINF_S;
1633                 type = AR5K_REG_MS(data, AR5K_PHY_PAPD_PROBE_TYPE);
1634
1635                 if (type == AR5K_PHY_PAPD_PROBE_TYPE_CCK)
1636                         ah->ah_gain.g_current += AR5K_GAIN_CCK_PROBE_CORR;
1637
1638                 if (ah->ah_radio >= AR5K_RF5112) {
1639                         ath5k_hw_rfregs_gainf_corr(ah);
1640                         ah->ah_gain.g_current =
1641                                 ah->ah_gain.g_current>=ah->ah_gain.g_f_corr ?
1642                                 (ah->ah_gain.g_current-ah->ah_gain.g_f_corr) :
1643                                 0;
1644                 }
1645
1646                 if (ath5k_hw_rfregs_gain_readback(ah) &&
1647                                 AR5K_GAIN_CHECK_ADJUST(&ah->ah_gain) &&
1648                                 ath5k_hw_rfregs_gain_adjust(ah))
1649                         ah->ah_rf_gain = AR5K_RFGAIN_NEED_CHANGE;
1650         }
1651
1652 done:
1653         return ah->ah_rf_gain;
1654 }
1655
1656 int ath5k_hw_set_rfgain_opt(struct ath5k_hw *ah)
1657 {
1658         /* Initialize the gain optimization values */
1659         switch (ah->ah_radio) {
1660         case AR5K_RF5111:
1661                 ah->ah_gain.g_step_idx = rfgain_opt_5111.go_default;
1662                 ah->ah_gain.g_step =
1663                     &rfgain_opt_5111.go_step[ah->ah_gain.g_step_idx];
1664                 ah->ah_gain.g_low = 20;
1665                 ah->ah_gain.g_high = 35;
1666                 ah->ah_gain.g_active = 1;
1667                 break;
1668         case AR5K_RF5112:
1669                 ah->ah_gain.g_step_idx = rfgain_opt_5112.go_default;
1670                 ah->ah_gain.g_step =
1671                     &rfgain_opt_5112.go_step[ah->ah_gain.g_step_idx];
1672                 ah->ah_gain.g_low = 20;
1673                 ah->ah_gain.g_high = 85;
1674                 ah->ah_gain.g_active = 1;
1675                 break;
1676         default:
1677                 return -EINVAL;
1678         }
1679
1680         return 0;
1681 }
1682
1683 /**************************\
1684   PHY/RF channel functions
1685 \**************************/
1686
1687 /*
1688  * Check if a channel is supported
1689  */
1690 bool ath5k_channel_ok(struct ath5k_hw *ah, u16 freq, unsigned int flags)
1691 {
1692         /* Check if the channel is in our supported range */
1693         if (flags & CHANNEL_2GHZ) {
1694                 if ((freq >= ah->ah_capabilities.cap_range.range_2ghz_min) &&
1695                     (freq <= ah->ah_capabilities.cap_range.range_2ghz_max))
1696                         return true;
1697         } else if (flags & CHANNEL_5GHZ)
1698                 if ((freq >= ah->ah_capabilities.cap_range.range_5ghz_min) &&
1699                     (freq <= ah->ah_capabilities.cap_range.range_5ghz_max))
1700                         return true;
1701
1702         return false;
1703 }
1704
1705 /*
1706  * Convertion needed for RF5110
1707  */
1708 static u32 ath5k_hw_rf5110_chan2athchan(struct ieee80211_channel *channel)
1709 {
1710         u32 athchan;
1711
1712         /*
1713          * Convert IEEE channel/MHz to an internal channel value used
1714          * by the AR5210 chipset. This has not been verified with
1715          * newer chipsets like the AR5212A who have a completely
1716          * different RF/PHY part.
1717          */
1718         athchan = (ath5k_hw_bitswap(
1719                         (ieee80211_frequency_to_channel(
1720                                 channel->center_freq) - 24) / 2, 5)
1721                                 << 1) | (1 << 6) | 0x1;
1722         return athchan;
1723 }
1724
1725 /*
1726  * Set channel on RF5110
1727  */
1728 static int ath5k_hw_rf5110_channel(struct ath5k_hw *ah,
1729                 struct ieee80211_channel *channel)
1730 {
1731         u32 data;
1732
1733         /*
1734          * Set the channel and wait
1735          */
1736         data = ath5k_hw_rf5110_chan2athchan(channel);
1737         ath5k_hw_reg_write(ah, data, AR5K_RF_BUFFER);
1738         ath5k_hw_reg_write(ah, 0, AR5K_RF_BUFFER_CONTROL_0);
1739         mdelay(1);
1740
1741         return 0;
1742 }
1743
1744 /*
1745  * Convertion needed for 5111
1746  */
1747 static int ath5k_hw_rf5111_chan2athchan(unsigned int ieee,
1748                 struct ath5k_athchan_2ghz *athchan)
1749 {
1750         int channel;
1751
1752         /* Cast this value to catch negative channel numbers (>= -19) */
1753         channel = (int)ieee;
1754
1755         /*
1756          * Map 2GHz IEEE channel to 5GHz Atheros channel
1757          */
1758         if (channel <= 13) {
1759                 athchan->a2_athchan = 115 + channel;
1760                 athchan->a2_flags = 0x46;
1761         } else if (channel == 14) {
1762                 athchan->a2_athchan = 124;
1763                 athchan->a2_flags = 0x44;
1764         } else if (channel >= 15 && channel <= 26) {
1765                 athchan->a2_athchan = ((channel - 14) * 4) + 132;
1766                 athchan->a2_flags = 0x46;
1767         } else
1768                 return -EINVAL;
1769
1770         return 0;
1771 }
1772
1773 /*
1774  * Set channel on 5111
1775  */
1776 static int ath5k_hw_rf5111_channel(struct ath5k_hw *ah,
1777                 struct ieee80211_channel *channel)
1778 {
1779         struct ath5k_athchan_2ghz ath5k_channel_2ghz;
1780         unsigned int ath5k_channel =
1781                 ieee80211_frequency_to_channel(channel->center_freq);
1782         u32 data0, data1, clock;
1783         int ret;
1784
1785         /*
1786          * Set the channel on the RF5111 radio
1787          */
1788         data0 = data1 = 0;
1789
1790         if (channel->hw_value & CHANNEL_2GHZ) {
1791                 /* Map 2GHz channel to 5GHz Atheros channel ID */
1792                 ret = ath5k_hw_rf5111_chan2athchan(
1793                         ieee80211_frequency_to_channel(channel->center_freq),
1794                         &ath5k_channel_2ghz);
1795                 if (ret)
1796                         return ret;
1797
1798                 ath5k_channel = ath5k_channel_2ghz.a2_athchan;
1799                 data0 = ((ath5k_hw_bitswap(ath5k_channel_2ghz.a2_flags, 8) & 0xff)
1800                     << 5) | (1 << 4);
1801         }
1802
1803         if (ath5k_channel < 145 || !(ath5k_channel & 1)) {
1804                 clock = 1;
1805                 data1 = ((ath5k_hw_bitswap(ath5k_channel - 24, 8) & 0xff) << 2) |
1806                         (clock << 1) | (1 << 10) | 1;
1807         } else {
1808                 clock = 0;
1809                 data1 = ((ath5k_hw_bitswap((ath5k_channel - 24) / 2, 8) & 0xff)
1810                         << 2) | (clock << 1) | (1 << 10) | 1;
1811         }
1812
1813         ath5k_hw_reg_write(ah, (data1 & 0xff) | ((data0 & 0xff) << 8),
1814                         AR5K_RF_BUFFER);
1815         ath5k_hw_reg_write(ah, ((data1 >> 8) & 0xff) | (data0 & 0xff00),
1816                         AR5K_RF_BUFFER_CONTROL_3);
1817
1818         return 0;
1819 }
1820
1821 /*
1822  * Set channel on 5112 and newer
1823  */
1824 static int ath5k_hw_rf5112_channel(struct ath5k_hw *ah,
1825                 struct ieee80211_channel *channel)
1826 {
1827         u32 data, data0, data1, data2;
1828         u16 c;
1829
1830         data = data0 = data1 = data2 = 0;
1831         c = channel->center_freq;
1832
1833         /*
1834          * Set the channel on the RF5112 or newer
1835          */
1836         if (c < 4800) {
1837                 if (!((c - 2224) % 5)) {
1838                         data0 = ((2 * (c - 704)) - 3040) / 10;
1839                         data1 = 1;
1840                 } else if (!((c - 2192) % 5)) {
1841                         data0 = ((2 * (c - 672)) - 3040) / 10;
1842                         data1 = 0;
1843                 } else
1844                         return -EINVAL;
1845
1846                 data0 = ath5k_hw_bitswap((data0 << 2) & 0xff, 8);
1847         } else {
1848                 if (!(c % 20) && c >= 5120) {
1849                         data0 = ath5k_hw_bitswap(((c - 4800) / 20 << 2), 8);
1850                         data2 = ath5k_hw_bitswap(3, 2);
1851                 } else if (!(c % 10)) {
1852                         data0 = ath5k_hw_bitswap(((c - 4800) / 10 << 1), 8);
1853                         data2 = ath5k_hw_bitswap(2, 2);
1854                 } else if (!(c % 5)) {
1855                         data0 = ath5k_hw_bitswap((c - 4800) / 5, 8);
1856                         data2 = ath5k_hw_bitswap(1, 2);
1857                 } else
1858                         return -EINVAL;
1859         }
1860
1861         data = (data0 << 4) | (data1 << 1) | (data2 << 2) | 0x1001;
1862
1863         ath5k_hw_reg_write(ah, data & 0xff, AR5K_RF_BUFFER);
1864         ath5k_hw_reg_write(ah, (data >> 8) & 0x7f, AR5K_RF_BUFFER_CONTROL_5);
1865
1866         return 0;
1867 }
1868
1869 /*
1870  * Set a channel on the radio chip
1871  */
1872 int ath5k_hw_channel(struct ath5k_hw *ah, struct ieee80211_channel *channel)
1873 {
1874         int ret;
1875         /*
1876          * Check bounds supported by the PHY (we don't care about regultory
1877          * restrictions at this point). Note: hw_value already has the band
1878          * (CHANNEL_2GHZ, or CHANNEL_5GHZ) so we inform ath5k_channel_ok()
1879          * of the band by that */
1880         if (!ath5k_channel_ok(ah, channel->center_freq, channel->hw_value)) {
1881                 ATH5K_ERR(ah->ah_sc,
1882                         "channel frequency (%u MHz) out of supported "
1883                         "band range\n",
1884                         channel->center_freq);
1885                         return -EINVAL;
1886         }
1887
1888         /*
1889          * Set the channel and wait
1890          */
1891         switch (ah->ah_radio) {
1892         case AR5K_RF5110:
1893                 ret = ath5k_hw_rf5110_channel(ah, channel);
1894                 break;
1895         case AR5K_RF5111:
1896                 ret = ath5k_hw_rf5111_channel(ah, channel);
1897                 break;
1898         default:
1899                 ret = ath5k_hw_rf5112_channel(ah, channel);
1900                 break;
1901         }
1902
1903         if (ret)
1904                 return ret;
1905
1906         ah->ah_current_channel.center_freq = channel->center_freq;
1907         ah->ah_current_channel.hw_value = channel->hw_value;
1908         ah->ah_turbo = channel->hw_value == CHANNEL_T ? true : false;
1909
1910         return 0;
1911 }
1912
1913 /*****************\
1914   PHY calibration
1915 \*****************/
1916
1917 /**
1918  * ath5k_hw_noise_floor_calibration - perform PHY noise floor calibration
1919  *
1920  * @ah: struct ath5k_hw pointer we are operating on
1921  * @freq: the channel frequency, just used for error logging
1922  *
1923  * This function performs a noise floor calibration of the PHY and waits for
1924  * it to complete. Then the noise floor value is compared to some maximum
1925  * noise floor we consider valid.
1926  *
1927  * Note that this is different from what the madwifi HAL does: it reads the
1928  * noise floor and afterwards initiates the calibration. Since the noise floor
1929  * calibration can take some time to finish, depending on the current channel
1930  * use, that avoids the occasional timeout warnings we are seeing now.
1931  *
1932  * See the following link for an Atheros patent on noise floor calibration:
1933  * http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL \
1934  * &p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=7245893.PN.&OS=PN/7
1935  *
1936  */
1937 int
1938 ath5k_hw_noise_floor_calibration(struct ath5k_hw *ah, short freq)
1939 {
1940         int ret;
1941         unsigned int i;
1942         s32 noise_floor;
1943
1944         /*
1945          * Enable noise floor calibration and wait until completion
1946          */
1947         AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL,
1948                                 AR5K_PHY_AGCCTL_NF);
1949
1950         ret = ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL,
1951                         AR5K_PHY_AGCCTL_NF, 0, false);
1952         if (ret) {
1953                 ATH5K_ERR(ah->ah_sc,
1954                         "noise floor calibration timeout (%uMHz)\n", freq);
1955                 return ret;
1956         }
1957
1958         /* Wait until the noise floor is calibrated and read the value */
1959         for (i = 20; i > 0; i--) {
1960                 mdelay(1);
1961                 noise_floor = ath5k_hw_reg_read(ah, AR5K_PHY_NF);
1962                 noise_floor = AR5K_PHY_NF_RVAL(noise_floor);
1963                 if (noise_floor & AR5K_PHY_NF_ACTIVE) {
1964                         noise_floor = AR5K_PHY_NF_AVAL(noise_floor);
1965
1966                         if (noise_floor <= AR5K_TUNE_NOISE_FLOOR)
1967                                 break;
1968                 }
1969         }
1970
1971         ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_CALIBRATE,
1972                 "noise floor %d\n", noise_floor);
1973
1974         if (noise_floor > AR5K_TUNE_NOISE_FLOOR) {
1975                 ATH5K_ERR(ah->ah_sc,
1976                         "noise floor calibration failed (%uMHz)\n", freq);
1977                 return -EIO;
1978         }
1979
1980         ah->ah_noise_floor = noise_floor;
1981
1982         return 0;
1983 }
1984
1985 /*
1986  * Perform a PHY calibration on RF5110
1987  * -Fix BPSK/QAM Constellation (I/Q correction)
1988  * -Calculate Noise Floor
1989  */
1990 static int ath5k_hw_rf5110_calibrate(struct ath5k_hw *ah,
1991                 struct ieee80211_channel *channel)
1992 {
1993         u32 phy_sig, phy_agc, phy_sat, beacon;
1994         int ret;
1995
1996         /*
1997          * Disable beacons and RX/TX queues, wait
1998          */
1999         AR5K_REG_ENABLE_BITS(ah, AR5K_DIAG_SW_5210,
2000                 AR5K_DIAG_SW_DIS_TX | AR5K_DIAG_SW_DIS_RX_5210);
2001         beacon = ath5k_hw_reg_read(ah, AR5K_BEACON_5210);
2002         ath5k_hw_reg_write(ah, beacon & ~AR5K_BEACON_ENABLE, AR5K_BEACON_5210);
2003
2004         udelay(2300);
2005
2006         /*
2007          * Set the channel (with AGC turned off)
2008          */
2009         AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE);
2010         udelay(10);
2011         ret = ath5k_hw_channel(ah, channel);
2012
2013         /*
2014          * Activate PHY and wait
2015          */
2016         ath5k_hw_reg_write(ah, AR5K_PHY_ACT_ENABLE, AR5K_PHY_ACT);
2017         mdelay(1);
2018
2019         AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE);
2020
2021         if (ret)
2022                 return ret;
2023
2024         /*
2025          * Calibrate the radio chip
2026          */
2027
2028         /* Remember normal state */
2029         phy_sig = ath5k_hw_reg_read(ah, AR5K_PHY_SIG);
2030         phy_agc = ath5k_hw_reg_read(ah, AR5K_PHY_AGCCOARSE);
2031         phy_sat = ath5k_hw_reg_read(ah, AR5K_PHY_ADCSAT);
2032
2033         /* Update radio registers */
2034         ath5k_hw_reg_write(ah, (phy_sig & ~(AR5K_PHY_SIG_FIRPWR)) |
2035                 AR5K_REG_SM(-1, AR5K_PHY_SIG_FIRPWR), AR5K_PHY_SIG);
2036
2037         ath5k_hw_reg_write(ah, (phy_agc & ~(AR5K_PHY_AGCCOARSE_HI |
2038                         AR5K_PHY_AGCCOARSE_LO)) |
2039                 AR5K_REG_SM(-1, AR5K_PHY_AGCCOARSE_HI) |
2040                 AR5K_REG_SM(-127, AR5K_PHY_AGCCOARSE_LO), AR5K_PHY_AGCCOARSE);
2041
2042         ath5k_hw_reg_write(ah, (phy_sat & ~(AR5K_PHY_ADCSAT_ICNT |
2043                         AR5K_PHY_ADCSAT_THR)) |
2044                 AR5K_REG_SM(2, AR5K_PHY_ADCSAT_ICNT) |
2045                 AR5K_REG_SM(12, AR5K_PHY_ADCSAT_THR), AR5K_PHY_ADCSAT);
2046
2047         udelay(20);
2048
2049         AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE);
2050         udelay(10);
2051         ath5k_hw_reg_write(ah, AR5K_PHY_RFSTG_DISABLE, AR5K_PHY_RFSTG);
2052         AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE);
2053
2054         mdelay(1);
2055
2056         /*
2057          * Enable calibration and wait until completion
2058          */
2059         AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL, AR5K_PHY_AGCCTL_CAL);
2060
2061         ret = ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL,
2062                         AR5K_PHY_AGCCTL_CAL, 0, false);
2063
2064         /* Reset to normal state */
2065         ath5k_hw_reg_write(ah, phy_sig, AR5K_PHY_SIG);
2066         ath5k_hw_reg_write(ah, phy_agc, AR5K_PHY_AGCCOARSE);
2067         ath5k_hw_reg_write(ah, phy_sat, AR5K_PHY_ADCSAT);
2068
2069         if (ret) {
2070                 ATH5K_ERR(ah->ah_sc, "calibration timeout (%uMHz)\n",
2071                                 channel->center_freq);
2072                 return ret;
2073         }
2074
2075         ret = ath5k_hw_noise_floor_calibration(ah, channel->center_freq);
2076         if (ret)
2077                 return ret;
2078
2079         /*
2080          * Re-enable RX/TX and beacons
2081          */
2082         AR5K_REG_DISABLE_BITS(ah, AR5K_DIAG_SW_5210,
2083                 AR5K_DIAG_SW_DIS_TX | AR5K_DIAG_SW_DIS_RX_5210);
2084         ath5k_hw_reg_write(ah, beacon, AR5K_BEACON_5210);
2085
2086         return 0;
2087 }
2088
2089 /*
2090  * Perform a PHY calibration on RF5111/5112
2091  */
2092 static int ath5k_hw_rf511x_calibrate(struct ath5k_hw *ah,
2093                 struct ieee80211_channel *channel)
2094 {
2095         u32 i_pwr, q_pwr;
2096         s32 iq_corr, i_coff, i_coffd, q_coff, q_coffd;
2097         ATH5K_TRACE(ah->ah_sc);
2098
2099         if (!ah->ah_calibration ||
2100                         ath5k_hw_reg_read(ah, AR5K_PHY_IQ) & AR5K_PHY_IQ_RUN)
2101                 goto done;
2102
2103         ah->ah_calibration = false;
2104
2105         iq_corr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_CORR);
2106         i_pwr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_PWR_I);
2107         q_pwr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_PWR_Q);
2108         i_coffd = ((i_pwr >> 1) + (q_pwr >> 1)) >> 7;
2109         q_coffd = q_pwr >> 6;
2110
2111         if (i_coffd == 0 || q_coffd == 0)
2112                 goto done;
2113
2114         i_coff = ((-iq_corr) / i_coffd) & 0x3f;
2115         q_coff = (((s32)i_pwr / q_coffd) - 64) & 0x1f;
2116
2117         /* Commit new IQ value */
2118         AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_ENABLE |
2119                 ((u32)q_coff) | ((u32)i_coff << AR5K_PHY_IQ_CORR_Q_I_COFF_S));
2120
2121 done:
2122         ath5k_hw_noise_floor_calibration(ah, channel->center_freq);
2123
2124         /* Request RF gain */
2125         if (channel->hw_value & CHANNEL_5GHZ) {
2126                 ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txpower.txp_max,
2127                         AR5K_PHY_PAPD_PROBE_TXPOWER) |
2128                         AR5K_PHY_PAPD_PROBE_TX_NEXT, AR5K_PHY_PAPD_PROBE);
2129                 ah->ah_rf_gain = AR5K_RFGAIN_READ_REQUESTED;
2130         }
2131
2132         return 0;
2133 }
2134
2135 /*
2136  * Perform a PHY calibration
2137  */
2138 int ath5k_hw_phy_calibrate(struct ath5k_hw *ah,
2139                 struct ieee80211_channel *channel)
2140 {
2141         int ret;
2142
2143         if (ah->ah_radio == AR5K_RF5110)
2144                 ret = ath5k_hw_rf5110_calibrate(ah, channel);
2145         else
2146                 ret = ath5k_hw_rf511x_calibrate(ah, channel);
2147
2148         return ret;
2149 }
2150
2151 int ath5k_hw_phy_disable(struct ath5k_hw *ah)
2152 {
2153         ATH5K_TRACE(ah->ah_sc);
2154         /*Just a try M.F.*/
2155         ath5k_hw_reg_write(ah, AR5K_PHY_ACT_DISABLE, AR5K_PHY_ACT);
2156
2157         return 0;
2158 }
2159
2160 /********************\
2161   Misc PHY functions
2162 \********************/
2163
2164 /*
2165  * Get the PHY Chip revision
2166  */
2167 u16 ath5k_hw_radio_revision(struct ath5k_hw *ah, unsigned int chan)
2168 {
2169         unsigned int i;
2170         u32 srev;
2171         u16 ret;
2172
2173         ATH5K_TRACE(ah->ah_sc);
2174
2175         /*
2176          * Set the radio chip access register
2177          */
2178         switch (chan) {
2179         case CHANNEL_2GHZ:
2180                 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_2GHZ, AR5K_PHY(0));
2181                 break;
2182         case CHANNEL_5GHZ:
2183                 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0));
2184                 break;
2185         default:
2186                 return 0;
2187         }
2188
2189         mdelay(2);
2190
2191         /* ...wait until PHY is ready and read the selected radio revision */
2192         ath5k_hw_reg_write(ah, 0x00001c16, AR5K_PHY(0x34));
2193
2194         for (i = 0; i < 8; i++)
2195                 ath5k_hw_reg_write(ah, 0x00010000, AR5K_PHY(0x20));
2196
2197         if (ah->ah_version == AR5K_AR5210) {
2198                 srev = ath5k_hw_reg_read(ah, AR5K_PHY(256) >> 28) & 0xf;
2199                 ret = (u16)ath5k_hw_bitswap(srev, 4) + 1;
2200         } else {
2201                 srev = (ath5k_hw_reg_read(ah, AR5K_PHY(0x100)) >> 24) & 0xff;
2202                 ret = (u16)ath5k_hw_bitswap(((srev & 0xf0) >> 4) |
2203                                 ((srev & 0x0f) << 4), 8);
2204         }
2205
2206         /* Reset to the 5GHz mode */
2207         ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0));
2208
2209         return ret;
2210 }
2211
2212 void /*TODO:Boundary check*/
2213 ath5k_hw_set_def_antenna(struct ath5k_hw *ah, unsigned int ant)
2214 {
2215         ATH5K_TRACE(ah->ah_sc);
2216         /*Just a try M.F.*/
2217         if (ah->ah_version != AR5K_AR5210)
2218                 ath5k_hw_reg_write(ah, ant, AR5K_DEFAULT_ANTENNA);
2219 }
2220
2221 unsigned int ath5k_hw_get_def_antenna(struct ath5k_hw *ah)
2222 {
2223         ATH5K_TRACE(ah->ah_sc);
2224         /*Just a try M.F.*/
2225         if (ah->ah_version != AR5K_AR5210)
2226                 return ath5k_hw_reg_read(ah, AR5K_DEFAULT_ANTENNA);
2227
2228         return false; /*XXX: What do we return for 5210 ?*/
2229 }
2230
2231 /*
2232  * TX power setup
2233  */
2234
2235 /*
2236  * Initialize the tx power table (not fully implemented)
2237  */
2238 static void ath5k_txpower_table(struct ath5k_hw *ah,
2239                 struct ieee80211_channel *channel, s16 max_power)
2240 {
2241         unsigned int i, min, max, n;
2242         u16 txpower, *rates;
2243
2244         rates = ah->ah_txpower.txp_rates;
2245
2246         txpower = AR5K_TUNE_DEFAULT_TXPOWER * 2;
2247         if (max_power > txpower)
2248                 txpower = max_power > AR5K_TUNE_MAX_TXPOWER ?
2249                     AR5K_TUNE_MAX_TXPOWER : max_power;
2250
2251         for (i = 0; i < AR5K_MAX_RATES; i++)
2252                 rates[i] = txpower;
2253
2254         /* XXX setup target powers by rate */
2255
2256         ah->ah_txpower.txp_min = rates[7];
2257         ah->ah_txpower.txp_max = rates[0];
2258         ah->ah_txpower.txp_ofdm = rates[0];
2259
2260         /* Calculate the power table */
2261         n = ARRAY_SIZE(ah->ah_txpower.txp_pcdac);
2262         min = AR5K_EEPROM_PCDAC_START;
2263         max = AR5K_EEPROM_PCDAC_STOP;
2264         for (i = 0; i < n; i += AR5K_EEPROM_PCDAC_STEP)
2265                 ah->ah_txpower.txp_pcdac[i] =
2266 #ifdef notyet
2267                 min + ((i * (max - min)) / n);
2268 #else
2269                 min;
2270 #endif
2271 }
2272
2273 /*
2274  * Set transmition power
2275  */
2276 int /*O.K. - txpower_table is unimplemented so this doesn't work*/
2277 ath5k_hw_txpower(struct ath5k_hw *ah, struct ieee80211_channel *channel,
2278                 unsigned int txpower)
2279 {
2280         bool tpc = ah->ah_txpower.txp_tpc;
2281         unsigned int i;
2282
2283         ATH5K_TRACE(ah->ah_sc);
2284         if (txpower > AR5K_TUNE_MAX_TXPOWER) {
2285                 ATH5K_ERR(ah->ah_sc, "invalid tx power: %u\n", txpower);
2286                 return -EINVAL;
2287         }
2288
2289         /*
2290          * RF2413 for some reason can't
2291          * transmit anything if we call
2292          * this funtion, so we skip it
2293          * until we fix txpower.
2294          *
2295          * XXX: Assume same for RF2425
2296          * to be safe.
2297          */
2298         if ((ah->ah_radio == AR5K_RF2413) || (ah->ah_radio == AR5K_RF2425))
2299                 return 0;
2300
2301         /* Reset TX power values */
2302         memset(&ah->ah_txpower, 0, sizeof(ah->ah_txpower));
2303         ah->ah_txpower.txp_tpc = tpc;
2304
2305         /* Initialize TX power table */
2306         ath5k_txpower_table(ah, channel, txpower);
2307
2308         /*
2309          * Write TX power values
2310          */
2311         for (i = 0; i < (AR5K_EEPROM_POWER_TABLE_SIZE / 2); i++) {
2312                 ath5k_hw_reg_write(ah,
2313                         ((((ah->ah_txpower.txp_pcdac[(i << 1) + 1] << 8) | 0xff) & 0xffff) << 16) |
2314                         (((ah->ah_txpower.txp_pcdac[(i << 1)    ] << 8) | 0xff) & 0xffff),
2315                         AR5K_PHY_PCDAC_TXPOWER(i));
2316         }
2317
2318         ath5k_hw_reg_write(ah, AR5K_TXPOWER_OFDM(3, 24) |
2319                 AR5K_TXPOWER_OFDM(2, 16) | AR5K_TXPOWER_OFDM(1, 8) |
2320                 AR5K_TXPOWER_OFDM(0, 0), AR5K_PHY_TXPOWER_RATE1);
2321
2322         ath5k_hw_reg_write(ah, AR5K_TXPOWER_OFDM(7, 24) |
2323                 AR5K_TXPOWER_OFDM(6, 16) | AR5K_TXPOWER_OFDM(5, 8) |
2324                 AR5K_TXPOWER_OFDM(4, 0), AR5K_PHY_TXPOWER_RATE2);
2325
2326         ath5k_hw_reg_write(ah, AR5K_TXPOWER_CCK(10, 24) |
2327                 AR5K_TXPOWER_CCK(9, 16) | AR5K_TXPOWER_CCK(15, 8) |
2328                 AR5K_TXPOWER_CCK(8, 0), AR5K_PHY_TXPOWER_RATE3);
2329
2330         ath5k_hw_reg_write(ah, AR5K_TXPOWER_CCK(14, 24) |
2331                 AR5K_TXPOWER_CCK(13, 16) | AR5K_TXPOWER_CCK(12, 8) |
2332                 AR5K_TXPOWER_CCK(11, 0), AR5K_PHY_TXPOWER_RATE4);
2333
2334         if (ah->ah_txpower.txp_tpc)
2335                 ath5k_hw_reg_write(ah, AR5K_PHY_TXPOWER_RATE_MAX_TPC_ENABLE |
2336                         AR5K_TUNE_MAX_TXPOWER, AR5K_PHY_TXPOWER_RATE_MAX);
2337         else
2338                 ath5k_hw_reg_write(ah, AR5K_PHY_TXPOWER_RATE_MAX |
2339                         AR5K_TUNE_MAX_TXPOWER, AR5K_PHY_TXPOWER_RATE_MAX);
2340
2341         return 0;
2342 }
2343
2344 int ath5k_hw_set_txpower_limit(struct ath5k_hw *ah, unsigned int power)
2345 {
2346         /*Just a try M.F.*/
2347         struct ieee80211_channel *channel = &ah->ah_current_channel;
2348
2349         ATH5K_TRACE(ah->ah_sc);
2350         ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_TXPOWER,
2351                 "changing txpower to %d\n", power);
2352
2353         return ath5k_hw_txpower(ah, channel, power);
2354 }