2 * Copyright (c) 2008 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 #include <linux/version.h>
21 #include <linux/autoconf.h>
22 #include <linux/kernel.h>
23 #include <linux/module.h>
24 #include <linux/spinlock.h>
25 #include <linux/errno.h>
26 #include <linux/skbuff.h>
27 #include <linux/netdevice.h>
28 #include <linux/etherdevice.h>
30 #include <linux/tcp.h>
32 #include <linux/delay.h>
33 #include <linux/wait.h>
34 #include <linux/pci.h>
35 #include <linux/interrupt.h>
36 #include <linux/sched.h>
37 #include <linux/list.h>
38 #include <asm/byteorder.h>
39 #include <linux/scatterlist.h>
41 #include <net/mac80211.h>
42 #include <linux/leds.h>
43 #include <linux/rfkill.h>
50 /* Macro to expand scalars to 64-bit objects */
52 #define ito64(x) (sizeof(x) == 8) ? \
53 (((unsigned long long int)(x)) & (0xff)) : \
55 (((unsigned long long int)(x)) & 0xffff) : \
56 ((sizeof(x) == 32) ? \
57 (((unsigned long long int)(x)) & 0xffffffff) : \
58 (unsigned long long int)(x))
60 /* increment with wrap-around */
61 #define INCR(_l, _sz) do { \
63 (_l) &= ((_sz) - 1); \
66 /* decrement with wrap-around */
67 #define DECR(_l, _sz) do { \
69 (_l) &= ((_sz) - 1); \
72 #define A_MAX(a, b) ((a) > (b) ? (a) : (b))
74 #define ASSERT(exp) do { \
75 if (unlikely(!(exp))) { \
80 #define TSF_TO_TU(_h,_l) \
81 ((((u32)(_h)) << 22) | (((u32)(_l)) >> 10))
83 #define ATH_TXQ_SETUP(sc, i) ((sc)->sc_txqsetup & (1<<i))
85 static const u8 ath_bcast_mac[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
88 ATH_DBG_RESET = 0x00000001,
89 ATH_DBG_REG_IO = 0x00000002,
90 ATH_DBG_QUEUE = 0x00000004,
91 ATH_DBG_EEPROM = 0x00000008,
92 ATH_DBG_CALIBRATE = 0x00000010,
93 ATH_DBG_CHANNEL = 0x00000020,
94 ATH_DBG_INTERRUPT = 0x00000040,
95 ATH_DBG_REGULATORY = 0x00000080,
96 ATH_DBG_ANI = 0x00000100,
97 ATH_DBG_POWER_MGMT = 0x00000200,
98 ATH_DBG_XMIT = 0x00000400,
99 ATH_DBG_BEACON = 0x00001000,
100 ATH_DBG_CONFIG = 0x00002000,
101 ATH_DBG_KEYCACHE = 0x00004000,
102 ATH_DBG_FATAL = 0x00008000,
103 ATH_DBG_ANY = 0xffffffff
106 #define DBG_DEFAULT (ATH_DBG_FATAL)
108 #ifdef CONFIG_ATH9K_DEBUG
110 void DPRINTF(struct ath_softc *sc, int dbg_mask, const char *fmt, ...);
111 void ath9k_init_debug(struct ath_softc *sc);
115 static inline void DPRINTF(struct ath_softc *sc, int dbg_mask,
116 const char *fmt, ...)
120 static inline ath9k_init_debug(struct ath_softc *sc)
129 u16 txpowlimit_override;
134 /*************************/
135 /* Descriptor Management */
136 /*************************/
138 #define ATH_TXBUF_RESET(_bf) do { \
139 (_bf)->bf_status = 0; \
140 (_bf)->bf_lastbf = NULL; \
141 (_bf)->bf_lastfrm = NULL; \
142 (_bf)->bf_next = NULL; \
143 memset(&((_bf)->bf_state), 0, \
144 sizeof(struct ath_buf_state)); \
154 BUF_SHORT_PREAMBLE = BIT(6),
157 BUF_AGGR_BURST = BIT(9),
158 BUF_CALC_AIRTIME = BIT(10),
161 struct ath_buf_state {
162 int bfs_nframes; /* # frames in aggregate */
163 u16 bfs_al; /* length of aggregate */
164 u16 bfs_frmlen; /* length of frame */
165 int bfs_seqno; /* sequence number */
166 int bfs_tidno; /* tid of this frame */
167 int bfs_retries; /* current retries */
168 u32 bf_type; /* BUF_* (enum buffer_type) */
170 enum ath9k_key_type bfs_keytype;
173 #define bf_nframes bf_state.bfs_nframes
174 #define bf_al bf_state.bfs_al
175 #define bf_frmlen bf_state.bfs_frmlen
176 #define bf_retries bf_state.bfs_retries
177 #define bf_seqno bf_state.bfs_seqno
178 #define bf_tidno bf_state.bfs_tidno
179 #define bf_rcs bf_state.bfs_rcs
180 #define bf_keyix bf_state.bfs_keyix
181 #define bf_keytype bf_state.bfs_keytype
182 #define bf_isdata(bf) (bf->bf_state.bf_type & BUF_DATA)
183 #define bf_isaggr(bf) (bf->bf_state.bf_type & BUF_AGGR)
184 #define bf_isampdu(bf) (bf->bf_state.bf_type & BUF_AMPDU)
185 #define bf_isht(bf) (bf->bf_state.bf_type & BUF_HT)
186 #define bf_isretried(bf) (bf->bf_state.bf_type & BUF_RETRY)
187 #define bf_isxretried(bf) (bf->bf_state.bf_type & BUF_XRETRY)
188 #define bf_isshpreamble(bf) (bf->bf_state.bf_type & BUF_SHORT_PREAMBLE)
189 #define bf_isbar(bf) (bf->bf_state.bf_type & BUF_BAR)
190 #define bf_ispspoll(bf) (bf->bf_state.bf_type & BUF_PSPOLL)
191 #define bf_isaggrburst(bf) (bf->bf_state.bf_type & BUF_AGGR_BURST)
194 * Abstraction of a contiguous buffer to transmit/receive. There is only
195 * a single hw descriptor encapsulated here.
198 struct list_head list;
199 struct list_head *last;
200 struct ath_buf *bf_lastbf; /* last buf of this unit (a frame or
202 struct ath_buf *bf_lastfrm; /* last buf of this frame */
203 struct ath_buf *bf_next; /* next subframe in the aggregate */
204 void *bf_mpdu; /* enclosing frame structure */
205 struct ath_desc *bf_desc; /* virtual addr of desc */
206 dma_addr_t bf_daddr; /* physical addr of desc */
207 dma_addr_t bf_buf_addr; /* physical addr of data buffer */
209 u16 bf_flags; /* tx descriptor flags */
210 struct ath_buf_state bf_state; /* buffer state */
211 dma_addr_t bf_dmacontext;
214 #define ATH_RXBUF_RESET(_bf) ((_bf)->bf_status = 0)
216 /* hw processing complete, desc processed by hal */
217 #define ATH_BUFSTATUS_DONE 0x00000001
218 /* hw processing complete, desc hold for hw */
219 #define ATH_BUFSTATUS_STALE 0x00000002
220 /* Rx-only: OS is done with this packet and it's ok to queued it to hw */
221 #define ATH_BUFSTATUS_FREE 0x00000004
223 /* DMA state for tx/rx descriptors */
227 struct ath_desc *dd_desc; /* descriptors */
228 dma_addr_t dd_desc_paddr; /* physical addr of dd_desc */
229 u32 dd_desc_len; /* size of dd_desc */
230 struct ath_buf *dd_bufptr; /* associated buffers */
231 dma_addr_t dd_dmacontext;
234 int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
235 struct list_head *head, const char *name,
236 int nbuf, int ndesc);
237 void ath_descdma_cleanup(struct ath_softc *sc, struct ath_descdma *dd,
238 struct list_head *head);
244 #define ATH_MAX_ANTENNA 3
245 #define ATH_RXBUF 512
246 #define WME_NUM_TID 16
248 int ath_startrecv(struct ath_softc *sc);
249 bool ath_stoprecv(struct ath_softc *sc);
250 void ath_flushrecv(struct ath_softc *sc);
251 u32 ath_calcrxfilter(struct ath_softc *sc);
252 int ath_rx_init(struct ath_softc *sc, int nbufs);
253 void ath_rx_cleanup(struct ath_softc *sc);
254 int ath_rx_tasklet(struct ath_softc *sc, int flush);
256 #define ATH_TXBUF 512
257 #define ATH_TXMAXTRY 13
258 #define ATH_11N_TXMAXTRY 10
259 #define ATH_MGT_TXMAXTRY 4
260 #define WME_BA_BMP_SIZE 64
261 #define WME_MAX_BA WME_BA_BMP_SIZE
262 #define ATH_TID_MAX_BUFS (2 * WME_MAX_BA)
263 #define TID_TO_WME_AC(_tid) \
264 ((((_tid) == 0) || ((_tid) == 3)) ? WME_AC_BE : \
265 (((_tid) == 1) || ((_tid) == 2)) ? WME_AC_BK : \
266 (((_tid) == 4) || ((_tid) == 5)) ? WME_AC_VI : \
277 u32 axq_qnum; /* hardware q number */
278 u32 *axq_link; /* link ptr in last TX desc */
279 struct list_head axq_q; /* transmit queue */
281 unsigned long axq_lockflags; /* intr state when must cli */
282 u32 axq_depth; /* queue depth */
283 u8 axq_aggr_depth; /* aggregates queued */
284 u32 axq_totalqueued; /* total ever queued */
286 bool stopped; /* Is mac80211 queue stopped ? */
287 struct ath_buf *axq_linkbuf; /* virtual addr of last buffer*/
289 /* first desc of the last descriptor that contains CTS */
290 struct ath_desc *axq_lastdsWithCTS;
292 /* final desc of the gating desc that determines whether
293 lastdsWithCTS has been DMA'ed or not */
294 struct ath_desc *axq_gatingds;
296 struct list_head axq_acq;
299 #define AGGR_CLEANUP BIT(1)
300 #define AGGR_ADDBA_COMPLETE BIT(2)
301 #define AGGR_ADDBA_PROGRESS BIT(3)
303 /* per TID aggregate tx state for a destination */
305 struct list_head list; /* round-robin tid entry */
306 struct list_head buf_q; /* pending buffers */
308 struct ath_atx_ac *ac;
309 struct ath_buf *tx_buf[ATH_TID_MAX_BUFS]; /* active tx frames */
314 int baw_head; /* first un-acked tx buffer */
315 int baw_tail; /* next unused tx buffer slot */
319 int addba_exchangeattempts;
322 /* per access-category aggregate tx state for a destination */
324 int sched; /* dest-ac is scheduled */
325 int qnum; /* H/W queue number associated
327 struct list_head list; /* round-robin txq entry */
328 struct list_head tid_q; /* queue of TIDs with buffers */
331 /* per dest tx state */
333 struct ath_atx_tid tid[WME_NUM_TID];
334 struct ath_atx_ac ac[WME_NUM_AC];
337 /* per-frame tx control block */
338 struct ath_tx_control {
343 /* per frame tx status block */
344 struct ath_xmit_status {
345 int retries; /* number of retries to successufully
346 transmit this frame */
347 int flags; /* status of transmit */
348 #define ATH_TX_ERROR 0x01
349 #define ATH_TX_XRETRY 0x02
350 #define ATH_TX_BAR 0x04
353 /* All RSSI values are noise floor adjusted */
356 int rssictl[ATH_MAX_ANTENNA];
357 int rssiextn[ATH_MAX_ANTENNA];
362 /* if any of ctl,extn chain rssis are valid */
363 #define ATH_TX_CHAIN_RSSI_VALID 0x01
364 /* if extn chain rssis are valid */
365 #define ATH_TX_RSSI_EXTN_VALID 0x02
366 u32 airtime; /* time on air per final tx rate */
369 struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype);
370 void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq);
371 int ath_tx_setup(struct ath_softc *sc, int haltype);
372 void ath_draintxq(struct ath_softc *sc, bool retry_tx);
373 void ath_tx_draintxq(struct ath_softc *sc,
374 struct ath_txq *txq, bool retry_tx);
375 void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an);
376 void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an);
377 void ath_tx_node_free(struct ath_softc *sc, struct ath_node *an);
378 void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq);
379 int ath_tx_init(struct ath_softc *sc, int nbufs);
380 int ath_tx_cleanup(struct ath_softc *sc);
381 int ath_tx_get_qnum(struct ath_softc *sc, int qtype, int haltype);
382 struct ath_txq *ath_test_get_txq(struct ath_softc *sc, struct sk_buff *skb);
383 int ath_txq_update(struct ath_softc *sc, int qnum,
384 struct ath9k_tx_queue_info *q);
385 int ath_tx_start(struct ath_softc *sc, struct sk_buff *skb,
386 struct ath_tx_control *txctl);
387 void ath_tx_tasklet(struct ath_softc *sc);
388 u32 ath_txq_depth(struct ath_softc *sc, int qnum);
389 u32 ath_txq_aggr_depth(struct ath_softc *sc, int qnum);
390 void ath_tx_cabq(struct ath_softc *sc, struct sk_buff *skb);
392 /**********************/
393 /* Node / Aggregation */
394 /**********************/
396 #define ADDBA_EXCHANGE_ATTEMPTS 10
397 #define ATH_AGGR_DELIM_SZ 4
398 #define ATH_AGGR_MINPLEN 256 /* in bytes, minimum packet length */
399 /* number of delimiters for encryption padding */
400 #define ATH_AGGR_ENCRYPTDELIM 10
401 /* minimum h/w qdepth to be sustained to maximize aggregation */
402 #define ATH_AGGR_MIN_QDEPTH 2
403 #define ATH_AMPDU_SUBFRAME_DEFAULT 32
404 #define IEEE80211_SEQ_SEQ_SHIFT 4
405 #define IEEE80211_SEQ_MAX 4096
406 #define IEEE80211_MIN_AMPDU_BUF 0x8
407 #define IEEE80211_HTCAP_MAXRXAMPDU_FACTOR 13
409 /* return whether a bit at index _n in bitmap _bm is set
410 * _sz is the size of the bitmap */
411 #define ATH_BA_ISSET(_bm, _n) (((_n) < (WME_BA_BMP_SIZE)) && \
412 ((_bm)[(_n) >> 5] & (1 << ((_n) & 31))))
414 /* return block-ack bitmap index given sequence and starting sequence */
415 #define ATH_BA_INDEX(_st, _seq) (((_seq) - (_st)) & (IEEE80211_SEQ_MAX - 1))
417 /* returns delimiter padding required given the packet length */
418 #define ATH_AGGR_GET_NDELIM(_len) \
419 (((((_len) + ATH_AGGR_DELIM_SZ) < ATH_AGGR_MINPLEN) ? \
420 (ATH_AGGR_MINPLEN - (_len) - ATH_AGGR_DELIM_SZ) : 0) >> 2)
422 #define BAW_WITHIN(_start, _bawsz, _seqno) \
423 ((((_seqno) - (_start)) & 4095) < (_bawsz))
425 #define ATH_DS_BA_SEQ(_ds) ((_ds)->ds_us.tx.ts_seqnum)
426 #define ATH_DS_BA_BITMAP(_ds) (&(_ds)->ds_us.tx.ba_low)
427 #define ATH_DS_TX_BA(_ds) ((_ds)->ds_us.tx.ts_flags & ATH9K_TX_BA)
428 #define ATH_AN_2_TID(_an, _tidno) (&(_an)->an_aggr.tx.tid[(_tidno)])
430 enum ATH_AGGR_STATUS {
438 struct aggr_rifs_param {
439 int param_max_frames;
443 struct ath_rc_series *param_rcs;
446 /* Per-node aggregation state */
447 struct ath_node_aggr {
452 struct ath_softc *an_sc;
453 struct ath_node_aggr an_aggr;
458 void ath_tx_resume_tid(struct ath_softc *sc, struct ath_atx_tid *tid);
459 bool ath_tx_aggr_check(struct ath_softc *sc, struct ath_node *an, u8 tidno);
460 void ath_tx_aggr_teardown(struct ath_softc *sc, struct ath_node *an, u8 tidno);
461 int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
463 int ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid);
464 void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid);
471 * Define the scheme that we select MAC address for multiple
472 * BSS on the same radio. The very first VAP will just use the MAC
473 * address from the EEPROM. For the next 3 VAPs, we set the
474 * U/L bit (bit 1) in MAC address, and use the next two bits as the
478 #define ATH_SET_VAP_BSSID_MASK(bssid_mask) \
479 ((bssid_mask)[0] &= ~(((ATH_BCBUF-1)<<2)|0x02))
483 enum ath9k_opmode av_opmode;
484 struct ath_buf *av_bcbuf;
485 struct ath_tx_control av_btxctl;
488 /*******************/
489 /* Beacon Handling */
490 /*******************/
493 * Regardless of the number of beacons we stagger, (i.e. regardless of the
494 * number of BSSIDs) if a given beacon does not go out even after waiting this
495 * number of beacon intervals, the game's up.
497 #define BSTUCK_THRESH (9 * ATH_BCBUF)
499 #define ATH_DEFAULT_BINTVAL 100 /* TU */
500 #define ATH_DEFAULT_BMISS_LIMIT 10
501 #define IEEE80211_MS_TO_TU(x) (((x) * 1000) / 1024)
503 struct ath_beacon_config {
513 } u; /* last received beacon/probe response timestamp of this BSS. */
516 void ath9k_beacon_tasklet(unsigned long data);
517 void ath_beacon_config(struct ath_softc *sc, int if_id);
518 int ath_beaconq_setup(struct ath_hal *ah);
519 int ath_beacon_alloc(struct ath_softc *sc, int if_id);
520 void ath_beacon_return(struct ath_softc *sc, struct ath_vap *avp);
521 void ath_beacon_sync(struct ath_softc *sc, int if_id);
527 /* ANI values for STA only.
528 FIXME: Add appropriate values for AP later */
530 #define ATH_ANI_POLLINTERVAL 100 /* 100 milliseconds between ANI poll */
531 #define ATH_SHORT_CALINTERVAL 1000 /* 1 second between calibrations */
532 #define ATH_LONG_CALINTERVAL 30000 /* 30 seconds between calibrations */
533 #define ATH_RESTART_CALINTERVAL 1200000 /* 20 minutes between calibrations */
537 int16_t sc_noise_floor;
538 unsigned int sc_longcal_timer;
539 unsigned int sc_shortcal_timer;
540 unsigned int sc_resetcal_timer;
541 unsigned int sc_checkani_timer;
542 struct timer_list timer;
545 /********************/
547 /********************/
549 #define ATH_LED_PIN 1
559 struct ath_softc *sc;
560 struct led_classdev led_cdev;
561 enum ath_led_type led_type;
567 #define ATH_RFKILL_POLL_INTERVAL 2000 /* msecs */
570 struct rfkill *rfkill;
571 struct delayed_work rfkill_poll;
572 char rfkill_name[32];
575 /********************/
576 /* Main driver core */
577 /********************/
580 * Default cache line size, in bytes.
581 * Used when PCI device not fully initialized by bootrom/BIOS
583 #define DEFAULT_CACHELINE 32
584 #define ATH_DEFAULT_NOISE_FLOOR -95
585 #define ATH_REGCLASSIDS_MAX 10
586 #define ATH_CABQ_READY_TIME 80 /* % of beacon interval */
587 #define ATH_MAX_SW_RETRIES 10
588 #define ATH_CHAN_MAX 255
589 #define IEEE80211_WEP_NKID 4 /* number of key ids */
590 #define IEEE80211_RATE_VAL 0x7f
592 * The key cache is used for h/w cipher state and also for
593 * tracking station state such as the current tx antenna.
594 * We also setup a mapping table between key cache slot indices
595 * and station state to short-circuit node lookups on rx.
596 * Different parts have different size key caches. We handle
597 * up to ATH_KEYMAX entries (could dynamically allocate state).
599 #define ATH_KEYMAX 128 /* max key cache size we handle */
601 #define ATH_IF_ID_ANY 0xff
602 #define ATH_TXPOWER_MAX 100 /* .5 dBm units */
603 #define ATH_RSSI_DUMMY_MARKER 0x127
604 #define ATH_RATE_DUMMY_MARKER 0
612 #define SC_OP_INVALID BIT(0)
613 #define SC_OP_BEACONS BIT(1)
614 #define SC_OP_RXAGGR BIT(2)
615 #define SC_OP_TXAGGR BIT(3)
616 #define SC_OP_CHAINMASK_UPDATE BIT(4)
617 #define SC_OP_FULL_RESET BIT(5)
618 #define SC_OP_NO_RESET BIT(6)
619 #define SC_OP_PREAMBLE_SHORT BIT(7)
620 #define SC_OP_PROTECT_ENABLE BIT(8)
621 #define SC_OP_RXFLUSH BIT(9)
622 #define SC_OP_LED_ASSOCIATED BIT(10)
623 #define SC_OP_RFKILL_REGISTERED BIT(11)
624 #define SC_OP_RFKILL_SW_BLOCKED BIT(12)
625 #define SC_OP_RFKILL_HW_BLOCKED BIT(13)
628 struct ieee80211_hw *hw;
629 struct pci_dev *pdev;
630 struct tasklet_struct intr_tq;
631 struct tasklet_struct bcon_tasklet;
632 struct ath_config sc_config;
633 struct ath_hal *sc_ah;
636 u8 sc_curbssid[ETH_ALEN];
637 u8 sc_myaddr[ETH_ALEN];
638 u8 sc_bssidmask[ETH_ALEN];
640 #ifdef CONFIG_ATH9K_DEBUG
644 u32 sc_flags; /* SC_OP_* */
645 unsigned int rx_filter;
649 int sc_slotupdate; /* slot to next advance fsm */
651 int sc_bslot[ATH_BCBUF];
654 enum ath9k_int sc_imask;
655 enum wireless_mode sc_curmode;
656 enum PROT_MODE sc_protmode;
660 struct ieee80211_vif *sc_vaps[ATH_BCBUF];
666 struct ath9k_node_stats sc_halstats;
667 enum ath9k_ht_extprotspacing sc_ht_extprotspacing;
668 enum ath9k_ht_macmode tx_chan_width;
670 #ifdef CONFIG_SLOW_ANT_DIV
671 struct ath_antdiv sc_antdiv;
674 OK, /* no change needed */
675 UPDATE, /* update pending */
676 COMMIT /* beacon sent, commit change */
677 } sc_updateslot; /* slot time update fsm */
681 DECLARE_BITMAP(sc_keymap, ATH_KEYMAX);
682 u8 sc_splitmic; /* split TKIP MIC keys */
685 struct list_head sc_rxbuf;
686 struct ath_descdma sc_rxdma;
691 struct list_head sc_txbuf;
692 struct ath_txq sc_txq[ATH9K_NUM_TX_QUEUES];
693 struct ath_descdma sc_txdma;
695 int sc_haltype2q[ATH9K_WME_AC_VO+1];
696 u16 seq_no; /* TX sequence number */
699 struct ath9k_tx_queue_info sc_beacon_qi;
700 struct ath_descdma sc_bdma;
701 struct ath_txq *sc_cabq;
702 struct list_head sc_bbuf;
709 struct ieee80211_rate rates[IEEE80211_NUM_BANDS][ATH_RATE_MAX];
710 struct ath_rate_table *hw_rate_table[ATH9K_MODE_MAX];
714 struct ieee80211_channel channels[IEEE80211_NUM_BANDS][ATH_CHAN_MAX];
715 struct ieee80211_supported_band sbands[IEEE80211_NUM_BANDS];
718 spinlock_t sc_rxflushlock;
719 spinlock_t sc_rxbuflock;
720 spinlock_t sc_txbuflock;
721 spinlock_t sc_resetlock;
724 struct ath_led radio_led;
725 struct ath_led assoc_led;
726 struct ath_led tx_led;
727 struct ath_led rx_led;
730 struct ath_rfkill rf_kill;
733 struct ath_ani sc_ani;
736 int ath_reset(struct ath_softc *sc, bool retry_tx);
737 int ath_get_hal_qnum(u16 queue, struct ath_softc *sc);
738 int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc);
739 int ath_cabq_update(struct ath_softc *);