drivers/net/wireless/ath9k/hw.c

   1 /*
   2  * Copyright (c) 2008 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include <linux/io.h>
  18 #include <asm/unaligned.h>
  19
  20 #include "core.h"
  21 #include "hw.h"
  22 #include "reg.h"
  23 #include "phy.h"
  24 #include "initvals.h"
  25
  26 static void ath9k_hw_iqcal_collect(struct ath_hal *ah);
  27 static void ath9k_hw_iqcalibrate(struct ath_hal *ah, u8 numChains);
  28 static void ath9k_hw_adc_gaincal_collect(struct ath_hal *ah);
  29 static void ath9k_hw_adc_gaincal_calibrate(struct ath_hal *ah,
  30                                            u8 numChains);
  31 static void ath9k_hw_adc_dccal_collect(struct ath_hal *ah);
  32 static void ath9k_hw_adc_dccal_calibrate(struct ath_hal *ah,
  33                                          u8 numChains);
  34
  35 static const u8 CLOCK_RATE[] = { 40, 80, 22, 44, 88, 40 };
  36 static const int16_t NOISE_FLOOR[] = { -96, -93, -98, -96, -93, -96 };
  37
  38 static const struct hal_percal_data iq_cal_multi_sample = {
  39         IQ_MISMATCH_CAL,
  40         MAX_CAL_SAMPLES,
  41         PER_MIN_LOG_COUNT,
  42         ath9k_hw_iqcal_collect,
  43         ath9k_hw_iqcalibrate
  44 };
  45 static const struct hal_percal_data iq_cal_single_sample = {
  46         IQ_MISMATCH_CAL,
  47         MIN_CAL_SAMPLES,
  48         PER_MAX_LOG_COUNT,
  49         ath9k_hw_iqcal_collect,
  50         ath9k_hw_iqcalibrate
  51 };
  52 static const struct hal_percal_data adc_gain_cal_multi_sample = {
  53         ADC_GAIN_CAL,
  54         MAX_CAL_SAMPLES,
  55         PER_MIN_LOG_COUNT,
  56         ath9k_hw_adc_gaincal_collect,
  57         ath9k_hw_adc_gaincal_calibrate
  58 };
  59 static const struct hal_percal_data adc_gain_cal_single_sample = {
  60         ADC_GAIN_CAL,
  61         MIN_CAL_SAMPLES,
  62         PER_MAX_LOG_COUNT,
  63         ath9k_hw_adc_gaincal_collect,
  64         ath9k_hw_adc_gaincal_calibrate
  65 };
  66 static const struct hal_percal_data adc_dc_cal_multi_sample = {
  67         ADC_DC_CAL,
  68         MAX_CAL_SAMPLES,
  69         PER_MIN_LOG_COUNT,
  70         ath9k_hw_adc_dccal_collect,
  71         ath9k_hw_adc_dccal_calibrate
  72 };
  73 static const struct hal_percal_data adc_dc_cal_single_sample = {
  74         ADC_DC_CAL,
  75         MIN_CAL_SAMPLES,
  76         PER_MAX_LOG_COUNT,
  77         ath9k_hw_adc_dccal_collect,
  78         ath9k_hw_adc_dccal_calibrate
  79 };
  80 static const struct hal_percal_data adc_init_dc_cal = {
  81         ADC_DC_INIT_CAL,
  82         MIN_CAL_SAMPLES,
  83         INIT_LOG_COUNT,
  84         ath9k_hw_adc_dccal_collect,
  85         ath9k_hw_adc_dccal_calibrate
  86 };
  87
  88 static struct ath9k_rate_table ar5416_11a_table = {
  89         8,
  90         {0},
  91         {
  92                 {true, PHY_OFDM, 6000, 0x0b, 0x00, (0x80 | 12), 0},
  93                 {true, PHY_OFDM, 9000, 0x0f, 0x00, 18, 0},
  94                 {true, PHY_OFDM, 12000, 0x0a, 0x00, (0x80 | 24), 2},
  95                 {true, PHY_OFDM, 18000, 0x0e, 0x00, 36, 2},
  96                 {true, PHY_OFDM, 24000, 0x09, 0x00, (0x80 | 48), 4},
  97                 {true, PHY_OFDM, 36000, 0x0d, 0x00, 72, 4},
  98                 {true, PHY_OFDM, 48000, 0x08, 0x00, 96, 4},
  99                 {true, PHY_OFDM, 54000, 0x0c, 0x00, 108, 4}
 100         },
 101 };
 102
 103 static struct ath9k_rate_table ar5416_11b_table = {
 104         4,
 105         {0},
 106         {
 107                 {true, PHY_CCK, 1000, 0x1b, 0x00, (0x80 | 2), 0},
 108                 {true, PHY_CCK, 2000, 0x1a, 0x04, (0x80 | 4), 1},
 109                 {true, PHY_CCK, 5500, 0x19, 0x04, (0x80 | 11), 1},
 110                 {true, PHY_CCK, 11000, 0x18, 0x04, (0x80 | 22), 1}
 111         },
 112 };
 113
 114 static struct ath9k_rate_table ar5416_11g_table = {
 115         12,
 116         {0},
 117         {
 118                 {true, PHY_CCK, 1000, 0x1b, 0x00, (0x80 | 2), 0},
 119                 {true, PHY_CCK, 2000, 0x1a, 0x04, (0x80 | 4), 1},
 120                 {true, PHY_CCK, 5500, 0x19, 0x04, (0x80 | 11), 2},
 121                 {true, PHY_CCK, 11000, 0x18, 0x04, (0x80 | 22), 3},
 122
 123                 {false, PHY_OFDM, 6000, 0x0b, 0x00, 12, 4},
 124                 {false, PHY_OFDM, 9000, 0x0f, 0x00, 18, 4},
 125                 {true, PHY_OFDM, 12000, 0x0a, 0x00, 24, 6},
 126                 {true, PHY_OFDM, 18000, 0x0e, 0x00, 36, 6},
 127                 {true, PHY_OFDM, 24000, 0x09, 0x00, 48, 8},
 128                 {true, PHY_OFDM, 36000, 0x0d, 0x00, 72, 8},
 129                 {true, PHY_OFDM, 48000, 0x08, 0x00, 96, 8},
 130                 {true, PHY_OFDM, 54000, 0x0c, 0x00, 108, 8}
 131         },
 132 };
 133
 134 static struct ath9k_rate_table ar5416_11ng_table = {
 135         28,
 136         {0},
 137         {
 138                 {true, PHY_CCK, 1000, 0x1b, 0x00, (0x80 | 2), 0},
 139                 {true, PHY_CCK, 2000, 0x1a, 0x04, (0x80 | 4), 1},
 140                 {true, PHY_CCK, 5500, 0x19, 0x04, (0x80 | 11), 2},
 141                 {true, PHY_CCK, 11000, 0x18, 0x04, (0x80 | 22), 3},
 142
 143                 {false, PHY_OFDM, 6000, 0x0b, 0x00, 12, 4},
 144                 {false, PHY_OFDM, 9000, 0x0f, 0x00, 18, 4},
 145                 {true, PHY_OFDM, 12000, 0x0a, 0x00, 24, 6},
 146                 {true, PHY_OFDM, 18000, 0x0e, 0x00, 36, 6},
 147                 {true, PHY_OFDM, 24000, 0x09, 0x00, 48, 8},
 148                 {true, PHY_OFDM, 36000, 0x0d, 0x00, 72, 8},
 149                 {true, PHY_OFDM, 48000, 0x08, 0x00, 96, 8},
 150                 {true, PHY_OFDM, 54000, 0x0c, 0x00, 108, 8},
 151                 {true, PHY_HT, 6500, 0x80, 0x00, 0, 4},
 152                 {true, PHY_HT, 13000, 0x81, 0x00, 1, 6},
 153                 {true, PHY_HT, 19500, 0x82, 0x00, 2, 6},
 154                 {true, PHY_HT, 26000, 0x83, 0x00, 3, 8},
 155                 {true, PHY_HT, 39000, 0x84, 0x00, 4, 8},
 156                 {true, PHY_HT, 52000, 0x85, 0x00, 5, 8},
 157                 {true, PHY_HT, 58500, 0x86, 0x00, 6, 8},
 158                 {true, PHY_HT, 65000, 0x87, 0x00, 7, 8},
 159                 {true, PHY_HT, 13000, 0x88, 0x00, 8, 4},
 160                 {true, PHY_HT, 26000, 0x89, 0x00, 9, 6},
 161                 {true, PHY_HT, 39000, 0x8a, 0x00, 10, 6},
 162                 {true, PHY_HT, 52000, 0x8b, 0x00, 11, 8},
 163                 {true, PHY_HT, 78000, 0x8c, 0x00, 12, 8},
 164                 {true, PHY_HT, 104000, 0x8d, 0x00, 13, 8},
 165                 {true, PHY_HT, 117000, 0x8e, 0x00, 14, 8},
 166                 {true, PHY_HT, 130000, 0x8f, 0x00, 15, 8},
 167         },
 168 };
 169
 170 static struct ath9k_rate_table ar5416_11na_table = {
 171         24,
 172         {0},
 173         {
 174                 {true, PHY_OFDM, 6000, 0x0b, 0x00, (0x80 | 12), 0},
 175                 {true, PHY_OFDM, 9000, 0x0f, 0x00, 18, 0},
 176                 {true, PHY_OFDM, 12000, 0x0a, 0x00, (0x80 | 24), 2},
 177                 {true, PHY_OFDM, 18000, 0x0e, 0x00, 36, 2},
 178                 {true, PHY_OFDM, 24000, 0x09, 0x00, (0x80 | 48), 4},
 179                 {true, PHY_OFDM, 36000, 0x0d, 0x00, 72, 4},
 180                 {true, PHY_OFDM, 48000, 0x08, 0x00, 96, 4},
 181                 {true, PHY_OFDM, 54000, 0x0c, 0x00, 108, 4},
 182                 {true, PHY_HT, 6500, 0x80, 0x00, 0, 0},
 183                 {true, PHY_HT, 13000, 0x81, 0x00, 1, 2},
 184                 {true, PHY_HT, 19500, 0x82, 0x00, 2, 2},
 185                 {true, PHY_HT, 26000, 0x83, 0x00, 3, 4},
 186                 {true, PHY_HT, 39000, 0x84, 0x00, 4, 4},
 187                 {true, PHY_HT, 52000, 0x85, 0x00, 5, 4},
 188                 {true, PHY_HT, 58500, 0x86, 0x00, 6, 4},
 189                 {true, PHY_HT, 65000, 0x87, 0x00, 7, 4},
 190                 {true, PHY_HT, 13000, 0x88, 0x00, 8, 0},
 191                 {true, PHY_HT, 26000, 0x89, 0x00, 9, 2},
 192                 {true, PHY_HT, 39000, 0x8a, 0x00, 10, 2},
 193                 {true, PHY_HT, 52000, 0x8b, 0x00, 11, 4},
 194                 {true, PHY_HT, 78000, 0x8c, 0x00, 12, 4},
 195                 {true, PHY_HT, 104000, 0x8d, 0x00, 13, 4},
 196                 {true, PHY_HT, 117000, 0x8e, 0x00, 14, 4},
 197                 {true, PHY_HT, 130000, 0x8f, 0x00, 15, 4},
 198         },
 199 };
 200
 201 static enum wireless_mode ath9k_hw_chan2wmode(struct ath_hal *ah,
 202                                        const struct ath9k_channel *chan)
 203 {
 204         if (IS_CHAN_CCK(chan))
 205                 return ATH9K_MODE_11A;
 206         if (IS_CHAN_G(chan))
 207                 return ATH9K_MODE_11G;
 208         return ATH9K_MODE_11A;
 209 }
 210
 211 static bool ath9k_hw_wait(struct ath_hal *ah,
 212                           u32 reg,
 213                           u32 mask,
 214                           u32 val)
 215 {
 216         int i;
 217
 218         for (i = 0; i < (AH_TIMEOUT / AH_TIME_QUANTUM); i++) {
 219                 if ((REG_READ(ah, reg) & mask) == val)
 220                         return true;
 221
 222                 udelay(AH_TIME_QUANTUM);
 223         }
 224         DPRINTF(ah->ah_sc, ATH_DBG_PHY_IO,
 225                  "%s: timeout on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
 226                  __func__, reg, REG_READ(ah, reg), mask, val);
 227         return false;
 228 }
 229
 230 static bool ath9k_hw_eeprom_read(struct ath_hal *ah, u32 off,
 231                                  u16 *data)
 232 {
 233         (void) REG_READ(ah, AR5416_EEPROM_OFFSET + (off << AR5416_EEPROM_S));
 234
 235         if (!ath9k_hw_wait(ah,
 236                            AR_EEPROM_STATUS_DATA,
 237                            AR_EEPROM_STATUS_DATA_BUSY |
 238                            AR_EEPROM_STATUS_DATA_PROT_ACCESS, 0)) {
 239                 return false;
 240         }
 241
 242         *data = MS(REG_READ(ah, AR_EEPROM_STATUS_DATA),
 243                    AR_EEPROM_STATUS_DATA_VAL);
 244
 245         return true;
 246 }
 247
 248 static int ath9k_hw_flash_map(struct ath_hal *ah)
 249 {
 250         struct ath_hal_5416 *ahp = AH5416(ah);
 251
 252         ahp->ah_cal_mem = ioremap(AR5416_EEPROM_START_ADDR, AR5416_EEPROM_MAX);
 253
 254         if (!ahp->ah_cal_mem) {
 255                 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
 256                          "%s: cannot remap eeprom region \n", __func__);
 257                 return -EIO;
 258         }
 259
 260         return 0;
 261 }
 262
 263 static bool ath9k_hw_flash_read(struct ath_hal *ah, u32 off,
 264                                 u16 *data)
 265 {
 266         struct ath_hal_5416 *ahp = AH5416(ah);
 267
 268         *data = ioread16(ahp->ah_cal_mem + off);
 269         return true;
 270 }
 271
 272 static void ath9k_hw_read_revisions(struct ath_hal *ah)
 273 {
 274         u32 val;
 275
 276         val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
 277
 278         if (val == 0xFF) {
 279                 val = REG_READ(ah, AR_SREV);
 280
 281                 ah->ah_macVersion =
 282                         (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
 283
 284                 ah->ah_macRev = MS(val, AR_SREV_REVISION2);
 285                 ah->ah_isPciExpress =
 286                         (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
 287
 288         } else {
 289                 if (!AR_SREV_9100(ah))
 290                         ah->ah_macVersion = MS(val, AR_SREV_VERSION);
 291
 292                 ah->ah_macRev = val & AR_SREV_REVISION;
 293
 294                 if (ah->ah_macVersion == AR_SREV_VERSION_5416_PCIE)
 295                         ah->ah_isPciExpress = true;
 296         }
 297 }
 298
 299 u32 ath9k_hw_reverse_bits(u32 val, u32 n)
 300 {
 301         u32 retval;
 302         int i;
 303
 304         for (i = 0, retval = 0; i < n; i++) {
 305                 retval = (retval << 1) | (val & 1);
 306                 val >>= 1;
 307         }
 308         return retval;
 309 }
 310
 311 static void ath9k_hw_set_defaults(struct ath_hal *ah)
 312 {
 313         int i;
 314
 315         ah->ah_config.dma_beacon_response_time = 2;
 316         ah->ah_config.sw_beacon_response_time = 10;
 317         ah->ah_config.additional_swba_backoff = 0;
 318         ah->ah_config.ack_6mb = 0x0;
 319         ah->ah_config.cwm_ignore_extcca = 0;
 320         ah->ah_config.pcie_powersave_enable = 0;
 321         ah->ah_config.pcie_l1skp_enable = 0;
 322         ah->ah_config.pcie_clock_req = 0;
 323         ah->ah_config.pcie_power_reset = 0x100;
 324         ah->ah_config.pcie_restore = 0;
 325         ah->ah_config.pcie_waen = 0;
 326         ah->ah_config.analog_shiftreg = 1;
 327         ah->ah_config.ht_enable = 1;
 328         ah->ah_config.ofdm_trig_low = 200;
 329         ah->ah_config.ofdm_trig_high = 500;
 330         ah->ah_config.cck_trig_high = 200;
 331         ah->ah_config.cck_trig_low = 100;
 332         ah->ah_config.enable_ani = 0;
 333         ah->ah_config.noise_immunity_level = 4;
 334         ah->ah_config.ofdm_weaksignal_det = 1;
 335         ah->ah_config.cck_weaksignal_thr = 0;
 336         ah->ah_config.spur_immunity_level = 2;
 337         ah->ah_config.firstep_level = 0;
 338         ah->ah_config.rssi_thr_high = 40;
 339         ah->ah_config.rssi_thr_low = 7;
 340         ah->ah_config.diversity_control = 0;
 341         ah->ah_config.antenna_switch_swap = 0;
 342
 343         for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
 344                 ah->ah_config.spurchans[i][0] = AR_NO_SPUR;
 345                 ah->ah_config.spurchans[i][1] = AR_NO_SPUR;
 346         }
 347
 348         ah->ah_config.intr_mitigation = 0;
 349 }
 350
 351 static void ath9k_hw_override_ini(struct ath_hal *ah,
 352                                          struct ath9k_channel *chan)
 353 {
 354         if (!AR_SREV_5416_V20_OR_LATER(ah)
 355             || AR_SREV_9280_10_OR_LATER(ah))
 356                 return;
 357
 358         REG_WRITE(ah, 0x9800 + (651 << 2), 0x11);
 359 }
 360
 361 static void ath9k_hw_init_bb(struct ath_hal *ah,
 362                              struct ath9k_channel *chan)
 363 {
 364         u32 synthDelay;
 365
 366         synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
 367         if (IS_CHAN_CCK(chan))
 368                 synthDelay = (4 * synthDelay) / 22;
 369         else
 370                 synthDelay /= 10;
 371
 372         REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
 373
 374         udelay(synthDelay + BASE_ACTIVATE_DELAY);
 375 }
 376
 377 static void ath9k_hw_init_interrupt_masks(struct ath_hal *ah,
 378                                           enum ath9k_opmode opmode)
 379 {
 380         struct ath_hal_5416 *ahp = AH5416(ah);
 381
 382         ahp->ah_maskReg = AR_IMR_TXERR |
 383                 AR_IMR_TXURN |
 384                 AR_IMR_RXERR |
 385                 AR_IMR_RXORN |
 386                 AR_IMR_BCNMISC;
 387
 388         if (ahp->ah_intrMitigation)
 389                 ahp->ah_maskReg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
 390         else
 391                 ahp->ah_maskReg |= AR_IMR_RXOK;
 392
 393         ahp->ah_maskReg |= AR_IMR_TXOK;
 394
 395         if (opmode == ATH9K_M_HOSTAP)
 396                 ahp->ah_maskReg |= AR_IMR_MIB;
 397
 398         REG_WRITE(ah, AR_IMR, ahp->ah_maskReg);
 399         REG_WRITE(ah, AR_IMR_S2, REG_READ(ah, AR_IMR_S2) | AR_IMR_S2_GTT);
 400
 401         if (!AR_SREV_9100(ah)) {
 402                 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
 403                 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT);
 404                 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
 405         }
 406 }
 407
 408 static void ath9k_hw_init_qos(struct ath_hal *ah)
 409 {
 410         REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
 411         REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
 412
 413         REG_WRITE(ah, AR_QOS_NO_ACK,
 414                   SM(2, AR_QOS_NO_ACK_TWO_BIT) |
 415                   SM(5, AR_QOS_NO_ACK_BIT_OFF) |
 416                   SM(0, AR_QOS_NO_ACK_BYTE_OFF));
 417
 418         REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
 419         REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
 420         REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
 421         REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
 422         REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
 423 }
 424
 425 static void ath9k_hw_analog_shift_rmw(struct ath_hal *ah,
 426                                       u32 reg,
 427                                       u32 mask,
 428                                       u32 shift,
 429                                       u32 val)
 430 {
 431         u32 regVal;
 432
 433         regVal = REG_READ(ah, reg) & ~mask;
 434         regVal |= (val << shift) & mask;
 435
 436         REG_WRITE(ah, reg, regVal);
 437
 438         if (ah->ah_config.analog_shiftreg)
 439                 udelay(100);
 440
 441         return;
 442 }
 443
 444 static u8 ath9k_hw_get_num_ant_config(struct ath_hal_5416 *ahp,
 445                                       enum ieee80211_band freq_band)
 446 {
 447         struct ar5416_eeprom *eep = &ahp->ah_eeprom;
 448         struct modal_eep_header *pModal =
 449                 &(eep->modalHeader[IEEE80211_BAND_5GHZ == freq_band]);
 450         struct base_eep_header *pBase = &eep->baseEepHeader;
 451         u8 num_ant_config;
 452
 453         num_ant_config = 1;
 454
 455         if (pBase->version >= 0x0E0D)
 456                 if (pModal->useAnt1)
 457                         num_ant_config += 1;
 458
 459         return num_ant_config;
 460 }
 461
 462 static int
 463 ath9k_hw_get_eeprom_antenna_cfg(struct ath_hal_5416 *ahp,
 464                                 struct ath9k_channel *chan,
 465                                 u8 index,
 466                                 u16 *config)
 467 {
 468         struct ar5416_eeprom *eep = &ahp->ah_eeprom;
 469         struct modal_eep_header *pModal =
 470                 &(eep->modalHeader[IS_CHAN_2GHZ(chan)]);
 471         struct base_eep_header *pBase = &eep->baseEepHeader;
 472
 473         switch (index) {
 474         case 0:
 475                 *config = pModal->antCtrlCommon & 0xFFFF;
 476                 return 0;
 477         case 1:
 478                 if (pBase->version >= 0x0E0D) {
 479                         if (pModal->useAnt1) {
 480                                 *config =
 481                                 ((pModal->antCtrlCommon & 0xFFFF0000) >> 16);
 482                                 return 0;
 483                         }
 484                 }
 485                 break;
 486         default:
 487                 break;
 488         }
 489
 490         return -EINVAL;
 491 }
 492
 493 static inline bool ath9k_hw_nvram_read(struct ath_hal *ah,
 494                                        u32 off,
 495                                        u16 *data)
 496 {
 497         if (ath9k_hw_use_flash(ah))
 498                 return ath9k_hw_flash_read(ah, off, data);
 499         else
 500                 return ath9k_hw_eeprom_read(ah, off, data);
 501 }
 502
 503 static bool ath9k_hw_fill_eeprom(struct ath_hal *ah)
 504 {
 505         struct ath_hal_5416 *ahp = AH5416(ah);
 506         struct ar5416_eeprom *eep = &ahp->ah_eeprom;
 507         u16 *eep_data;
 508         int addr, ar5416_eep_start_loc = 0;
 509
 510         if (!ath9k_hw_use_flash(ah)) {
 511                 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
 512                          "%s: Reading from EEPROM, not flash\n", __func__);
 513                 ar5416_eep_start_loc = 256;
 514         }
 515         if (AR_SREV_9100(ah))
 516                 ar5416_eep_start_loc = 256;
 517
 518         eep_data = (u16 *) eep;
 519         for (addr = 0;
 520              addr < sizeof(struct ar5416_eeprom) / sizeof(u16);
 521              addr++) {
 522                 if (!ath9k_hw_nvram_read(ah, addr + ar5416_eep_start_loc,
 523                                          eep_data)) {
 524                         DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
 525                                  "%s: Unable to read eeprom region \n",
 526                                  __func__);
 527                         return false;
 528                 }
 529                 eep_data++;
 530         }
 531         return true;
 532 }
 533
 534 /* XXX: Clean me up, make me more legible */
 535 static bool
 536 ath9k_hw_eeprom_set_board_values(struct ath_hal *ah,
 537                                  struct ath9k_channel *chan)
 538 {
 539         struct modal_eep_header *pModal;
 540         int i, regChainOffset;
 541         struct ath_hal_5416 *ahp = AH5416(ah);
 542         struct ar5416_eeprom *eep = &ahp->ah_eeprom;
 543         u8 txRxAttenLocal;
 544         u16 ant_config;
 545
 546         pModal = &(eep->modalHeader[IS_CHAN_2GHZ(chan)]);
 547
 548         txRxAttenLocal = IS_CHAN_2GHZ(chan) ? 23 : 44;
 549
 550         ath9k_hw_get_eeprom_antenna_cfg(ahp, chan, 1, &ant_config);
 551         REG_WRITE(ah, AR_PHY_SWITCH_COM, ant_config);
 552
 553         for (i = 0; i < AR5416_MAX_CHAINS; i++) {
 554                 if (AR_SREV_9280(ah)) {
 555                         if (i >= 2)
 556                                 break;
 557                 }
 558
 559                 if (AR_SREV_5416_V20_OR_LATER(ah) &&
 560                     (ahp->ah_rxchainmask == 5 || ahp->ah_txchainmask == 5)
 561                     && (i != 0))
 562                         regChainOffset = (i == 1) ? 0x2000 : 0x1000;
 563                 else
 564                         regChainOffset = i * 0x1000;
 565
 566                 REG_WRITE(ah, AR_PHY_SWITCH_CHAIN_0 + regChainOffset,
 567                           pModal->antCtrlChain[i]);
 568
 569                 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset,
 570                           (REG_READ(ah,
 571                                     AR_PHY_TIMING_CTRL4(0) +
 572                                     regChainOffset) &
 573                            ~(AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF |
 574                              AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF)) |
 575                           SM(pModal->iqCalICh[i],
 576                              AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF) |
 577                           SM(pModal->iqCalQCh[i],
 578                              AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF));
 579
 580                 if ((i == 0) || AR_SREV_5416_V20_OR_LATER(ah)) {
 581                         if ((eep->baseEepHeader.version &
 582                              AR5416_EEP_VER_MINOR_MASK) >=
 583                             AR5416_EEP_MINOR_VER_3) {
 584                                 txRxAttenLocal = pModal->txRxAttenCh[i];
 585                                 if (AR_SREV_9280_10_OR_LATER(ah)) {
 586                                         REG_RMW_FIELD(ah,
 587                                                 AR_PHY_GAIN_2GHZ +
 588                                                 regChainOffset,
 589                                                 AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN,
 590                                                 pModal->
 591                                                 bswMargin[i]);
 592                                         REG_RMW_FIELD(ah,
 593                                                 AR_PHY_GAIN_2GHZ +
 594                                                 regChainOffset,
 595                                                 AR_PHY_GAIN_2GHZ_XATTEN1_DB,
 596                                                 pModal->
 597                                                 bswAtten[i]);
 598                                         REG_RMW_FIELD(ah,
 599                                                 AR_PHY_GAIN_2GHZ +
 600                                                 regChainOffset,
 601                                                 AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN,
 602                                                 pModal->
 603                                                 xatten2Margin[i]);
 604                                         REG_RMW_FIELD(ah,
 605                                                 AR_PHY_GAIN_2GHZ +
 606                                                 regChainOffset,
 607                                                 AR_PHY_GAIN_2GHZ_XATTEN2_DB,
 608                                                 pModal->
 609                                                 xatten2Db[i]);
 610                                 } else {
 611                                         REG_WRITE(ah,
 612                                                   AR_PHY_GAIN_2GHZ +
 613                                                   regChainOffset,
 614                                                   (REG_READ(ah,
 615                                                             AR_PHY_GAIN_2GHZ +
 616                                                             regChainOffset) &
 617                                                    ~AR_PHY_GAIN_2GHZ_BSW_MARGIN)
 618                                                   | SM(pModal->
 619                                                   bswMargin[i],
 620                                                   AR_PHY_GAIN_2GHZ_BSW_MARGIN));
 621                                         REG_WRITE(ah,
 622                                                   AR_PHY_GAIN_2GHZ +
 623                                                   regChainOffset,
 624                                                   (REG_READ(ah,
 625                                                             AR_PHY_GAIN_2GHZ +
 626                                                             regChainOffset) &
 627                                                    ~AR_PHY_GAIN_2GHZ_BSW_ATTEN)
 628                                                   | SM(pModal->bswAtten[i],
 629                                                   AR_PHY_GAIN_2GHZ_BSW_ATTEN));
 630                                 }
 631                         }
 632                         if (AR_SREV_9280_10_OR_LATER(ah)) {
 633                                 REG_RMW_FIELD(ah,
 634                                               AR_PHY_RXGAIN +
 635                                               regChainOffset,
 636                                               AR9280_PHY_RXGAIN_TXRX_ATTEN,
 637                                               txRxAttenLocal);
 638                                 REG_RMW_FIELD(ah,
 639                                               AR_PHY_RXGAIN +
 640                                               regChainOffset,
 641                                               AR9280_PHY_RXGAIN_TXRX_MARGIN,
 642                                               pModal->rxTxMarginCh[i]);
 643                         } else {
 644                                 REG_WRITE(ah,
 645                                           AR_PHY_RXGAIN + regChainOffset,
 646                                           (REG_READ(ah,
 647                                                     AR_PHY_RXGAIN +
 648                                                     regChainOffset) &
 649                                            ~AR_PHY_RXGAIN_TXRX_ATTEN) |
 650                                           SM(txRxAttenLocal,
 651                                              AR_PHY_RXGAIN_TXRX_ATTEN));
 652                                 REG_WRITE(ah,
 653                                           AR_PHY_GAIN_2GHZ +
 654                                           regChainOffset,
 655                                           (REG_READ(ah,
 656                                                     AR_PHY_GAIN_2GHZ +
 657                                                     regChainOffset) &
 658                                            ~AR_PHY_GAIN_2GHZ_RXTX_MARGIN) |
 659                                           SM(pModal->rxTxMarginCh[i],
 660                                              AR_PHY_GAIN_2GHZ_RXTX_MARGIN));
 661                         }
 662                 }
 663         }
 664
 665         if (AR_SREV_9280_10_OR_LATER(ah)) {
 666                 if (IS_CHAN_2GHZ(chan)) {
 667                         ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH0,
 668                                                   AR_AN_RF2G1_CH0_OB,
 669                                                   AR_AN_RF2G1_CH0_OB_S,
 670                                                   pModal->ob);
 671                         ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH0,
 672                                                   AR_AN_RF2G1_CH0_DB,
 673                                                   AR_AN_RF2G1_CH0_DB_S,
 674                                                   pModal->db);
 675                         ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH1,
 676                                                   AR_AN_RF2G1_CH1_OB,
 677                                                   AR_AN_RF2G1_CH1_OB_S,
 678                                                   pModal->ob_ch1);
 679                         ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH1,
 680                                                   AR_AN_RF2G1_CH1_DB,
 681                                                   AR_AN_RF2G1_CH1_DB_S,
 682                                                   pModal->db_ch1);
 683                 } else {
 684                         ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH0,
 685                                                   AR_AN_RF5G1_CH0_OB5,
 686                                                   AR_AN_RF5G1_CH0_OB5_S,
 687                                                   pModal->ob);
 688                         ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH0,
 689                                                   AR_AN_RF5G1_CH0_DB5,
 690                                                   AR_AN_RF5G1_CH0_DB5_S,
 691                                                   pModal->db);
 692                         ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH1,
 693                                                   AR_AN_RF5G1_CH1_OB5,
 694                                                   AR_AN_RF5G1_CH1_OB5_S,
 695                                                   pModal->ob_ch1);
 696                         ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH1,
 697                                                   AR_AN_RF5G1_CH1_DB5,
 698                                                   AR_AN_RF5G1_CH1_DB5_S,
 699                                                   pModal->db_ch1);
 700                 }
 701                 ath9k_hw_analog_shift_rmw(ah, AR_AN_TOP2,
 702                                           AR_AN_TOP2_XPABIAS_LVL,
 703                                           AR_AN_TOP2_XPABIAS_LVL_S,
 704                                           pModal->xpaBiasLvl);
 705                 ath9k_hw_analog_shift_rmw(ah, AR_AN_TOP2,
 706                                           AR_AN_TOP2_LOCALBIAS,
 707                                           AR_AN_TOP2_LOCALBIAS_S,
 708                                           pModal->local_bias);
 709                 DPRINTF(ah->ah_sc, ATH_DBG_ANY, "ForceXPAon: %d\n",
 710                         pModal->force_xpaon);
 711                 REG_RMW_FIELD(ah, AR_PHY_XPA_CFG, AR_PHY_FORCE_XPA_CFG,
 712                               pModal->force_xpaon);
 713         }
 714
 715         REG_RMW_FIELD(ah, AR_PHY_SETTLING, AR_PHY_SETTLING_SWITCH,
 716                       pModal->switchSettling);
 717         REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, AR_PHY_DESIRED_SZ_ADC,
 718                       pModal->adcDesiredSize);
 719
 720         if (!AR_SREV_9280_10_OR_LATER(ah))
 721                 REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ,
 722                               AR_PHY_DESIRED_SZ_PGA,
 723                               pModal->pgaDesiredSize);
 724
 725         REG_WRITE(ah, AR_PHY_RF_CTL4,
 726                   SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAA_OFF)
 727                   | SM(pModal->txEndToXpaOff,
 728                        AR_PHY_RF_CTL4_TX_END_XPAB_OFF)
 729                   | SM(pModal->txFrameToXpaOn,
 730                        AR_PHY_RF_CTL4_FRAME_XPAA_ON)
 731                   | SM(pModal->txFrameToXpaOn,
 732                        AR_PHY_RF_CTL4_FRAME_XPAB_ON));
 733
 734         REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_A2_RX_ON,
 735                       pModal->txEndToRxOn);
 736         if (AR_SREV_9280_10_OR_LATER(ah)) {
 737                 REG_RMW_FIELD(ah, AR_PHY_CCA, AR9280_PHY_CCA_THRESH62,
 738                               pModal->thresh62);
 739                 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA0,
 740                               AR_PHY_EXT_CCA0_THRESH62,
 741                               pModal->thresh62);
 742         } else {
 743                 REG_RMW_FIELD(ah, AR_PHY_CCA, AR_PHY_CCA_THRESH62,
 744                               pModal->thresh62);
 745                 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA,
 746                               AR_PHY_EXT_CCA_THRESH62,
 747                               pModal->thresh62);
 748         }
 749
 750         if ((eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
 751             AR5416_EEP_MINOR_VER_2) {
 752                 REG_RMW_FIELD(ah, AR_PHY_RF_CTL2,
 753                               AR_PHY_TX_END_DATA_START,
 754                               pModal->txFrameToDataStart);
 755                 REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_END_PA_ON,
 756                               pModal->txFrameToPaOn);
 757         }
 758
 759         if ((eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
 760             AR5416_EEP_MINOR_VER_3) {
 761                 if (IS_CHAN_HT40(chan))
 762                         REG_RMW_FIELD(ah, AR_PHY_SETTLING,
 763                                       AR_PHY_SETTLING_SWITCH,
 764                                       pModal->swSettleHt40);
 765         }
 766
 767         return true;
 768 }
 769
 770 static int ath9k_hw_check_eeprom(struct ath_hal *ah)
 771 {
 772         u32 sum = 0, el;
 773         u16 *eepdata;
 774         int i;
 775         struct ath_hal_5416 *ahp = AH5416(ah);
 776         bool need_swap = false;
 777         struct ar5416_eeprom *eep =
 778                 (struct ar5416_eeprom *) &ahp->ah_eeprom;
 779
 780         if (!ath9k_hw_use_flash(ah)) {
 781                 u16 magic, magic2;
 782                 int addr;
 783
 784                 if (!ath9k_hw_nvram_read(ah, AR5416_EEPROM_MAGIC_OFFSET,
 785                                         &magic)) {
 786                         DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
 787                                  "%s: Reading Magic # failed\n", __func__);
 788                         return false;
 789                 }
 790                 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, "%s: Read Magic = 0x%04X\n",
 791                          __func__, magic);
 792
 793                 if (magic != AR5416_EEPROM_MAGIC) {
 794                         magic2 = swab16(magic);
 795
 796                         if (magic2 == AR5416_EEPROM_MAGIC) {
 797                                 need_swap = true;
 798                                 eepdata = (u16 *) (&ahp->ah_eeprom);
 799
 800                                 for (addr = 0;
 801                                      addr <
 802                                              sizeof(struct ar5416_eeprom) /
 803                                              sizeof(u16); addr++) {
 804                                         u16 temp;
 805
 806                                         temp = swab16(*eepdata);
 807                                         *eepdata = temp;
 808                                         eepdata++;
 809
 810                                         DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
 811                                                  "0x%04X  ", *eepdata);
 812                                         if (((addr + 1) % 6) == 0)
 813                                                 DPRINTF(ah->ah_sc,
 814                                                          ATH_DBG_EEPROM,
 815                                                          "\n");
 816                                 }
 817                         } else {
 818                                 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
 819                                          "Invalid EEPROM Magic. "
 820                                         "endianness missmatch.\n");
 821                                 return -EINVAL;
 822                         }
 823                 }
 824         }
 825         DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, "need_swap = %s.\n",
 826                  need_swap ? "True" : "False");
 827
 828         if (need_swap)
 829                 el = swab16(ahp->ah_eeprom.baseEepHeader.length);
 830         else
 831                 el = ahp->ah_eeprom.baseEepHeader.length;
 832
 833         if (el > sizeof(struct ar5416_eeprom))
 834                 el = sizeof(struct ar5416_eeprom) / sizeof(u16);
 835         else
 836                 el = el / sizeof(u16);
 837
 838         eepdata = (u16 *) (&ahp->ah_eeprom);
 839
 840         for (i = 0; i < el; i++)
 841                 sum ^= *eepdata++;
 842
 843         if (need_swap) {
 844                 u32 integer, j;
 845                 u16 word;
 846
 847                 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
 848                          "EEPROM Endianness is not native.. Changing \n");
 849
 850                 word = swab16(eep->baseEepHeader.length);
 851                 eep->baseEepHeader.length = word;
 852
 853                 word = swab16(eep->baseEepHeader.checksum);
 854                 eep->baseEepHeader.checksum = word;
 855
 856                 word = swab16(eep->baseEepHeader.version);
 857                 eep->baseEepHeader.version = word;
 858
 859                 word = swab16(eep->baseEepHeader.regDmn[0]);
 860                 eep->baseEepHeader.regDmn[0] = word;
 861
 862                 word = swab16(eep->baseEepHeader.regDmn[1]);
 863                 eep->baseEepHeader.regDmn[1] = word;
 864
 865                 word = swab16(eep->baseEepHeader.rfSilent);
 866                 eep->baseEepHeader.rfSilent = word;
 867
 868                 word = swab16(eep->baseEepHeader.blueToothOptions);
 869                 eep->baseEepHeader.blueToothOptions = word;
 870
 871                 word = swab16(eep->baseEepHeader.deviceCap);
 872                 eep->baseEepHeader.deviceCap = word;
 873
 874                 for (j = 0; j < ARRAY_SIZE(eep->modalHeader); j++) {
 875                         struct modal_eep_header *pModal =
 876                                 &eep->modalHeader[j];
 877                         integer = swab32(pModal->antCtrlCommon);
 878                         pModal->antCtrlCommon = integer;
 879
 880                         for (i = 0; i < AR5416_MAX_CHAINS; i++) {
 881                                 integer = swab32(pModal->antCtrlChain[i]);
 882                                 pModal->antCtrlChain[i] = integer;
 883                         }
 884
 885                         for (i = 0; i < AR5416_EEPROM_MODAL_SPURS; i++) {
 886                                 word = swab16(pModal->spurChans[i].spurChan);
 887                                 pModal->spurChans[i].spurChan = word;
 888                         }
 889                 }
 890         }
 891
 892         if (sum != 0xffff || ar5416_get_eep_ver(ahp) != AR5416_EEP_VER ||
 893             ar5416_get_eep_rev(ahp) < AR5416_EEP_NO_BACK_VER) {
 894                 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
 895                          "Bad EEPROM checksum 0x%x or revision 0x%04x\n",
 896                          sum, ar5416_get_eep_ver(ahp));
 897                 return -EINVAL;
 898         }
 899
 900         return 0;
 901 }
 902
 903 static bool ath9k_hw_chip_test(struct ath_hal *ah)
 904 {
 905         u32 regAddr[2] = { AR_STA_ID0, AR_PHY_BASE + (8 << 2) };
 906         u32 regHold[2];
 907         u32 patternData[4] = { 0x55555555,
 908                                      0xaaaaaaaa,
 909                                      0x66666666,
 910                                      0x99999999 };
 911         int i, j;
 912
 913         for (i = 0; i < 2; i++) {
 914                 u32 addr = regAddr[i];
 915                 u32 wrData, rdData;
 916
 917                 regHold[i] = REG_READ(ah, addr);
 918                 for (j = 0; j < 0x100; j++) {
 919                         wrData = (j << 16) | j;
 920                         REG_WRITE(ah, addr, wrData);
 921                         rdData = REG_READ(ah, addr);
 922                         if (rdData != wrData) {
 923                                 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
 924                                  "%s: address test failed "
 925                                 "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
 926                                  __func__, addr, wrData, rdData);
 927                                 return false;
 928                         }
 929                 }
 930                 for (j = 0; j < 4; j++) {
 931                         wrData = patternData[j];
 932                         REG_WRITE(ah, addr, wrData);
 933                         rdData = REG_READ(ah, addr);
 934                         if (wrData != rdData) {
 935                                 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
 936                                  "%s: address test failed "
 937                                 "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
 938                                  __func__, addr, wrData, rdData);
 939                                 return false;
 940                         }
 941                 }
 942                 REG_WRITE(ah, regAddr[i], regHold[i]);
 943         }
 944         udelay(100);
 945         return true;
 946 }
 947
 948 u32 ath9k_hw_getrxfilter(struct ath_hal *ah)
 949 {
 950         u32 bits = REG_READ(ah, AR_RX_FILTER);
 951         u32 phybits = REG_READ(ah, AR_PHY_ERR);
 952
 953         if (phybits & AR_PHY_ERR_RADAR)
 954                 bits |= ATH9K_RX_FILTER_PHYRADAR;
 955         if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
 956                 bits |= ATH9K_RX_FILTER_PHYERR;
 957         return bits;
 958 }
 959
 960 void ath9k_hw_setrxfilter(struct ath_hal *ah, u32 bits)
 961 {
 962         u32 phybits;
 963
 964         REG_WRITE(ah, AR_RX_FILTER, (bits & 0xffff) | AR_RX_COMPR_BAR);
 965         phybits = 0;
 966         if (bits & ATH9K_RX_FILTER_PHYRADAR)
 967                 phybits |= AR_PHY_ERR_RADAR;
 968         if (bits & ATH9K_RX_FILTER_PHYERR)
 969                 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
 970         REG_WRITE(ah, AR_PHY_ERR, phybits);
 971
 972         if (phybits)
 973                 REG_WRITE(ah, AR_RXCFG,
 974                           REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
 975         else
 976                 REG_WRITE(ah, AR_RXCFG,
 977                           REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA);
 978 }
 979
 980 bool ath9k_hw_setcapability(struct ath_hal *ah,
 981                             enum ath9k_capability_type type,
 982                             u32 capability,
 983                             u32 setting,
 984                             int *status)
 985 {
 986         struct ath_hal_5416 *ahp = AH5416(ah);
 987         u32 v;
 988
 989         switch (type) {
 990         case ATH9K_CAP_TKIP_MIC:
 991                 if (setting)
 992                         ahp->ah_staId1Defaults |=
 993                                 AR_STA_ID1_CRPT_MIC_ENABLE;
 994                 else
 995                         ahp->ah_staId1Defaults &=
 996                                 ~AR_STA_ID1_CRPT_MIC_ENABLE;
 997                 return true;
 998         case ATH9K_CAP_DIVERSITY:
 999                 v = REG_READ(ah, AR_PHY_CCK_DETECT);
1000                 if (setting)
1001                         v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
1002                 else
1003                         v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
1004                 REG_WRITE(ah, AR_PHY_CCK_DETECT, v);
1005                 return true;
1006         case ATH9K_CAP_MCAST_KEYSRCH:
1007                 if (setting)
1008                         ahp->ah_staId1Defaults |= AR_STA_ID1_MCAST_KSRCH;
1009                 else
1010                         ahp->ah_staId1Defaults &= ~AR_STA_ID1_MCAST_KSRCH;
1011                 return true;
1012         case ATH9K_CAP_TSF_ADJUST:
1013                 if (setting)
1014                         ahp->ah_miscMode |= AR_PCU_TX_ADD_TSF;
1015                 else
1016                         ahp->ah_miscMode &= ~AR_PCU_TX_ADD_TSF;
1017                 return true;
1018         default:
1019                 return false;
1020         }
1021 }
1022
1023 void ath9k_hw_dmaRegDump(struct ath_hal *ah)
1024 {
1025         u32 val[ATH9K_NUM_DMA_DEBUG_REGS];
1026         int qcuOffset = 0, dcuOffset = 0;
1027         u32 *qcuBase = &val[0], *dcuBase = &val[4];
1028         int i;
1029
1030         REG_WRITE(ah, AR_MACMISC,
1031                   ((AR_MACMISC_DMA_OBS_LINE_8 << AR_MACMISC_DMA_OBS_S) |
1032                    (AR_MACMISC_MISC_OBS_BUS_1 <<
1033                     AR_MACMISC_MISC_OBS_BUS_MSB_S)));
1034
1035         DPRINTF(ah->ah_sc, ATH_DBG_REG_IO, "Raw DMA Debug values:\n");
1036         for (i = 0; i < ATH9K_NUM_DMA_DEBUG_REGS; i++) {
1037                 if (i % 4 == 0)
1038                         DPRINTF(ah->ah_sc, ATH_DBG_REG_IO, "\n");
1039
1040                 val[i] = REG_READ(ah, AR_DMADBG_0 + (i * sizeof(u32)));
1041                 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO, "%d: %08x ", i, val[i]);
1042         }
1043
1044         DPRINTF(ah->ah_sc, ATH_DBG_REG_IO, "\n\n");
1045         DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
1046                  "Num QCU: chain_st fsp_ok fsp_st DCU: chain_st\n");
1047
1048         for (i = 0; i < ATH9K_NUM_QUEUES;
1049              i++, qcuOffset += 4, dcuOffset += 5) {
1050                 if (i == 8) {
1051                         qcuOffset = 0;
1052                         qcuBase++;
1053                 }
1054
1055                 if (i == 6) {
1056                         dcuOffset = 0;
1057                         dcuBase++;
1058                 }
1059
1060                 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
1061                          "%2d          %2x      %1x     %2x           %2x\n",
1062                          i, (*qcuBase & (0x7 << qcuOffset)) >> qcuOffset,
1063                          (*qcuBase & (0x8 << qcuOffset)) >> (qcuOffset +
1064                                                              3),
1065                          val[2] & (0x7 << (i * 3)) >> (i * 3),
1066                          (*dcuBase & (0x1f << dcuOffset)) >> dcuOffset);
1067         }
1068
1069         DPRINTF(ah->ah_sc, ATH_DBG_REG_IO, "\n");
1070         DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
1071                  "qcu_stitch state:   %2x    qcu_fetch state:        %2x\n",
1072                  (val[3] & 0x003c0000) >> 18, (val[3] & 0x03c00000) >> 22);
1073         DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
1074                  "qcu_complete state: %2x    dcu_complete state:     %2x\n",
1075                  (val[3] & 0x1c000000) >> 26, (val[6] & 0x3));
1076         DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
1077                  "dcu_arb state:      %2x    dcu_fp state:           %2x\n",
1078                  (val[5] & 0x06000000) >> 25, (val[5] & 0x38000000) >> 27);
1079         DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
1080                  "chan_idle_dur:     %3d    chan_idle_dur_valid:     %1d\n",
1081                  (val[6] & 0x000003fc) >> 2, (val[6] & 0x00000400) >> 10);
1082         DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
1083                  "txfifo_valid_0:      %1d    txfifo_valid_1:          %1d\n",
1084                  (val[6] & 0x00000800) >> 11, (val[6] & 0x00001000) >> 12);
1085         DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
1086                  "txfifo_dcu_num_0:   %2d    txfifo_dcu_num_1:       %2d\n",
1087                  (val[6] & 0x0001e000) >> 13, (val[6] & 0x001e0000) >> 17);
1088
1089         DPRINTF(ah->ah_sc, ATH_DBG_REG_IO, "pcu observe 0x%x \n",
1090                 REG_READ(ah, AR_OBS_BUS_1));
1091         DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
1092                 "AR_CR 0x%x \n", REG_READ(ah, AR_CR));
1093 }
1094
1095 u32 ath9k_hw_GetMibCycleCountsPct(struct ath_hal *ah,
1096                                         u32 *rxc_pcnt,
1097                                         u32 *rxf_pcnt,
1098                                         u32 *txf_pcnt)
1099 {
1100         static u32 cycles, rx_clear, rx_frame, tx_frame;
1101         u32 good = 1;
1102
1103         u32 rc = REG_READ(ah, AR_RCCNT);
1104         u32 rf = REG_READ(ah, AR_RFCNT);
1105         u32 tf = REG_READ(ah, AR_TFCNT);
1106         u32 cc = REG_READ(ah, AR_CCCNT);
1107
1108         if (cycles == 0 || cycles > cc) {
1109                 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
1110                          "%s: cycle counter wrap. ExtBusy = 0\n",
1111                          __func__);
1112                 good = 0;
1113         } else {
1114                 u32 cc_d = cc - cycles;
1115                 u32 rc_d = rc - rx_clear;
1116                 u32 rf_d = rf - rx_frame;
1117                 u32 tf_d = tf - tx_frame;
1118
1119                 if (cc_d != 0) {
1120                         *rxc_pcnt = rc_d * 100 / cc_d;
1121                         *rxf_pcnt = rf_d * 100 / cc_d;
1122                         *txf_pcnt = tf_d * 100 / cc_d;
1123                 } else {
1124                         good = 0;
1125                 }
1126         }
1127
1128         cycles = cc;
1129         rx_frame = rf;
1130         rx_clear = rc;
1131         tx_frame = tf;
1132
1133         return good;
1134 }
1135
1136 void ath9k_hw_set11nmac2040(struct ath_hal *ah, enum ath9k_ht_macmode mode)
1137 {
1138         u32 macmode;
1139
1140         if (mode == ATH9K_HT_MACMODE_2040 &&
1141             !ah->ah_config.cwm_ignore_extcca)
1142                 macmode = AR_2040_JOINED_RX_CLEAR;
1143         else
1144                 macmode = 0;
1145
1146         REG_WRITE(ah, AR_2040_MODE, macmode);
1147 }
1148
1149 static void ath9k_hw_mark_phy_inactive(struct ath_hal *ah)
1150 {
1151         REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
1152 }
1153
1154
1155 static struct ath_hal_5416 *ath9k_hw_newstate(u16 devid,
1156                                               struct ath_softc *sc,
1157                                               void __iomem *mem,
1158                                               int *status)
1159 {
1160         static const u8 defbssidmask[ETH_ALEN] =
1161                 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
1162         struct ath_hal_5416 *ahp;
1163         struct ath_hal *ah;
1164
1165         ahp = kzalloc(sizeof(struct ath_hal_5416), GFP_KERNEL);
1166         if (ahp == NULL) {
1167                 DPRINTF(sc, ATH_DBG_FATAL,
1168                          "%s: cannot allocate memory for state block\n",
1169                          __func__);
1170                 *status = -ENOMEM;
1171                 return NULL;
1172         }
1173
1174         ah = &ahp->ah;
1175
1176         ah->ah_sc = sc;
1177         ah->ah_sh = mem;
1178
1179         ah->ah_magic = AR5416_MAGIC;
1180         ah->ah_countryCode = CTRY_DEFAULT;
1181
1182         ah->ah_devid = devid;
1183         ah->ah_subvendorid = 0;
1184
1185         ah->ah_flags = 0;
1186         if ((devid == AR5416_AR9100_DEVID))
1187                 ah->ah_macVersion = AR_SREV_VERSION_9100;
1188         if (!AR_SREV_9100(ah))
1189                 ah->ah_flags = AH_USE_EEPROM;
1190
1191         ah->ah_powerLimit = MAX_RATE_POWER;
1192         ah->ah_tpScale = ATH9K_TP_SCALE_MAX;
1193
1194         ahp->ah_atimWindow = 0;
1195         ahp->ah_diversityControl = ah->ah_config.diversity_control;
1196         ahp->ah_antennaSwitchSwap =
1197                 ah->ah_config.antenna_switch_swap;
1198
1199         ahp->ah_staId1Defaults = AR_STA_ID1_CRPT_MIC_ENABLE;
1200         ahp->ah_beaconInterval = 100;
1201         ahp->ah_enable32kHzClock = DONT_USE_32KHZ;
1202         ahp->ah_slottime = (u32) -1;
1203         ahp->ah_acktimeout = (u32) -1;
1204         ahp->ah_ctstimeout = (u32) -1;
1205         ahp->ah_globaltxtimeout = (u32) -1;
1206         memcpy(&ahp->ah_bssidmask, defbssidmask, ETH_ALEN);
1207
1208         ahp->ah_gBeaconRate = 0;
1209
1210         return ahp;
1211 }
1212
1213 static int ath9k_hw_eeprom_attach(struct ath_hal *ah)
1214 {
1215         int status;
1216
1217         if (ath9k_hw_use_flash(ah))
1218                 ath9k_hw_flash_map(ah);
1219
1220         if (!ath9k_hw_fill_eeprom(ah))
1221                 return -EIO;
1222
1223         status = ath9k_hw_check_eeprom(ah);
1224
1225         return status;
1226 }
1227
1228 u32 ath9k_hw_get_eeprom(struct ath_hal_5416 *ahp,
1229                               enum eeprom_param param)
1230 {
1231         struct ar5416_eeprom *eep = &ahp->ah_eeprom;
1232         struct modal_eep_header *pModal = eep->modalHeader;
1233         struct base_eep_header *pBase = &eep->baseEepHeader;
1234
1235         switch (param) {
1236         case EEP_NFTHRESH_5:
1237                 return -pModal[0].noiseFloorThreshCh[0];
1238         case EEP_NFTHRESH_2:
1239                 return -pModal[1].noiseFloorThreshCh[0];
1240         case AR_EEPROM_MAC(0):
1241                 return pBase->macAddr[0] << 8 | pBase->macAddr[1];
1242         case AR_EEPROM_MAC(1):
1243                 return pBase->macAddr[2] << 8 | pBase->macAddr[3];
1244         case AR_EEPROM_MAC(2):
1245                 return pBase->macAddr[4] << 8 | pBase->macAddr[5];
1246         case EEP_REG_0:
1247                 return pBase->regDmn[0];
1248         case EEP_REG_1:
1249                 return pBase->regDmn[1];
1250         case EEP_OP_CAP:
1251                 return pBase->deviceCap;
1252         case EEP_OP_MODE:
1253                 return pBase->opCapFlags;
1254         case EEP_RF_SILENT:
1255                 return pBase->rfSilent;
1256         case EEP_OB_5:
1257                 return pModal[0].ob;
1258         case EEP_DB_5:
1259                 return pModal[0].db;
1260         case EEP_OB_2:
1261                 return pModal[1].ob;
1262         case EEP_DB_2:
1263                 return pModal[1].db;
1264         case EEP_MINOR_REV:
1265                 return pBase->version & AR5416_EEP_VER_MINOR_MASK;
1266         case EEP_TX_MASK:
1267                 return pBase->txMask;
1268         case EEP_RX_MASK:
1269                 return pBase->rxMask;
1270         default:
1271                 return 0;
1272         }
1273 }
1274
1275 static int ath9k_hw_get_radiorev(struct ath_hal *ah)
1276 {
1277         u32 val;
1278         int i;
1279
1280         REG_WRITE(ah, AR_PHY(0x36), 0x00007058);
1281         for (i = 0; i < 8; i++)
1282                 REG_WRITE(ah, AR_PHY(0x20), 0x00010000);
1283         val = (REG_READ(ah, AR_PHY(256)) >> 24) & 0xff;
1284         val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4);
1285         return ath9k_hw_reverse_bits(val, 8);
1286 }
1287
1288 static int ath9k_hw_init_macaddr(struct ath_hal *ah)
1289 {
1290         u32 sum;
1291         int i;
1292         u16 eeval;
1293         struct ath_hal_5416 *ahp = AH5416(ah);
1294         DECLARE_MAC_BUF(mac);
1295
1296         sum = 0;
1297         for (i = 0; i < 3; i++) {
1298                 eeval = ath9k_hw_get_eeprom(ahp, AR_EEPROM_MAC(i));
1299                 sum += eeval;
1300                 ahp->ah_macaddr[2 * i] = eeval >> 8;
1301                 ahp->ah_macaddr[2 * i + 1] = eeval & 0xff;
1302         }
1303         if (sum == 0 || sum == 0xffff * 3) {
1304                 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1305                          "%s: mac address read failed: %s\n", __func__,
1306                          print_mac(mac, ahp->ah_macaddr));
1307                 return -EADDRNOTAVAIL;
1308         }
1309
1310         return 0;
1311 }
1312
1313 static inline int16_t ath9k_hw_interpolate(u16 target,
1314                                            u16 srcLeft,
1315                                            u16 srcRight,
1316                                            int16_t targetLeft,
1317                                            int16_t targetRight)
1318 {
1319         int16_t rv;
1320
1321         if (srcRight == srcLeft) {
1322                 rv = targetLeft;
1323         } else {
1324                 rv = (int16_t) (((target - srcLeft) * targetRight +
1325                                  (srcRight - target) * targetLeft) /
1326                                 (srcRight - srcLeft));
1327         }
1328         return rv;
1329 }
1330
1331 static inline u16 ath9k_hw_fbin2freq(u8 fbin,
1332                                            bool is2GHz)
1333 {
1334
1335         if (fbin == AR5416_BCHAN_UNUSED)
1336                 return fbin;
1337
1338         return (u16) ((is2GHz) ? (2300 + fbin) : (4800 + 5 * fbin));
1339 }
1340
1341 static u16 ath9k_hw_eeprom_get_spur_chan(struct ath_hal *ah,
1342                                                u16 i,
1343                                                bool is2GHz)
1344 {
1345         struct ath_hal_5416 *ahp = AH5416(ah);
1346         struct ar5416_eeprom *eep =
1347                 (struct ar5416_eeprom *) &ahp->ah_eeprom;
1348         u16 spur_val = AR_NO_SPUR;
1349
1350         DPRINTF(ah->ah_sc, ATH_DBG_ANI,
1351                  "Getting spur idx %d is2Ghz. %d val %x\n",
1352                  i, is2GHz, ah->ah_config.spurchans[i][is2GHz]);
1353
1354         switch (ah->ah_config.spurmode) {
1355         case SPUR_DISABLE:
1356                 break;
1357         case SPUR_ENABLE_IOCTL:
1358                 spur_val = ah->ah_config.spurchans[i][is2GHz];
1359                 DPRINTF(ah->ah_sc, ATH_DBG_ANI,
1360                          "Getting spur val from new loc. %d\n", spur_val);
1361                 break;
1362         case SPUR_ENABLE_EEPROM:
1363                 spur_val = eep->modalHeader[is2GHz].spurChans[i].spurChan;
1364                 break;
1365
1366         }
1367         return spur_val;
1368 }
1369
1370 static int ath9k_hw_rfattach(struct ath_hal *ah)
1371 {
1372         bool rfStatus = false;
1373         int ecode = 0;
1374
1375         rfStatus = ath9k_hw_init_rf(ah, &ecode);
1376         if (!rfStatus) {
1377                 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
1378                          "%s: RF setup failed, status %u\n", __func__,
1379                          ecode);
1380                 return ecode;
1381         }
1382
1383         return 0;
1384 }
1385
1386 static int ath9k_hw_rf_claim(struct ath_hal *ah)
1387 {
1388         u32 val;
1389
1390         REG_WRITE(ah, AR_PHY(0), 0x00000007);
1391
1392         val = ath9k_hw_get_radiorev(ah);
1393         switch (val & AR_RADIO_SREV_MAJOR) {
1394         case 0:
1395                 val = AR_RAD5133_SREV_MAJOR;
1396                 break;
1397         case AR_RAD5133_SREV_MAJOR:
1398         case AR_RAD5122_SREV_MAJOR:
1399         case AR_RAD2133_SREV_MAJOR:
1400         case AR_RAD2122_SREV_MAJOR:
1401                 break;
1402         default:
1403                 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
1404                          "%s: 5G Radio Chip Rev 0x%02X is not "
1405                         "supported by this driver\n",
1406                          __func__, ah->ah_analog5GhzRev);
1407                 return -EOPNOTSUPP;
1408         }
1409
1410         ah->ah_analog5GhzRev = val;
1411
1412         return 0;
1413 }
1414
1415 static void ath9k_hw_init_pll(struct ath_hal *ah,
1416                               struct ath9k_channel *chan)
1417 {
1418         u32 pll;
1419
1420         if (AR_SREV_9100(ah)) {
1421                 if (chan && IS_CHAN_5GHZ(chan))
1422                         pll = 0x1450;
1423                 else
1424                         pll = 0x1458;
1425         } else {
1426                 if (AR_SREV_9280_10_OR_LATER(ah)) {
1427                         pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
1428
1429                         if (chan && IS_CHAN_HALF_RATE(chan))
1430                                 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
1431                         else if (chan && IS_CHAN_QUARTER_RATE(chan))
1432                                 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
1433
1434                         if (chan && IS_CHAN_5GHZ(chan)) {
1435                                 pll |= SM(0x28, AR_RTC_9160_PLL_DIV);
1436
1437
1438                                 if (AR_SREV_9280_20(ah)) {
1439                                         if (((chan->channel % 20) == 0)
1440                                             || ((chan->channel % 10) == 0))
1441                                                 pll = 0x2850;
1442                                         else
1443                                                 pll = 0x142c;
1444                                 }
1445                         } else {
1446                                 pll |= SM(0x2c, AR_RTC_9160_PLL_DIV);
1447                         }
1448
1449                 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
1450
1451                         pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
1452
1453                         if (chan && IS_CHAN_HALF_RATE(chan))
1454                                 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
1455                         else if (chan && IS_CHAN_QUARTER_RATE(chan))
1456                                 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
1457
1458                         if (chan && IS_CHAN_5GHZ(chan))
1459                                 pll |= SM(0x50, AR_RTC_9160_PLL_DIV);
1460                         else
1461                                 pll |= SM(0x58, AR_RTC_9160_PLL_DIV);
1462                 } else {
1463                         pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2;
1464
1465                         if (chan && IS_CHAN_HALF_RATE(chan))
1466                                 pll |= SM(0x1, AR_RTC_PLL_CLKSEL);
1467                         else if (chan && IS_CHAN_QUARTER_RATE(chan))
1468                                 pll |= SM(0x2, AR_RTC_PLL_CLKSEL);
1469
1470                         if (chan && IS_CHAN_5GHZ(chan))
1471                                 pll |= SM(0xa, AR_RTC_PLL_DIV);
1472                         else
1473                                 pll |= SM(0xb, AR_RTC_PLL_DIV);
1474                 }
1475         }
1476         REG_WRITE(ah, (u16) (AR_RTC_PLL_CONTROL), pll);
1477
1478         udelay(RTC_PLL_SETTLE_DELAY);
1479
1480         REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
1481 }
1482
1483 static void ath9k_hw_set_regs(struct ath_hal *ah, struct ath9k_channel *chan,
1484                               enum ath9k_ht_macmode macmode)
1485 {
1486         u32 phymode;
1487         struct ath_hal_5416 *ahp = AH5416(ah);
1488
1489         phymode = AR_PHY_FC_HT_EN | AR_PHY_FC_SHORT_GI_40
1490                 | AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH;
1491
1492         if (IS_CHAN_HT40(chan)) {
1493                 phymode |= AR_PHY_FC_DYN2040_EN;
1494
1495                 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
1496                     (chan->chanmode == CHANNEL_G_HT40PLUS))
1497                         phymode |= AR_PHY_FC_DYN2040_PRI_CH;
1498
1499                 if (ahp->ah_extprotspacing == ATH9K_HT_EXTPROTSPACING_25)
1500                         phymode |= AR_PHY_FC_DYN2040_EXT_CH;
1501         }
1502         REG_WRITE(ah, AR_PHY_TURBO, phymode);
1503
1504         ath9k_hw_set11nmac2040(ah, macmode);
1505
1506         REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
1507         REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
1508 }
1509
1510 static void ath9k_hw_set_operating_mode(struct ath_hal *ah, int opmode)
1511 {
1512         u32 val;
1513
1514         val = REG_READ(ah, AR_STA_ID1);
1515         val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC);
1516         switch (opmode) {
1517         case ATH9K_M_HOSTAP:
1518                 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP
1519                           | AR_STA_ID1_KSRCH_MODE);
1520                 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1521                 break;
1522         case ATH9K_M_IBSS:
1523                 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC
1524                           | AR_STA_ID1_KSRCH_MODE);
1525                 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1526                 break;
1527         case ATH9K_M_STA:
1528         case ATH9K_M_MONITOR:
1529                 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE);
1530                 break;
1531         }
1532 }
1533
1534 static void
1535 ath9k_hw_set_rfmode(struct ath_hal *ah, struct ath9k_channel *chan)
1536 {
1537         u32 rfMode = 0;
1538
1539         if (chan == NULL)
1540                 return;
1541
1542         rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan))
1543                 ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
1544
1545         if (!AR_SREV_9280_10_OR_LATER(ah))
1546                 rfMode |= (IS_CHAN_5GHZ(chan)) ? AR_PHY_MODE_RF5GHZ :
1547                         AR_PHY_MODE_RF2GHZ;
1548
1549         if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan))
1550                 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
1551
1552         REG_WRITE(ah, AR_PHY_MODE, rfMode);
1553 }
1554
1555 static bool ath9k_hw_set_reset(struct ath_hal *ah, int type)
1556 {
1557         u32 rst_flags;
1558         u32 tmpReg;
1559
1560         REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1561                   AR_RTC_FORCE_WAKE_ON_INT);
1562
1563         if (AR_SREV_9100(ah)) {
1564                 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1565                         AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1566         } else {
1567                 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1568                 if (tmpReg &
1569                     (AR_INTR_SYNC_LOCAL_TIMEOUT |
1570                      AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
1571                         REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
1572                         REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
1573                 } else {
1574                         REG_WRITE(ah, AR_RC, AR_RC_AHB);
1575                 }
1576
1577                 rst_flags = AR_RTC_RC_MAC_WARM;
1578                 if (type == ATH9K_RESET_COLD)
1579                         rst_flags |= AR_RTC_RC_MAC_COLD;
1580         }
1581
1582         REG_WRITE(ah, (u16) (AR_RTC_RC), rst_flags);
1583         udelay(50);
1584
1585         REG_WRITE(ah, (u16) (AR_RTC_RC), 0);
1586         if (!ath9k_hw_wait(ah, (u16) (AR_RTC_RC), AR_RTC_RC_M, 0)) {
1587                 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
1588                         "%s: RTC stuck in MAC reset\n",
1589                         __func__);
1590                 return false;
1591         }
1592
1593         if (!AR_SREV_9100(ah))
1594                 REG_WRITE(ah, AR_RC, 0);
1595
1596         ath9k_hw_init_pll(ah, NULL);
1597
1598         if (AR_SREV_9100(ah))
1599                 udelay(50);
1600
1601         return true;
1602 }
1603
1604 static bool ath9k_hw_set_reset_power_on(struct ath_hal *ah)
1605 {
1606         REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1607                   AR_RTC_FORCE_WAKE_ON_INT);
1608
1609         REG_WRITE(ah, (u16) (AR_RTC_RESET), 0);
1610         REG_WRITE(ah, (u16) (AR_RTC_RESET), 1);
1611
1612         if (!ath9k_hw_wait(ah,
1613                            AR_RTC_STATUS,
1614                            AR_RTC_STATUS_M,
1615                            AR_RTC_STATUS_ON)) {
1616                 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "%s: RTC not waking up\n",
1617                          __func__);
1618                 return false;
1619         }
1620
1621         ath9k_hw_read_revisions(ah);
1622
1623         return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1624 }
1625
1626 static bool ath9k_hw_set_reset_reg(struct ath_hal *ah,
1627                                    u32 type)
1628 {
1629         REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1630                   AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1631
1632         switch (type) {
1633         case ATH9K_RESET_POWER_ON:
1634                 return ath9k_hw_set_reset_power_on(ah);
1635                 break;
1636         case ATH9K_RESET_WARM:
1637         case ATH9K_RESET_COLD:
1638                 return ath9k_hw_set_reset(ah, type);
1639                 break;
1640         default:
1641                 return false;
1642         }
1643 }
1644
1645 static
1646 struct ath9k_channel *ath9k_hw_check_chan(struct ath_hal *ah,
1647                                           struct ath9k_channel *chan)
1648 {
1649         if (!(IS_CHAN_2GHZ(chan) ^ IS_CHAN_5GHZ(chan))) {
1650                 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
1651                          "%s: invalid channel %u/0x%x; not marked as "
1652                          "2GHz or 5GHz\n", __func__, chan->channel,
1653                          chan->channelFlags);
1654                 return NULL;
1655         }
1656
1657         if (!IS_CHAN_OFDM(chan) &&
1658               !IS_CHAN_CCK(chan) &&
1659               !IS_CHAN_HT20(chan) &&
1660               !IS_CHAN_HT40(chan)) {
1661                 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
1662                         "%s: invalid channel %u/0x%x; not marked as "
1663                         "OFDM or CCK or HT20 or HT40PLUS or HT40MINUS\n",
1664                         __func__, chan->channel, chan->channelFlags);
1665                 return NULL;
1666         }
1667
1668         return ath9k_regd_check_channel(ah, chan);
1669 }
1670
1671 static inline bool
1672 ath9k_hw_get_lower_upper_index(u8 target,
1673                                u8 *pList,
1674                                u16 listSize,
1675                                u16 *indexL,
1676                                u16 *indexR)
1677 {
1678         u16 i;
1679
1680         if (target <= pList[0]) {
1681                 *indexL = *indexR = 0;
1682                 return true;
1683         }
1684         if (target >= pList[listSize - 1]) {
1685                 *indexL = *indexR = (u16) (listSize - 1);
1686                 return true;
1687         }
1688
1689         for (i = 0; i < listSize - 1; i++) {
1690                 if (pList[i] == target) {
1691                         *indexL = *indexR = i;
1692                         return true;
1693                 }
1694                 if (target < pList[i + 1]) {
1695                         *indexL = i;
1696                         *indexR = (u16) (i + 1);
1697                         return false;
1698                 }
1699         }
1700         return false;
1701 }
1702
1703 static int16_t ath9k_hw_get_nf_hist_mid(int16_t *nfCalBuffer)
1704 {
1705         int16_t nfval;
1706         int16_t sort[ATH9K_NF_CAL_HIST_MAX];
1707         int i, j;
1708
1709         for (i = 0; i < ATH9K_NF_CAL_HIST_MAX; i++)
1710                 sort[i] = nfCalBuffer[i];
1711
1712         for (i = 0; i < ATH9K_NF_CAL_HIST_MAX - 1; i++) {
1713                 for (j = 1; j < ATH9K_NF_CAL_HIST_MAX - i; j++) {
1714                         if (sort[j] > sort[j - 1]) {
1715                                 nfval = sort[j];
1716                                 sort[j] = sort[j - 1];
1717                                 sort[j - 1] = nfval;
1718                         }
1719                 }
1720         }
1721         nfval = sort[(ATH9K_NF_CAL_HIST_MAX - 1) >> 1];
1722
1723         return nfval;
1724 }
1725
1726 static void ath9k_hw_update_nfcal_hist_buffer(struct ath9k_nfcal_hist *h,
1727                                               int16_t *nfarray)
1728 {
1729         int i;
1730
1731         for (i = 0; i < NUM_NF_READINGS; i++) {
1732                 h[i].nfCalBuffer[h[i].currIndex] = nfarray[i];
1733
1734                 if (++h[i].currIndex >= ATH9K_NF_CAL_HIST_MAX)
1735                         h[i].currIndex = 0;
1736
1737                 if (h[i].invalidNFcount > 0) {
1738                         if (nfarray[i] < AR_PHY_CCA_MIN_BAD_VALUE
1739                             || nfarray[i] > AR_PHY_CCA_MAX_HIGH_VALUE) {
1740                                 h[i].invalidNFcount = ATH9K_NF_CAL_HIST_MAX;
1741                         } else {
1742                                 h[i].invalidNFcount--;
1743                                 h[i].privNF = nfarray[i];
1744                         }
1745                 } else {
1746                         h[i].privNF =
1747                                 ath9k_hw_get_nf_hist_mid(h[i].nfCalBuffer);
1748                 }
1749         }
1750         return;
1751 }
1752
1753 static void ar5416GetNoiseFloor(struct ath_hal *ah,
1754                                 int16_t nfarray[NUM_NF_READINGS])
1755 {
1756         int16_t nf;
1757
1758         if (AR_SREV_9280_10_OR_LATER(ah))
1759                 nf = MS(REG_READ(ah, AR_PHY_CCA), AR9280_PHY_MINCCA_PWR);
1760         else
1761                 nf = MS(REG_READ(ah, AR_PHY_CCA), AR_PHY_MINCCA_PWR);
1762
1763         if (nf & 0x100)
1764                 nf = 0 - ((nf ^ 0x1ff) + 1);
1765         DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
1766                  "NF calibrated [ctl] [chain 0] is %d\n", nf);
1767         nfarray[0] = nf;
1768
1769         if (AR_SREV_9280_10_OR_LATER(ah))
1770                 nf = MS(REG_READ(ah, AR_PHY_CH1_CCA),
1771                         AR9280_PHY_CH1_MINCCA_PWR);
1772         else
1773                 nf = MS(REG_READ(ah, AR_PHY_CH1_CCA),
1774                         AR_PHY_CH1_MINCCA_PWR);
1775
1776         if (nf & 0x100)
1777                 nf = 0 - ((nf ^ 0x1ff) + 1);
1778         DPRINTF(ah->ah_sc, ATH_DBG_NF_CAL,
1779                  "NF calibrated [ctl] [chain 1] is %d\n", nf);
1780         nfarray[1] = nf;
1781
1782         if (!AR_SREV_9280(ah)) {
1783                 nf = MS(REG_READ(ah, AR_PHY_CH2_CCA),
1784                         AR_PHY_CH2_MINCCA_PWR);
1785                 if (nf & 0x100)
1786                         nf = 0 - ((nf ^ 0x1ff) + 1);
1787                 DPRINTF(ah->ah_sc, ATH_DBG_NF_CAL,
1788                          "NF calibrated [ctl] [chain 2] is %d\n", nf);
1789                 nfarray[2] = nf;
1790         }
1791
1792         if (AR_SREV_9280_10_OR_LATER(ah))
1793                 nf = MS(REG_READ(ah, AR_PHY_EXT_CCA),
1794                         AR9280_PHY_EXT_MINCCA_PWR);
1795         else
1796                 nf = MS(REG_READ(ah, AR_PHY_EXT_CCA),
1797                         AR_PHY_EXT_MINCCA_PWR);
1798
1799         if (nf & 0x100)
1800                 nf = 0 - ((nf ^ 0x1ff) + 1);
1801         DPRINTF(ah->ah_sc, ATH_DBG_NF_CAL,
1802                  "NF calibrated [ext] [chain 0] is %d\n", nf);
1803         nfarray[3] = nf;
1804
1805         if (AR_SREV_9280_10_OR_LATER(ah))
1806                 nf = MS(REG_READ(ah, AR_PHY_CH1_EXT_CCA),
1807                         AR9280_PHY_CH1_EXT_MINCCA_PWR);
1808         else
1809                 nf = MS(REG_READ(ah, AR_PHY_CH1_EXT_CCA),
1810                         AR_PHY_CH1_EXT_MINCCA_PWR);
1811
1812         if (nf & 0x100)
1813                 nf = 0 - ((nf ^ 0x1ff) + 1);
1814         DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
1815                  "NF calibrated [ext] [chain 1] is %d\n", nf);
1816         nfarray[4] = nf;
1817
1818         if (!AR_SREV_9280(ah)) {
1819                 nf = MS(REG_READ(ah, AR_PHY_CH2_EXT_CCA),
1820                         AR_PHY_CH2_EXT_MINCCA_PWR);
1821                 if (nf & 0x100)
1822                         nf = 0 - ((nf ^ 0x1ff) + 1);
1823                 DPRINTF(ah->ah_sc, ATH_DBG_NF_CAL,
1824                          "NF calibrated [ext] [chain 2] is %d\n", nf);
1825                 nfarray[5] = nf;
1826         }
1827 }
1828
1829 static bool
1830 getNoiseFloorThresh(struct ath_hal *ah,
1831                     const struct ath9k_channel *chan,
1832                     int16_t *nft)
1833 {
1834         struct ath_hal_5416 *ahp = AH5416(ah);
1835
1836         switch (chan->chanmode) {
1837         case CHANNEL_A:
1838         case CHANNEL_A_HT20:
1839         case CHANNEL_A_HT40PLUS:
1840         case CHANNEL_A_HT40MINUS:
1841                 *nft = (int16_t) ath9k_hw_get_eeprom(ahp, EEP_NFTHRESH_5);
1842                 break;
1843         case CHANNEL_B:
1844         case CHANNEL_G:
1845         case CHANNEL_G_HT20:
1846         case CHANNEL_G_HT40PLUS:
1847         case CHANNEL_G_HT40MINUS:
1848                 *nft = (int16_t) ath9k_hw_get_eeprom(ahp, EEP_NFTHRESH_2);
1849                 break;
1850         default:
1851                 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
1852                          "%s: invalid channel flags 0x%x\n", __func__,
1853                          chan->channelFlags);
1854                 return false;
1855         }
1856         return true;
1857 }
1858
1859 static void ath9k_hw_start_nfcal(struct ath_hal *ah)
1860 {
1861         REG_SET_BIT(ah, AR_PHY_AGC_CONTROL,
1862                     AR_PHY_AGC_CONTROL_ENABLE_NF);
1863         REG_SET_BIT(ah, AR_PHY_AGC_CONTROL,
1864                     AR_PHY_AGC_CONTROL_NO_UPDATE_NF);
1865         REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);
1866 }
1867
1868 static void
1869 ath9k_hw_loadnf(struct ath_hal *ah, struct ath9k_channel *chan)
1870 {
1871         struct ath9k_nfcal_hist *h;
1872         int i, j;
1873         int32_t val;
1874         const u32 ar5416_cca_regs[6] = {
1875                 AR_PHY_CCA,
1876                 AR_PHY_CH1_CCA,
1877                 AR_PHY_CH2_CCA,
1878                 AR_PHY_EXT_CCA,
1879                 AR_PHY_CH1_EXT_CCA,
1880                 AR_PHY_CH2_EXT_CCA
1881         };
1882         u8 chainmask;
1883
1884         if (AR_SREV_9280(ah))
1885                 chainmask = 0x1B;
1886         else
1887                 chainmask = 0x3F;
1888
1889 #ifdef ATH_NF_PER_CHAN
1890         h = chan->nfCalHist;
1891 #else
1892         h = ah->nfCalHist;
1893 #endif
1894
1895         for (i = 0; i < NUM_NF_READINGS; i++) {
1896                 if (chainmask & (1 << i)) {
1897                         val = REG_READ(ah, ar5416_cca_regs[i]);
1898                         val &= 0xFFFFFE00;
1899                         val |= (((u32) (h[i].privNF) << 1) & 0x1ff);
1900                         REG_WRITE(ah, ar5416_cca_regs[i], val);
1901                 }
1902         }
1903
1904         REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
1905                     AR_PHY_AGC_CONTROL_ENABLE_NF);
1906         REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
1907                     AR_PHY_AGC_CONTROL_NO_UPDATE_NF);
1908         REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);
1909
1910         for (j = 0; j < 1000; j++) {
1911                 if ((REG_READ(ah, AR_PHY_AGC_CONTROL) &
1912                      AR_PHY_AGC_CONTROL_NF) == 0)
1913                         break;
1914                 udelay(10);
1915         }
1916
1917         for (i = 0; i < NUM_NF_READINGS; i++) {
1918                 if (chainmask & (1 << i)) {
1919                         val = REG_READ(ah, ar5416_cca_regs[i]);
1920                         val &= 0xFFFFFE00;
1921                         val |= (((u32) (-50) << 1) & 0x1ff);
1922                         REG_WRITE(ah, ar5416_cca_regs[i], val);
1923                 }
1924         }
1925 }
1926
1927 static int16_t ath9k_hw_getnf(struct ath_hal *ah,
1928                               struct ath9k_channel *chan)
1929 {
1930         int16_t nf, nfThresh;
1931         int16_t nfarray[NUM_NF_READINGS] = { 0 };
1932         struct ath9k_nfcal_hist *h;
1933         u8 chainmask;
1934
1935         if (AR_SREV_9280(ah))
1936                 chainmask = 0x1B;
1937         else
1938                 chainmask = 0x3F;
1939
1940         chan->channelFlags &= (~CHANNEL_CW_INT);
1941         if (REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF) {
1942                 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
1943                          "%s: NF did not complete in calibration window\n",
1944                          __func__);
1945                 nf = 0;
1946                 chan->rawNoiseFloor = nf;
1947                 return chan->rawNoiseFloor;
1948         } else {
1949                 ar5416GetNoiseFloor(ah, nfarray);
1950                 nf = nfarray[0];
1951                 if (getNoiseFloorThresh(ah, chan, &nfThresh)
1952                     && nf > nfThresh) {
1953                         DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
1954                                  "%s: noise floor failed detected; "
1955                                  "detected %d, threshold %d\n", __func__,
1956                                  nf, nfThresh);
1957                         chan->channelFlags |= CHANNEL_CW_INT;
1958                 }
1959         }
1960
1961 #ifdef ATH_NF_PER_CHAN
1962         h = chan->nfCalHist;
1963 #else
1964         h = ah->nfCalHist;
1965 #endif
1966
1967         ath9k_hw_update_nfcal_hist_buffer(h, nfarray);
1968         chan->rawNoiseFloor = h[0].privNF;
1969
1970         return chan->rawNoiseFloor;
1971 }
1972
1973 static void ath9k_hw_update_mibstats(struct ath_hal *ah,
1974                               struct ath9k_mib_stats *stats)
1975 {
1976         stats->ackrcv_bad += REG_READ(ah, AR_ACK_FAIL);
1977         stats->rts_bad += REG_READ(ah, AR_RTS_FAIL);
1978         stats->fcs_bad += REG_READ(ah, AR_FCS_FAIL);
1979         stats->rts_good += REG_READ(ah, AR_RTS_OK);
1980         stats->beacons += REG_READ(ah, AR_BEACON_CNT);
1981 }
1982
1983 static void ath9k_enable_mib_counters(struct ath_hal *ah)
1984 {
1985         struct ath_hal_5416 *ahp = AH5416(ah);
1986
1987         DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Enable mib counters\n");
1988
1989         ath9k_hw_update_mibstats(ah, &ahp->ah_mibStats);
1990
1991         REG_WRITE(ah, AR_FILT_OFDM, 0);
1992         REG_WRITE(ah, AR_FILT_CCK, 0);
1993         REG_WRITE(ah, AR_MIBC,
1994                   ~(AR_MIBC_COW | AR_MIBC_FMC | AR_MIBC_CMC | AR_MIBC_MCS)
1995                   & 0x0f);
1996         REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING);
1997         REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING);
1998 }
1999
2000 static void ath9k_hw_disable_mib_counters(struct ath_hal *ah)
2001 {
2002         struct ath_hal_5416 *ahp = AH5416(ah);
2003
2004         DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Disabling MIB counters\n");
2005
2006         REG_WRITE(ah, AR_MIBC, AR_MIBC_FMC | AR_MIBC_CMC);
2007
2008         ath9k_hw_update_mibstats(ah, &ahp->ah_mibStats);
2009
2010         REG_WRITE(ah, AR_FILT_OFDM, 0);
2011         REG_WRITE(ah, AR_FILT_CCK, 0);
2012 }
2013
2014 static int ath9k_hw_get_ani_channel_idx(struct ath_hal *ah,
2015                                         struct ath9k_channel *chan)
2016 {
2017         struct ath_hal_5416 *ahp = AH5416(ah);
2018         int i;
2019
2020         for (i = 0; i < ARRAY_SIZE(ahp->ah_ani); i++) {
2021                 if (ahp->ah_ani[i].c.channel == chan->channel)
2022                         return i;
2023                 if (ahp->ah_ani[i].c.channel == 0) {
2024                         ahp->ah_ani[i].c.channel = chan->channel;
2025                         ahp->ah_ani[i].c.channelFlags = chan->channelFlags;
2026                         return i;
2027                 }
2028         }
2029
2030         DPRINTF(ah->ah_sc, ATH_DBG_ANI,
2031                  "No more channel states left. Using channel 0\n");
2032         return 0;
2033 }
2034
2035 static void ath9k_hw_ani_attach(struct ath_hal *ah)
2036 {
2037         struct ath_hal_5416 *ahp = AH5416(ah);
2038         int i;
2039
2040         ahp->ah_hasHwPhyCounters = 1;
2041
2042         memset(ahp->ah_ani, 0, sizeof(ahp->ah_ani));
2043         for (i = 0; i < ARRAY_SIZE(ahp->ah_ani); i++) {
2044                 ahp->ah_ani[i].ofdmTrigHigh = ATH9K_ANI_OFDM_TRIG_HIGH;
2045                 ahp->ah_ani[i].ofdmTrigLow = ATH9K_ANI_OFDM_TRIG_LOW;
2046                 ahp->ah_ani[i].cckTrigHigh = ATH9K_ANI_CCK_TRIG_HIGH;
2047                 ahp->ah_ani[i].cckTrigLow = ATH9K_ANI_CCK_TRIG_LOW;
2048                 ahp->ah_ani[i].rssiThrHigh = ATH9K_ANI_RSSI_THR_HIGH;
2049                 ahp->ah_ani[i].rssiThrLow = ATH9K_ANI_RSSI_THR_LOW;
2050                 ahp->ah_ani[i].ofdmWeakSigDetectOff =
2051                         !ATH9K_ANI_USE_OFDM_WEAK_SIG;
2052                 ahp->ah_ani[i].cckWeakSigThreshold =
2053                         ATH9K_ANI_CCK_WEAK_SIG_THR;
2054                 ahp->ah_ani[i].spurImmunityLevel = ATH9K_ANI_SPUR_IMMUNE_LVL;
2055                 ahp->ah_ani[i].firstepLevel = ATH9K_ANI_FIRSTEP_LVL;
2056                 if (ahp->ah_hasHwPhyCounters) {
2057                         ahp->ah_ani[i].ofdmPhyErrBase =
2058                                 AR_PHY_COUNTMAX - ATH9K_ANI_OFDM_TRIG_HIGH;
2059                         ahp->ah_ani[i].cckPhyErrBase =
2060                                 AR_PHY_COUNTMAX - ATH9K_ANI_CCK_TRIG_HIGH;
2061                 }
2062         }
2063         if (ahp->ah_hasHwPhyCounters) {
2064                 DPRINTF(ah->ah_sc, ATH_DBG_ANI,
2065                         "Setting OfdmErrBase = 0x%08x\n",
2066                         ahp->ah_ani[0].ofdmPhyErrBase);
2067                 DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Setting cckErrBase = 0x%08x\n",
2068                         ahp->ah_ani[0].cckPhyErrBase);
2069
2070                 REG_WRITE(ah, AR_PHY_ERR_1, ahp->ah_ani[0].ofdmPhyErrBase);
2071                 REG_WRITE(ah, AR_PHY_ERR_2, ahp->ah_ani[0].cckPhyErrBase);
2072                 ath9k_enable_mib_counters(ah);
2073         }
2074         ahp->ah_aniPeriod = ATH9K_ANI_PERIOD;
2075         if (ah->ah_config.enable_ani)
2076                 ahp->ah_procPhyErr |= HAL_PROCESS_ANI;
2077 }
2078
2079 static void ath9k_hw_ani_setup(struct ath_hal *ah)
2080 {
2081         struct ath_hal_5416 *ahp = AH5416(ah);
2082         int i;
2083
2084         const int totalSizeDesired[] = { -55, -55, -55, -55, -62 };
2085         const int coarseHigh[] = { -14, -14, -14, -14, -12 };
2086         const int coarseLow[] = { -64, -64, -64, -64, -70 };
2087         const int firpwr[] = { -78, -78, -78, -78, -80 };
2088
2089         for (i = 0; i < 5; i++) {
2090                 ahp->ah_totalSizeDesired[i] = totalSizeDesired[i];
2091                 ahp->ah_coarseHigh[i] = coarseHigh[i];
2092                 ahp->ah_coarseLow[i] = coarseLow[i];
2093                 ahp->ah_firpwr[i] = firpwr[i];
2094         }
2095 }
2096
2097 static void ath9k_hw_ani_detach(struct ath_hal *ah)
2098 {
2099         struct ath_hal_5416 *ahp = AH5416(ah);
2100
2101         DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Detaching Ani\n");
2102         if (ahp->ah_hasHwPhyCounters) {
2103                 ath9k_hw_disable_mib_counters(ah);
2104                 REG_WRITE(ah, AR_PHY_ERR_1, 0);
2105                 REG_WRITE(ah, AR_PHY_ERR_2, 0);
2106         }
2107 }
2108
2109
2110 static bool ath9k_hw_ani_control(struct ath_hal *ah,
2111                                  enum ath9k_ani_cmd cmd, int param)
2112 {
2113         struct ath_hal_5416 *ahp = AH5416(ah);
2114         struct ar5416AniState *aniState = ahp->ah_curani;
2115
2116         switch (cmd & ahp->ah_ani_function) {
2117         case ATH9K_ANI_NOISE_IMMUNITY_LEVEL:{
2118                 u32 level = param;
2119
2120                 if (level >= ARRAY_SIZE(ahp->ah_totalSizeDesired)) {
2121                         DPRINTF(ah->ah_sc, ATH_DBG_ANI,
2122                                  "%s: level out of range (%u > %u)\n",
2123                                  __func__, level,
2124                                  (unsigned) ARRAY_SIZE(ahp->
2125                                                        ah_totalSizeDesired));
2126                         return false;
2127                 }
2128
2129                 REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ,
2130                               AR_PHY_DESIRED_SZ_TOT_DES,
2131                               ahp->ah_totalSizeDesired[level]);
2132                 REG_RMW_FIELD(ah, AR_PHY_AGC_CTL1,
2133                               AR_PHY_AGC_CTL1_COARSE_LOW,
2134                               ahp->ah_coarseLow[level]);
2135                 REG_RMW_FIELD(ah, AR_PHY_AGC_CTL1,
2136                               AR_PHY_AGC_CTL1_COARSE_HIGH,
2137                               ahp->ah_coarseHigh[level]);
2138                 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
2139                               AR_PHY_FIND_SIG_FIRPWR,
2140                               ahp->ah_firpwr[level]);
2141
2142                 if (level > aniState->noiseImmunityLevel)
2143                         ahp->ah_stats.ast_ani_niup++;
2144                 else if (level < aniState->noiseImmunityLevel)
2145                         ahp->ah_stats.ast_ani_nidown++;
2146                 aniState->noiseImmunityLevel = level;
2147                 break;
2148         }
2149         case ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION:{
2150                 const int m1ThreshLow[] = { 127, 50 };
2151                 const int m2ThreshLow[] = { 127, 40 };
2152                 const int m1Thresh[] = { 127, 0x4d };
2153                 const int m2Thresh[] = { 127, 0x40 };
2154                 const int m2CountThr[] = { 31, 16 };
2155                 const int m2CountThrLow[] = { 63, 48 };
2156                 u32 on = param ? 1 : 0;
2157
2158                 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
2159                               AR_PHY_SFCORR_LOW_M1_THRESH_LOW,
2160                               m1ThreshLow[on]);
2161                 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
2162                               AR_PHY_SFCORR_LOW_M2_THRESH_LOW,
2163                               m2ThreshLow[on]);
2164                 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
2165                               AR_PHY_SFCORR_M1_THRESH,
2166                               m1Thresh[on]);
2167                 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
2168                               AR_PHY_SFCORR_M2_THRESH,
2169                               m2Thresh[on]);
2170                 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
2171                               AR_PHY_SFCORR_M2COUNT_THR,
2172                               m2CountThr[on]);
2173                 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
2174                               AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW,
2175                               m2CountThrLow[on]);
2176
2177                 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
2178                               AR_PHY_SFCORR_EXT_M1_THRESH_LOW,
2179                               m1ThreshLow[on]);
2180                 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
2181                               AR_PHY_SFCORR_EXT_M2_THRESH_LOW,
2182                               m2ThreshLow[on]);
2183                 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
2184                               AR_PHY_SFCORR_EXT_M1_THRESH,
2185                               m1Thresh[on]);
2186                 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
2187                               AR_PHY_SFCORR_EXT_M2_THRESH,
2188                               m2Thresh[on]);
2189
2190                 if (on)
2191                         REG_SET_BIT(ah, AR_PHY_SFCORR_LOW,
2192                                     AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
2193                 else
2194                         REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW,
2195                                     AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
2196
2197                 if (!on != aniState->ofdmWeakSigDetectOff) {
2198                         if (on)
2199                                 ahp->ah_stats.ast_ani_ofdmon++;
2200                         else
2201                                 ahp->ah_stats.ast_ani_ofdmoff++;
2202                         aniState->ofdmWeakSigDetectOff = !on;
2203                 }
2204                 break;
2205         }
2206         case ATH9K_ANI_CCK_WEAK_SIGNAL_THR:{
2207                 const int weakSigThrCck[] = { 8, 6 };
2208                 u32 high = param ? 1 : 0;
2209
2210                 REG_RMW_FIELD(ah, AR_PHY_CCK_DETECT,
2211                               AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK,
2212                               weakSigThrCck[high]);
2213                 if (high != aniState->cckWeakSigThreshold) {
2214                         if (high)
2215                                 ahp->ah_stats.ast_ani_cckhigh++;
2216                         else
2217                                 ahp->ah_stats.ast_ani_ccklow++;
2218                         aniState->cckWeakSigThreshold = high;
2219                 }
2220                 break;
2221         }
2222         case ATH9K_ANI_FIRSTEP_LEVEL:{
2223                 const int firstep[] = { 0, 4, 8 };
2224                 u32 level = param;
2225
2226                 if (level >= ARRAY_SIZE(firstep)) {
2227                         DPRINTF(ah->ah_sc, ATH_DBG_ANI,
2228                                  "%s: level out of range (%u > %u)\n",
2229                                  __func__, level,
2230                                 (unsigned) ARRAY_SIZE(firstep));
2231                         return false;
2232                 }
2233                 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
2234                               AR_PHY_FIND_SIG_FIRSTEP,
2235                               firstep[level]);
2236                 if (level > aniState->firstepLevel)
2237                         ahp->ah_stats.ast_ani_stepup++;
2238                 else if (level < aniState->firstepLevel)
2239                         ahp->ah_stats.ast_ani_stepdown++;
2240                 aniState->firstepLevel = level;
2241                 break;
2242         }
2243         case ATH9K_ANI_SPUR_IMMUNITY_LEVEL:{
2244                 const int cycpwrThr1[] =
2245                         { 2, 4, 6, 8, 10, 12, 14, 16 };
2246                 u32 level = param;
2247
2248                 if (level >= ARRAY_SIZE(cycpwrThr1)) {
2249                         DPRINTF(ah->ah_sc, ATH_DBG_ANI,
2250                                  "%s: level out of range (%u > %u)\n",
2251                                  __func__, level,
2252                                  (unsigned)
2253                                 ARRAY_SIZE(cycpwrThr1));
2254                         return false;
2255                 }
2256                 REG_RMW_FIELD(ah, AR_PHY_TIMING5,
2257                               AR_PHY_TIMING5_CYCPWR_THR1,
2258                               cycpwrThr1[level]);
2259                 if (level > aniState->spurImmunityLevel)
2260                         ahp->ah_stats.ast_ani_spurup++;
2261                 else if (level < aniState->spurImmunityLevel)
2262                         ahp->ah_stats.ast_ani_spurdown++;
2263                 aniState->spurImmunityLevel = level;
2264                 break;
2265         }
2266         case ATH9K_ANI_PRESENT:
2267                 break;
2268         default:
2269                 DPRINTF(ah->ah_sc, ATH_DBG_ANI,
2270                         "%s: invalid cmd %u\n", __func__, cmd);
2271                 return false;
2272         }
2273
2274         DPRINTF(ah->ah_sc, ATH_DBG_ANI, "%s: ANI parameters:\n", __func__);
2275         DPRINTF(ah->ah_sc, ATH_DBG_ANI,
2276                 "noiseImmunityLevel=%d, spurImmunityLevel=%d, "
2277                 "ofdmWeakSigDetectOff=%d\n",
2278                  aniState->noiseImmunityLevel, aniState->spurImmunityLevel,
2279                  !aniState->ofdmWeakSigDetectOff);
2280         DPRINTF(ah->ah_sc, ATH_DBG_ANI,
2281                 "cckWeakSigThreshold=%d, "
2282                 "firstepLevel=%d, listenTime=%d\n",
2283                  aniState->cckWeakSigThreshold, aniState->firstepLevel,
2284                  aniState->listenTime);
2285         DPRINTF(ah->ah_sc, ATH_DBG_ANI,
2286                  "cycleCount=%d, ofdmPhyErrCount=%d, cckPhyErrCount=%d\n\n",
2287                  aniState->cycleCount, aniState->ofdmPhyErrCount,
2288                  aniState->cckPhyErrCount);
2289         return true;
2290 }
2291
2292 static void ath9k_ani_restart(struct ath_hal *ah)
2293 {
2294         struct ath_hal_5416 *ahp = AH5416(ah);
2295         struct ar5416AniState *aniState;
2296
2297         if (!DO_ANI(ah))
2298                 return;
2299
2300         aniState = ahp->ah_curani;
2301
2302         aniState->listenTime = 0;
2303         if (ahp->ah_hasHwPhyCounters) {
2304                 if (aniState->ofdmTrigHigh > AR_PHY_COUNTMAX) {
2305                         aniState->ofdmPhyErrBase = 0;
2306                         DPRINTF(ah->ah_sc, ATH_DBG_ANI,
2307                                  "OFDM Trigger is too high for hw counters\n");
2308                 } else {
2309                         aniState->ofdmPhyErrBase =
2310                                 AR_PHY_COUNTMAX - aniState->ofdmTrigHigh;
2311                 }
2312                 if (aniState->cckTrigHigh > AR_PHY_COUNTMAX) {
2313                         aniState->cckPhyErrBase = 0;
2314                         DPRINTF(ah->ah_sc, ATH_DBG_ANI,
2315                                  "CCK Trigger is too high for hw counters\n");
2316                 } else {
2317                         aniState->cckPhyErrBase =
2318                                 AR_PHY_COUNTMAX - aniState->cckTrigHigh;
2319                 }
2320                 DPRINTF(ah->ah_sc, ATH_DBG_ANI,
2321                          "%s: Writing ofdmbase=%u   cckbase=%u\n",
2322                          __func__, aniState->ofdmPhyErrBase,
2323                          aniState->cckPhyErrBase);
2324                 REG_WRITE(ah, AR_PHY_ERR_1, aniState->ofdmPhyErrBase);
2325                 REG_WRITE(ah, AR_PHY_ERR_2, aniState->cckPhyErrBase);
2326                 REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING);
2327                 REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING);
2328
2329                 ath9k_hw_update_mibstats(ah, &ahp->ah_mibStats);
2330         }
2331         aniState->ofdmPhyErrCount = 0;
2332         aniState->cckPhyErrCount = 0;
2333 }
2334
2335 static void ath9k_hw_ani_ofdm_err_trigger(struct ath_hal *ah)
2336 {
2337         struct ath_hal_5416 *ahp = AH5416(ah);
2338         struct ath9k_channel *chan = ah->ah_curchan;
2339         struct ar5416AniState *aniState;
2340         enum wireless_mode mode;
2341         int32_t rssi;
2342
2343         if (!DO_ANI(ah))
2344                 return;
2345
2346         aniState = ahp->ah_curani;
2347
2348         if (aniState->noiseImmunityLevel < HAL_NOISE_IMMUNE_MAX) {
2349                 if (ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL,
2350                                          aniState->noiseImmunityLevel + 1)) {
2351                         return;
2352                 }
2353         }
2354
2355         if (aniState->spurImmunityLevel < HAL_SPUR_IMMUNE_MAX) {
2356                 if (ath9k_hw_ani_control(ah, ATH9K_ANI_SPUR_IMMUNITY_LEVEL,
2357                                          aniState->spurImmunityLevel + 1)) {
2358                         return;
2359                 }
2360         }
2361
2362         if (ah->ah_opmode == ATH9K_M_HOSTAP) {
2363                 if (aniState->firstepLevel < HAL_FIRST_STEP_MAX) {
2364                         ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL,
2365                                              aniState->firstepLevel + 1);
2366                 }
2367                 return;
2368         }
2369         rssi = BEACON_RSSI(ahp);
2370         if (rssi > aniState->rssiThrHigh) {
2371                 if (!aniState->ofdmWeakSigDetectOff) {
2372                         if (ath9k_hw_ani_control(ah,
2373                                          ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION,
2374                                          false)) {
2375                                 ath9k_hw_ani_control(ah,
2376                                         ATH9K_ANI_SPUR_IMMUNITY_LEVEL,
2377                                         0);
2378                                 return;
2379                         }
2380                 }
2381                 if (aniState->firstepLevel < HAL_FIRST_STEP_MAX) {
2382                         ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL,
2383                                              aniState->firstepLevel + 1);
2384                         return;
2385                 }
2386         } else if (rssi > aniState->rssiThrLow) {
2387                 if (aniState->ofdmWeakSigDetectOff)
2388                         ath9k_hw_ani_control(ah,
2389                                      ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION,
2390                                      true);
2391                 if (aniState->firstepLevel < HAL_FIRST_STEP_MAX)
2392                         ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL,
2393                                              aniState->firstepLevel + 1);
2394                 return;
2395         } else {
2396                 mode = ath9k_hw_chan2wmode(ah, chan);
2397                 if (mode == ATH9K_MODE_11G || mode == ATH9K_MODE_11B) {
2398                         if (!aniState->ofdmWeakSigDetectOff)
2399                                 ath9k_hw_ani_control(ah,
2400                                      ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION,
2401                                      false);
2402                         if (aniState->firstepLevel > 0)
2403                                 ath9k_hw_ani_control(ah,
2404                                                      ATH9K_ANI_FIRSTEP_LEVEL,
2405                                                      0);
2406                         return;
2407                 }
2408         }
2409 }
2410
2411 static void ath9k_hw_ani_cck_err_trigger(struct ath_hal *ah)
2412 {
2413         struct ath_hal_5416 *ahp = AH5416(ah);
2414         struct ath9k_channel *chan = ah->ah_curchan;
2415         struct ar5416AniState *aniState;
2416         enum wireless_mode mode;
2417         int32_t rssi;
2418
2419         if (!DO_ANI(ah))
2420                 return;
2421
2422         aniState = ahp->ah_curani;
2423         if (aniState->noiseImmunityLevel < HAL_NOISE_IMMUNE_MAX) {
2424                 if (ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL,
2425                                          aniState->noiseImmunityLevel + 1)) {
2426                         return;
2427                 }
2428         }
2429         if (ah->ah_opmode == ATH9K_M_HOSTAP) {
2430                 if (aniState->firstepLevel < HAL_FIRST_STEP_MAX) {
2431                         ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL,
2432                                              aniState->firstepLevel + 1);
2433                 }
2434                 return;
2435         }
2436         rssi = BEACON_RSSI(ahp);
2437         if (rssi > aniState->rssiThrLow) {
2438                 if (aniState->firstepLevel < HAL_FIRST_STEP_MAX)
2439                         ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL,
2440                                              aniState->firstepLevel + 1);
2441         } else {
2442                 mode = ath9k_hw_chan2wmode(ah, chan);
2443                 if (mode == ATH9K_MODE_11G || mode == ATH9K_MODE_11B) {
2444                         if (aniState->firstepLevel > 0)
2445                                 ath9k_hw_ani_control(ah,
2446                                                      ATH9K_ANI_FIRSTEP_LEVEL,
2447                                                      0);
2448                 }
2449         }
2450 }
2451
2452 static void ath9k_ani_reset(struct ath_hal *ah)
2453 {
2454         struct ath_hal_5416 *ahp = AH5416(ah);
2455         struct ar5416AniState *aniState;
2456         struct ath9k_channel *chan = ah->ah_curchan;
2457         int index;
2458
2459         if (!DO_ANI(ah))
2460                 return;
2461
2462         index = ath9k_hw_get_ani_channel_idx(ah, chan);
2463         aniState = &ahp->ah_ani[index];
2464         ahp->ah_curani = aniState;
2465
2466         if (DO_ANI(ah) && ah->ah_opmode != ATH9K_M_STA
2467             && ah->ah_opmode != ATH9K_M_IBSS) {
2468                 DPRINTF(ah->ah_sc, ATH_DBG_ANI,
2469                          "%s: Reset ANI state opmode %u\n", __func__,
2470                          ah->ah_opmode);
2471                 ahp->ah_stats.ast_ani_reset++;
2472                 ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL, 0);
2473                 ath9k_hw_ani_control(ah, ATH9K_ANI_SPUR_IMMUNITY_LEVEL, 0);
2474                 ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL, 0);
2475                 ath9k_hw_ani_control(ah,
2476                                      ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION,
2477                                      !ATH9K_ANI_USE_OFDM_WEAK_SIG);
2478                 ath9k_hw_ani_control(ah, ATH9K_ANI_CCK_WEAK_SIGNAL_THR,
2479                                      ATH9K_ANI_CCK_WEAK_SIG_THR);
2480                 ath9k_hw_setrxfilter(ah,
2481                                      ath9k_hw_getrxfilter(ah) |
2482                                      ATH9K_RX_FILTER_PHYERR);
2483                 if (ah->ah_opmode == ATH9K_M_HOSTAP) {
2484                         ahp->ah_curani->ofdmTrigHigh =
2485                                 ah->ah_config.ofdm_trig_high;
2486                         ahp->ah_curani->ofdmTrigLow =
2487                                 ah->ah_config.ofdm_trig_low;
2488                         ahp->ah_curani->cckTrigHigh =
2489                                 ah->ah_config.cck_trig_high;
2490                         ahp->ah_curani->cckTrigLow =
2491                                 ah->ah_config.cck_trig_low;
2492                 }
2493                 ath9k_ani_restart(ah);
2494                 return;
2495         }
2496
2497         if (aniState->noiseImmunityLevel != 0)
2498                 ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL,
2499                                      aniState->noiseImmunityLevel);
2500         if (aniState->spurImmunityLevel != 0)
2501                 ath9k_hw_ani_control(ah, ATH9K_ANI_SPUR_IMMUNITY_LEVEL,
2502                                      aniState->spurImmunityLevel);
2503         if (aniState->ofdmWeakSigDetectOff)
2504                 ath9k_hw_ani_control(ah,
2505                                      ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION,
2506                                      !aniState->ofdmWeakSigDetectOff);
2507         if (aniState->cckWeakSigThreshold)
2508                 ath9k_hw_ani_control(ah, ATH9K_ANI_CCK_WEAK_SIGNAL_THR,
2509                                      aniState->cckWeakSigThreshold);
2510         if (aniState->firstepLevel != 0)
2511                 ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL,
2512                                      aniState->firstepLevel);
2513         if (ahp->ah_hasHwPhyCounters) {
2514                 ath9k_hw_setrxfilter(ah,
2515                                      ath9k_hw_getrxfilter(ah) &
2516                                      ~ATH9K_RX_FILTER_PHYERR);
2517                 ath9k_ani_restart(ah);
2518                 REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING);
2519                 REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING);
2520
2521         } else {
2522                 ath9k_ani_restart(ah);
2523                 ath9k_hw_setrxfilter(ah,
2524                                      ath9k_hw_getrxfilter(ah) |
2525                                      ATH9K_RX_FILTER_PHYERR);
2526         }
2527 }
2528
2529 void ath9k_hw_procmibevent(struct ath_hal *ah,
2530                            const struct ath9k_node_stats *stats)
2531 {
2532         struct ath_hal_5416 *ahp = AH5416(ah);
2533         u32 phyCnt1, phyCnt2;
2534
2535         DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Processing Mib Intr\n");
2536
2537         REG_WRITE(ah, AR_FILT_OFDM, 0);
2538         REG_WRITE(ah, AR_FILT_CCK, 0);
2539         if (!(REG_READ(ah, AR_SLP_MIB_CTRL) & AR_SLP_MIB_PENDING))
2540                 REG_WRITE(ah, AR_SLP_MIB_CTRL, AR_SLP_MIB_CLEAR);
2541
2542         ath9k_hw_update_mibstats(ah, &ahp->ah_mibStats);
2543         ahp->ah_stats.ast_nodestats = *stats;
2544
2545         if (!DO_ANI(ah))
2546                 return;
2547
2548         phyCnt1 = REG_READ(ah, AR_PHY_ERR_1);
2549         phyCnt2 = REG_READ(ah, AR_PHY_ERR_2);
2550         if (((phyCnt1 & AR_MIBCNT_INTRMASK) == AR_MIBCNT_INTRMASK) ||
2551             ((phyCnt2 & AR_MIBCNT_INTRMASK) == AR_MIBCNT_INTRMASK)) {
2552                 struct ar5416AniState *aniState = ahp->ah_curani;
2553                 u32 ofdmPhyErrCnt, cckPhyErrCnt;
2554
2555                 ofdmPhyErrCnt = phyCnt1 - aniState->ofdmPhyErrBase;
2556                 ahp->ah_stats.ast_ani_ofdmerrs +=
2557                         ofdmPhyErrCnt - aniState->ofdmPhyErrCount;
2558                 aniState->ofdmPhyErrCount = ofdmPhyErrCnt;
2559
2560                 cckPhyErrCnt = phyCnt2 - aniState->cckPhyErrBase;
2561                 ahp->ah_stats.ast_ani_cckerrs +=
2562                         cckPhyErrCnt - aniState->cckPhyErrCount;
2563                 aniState->cckPhyErrCount = cckPhyErrCnt;
2564
2565                 if (aniState->ofdmPhyErrCount > aniState->ofdmTrigHigh)
2566                         ath9k_hw_ani_ofdm_err_trigger(ah);
2567                 if (aniState->cckPhyErrCount > aniState->cckTrigHigh)
2568                         ath9k_hw_ani_cck_err_trigger(ah);
2569
2570                 ath9k_ani_restart(ah);
2571         }
2572 }
2573
2574 static void ath9k_hw_ani_lower_immunity(struct ath_hal *ah)
2575 {
2576         struct ath_hal_5416 *ahp = AH5416(ah);
2577         struct ar5416AniState *aniState;
2578         int32_t rssi;
2579
2580         aniState = ahp->ah_curani;
2581
2582         if (ah->ah_opmode == ATH9K_M_HOSTAP) {
2583                 if (aniState->firstepLevel > 0) {
2584                         if (ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL,
2585                                                  aniState->firstepLevel - 1)) {
2586                                 return;
2587                         }
2588                 }
2589         } else {
2590                 rssi = BEACON_RSSI(ahp);
2591                 if (rssi > aniState->rssiThrHigh) {
2592                         /* XXX: Handle me */
2593                 } else if (rssi > aniState->rssiThrLow) {
2594                         if (aniState->ofdmWeakSigDetectOff) {
2595                                 if (ath9k_hw_ani_control(ah,
2596                                          ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION,
2597                                          true) ==
2598                                     true) {
2599                                         return;
2600                                 }
2601                         }
2602                         if (aniState->firstepLevel > 0) {
2603                                 if (ath9k_hw_ani_control
2604                                     (ah, ATH9K_ANI_FIRSTEP_LEVEL,
2605                                      aniState->firstepLevel - 1) ==
2606                                     true) {
2607                                         return;
2608                                 }
2609                         }
2610                 } else {
2611                         if (aniState->firstepLevel > 0) {
2612                                 if (ath9k_hw_ani_control
2613                                     (ah, ATH9K_ANI_FIRSTEP_LEVEL,
2614                                      aniState->firstepLevel - 1) ==
2615                                     true) {
2616                                         return;
2617                                 }
2618                         }
2619                 }
2620         }
2621
2622         if (aniState->spurImmunityLevel > 0) {
2623                 if (ath9k_hw_ani_control(ah, ATH9K_ANI_SPUR_IMMUNITY_LEVEL,
2624                                          aniState->spurImmunityLevel - 1)) {
2625                         return;
2626                 }
2627         }
2628
2629         if (aniState->noiseImmunityLevel > 0) {
2630                 ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL,
2631                                      aniState->noiseImmunityLevel - 1);
2632                 return;
2633         }
2634 }
2635
2636 static int32_t ath9k_hw_ani_get_listen_time(struct ath_hal *ah)
2637 {
2638         struct ath_hal_5416 *ahp = AH5416(ah);
2639         struct ar5416AniState *aniState;
2640         u32 txFrameCount, rxFrameCount, cycleCount;
2641         int32_t listenTime;
2642
2643         txFrameCount = REG_READ(ah, AR_TFCNT);
2644         rxFrameCount = REG_READ(ah, AR_RFCNT);
2645         cycleCount = REG_READ(ah, AR_CCCNT);
2646
2647         aniState = ahp->ah_curani;
2648         if (aniState->cycleCount == 0 || aniState->cycleCount > cycleCount) {
2649
2650                 listenTime = 0;
2651                 ahp->ah_stats.ast_ani_lzero++;
2652         } else {
2653                 int32_t ccdelta = cycleCount - aniState->cycleCount;
2654                 int32_t rfdelta = rxFrameCount - aniState->rxFrameCount;
2655                 int32_t tfdelta = txFrameCount - aniState->txFrameCount;
2656                 listenTime = (ccdelta - rfdelta - tfdelta) / 44000;
2657         }
2658         aniState->cycleCount = cycleCount;
2659         aniState->txFrameCount = txFrameCount;
2660         aniState->rxFrameCount = rxFrameCount;
2661
2662         return listenTime;
2663 }
2664
2665 void ath9k_hw_ani_monitor(struct ath_hal *ah,
2666                           const struct ath9k_node_stats *stats,
2667                           struct ath9k_channel *chan)
2668 {
2669         struct ath_hal_5416 *ahp = AH5416(ah);
2670         struct ar5416AniState *aniState;
2671         int32_t listenTime;
2672
2673         aniState = ahp->ah_curani;
2674         ahp->ah_stats.ast_nodestats = *stats;
2675
2676         listenTime = ath9k_hw_ani_get_listen_time(ah);
2677         if (listenTime < 0) {
2678                 ahp->ah_stats.ast_ani_lneg++;
2679                 ath9k_ani_restart(ah);
2680                 return;
2681         }
2682
2683         aniState->listenTime += listenTime;
2684
2685         if (ahp->ah_hasHwPhyCounters) {
2686                 u32 phyCnt1, phyCnt2;
2687                 u32 ofdmPhyErrCnt, cckPhyErrCnt;
2688
2689                 ath9k_hw_update_mibstats(ah, &ahp->ah_mibStats);
2690
2691                 phyCnt1 = REG_READ(ah, AR_PHY_ERR_1);
2692                 phyCnt2 = REG_READ(ah, AR_PHY_ERR_2);
2693
2694                 if (phyCnt1 < aniState->ofdmPhyErrBase ||
2695                     phyCnt2 < aniState->cckPhyErrBase) {
2696                         if (phyCnt1 < aniState->ofdmPhyErrBase) {
2697                                 DPRINTF(ah->ah_sc, ATH_DBG_ANI,
2698                                          "%s: phyCnt1 0x%x, resetting "
2699                                          "counter value to 0x%x\n",
2700                                          __func__, phyCnt1,
2701                                          aniState->ofdmPhyErrBase);
2702                                 REG_WRITE(ah, AR_PHY_ERR_1,
2703                                           aniState->ofdmPhyErrBase);
2704                                 REG_WRITE(ah, AR_PHY_ERR_MASK_1,
2705                                           AR_PHY_ERR_OFDM_TIMING);
2706                         }
2707                         if (phyCnt2 < aniState->cckPhyErrBase) {
2708                                 DPRINTF(ah->ah_sc, ATH_DBG_ANI,
2709                                          "%s: phyCnt2 0x%x, resetting "
2710                                          "counter value to 0x%x\n",
2711                                          __func__, phyCnt2,
2712                                          aniState->cckPhyErrBase);
2713                                 REG_WRITE(ah, AR_PHY_ERR_2,
2714                                           aniState->cckPhyErrBase);
2715                                 REG_WRITE(ah, AR_PHY_ERR_MASK_2,
2716                                           AR_PHY_ERR_CCK_TIMING);
2717                         }
2718                         return;
2719                 }
2720
2721                 ofdmPhyErrCnt = phyCnt1 - aniState->ofdmPhyErrBase;
2722                 ahp->ah_stats.ast_ani_ofdmerrs +=
2723                         ofdmPhyErrCnt - aniState->ofdmPhyErrCount;
2724                 aniState->ofdmPhyErrCount = ofdmPhyErrCnt;
2725
2726                 cckPhyErrCnt = phyCnt2 - aniState->cckPhyErrBase;
2727                 ahp->ah_stats.ast_ani_cckerrs +=
2728                         cckPhyErrCnt - aniState->cckPhyErrCount;
2729                 aniState->cckPhyErrCount = cckPhyErrCnt;
2730         }
2731
2732         if (!DO_ANI(ah))
2733                 return;
2734
2735         if (aniState->listenTime > 5 * ahp->ah_aniPeriod) {
2736                 if (aniState->ofdmPhyErrCount <= aniState->listenTime *
2737                     aniState->ofdmTrigLow / 1000 &&
2738                     aniState->cckPhyErrCount <= aniState->listenTime *
2739                     aniState->cckTrigLow / 1000)
2740                         ath9k_hw_ani_lower_immunity(ah);
2741                 ath9k_ani_restart(ah);
2742         } else if (aniState->listenTime > ahp->ah_aniPeriod) {
2743                 if (aniState->ofdmPhyErrCount > aniState->listenTime *
2744                     aniState->ofdmTrigHigh / 1000) {
2745                         ath9k_hw_ani_ofdm_err_trigger(ah);
2746                         ath9k_ani_restart(ah);
2747                 } else if (aniState->cckPhyErrCount >
2748                            aniState->listenTime * aniState->cckTrigHigh /
2749                            1000) {
2750                         ath9k_hw_ani_cck_err_trigger(ah);
2751                         ath9k_ani_restart(ah);
2752                 }
2753         }
2754 }
2755
2756 #ifndef ATH_NF_PER_CHAN
2757 static void ath9k_init_nfcal_hist_buffer(struct ath_hal *ah)
2758 {
2759         int i, j;
2760
2761         for (i = 0; i < NUM_NF_READINGS; i++) {
2762                 ah->nfCalHist[i].currIndex = 0;
2763                 ah->nfCalHist[i].privNF = AR_PHY_CCA_MAX_GOOD_VALUE;
2764                 ah->nfCalHist[i].invalidNFcount =
2765                         AR_PHY_CCA_FILTERWINDOW_LENGTH;
2766                 for (j = 0; j < ATH9K_NF_CAL_HIST_MAX; j++) {
2767                         ah->nfCalHist[i].nfCalBuffer[j] =
2768                                 AR_PHY_CCA_MAX_GOOD_VALUE;
2769                 }
2770         }
2771         return;
2772 }
2773 #endif
2774
2775 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hal *ah,
2776                                          u32 gpio, u32 type)
2777 {
2778         int addr;
2779         u32 gpio_shift, tmp;
2780
2781         if (gpio > 11)
2782                 addr = AR_GPIO_OUTPUT_MUX3;
2783         else if (gpio > 5)
2784                 addr = AR_GPIO_OUTPUT_MUX2;
2785         else
2786                 addr = AR_GPIO_OUTPUT_MUX1;
2787
2788         gpio_shift = (gpio % 6) * 5;
2789
2790         if (AR_SREV_9280_20_OR_LATER(ah)
2791             || (addr != AR_GPIO_OUTPUT_MUX1)) {
2792                 REG_RMW(ah, addr, (type << gpio_shift),
2793                         (0x1f << gpio_shift));
2794         } else {
2795                 tmp = REG_READ(ah, addr);
2796                 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
2797                 tmp &= ~(0x1f << gpio_shift);
2798                 tmp |= (type << gpio_shift);
2799                 REG_WRITE(ah, addr, tmp);
2800         }
2801 }
2802
2803 void ath9k_hw_cfg_output(struct ath_hal *ah, u32 gpio,
2804                          u32 ah_signal_type)
2805 {
2806         u32 gpio_shift;
2807
2808         ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
2809
2810         gpio_shift = 2 * gpio;
2811
2812         REG_RMW(ah,
2813                 AR_GPIO_OE_OUT,
2814                 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
2815                 (AR_GPIO_OE_OUT_DRV << gpio_shift));
2816 }
2817
2818 void ath9k_hw_set_gpio(struct ath_hal *ah, u32 gpio, u32 val)
2819 {
2820         REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
2821                 AR_GPIO_BIT(gpio));
2822 }
2823
2824 /*
2825  * Configure GPIO Input lines
2826  */
2827 void ath9k_hw_cfg_gpio_input(struct ath_hal *ah, u32 gpio)
2828 {
2829         u32 gpio_shift;
2830
2831         ASSERT(gpio < ah->ah_caps.num_gpio_pins);
2832
2833         gpio_shift = gpio << 1;
2834
2835         REG_RMW(ah,
2836                 AR_GPIO_OE_OUT,
2837                 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
2838                 (AR_GPIO_OE_OUT_DRV << gpio_shift));
2839 }
2840
2841 #ifdef CONFIG_RFKILL
2842 static void ath9k_enable_rfkill(struct ath_hal *ah)
2843 {
2844         REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
2845                     AR_GPIO_INPUT_EN_VAL_RFSILENT_BB);
2846
2847         REG_CLR_BIT(ah, AR_GPIO_INPUT_MUX2,
2848                     AR_GPIO_INPUT_MUX2_RFSILENT);
2849
2850         ath9k_hw_cfg_gpio_input(ah, ah->ah_rfkill_gpio);
2851         REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB);
2852 }
2853 #endif
2854
2855 u32 ath9k_hw_gpio_get(struct ath_hal *ah, u32 gpio)
2856 {
2857         if (gpio >= ah->ah_caps.num_gpio_pins)
2858                 return 0xffffffff;
2859
2860         if (AR_SREV_9280_10_OR_LATER(ah)) {
2861                 return (MS
2862                         (REG_READ(ah, AR_GPIO_IN_OUT),
2863                          AR928X_GPIO_IN_VAL) & AR_GPIO_BIT(gpio)) != 0;
2864         } else {
2865                 return (MS(REG_READ(ah, AR_GPIO_IN_OUT), AR_GPIO_IN_VAL) &
2866                         AR_GPIO_BIT(gpio)) != 0;
2867         }
2868 }
2869
2870 static int ath9k_hw_post_attach(struct ath_hal *ah)
2871 {
2872         int ecode;
2873
2874         if (!ath9k_hw_chip_test(ah)) {
2875                 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
2876                          "%s: hardware self-test failed\n", __func__);
2877                 return -ENODEV;
2878         }
2879
2880         ecode = ath9k_hw_rf_claim(ah);
2881         if (ecode != 0)
2882                 return ecode;
2883
2884         ecode = ath9k_hw_eeprom_attach(ah);
2885         if (ecode != 0)
2886                 return ecode;
2887         ecode = ath9k_hw_rfattach(ah);
2888         if (ecode != 0)
2889                 return ecode;
2890
2891         if (!AR_SREV_9100(ah)) {
2892                 ath9k_hw_ani_setup(ah);
2893                 ath9k_hw_ani_attach(ah);
2894         }
2895         return 0;
2896 }
2897
2898 static u32 ath9k_hw_ini_fixup(struct ath_hal *ah,
2899                                     struct ar5416_eeprom *pEepData,
2900                                     u32 reg, u32 value)
2901 {
2902         struct base_eep_header *pBase = &(pEepData->baseEepHeader);
2903
2904         switch (ah->ah_devid) {
2905         case AR9280_DEVID_PCI:
2906                 if (reg == 0x7894) {
2907                         DPRINTF(ah->ah_sc, ATH_DBG_ANY,
2908                                  "ini VAL: %x  EEPROM: %x\n", value,
2909                                  (pBase->version & 0xff));
2910
2911                         if ((pBase->version & 0xff) > 0x0a) {
2912                                 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
2913                                          "PWDCLKIND: %d\n",
2914                                          pBase->pwdclkind);
2915                                 value &= ~AR_AN_TOP2_PWDCLKIND;
2916                                 value |= AR_AN_TOP2_PWDCLKIND & (pBase->
2917                                          pwdclkind << AR_AN_TOP2_PWDCLKIND_S);
2918                         } else {
2919                                 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
2920                                          "PWDCLKIND Earlier Rev\n");
2921                         }
2922
2923                         DPRINTF(ah->ah_sc, ATH_DBG_ANY,
2924                                  "final ini VAL: %x\n", value);
2925                 }
2926                 break;
2927         }
2928         return value;
2929 }
2930
2931 static bool ath9k_hw_fill_cap_info(struct ath_hal *ah)
2932 {
2933         struct ath_hal_5416 *ahp = AH5416(ah);
2934         struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
2935         u16 capField = 0, eeval;
2936
2937         eeval = ath9k_hw_get_eeprom(ahp, EEP_REG_0);
2938
2939         ah->ah_currentRD = eeval;
2940
2941         eeval = ath9k_hw_get_eeprom(ahp, EEP_REG_1);
2942         ah->ah_currentRDExt = eeval;
2943
2944         capField = ath9k_hw_get_eeprom(ahp, EEP_OP_CAP);
2945
2946         if (ah->ah_opmode != ATH9K_M_HOSTAP &&
2947             ah->ah_subvendorid == AR_SUBVENDOR_ID_NEW_A) {
2948                 if (ah->ah_currentRD == 0x64 || ah->ah_currentRD == 0x65)
2949                         ah->ah_currentRD += 5;
2950                 else if (ah->ah_currentRD == 0x41)
2951                         ah->ah_currentRD = 0x43;
2952                 DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
2953                          "%s: regdomain mapped to 0x%x\n", __func__,
2954                          ah->ah_currentRD);
2955         }
2956
2957         eeval = ath9k_hw_get_eeprom(ahp, EEP_OP_MODE);
2958         bitmap_zero(pCap->wireless_modes, ATH9K_MODE_MAX);
2959
2960         if (eeval & AR5416_OPFLAGS_11A) {
2961                 set_bit(ATH9K_MODE_11A, pCap->wireless_modes);
2962                 if (ah->ah_config.ht_enable) {
2963                         if (!(eeval & AR5416_OPFLAGS_N_5G_HT20))
2964                                 set_bit(ATH9K_MODE_11NA_HT20,
2965                                         pCap->wireless_modes);
2966                         if (!(eeval & AR5416_OPFLAGS_N_5G_HT40)) {
2967                                 set_bit(ATH9K_MODE_11NA_HT40PLUS,
2968                                         pCap->wireless_modes);
2969                                 set_bit(ATH9K_MODE_11NA_HT40MINUS,
2970                                         pCap->wireless_modes);
2971                         }
2972                 }
2973         }
2974
2975         if (eeval & AR5416_OPFLAGS_11G) {
2976                 set_bit(ATH9K_MODE_11B, pCap->wireless_modes);
2977                 set_bit(ATH9K_MODE_11G, pCap->wireless_modes);
2978                 if (ah->ah_config.ht_enable) {
2979                         if (!(eeval & AR5416_OPFLAGS_N_2G_HT20))
2980                                 set_bit(ATH9K_MODE_11NG_HT20,
2981                                         pCap->wireless_modes);
2982                         if (!(eeval & AR5416_OPFLAGS_N_2G_HT40)) {
2983                                 set_bit(ATH9K_MODE_11NG_HT40PLUS,
2984                                         pCap->wireless_modes);
2985                                 set_bit(ATH9K_MODE_11NG_HT40MINUS,
2986                                         pCap->wireless_modes);
2987                         }
2988                 }
2989         }
2990
2991         pCap->tx_chainmask = ath9k_hw_get_eeprom(ahp, EEP_TX_MASK);
2992         if ((ah->ah_isPciExpress)
2993             || (eeval & AR5416_OPFLAGS_11A)) {
2994                 pCap->rx_chainmask =
2995                         ath9k_hw_get_eeprom(ahp, EEP_RX_MASK);
2996         } else {
2997                 pCap->rx_chainmask =
2998                         (ath9k_hw_gpio_get(ah, 0)) ? 0x5 : 0x7;
2999         }
3000
3001         if (!(AR_SREV_9280(ah) && (ah->ah_macRev == 0)))
3002                 ahp->ah_miscMode |= AR_PCU_MIC_NEW_LOC_ENA;
3003
3004         pCap->low_2ghz_chan = 2312;
3005         pCap->high_2ghz_chan = 2732;
3006
3007         pCap->low_5ghz_chan = 4920;
3008         pCap->high_5ghz_chan = 6100;
3009
3010         pCap->hw_caps &= ~ATH9K_HW_CAP_CIPHER_CKIP;
3011         pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_TKIP;
3012         pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_AESCCM;
3013
3014         pCap->hw_caps &= ~ATH9K_HW_CAP_MIC_CKIP;
3015         pCap->hw_caps |= ATH9K_HW_CAP_MIC_TKIP;
3016         pCap->hw_caps |= ATH9K_HW_CAP_MIC_AESCCM;
3017
3018         pCap->hw_caps |= ATH9K_HW_CAP_CHAN_SPREAD;
3019
3020         if (ah->ah_config.ht_enable)
3021                 pCap->hw_caps |= ATH9K_HW_CAP_HT;
3022         else
3023                 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
3024
3025         pCap->hw_caps |= ATH9K_HW_CAP_GTT;
3026         pCap->hw_caps |= ATH9K_HW_CAP_VEOL;
3027         pCap->hw_caps |= ATH9K_HW_CAP_BSSIDMASK;
3028         pCap->hw_caps &= ~ATH9K_HW_CAP_MCAST_KEYSEARCH;
3029
3030         if (capField & AR_EEPROM_EEPCAP_MAXQCU)
3031                 pCap->total_queues =
3032                         MS(capField, AR_EEPROM_EEPCAP_MAXQCU);
3033         else
3034                 pCap->total_queues = ATH9K_NUM_TX_QUEUES;
3035
3036         if (capField & AR_EEPROM_EEPCAP_KC_ENTRIES)
3037                 pCap->keycache_size =
3038                         1 << MS(capField, AR_EEPROM_EEPCAP_KC_ENTRIES);
3039         else
3040                 pCap->keycache_size = AR_KEYTABLE_SIZE;
3041
3042         pCap->hw_caps |= ATH9K_HW_CAP_FASTCC;
3043         pCap->num_mr_retries = 4;
3044         pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD;
3045
3046         if (AR_SREV_9280_10_OR_LATER(ah))
3047                 pCap->num_gpio_pins = AR928X_NUM_GPIO;
3048         else
3049                 pCap->num_gpio_pins = AR_NUM_GPIO;
3050
3051         if (AR_SREV_9280_10_OR_LATER(ah)) {
3052                 pCap->hw_caps |= ATH9K_HW_CAP_WOW;
3053                 pCap->hw_caps |= ATH9K_HW_CAP_WOW_MATCHPATTERN_EXACT;
3054         } else {
3055                 pCap->hw_caps &= ~ATH9K_HW_CAP_WOW;
3056                 pCap->hw_caps &= ~ATH9K_HW_CAP_WOW_MATCHPATTERN_EXACT;
3057         }
3058
3059         if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) {
3060                 pCap->hw_caps |= ATH9K_HW_CAP_CST;
3061                 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
3062         } else {
3063                 pCap->rts_aggr_limit = (8 * 1024);
3064         }
3065
3066         pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM;
3067
3068 #ifdef CONFIG_RFKILL
3069         ah->ah_rfsilent = ath9k_hw_get_eeprom(ahp, EEP_RF_SILENT);
3070         if (ah->ah_rfsilent & EEP_RFSILENT_ENABLED) {
3071                 ah->ah_rfkill_gpio =
3072                         MS(ah->ah_rfsilent, EEP_RFSILENT_GPIO_SEL);
3073                 ah->ah_rfkill_polarity =
3074                         MS(ah->ah_rfsilent, EEP_RFSILENT_POLARITY);
3075
3076                 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
3077         }
3078 #endif
3079
3080         if ((ah->ah_macVersion == AR_SREV_VERSION_5416_PCI) ||
3081             (ah->ah_macVersion == AR_SREV_VERSION_5416_PCIE) ||
3082             (ah->ah_macVersion == AR_SREV_VERSION_9160) ||
3083             (ah->ah_macVersion == AR_SREV_VERSION_9100) ||
3084             (ah->ah_macVersion == AR_SREV_VERSION_9280))
3085                 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
3086         else
3087                 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
3088
3089         if (AR_SREV_9280(ah))
3090                 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
3091         else
3092                 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
3093
3094         if (ah->ah_currentRDExt & (1 << REG_EXT_JAPAN_MIDBAND)) {
3095                 pCap->reg_cap =
3096                         AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3097                         AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN |
3098                         AR_EEPROM_EEREGCAP_EN_KK_U2 |
3099                         AR_EEPROM_EEREGCAP_EN_KK_MIDBAND;
3100         } else {
3101                 pCap->reg_cap =
3102                         AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3103                         AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN;
3104         }
3105
3106         pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND;
3107
3108         pCap->num_antcfg_5ghz =
3109                 ath9k_hw_get_num_ant_config(ahp, IEEE80211_BAND_5GHZ);
3110         pCap->num_antcfg_2ghz =
3111                 ath9k_hw_get_num_ant_config(ahp, IEEE80211_BAND_2GHZ);
3112
3113         return true;
3114 }
3115
3116 static void ar5416DisablePciePhy(struct ath_hal *ah)
3117 {
3118         if (!AR_SREV_9100(ah))
3119                 return;
3120
3121         REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
3122         REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
3123         REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
3124         REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
3125         REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
3126         REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
3127         REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
3128         REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
3129         REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
3130
3131         REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
3132 }
3133
3134 static void ath9k_set_power_sleep(struct ath_hal *ah, int setChip)
3135 {
3136         REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
3137         if (setChip) {
3138                 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
3139                             AR_RTC_FORCE_WAKE_EN);
3140                 if (!AR_SREV_9100(ah))
3141                         REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
3142
3143                 REG_CLR_BIT(ah, (u16) (AR_RTC_RESET),
3144                             AR_RTC_RESET_EN);
3145         }
3146 }
3147
3148 static void ath9k_set_power_network_sleep(struct ath_hal *ah, int setChip)
3149 {
3150         REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
3151         if (setChip) {
3152                 struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
3153
3154                 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
3155                         REG_WRITE(ah, AR_RTC_FORCE_WAKE,
3156                                   AR_RTC_FORCE_WAKE_ON_INT);
3157                 } else {
3158                         REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
3159                                     AR_RTC_FORCE_WAKE_EN);
3160                 }
3161         }
3162 }
3163
3164 static bool ath9k_hw_set_power_awake(struct ath_hal *ah,
3165                                      int setChip)
3166 {
3167         u32 val;
3168         int i;
3169
3170         if (setChip) {
3171                 if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M) ==
3172                     AR_RTC_STATUS_SHUTDOWN) {
3173                         if (ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)
3174                             != true) {
3175                                 return false;
3176                         }
3177                 }
3178                 if (AR_SREV_9100(ah))
3179                         REG_SET_BIT(ah, AR_RTC_RESET,
3180                                        AR_RTC_RESET_EN);
3181
3182                 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
3183                             AR_RTC_FORCE_WAKE_EN);
3184                 udelay(50);
3185
3186                 for (i = POWER_UP_TIME / 50; i > 0; i--) {
3187                         val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
3188                         if (val == AR_RTC_STATUS_ON)
3189                                 break;
3190                         udelay(50);
3191                         REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
3192                                        AR_RTC_FORCE_WAKE_EN);
3193                 }
3194                 if (i == 0) {
3195                         DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
3196                                  "%s: Failed to wakeup in %uus\n",
3197                                  __func__, POWER_UP_TIME / 20);
3198                         return false;
3199                 }
3200         }
3201
3202         REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
3203         return true;
3204 }
3205
3206 bool ath9k_hw_setpower(struct ath_hal *ah,
3207                        enum ath9k_power_mode mode)
3208 {
3209         struct ath_hal_5416 *ahp = AH5416(ah);
3210         static const char *modes[] = {
3211                 "AWAKE",
3212                 "FULL-SLEEP",
3213                 "NETWORK SLEEP",
3214                 "UNDEFINED"
3215         };
3216         int status = true, setChip = true;
3217
3218         DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT, "%s: %s -> %s (%s)\n", __func__,
3219                  modes[ahp->ah_powerMode], modes[mode],
3220                  setChip ? "set chip " : "");
3221
3222         switch (mode) {
3223         case ATH9K_PM_AWAKE:
3224                 status = ath9k_hw_set_power_awake(ah, setChip);
3225                 break;
3226         case ATH9K_PM_FULL_SLEEP:
3227                 ath9k_set_power_sleep(ah, setChip);
3228                 ahp->ah_chipFullSleep = true;
3229                 break;
3230         case ATH9K_PM_NETWORK_SLEEP:
3231                 ath9k_set_power_network_sleep(ah, setChip);
3232                 break;
3233         default:
3234                 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
3235                          "%s: unknown power mode %u\n", __func__, mode);
3236                 return false;
3237         }
3238         ahp->ah_powerMode = mode;
3239         return status;
3240 }
3241
3242 static struct ath_hal *ath9k_hw_do_attach(u16 devid,
3243                                           struct ath_softc *sc,
3244                                           void __iomem *mem,
3245                                           int *status)
3246 {
3247         struct ath_hal_5416 *ahp;
3248         struct ath_hal *ah;
3249         int ecode;
3250 #ifndef CONFIG_SLOW_ANT_DIV
3251         u32 i;
3252         u32 j;
3253 #endif
3254
3255         ahp = ath9k_hw_newstate(devid, sc, mem, status);
3256         if (ahp == NULL)
3257                 return NULL;
3258
3259         ah = &ahp->ah;
3260
3261         ath9k_hw_set_defaults(ah);
3262
3263         if (ah->ah_config.intr_mitigation != 0)
3264                 ahp->ah_intrMitigation = true;
3265
3266         if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
3267                 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "%s: couldn't reset chip\n",
3268                          __func__);
3269                 ecode = -EIO;
3270                 goto bad;
3271         }
3272
3273         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
3274                 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "%s: couldn't wakeup chip\n",
3275                          __func__);
3276                 ecode = -EIO;
3277                 goto bad;
3278         }
3279
3280         if (ah->ah_config.serialize_regmode == SER_REG_MODE_AUTO) {
3281                 if (ah->ah_macVersion == AR_SREV_VERSION_5416_PCI) {
3282                         ah->ah_config.serialize_regmode =
3283                                 SER_REG_MODE_ON;
3284                 } else {
3285                         ah->ah_config.serialize_regmode =
3286                                 SER_REG_MODE_OFF;
3287                 }
3288         }
3289         DPRINTF(ah->ah_sc, ATH_DBG_RESET,
3290                 "%s: serialize_regmode is %d\n",
3291                 __func__, ah->ah_config.serialize_regmode);
3292
3293         if ((ah->ah_macVersion != AR_SREV_VERSION_5416_PCI) &&
3294             (ah->ah_macVersion != AR_SREV_VERSION_5416_PCIE) &&
3295             (ah->ah_macVersion != AR_SREV_VERSION_9160) &&
3296             (!AR_SREV_9100(ah)) && (!AR_SREV_9280(ah))) {
3297                 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
3298                          "%s: Mac Chip Rev 0x%02x.%x is not supported by "
3299                          "this driver\n", __func__,
3300                          ah->ah_macVersion, ah->ah_macRev);
3301                 ecode = -EOPNOTSUPP;
3302                 goto bad;
3303         }
3304
3305         if (AR_SREV_9100(ah)) {
3306                 ahp->ah_iqCalData.calData = &iq_cal_multi_sample;
3307                 ahp->ah_suppCals = IQ_MISMATCH_CAL;
3308                 ah->ah_isPciExpress = false;
3309         }
3310         ah->ah_phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
3311
3312         if (AR_SREV_9160_10_OR_LATER(ah)) {
3313                 if (AR_SREV_9280_10_OR_LATER(ah)) {
3314                         ahp->ah_iqCalData.calData = &iq_cal_single_sample;
3315                         ahp->ah_adcGainCalData.calData =
3316                                 &adc_gain_cal_single_sample;
3317                         ahp->ah_adcDcCalData.calData =
3318                                 &adc_dc_cal_single_sample;
3319                         ahp->ah_adcDcCalInitData.calData =
3320                                 &adc_init_dc_cal;
3321                 } else {
3322                         ahp->ah_iqCalData.calData = &iq_cal_multi_sample;
3323                         ahp->ah_adcGainCalData.calData =
3324                                 &adc_gain_cal_multi_sample;
3325                         ahp->ah_adcDcCalData.calData =
3326                                 &adc_dc_cal_multi_sample;
3327                         ahp->ah_adcDcCalInitData.calData =
3328                                 &adc_init_dc_cal;
3329                 }
3330                 ahp->ah_suppCals =
3331                         ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL;
3332         }
3333
3334         if (AR_SREV_9160(ah)) {
3335                 ah->ah_config.enable_ani = 1;
3336                 ahp->ah_ani_function = (ATH9K_ANI_SPUR_IMMUNITY_LEVEL |
3337                                         ATH9K_ANI_FIRSTEP_LEVEL);
3338         } else {
3339                 ahp->ah_ani_function = ATH9K_ANI_ALL;
3340                 if (AR_SREV_9280_10_OR_LATER(ah)) {
3341                         ahp->ah_ani_function &=
3342                                 ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
3343                 }
3344         }
3345
3346         DPRINTF(ah->ah_sc, ATH_DBG_RESET,
3347                  "%s: This Mac Chip Rev 0x%02x.%x is \n", __func__,
3348                  ah->ah_macVersion, ah->ah_macRev);
3349
3350         if (AR_SREV_9280_20_OR_LATER(ah)) {
3351                 INIT_INI_ARRAY(&ahp->ah_iniModes, ar9280Modes_9280_2,
3352                                ARRAY_SIZE(ar9280Modes_9280_2), 6);
3353                 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar9280Common_9280_2,
3354                                ARRAY_SIZE(ar9280Common_9280_2), 2);
3355
3356                 if (ah->ah_config.pcie_clock_req) {
3357                         INIT_INI_ARRAY(&ahp->ah_iniPcieSerdes,
3358                                        ar9280PciePhy_clkreq_off_L1_9280,
3359                                        ARRAY_SIZE
3360                                        (ar9280PciePhy_clkreq_off_L1_9280),
3361                                        2);
3362                 } else {
3363                         INIT_INI_ARRAY(&ahp->ah_iniPcieSerdes,
3364                                        ar9280PciePhy_clkreq_always_on_L1_9280,
3365                                        ARRAY_SIZE
3366                                        (ar9280PciePhy_clkreq_always_on_L1_9280),
3367                                        2);
3368                 }
3369                 INIT_INI_ARRAY(&ahp->ah_iniModesAdditional,
3370                                ar9280Modes_fast_clock_9280_2,
3371                                ARRAY_SIZE(ar9280Modes_fast_clock_9280_2),
3372                                3);
3373         } else if (AR_SREV_9280_10_OR_LATER(ah)) {
3374                 INIT_INI_ARRAY(&ahp->ah_iniModes, ar9280Modes_9280,
3375                                ARRAY_SIZE(ar9280Modes_9280), 6);
3376                 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar9280Common_9280,
3377                                ARRAY_SIZE(ar9280Common_9280), 2);
3378         } else if (AR_SREV_9160_10_OR_LATER(ah)) {
3379                 INIT_INI_ARRAY(&ahp->ah_iniModes, ar5416Modes_9160,
3380                                ARRAY_SIZE(ar5416Modes_9160), 6);
3381                 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar5416Common_9160,
3382                                ARRAY_SIZE(ar5416Common_9160), 2);
3383                 INIT_INI_ARRAY(&ahp->ah_iniBank0, ar5416Bank0_9160,
3384                                ARRAY_SIZE(ar5416Bank0_9160), 2);
3385                 INIT_INI_ARRAY(&ahp->ah_iniBB_RfGain, ar5416BB_RfGain_9160,
3386                                ARRAY_SIZE(ar5416BB_RfGain_9160), 3);
3387                 INIT_INI_ARRAY(&ahp->ah_iniBank1, ar5416Bank1_9160,
3388                                ARRAY_SIZE(ar5416Bank1_9160), 2);
3389                 INIT_INI_ARRAY(&ahp->ah_iniBank2, ar5416Bank2_9160,
3390                                ARRAY_SIZE(ar5416Bank2_9160), 2);
3391                 INIT_INI_ARRAY(&ahp->ah_iniBank3, ar5416Bank3_9160,
3392                                ARRAY_SIZE(ar5416Bank3_9160), 3);
3393                 INIT_INI_ARRAY(&ahp->ah_iniBank6, ar5416Bank6_9160,
3394                                ARRAY_SIZE(ar5416Bank6_9160), 3);
3395                 INIT_INI_ARRAY(&ahp->ah_iniBank6TPC, ar5416Bank6TPC_9160,
3396                                ARRAY_SIZE(ar5416Bank6TPC_9160), 3);
3397                 INIT_INI_ARRAY(&ahp->ah_iniBank7, ar5416Bank7_9160,
3398                                ARRAY_SIZE(ar5416Bank7_9160), 2);
3399                 if (AR_SREV_9160_11(ah)) {
3400                         INIT_INI_ARRAY(&ahp->ah_iniAddac,
3401                                        ar5416Addac_91601_1,
3402                                        ARRAY_SIZE(ar5416Addac_91601_1), 2);
3403                 } else {
3404                         INIT_INI_ARRAY(&ahp->ah_iniAddac, ar5416Addac_9160,
3405                                        ARRAY_SIZE(ar5416Addac_9160), 2);
3406                 }
3407         } else if (AR_SREV_9100_OR_LATER(ah)) {
3408                 INIT_INI_ARRAY(&ahp->ah_iniModes, ar5416Modes_9100,
3409                                ARRAY_SIZE(ar5416Modes_9100), 6);
3410                 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar5416Common_9100,
3411                                ARRAY_SIZE(ar5416Common_9100), 2);
3412                 INIT_INI_ARRAY(&ahp->ah_iniBank0, ar5416Bank0_9100,
3413                                ARRAY_SIZE(ar5416Bank0_9100), 2);
3414                 INIT_INI_ARRAY(&ahp->ah_iniBB_RfGain, ar5416BB_RfGain_9100,
3415                                ARRAY_SIZE(ar5416BB_RfGain_9100), 3);
3416                 INIT_INI_ARRAY(&ahp->ah_iniBank1, ar5416Bank1_9100,
3417                                ARRAY_SIZE(ar5416Bank1_9100), 2);
3418                 INIT_INI_ARRAY(&ahp->ah_iniBank2, ar5416Bank2_9100,
3419                                ARRAY_SIZE(ar5416Bank2_9100), 2);
3420                 INIT_INI_ARRAY(&ahp->ah_iniBank3, ar5416Bank3_9100,
3421                                ARRAY_SIZE(ar5416Bank3_9100), 3);
3422                 INIT_INI_ARRAY(&ahp->ah_iniBank6, ar5416Bank6_9100,
3423                                ARRAY_SIZE(ar5416Bank6_9100), 3);
3424                 INIT_INI_ARRAY(&ahp->ah_iniBank6TPC, ar5416Bank6TPC_9100,
3425                                ARRAY_SIZE(ar5416Bank6TPC_9100), 3);
3426                 INIT_INI_ARRAY(&ahp->ah_iniBank7, ar5416Bank7_9100,
3427                                ARRAY_SIZE(ar5416Bank7_9100), 2);
3428                 INIT_INI_ARRAY(&ahp->ah_iniAddac, ar5416Addac_9100,
3429                                ARRAY_SIZE(ar5416Addac_9100), 2);
3430         } else {
3431                 INIT_INI_ARRAY(&ahp->ah_iniModes, ar5416Modes,
3432                                ARRAY_SIZE(ar5416Modes), 6);
3433                 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar5416Common,
3434                                ARRAY_SIZE(ar5416Common), 2);
3435                 INIT_INI_ARRAY(&ahp->ah_iniBank0, ar5416Bank0,
3436                                ARRAY_SIZE(ar5416Bank0), 2);
3437                 INIT_INI_ARRAY(&ahp->ah_iniBB_RfGain, ar5416BB_RfGain,
3438                                ARRAY_SIZE(ar5416BB_RfGain), 3);
3439                 INIT_INI_ARRAY(&ahp->ah_iniBank1, ar5416Bank1,
3440                                ARRAY_SIZE(ar5416Bank1), 2);
3441                 INIT_INI_ARRAY(&ahp->ah_iniBank2, ar5416Bank2,
3442                                ARRAY_SIZE(ar5416Bank2), 2);
3443                 INIT_INI_ARRAY(&ahp->ah_iniBank3, ar5416Bank3,
3444                                ARRAY_SIZE(ar5416Bank3), 3);
3445                 INIT_INI_ARRAY(&ahp->ah_iniBank6, ar5416Bank6,
3446                                ARRAY_SIZE(ar5416Bank6), 3);
3447                 INIT_INI_ARRAY(&ahp->ah_iniBank6TPC, ar5416Bank6TPC,
3448                                ARRAY_SIZE(ar5416Bank6TPC), 3);
3449                 INIT_INI_ARRAY(&ahp->ah_iniBank7, ar5416Bank7,
3450                                ARRAY_SIZE(ar5416Bank7), 2);
3451                 INIT_INI_ARRAY(&ahp->ah_iniAddac, ar5416Addac,
3452                                ARRAY_SIZE(ar5416Addac), 2);
3453         }
3454
3455         if (ah->ah_isPciExpress)
3456                 ath9k_hw_configpcipowersave(ah, 0);
3457         else
3458                 ar5416DisablePciePhy(ah);
3459
3460         ecode = ath9k_hw_post_attach(ah);
3461         if (ecode != 0)
3462                 goto bad;
3463
3464 #ifndef CONFIG_SLOW_ANT_DIV
3465         if (ah->ah_devid == AR9280_DEVID_PCI) {
3466                 for (i = 0; i < ahp->ah_iniModes.ia_rows; i++) {
3467                         u32 reg = INI_RA(&ahp->ah_iniModes, i, 0);
3468
3469                         for (j = 1; j < ahp->ah_iniModes.ia_columns; j++) {
3470                                 u32 val = INI_RA(&ahp->ah_iniModes, i, j);
3471
3472                                 INI_RA(&ahp->ah_iniModes, i, j) =
3473                                         ath9k_hw_ini_fixup(ah, &ahp->ah_eeprom,
3474                                                            reg, val);
3475                         }
3476                 }
3477         }
3478 #endif
3479
3480         if (!ath9k_hw_fill_cap_info(ah)) {
3481                 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
3482                          "%s:failed ath9k_hw_fill_cap_info\n", __func__);
3483                 ecode = -EINVAL;
3484                 goto bad;
3485         }
3486
3487         ecode = ath9k_hw_init_macaddr(ah);
3488         if (ecode != 0) {
3489                 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
3490                          "%s: failed initializing mac address\n",
3491                          __func__);
3492                 goto bad;
3493         }
3494
3495         if (AR_SREV_9285(ah))
3496                 ah->ah_txTrigLevel = (AR_FTRIG_256B >> AR_FTRIG_S);
3497         else
3498                 ah->ah_txTrigLevel = (AR_FTRIG_512B >> AR_FTRIG_S);
3499
3500 #ifndef ATH_NF_PER_CHAN
3501
3502         ath9k_init_nfcal_hist_buffer(ah);
3503 #endif
3504
3505         return ah;
3506
3507 bad:
3508         if (ahp)
3509                 ath9k_hw_detach((struct ath_hal *) ahp);
3510         if (status)
3511                 *status = ecode;
3512         return NULL;
3513 }
3514
3515 void ath9k_hw_detach(struct ath_hal *ah)
3516 {
3517         if (!AR_SREV_9100(ah))
3518                 ath9k_hw_ani_detach(ah);
3519         ath9k_hw_rfdetach(ah);
3520
3521         ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
3522         kfree(ah);
3523 }
3524
3525 bool ath9k_get_channel_edges(struct ath_hal *ah,
3526                              u16 flags, u16 *low,
3527                              u16 *high)
3528 {
3529         struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
3530
3531         if (flags & CHANNEL_5GHZ) {
3532                 *low = pCap->low_5ghz_chan;
3533                 *high = pCap->high_5ghz_chan;
3534                 return true;
3535         }
3536         if ((flags & CHANNEL_2GHZ)) {
3537                 *low = pCap->low_2ghz_chan;
3538                 *high = pCap->high_2ghz_chan;
3539
3540                 return true;
3541         }
3542         return false;
3543 }
3544
3545 static inline bool ath9k_hw_fill_vpd_table(u8 pwrMin,
3546                                            u8 pwrMax,
3547                                            u8 *pPwrList,
3548                                            u8 *pVpdList,
3549                                            u16
3550                                            numIntercepts,
3551                                            u8 *pRetVpdList)
3552 {
3553         u16 i, k;
3554         u8 currPwr = pwrMin;
3555         u16 idxL = 0, idxR = 0;
3556
3557         for (i = 0; i <= (pwrMax - pwrMin) / 2; i++) {
3558                 ath9k_hw_get_lower_upper_index(currPwr, pPwrList,
3559                                                numIntercepts, &(idxL),
3560                                                &(idxR));
3561                 if (idxR < 1)
3562                         idxR = 1;
3563                 if (idxL == numIntercepts - 1)
3564                         idxL = (u16) (numIntercepts - 2);
3565                 if (pPwrList[idxL] == pPwrList[idxR])
3566                         k = pVpdList[idxL];
3567                 else
3568                         k = (u16) (((currPwr -
3569                                            pPwrList[idxL]) *
3570                                           pVpdList[idxR] +
3571                                           (pPwrList[idxR] -
3572                                            currPwr) * pVpdList[idxL]) /
3573                                          (pPwrList[idxR] -
3574                                           pPwrList[idxL]));
3575                 pRetVpdList[i] = (u8) k;
3576                 currPwr += 2;
3577         }
3578
3579         return true;
3580 }
3581
3582 static void
3583 ath9k_hw_get_gain_boundaries_pdadcs(struct ath_hal *ah,
3584                                     struct ath9k_channel *chan,
3585                                     struct cal_data_per_freq *pRawDataSet,
3586                                     u8 *bChans,
3587                                     u16 availPiers,
3588                                     u16 tPdGainOverlap,
3589                                     int16_t *pMinCalPower,
3590                                     u16 *pPdGainBoundaries,
3591                                     u8 *pPDADCValues,
3592                                     u16 numXpdGains)
3593 {
3594         int i, j, k;
3595         int16_t ss;
3596         u16 idxL = 0, idxR = 0, numPiers;
3597         static u8 vpdTableL[AR5416_NUM_PD_GAINS]
3598                 [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
3599         static u8 vpdTableR[AR5416_NUM_PD_GAINS]
3600                 [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
3601         static u8 vpdTableI[AR5416_NUM_PD_GAINS]
3602                 [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
3603
3604         u8 *pVpdL, *pVpdR, *pPwrL, *pPwrR;
3605         u8 minPwrT4[AR5416_NUM_PD_GAINS];
3606         u8 maxPwrT4[AR5416_NUM_PD_GAINS];
3607         int16_t vpdStep;
3608         int16_t tmpVal;
3609         u16 sizeCurrVpdTable, maxIndex, tgtIndex;
3610         bool match;
3611         int16_t minDelta = 0;
3612         struct chan_centers centers;
3613
3614         ath9k_hw_get_channel_centers(ah, chan, &centers);
3615
3616         for (numPiers = 0; numPiers < availPiers; numPiers++) {
3617                 if (bChans[numPiers] == AR5416_BCHAN_UNUSED)
3618                         break;
3619         }
3620
3621         match = ath9k_hw_get_lower_upper_index((u8)
3622                                                FREQ2FBIN(centers.
3623                                                          synth_center,
3624                                                          IS_CHAN_2GHZ
3625                                                          (chan)), bChans,
3626                                                numPiers, &idxL, &idxR);
3627
3628         if (match) {
3629                 for (i = 0; i < numXpdGains; i++) {
3630                         minPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][0];
3631                         maxPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][4];
3632                         ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
3633                                                 pRawDataSet[idxL].
3634                                                 pwrPdg[i],
3635                                                 pRawDataSet[idxL].
3636                                                 vpdPdg[i],
3637                                                 AR5416_PD_GAIN_ICEPTS,
3638                                                 vpdTableI[i]);
3639                 }
3640         } else {
3641                 for (i = 0; i < numXpdGains; i++) {
3642                         pVpdL = pRawDataSet[idxL].vpdPdg[i];
3643                         pPwrL = pRawDataSet[idxL].pwrPdg[i];
3644                         pVpdR = pRawDataSet[idxR].vpdPdg[i];
3645                         pPwrR = pRawDataSet[idxR].pwrPdg[i];
3646
3647                         minPwrT4[i] = max(pPwrL[0], pPwrR[0]);
3648
3649                         maxPwrT4[i] =
3650                                 min(pPwrL[AR5416_PD_GAIN_ICEPTS - 1],
3651                                     pPwrR[AR5416_PD_GAIN_ICEPTS - 1]);
3652
3653
3654                         ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
3655                                                 pPwrL, pVpdL,
3656                                                 AR5416_PD_GAIN_ICEPTS,
3657                                                 vpdTableL[i]);
3658                         ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
3659                                                 pPwrR, pVpdR,
3660                                                 AR5416_PD_GAIN_ICEPTS,
3661                                                 vpdTableR[i]);
3662
3663                         for (j = 0; j <= (maxPwrT4[i] - minPwrT4[i]) / 2; j++) {
3664                                 vpdTableI[i][j] =
3665                                         (u8) (ath9k_hw_interpolate
3666                                                     ((u16)
3667                                                      FREQ2FBIN(centers.
3668                                                                synth_center,
3669                                                                IS_CHAN_2GHZ
3670                                                                (chan)),
3671                                                      bChans[idxL],
3672                                                      bChans[idxR], vpdTableL[i]
3673                                                      [j], vpdTableR[i]
3674                                                      [j]));
3675                         }
3676                 }
3677         }
3678
3679         *pMinCalPower = (int16_t) (minPwrT4[0] / 2);
3680
3681         k = 0;
3682         for (i = 0; i < numXpdGains; i++) {
3683                 if (i == (numXpdGains - 1))
3684                         pPdGainBoundaries[i] =
3685                                 (u16) (maxPwrT4[i] / 2);
3686                 else
3687                         pPdGainBoundaries[i] =
3688                                 (u16) ((maxPwrT4[i] +
3689                                               minPwrT4[i + 1]) / 4);
3690
3691                 pPdGainBoundaries[i] =
3692                         min((u16) AR5416_MAX_RATE_POWER,
3693                             pPdGainBoundaries[i]);
3694
3695                 if ((i == 0) && !AR_SREV_5416_V20_OR_LATER(ah)) {
3696                         minDelta = pPdGainBoundaries[0] - 23;
3697                         pPdGainBoundaries[0] = 23;
3698                 } else {
3699                         minDelta = 0;
3700                 }
3701
3702                 if (i == 0) {
3703                         if (AR_SREV_9280_10_OR_LATER(ah))
3704                                 ss = (int16_t) (0 - (minPwrT4[i] / 2));
3705                         else
3706                                 ss = 0;
3707                 } else {
3708                         ss = (int16_t) ((pPdGainBoundaries[i - 1] -
3709                                          (minPwrT4[i] / 2)) -
3710                                         tPdGainOverlap + 1 + minDelta);
3711                 }
3712                 vpdStep = (int16_t) (vpdTableI[i][1] - vpdTableI[i][0]);
3713                 vpdStep = (int16_t) ((vpdStep < 1) ? 1 : vpdStep);
3714
3715                 while ((ss < 0) && (k < (AR5416_NUM_PDADC_VALUES - 1))) {
3716                         tmpVal = (int16_t) (vpdTableI[i][0] + ss * vpdStep);
3717                         pPDADCValues[k++] =
3718                                 (u8) ((tmpVal < 0) ? 0 : tmpVal);
3719                         ss++;
3720                 }
3721
3722                 sizeCurrVpdTable =
3723                         (u8) ((maxPwrT4[i] - minPwrT4[i]) / 2 + 1);
3724                 tgtIndex = (u8) (pPdGainBoundaries[i] + tPdGainOverlap -
3725                                        (minPwrT4[i] / 2));
3726                 maxIndex = (tgtIndex <
3727                             sizeCurrVpdTable) ? tgtIndex : sizeCurrVpdTable;
3728
3729                 while ((ss < maxIndex)
3730                        && (k < (AR5416_NUM_PDADC_VALUES - 1))) {
3731                         pPDADCValues[k++] = vpdTableI[i][ss++];
3732                 }
3733
3734                 vpdStep = (int16_t) (vpdTableI[i][sizeCurrVpdTable - 1] -
3735                                      vpdTableI[i][sizeCurrVpdTable - 2]);
3736                 vpdStep = (int16_t) ((vpdStep < 1) ? 1 : vpdStep);
3737
3738                 if (tgtIndex > maxIndex) {
3739                         while ((ss <= tgtIndex)
3740                                && (k < (AR5416_NUM_PDADC_VALUES - 1))) {
3741                                 tmpVal = (int16_t) ((vpdTableI[i]
3742                                                      [sizeCurrVpdTable -
3743                                                       1] + (ss - maxIndex +
3744                                                             1) * vpdStep));
3745                                 pPDADCValues[k++] = (u8) ((tmpVal >
3746                                                  255) ? 255 : tmpVal);
3747                                 ss++;
3748                         }
3749                 }
3750         }
3751
3752         while (i < AR5416_PD_GAINS_IN_MASK) {
3753                 pPdGainBoundaries[i] = pPdGainBoundaries[i - 1];
3754                 i++;
3755         }
3756
3757         while (k < AR5416_NUM_PDADC_VALUES) {
3758                 pPDADCValues[k] = pPDADCValues[k - 1];
3759                 k++;
3760         }
3761         return;
3762 }
3763
3764 static bool
3765 ath9k_hw_set_power_cal_table(struct ath_hal *ah,
3766                              struct ar5416_eeprom *pEepData,
3767                              struct ath9k_channel *chan,
3768                              int16_t *pTxPowerIndexOffset)
3769 {
3770         struct cal_data_per_freq *pRawDataset;
3771         u8 *pCalBChans = NULL;
3772         u16 pdGainOverlap_t2;
3773         static u8 pdadcValues[AR5416_NUM_PDADC_VALUES];
3774         u16 gainBoundaries[AR5416_PD_GAINS_IN_MASK];
3775         u16 numPiers, i, j;
3776         int16_t tMinCalPower;
3777         u16 numXpdGain, xpdMask;
3778         u16 xpdGainValues[AR5416_NUM_PD_GAINS] = { 0, 0, 0, 0 };
3779         u32 reg32, regOffset, regChainOffset;
3780         int16_t modalIdx;
3781         struct ath_hal_5416 *ahp = AH5416(ah);
3782
3783         modalIdx = IS_CHAN_2GHZ(chan) ? 1 : 0;
3784         xpdMask = pEepData->modalHeader[modalIdx].xpdGain;
3785
3786         if ((pEepData->baseEepHeader.
3787              version & AR5416_EEP_VER_MINOR_MASK) >=
3788             AR5416_EEP_MINOR_VER_2) {
3789                 pdGainOverlap_t2 =
3790                         pEepData->modalHeader[modalIdx].pdGainOverlap;
3791         } else {
3792                 pdGainOverlap_t2 =
3793                         (u16) (MS
3794                                      (REG_READ(ah, AR_PHY_TPCRG5),
3795                                       AR_PHY_TPCRG5_PD_GAIN_OVERLAP));
3796         }
3797
3798         if (IS_CHAN_2GHZ(chan)) {
3799                 pCalBChans = pEepData->calFreqPier2G;
3800                 numPiers = AR5416_NUM_2G_CAL_PIERS;
3801         } else {
3802                 pCalBChans = pEepData->calFreqPier5G;
3803                 numPiers = AR5416_NUM_5G_CAL_PIERS;
3804         }
3805
3806         numXpdGain = 0;
3807
3808         for (i = 1; i <= AR5416_PD_GAINS_IN_MASK; i++) {
3809                 if ((xpdMask >> (AR5416_PD_GAINS_IN_MASK - i)) & 1) {
3810                         if (numXpdGain >= AR5416_NUM_PD_GAINS)
3811                                 break;
3812                         xpdGainValues[numXpdGain] =
3813                                 (u16) (AR5416_PD_GAINS_IN_MASK - i);
3814                         numXpdGain++;
3815                 }
3816         }
3817
3818         REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_NUM_PD_GAIN,
3819                       (numXpdGain - 1) & 0x3);
3820         REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_1,
3821                       xpdGainValues[0]);
3822         REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_2,
3823                       xpdGainValues[1]);
3824         REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_3,
3825                       xpdGainValues[2]);
3826
3827         for (i = 0; i < AR5416_MAX_CHAINS; i++) {
3828                 if (AR_SREV_5416_V20_OR_LATER(ah) &&
3829                     (ahp->ah_rxchainmask == 5 || ahp->ah_txchainmask == 5)
3830                     && (i != 0)) {
3831                         regChainOffset = (i == 1) ? 0x2000 : 0x1000;
3832                 } else
3833                         regChainOffset = i * 0x1000;
3834                 if (pEepData->baseEepHeader.txMask & (1 << i)) {
3835                         if (IS_CHAN_2GHZ(chan))
3836                                 pRawDataset = pEepData->calPierData2G[i];
3837                         else
3838                                 pRawDataset = pEepData->calPierData5G[i];
3839
3840                         ath9k_hw_get_gain_boundaries_pdadcs(ah, chan,
3841                                                             pRawDataset,
3842                                                             pCalBChans,
3843                                                             numPiers,
3844                                                             pdGainOverlap_t2,
3845                                                             &tMinCalPower,
3846                                                             gainBoundaries,
3847                                                             pdadcValues,
3848                                                             numXpdGain);
3849
3850                         if ((i == 0) || AR_SREV_5416_V20_OR_LATER(ah)) {
3851
3852                                 REG_WRITE(ah,
3853                                           AR_PHY_TPCRG5 + regChainOffset,
3854                                           SM(pdGainOverlap_t2,
3855                                              AR_PHY_TPCRG5_PD_GAIN_OVERLAP)
3856                                           | SM(gainBoundaries[0],
3857                                                AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1)
3858                                           | SM(gainBoundaries[1],
3859                                                AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2)
3860                                           | SM(gainBoundaries[2],
3861                                                AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3)
3862                                           | SM(gainBoundaries[3],
3863                                        AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4));
3864                         }
3865
3866                         regOffset =
3867                                 AR_PHY_BASE + (672 << 2) + regChainOffset;
3868                         for (j = 0; j < 32; j++) {
3869                                 reg32 =
3870                                         ((pdadcValues[4 * j + 0] & 0xFF) << 0)
3871                                         | ((pdadcValues[4 * j + 1] & 0xFF) <<
3872                                            8) | ((pdadcValues[4 * j + 2] &
3873                                                   0xFF) << 16) |
3874                                         ((pdadcValues[4 * j + 3] & 0xFF) <<
3875                                          24);
3876                                 REG_WRITE(ah, regOffset, reg32);
3877
3878                                 DPRINTF(ah->ah_sc, ATH_DBG_PHY_IO,
3879                                          "PDADC (%d,%4x): %4.4x %8.8x\n",
3880                                          i, regChainOffset, regOffset,
3881                                          reg32);
3882                                 DPRINTF(ah->ah_sc, ATH_DBG_PHY_IO,
3883                                 "PDADC: Chain %d | PDADC %3d Value %3d | "
3884                                 "PDADC %3d Value %3d | PDADC %3d Value %3d | "
3885                                 "PDADC %3d Value %3d |\n",
3886                                          i, 4 * j, pdadcValues[4 * j],
3887                                          4 * j + 1, pdadcValues[4 * j + 1],
3888                                          4 * j + 2, pdadcValues[4 * j + 2],
3889                                          4 * j + 3,
3890                                          pdadcValues[4 * j + 3]);
3891
3892                                 regOffset += 4;
3893                         }
3894                 }
3895         }
3896         *pTxPowerIndexOffset = 0;
3897
3898         return true;
3899 }
3900
3901 void ath9k_hw_configpcipowersave(struct ath_hal *ah, int restore)
3902 {
3903         struct ath_hal_5416 *ahp = AH5416(ah);
3904         u8 i;
3905
3906         if (ah->ah_isPciExpress != true)
3907                 return;
3908
3909         if (ah->ah_config.pcie_powersave_enable == 2)
3910                 return;
3911
3912         if (restore)
3913                 return;
3914
3915         if (AR_SREV_9280_20_OR_LATER(ah)) {
3916                 for (i = 0; i < ahp->ah_iniPcieSerdes.ia_rows; i++) {
3917                         REG_WRITE(ah, INI_RA(&ahp->ah_iniPcieSerdes, i, 0),
3918                                   INI_RA(&ahp->ah_iniPcieSerdes, i, 1));
3919                 }
3920                 udelay(1000);
3921         } else if (AR_SREV_9280(ah)
3922                    && (ah->ah_macRev == AR_SREV_REVISION_9280_10)) {
3923                 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fd00);
3924                 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
3925
3926                 REG_WRITE(ah, AR_PCIE_SERDES, 0xa8000019);
3927                 REG_WRITE(ah, AR_PCIE_SERDES, 0x13160820);
3928                 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980560);
3929
3930                 if (ah->ah_config.pcie_clock_req)
3931                         REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffc);
3932                 else
3933                         REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffd);
3934
3935                 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
3936                 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
3937                 REG_WRITE(ah, AR_PCIE_SERDES, 0x00043007);
3938
3939                 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
3940
3941                 udelay(1000);
3942         } else {
3943                 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
3944                 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
3945                 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039);
3946                 REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824);
3947                 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579);
3948                 REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff);
3949                 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
3950                 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
3951                 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007);
3952                 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
3953         }
3954
3955         REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
3956
3957         if (ah->ah_config.pcie_waen) {
3958                 REG_WRITE(ah, AR_WA, ah->ah_config.pcie_waen);
3959         } else {
3960                 if (AR_SREV_9280(ah))
3961                         REG_WRITE(ah, AR_WA, 0x0040073f);
3962                 else
3963                         REG_WRITE(ah, AR_WA, 0x0000073f);
3964         }
3965 }
3966
3967 static void
3968 ath9k_hw_get_legacy_target_powers(struct ath_hal *ah,
3969                                   struct ath9k_channel *chan,
3970                                   struct cal_target_power_leg *powInfo,
3971                                   u16 numChannels,
3972                                   struct cal_target_power_leg *pNewPower,
3973                                   u16 numRates,
3974                                   bool isExtTarget)
3975 {
3976         u16 clo, chi;
3977         int i;
3978         int matchIndex = -1, lowIndex = -1;
3979         u16 freq;
3980         struct chan_centers centers;
3981
3982         ath9k_hw_get_channel_centers(ah, chan, &centers);
3983         freq = (isExtTarget) ? centers.ext_center : centers.ctl_center;
3984
3985         if (freq <= ath9k_hw_fbin2freq(powInfo[0].bChannel,
3986                 IS_CHAN_2GHZ(chan))) {
3987                 matchIndex = 0;
3988         } else {
3989                 for (i = 0; (i < numChannels)
3990                      && (powInfo[i].bChannel != AR5416_BCHAN_UNUSED); i++) {
3991                         if (freq ==
3992                             ath9k_hw_fbin2freq(powInfo[i].bChannel,
3993                                                IS_CHAN_2GHZ(chan))) {
3994                                 matchIndex = i;
3995                                 break;
3996                         } else if ((freq <
3997                                     ath9k_hw_fbin2freq(powInfo[i].bChannel,
3998                                                        IS_CHAN_2GHZ(chan)))
3999                                    && (freq >
4000                                        ath9k_hw_fbin2freq(powInfo[i - 1].
4001                                                           bChannel,
4002                                                           IS_CHAN_2GHZ
4003                                                           (chan)))) {
4004                                 lowIndex = i - 1;
4005                                 break;
4006                         }
4007                 }
4008                 if ((matchIndex == -1) && (lowIndex == -1))
4009                         matchIndex = i - 1;
4010         }
4011
4012         if (matchIndex != -1) {
4013                 *pNewPower = powInfo[matchIndex];
4014         } else {
4015                 clo = ath9k_hw_fbin2freq(powInfo[lowIndex].bChannel,
4016                                          IS_CHAN_2GHZ(chan));
4017                 chi = ath9k_hw_fbin2freq(powInfo[lowIndex + 1].bChannel,
4018                                          IS_CHAN_2GHZ(chan));
4019
4020                 for (i = 0; i < numRates; i++) {
4021                         pNewPower->tPow2x[i] =
4022                                 (u8) ath9k_hw_interpolate(freq, clo, chi,
4023                                                                 powInfo
4024                                                                 [lowIndex].
4025                                                                 tPow2x[i],
4026                                                                 powInfo
4027                                                                 [lowIndex +
4028                                                                  1].tPow2x[i]);
4029                 }
4030         }
4031 }
4032
4033 static void
4034 ath9k_hw_get_target_powers(struct ath_hal *ah,
4035                            struct ath9k_channel *chan,
4036                            struct cal_target_power_ht *powInfo,
4037                            u16 numChannels,
4038                            struct cal_target_power_ht *pNewPower,
4039                            u16 numRates,
4040                            bool isHt40Target)
4041 {
4042         u16 clo, chi;
4043         int i;
4044         int matchIndex = -1, lowIndex = -1;
4045         u16 freq;
4046         struct chan_centers centers;
4047
4048         ath9k_hw_get_channel_centers(ah, chan, &centers);
4049         freq = isHt40Target ? centers.synth_center : centers.ctl_center;
4050
4051         if (freq <=
4052                 ath9k_hw_fbin2freq(powInfo[0].bChannel, IS_CHAN_2GHZ(chan))) {
4053                 matchIndex = 0;
4054         } else {
4055                 for (i = 0; (i < numChannels)
4056                      && (powInfo[i].bChannel != AR5416_BCHAN_UNUSED); i++) {
4057                         if (freq ==
4058                             ath9k_hw_fbin2freq(powInfo[i].bChannel,
4059                                                IS_CHAN_2GHZ(chan))) {
4060                                 matchIndex = i;
4061                                 break;
4062                         } else
4063                                 if ((freq <
4064                                      ath9k_hw_fbin2freq(powInfo[i].bChannel,
4065                                                         IS_CHAN_2GHZ(chan)))
4066                                     && (freq >
4067                                         ath9k_hw_fbin2freq(powInfo[i - 1].
4068                                                            bChannel,
4069                                                            IS_CHAN_2GHZ
4070                                                            (chan)))) {
4071                                         lowIndex = i - 1;
4072                                         break;
4073                                 }
4074                 }
4075                 if ((matchIndex == -1) && (lowIndex == -1))
4076                         matchIndex = i - 1;
4077         }
4078
4079         if (matchIndex != -1) {
4080                 *pNewPower = powInfo[matchIndex];
4081         } else {
4082                 clo = ath9k_hw_fbin2freq(powInfo[lowIndex].bChannel,
4083                                          IS_CHAN_2GHZ(chan));
4084                 chi = ath9k_hw_fbin2freq(powInfo[lowIndex + 1].bChannel,
4085                                          IS_CHAN_2GHZ(chan));
4086
4087                 for (i = 0; i < numRates; i++) {
4088                         pNewPower->tPow2x[i] =
4089                                 (u8) ath9k_hw_interpolate(freq, clo, chi,
4090                                                                 powInfo
4091                                                                 [lowIndex].
4092                                                                 tPow2x[i],
4093                                                                 powInfo
4094                                                                 [lowIndex +
4095                                                                  1].tPow2x[i]);
4096                 }
4097         }
4098 }
4099
4100 static u16
4101 ath9k_hw_get_max_edge_power(u16 freq,
4102                             struct cal_ctl_edges *pRdEdgesPower,
4103                             bool is2GHz)
4104 {
4105         u16 twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
4106         int i;
4107
4108         for (i = 0; (i < AR5416_NUM_BAND_EDGES)
4109              && (pRdEdgesPower[i].bChannel != AR5416_BCHAN_UNUSED); i++) {
4110                 if (freq == ath9k_hw_fbin2freq(pRdEdgesPower[i].bChannel,
4111                                                is2GHz)) {
4112                         twiceMaxEdgePower = pRdEdgesPower[i].tPower;
4113                         break;
4114                 } else if ((i > 0)
4115                            && (freq <
4116                                ath9k_hw_fbin2freq(pRdEdgesPower[i].
4117                                                   bChannel, is2GHz))) {
4118                         if (ath9k_hw_fbin2freq
4119                             (pRdEdgesPower[i - 1].bChannel, is2GHz) < freq
4120                             && pRdEdgesPower[i - 1].flag) {
4121                                 twiceMaxEdgePower =
4122                                         pRdEdgesPower[i - 1].tPower;
4123                         }
4124                         break;
4125                 }
4126         }
4127         return twiceMaxEdgePower;
4128 }
4129
4130 static bool
4131 ath9k_hw_set_power_per_rate_table(struct ath_hal *ah,
4132                                   struct ar5416_eeprom *pEepData,
4133                                   struct ath9k_channel *chan,
4134                                   int16_t *ratesArray,
4135                                   u16 cfgCtl,
4136                                   u8 AntennaReduction,
4137                                   u8 twiceMaxRegulatoryPower,
4138                                   u8 powerLimit)
4139 {
4140         u8 twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
4141         static const u16 tpScaleReductionTable[5] =
4142                 { 0, 3, 6, 9, AR5416_MAX_RATE_POWER };
4143
4144         int i;
4145         int8_t twiceLargestAntenna;
4146         struct cal_ctl_data *rep;
4147         struct cal_target_power_leg targetPowerOfdm, targetPowerCck = {
4148                 0, { 0, 0, 0, 0}
4149         };
4150         struct cal_target_power_leg targetPowerOfdmExt = {
4151                 0, { 0, 0, 0, 0} }, targetPowerCckExt = {
4152                 0, { 0, 0, 0, 0 }
4153         };
4154         struct cal_target_power_ht targetPowerHt20, targetPowerHt40 = {
4155                 0, {0, 0, 0, 0}
4156         };
4157         u8 scaledPower = 0, minCtlPower, maxRegAllowedPower;
4158         u16 ctlModesFor11a[] =
4159                 { CTL_11A, CTL_5GHT20, CTL_11A_EXT, CTL_5GHT40 };
4160         u16 ctlModesFor11g[] =
4161                 { CTL_11B, CTL_11G, CTL_2GHT20, CTL_11B_EXT, CTL_11G_EXT,
4162                   CTL_2GHT40
4163                 };
4164         u16 numCtlModes, *pCtlMode, ctlMode, freq;
4165         struct chan_centers centers;
4166         int tx_chainmask;
4167         u8 twiceMinEdgePower;
4168         struct ath_hal_5416 *ahp = AH5416(ah);
4169
4170         tx_chainmask = ahp->ah_txchainmask;
4171
4172         ath9k_hw_get_channel_centers(ah, chan, &centers);
4173
4174         twiceLargestAntenna = max(
4175                 pEepData->modalHeader
4176                         [IS_CHAN_2GHZ(chan)].antennaGainCh[0],
4177                 pEepData->modalHeader
4178                         [IS_CHAN_2GHZ(chan)].antennaGainCh[1]);
4179
4180         twiceLargestAntenna = max((u8) twiceLargestAntenna,
4181                 pEepData->modalHeader
4182                         [IS_CHAN_2GHZ(chan)].antennaGainCh[2]);
4183
4184         twiceLargestAntenna =
4185                 (int8_t) min(AntennaReduction - twiceLargestAntenna, 0);
4186
4187         maxRegAllowedPower = twiceMaxRegulatoryPower + twiceLargestAntenna;
4188
4189         if (ah->ah_tpScale != ATH9K_TP_SCALE_MAX) {
4190                 maxRegAllowedPower -=
4191                         (tpScaleReductionTable[(ah->ah_tpScale)] * 2);
4192         }
4193
4194         scaledPower = min(powerLimit, maxRegAllowedPower);
4195
4196         switch (ar5416_get_ntxchains(tx_chainmask)) {
4197         case 1:
4198                 break;
4199         case 2:
4200                 scaledPower -=
4201                         pEepData->modalHeader[IS_CHAN_2GHZ(chan)].
4202                         pwrDecreaseFor2Chain;
4203                 break;
4204         case 3:
4205                 scaledPower -=
4206                         pEepData->modalHeader[IS_CHAN_2GHZ(chan)].
4207                         pwrDecreaseFor3Chain;
4208                 break;
4209         }
4210
4211         scaledPower = max(0, (int32_t) scaledPower);
4212
4213         if (IS_CHAN_2GHZ(chan)) {
4214                 numCtlModes =
4215                         ARRAY_SIZE(ctlModesFor11g) -
4216                         SUB_NUM_CTL_MODES_AT_2G_40;
4217                 pCtlMode = ctlModesFor11g;
4218
4219                 ath9k_hw_get_legacy_target_powers(ah, chan,
4220                         pEepData->
4221                         calTargetPowerCck,
4222                         AR5416_NUM_2G_CCK_TARGET_POWERS,
4223                         &targetPowerCck, 4,
4224                         false);
4225                 ath9k_hw_get_legacy_target_powers(ah, chan,
4226                         pEepData->
4227                         calTargetPower2G,
4228                         AR5416_NUM_2G_20_TARGET_POWERS,
4229                         &targetPowerOfdm, 4,
4230                         false);
4231                 ath9k_hw_get_target_powers(ah, chan,
4232                         pEepData->calTargetPower2GHT20,
4233                         AR5416_NUM_2G_20_TARGET_POWERS,
4234                         &targetPowerHt20, 8, false);
4235
4236                 if (IS_CHAN_HT40(chan)) {
4237                         numCtlModes = ARRAY_SIZE(ctlModesFor11g);
4238                         ath9k_hw_get_target_powers(ah, chan,
4239                                 pEepData->
4240                                 calTargetPower2GHT40,
4241                                 AR5416_NUM_2G_40_TARGET_POWERS,
4242                                 &targetPowerHt40, 8,
4243                                 true);
4244                         ath9k_hw_get_legacy_target_powers(ah, chan,
4245                                 pEepData->
4246                                 calTargetPowerCck,
4247                                 AR5416_NUM_2G_CCK_TARGET_POWERS,
4248                                 &targetPowerCckExt,
4249                                 4, true);
4250                         ath9k_hw_get_legacy_target_powers(ah, chan,
4251                                 pEepData->
4252                                 calTargetPower2G,
4253                                 AR5416_NUM_2G_20_TARGET_POWERS,
4254                                 &targetPowerOfdmExt,
4255                                 4, true);
4256                 }
4257         } else {
4258
4259                 numCtlModes =
4260                         ARRAY_SIZE(ctlModesFor11a) -
4261                         SUB_NUM_CTL_MODES_AT_5G_40;
4262                 pCtlMode = ctlModesFor11a;
4263
4264                 ath9k_hw_get_legacy_target_powers(ah, chan,
4265                         pEepData->
4266                         calTargetPower5G,
4267                         AR5416_NUM_5G_20_TARGET_POWERS,
4268                         &targetPowerOfdm, 4,
4269                         false);
4270                 ath9k_hw_get_target_powers(ah, chan,
4271                         pEepData->calTargetPower5GHT20,
4272                         AR5416_NUM_5G_20_TARGET_POWERS,
4273                         &targetPowerHt20, 8, false);
4274
4275                 if (IS_CHAN_HT40(chan)) {
4276                         numCtlModes = ARRAY_SIZE(ctlModesFor11a);
4277                         ath9k_hw_get_target_powers(ah, chan,
4278                                 pEepData->
4279                                 calTargetPower5GHT40,
4280                                 AR5416_NUM_5G_40_TARGET_POWERS,
4281                                 &targetPowerHt40, 8,
4282                                 true);
4283                         ath9k_hw_get_legacy_target_powers(ah, chan,
4284                                 pEepData->
4285                                 calTargetPower5G,
4286                                 AR5416_NUM_5G_20_TARGET_POWERS,
4287                                 &targetPowerOfdmExt,
4288                                 4, true);
4289                 }
4290         }
4291
4292         for (ctlMode = 0; ctlMode < numCtlModes; ctlMode++) {
4293                 bool isHt40CtlMode =
4294                         (pCtlMode[ctlMode] == CTL_5GHT40)
4295                         || (pCtlMode[ctlMode] == CTL_2GHT40);
4296                 if (isHt40CtlMode)
4297                         freq = centers.synth_center;
4298                 else if (pCtlMode[ctlMode] & EXT_ADDITIVE)
4299                         freq = centers.ext_center;
4300                 else
4301                         freq = centers.ctl_center;
4302
4303                 if (ar5416_get_eep_ver(ahp) == 14
4304                     && ar5416_get_eep_rev(ahp) <= 2)
4305                         twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
4306
4307                 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
4308                         "LOOP-Mode ctlMode %d < %d, isHt40CtlMode %d, "
4309                         "EXT_ADDITIVE %d\n",
4310                          ctlMode, numCtlModes, isHt40CtlMode,
4311                          (pCtlMode[ctlMode] & EXT_ADDITIVE));
4312
4313                 for (i = 0; (i < AR5416_NUM_CTLS) && pEepData->ctlIndex[i];
4314                      i++) {
4315                         DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
4316                                 "  LOOP-Ctlidx %d: cfgCtl 0x%2.2x "
4317                                 "pCtlMode 0x%2.2x ctlIndex 0x%2.2x "
4318                                 "chan %d\n",
4319                                 i, cfgCtl, pCtlMode[ctlMode],
4320                                 pEepData->ctlIndex[i], chan->channel);
4321
4322                         if ((((cfgCtl & ~CTL_MODE_M) |
4323                               (pCtlMode[ctlMode] & CTL_MODE_M)) ==
4324                              pEepData->ctlIndex[i])
4325                             ||
4326                             (((cfgCtl & ~CTL_MODE_M) |
4327                               (pCtlMode[ctlMode] & CTL_MODE_M)) ==
4328                              ((pEepData->
4329                                ctlIndex[i] & CTL_MODE_M) | SD_NO_CTL))) {
4330                                 rep = &(pEepData->ctlData[i]);
4331
4332                                 twiceMinEdgePower =
4333                                         ath9k_hw_get_max_edge_power(freq,
4334                                                 rep->
4335                                                 ctlEdges
4336                                                 [ar5416_get_ntxchains
4337                                                 (tx_chainmask)
4338                                                 - 1],
4339                                                 IS_CHAN_2GHZ
4340                                                 (chan));
4341
4342                                 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
4343                                         "    MATCH-EE_IDX %d: ch %d is2 %d "
4344                                         "2xMinEdge %d chainmask %d chains %d\n",
4345                                          i, freq, IS_CHAN_2GHZ(chan),
4346                                          twiceMinEdgePower, tx_chainmask,
4347                                          ar5416_get_ntxchains
4348                                          (tx_chainmask));
4349                                 if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL) {
4350                                         twiceMaxEdgePower =
4351                                                 min(twiceMaxEdgePower,
4352                                                     twiceMinEdgePower);
4353                                 } else {
4354                                         twiceMaxEdgePower =
4355                                                 twiceMinEdgePower;
4356                                         break;
4357                                 }
4358                         }
4359                 }
4360
4361                 minCtlPower = min(twiceMaxEdgePower, scaledPower);
4362
4363                 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
4364                                 "    SEL-Min ctlMode %d pCtlMode %d "
4365                                 "2xMaxEdge %d sP %d minCtlPwr %d\n",
4366                          ctlMode, pCtlMode[ctlMode], twiceMaxEdgePower,
4367                          scaledPower, minCtlPower);
4368
4369                 switch (pCtlMode[ctlMode]) {
4370                 case CTL_11B:
4371                         for (i = 0; i < ARRAY_SIZE(targetPowerCck.tPow2x);
4372                              i++) {
4373                                 targetPowerCck.tPow2x[i] =
4374                                         min(targetPowerCck.tPow2x[i],
4375                                             minCtlPower);
4376                         }
4377                         break;
4378                 case CTL_11A:
4379                 case CTL_11G:
4380                         for (i = 0; i < ARRAY_SIZE(targetPowerOfdm.tPow2x);
4381                              i++) {
4382                                 targetPowerOfdm.tPow2x[i] =
4383                                         min(targetPowerOfdm.tPow2x[i],
4384                                             minCtlPower);
4385                         }
4386                         break;
4387                 case CTL_5GHT20:
4388                 case CTL_2GHT20:
4389                         for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x);
4390                              i++) {
4391                                 targetPowerHt20.tPow2x[i] =
4392                                         min(targetPowerHt20.tPow2x[i],
4393                                             minCtlPower);
4394                         }
4395                         break;
4396                 case CTL_11B_EXT:
4397                         targetPowerCckExt.tPow2x[0] =
4398                                 min(targetPowerCckExt.tPow2x[0], minCtlPower);
4399                         break;
4400                 case CTL_11A_EXT:
4401                 case CTL_11G_EXT:
4402                         targetPowerOfdmExt.tPow2x[0] =
4403                                 min(targetPowerOfdmExt.tPow2x[0], minCtlPower);
4404                         break;
4405                 case CTL_5GHT40:
4406                 case CTL_2GHT40:
4407                         for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x);
4408                              i++) {
4409                                 targetPowerHt40.tPow2x[i] =
4410                                         min(targetPowerHt40.tPow2x[i],
4411                                             minCtlPower);
4412                         }
4413                         break;
4414                 default:
4415                         break;
4416                 }
4417         }
4418
4419         ratesArray[rate6mb] = ratesArray[rate9mb] = ratesArray[rate12mb] =
4420                 ratesArray[rate18mb] = ratesArray[rate24mb] =
4421                 targetPowerOfdm.tPow2x[0];
4422         ratesArray[rate36mb] = targetPowerOfdm.tPow2x[1];
4423         ratesArray[rate48mb] = targetPowerOfdm.tPow2x[2];
4424         ratesArray[rate54mb] = targetPowerOfdm.tPow2x[3];
4425         ratesArray[rateXr] = targetPowerOfdm.tPow2x[0];
4426
4427         for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x); i++)
4428                 ratesArray[rateHt20_0 + i] = targetPowerHt20.tPow2x[i];
4429
4430         if (IS_CHAN_2GHZ(chan)) {
4431                 ratesArray[rate1l] = targetPowerCck.tPow2x[0];
4432                 ratesArray[rate2s] = ratesArray[rate2l] =
4433                         targetPowerCck.tPow2x[1];
4434                 ratesArray[rate5_5s] = ratesArray[rate5_5l] =
4435                         targetPowerCck.tPow2x[2];
4436                 ;
4437                 ratesArray[rate11s] = ratesArray[rate11l] =
4438                         targetPowerCck.tPow2x[3];
4439                 ;
4440         }
4441         if (IS_CHAN_HT40(chan)) {
4442                 for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x); i++) {
4443                         ratesArray[rateHt40_0 + i] =
4444                                 targetPowerHt40.tPow2x[i];
4445                 }
4446                 ratesArray[rateDupOfdm] = targetPowerHt40.tPow2x[0];
4447                 ratesArray[rateDupCck] = targetPowerHt40.tPow2x[0];
4448                 ratesArray[rateExtOfdm] = targetPowerOfdmExt.tPow2x[0];
4449                 if (IS_CHAN_2GHZ(chan)) {
4450                         ratesArray[rateExtCck] =
4451                                 targetPowerCckExt.tPow2x[0];
4452                 }
4453         }
4454         return true;
4455 }
4456
4457 static int
4458 ath9k_hw_set_txpower(struct ath_hal *ah,
4459                      struct ar5416_eeprom *pEepData,
4460                      struct ath9k_channel *chan,
4461                      u16 cfgCtl,
4462                      u8 twiceAntennaReduction,
4463                      u8 twiceMaxRegulatoryPower,
4464                      u8 powerLimit)
4465 {
4466         struct modal_eep_header *pModal =
4467                 &(pEepData->modalHeader[IS_CHAN_2GHZ(chan)]);
4468         int16_t ratesArray[Ar5416RateSize];
4469         int16_t txPowerIndexOffset = 0;
4470         u8 ht40PowerIncForPdadc = 2;
4471         int i;
4472
4473         memset(ratesArray, 0, sizeof(ratesArray));
4474
4475         if ((pEepData->baseEepHeader.
4476              version & AR5416_EEP_VER_MINOR_MASK) >=
4477             AR5416_EEP_MINOR_VER_2) {
4478                 ht40PowerIncForPdadc = pModal->ht40PowerIncForPdadc;
4479         }
4480
4481         if (!ath9k_hw_set_power_per_rate_table(ah, pEepData, chan,
4482                                                &ratesArray[0], cfgCtl,
4483                                                twiceAntennaReduction,
4484                                                twiceMaxRegulatoryPower,
4485                                                powerLimit)) {
4486                 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
4487                         "ath9k_hw_set_txpower: unable to set "
4488                         "tx power per rate table\n");
4489                 return -EIO;
4490         }
4491
4492         if (!ath9k_hw_set_power_cal_table
4493             (ah, pEepData, chan, &txPowerIndexOffset)) {
4494                 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
4495                          "ath9k_hw_set_txpower: unable to set power table\n");
4496                 return -EIO;
4497         }
4498
4499         for (i = 0; i < ARRAY_SIZE(ratesArray); i++) {
4500                 ratesArray[i] =
4501                         (int16_t) (txPowerIndexOffset + ratesArray[i]);
4502                 if (ratesArray[i] > AR5416_MAX_RATE_POWER)
4503                         ratesArray[i] = AR5416_MAX_RATE_POWER;
4504         }
4505
4506         if (AR_SREV_9280_10_OR_LATER(ah)) {
4507                 for (i = 0; i < Ar5416RateSize; i++)
4508                         ratesArray[i] -= AR5416_PWR_TABLE_OFFSET * 2;
4509         }
4510
4511         REG_WRITE(ah, AR_PHY_POWER_TX_RATE1,
4512                   ATH9K_POW_SM(ratesArray[rate18mb], 24)
4513                   | ATH9K_POW_SM(ratesArray[rate12mb], 16)
4514                   | ATH9K_POW_SM(ratesArray[rate9mb], 8)
4515                   | ATH9K_POW_SM(ratesArray[rate6mb], 0)
4516                 );
4517         REG_WRITE(ah, AR_PHY_POWER_TX_RATE2,
4518                   ATH9K_POW_SM(ratesArray[rate54mb], 24)
4519                   | ATH9K_POW_SM(ratesArray[rate48mb], 16)
4520                   | ATH9K_POW_SM(ratesArray[rate36mb], 8)
4521                   | ATH9K_POW_SM(ratesArray[rate24mb], 0)
4522                 );
4523
4524         if (IS_CHAN_2GHZ(chan)) {
4525                 REG_WRITE(ah, AR_PHY_POWER_TX_RATE3,
4526                           ATH9K_POW_SM(ratesArray[rate2s], 24)
4527                           | ATH9K_POW_SM(ratesArray[rate2l], 16)
4528                           | ATH9K_POW_SM(ratesArray[rateXr], 8)
4529                           | ATH9K_POW_SM(ratesArray[rate1l], 0)
4530                         );
4531                 REG_WRITE(ah, AR_PHY_POWER_TX_RATE4,
4532                           ATH9K_POW_SM(ratesArray[rate11s], 24)
4533                           | ATH9K_POW_SM(ratesArray[rate11l], 16)
4534                           | ATH9K_POW_SM(ratesArray[rate5_5s], 8)
4535                           | ATH9K_POW_SM(ratesArray[rate5_5l], 0)
4536                         );
4537         }
4538
4539         REG_WRITE(ah, AR_PHY_POWER_TX_RATE5,
4540                   ATH9K_POW_SM(ratesArray[rateHt20_3], 24)
4541                   | ATH9K_POW_SM(ratesArray[rateHt20_2], 16)
4542                   | ATH9K_POW_SM(ratesArray[rateHt20_1], 8)
4543                   | ATH9K_POW_SM(ratesArray[rateHt20_0], 0)
4544                 );
4545         REG_WRITE(ah, AR_PHY_POWER_TX_RATE6,
4546                   ATH9K_POW_SM(ratesArray[rateHt20_7], 24)
4547                   | ATH9K_POW_SM(ratesArray[rateHt20_6], 16)
4548                   | ATH9K_POW_SM(ratesArray[rateHt20_5], 8)
4549                   | ATH9K_POW_SM(ratesArray[rateHt20_4], 0)
4550                 );
4551
4552         if (IS_CHAN_HT40(chan)) {
4553                 REG_WRITE(ah, AR_PHY_POWER_TX_RATE7,
4554                           ATH9K_POW_SM(ratesArray[rateHt40_3] +
4555                                        ht40PowerIncForPdadc, 24)
4556                           | ATH9K_POW_SM(ratesArray[rateHt40_2] +
4557                                          ht40PowerIncForPdadc, 16)
4558                           | ATH9K_POW_SM(ratesArray[rateHt40_1] +
4559                                          ht40PowerIncForPdadc, 8)
4560                           | ATH9K_POW_SM(ratesArray[rateHt40_0] +
4561                                          ht40PowerIncForPdadc, 0)
4562                         );
4563                 REG_WRITE(ah, AR_PHY_POWER_TX_RATE8,
4564                           ATH9K_POW_SM(ratesArray[rateHt40_7] +
4565                                        ht40PowerIncForPdadc, 24)
4566                           | ATH9K_POW_SM(ratesArray[rateHt40_6] +
4567                                          ht40PowerIncForPdadc, 16)
4568                           | ATH9K_POW_SM(ratesArray[rateHt40_5] +
4569                                          ht40PowerIncForPdadc, 8)
4570                           | ATH9K_POW_SM(ratesArray[rateHt40_4] +
4571                                          ht40PowerIncForPdadc, 0)
4572                         );
4573
4574                 REG_WRITE(ah, AR_PHY_POWER_TX_RATE9,
4575                           ATH9K_POW_SM(ratesArray[rateExtOfdm], 24)
4576                           | ATH9K_POW_SM(ratesArray[rateExtCck], 16)
4577                           | ATH9K_POW_SM(ratesArray[rateDupOfdm], 8)
4578                           | ATH9K_POW_SM(ratesArray[rateDupCck], 0)
4579                         );
4580         }
4581
4582         REG_WRITE(ah, AR_PHY_POWER_TX_SUB,
4583                   ATH9K_POW_SM(pModal->pwrDecreaseFor3Chain, 6)
4584                   | ATH9K_POW_SM(pModal->pwrDecreaseFor2Chain, 0)
4585                 );
4586
4587         i = rate6mb;
4588         if (IS_CHAN_HT40(chan))
4589                 i = rateHt40_0;
4590         else if (IS_CHAN_HT20(chan))
4591                 i = rateHt20_0;
4592
4593         if (AR_SREV_9280_10_OR_LATER(ah))
4594                 ah->ah_maxPowerLevel =
4595                         ratesArray[i] + AR5416_PWR_TABLE_OFFSET * 2;
4596         else
4597                 ah->ah_maxPowerLevel = ratesArray[i];
4598
4599         return 0;
4600 }
4601
4602 static inline void ath9k_hw_get_delta_slope_vals(struct ath_hal *ah,
4603                                                  u32 coef_scaled,
4604                                                  u32 *coef_mantissa,
4605                                                  u32 *coef_exponent)
4606 {
4607         u32 coef_exp, coef_man;
4608
4609         for (coef_exp = 31; coef_exp > 0; coef_exp--)
4610                 if ((coef_scaled >> coef_exp) & 0x1)
4611                         break;
4612
4613         coef_exp = 14 - (coef_exp - COEF_SCALE_S);
4614
4615         coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
4616
4617         *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
4618         *coef_exponent = coef_exp - 16;
4619 }
4620
4621 static void
4622 ath9k_hw_set_delta_slope(struct ath_hal *ah,
4623                          struct ath9k_channel *chan)
4624 {
4625         u32 coef_scaled, ds_coef_exp, ds_coef_man;
4626         u32 clockMhzScaled = 0x64000000;
4627         struct chan_centers centers;
4628
4629         if (IS_CHAN_HALF_RATE(chan))
4630                 clockMhzScaled = clockMhzScaled >> 1;
4631         else if (IS_CHAN_QUARTER_RATE(chan))
4632                 clockMhzScaled = clockMhzScaled >> 2;
4633
4634         ath9k_hw_get_channel_centers(ah, chan, &centers);
4635         coef_scaled = clockMhzScaled / centers.synth_center;
4636
4637         ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
4638                                       &ds_coef_exp);
4639
4640         REG_RMW_FIELD(ah, AR_PHY_TIMING3,
4641                       AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
4642         REG_RMW_FIELD(ah, AR_PHY_TIMING3,
4643                       AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
4644
4645         coef_scaled = (9 * coef_scaled) / 10;
4646
4647         ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
4648                                       &ds_coef_exp);
4649
4650         REG_RMW_FIELD(ah, AR_PHY_HALFGI,
4651                       AR_PHY_HALFGI_DSC_MAN, ds_coef_man);
4652         REG_RMW_FIELD(ah, AR_PHY_HALFGI,
4653                       AR_PHY_HALFGI_DSC_EXP, ds_coef_exp);
4654 }
4655
4656 static void ath9k_hw_9280_spur_mitigate(struct ath_hal *ah,
4657                                         struct ath9k_channel *chan)
4658 {
4659         int bb_spur = AR_NO_SPUR;
4660         int freq;
4661         int bin, cur_bin;
4662         int bb_spur_off, spur_subchannel_sd;
4663         int spur_freq_sd;
4664         int spur_delta_phase;
4665         int denominator;
4666         int upper, lower, cur_vit_mask;
4667         int tmp, newVal;
4668         int i;
4669         int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
4670                           AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
4671         };
4672         int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
4673                          AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
4674         };
4675         int inc[4] = { 0, 100, 0, 0 };
4676         struct chan_centers centers;
4677
4678         int8_t mask_m[123];
4679         int8_t mask_p[123];
4680         int8_t mask_amt;
4681         int tmp_mask;
4682         int cur_bb_spur;
4683         bool is2GHz = IS_CHAN_2GHZ(chan);
4684
4685         memset(&mask_m, 0, sizeof(int8_t) * 123);
4686         memset(&mask_p, 0, sizeof(int8_t) * 123);
4687
4688         ath9k_hw_get_channel_centers(ah, chan, &centers);
4689         freq = centers.synth_center;
4690
4691         ah->ah_config.spurmode = SPUR_ENABLE_EEPROM;
4692         for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
4693                 cur_bb_spur = ath9k_hw_eeprom_get_spur_chan(ah, i, is2GHz);
4694
4695                 if (is2GHz)
4696                         cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_2GHZ;
4697                 else
4698                         cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_5GHZ;
4699
4700                 if (AR_NO_SPUR == cur_bb_spur)
4701                         break;
4702                 cur_bb_spur = cur_bb_spur - freq;
4703
4704                 if (IS_CHAN_HT40(chan)) {
4705                         if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT40) &&
4706                             (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT40)) {
4707                                 bb_spur = cur_bb_spur;
4708                                 break;
4709                         }
4710                 } else if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT20) &&
4711                            (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT20)) {
4712                         bb_spur = cur_bb_spur;
4713                         break;
4714                 }
4715         }
4716
4717         if (AR_NO_SPUR == bb_spur) {
4718                 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
4719                             AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
4720                 return;
4721         } else {
4722                 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
4723                             AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
4724         }
4725
4726         bin = bb_spur * 320;
4727
4728         tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
4729
4730         newVal = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
4731                         AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
4732                         AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
4733                         AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
4734         REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), newVal);
4735
4736         newVal = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
4737                   AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
4738                   AR_PHY_SPUR_REG_MASK_RATE_SELECT |
4739                   AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
4740                   SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
4741         REG_WRITE(ah, AR_PHY_SPUR_REG, newVal);
4742
4743         if (IS_CHAN_HT40(chan)) {
4744                 if (bb_spur < 0) {
4745                         spur_subchannel_sd = 1;
4746                         bb_spur_off = bb_spur + 10;
4747                 } else {
4748                         spur_subchannel_sd = 0;
4749                         bb_spur_off = bb_spur - 10;
4750                 }
4751         } else {
4752                 spur_subchannel_sd = 0;
4753                 bb_spur_off = bb_spur;
4754         }
4755
4756         if (IS_CHAN_HT40(chan))
4757                 spur_delta_phase =
4758                         ((bb_spur * 262144) /
4759                          10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
4760         else
4761                 spur_delta_phase =
4762                         ((bb_spur * 524288) /
4763                          10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
4764
4765         denominator = IS_CHAN_2GHZ(chan) ? 44 : 40;
4766         spur_freq_sd = ((bb_spur_off * 2048) / denominator) & 0x3ff;
4767
4768         newVal = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
4769                   SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
4770                   SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
4771         REG_WRITE(ah, AR_PHY_TIMING11, newVal);
4772
4773         newVal = spur_subchannel_sd << AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S;
4774         REG_WRITE(ah, AR_PHY_SFCORR_EXT, newVal);
4775
4776         cur_bin = -6000;
4777         upper = bin + 100;
4778         lower = bin - 100;
4779
4780         for (i = 0; i < 4; i++) {
4781                 int pilot_mask = 0;
4782                 int chan_mask = 0;
4783                 int bp = 0;
4784                 for (bp = 0; bp < 30; bp++) {
4785                         if ((cur_bin > lower) && (cur_bin < upper)) {
4786                                 pilot_mask = pilot_mask | 0x1 << bp;
4787                                 chan_mask = chan_mask | 0x1 << bp;
4788                         }
4789                         cur_bin += 100;
4790                 }
4791                 cur_bin += inc[i];
4792                 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
4793                 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
4794         }
4795
4796         cur_vit_mask = 6100;
4797         upper = bin + 120;
4798         lower = bin - 120;
4799
4800         for (i = 0; i < 123; i++) {
4801                 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
4802
4803                         /* workaround for gcc bug #37014 */
4804                         volatile int tmp = abs(cur_vit_mask - bin);
4805
4806                         if (tmp < 75)
4807                                 mask_amt = 1;
4808                         else
4809                                 mask_amt = 0;
4810                         if (cur_vit_mask < 0)
4811                                 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
4812                         else
4813                                 mask_p[cur_vit_mask / 100] = mask_amt;
4814                 }
4815                 cur_vit_mask -= 100;
4816         }
4817
4818         tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
4819                 | (mask_m[48] << 26) | (mask_m[49] << 24)
4820                 | (mask_m[50] << 22) | (mask_m[51] << 20)
4821                 | (mask_m[52] << 18) | (mask_m[53] << 16)
4822                 | (mask_m[54] << 14) | (mask_m[55] << 12)
4823                 | (mask_m[56] << 10) | (mask_m[57] << 8)
4824                 | (mask_m[58] << 6) | (mask_m[59] << 4)
4825                 | (mask_m[60] << 2) | (mask_m[61] << 0);
4826         REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
4827         REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
4828
4829         tmp_mask = (mask_m[31] << 28)
4830                 | (mask_m[32] << 26) | (mask_m[33] << 24)
4831                 | (mask_m[34] << 22) | (mask_m[35] << 20)
4832                 | (mask_m[36] << 18) | (mask_m[37] << 16)
4833                 | (mask_m[48] << 14) | (mask_m[39] << 12)
4834                 | (mask_m[40] << 10) | (mask_m[41] << 8)
4835                 | (mask_m[42] << 6) | (mask_m[43] << 4)
4836                 | (mask_m[44] << 2) | (mask_m[45] << 0);
4837         REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
4838         REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
4839
4840         tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
4841                 | (mask_m[18] << 26) | (mask_m[18] << 24)
4842                 | (mask_m[20] << 22) | (mask_m[20] << 20)
4843                 | (mask_m[22] << 18) | (mask_m[22] << 16)
4844                 | (mask_m[24] << 14) | (mask_m[24] << 12)
4845                 | (mask_m[25] << 10) | (mask_m[26] << 8)
4846                 | (mask_m[27] << 6) | (mask_m[28] << 4)
4847                 | (mask_m[29] << 2) | (mask_m[30] << 0);
4848         REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
4849         REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
4850
4851         tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
4852                 | (mask_m[2] << 26) | (mask_m[3] << 24)
4853                 | (mask_m[4] << 22) | (mask_m[5] << 20)
4854                 | (mask_m[6] << 18) | (mask_m[7] << 16)
4855                 | (mask_m[8] << 14) | (mask_m[9] << 12)
4856                 | (mask_m[10] << 10) | (mask_m[11] << 8)
4857                 | (mask_m[12] << 6) | (mask_m[13] << 4)
4858                 | (mask_m[14] << 2) | (mask_m[15] << 0);
4859         REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
4860         REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
4861
4862         tmp_mask = (mask_p[15] << 28)
4863                 | (mask_p[14] << 26) | (mask_p[13] << 24)
4864                 | (mask_p[12] << 22) | (mask_p[11] << 20)
4865                 | (mask_p[10] << 18) | (mask_p[9] << 16)
4866                 | (mask_p[8] << 14) | (mask_p[7] << 12)
4867                 | (mask_p[6] << 10) | (mask_p[5] << 8)
4868                 | (mask_p[4] << 6) | (mask_p[3] << 4)
4869                 | (mask_p[2] << 2) | (mask_p[1] << 0);
4870         REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
4871         REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
4872
4873         tmp_mask = (mask_p[30] << 28)
4874                 | (mask_p[29] << 26) | (mask_p[28] << 24)
4875                 | (mask_p[27] << 22) | (mask_p[26] << 20)
4876                 | (mask_p[25] << 18) | (mask_p[24] << 16)
4877                 | (mask_p[23] << 14) | (mask_p[22] << 12)
4878                 | (mask_p[21] << 10) | (mask_p[20] << 8)
4879                 | (mask_p[19] << 6) | (mask_p[18] << 4)
4880                 | (mask_p[17] << 2) | (mask_p[16] << 0);
4881         REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
4882         REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
4883
4884         tmp_mask = (mask_p[45] << 28)
4885                 | (mask_p[44] << 26) | (mask_p[43] << 24)
4886                 | (mask_p[42] << 22) | (mask_p[41] << 20)
4887                 | (mask_p[40] << 18) | (mask_p[39] << 16)
4888                 | (mask_p[38] << 14) | (mask_p[37] << 12)
4889                 | (mask_p[36] << 10) | (mask_p[35] << 8)
4890                 | (mask_p[34] << 6) | (mask_p[33] << 4)
4891                 | (mask_p[32] << 2) | (mask_p[31] << 0);
4892         REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
4893         REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
4894
4895         tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
4896                 | (mask_p[59] << 26) | (mask_p[58] << 24)
4897                 | (mask_p[57] << 22) | (mask_p[56] << 20)
4898                 | (mask_p[55] << 18) | (mask_p[54] << 16)
4899                 | (mask_p[53] << 14) | (mask_p[52] << 12)
4900                 | (mask_p[51] << 10) | (mask_p[50] << 8)
4901                 | (mask_p[49] << 6) | (mask_p[48] << 4)
4902                 | (mask_p[47] << 2) | (mask_p[46] << 0);
4903         REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
4904         REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
4905 }
4906
4907 static void ath9k_hw_spur_mitigate(struct ath_hal *ah,
4908                                    struct ath9k_channel *chan)
4909 {
4910         int bb_spur = AR_NO_SPUR;
4911         int bin, cur_bin;
4912         int spur_freq_sd;
4913         int spur_delta_phase;
4914         int denominator;
4915         int upper, lower, cur_vit_mask;
4916         int tmp, new;
4917         int i;
4918         int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
4919                           AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
4920         };
4921         int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
4922                          AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
4923         };
4924         int inc[4] = { 0, 100, 0, 0 };
4925
4926         int8_t mask_m[123];
4927         int8_t mask_p[123];
4928         int8_t mask_amt;
4929         int tmp_mask;
4930         int cur_bb_spur;
4931         bool is2GHz = IS_CHAN_2GHZ(chan);
4932
4933         memset(&mask_m, 0, sizeof(int8_t) * 123);
4934         memset(&mask_p, 0, sizeof(int8_t) * 123);
4935
4936         for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
4937                 cur_bb_spur = ath9k_hw_eeprom_get_spur_chan(ah, i, is2GHz);
4938                 if (AR_NO_SPUR == cur_bb_spur)
4939                         break;
4940                 cur_bb_spur = cur_bb_spur - (chan->channel * 10);
4941                 if ((cur_bb_spur > -95) && (cur_bb_spur < 95)) {
4942                         bb_spur = cur_bb_spur;
4943                         break;
4944                 }
4945         }
4946
4947         if (AR_NO_SPUR == bb_spur)
4948                 return;
4949
4950         bin = bb_spur * 32;
4951
4952         tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
4953         new = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
4954                      AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
4955                      AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
4956                      AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
4957
4958         REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), new);
4959
4960         new = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
4961                AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
4962                AR_PHY_SPUR_REG_MASK_RATE_SELECT |
4963                AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
4964                SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
4965         REG_WRITE(ah, AR_PHY_SPUR_REG, new);
4966
4967         spur_delta_phase = ((bb_spur * 524288) / 100) &
4968                 AR_PHY_TIMING11_SPUR_DELTA_PHASE;
4969
4970         denominator = IS_CHAN_2GHZ(chan) ? 440 : 400;
4971         spur_freq_sd = ((bb_spur * 2048) / denominator) & 0x3ff;
4972
4973         new = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
4974                SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
4975                SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
4976         REG_WRITE(ah, AR_PHY_TIMING11, new);
4977
4978         cur_bin = -6000;
4979         upper = bin + 100;
4980         lower = bin - 100;
4981
4982         for (i = 0; i < 4; i++) {
4983                 int pilot_mask = 0;
4984                 int chan_mask = 0;
4985                 int bp = 0;
4986                 for (bp = 0; bp < 30; bp++) {
4987                         if ((cur_bin > lower) && (cur_bin < upper)) {
4988                                 pilot_mask = pilot_mask | 0x1 << bp;
4989                                 chan_mask = chan_mask | 0x1 << bp;
4990                         }
4991                         cur_bin += 100;
4992                 }
4993                 cur_bin += inc[i];
4994                 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
4995                 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
4996         }
4997
4998         cur_vit_mask = 6100;
4999         upper = bin + 120;
5000         lower = bin - 120;
5001
5002         for (i = 0; i < 123; i++) {
5003                 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
5004
5005                         /* workaround for gcc bug #37014 */
5006                         volatile int tmp = abs(cur_vit_mask - bin);
5007
5008                         if (tmp < 75)
5009                                 mask_amt = 1;
5010                         else
5011                                 mask_amt = 0;
5012                         if (cur_vit_mask < 0)
5013                                 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
5014                         else
5015                                 mask_p[cur_vit_mask / 100] = mask_amt;
5016                 }
5017                 cur_vit_mask -= 100;
5018         }
5019
5020         tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
5021                 | (mask_m[48] << 26) | (mask_m[49] << 24)
5022                 | (mask_m[50] << 22) | (mask_m[51] << 20)
5023                 | (mask_m[52] << 18) | (mask_m[53] << 16)
5024                 | (mask_m[54] << 14) | (mask_m[55] << 12)
5025                 | (mask_m[56] << 10) | (mask_m[57] << 8)
5026                 | (mask_m[58] << 6) | (mask_m[59] << 4)
5027                 | (mask_m[60] << 2) | (mask_m[61] << 0);
5028         REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
5029         REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
5030
5031         tmp_mask = (mask_m[31] << 28)
5032                 | (mask_m[32] << 26) | (mask_m[33] << 24)
5033                 | (mask_m[34] << 22) | (mask_m[35] << 20)
5034                 | (mask_m[36] << 18) | (mask_m[37] << 16)
5035                 | (mask_m[48] << 14) | (mask_m[39] << 12)
5036                 | (mask_m[40] << 10) | (mask_m[41] << 8)
5037                 | (mask_m[42] << 6) | (mask_m[43] << 4)
5038                 | (mask_m[44] << 2) | (mask_m[45] << 0);
5039         REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
5040         REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
5041
5042         tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
5043                 | (mask_m[18] << 26) | (mask_m[18] << 24)
5044                 | (mask_m[20] << 22) | (mask_m[20] << 20)
5045                 | (mask_m[22] << 18) | (mask_m[22] << 16)
5046                 | (mask_m[24] << 14) | (mask_m[24] << 12)
5047                 | (mask_m[25] << 10) | (mask_m[26] << 8)
5048                 | (mask_m[27] << 6) | (mask_m[28] << 4)
5049                 | (mask_m[29] << 2) | (mask_m[30] << 0);
5050         REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
5051         REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
5052
5053         tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
5054                 | (mask_m[2] << 26) | (mask_m[3] << 24)
5055                 | (mask_m[4] << 22) | (mask_m[5] << 20)
5056                 | (mask_m[6] << 18) | (mask_m[7] << 16)
5057                 | (mask_m[8] << 14) | (mask_m[9] << 12)
5058                 | (mask_m[10] << 10) | (mask_m[11] << 8)
5059                 | (mask_m[12] << 6) | (mask_m[13] << 4)
5060                 | (mask_m[14] << 2) | (mask_m[15] << 0);
5061         REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
5062         REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
5063
5064         tmp_mask = (mask_p[15] << 28)
5065                 | (mask_p[14] << 26) | (mask_p[13] << 24)
5066                 | (mask_p[12] << 22) | (mask_p[11] << 20)
5067                 | (mask_p[10] << 18) | (mask_p[9] << 16)
5068                 | (mask_p[8] << 14) | (mask_p[7] << 12)
5069                 | (mask_p[6] << 10) | (mask_p[5] << 8)
5070                 | (mask_p[4] << 6) | (mask_p[3] << 4)
5071                 | (mask_p[2] << 2) | (mask_p[1] << 0);
5072         REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
5073         REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
5074
5075         tmp_mask = (mask_p[30] << 28)
5076                 | (mask_p[29] << 26) | (mask_p[28] << 24)
5077                 | (mask_p[27] << 22) | (mask_p[26] << 20)
5078                 | (mask_p[25] << 18) | (mask_p[24] << 16)
5079                 | (mask_p[23] << 14) | (mask_p[22] << 12)
5080                 | (mask_p[21] << 10) | (mask_p[20] << 8)
5081                 | (mask_p[19] << 6) | (mask_p[18] << 4)
5082                 | (mask_p[17] << 2) | (mask_p[16] << 0);
5083         REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
5084         REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
5085
5086         tmp_mask = (mask_p[45] << 28)
5087                 | (mask_p[44] << 26) | (mask_p[43] << 24)
5088                 | (mask_p[42] << 22) | (mask_p[41] << 20)
5089                 | (mask_p[40] << 18) | (mask_p[39] << 16)
5090                 | (mask_p[38] << 14) | (mask_p[37] << 12)
5091                 | (mask_p[36] << 10) | (mask_p[35] << 8)
5092                 | (mask_p[34] << 6) | (mask_p[33] << 4)
5093                 | (mask_p[32] << 2) | (mask_p[31] << 0);
5094         REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
5095         REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
5096
5097         tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
5098                 | (mask_p[59] << 26) | (mask_p[58] << 24)
5099                 | (mask_p[57] << 22) | (mask_p[56] << 20)
5100                 | (mask_p[55] << 18) | (mask_p[54] << 16)
5101                 | (mask_p[53] << 14) | (mask_p[52] << 12)
5102                 | (mask_p[51] << 10) | (mask_p[50] << 8)
5103                 | (mask_p[49] << 6) | (mask_p[48] << 4)
5104                 | (mask_p[47] << 2) | (mask_p[46] << 0);
5105         REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
5106         REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
5107 }
5108
5109 static void ath9k_hw_init_chain_masks(struct ath_hal *ah)
5110 {
5111         struct ath_hal_5416 *ahp = AH5416(ah);
5112         int rx_chainmask, tx_chainmask;
5113
5114         rx_chainmask = ahp->ah_rxchainmask;
5115         tx_chainmask = ahp->ah_txchainmask;
5116
5117         switch (rx_chainmask) {
5118         case 0x5:
5119                 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
5120                             AR_PHY_SWAP_ALT_CHAIN);
5121         case 0x3:
5122                 if (((ah)->ah_macVersion <= AR_SREV_VERSION_9160)) {
5123                         REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7);
5124                         REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7);
5125                         break;
5126                 }
5127         case 0x1:
5128         case 0x2:
5129                 if (!AR_SREV_9280(ah))
5130                         break;
5131         case 0x7:
5132                 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
5133                 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
5134                 break;
5135         default:
5136                 break;
5137         }
5138
5139         REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask);
5140         if (tx_chainmask == 0x5) {
5141                 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
5142                             AR_PHY_SWAP_ALT_CHAIN);
5143         }
5144         if (AR_SREV_9100(ah))
5145                 REG_WRITE(ah, AR_PHY_ANALOG_SWAP,
5146                           REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001);
5147 }
5148
5149 static void ath9k_hw_set_addac(struct ath_hal *ah,
5150                                struct ath9k_channel *chan)
5151 {
5152         struct modal_eep_header *pModal;
5153         struct ath_hal_5416 *ahp = AH5416(ah);
5154         struct ar5416_eeprom *eep = &ahp->ah_eeprom;
5155         u8 biaslevel;
5156
5157         if (ah->ah_macVersion != AR_SREV_VERSION_9160)
5158                 return;
5159
5160         if (ar5416_get_eep_rev(ahp) < AR5416_EEP_MINOR_VER_7)
5161                 return;
5162
5163         pModal = &(eep->modalHeader[IS_CHAN_2GHZ(chan)]);
5164
5165         if (pModal->xpaBiasLvl != 0xff) {
5166                 biaslevel = pModal->xpaBiasLvl;
5167         } else {
5168
5169                 u16 resetFreqBin, freqBin, freqCount = 0;
5170                 struct chan_centers centers;
5171
5172                 ath9k_hw_get_channel_centers(ah, chan, &centers);
5173
5174                 resetFreqBin =
5175                         FREQ2FBIN(centers.synth_center, IS_CHAN_2GHZ(chan));
5176                 freqBin = pModal->xpaBiasLvlFreq[0] & 0xff;
5177                 biaslevel = (u8) (pModal->xpaBiasLvlFreq[0] >> 14);
5178
5179                 freqCount++;
5180
5181                 while (freqCount < 3) {
5182                         if (pModal->xpaBiasLvlFreq[freqCount] == 0x0)
5183                                 break;
5184
5185                         freqBin = pModal->xpaBiasLvlFreq[freqCount] & 0xff;
5186                         if (resetFreqBin >= freqBin) {
5187                                 biaslevel =
5188                                         (u8) (pModal->
5189                                                     xpaBiasLvlFreq[freqCount]
5190                                                     >> 14);
5191                         } else {
5192                                 break;
5193                         }
5194                         freqCount++;
5195                 }
5196         }
5197
5198         if (IS_CHAN_2GHZ(chan)) {
5199                 INI_RA(&ahp->ah_iniAddac, 7, 1) =
5200                         (INI_RA(&ahp->ah_iniAddac, 7, 1) & (~0x18)) | biaslevel
5201                         << 3;
5202         } else {
5203                 INI_RA(&ahp->ah_iniAddac, 6, 1) =
5204                         (INI_RA(&ahp->ah_iniAddac, 6, 1) & (~0xc0)) | biaslevel
5205                         << 6;
5206         }
5207 }
5208
5209 static u32 ath9k_hw_mac_usec(struct ath_hal *ah, u32 clks)
5210 {
5211         if (ah->ah_curchan != NULL)
5212                 return clks /
5213                 CLOCK_RATE[ath9k_hw_chan2wmode(ah, ah->ah_curchan)];
5214         else
5215                 return clks / CLOCK_RATE[ATH9K_MODE_11B];
5216 }
5217
5218 static u32 ath9k_hw_mac_to_usec(struct ath_hal *ah, u32 clks)
5219 {
5220         struct ath9k_channel *chan = ah->ah_curchan;
5221
5222         if (chan && IS_CHAN_HT40(chan))
5223                 return ath9k_hw_mac_usec(ah, clks) / 2;
5224         else
5225                 return ath9k_hw_mac_usec(ah, clks);
5226 }
5227
5228 static u32 ath9k_hw_mac_clks(struct ath_hal *ah, u32 usecs)
5229 {
5230         if (ah->ah_curchan != NULL)
5231                 return usecs * CLOCK_RATE[ath9k_hw_chan2wmode(ah,
5232                         ah->ah_curchan)];
5233         else
5234                 return usecs * CLOCK_RATE[ATH9K_MODE_11B];
5235 }
5236
5237 static u32 ath9k_hw_mac_to_clks(struct ath_hal *ah, u32 usecs)
5238 {
5239         struct ath9k_channel *chan = ah->ah_curchan;
5240
5241         if (chan && IS_CHAN_HT40(chan))
5242                 return ath9k_hw_mac_clks(ah, usecs) * 2;
5243         else
5244                 return ath9k_hw_mac_clks(ah, usecs);
5245 }
5246
5247 static bool ath9k_hw_set_ack_timeout(struct ath_hal *ah, u32 us)
5248 {
5249         struct ath_hal_5416 *ahp = AH5416(ah);
5250
5251         if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_ACK))) {
5252                 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "%s: bad ack timeout %u\n",
5253                          __func__, us);
5254                 ahp->ah_acktimeout = (u32) -1;
5255                 return false;
5256         } else {
5257                 REG_RMW_FIELD(ah, AR_TIME_OUT,
5258                               AR_TIME_OUT_ACK, ath9k_hw_mac_to_clks(ah, us));
5259                 ahp->ah_acktimeout = us;
5260                 return true;
5261         }
5262 }
5263
5264 static bool ath9k_hw_set_cts_timeout(struct ath_hal *ah, u32 us)
5265 {
5266         struct ath_hal_5416 *ahp = AH5416(ah);
5267
5268         if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_CTS))) {
5269                 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "%s: bad cts timeout %u\n",
5270                          __func__, us);
5271                 ahp->ah_ctstimeout = (u32) -1;
5272                 return false;
5273         } else {
5274                 REG_RMW_FIELD(ah, AR_TIME_OUT,
5275                               AR_TIME_OUT_CTS, ath9k_hw_mac_to_clks(ah, us));
5276                 ahp->ah_ctstimeout = us;
5277                 return true;
5278         }
5279 }
5280 static bool ath9k_hw_set_global_txtimeout(struct ath_hal *ah,
5281                                           u32 tu)
5282 {
5283         struct ath_hal_5416 *ahp = AH5416(ah);
5284
5285         if (tu > 0xFFFF) {
5286                 DPRINTF(ah->ah_sc, ATH_DBG_XMIT,
5287                         "%s: bad global tx timeout %u\n", __func__, tu);
5288                 ahp->ah_globaltxtimeout = (u32) -1;
5289                 return false;
5290         } else {
5291                 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
5292                 ahp->ah_globaltxtimeout = tu;
5293                 return true;
5294         }
5295 }
5296
5297 bool ath9k_hw_setslottime(struct ath_hal *ah, u32 us)
5298 {
5299         struct ath_hal_5416 *ahp = AH5416(ah);
5300
5301         if (us < ATH9K_SLOT_TIME_9 || us > ath9k_hw_mac_to_usec(ah, 0xffff)) {
5302                 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "%s: bad slot time %u\n",
5303                          __func__, us);
5304                 ahp->ah_slottime = (u32) -1;
5305                 return false;
5306         } else {
5307                 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, ath9k_hw_mac_to_clks(ah, us));
5308                 ahp->ah_slottime = us;
5309                 return true;
5310         }
5311 }
5312
5313 static void ath9k_hw_init_user_settings(struct ath_hal *ah)
5314 {
5315         struct ath_hal_5416 *ahp = AH5416(ah);
5316
5317         DPRINTF(ah->ah_sc, ATH_DBG_RESET, "--AP %s ahp->ah_miscMode 0x%x\n",
5318                  __func__, ahp->ah_miscMode);
5319         if (ahp->ah_miscMode != 0)
5320                 REG_WRITE(ah, AR_PCU_MISC,
5321                           REG_READ(ah, AR_PCU_MISC) | ahp->ah_miscMode);
5322         if (ahp->ah_slottime != (u32) -1)
5323                 ath9k_hw_setslottime(ah, ahp->ah_slottime);
5324         if (ahp->ah_acktimeout != (u32) -1)
5325                 ath9k_hw_set_ack_timeout(ah, ahp->ah_acktimeout);
5326         if (ahp->ah_ctstimeout != (u32) -1)
5327                 ath9k_hw_set_cts_timeout(ah, ahp->ah_ctstimeout);
5328         if (ahp->ah_globaltxtimeout != (u32) -1)
5329                 ath9k_hw_set_global_txtimeout(ah, ahp->ah_globaltxtimeout);
5330 }
5331
5332 static int
5333 ath9k_hw_process_ini(struct ath_hal *ah,
5334                      struct ath9k_channel *chan,
5335                      enum ath9k_ht_macmode macmode)
5336 {
5337         int i, regWrites = 0;
5338         struct ath_hal_5416 *ahp = AH5416(ah);
5339         u32 modesIndex, freqIndex;
5340         int status;
5341
5342         switch (chan->chanmode) {
5343         case CHANNEL_A:
5344         case CHANNEL_A_HT20:
5345                 modesIndex = 1;
5346                 freqIndex = 1;
5347                 break;
5348         case CHANNEL_A_HT40PLUS:
5349         case CHANNEL_A_HT40MINUS:
5350                 modesIndex = 2;
5351                 freqIndex = 1;
5352                 break;
5353         case CHANNEL_G:
5354         case CHANNEL_G_HT20:
5355         case CHANNEL_B:
5356                 modesIndex = 4;
5357                 freqIndex = 2;
5358                 break;
5359         case CHANNEL_G_HT40PLUS:
5360         case CHANNEL_G_HT40MINUS:
5361                 modesIndex = 3;
5362                 freqIndex = 2;
5363                 break;
5364
5365         default:
5366                 return -EINVAL;
5367         }
5368
5369         REG_WRITE(ah, AR_PHY(0), 0x00000007);
5370
5371         REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO);
5372
5373         ath9k_hw_set_addac(ah, chan);
5374
5375         if (AR_SREV_5416_V22_OR_LATER(ah)) {
5376                 REG_WRITE_ARRAY(&ahp->ah_iniAddac, 1, regWrites);
5377         } else {
5378                 struct ar5416IniArray temp;
5379                 u32 addacSize =
5380                         sizeof(u32) * ahp->ah_iniAddac.ia_rows *
5381                         ahp->ah_iniAddac.ia_columns;
5382
5383                 memcpy(ahp->ah_addac5416_21,
5384                        ahp->ah_iniAddac.ia_array, addacSize);
5385
5386                 (ahp->ah_addac5416_21)[31 *
5387                                        ahp->ah_iniAddac.ia_columns + 1] = 0;
5388
5389                 temp.ia_array = ahp->ah_addac5416_21;
5390                 temp.ia_columns = ahp->ah_iniAddac.ia_columns;
5391                 temp.ia_rows = ahp->ah_iniAddac.ia_rows;
5392                 REG_WRITE_ARRAY(&temp, 1, regWrites);
5393         }
5394         REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
5395
5396         for (i = 0; i < ahp->ah_iniModes.ia_rows; i++) {
5397                 u32 reg = INI_RA(&ahp->ah_iniModes, i, 0);
5398                 u32 val = INI_RA(&ahp->ah_iniModes, i, modesIndex);
5399
5400 #ifdef CONFIG_SLOW_ANT_DIV
5401                 if (ah->ah_devid == AR9280_DEVID_PCI)
5402                         val = ath9k_hw_ini_fixup(ah, &ahp->ah_eeprom, reg,
5403                                                  val);
5404 #endif
5405
5406                 REG_WRITE(ah, reg, val);
5407
5408                 if (reg >= 0x7800 && reg < 0x78a0
5409                     && ah->ah_config.analog_shiftreg) {
5410                         udelay(100);
5411                 }
5412
5413                 DO_DELAY(regWrites);
5414         }
5415
5416         for (i = 0; i < ahp->ah_iniCommon.ia_rows; i++) {
5417                 u32 reg = INI_RA(&ahp->ah_iniCommon, i, 0);
5418                 u32 val = INI_RA(&ahp->ah_iniCommon, i, 1);
5419
5420                 REG_WRITE(ah, reg, val);
5421
5422                 if (reg >= 0x7800 && reg < 0x78a0
5423                     && ah->ah_config.analog_shiftreg) {
5424                         udelay(100);
5425                 }
5426
5427                 DO_DELAY(regWrites);
5428         }
5429
5430         ath9k_hw_write_regs(ah, modesIndex, freqIndex, regWrites);
5431
5432         if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan)) {
5433                 REG_WRITE_ARRAY(&ahp->ah_iniModesAdditional, modesIndex,
5434                                 regWrites);
5435         }
5436
5437         ath9k_hw_override_ini(ah, chan);
5438         ath9k_hw_set_regs(ah, chan, macmode);
5439         ath9k_hw_init_chain_masks(ah);
5440
5441         status = ath9k_hw_set_txpower(ah, &ahp->ah_eeprom, chan,
5442                                       ath9k_regd_get_ctl(ah, chan),
5443                                       ath9k_regd_get_antenna_allowed(ah,
5444                                                                      chan),
5445                                       chan->maxRegTxPower * 2,
5446                                       min((u32) MAX_RATE_POWER,
5447                                           (u32) ah->ah_powerLimit));
5448         if (status != 0) {
5449                 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
5450                          "%s: error init'ing transmit power\n", __func__);
5451                 return -EIO;
5452         }
5453
5454         if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) {
5455                 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
5456                          "%s: ar5416SetRfRegs failed\n", __func__);
5457                 return -EIO;
5458         }
5459
5460         return 0;
5461 }
5462
5463 static void ath9k_hw_setup_calibration(struct ath_hal *ah,
5464                                               struct hal_cal_list *currCal)
5465 {
5466         REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(0),
5467                       AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX,
5468                       currCal->calData->calCountMax);
5469
5470         switch (currCal->calData->calType) {
5471         case IQ_MISMATCH_CAL:
5472                 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_IQ);
5473                 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
5474                          "%s: starting IQ Mismatch Calibration\n",
5475                          __func__);
5476                 break;
5477         case ADC_GAIN_CAL:
5478                 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_GAIN);
5479                 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
5480                          "%s: starting ADC Gain Calibration\n", __func__);
5481                 break;
5482         case ADC_DC_CAL:
5483                 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_DC_PER);
5484                 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
5485                          "%s: starting ADC DC Calibration\n", __func__);
5486                 break;
5487         case ADC_DC_INIT_CAL:
5488                 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_DC_INIT);
5489                 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
5490                          "%s: starting Init ADC DC Calibration\n",
5491                          __func__);
5492                 break;
5493         }
5494
5495         REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4(0),
5496                     AR_PHY_TIMING_CTRL4_DO_CAL);
5497 }
5498
5499 static void ath9k_hw_reset_calibration(struct ath_hal *ah,
5500                                        struct hal_cal_list *currCal)
5501 {
5502         struct ath_hal_5416 *ahp = AH5416(ah);
5503         int i;
5504
5505         ath9k_hw_setup_calibration(ah, currCal);
5506
5507         currCal->calState = CAL_RUNNING;
5508
5509         for (i = 0; i < AR5416_MAX_CHAINS; i++) {
5510                 ahp->ah_Meas0.sign[i] = 0;
5511                 ahp->ah_Meas1.sign[i] = 0;
5512                 ahp->ah_Meas2.sign[i] = 0;
5513                 ahp->ah_Meas3.sign[i] = 0;
5514         }
5515
5516         ahp->ah_CalSamples = 0;
5517 }
5518
5519 static void
5520 ath9k_hw_per_calibration(struct ath_hal *ah,
5521                          struct ath9k_channel *ichan,
5522                          u8 rxchainmask,
5523                          struct hal_cal_list *currCal,
5524                          bool *isCalDone)
5525 {
5526         struct ath_hal_5416 *ahp = AH5416(ah);
5527
5528         *isCalDone = false;
5529
5530         if (currCal->calState == CAL_RUNNING) {
5531                 if (!(REG_READ(ah,
5532                                AR_PHY_TIMING_CTRL4(0)) &
5533                       AR_PHY_TIMING_CTRL4_DO_CAL)) {
5534
5535                         currCal->calData->calCollect(ah);
5536
5537                         ahp->ah_CalSamples++;
5538
5539                         if (ahp->ah_CalSamples >=
5540                             currCal->calData->calNumSamples) {
5541                                 int i, numChains = 0;
5542                                 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
5543                                         if (rxchainmask & (1 << i))
5544                                                 numChains++;
5545                                 }
5546
5547                                 currCal->calData->calPostProc(ah,
5548                                                               numChains);
5549
5550                                 ichan->CalValid |=
5551                                         currCal->calData->calType;
5552                                 currCal->calState = CAL_DONE;
5553                                 *isCalDone = true;
5554                         } else {
5555                                 ath9k_hw_setup_calibration(ah, currCal);
5556                         }
5557                 }
5558         } else if (!(ichan->CalValid & currCal->calData->calType)) {
5559                 ath9k_hw_reset_calibration(ah, currCal);
5560         }
5561 }
5562
5563 static inline bool ath9k_hw_run_init_cals(struct ath_hal *ah,
5564                                           int init_cal_count)
5565 {
5566         struct ath_hal_5416 *ahp = AH5416(ah);
5567         struct ath9k_channel ichan;
5568         bool isCalDone;
5569         struct hal_cal_list *currCal = ahp->ah_cal_list_curr;
5570         const struct hal_percal_data *calData = currCal->calData;
5571         int i;
5572
5573         if (currCal == NULL)
5574                 return false;
5575
5576         ichan.CalValid = 0;
5577
5578         for (i = 0; i < init_cal_count; i++) {
5579                 ath9k_hw_reset_calibration(ah, currCal);
5580
5581                 if (!ath9k_hw_wait(ah, AR_PHY_TIMING_CTRL4(0),
5582                                    AR_PHY_TIMING_CTRL4_DO_CAL, 0)) {
5583                         DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
5584                                  "%s: Cal %d failed to complete in 100ms.\n",
5585                                  __func__, calData->calType);
5586
5587                         ahp->ah_cal_list = ahp->ah_cal_list_last =
5588                                 ahp->ah_cal_list_curr = NULL;
5589                         return false;
5590                 }
5591
5592                 ath9k_hw_per_calibration(ah, &ichan, ahp->ah_rxchainmask,
5593                                          currCal, &isCalDone);
5594                 if (!isCalDone) {
5595                         DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
5596                                  "%s: Not able to run Init Cal %d.\n",
5597                                  __func__, calData->calType);
5598                 }
5599                 if (currCal->calNext) {
5600                         currCal = currCal->calNext;
5601                         calData = currCal->calData;
5602                 }
5603         }
5604
5605         ahp->ah_cal_list = ahp->ah_cal_list_last = ahp->ah_cal_list_curr = NULL;
5606         return true;
5607 }
5608
5609 static bool
5610 ath9k_hw_channel_change(struct ath_hal *ah,
5611                         struct ath9k_channel *chan,
5612                         enum ath9k_ht_macmode macmode)
5613 {
5614         u32 synthDelay, qnum;
5615         struct ath_hal_5416 *ahp = AH5416(ah);
5616
5617         for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
5618                 if (ath9k_hw_numtxpending(ah, qnum)) {
5619                         DPRINTF(ah->ah_sc, ATH_DBG_QUEUE,
5620                                  "%s: Transmit frames pending on queue %d\n",
5621                                  __func__, qnum);
5622                         return false;
5623                 }
5624         }
5625
5626         REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
5627         if (!ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
5628                            AR_PHY_RFBUS_GRANT_EN)) {
5629                 DPRINTF(ah->ah_sc, ATH_DBG_PHY_IO,
5630                          "%s: Could not kill baseband RX\n", __func__);
5631                 return false;
5632         }
5633
5634         ath9k_hw_set_regs(ah, chan, macmode);
5635
5636         if (AR_SREV_9280_10_OR_LATER(ah)) {
5637                 if (!(ath9k_hw_ar9280_set_channel(ah, chan))) {
5638                         DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
5639                                  "%s: failed to set channel\n", __func__);
5640                         return false;
5641                 }
5642         } else {
5643                 if (!(ath9k_hw_set_channel(ah, chan))) {
5644                         DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
5645                                  "%s: failed to set channel\n", __func__);
5646                         return false;
5647                 }
5648         }
5649
5650         if (ath9k_hw_set_txpower(ah, &ahp->ah_eeprom, chan,
5651                                  ath9k_regd_get_ctl(ah, chan),
5652                                  ath9k_regd_get_antenna_allowed(ah, chan),
5653                                  chan->maxRegTxPower * 2,
5654                                  min((u32) MAX_RATE_POWER,
5655                                      (u32) ah->ah_powerLimit)) != 0) {
5656                 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
5657                          "%s: error init'ing transmit power\n", __func__);
5658                 return false;
5659         }
5660
5661         synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
5662         if (IS_CHAN_CCK(chan))
5663                 synthDelay = (4 * synthDelay) / 22;
5664         else
5665                 synthDelay /= 10;
5666
5667         udelay(synthDelay + BASE_ACTIVATE_DELAY);
5668
5669         REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
5670
5671         if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
5672                 ath9k_hw_set_delta_slope(ah, chan);
5673
5674         if (AR_SREV_9280_10_OR_LATER(ah))
5675                 ath9k_hw_9280_spur_mitigate(ah, chan);
5676         else
5677                 ath9k_hw_spur_mitigate(ah, chan);
5678
5679         if (!chan->oneTimeCalsDone)
5680                 chan->oneTimeCalsDone = true;
5681
5682         return true;
5683 }
5684
5685 static bool ath9k_hw_chip_reset(struct ath_hal *ah,
5686                                 struct ath9k_channel *chan)
5687 {
5688         struct ath_hal_5416 *ahp = AH5416(ah);
5689
5690         if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
5691                 return false;
5692
5693         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
5694                 return false;
5695
5696         ahp->ah_chipFullSleep = false;
5697
5698         ath9k_hw_init_pll(ah, chan);
5699
5700         ath9k_hw_set_rfmode(ah, chan);
5701
5702         return true;
5703 }
5704
5705 static inline void ath9k_hw_set_dma(struct ath_hal *ah)
5706 {
5707         u32 regval;
5708
5709         regval = REG_READ(ah, AR_AHB_MODE);
5710         REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN);
5711
5712         regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK;
5713         REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B);
5714
5715         REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->ah_txTrigLevel);
5716
5717         regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK;
5718         REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B);
5719
5720         REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
5721
5722         if (AR_SREV_9285(ah)) {
5723                 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
5724                           AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
5725         } else {
5726                 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
5727                           AR_PCU_TXBUF_CTRL_USABLE_SIZE);
5728         }
5729 }
5730
5731 bool ath9k_hw_stopdmarecv(struct ath_hal *ah)
5732 {
5733         REG_WRITE(ah, AR_CR, AR_CR_RXD);
5734         if (!ath9k_hw_wait(ah, AR_CR, AR_CR_RXE, 0)) {
5735                 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE,
5736                         "%s: dma failed to stop in 10ms\n"
5737                         "AR_CR=0x%08x\nAR_DIAG_SW=0x%08x\n",
5738                         __func__,
5739                         REG_READ(ah, AR_CR), REG_READ(ah, AR_DIAG_SW));
5740                 return false;
5741         } else {
5742                 return true;
5743         }
5744 }
5745
5746 void ath9k_hw_startpcureceive(struct ath_hal *ah)
5747 {
5748         REG_CLR_BIT(ah, AR_DIAG_SW,
5749                     (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
5750
5751         ath9k_enable_mib_counters(ah);
5752
5753         ath9k_ani_reset(ah);
5754 }
5755
5756 void ath9k_hw_stoppcurecv(struct ath_hal *ah)
5757 {
5758         REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_DIS);
5759
5760         ath9k_hw_disable_mib_counters(ah);
5761 }
5762
5763 static bool ath9k_hw_iscal_supported(struct ath_hal *ah,
5764                                      struct ath9k_channel *chan,
5765                                      enum hal_cal_types calType)
5766 {
5767         struct ath_hal_5416 *ahp = AH5416(ah);
5768         bool retval = false;
5769
5770         switch (calType & ahp->ah_suppCals) {
5771         case IQ_MISMATCH_CAL:
5772                 if (!IS_CHAN_B(chan))
5773                         retval = true;
5774                 break;
5775         case ADC_GAIN_CAL:
5776         case ADC_DC_CAL:
5777                 if (!IS_CHAN_B(chan)
5778                     && !(IS_CHAN_2GHZ(chan) && IS_CHAN_HT20(chan)))
5779                         retval = true;
5780                 break;
5781         }
5782
5783         return retval;
5784 }
5785
5786 static bool ath9k_hw_init_cal(struct ath_hal *ah,
5787                               struct ath9k_channel *chan)
5788 {
5789         struct ath_hal_5416 *ahp = AH5416(ah);
5790         struct ath9k_channel *ichan =
5791                 ath9k_regd_check_channel(ah, chan);
5792
5793         REG_WRITE(ah, AR_PHY_AGC_CONTROL,
5794                   REG_READ(ah, AR_PHY_AGC_CONTROL) |
5795                   AR_PHY_AGC_CONTROL_CAL);
5796
5797         if (!ath9k_hw_wait
5798             (ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL, 0)) {
5799                 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
5800                          "%s: offset calibration failed to complete in 1ms; "
5801                          "noisy environment?\n", __func__);
5802                 return false;
5803         }
5804
5805         REG_WRITE(ah, AR_PHY_AGC_CONTROL,
5806                   REG_READ(ah, AR_PHY_AGC_CONTROL) |
5807                   AR_PHY_AGC_CONTROL_NF);
5808
5809         ahp->ah_cal_list = ahp->ah_cal_list_last = ahp->ah_cal_list_curr =
5810                 NULL;
5811
5812         if (AR_SREV_9100(ah) || AR_SREV_9160_10_OR_LATER(ah)) {
5813                 if (ath9k_hw_iscal_supported(ah, chan, ADC_GAIN_CAL)) {
5814                         INIT_CAL(&ahp->ah_adcGainCalData);
5815                         INSERT_CAL(ahp, &ahp->ah_adcGainCalData);
5816                         DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
5817                                  "%s: enabling ADC Gain Calibration.\n",
5818                                  __func__);
5819                 }
5820                 if (ath9k_hw_iscal_supported(ah, chan, ADC_DC_CAL)) {
5821                         INIT_CAL(&ahp->ah_adcDcCalData);
5822                         INSERT_CAL(ahp, &ahp->ah_adcDcCalData);
5823                         DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
5824                                  "%s: enabling ADC DC Calibration.\n",
5825                                  __func__);
5826                 }
5827                 if (ath9k_hw_iscal_supported(ah, chan, IQ_MISMATCH_CAL)) {
5828                         INIT_CAL(&ahp->ah_iqCalData);
5829                         INSERT_CAL(ahp, &ahp->ah_iqCalData);
5830                         DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
5831                                  "%s: enabling IQ Calibration.\n",
5832                                  __func__);
5833                 }
5834
5835                 ahp->ah_cal_list_curr = ahp->ah_cal_list;
5836
5837                 if (ahp->ah_cal_list_curr)
5838                         ath9k_hw_reset_calibration(ah,
5839                                                    ahp->ah_cal_list_curr);
5840         }
5841
5842         ichan->CalValid = 0;
5843
5844         return true;
5845 }
5846
5847
5848 bool ath9k_hw_reset(struct ath_hal *ah,
5849                     struct ath9k_channel *chan,
5850                     enum ath9k_ht_macmode macmode,
5851                     u8 txchainmask, u8 rxchainmask,
5852                     enum ath9k_ht_extprotspacing extprotspacing,
5853                     bool bChannelChange,
5854                     int *status)
5855 {
5856 #define FAIL(_code)     do { ecode = _code; goto bad; } while (0)
5857         u32 saveLedState;
5858         struct ath_hal_5416 *ahp = AH5416(ah);
5859         struct ath9k_channel *curchan = ah->ah_curchan;
5860         u32 saveDefAntenna;
5861         u32 macStaId1;
5862         int ecode;
5863         int i, rx_chainmask;
5864
5865         ahp->ah_extprotspacing = extprotspacing;
5866         ahp->ah_txchainmask = txchainmask;
5867         ahp->ah_rxchainmask = rxchainmask;
5868
5869         if (AR_SREV_9280(ah)) {
5870                 ahp->ah_txchainmask &= 0x3;
5871                 ahp->ah_rxchainmask &= 0x3;
5872         }
5873
5874         if (ath9k_hw_check_chan(ah, chan) == NULL) {
5875                 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
5876                          "%s: invalid channel %u/0x%x; no mapping\n",
5877                          __func__, chan->channel, chan->channelFlags);
5878                 FAIL(-EINVAL);
5879         }
5880
5881         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
5882                 return false;
5883
5884         if (curchan)
5885                 ath9k_hw_getnf(ah, curchan);
5886
5887         if (bChannelChange &&
5888             (ahp->ah_chipFullSleep != true) &&
5889             (ah->ah_curchan != NULL) &&
5890             (chan->channel != ah->ah_curchan->channel) &&
5891             ((chan->channelFlags & CHANNEL_ALL) ==
5892              (ah->ah_curchan->channelFlags & CHANNEL_ALL)) &&
5893             (!AR_SREV_9280(ah) || (!IS_CHAN_A_5MHZ_SPACED(chan) &&
5894                                    !IS_CHAN_A_5MHZ_SPACED(ah->
5895                                                           ah_curchan)))) {
5896
5897                 if (ath9k_hw_channel_change(ah, chan, macmode)) {
5898                         ath9k_hw_loadnf(ah, ah->ah_curchan);
5899                         ath9k_hw_start_nfcal(ah);
5900                         return true;
5901                 }
5902         }
5903
5904         saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
5905         if (saveDefAntenna == 0)
5906                 saveDefAntenna = 1;
5907
5908         macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
5909
5910         saveLedState = REG_READ(ah, AR_CFG_LED) &
5911                 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
5912                  AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
5913
5914         ath9k_hw_mark_phy_inactive(ah);
5915
5916         if (!ath9k_hw_chip_reset(ah, chan)) {
5917                 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "%s: chip reset failed\n",
5918                          __func__);
5919                 FAIL(-EIO);
5920         }
5921
5922         if (AR_SREV_9280(ah)) {
5923                 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
5924                             AR_GPIO_JTAG_DISABLE);
5925
5926                 if (test_bit(ATH9K_MODE_11A, ah->ah_caps.wireless_modes)) {
5927                         if (IS_CHAN_5GHZ(chan))
5928                                 ath9k_hw_set_gpio(ah, 9, 0);
5929                         else
5930                                 ath9k_hw_set_gpio(ah, 9, 1);
5931                 }
5932                 ath9k_hw_cfg_output(ah, 9, AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
5933         }
5934
5935         ecode = ath9k_hw_process_ini(ah, chan, macmode);
5936         if (ecode != 0)
5937                 goto bad;
5938
5939         if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
5940                 ath9k_hw_set_delta_slope(ah, chan);
5941
5942         if (AR_SREV_9280_10_OR_LATER(ah))
5943                 ath9k_hw_9280_spur_mitigate(ah, chan);
5944         else
5945                 ath9k_hw_spur_mitigate(ah, chan);
5946
5947         if (!ath9k_hw_eeprom_set_board_values(ah, chan)) {
5948                 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
5949                          "%s: error setting board options\n", __func__);
5950                 FAIL(-EIO);
5951         }
5952
5953         ath9k_hw_decrease_chain_power(ah, chan);
5954
5955         REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(ahp->ah_macaddr));
5956         REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(ahp->ah_macaddr + 4)
5957                   | macStaId1
5958                   | AR_STA_ID1_RTS_USE_DEF
5959                   | (ah->ah_config.
5960                      ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
5961                   | ahp->ah_staId1Defaults);
5962         ath9k_hw_set_operating_mode(ah, ah->ah_opmode);
5963
5964         REG_WRITE(ah, AR_BSSMSKL, get_unaligned_le32(ahp->ah_bssidmask));
5965         REG_WRITE(ah, AR_BSSMSKU, get_unaligned_le16(ahp->ah_bssidmask + 4));
5966
5967         REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
5968
5969         REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(ahp->ah_bssid));
5970         REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(ahp->ah_bssid + 4) |
5971                   ((ahp->ah_assocId & 0x3fff) << AR_BSS_ID1_AID_S));
5972
5973         REG_WRITE(ah, AR_ISR, ~0);
5974
5975         REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
5976
5977         if (AR_SREV_9280_10_OR_LATER(ah)) {
5978                 if (!(ath9k_hw_ar9280_set_channel(ah, chan)))
5979                         FAIL(-EIO);
5980         } else {
5981                 if (!(ath9k_hw_set_channel(ah, chan)))
5982                         FAIL(-EIO);
5983         }
5984
5985         for (i = 0; i < AR_NUM_DCU; i++)
5986                 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
5987
5988         ahp->ah_intrTxqs = 0;
5989         for (i = 0; i < ah->ah_caps.total_queues; i++)
5990                 ath9k_hw_resettxqueue(ah, i);
5991
5992         ath9k_hw_init_interrupt_masks(ah, ah->ah_opmode);
5993         ath9k_hw_init_qos(ah);
5994
5995 #ifdef CONFIG_RFKILL
5996         if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
5997                 ath9k_enable_rfkill(ah);
5998 #endif
5999         ath9k_hw_init_user_settings(ah);
6000
6001         REG_WRITE(ah, AR_STA_ID1,
6002                   REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM);
6003
6004         ath9k_hw_set_dma(ah);
6005
6006         REG_WRITE(ah, AR_OBS, 8);
6007
6008         if (ahp->ah_intrMitigation) {
6009
6010                 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
6011                 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
6012         }
6013
6014         ath9k_hw_init_bb(ah, chan);
6015
6016         if (!ath9k_hw_init_cal(ah, chan))
6017                 FAIL(-ENODEV);
6018
6019         rx_chainmask = ahp->ah_rxchainmask;
6020         if ((rx_chainmask == 0x5) || (rx_chainmask == 0x3)) {
6021                 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
6022                 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
6023         }
6024
6025         REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
6026
6027         if (AR_SREV_9100(ah)) {
6028                 u32 mask;
6029                 mask = REG_READ(ah, AR_CFG);
6030                 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
6031                         DPRINTF(ah->ah_sc, ATH_DBG_RESET,
6032                                  "%s CFG Byte Swap Set 0x%x\n", __func__,
6033                                  mask);
6034                 } else {
6035                         mask =
6036                                 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
6037                         REG_WRITE(ah, AR_CFG, mask);
6038                         DPRINTF(ah->ah_sc, ATH_DBG_RESET,
6039                                  "%s Setting CFG 0x%x\n", __func__,
6040                                  REG_READ(ah, AR_CFG));
6041                 }
6042         } else {
6043 #ifdef __BIG_ENDIAN
6044                 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
6045 #endif
6046         }
6047
6048         return true;
6049 bad:
6050         if (status)
6051                 *status = ecode;
6052         return false;
6053 #undef FAIL
6054 }
6055
6056 bool ath9k_hw_phy_disable(struct ath_hal *ah)
6057 {
6058         return ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM);
6059 }
6060
6061 bool ath9k_hw_disable(struct ath_hal *ah)
6062 {
6063         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
6064                 return false;
6065
6066         return ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD);
6067 }
6068
6069 bool
6070 ath9k_hw_calibrate(struct ath_hal *ah, struct ath9k_channel *chan,
6071                    u8 rxchainmask, bool longcal,
6072                    bool *isCalDone)
6073 {
6074         struct ath_hal_5416 *ahp = AH5416(ah);
6075         struct hal_cal_list *currCal = ahp->ah_cal_list_curr;
6076         struct ath9k_channel *ichan =
6077                 ath9k_regd_check_channel(ah, chan);
6078
6079         *isCalDone = true;
6080
6081         if (ichan == NULL) {
6082                 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
6083                          "%s: invalid channel %u/0x%x; no mapping\n",
6084                          __func__, chan->channel, chan->channelFlags);
6085                 return false;
6086         }
6087
6088         if (currCal &&
6089             (currCal->calState == CAL_RUNNING ||
6090              currCal->calState == CAL_WAITING)) {
6091                 ath9k_hw_per_calibration(ah, ichan, rxchainmask, currCal,
6092                                          isCalDone);
6093                 if (*isCalDone) {
6094                         ahp->ah_cal_list_curr = currCal = currCal->calNext;
6095
6096                         if (currCal->calState == CAL_WAITING) {
6097                                 *isCalDone = false;
6098                                 ath9k_hw_reset_calibration(ah, currCal);
6099                         }
6100                 }
6101         }
6102
6103         if (longcal) {
6104                 ath9k_hw_getnf(ah, ichan);
6105                 ath9k_hw_loadnf(ah, ah->ah_curchan);
6106                 ath9k_hw_start_nfcal(ah);
6107
6108                 if ((ichan->channelFlags & CHANNEL_CW_INT) != 0) {
6109
6110                         chan->channelFlags |= CHANNEL_CW_INT;
6111                         ichan->channelFlags &= ~CHANNEL_CW_INT;
6112                 }
6113         }
6114
6115         return true;
6116 }
6117
6118 static void ath9k_hw_iqcal_collect(struct ath_hal *ah)
6119 {
6120         struct ath_hal_5416 *ahp = AH5416(ah);
6121         int i;
6122
6123         for (i = 0; i < AR5416_MAX_CHAINS; i++) {
6124                 ahp->ah_totalPowerMeasI[i] +=
6125                         REG_READ(ah, AR_PHY_CAL_MEAS_0(i));
6126                 ahp->ah_totalPowerMeasQ[i] +=
6127                         REG_READ(ah, AR_PHY_CAL_MEAS_1(i));
6128                 ahp->ah_totalIqCorrMeas[i] +=
6129                         (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i));
6130                 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6131                          "%d: Chn %d pmi=0x%08x;pmq=0x%08x;iqcm=0x%08x;\n",
6132                          ahp->ah_CalSamples, i, ahp->ah_totalPowerMeasI[i],
6133                          ahp->ah_totalPowerMeasQ[i],
6134                          ahp->ah_totalIqCorrMeas[i]);
6135         }
6136 }
6137
6138 static void ath9k_hw_adc_gaincal_collect(struct ath_hal *ah)
6139 {
6140         struct ath_hal_5416 *ahp = AH5416(ah);
6141         int i;
6142
6143         for (i = 0; i < AR5416_MAX_CHAINS; i++) {
6144                 ahp->ah_totalAdcIOddPhase[i] +=
6145                         REG_READ(ah, AR_PHY_CAL_MEAS_0(i));
6146                 ahp->ah_totalAdcIEvenPhase[i] +=
6147                         REG_READ(ah, AR_PHY_CAL_MEAS_1(i));
6148                 ahp->ah_totalAdcQOddPhase[i] +=
6149                         REG_READ(ah, AR_PHY_CAL_MEAS_2(i));
6150                 ahp->ah_totalAdcQEvenPhase[i] +=
6151                         REG_READ(ah, AR_PHY_CAL_MEAS_3(i));
6152
6153                 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6154                         "%d: Chn %d oddi=0x%08x; eveni=0x%08x; "
6155                         "oddq=0x%08x; evenq=0x%08x;\n",
6156                          ahp->ah_CalSamples, i,
6157                          ahp->ah_totalAdcIOddPhase[i],
6158                          ahp->ah_totalAdcIEvenPhase[i],
6159                          ahp->ah_totalAdcQOddPhase[i],
6160                          ahp->ah_totalAdcQEvenPhase[i]);
6161         }
6162 }
6163
6164 static void ath9k_hw_adc_dccal_collect(struct ath_hal *ah)
6165 {
6166         struct ath_hal_5416 *ahp = AH5416(ah);
6167         int i;
6168
6169         for (i = 0; i < AR5416_MAX_CHAINS; i++) {
6170                 ahp->ah_totalAdcDcOffsetIOddPhase[i] +=
6171                         (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_0(i));
6172                 ahp->ah_totalAdcDcOffsetIEvenPhase[i] +=
6173                         (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_1(i));
6174                 ahp->ah_totalAdcDcOffsetQOddPhase[i] +=
6175                         (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i));
6176                 ahp->ah_totalAdcDcOffsetQEvenPhase[i] +=
6177                         (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_3(i));
6178
6179                 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6180                         "%d: Chn %d oddi=0x%08x; eveni=0x%08x; "
6181                         "oddq=0x%08x; evenq=0x%08x;\n",
6182                          ahp->ah_CalSamples, i,
6183                          ahp->ah_totalAdcDcOffsetIOddPhase[i],
6184                          ahp->ah_totalAdcDcOffsetIEvenPhase[i],
6185                          ahp->ah_totalAdcDcOffsetQOddPhase[i],
6186                          ahp->ah_totalAdcDcOffsetQEvenPhase[i]);
6187         }
6188 }
6189
6190 static void ath9k_hw_iqcalibrate(struct ath_hal *ah, u8 numChains)
6191 {
6192         struct ath_hal_5416 *ahp = AH5416(ah);
6193         u32 powerMeasQ, powerMeasI, iqCorrMeas;
6194         u32 qCoffDenom, iCoffDenom;
6195         int32_t qCoff, iCoff;
6196         int iqCorrNeg, i;
6197
6198         for (i = 0; i < numChains; i++) {
6199                 powerMeasI = ahp->ah_totalPowerMeasI[i];
6200                 powerMeasQ = ahp->ah_totalPowerMeasQ[i];
6201                 iqCorrMeas = ahp->ah_totalIqCorrMeas[i];
6202
6203                 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6204                          "Starting IQ Cal and Correction for Chain %d\n",
6205                          i);
6206
6207                 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6208                          "Orignal: Chn %diq_corr_meas = 0x%08x\n",
6209                          i, ahp->ah_totalIqCorrMeas[i]);
6210
6211                 iqCorrNeg = 0;
6212
6213
6214                 if (iqCorrMeas > 0x80000000) {
6215                         iqCorrMeas = (0xffffffff - iqCorrMeas) + 1;
6216                         iqCorrNeg = 1;
6217                 }
6218
6219                 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6220                          "Chn %d pwr_meas_i = 0x%08x\n", i, powerMeasI);
6221                 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6222                          "Chn %d pwr_meas_q = 0x%08x\n", i, powerMeasQ);
6223                 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, "iqCorrNeg is 0x%08x\n",
6224                          iqCorrNeg);
6225
6226                 iCoffDenom = (powerMeasI / 2 + powerMeasQ / 2) / 128;
6227                 qCoffDenom = powerMeasQ / 64;
6228
6229                 if (powerMeasQ != 0) {
6230
6231                         iCoff = iqCorrMeas / iCoffDenom;
6232                         qCoff = powerMeasI / qCoffDenom - 64;
6233                         DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6234                                  "Chn %d iCoff = 0x%08x\n", i, iCoff);
6235                         DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6236                                  "Chn %d qCoff = 0x%08x\n", i, qCoff);
6237
6238
6239                         iCoff = iCoff & 0x3f;
6240                         DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6241                                  "New: Chn %d iCoff = 0x%08x\n", i, iCoff);
6242                         if (iqCorrNeg == 0x0)
6243                                 iCoff = 0x40 - iCoff;
6244
6245                         if (qCoff > 15)
6246                                 qCoff = 15;
6247                         else if (qCoff <= -16)
6248                                 qCoff = 16;
6249
6250                         DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6251                                  "Chn %d : iCoff = 0x%x  qCoff = 0x%x\n",
6252                                 i, iCoff, qCoff);
6253
6254                         REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(i),
6255                                       AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF,
6256                                       iCoff);
6257                         REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(i),
6258                                       AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF,
6259                                       qCoff);
6260                         DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6261                                 "IQ Cal and Correction done for Chain %d\n",
6262                                 i);
6263                 }
6264         }
6265
6266         REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4(0),
6267                     AR_PHY_TIMING_CTRL4_IQCORR_ENABLE);
6268 }
6269
6270 static void
6271 ath9k_hw_adc_gaincal_calibrate(struct ath_hal *ah, u8 numChains)
6272 {
6273         struct ath_hal_5416 *ahp = AH5416(ah);
6274         u32 iOddMeasOffset, iEvenMeasOffset, qOddMeasOffset,
6275                 qEvenMeasOffset;
6276         u32 qGainMismatch, iGainMismatch, val, i;
6277
6278         for (i = 0; i < numChains; i++) {
6279                 iOddMeasOffset = ahp->ah_totalAdcIOddPhase[i];
6280                 iEvenMeasOffset = ahp->ah_totalAdcIEvenPhase[i];
6281                 qOddMeasOffset = ahp->ah_totalAdcQOddPhase[i];
6282                 qEvenMeasOffset = ahp->ah_totalAdcQEvenPhase[i];
6283
6284                 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6285                          "Starting ADC Gain Cal for Chain %d\n", i);
6286
6287                 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6288                          "Chn %d pwr_meas_odd_i = 0x%08x\n", i,
6289                          iOddMeasOffset);
6290                 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6291                          "Chn %d pwr_meas_even_i = 0x%08x\n", i,
6292                          iEvenMeasOffset);
6293                 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6294                          "Chn %d pwr_meas_odd_q = 0x%08x\n", i,
6295                          qOddMeasOffset);
6296                 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6297                          "Chn %d pwr_meas_even_q = 0x%08x\n", i,
6298                          qEvenMeasOffset);
6299
6300                 if (iOddMeasOffset != 0 && qEvenMeasOffset != 0) {
6301                         iGainMismatch =
6302                                 ((iEvenMeasOffset * 32) /
6303                                  iOddMeasOffset) & 0x3f;
6304                         qGainMismatch =
6305                                 ((qOddMeasOffset * 32) /
6306                                  qEvenMeasOffset) & 0x3f;
6307
6308                         DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6309                                  "Chn %d gain_mismatch_i = 0x%08x\n", i,
6310                                  iGainMismatch);
6311                         DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6312                                  "Chn %d gain_mismatch_q = 0x%08x\n", i,
6313                                  qGainMismatch);
6314
6315                         val = REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i));
6316                         val &= 0xfffff000;
6317                         val |= (qGainMismatch) | (iGainMismatch << 6);
6318                         REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), val);
6319
6320                         DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6321                                  "ADC Gain Cal done for Chain %d\n", i);
6322                 }
6323         }
6324
6325         REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0),
6326                   REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0)) |
6327                   AR_PHY_NEW_ADC_GAIN_CORR_ENABLE);
6328 }
6329
6330 static void
6331 ath9k_hw_adc_dccal_calibrate(struct ath_hal *ah, u8 numChains)
6332 {
6333         struct ath_hal_5416 *ahp = AH5416(ah);
6334         u32 iOddMeasOffset, iEvenMeasOffset, val, i;
6335         int32_t qOddMeasOffset, qEvenMeasOffset, qDcMismatch, iDcMismatch;
6336         const struct hal_percal_data *calData =
6337                 ahp->ah_cal_list_curr->calData;
6338         u32 numSamples =
6339                 (1 << (calData->calCountMax + 5)) * calData->calNumSamples;
6340
6341         for (i = 0; i < numChains; i++) {
6342                 iOddMeasOffset = ahp->ah_totalAdcDcOffsetIOddPhase[i];
6343                 iEvenMeasOffset = ahp->ah_totalAdcDcOffsetIEvenPhase[i];
6344                 qOddMeasOffset = ahp->ah_totalAdcDcOffsetQOddPhase[i];
6345                 qEvenMeasOffset = ahp->ah_totalAdcDcOffsetQEvenPhase[i];
6346
6347                 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6348                          "Starting ADC DC Offset Cal for Chain %d\n", i);
6349
6350                 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6351                          "Chn %d pwr_meas_odd_i = %d\n", i,
6352                          iOddMeasOffset);
6353                 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6354                          "Chn %d pwr_meas_even_i = %d\n", i,
6355                          iEvenMeasOffset);
6356                 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6357                          "Chn %d pwr_meas_odd_q = %d\n", i,
6358                          qOddMeasOffset);
6359                 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6360                          "Chn %d pwr_meas_even_q = %d\n", i,
6361                          qEvenMeasOffset);
6362
6363                 iDcMismatch = (((iEvenMeasOffset - iOddMeasOffset) * 2) /
6364                                numSamples) & 0x1ff;
6365                 qDcMismatch = (((qOddMeasOffset - qEvenMeasOffset) * 2) /
6366                                numSamples) & 0x1ff;
6367
6368                 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6369                          "Chn %d dc_offset_mismatch_i = 0x%08x\n", i,
6370                          iDcMismatch);
6371                 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6372                          "Chn %d dc_offset_mismatch_q = 0x%08x\n", i,
6373                          qDcMismatch);
6374
6375                 val = REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i));
6376                 val &= 0xc0000fff;
6377                 val |= (qDcMismatch << 12) | (iDcMismatch << 21);
6378                 REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), val);
6379
6380                 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6381                          "ADC DC Offset Cal done for Chain %d\n", i);
6382         }
6383
6384         REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0),
6385                   REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0)) |
6386                   AR_PHY_NEW_ADC_DC_OFFSET_CORR_ENABLE);
6387 }
6388
6389 bool ath9k_hw_set_txpowerlimit(struct ath_hal *ah, u32 limit)
6390 {
6391         struct ath_hal_5416 *ahp = AH5416(ah);
6392         struct ath9k_channel *chan = ah->ah_curchan;
6393
6394         ah->ah_powerLimit = min(limit, (u32) MAX_RATE_POWER);
6395
6396         if (ath9k_hw_set_txpower(ah, &ahp->ah_eeprom, chan,
6397                                  ath9k_regd_get_ctl(ah, chan),
6398                                  ath9k_regd_get_antenna_allowed(ah,
6399                                                                 chan),
6400                                  chan->maxRegTxPower * 2,
6401                                  min((u32) MAX_RATE_POWER,
6402                                      (u32) ah->ah_powerLimit)) != 0)
6403                 return false;
6404
6405         return true;
6406 }
6407
6408 void
6409 ath9k_hw_get_channel_centers(struct ath_hal *ah,
6410                              struct ath9k_channel *chan,
6411                              struct chan_centers *centers)
6412 {
6413         int8_t extoff;
6414         struct ath_hal_5416 *ahp = AH5416(ah);
6415
6416         if (!IS_CHAN_HT40(chan)) {
6417                 centers->ctl_center = centers->ext_center =
6418                         centers->synth_center = chan->channel;
6419                 return;
6420         }
6421
6422         if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
6423             (chan->chanmode == CHANNEL_G_HT40PLUS)) {
6424                 centers->synth_center =
6425                         chan->channel + HT40_CHANNEL_CENTER_SHIFT;
6426                 extoff = 1;
6427         } else {
6428                 centers->synth_center =
6429                         chan->channel - HT40_CHANNEL_CENTER_SHIFT;
6430                 extoff = -1;
6431         }
6432
6433         centers->ctl_center = centers->synth_center - (extoff *
6434                 HT40_CHANNEL_CENTER_SHIFT);
6435         centers->ext_center = centers->synth_center + (extoff *
6436                 ((ahp->
6437                 ah_extprotspacing
6438                 ==
6439                 ATH9K_HT_EXTPROTSPACING_20)
6440                 ?
6441                 HT40_CHANNEL_CENTER_SHIFT
6442                 : 15));
6443
6444 }
6445
6446 void
6447 ath9k_hw_reset_calvalid(struct ath_hal *ah, struct ath9k_channel *chan,
6448                         bool *isCalDone)
6449 {
6450         struct ath_hal_5416 *ahp = AH5416(ah);
6451         struct ath9k_channel *ichan =
6452                 ath9k_regd_check_channel(ah, chan);
6453         struct hal_cal_list *currCal = ahp->ah_cal_list_curr;
6454
6455         *isCalDone = true;
6456
6457         if (!AR_SREV_9100(ah) && !AR_SREV_9160_10_OR_LATER(ah))
6458                 return;
6459
6460         if (currCal == NULL)
6461                 return;
6462
6463         if (ichan == NULL) {
6464                 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6465                          "%s: invalid channel %u/0x%x; no mapping\n",
6466                          __func__, chan->channel, chan->channelFlags);
6467                 return;
6468         }
6469
6470
6471         if (currCal->calState != CAL_DONE) {
6472                 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6473                          "%s: Calibration state incorrect, %d\n",
6474                          __func__, currCal->calState);
6475                 return;
6476         }
6477
6478
6479         if (!ath9k_hw_iscal_supported(ah, chan, currCal->calData->calType))
6480                 return;
6481
6482         DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6483                  "%s: Resetting Cal %d state for channel %u/0x%x\n",
6484                  __func__, currCal->calData->calType, chan->channel,
6485                  chan->channelFlags);
6486
6487         ichan->CalValid &= ~currCal->calData->calType;
6488         currCal->calState = CAL_WAITING;
6489
6490         *isCalDone = false;
6491 }
6492
6493 void ath9k_hw_getmac(struct ath_hal *ah, u8 *mac)
6494 {
6495         struct ath_hal_5416 *ahp = AH5416(ah);
6496
6497         memcpy(mac, ahp->ah_macaddr, ETH_ALEN);
6498 }
6499
6500 bool ath9k_hw_setmac(struct ath_hal *ah, const u8 *mac)
6501 {
6502         struct ath_hal_5416 *ahp = AH5416(ah);
6503
6504         memcpy(ahp->ah_macaddr, mac, ETH_ALEN);
6505         return true;
6506 }
6507
6508 void ath9k_hw_getbssidmask(struct ath_hal *ah, u8 *mask)
6509 {
6510         struct ath_hal_5416 *ahp = AH5416(ah);
6511
6512         memcpy(mask, ahp->ah_bssidmask, ETH_ALEN);
6513 }
6514
6515 bool
6516 ath9k_hw_setbssidmask(struct ath_hal *ah, const u8 *mask)
6517 {
6518         struct ath_hal_5416 *ahp = AH5416(ah);
6519
6520         memcpy(ahp->ah_bssidmask, mask, ETH_ALEN);
6521
6522         REG_WRITE(ah, AR_BSSMSKL, get_unaligned_le32(ahp->ah_bssidmask));
6523         REG_WRITE(ah, AR_BSSMSKU, get_unaligned_le16(ahp->ah_bssidmask + 4));
6524
6525         return true;
6526 }
6527
6528 void
6529 ath9k_hw_write_associd(struct ath_hal *ah, const u8 *bssid,
6530                        u16 assocId)
6531 {
6532         struct ath_hal_5416 *ahp = AH5416(ah);
6533
6534         memcpy(ahp->ah_bssid, bssid, ETH_ALEN);
6535         ahp->ah_assocId = assocId;
6536
6537         REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(ahp->ah_bssid));
6538         REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(ahp->ah_bssid + 4) |
6539                   ((assocId & 0x3fff) << AR_BSS_ID1_AID_S));
6540 }
6541
6542 u64 ath9k_hw_gettsf64(struct ath_hal *ah)
6543 {
6544         u64 tsf;
6545
6546         tsf = REG_READ(ah, AR_TSF_U32);
6547         tsf = (tsf << 32) | REG_READ(ah, AR_TSF_L32);
6548         return tsf;
6549 }
6550
6551 void ath9k_hw_reset_tsf(struct ath_hal *ah)
6552 {
6553         int count;
6554
6555         count = 0;
6556         while (REG_READ(ah, AR_SLP32_MODE) & AR_SLP32_TSF_WRITE_STATUS) {
6557                 count++;
6558                 if (count > 10) {
6559                         DPRINTF(ah->ah_sc, ATH_DBG_RESET,
6560                          "%s: AR_SLP32_TSF_WRITE_STATUS limit exceeded\n",
6561                                  __func__);
6562                         break;
6563                 }
6564                 udelay(10);
6565         }
6566         REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
6567 }
6568
6569 u32 ath9k_hw_getdefantenna(struct ath_hal *ah)
6570 {
6571         return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
6572 }
6573
6574 void ath9k_hw_setantenna(struct ath_hal *ah, u32 antenna)
6575 {
6576         REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
6577 }
6578
6579 bool
6580 ath9k_hw_setantennaswitch(struct ath_hal *ah,
6581                           enum ath9k_ant_setting settings,
6582                           struct ath9k_channel *chan,
6583                           u8 *tx_chainmask,
6584                           u8 *rx_chainmask,
6585                           u8 *antenna_cfgd)
6586 {
6587         struct ath_hal_5416 *ahp = AH5416(ah);
6588         static u8 tx_chainmask_cfg, rx_chainmask_cfg;
6589
6590         if (AR_SREV_9280(ah)) {
6591                 if (!tx_chainmask_cfg) {
6592
6593                         tx_chainmask_cfg = *tx_chainmask;
6594                         rx_chainmask_cfg = *rx_chainmask;
6595                 }
6596
6597                 switch (settings) {
6598                 case ATH9K_ANT_FIXED_A:
6599                         *tx_chainmask = ATH9K_ANTENNA0_CHAINMASK;
6600                         *rx_chainmask = ATH9K_ANTENNA0_CHAINMASK;
6601                         *antenna_cfgd = true;
6602                         break;
6603                 case ATH9K_ANT_FIXED_B:
6604                         if (ah->ah_caps.tx_chainmask >
6605                             ATH9K_ANTENNA1_CHAINMASK) {
6606                                 *tx_chainmask = ATH9K_ANTENNA1_CHAINMASK;
6607                         }
6608                         *rx_chainmask = ATH9K_ANTENNA1_CHAINMASK;
6609                         *antenna_cfgd = true;
6610                         break;
6611                 case ATH9K_ANT_VARIABLE:
6612                         *tx_chainmask = tx_chainmask_cfg;
6613                         *rx_chainmask = rx_chainmask_cfg;
6614                         *antenna_cfgd = true;
6615                         break;
6616                 default:
6617                         break;
6618                 }
6619         } else {
6620                 ahp->ah_diversityControl = settings;
6621         }
6622
6623         return true;
6624 }
6625
6626 void ath9k_hw_setopmode(struct ath_hal *ah)
6627 {
6628         ath9k_hw_set_operating_mode(ah, ah->ah_opmode);
6629 }
6630
6631 bool
6632 ath9k_hw_getcapability(struct ath_hal *ah, enum ath9k_capability_type type,
6633                        u32 capability, u32 *result)
6634 {
6635         struct ath_hal_5416 *ahp = AH5416(ah);
6636         const struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
6637
6638         switch (type) {
6639         case ATH9K_CAP_CIPHER:
6640                 switch (capability) {
6641                 case ATH9K_CIPHER_AES_CCM:
6642                 case ATH9K_CIPHER_AES_OCB:
6643                 case ATH9K_CIPHER_TKIP:
6644                 case ATH9K_CIPHER_WEP:
6645                 case ATH9K_CIPHER_MIC:
6646                 case ATH9K_CIPHER_CLR:
6647                         return true;
6648                 default:
6649                         return false;
6650                 }
6651         case ATH9K_CAP_TKIP_MIC:
6652                 switch (capability) {
6653                 case 0:
6654                         return true;
6655                 case 1:
6656                         return (ahp->ah_staId1Defaults &
6657                                 AR_STA_ID1_CRPT_MIC_ENABLE) ? true :
6658                         false;
6659                 }
6660         case ATH9K_CAP_TKIP_SPLIT:
6661                 return (ahp->ah_miscMode & AR_PCU_MIC_NEW_LOC_ENA) ?
6662                         false : true;
6663         case ATH9K_CAP_WME_TKIPMIC:
6664                 return 0;
6665         case ATH9K_CAP_PHYCOUNTERS:
6666                 return ahp->ah_hasHwPhyCounters ? 0 : -ENXIO;
6667         case ATH9K_CAP_DIVERSITY:
6668                 return (REG_READ(ah, AR_PHY_CCK_DETECT) &
6669                         AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV) ?
6670                         true : false;
6671         case ATH9K_CAP_PHYDIAG:
6672                 return true;
6673         case ATH9K_CAP_MCAST_KEYSRCH:
6674                 switch (capability) {
6675                 case 0:
6676                         return true;
6677                 case 1:
6678                         if (REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_ADHOC) {
6679                                 return false;
6680                         } else {
6681                                 return (ahp->ah_staId1Defaults &
6682                                         AR_STA_ID1_MCAST_KSRCH) ? true :
6683                                         false;
6684                         }
6685                 }
6686                 return false;
6687         case ATH9K_CAP_TSF_ADJUST:
6688                 return (ahp->ah_miscMode & AR_PCU_TX_ADD_TSF) ?
6689                         true : false;
6690         case ATH9K_CAP_RFSILENT:
6691                 if (capability == 3)
6692                         return false;
6693         case ATH9K_CAP_ANT_CFG_2GHZ:
6694                 *result = pCap->num_antcfg_2ghz;
6695                 return true;
6696         case ATH9K_CAP_ANT_CFG_5GHZ:
6697                 *result = pCap->num_antcfg_5ghz;
6698                 return true;
6699         case ATH9K_CAP_TXPOW:
6700                 switch (capability) {
6701                 case 0:
6702                         return 0;
6703                 case 1:
6704                         *result = ah->ah_powerLimit;
6705                         return 0;
6706                 case 2:
6707                         *result = ah->ah_maxPowerLevel;
6708                         return 0;
6709                 case 3:
6710                         *result = ah->ah_tpScale;
6711                         return 0;
6712                 }
6713                 return false;
6714         default:
6715                 return false;
6716         }
6717 }
6718
6719 int
6720 ath9k_hw_select_antconfig(struct ath_hal *ah, u32 cfg)
6721 {
6722         struct ath_hal_5416 *ahp = AH5416(ah);
6723         struct ath9k_channel *chan = ah->ah_curchan;
6724         const struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
6725         u16 ant_config;
6726         u32 halNumAntConfig;
6727
6728         halNumAntConfig =
6729                 IS_CHAN_2GHZ(chan) ? pCap->num_antcfg_2ghz : pCap->
6730                 num_antcfg_5ghz;
6731
6732         if (cfg < halNumAntConfig) {
6733                 if (!ath9k_hw_get_eeprom_antenna_cfg(ahp, chan,
6734                                                      cfg, &ant_config)) {
6735                         REG_WRITE(ah, AR_PHY_SWITCH_COM, ant_config);
6736                         return 0;
6737                 }
6738         }
6739
6740         return -EINVAL;
6741 }
6742
6743 bool ath9k_hw_intrpend(struct ath_hal *ah)
6744 {
6745         u32 host_isr;
6746
6747         if (AR_SREV_9100(ah))
6748                 return true;
6749
6750         host_isr = REG_READ(ah, AR_INTR_ASYNC_CAUSE);
6751         if ((host_isr & AR_INTR_MAC_IRQ) && (host_isr != AR_INTR_SPURIOUS))
6752                 return true;
6753
6754         host_isr = REG_READ(ah, AR_INTR_SYNC_CAUSE);
6755         if ((host_isr & AR_INTR_SYNC_DEFAULT)
6756             && (host_isr != AR_INTR_SPURIOUS))
6757                 return true;
6758
6759         return false;
6760 }
6761
6762 bool ath9k_hw_getisr(struct ath_hal *ah, enum ath9k_int *masked)
6763 {
6764         u32 isr = 0;
6765         u32 mask2 = 0;
6766         struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
6767         u32 sync_cause = 0;
6768         bool fatal_int = false;
6769
6770         if (!AR_SREV_9100(ah)) {
6771                 if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
6772                         if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M)
6773                             == AR_RTC_STATUS_ON) {
6774                                 isr = REG_READ(ah, AR_ISR);
6775                         }
6776                 }
6777
6778                 sync_cause =
6779                         REG_READ(ah,
6780                                  AR_INTR_SYNC_CAUSE) & AR_INTR_SYNC_DEFAULT;
6781
6782                 *masked = 0;
6783
6784                 if (!isr && !sync_cause)
6785                         return false;
6786         } else {
6787                 *masked = 0;
6788                 isr = REG_READ(ah, AR_ISR);
6789         }
6790
6791         if (isr) {
6792                 struct ath_hal_5416 *ahp = AH5416(ah);
6793
6794                 if (isr & AR_ISR_BCNMISC) {
6795                         u32 isr2;
6796                         isr2 = REG_READ(ah, AR_ISR_S2);
6797                         if (isr2 & AR_ISR_S2_TIM)
6798                                 mask2 |= ATH9K_INT_TIM;
6799                         if (isr2 & AR_ISR_S2_DTIM)
6800                                 mask2 |= ATH9K_INT_DTIM;
6801                         if (isr2 & AR_ISR_S2_DTIMSYNC)
6802                                 mask2 |= ATH9K_INT_DTIMSYNC;
6803                         if (isr2 & (AR_ISR_S2_CABEND))
6804                                 mask2 |= ATH9K_INT_CABEND;
6805                         if (isr2 & AR_ISR_S2_GTT)
6806                                 mask2 |= ATH9K_INT_GTT;
6807                         if (isr2 & AR_ISR_S2_CST)
6808                                 mask2 |= ATH9K_INT_CST;
6809                 }
6810
6811                 isr = REG_READ(ah, AR_ISR_RAC);
6812                 if (isr == 0xffffffff) {
6813                         *masked = 0;
6814                         return false;
6815                 }
6816
6817                 *masked = isr & ATH9K_INT_COMMON;
6818
6819                 if (ahp->ah_intrMitigation) {
6820
6821                         if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM))
6822                                 *masked |= ATH9K_INT_RX;
6823                 }
6824
6825                 if (isr & (AR_ISR_RXOK | AR_ISR_RXERR))
6826                         *masked |= ATH9K_INT_RX;
6827                 if (isr &
6828                     (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR |
6829                      AR_ISR_TXEOL)) {
6830                         u32 s0_s, s1_s;
6831
6832                         *masked |= ATH9K_INT_TX;
6833
6834                         s0_s = REG_READ(ah, AR_ISR_S0_S);
6835                         ahp->ah_intrTxqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK);
6836                         ahp->ah_intrTxqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC);
6837
6838                         s1_s = REG_READ(ah, AR_ISR_S1_S);
6839                         ahp->ah_intrTxqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR);
6840                         ahp->ah_intrTxqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL);
6841                 }
6842
6843                 if (isr & AR_ISR_RXORN) {
6844                         DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
6845                                  "%s: receive FIFO overrun interrupt\n",
6846                                  __func__);
6847                 }
6848
6849                 if (!AR_SREV_9100(ah)) {
6850                         if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
6851                                 u32 isr5 = REG_READ(ah, AR_ISR_S5_S);
6852                                 if (isr5 & AR_ISR_S5_TIM_TIMER)
6853                                         *masked |= ATH9K_INT_TIM_TIMER;
6854                         }
6855                 }
6856
6857                 *masked |= mask2;
6858         }
6859         if (AR_SREV_9100(ah))
6860                 return true;
6861         if (sync_cause) {
6862                 fatal_int =
6863                         (sync_cause &
6864                          (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR))
6865                         ? true : false;
6866
6867                 if (fatal_int) {
6868                         if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) {
6869                                 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
6870                                          "%s: received PCI FATAL interrupt\n",
6871                                          __func__);
6872                         }
6873                         if (sync_cause & AR_INTR_SYNC_HOST1_PERR) {
6874                                 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
6875                                          "%s: received PCI PERR interrupt\n",
6876                                          __func__);
6877                         }
6878                 }
6879                 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
6880                         DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
6881                                  "%s: AR_INTR_SYNC_RADM_CPL_TIMEOUT\n",
6882                                  __func__);
6883                         REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
6884                         REG_WRITE(ah, AR_RC, 0);
6885                         *masked |= ATH9K_INT_FATAL;
6886                 }
6887                 if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) {
6888                         DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
6889                                  "%s: AR_INTR_SYNC_LOCAL_TIMEOUT\n",
6890                                  __func__);
6891                 }
6892
6893                 REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
6894                 (void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
6895         }
6896         return true;
6897 }
6898
6899 enum ath9k_int ath9k_hw_intrget(struct ath_hal *ah)
6900 {
6901         return AH5416(ah)->ah_maskReg;
6902 }
6903
6904 enum ath9k_int ath9k_hw_set_interrupts(struct ath_hal *ah, enum ath9k_int ints)
6905 {
6906         struct ath_hal_5416 *ahp = AH5416(ah);
6907         u32 omask = ahp->ah_maskReg;
6908         u32 mask, mask2;
6909         struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
6910
6911         DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "%s: 0x%x => 0x%x\n", __func__,
6912                  omask, ints);
6913
6914         if (omask & ATH9K_INT_GLOBAL) {
6915                 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "%s: disable IER\n",
6916                          __func__);
6917                 REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
6918                 (void) REG_READ(ah, AR_IER);
6919                 if (!AR_SREV_9100(ah)) {
6920                         REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0);
6921                         (void) REG_READ(ah, AR_INTR_ASYNC_ENABLE);
6922
6923                         REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
6924                         (void) REG_READ(ah, AR_INTR_SYNC_ENABLE);
6925                 }
6926         }
6927
6928         mask = ints & ATH9K_INT_COMMON;
6929         mask2 = 0;
6930
6931         if (ints & ATH9K_INT_TX) {
6932                 if (ahp->ah_txOkInterruptMask)
6933                         mask |= AR_IMR_TXOK;
6934                 if (ahp->ah_txDescInterruptMask)
6935                         mask |= AR_IMR_TXDESC;
6936                 if (ahp->ah_txErrInterruptMask)
6937                         mask |= AR_IMR_TXERR;
6938                 if (ahp->ah_txEolInterruptMask)
6939                         mask |= AR_IMR_TXEOL;
6940         }
6941         if (ints & ATH9K_INT_RX) {
6942                 mask |= AR_IMR_RXERR;
6943                 if (ahp->ah_intrMitigation)
6944                         mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM;
6945                 else
6946                         mask |= AR_IMR_RXOK | AR_IMR_RXDESC;
6947                 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
6948                         mask |= AR_IMR_GENTMR;
6949         }
6950
6951         if (ints & (ATH9K_INT_BMISC)) {
6952                 mask |= AR_IMR_BCNMISC;
6953                 if (ints & ATH9K_INT_TIM)
6954                         mask2 |= AR_IMR_S2_TIM;
6955                 if (ints & ATH9K_INT_DTIM)
6956                         mask2 |= AR_IMR_S2_DTIM;
6957                 if (ints & ATH9K_INT_DTIMSYNC)
6958                         mask2 |= AR_IMR_S2_DTIMSYNC;
6959                 if (ints & ATH9K_INT_CABEND)
6960                         mask2 |= (AR_IMR_S2_CABEND);
6961         }
6962
6963         if (ints & (ATH9K_INT_GTT | ATH9K_INT_CST)) {
6964                 mask |= AR_IMR_BCNMISC;
6965                 if (ints & ATH9K_INT_GTT)
6966                         mask2 |= AR_IMR_S2_GTT;
6967                 if (ints & ATH9K_INT_CST)
6968                         mask2 |= AR_IMR_S2_CST;
6969         }
6970
6971         DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "%s: new IMR 0x%x\n", __func__,
6972                  mask);
6973         REG_WRITE(ah, AR_IMR, mask);
6974         mask = REG_READ(ah, AR_IMR_S2) & ~(AR_IMR_S2_TIM |
6975                                            AR_IMR_S2_DTIM |
6976                                            AR_IMR_S2_DTIMSYNC |
6977                                            AR_IMR_S2_CABEND |
6978                                            AR_IMR_S2_CABTO |
6979                                            AR_IMR_S2_TSFOOR |
6980                                            AR_IMR_S2_GTT | AR_IMR_S2_CST);
6981         REG_WRITE(ah, AR_IMR_S2, mask | mask2);
6982         ahp->ah_maskReg = ints;
6983
6984         if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
6985                 if (ints & ATH9K_INT_TIM_TIMER)
6986                         REG_SET_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
6987                 else
6988                         REG_CLR_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
6989         }
6990
6991         if (ints & ATH9K_INT_GLOBAL) {
6992                 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "%s: enable IER\n",
6993                          __func__);
6994                 REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
6995                 if (!AR_SREV_9100(ah)) {
6996                         REG_WRITE(ah, AR_INTR_ASYNC_ENABLE,
6997                                   AR_INTR_MAC_IRQ);
6998                         REG_WRITE(ah, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ);
6999
7000
7001                         REG_WRITE(ah, AR_INTR_SYNC_ENABLE,
7002                                   AR_INTR_SYNC_DEFAULT);
7003                         REG_WRITE(ah, AR_INTR_SYNC_MASK,
7004                                   AR_INTR_SYNC_DEFAULT);
7005                 }
7006                 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "AR_IMR 0x%x IER 0x%x\n",
7007                          REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER));
7008         }
7009
7010         return omask;
7011 }
7012
7013 void
7014 ath9k_hw_beaconinit(struct ath_hal *ah,
7015                     u32 next_beacon, u32 beacon_period)
7016 {
7017         struct ath_hal_5416 *ahp = AH5416(ah);
7018         int flags = 0;
7019
7020         ahp->ah_beaconInterval = beacon_period;
7021
7022         switch (ah->ah_opmode) {
7023         case ATH9K_M_STA:
7024         case ATH9K_M_MONITOR:
7025                 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
7026                 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 0xffff);
7027                 REG_WRITE(ah, AR_NEXT_SWBA, 0x7ffff);
7028                 flags |= AR_TBTT_TIMER_EN;
7029                 break;
7030         case ATH9K_M_IBSS:
7031                 REG_SET_BIT(ah, AR_TXCFG,
7032                             AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
7033                 REG_WRITE(ah, AR_NEXT_NDP_TIMER,
7034                           TU_TO_USEC(next_beacon +
7035                                      (ahp->ah_atimWindow ? ahp->
7036                                       ah_atimWindow : 1)));
7037                 flags |= AR_NDP_TIMER_EN;
7038         case ATH9K_M_HOSTAP:
7039                 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
7040                 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT,
7041                           TU_TO_USEC(next_beacon -
7042                                      ah->ah_config.
7043                                      dma_beacon_response_time));
7044                 REG_WRITE(ah, AR_NEXT_SWBA,
7045                           TU_TO_USEC(next_beacon -
7046                                      ah->ah_config.
7047                                      sw_beacon_response_time));
7048                 flags |=
7049                         AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
7050                 break;
7051         }
7052
7053         REG_WRITE(ah, AR_BEACON_PERIOD, TU_TO_USEC(beacon_period));
7054         REG_WRITE(ah, AR_DMA_BEACON_PERIOD, TU_TO_USEC(beacon_period));
7055         REG_WRITE(ah, AR_SWBA_PERIOD, TU_TO_USEC(beacon_period));
7056         REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period));
7057
7058         beacon_period &= ~ATH9K_BEACON_ENA;
7059         if (beacon_period & ATH9K_BEACON_RESET_TSF) {
7060                 beacon_period &= ~ATH9K_BEACON_RESET_TSF;
7061                 ath9k_hw_reset_tsf(ah);
7062         }
7063
7064         REG_SET_BIT(ah, AR_TIMER_MODE, flags);
7065 }
7066
7067 void
7068 ath9k_hw_set_sta_beacon_timers(struct ath_hal *ah,
7069                                const struct ath9k_beacon_state *bs)
7070 {
7071         u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
7072         struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
7073
7074         REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
7075
7076         REG_WRITE(ah, AR_BEACON_PERIOD,
7077                   TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
7078         REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
7079                   TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
7080
7081         REG_RMW_FIELD(ah, AR_RSSI_THR,
7082                       AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
7083
7084         beaconintval = bs->bs_intval & ATH9K_BEACON_PERIOD;
7085
7086         if (bs->bs_sleepduration > beaconintval)
7087                 beaconintval = bs->bs_sleepduration;
7088
7089         dtimperiod = bs->bs_dtimperiod;
7090         if (bs->bs_sleepduration > dtimperiod)
7091                 dtimperiod = bs->bs_sleepduration;
7092
7093         if (beaconintval == dtimperiod)
7094                 nextTbtt = bs->bs_nextdtim;
7095         else
7096                 nextTbtt = bs->bs_nexttbtt;
7097
7098         DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "%s: next DTIM %d\n", __func__,
7099                  bs->bs_nextdtim);
7100         DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "%s: next beacon %d\n", __func__,
7101                  nextTbtt);
7102         DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "%s: beacon period %d\n", __func__,
7103                  beaconintval);
7104         DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "%s: DTIM period %d\n", __func__,
7105                  dtimperiod);
7106
7107         REG_WRITE(ah, AR_NEXT_DTIM,
7108                   TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
7109         REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
7110
7111         REG_WRITE(ah, AR_SLEEP1,
7112                   SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
7113                   | AR_SLEEP1_ASSUME_DTIM);
7114
7115         if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
7116                 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
7117         else
7118                 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
7119
7120         REG_WRITE(ah, AR_SLEEP2,
7121                   SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
7122
7123         REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
7124         REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
7125
7126         REG_SET_BIT(ah, AR_TIMER_MODE,
7127                     AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
7128                     AR_DTIM_TIMER_EN);
7129
7130 }
7131
7132 bool ath9k_hw_keyisvalid(struct ath_hal *ah, u16 entry)
7133 {
7134         if (entry < ah->ah_caps.keycache_size) {
7135                 u32 val = REG_READ(ah, AR_KEYTABLE_MAC1(entry));
7136                 if (val & AR_KEYTABLE_VALID)
7137                         return true;
7138         }
7139         return false;
7140 }
7141
7142 bool ath9k_hw_keyreset(struct ath_hal *ah, u16 entry)
7143 {
7144         u32 keyType;
7145
7146         if (entry >= ah->ah_caps.keycache_size) {
7147                 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
7148                          "%s: entry %u out of range\n", __func__, entry);
7149                 return false;
7150         }
7151         keyType = REG_READ(ah, AR_KEYTABLE_TYPE(entry));
7152
7153         REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0);
7154         REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0);
7155         REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0);
7156         REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0);
7157         REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0);
7158         REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR);
7159         REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0);
7160         REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0);
7161
7162         if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
7163                 u16 micentry = entry + 64;
7164
7165                 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), 0);
7166                 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
7167                 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), 0);
7168                 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
7169
7170         }
7171
7172         if (ah->ah_curchan == NULL)
7173                 return true;
7174
7175         return true;
7176 }
7177
7178 bool
7179 ath9k_hw_keysetmac(struct ath_hal *ah, u16 entry,
7180                    const u8 *mac)
7181 {
7182         u32 macHi, macLo;
7183
7184         if (entry >= ah->ah_caps.keycache_size) {
7185                 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
7186                          "%s: entry %u out of range\n", __func__, entry);
7187                 return false;
7188         }
7189
7190         if (mac != NULL) {
7191                 macHi = (mac[5] << 8) | mac[4];
7192                 macLo = (mac[3] << 24) | (mac[2] << 16)
7193                         | (mac[1] << 8) | mac[0];
7194                 macLo >>= 1;
7195                 macLo |= (macHi & 1) << 31;
7196                 macHi >>= 1;
7197         } else {
7198                 macLo = macHi = 0;
7199         }
7200         REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo);
7201         REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), macHi | AR_KEYTABLE_VALID);
7202
7203         return true;
7204 }
7205
7206 bool
7207 ath9k_hw_set_keycache_entry(struct ath_hal *ah, u16 entry,
7208                             const struct ath9k_keyval *k,
7209                             const u8 *mac, int xorKey)
7210 {
7211         const struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
7212         u32 key0, key1, key2, key3, key4;
7213         u32 keyType;
7214         u32 xorMask = xorKey ?
7215                 (ATH9K_KEY_XOR << 24 | ATH9K_KEY_XOR << 16 | ATH9K_KEY_XOR << 8
7216                  | ATH9K_KEY_XOR) : 0;
7217         struct ath_hal_5416 *ahp = AH5416(ah);
7218
7219         if (entry >= pCap->keycache_size) {
7220                 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
7221                          "%s: entry %u out of range\n", __func__, entry);
7222                 return false;
7223         }
7224         switch (k->kv_type) {
7225         case ATH9K_CIPHER_AES_OCB:
7226                 keyType = AR_KEYTABLE_TYPE_AES;
7227                 break;
7228         case ATH9K_CIPHER_AES_CCM:
7229                 if (!(pCap->hw_caps & ATH9K_HW_CAP_CIPHER_AESCCM)) {
7230                         DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
7231                                  "%s: AES-CCM not supported by "
7232                                  "mac rev 0x%x\n", __func__,
7233                                  ah->ah_macRev);
7234                         return false;
7235                 }
7236                 keyType = AR_KEYTABLE_TYPE_CCM;
7237                 break;
7238         case ATH9K_CIPHER_TKIP:
7239                 keyType = AR_KEYTABLE_TYPE_TKIP;
7240                 if (ATH9K_IS_MIC_ENABLED(ah)
7241                     && entry + 64 >= pCap->keycache_size) {
7242                         DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
7243                                  "%s: entry %u inappropriate for TKIP\n",
7244                                  __func__, entry);
7245                         return false;
7246                 }
7247                 break;
7248         case ATH9K_CIPHER_WEP:
7249                 if (k->kv_len < LEN_WEP40) {
7250                         DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
7251                                  "%s: WEP key length %u too small\n",
7252                                  __func__, k->kv_len);
7253                         return false;
7254                 }
7255                 if (k->kv_len <= LEN_WEP40)
7256                         keyType = AR_KEYTABLE_TYPE_40;
7257                 else if (k->kv_len <= LEN_WEP104)
7258                         keyType = AR_KEYTABLE_TYPE_104;
7259                 else
7260                         keyType = AR_KEYTABLE_TYPE_128;
7261                 break;
7262         case ATH9K_CIPHER_CLR:
7263                 keyType = AR_KEYTABLE_TYPE_CLR;
7264                 break;
7265         default:
7266                 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
7267                          "%s: cipher %u not supported\n", __func__,
7268                          k->kv_type);
7269                 return false;
7270         }
7271
7272         key0 = get_unaligned_le32(k->kv_val + 0) ^ xorMask;
7273         key1 = (get_unaligned_le16(k->kv_val + 4) ^ xorMask) & 0xffff;
7274         key2 = get_unaligned_le32(k->kv_val + 6) ^ xorMask;
7275         key3 = (get_unaligned_le16(k->kv_val + 10) ^ xorMask) & 0xffff;
7276         key4 = get_unaligned_le32(k->kv_val + 12) ^ xorMask;
7277         if (k->kv_len <= LEN_WEP104)
7278                 key4 &= 0xff;
7279
7280         if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
7281                 u16 micentry = entry + 64;
7282
7283                 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), ~key0);
7284                 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), ~key1);
7285                 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
7286                 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
7287                 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
7288                 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
7289                 (void) ath9k_hw_keysetmac(ah, entry, mac);
7290
7291                 if (ahp->ah_miscMode & AR_PCU_MIC_NEW_LOC_ENA) {
7292                         u32 mic0, mic1, mic2, mic3, mic4;
7293
7294                         mic0 = get_unaligned_le32(k->kv_mic + 0);
7295                         mic2 = get_unaligned_le32(k->kv_mic + 4);
7296                         mic1 = get_unaligned_le16(k->kv_txmic + 2) & 0xffff;
7297                         mic3 = get_unaligned_le16(k->kv_txmic + 0) & 0xffff;
7298                         mic4 = get_unaligned_le32(k->kv_txmic + 4);
7299                         REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
7300                         REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), mic1);
7301                         REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
7302                         REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), mic3);
7303                         REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), mic4);
7304                         REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
7305                                   AR_KEYTABLE_TYPE_CLR);
7306
7307                 } else {
7308                         u32 mic0, mic2;
7309
7310                         mic0 = get_unaligned_le32(k->kv_mic + 0);
7311                         mic2 = get_unaligned_le32(k->kv_mic + 4);
7312                         REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
7313                         REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
7314                         REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
7315                         REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
7316                         REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), 0);
7317                         REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
7318                                   AR_KEYTABLE_TYPE_CLR);
7319                 }
7320                 REG_WRITE(ah, AR_KEYTABLE_MAC0(micentry), 0);
7321                 REG_WRITE(ah, AR_KEYTABLE_MAC1(micentry), 0);
7322                 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
7323                 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
7324         } else {
7325                 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
7326                 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
7327                 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
7328                 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
7329                 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
7330                 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
7331
7332                 (void) ath9k_hw_keysetmac(ah, entry, mac);
7333         }
7334
7335         if (ah->ah_curchan == NULL)
7336                 return true;
7337
7338         return true;
7339 }
7340
7341 bool
7342 ath9k_hw_updatetxtriglevel(struct ath_hal *ah, bool bIncTrigLevel)
7343 {
7344         struct ath_hal_5416 *ahp = AH5416(ah);
7345         u32 txcfg, curLevel, newLevel;
7346         enum ath9k_int omask;
7347
7348         if (ah->ah_txTrigLevel >= MAX_TX_FIFO_THRESHOLD)
7349                 return false;
7350
7351         omask = ath9k_hw_set_interrupts(ah,
7352                                         ahp->ah_maskReg & ~ATH9K_INT_GLOBAL);
7353
7354         txcfg = REG_READ(ah, AR_TXCFG);
7355         curLevel = MS(txcfg, AR_FTRIG);
7356         newLevel = curLevel;
7357         if (bIncTrigLevel) {
7358                 if (curLevel < MAX_TX_FIFO_THRESHOLD)
7359                         newLevel++;
7360         } else if (curLevel > MIN_TX_FIFO_THRESHOLD)
7361                 newLevel--;
7362         if (newLevel != curLevel)
7363                 REG_WRITE(ah, AR_TXCFG,
7364                           (txcfg & ~AR_FTRIG) | SM(newLevel, AR_FTRIG));
7365
7366         ath9k_hw_set_interrupts(ah, omask);
7367
7368         ah->ah_txTrigLevel = newLevel;
7369
7370         return newLevel != curLevel;
7371 }
7372
7373 bool ath9k_hw_set_txq_props(struct ath_hal *ah, int q,
7374                             const struct ath9k_tx_queue_info *qinfo)
7375 {
7376         u32 cw;
7377         struct ath_hal_5416 *ahp = AH5416(ah);
7378         struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
7379         struct ath9k_tx_queue_info *qi;
7380
7381         if (q >= pCap->total_queues) {
7382                 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: invalid queue num %u\n",
7383                          __func__, q);
7384                 return false;
7385         }
7386
7387         qi = &ahp->ah_txq[q];
7388         if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
7389                 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: inactive queue\n",
7390                          __func__);
7391                 return false;
7392         }
7393
7394         DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: queue %p\n", __func__, qi);
7395
7396         qi->tqi_ver = qinfo->tqi_ver;
7397         qi->tqi_subtype = qinfo->tqi_subtype;
7398         qi->tqi_qflags = qinfo->tqi_qflags;
7399         qi->tqi_priority = qinfo->tqi_priority;
7400         if (qinfo->tqi_aifs != ATH9K_TXQ_USEDEFAULT)
7401                 qi->tqi_aifs = min(qinfo->tqi_aifs, 255U);
7402         else
7403                 qi->tqi_aifs = INIT_AIFS;
7404         if (qinfo->tqi_cwmin != ATH9K_TXQ_USEDEFAULT) {
7405                 cw = min(qinfo->tqi_cwmin, 1024U);
7406                 qi->tqi_cwmin = 1;
7407                 while (qi->tqi_cwmin < cw)
7408                         qi->tqi_cwmin = (qi->tqi_cwmin << 1) | 1;
7409         } else
7410                 qi->tqi_cwmin = qinfo->tqi_cwmin;
7411         if (qinfo->tqi_cwmax != ATH9K_TXQ_USEDEFAULT) {
7412                 cw = min(qinfo->tqi_cwmax, 1024U);
7413                 qi->tqi_cwmax = 1;
7414                 while (qi->tqi_cwmax < cw)
7415                         qi->tqi_cwmax = (qi->tqi_cwmax << 1) | 1;
7416         } else
7417                 qi->tqi_cwmax = INIT_CWMAX;
7418
7419         if (qinfo->tqi_shretry != 0)
7420                 qi->tqi_shretry = min((u32) qinfo->tqi_shretry, 15U);
7421         else
7422                 qi->tqi_shretry = INIT_SH_RETRY;
7423         if (qinfo->tqi_lgretry != 0)
7424                 qi->tqi_lgretry = min((u32) qinfo->tqi_lgretry, 15U);
7425         else
7426                 qi->tqi_lgretry = INIT_LG_RETRY;
7427         qi->tqi_cbrPeriod = qinfo->tqi_cbrPeriod;
7428         qi->tqi_cbrOverflowLimit = qinfo->tqi_cbrOverflowLimit;
7429         qi->tqi_burstTime = qinfo->tqi_burstTime;
7430         qi->tqi_readyTime = qinfo->tqi_readyTime;
7431
7432         switch (qinfo->tqi_subtype) {
7433         case ATH9K_WME_UPSD:
7434                 if (qi->tqi_type == ATH9K_TX_QUEUE_DATA)
7435                         qi->tqi_intFlags = ATH9K_TXQ_USE_LOCKOUT_BKOFF_DIS;
7436                 break;
7437         default:
7438                 break;
7439         }
7440         return true;
7441 }
7442
7443 bool ath9k_hw_get_txq_props(struct ath_hal *ah, int q,
7444                             struct ath9k_tx_queue_info *qinfo)
7445 {
7446         struct ath_hal_5416 *ahp = AH5416(ah);
7447         struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
7448         struct ath9k_tx_queue_info *qi;
7449
7450         if (q >= pCap->total_queues) {
7451                 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: invalid queue num %u\n",
7452                          __func__, q);
7453                 return false;
7454         }
7455
7456         qi = &ahp->ah_txq[q];
7457         if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
7458                 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: inactive queue\n",
7459                          __func__);
7460                 return false;
7461         }
7462
7463         qinfo->tqi_qflags = qi->tqi_qflags;
7464         qinfo->tqi_ver = qi->tqi_ver;
7465         qinfo->tqi_subtype = qi->tqi_subtype;
7466         qinfo->tqi_qflags = qi->tqi_qflags;
7467         qinfo->tqi_priority = qi->tqi_priority;
7468         qinfo->tqi_aifs = qi->tqi_aifs;
7469         qinfo->tqi_cwmin = qi->tqi_cwmin;
7470         qinfo->tqi_cwmax = qi->tqi_cwmax;
7471         qinfo->tqi_shretry = qi->tqi_shretry;
7472         qinfo->tqi_lgretry = qi->tqi_lgretry;
7473         qinfo->tqi_cbrPeriod = qi->tqi_cbrPeriod;
7474         qinfo->tqi_cbrOverflowLimit = qi->tqi_cbrOverflowLimit;
7475         qinfo->tqi_burstTime = qi->tqi_burstTime;
7476         qinfo->tqi_readyTime = qi->tqi_readyTime;
7477
7478         return true;
7479 }
7480
7481 int
7482 ath9k_hw_setuptxqueue(struct ath_hal *ah, enum ath9k_tx_queue type,
7483                       const struct ath9k_tx_queue_info *qinfo)
7484 {
7485         struct ath_hal_5416 *ahp = AH5416(ah);
7486         struct ath9k_tx_queue_info *qi;
7487         struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
7488         int q;
7489
7490         switch (type) {
7491         case ATH9K_TX_QUEUE_BEACON:
7492                 q = pCap->total_queues - 1;
7493                 break;
7494         case ATH9K_TX_QUEUE_CAB:
7495                 q = pCap->total_queues - 2;
7496                 break;
7497         case ATH9K_TX_QUEUE_PSPOLL:
7498                 q = 1;
7499                 break;
7500         case ATH9K_TX_QUEUE_UAPSD:
7501                 q = pCap->total_queues - 3;
7502                 break;
7503         case ATH9K_TX_QUEUE_DATA:
7504                 for (q = 0; q < pCap->total_queues; q++)
7505                         if (ahp->ah_txq[q].tqi_type ==
7506                             ATH9K_TX_QUEUE_INACTIVE)
7507                                 break;
7508                 if (q == pCap->total_queues) {
7509                         DPRINTF(ah->ah_sc, ATH_DBG_QUEUE,
7510                                  "%s: no available tx queue\n", __func__);
7511                         return -1;
7512                 }
7513                 break;
7514         default:
7515                 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: bad tx queue type %u\n",
7516                          __func__, type);
7517                 return -1;
7518         }
7519
7520         DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: queue %u\n", __func__, q);
7521
7522         qi = &ahp->ah_txq[q];
7523         if (qi->tqi_type != ATH9K_TX_QUEUE_INACTIVE) {
7524                 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE,
7525                          "%s: tx queue %u already active\n", __func__, q);
7526                 return -1;
7527         }
7528         memset(qi, 0, sizeof(struct ath9k_tx_queue_info));
7529         qi->tqi_type = type;
7530         if (qinfo == NULL) {
7531                 qi->tqi_qflags =
7532                         TXQ_FLAG_TXOKINT_ENABLE
7533                         | TXQ_FLAG_TXERRINT_ENABLE
7534                         | TXQ_FLAG_TXDESCINT_ENABLE | TXQ_FLAG_TXURNINT_ENABLE;
7535                 qi->tqi_aifs = INIT_AIFS;
7536                 qi->tqi_cwmin = ATH9K_TXQ_USEDEFAULT;
7537                 qi->tqi_cwmax = INIT_CWMAX;
7538                 qi->tqi_shretry = INIT_SH_RETRY;
7539                 qi->tqi_lgretry = INIT_LG_RETRY;
7540                 qi->tqi_physCompBuf = 0;
7541         } else {
7542                 qi->tqi_physCompBuf = qinfo->tqi_physCompBuf;
7543                 (void) ath9k_hw_set_txq_props(ah, q, qinfo);
7544         }
7545
7546         return q;
7547 }
7548
7549 static void
7550 ath9k_hw_set_txq_interrupts(struct ath_hal *ah,
7551                             struct ath9k_tx_queue_info *qi)
7552 {
7553         struct ath_hal_5416 *ahp = AH5416(ah);
7554
7555         DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
7556                  "%s: tx ok 0x%x err 0x%x desc 0x%x eol 0x%x urn 0x%x\n",
7557                  __func__, ahp->ah_txOkInterruptMask,
7558                  ahp->ah_txErrInterruptMask, ahp->ah_txDescInterruptMask,
7559                  ahp->ah_txEolInterruptMask, ahp->ah_txUrnInterruptMask);
7560
7561         REG_WRITE(ah, AR_IMR_S0,
7562                   SM(ahp->ah_txOkInterruptMask, AR_IMR_S0_QCU_TXOK)
7563                   | SM(ahp->ah_txDescInterruptMask, AR_IMR_S0_QCU_TXDESC));
7564         REG_WRITE(ah, AR_IMR_S1,
7565                   SM(ahp->ah_txErrInterruptMask, AR_IMR_S1_QCU_TXERR)
7566                   | SM(ahp->ah_txEolInterruptMask, AR_IMR_S1_QCU_TXEOL));
7567         REG_RMW_FIELD(ah, AR_IMR_S2,
7568                       AR_IMR_S2_QCU_TXURN, ahp->ah_txUrnInterruptMask);
7569 }
7570
7571 bool ath9k_hw_releasetxqueue(struct ath_hal *ah, u32 q)
7572 {
7573         struct ath_hal_5416 *ahp = AH5416(ah);
7574         struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
7575         struct ath9k_tx_queue_info *qi;
7576
7577         if (q >= pCap->total_queues) {
7578                 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: invalid queue num %u\n",
7579                          __func__, q);
7580                 return false;
7581         }
7582         qi = &ahp->ah_txq[q];
7583         if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
7584                 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: inactive queue %u\n",
7585                          __func__, q);
7586                 return false;
7587         }
7588
7589         DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: release queue %u\n",
7590                 __func__, q);
7591
7592         qi->tqi_type = ATH9K_TX_QUEUE_INACTIVE;
7593         ahp->ah_txOkInterruptMask &= ~(1 << q);
7594         ahp->ah_txErrInterruptMask &= ~(1 << q);
7595         ahp->ah_txDescInterruptMask &= ~(1 << q);
7596         ahp->ah_txEolInterruptMask &= ~(1 << q);
7597         ahp->ah_txUrnInterruptMask &= ~(1 << q);
7598         ath9k_hw_set_txq_interrupts(ah, qi);
7599
7600         return true;
7601 }
7602
7603 bool ath9k_hw_resettxqueue(struct ath_hal *ah, u32 q)
7604 {
7605         struct ath_hal_5416 *ahp = AH5416(ah);
7606         struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
7607         struct ath9k_channel *chan = ah->ah_curchan;
7608         struct ath9k_tx_queue_info *qi;
7609         u32 cwMin, chanCwMin, value;
7610
7611         if (q >= pCap->total_queues) {
7612                 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: invalid queue num %u\n",
7613                          __func__, q);
7614                 return false;
7615         }
7616         qi = &ahp->ah_txq[q];
7617         if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
7618                 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: inactive queue %u\n",
7619                          __func__, q);
7620                 return true;
7621         }
7622
7623         DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: reset queue %u\n", __func__, q);
7624
7625         if (qi->tqi_cwmin == ATH9K_TXQ_USEDEFAULT) {
7626                 if (chan && IS_CHAN_B(chan))
7627                         chanCwMin = INIT_CWMIN_11B;
7628                 else
7629                         chanCwMin = INIT_CWMIN;
7630
7631                 for (cwMin = 1; cwMin < chanCwMin; cwMin = (cwMin << 1) | 1);
7632         } else
7633                 cwMin = qi->tqi_cwmin;
7634
7635         REG_WRITE(ah, AR_DLCL_IFS(q), SM(cwMin, AR_D_LCL_IFS_CWMIN)
7636                   | SM(qi->tqi_cwmax, AR_D_LCL_IFS_CWMAX)
7637                   | SM(qi->tqi_aifs, AR_D_LCL_IFS_AIFS));
7638
7639         REG_WRITE(ah, AR_DRETRY_LIMIT(q),
7640                   SM(INIT_SSH_RETRY, AR_D_RETRY_LIMIT_STA_SH)
7641                   | SM(INIT_SLG_RETRY, AR_D_RETRY_LIMIT_STA_LG)
7642                   | SM(qi->tqi_shretry, AR_D_RETRY_LIMIT_FR_SH));
7643
7644         REG_WRITE(ah, AR_QMISC(q), AR_Q_MISC_DCU_EARLY_TERM_REQ);
7645         REG_WRITE(ah, AR_DMISC(q),
7646                   AR_D_MISC_CW_BKOFF_EN | AR_D_MISC_FRAG_WAIT_EN | 0x2);
7647
7648         if (qi->tqi_cbrPeriod) {
7649                 REG_WRITE(ah, AR_QCBRCFG(q),
7650                           SM(qi->tqi_cbrPeriod, AR_Q_CBRCFG_INTERVAL)
7651                           | SM(qi->tqi_cbrOverflowLimit,
7652                                AR_Q_CBRCFG_OVF_THRESH));
7653                 REG_WRITE(ah, AR_QMISC(q),
7654                           REG_READ(ah,
7655                                    AR_QMISC(q)) | AR_Q_MISC_FSP_CBR | (qi->
7656                                         tqi_cbrOverflowLimit
7657                                         ?
7658                                         AR_Q_MISC_CBR_EXP_CNTR_LIMIT_EN
7659                                         :
7660                                         0));
7661         }
7662         if (qi->tqi_readyTime && (qi->tqi_type != ATH9K_TX_QUEUE_CAB)) {
7663                 REG_WRITE(ah, AR_QRDYTIMECFG(q),
7664                           SM(qi->tqi_readyTime, AR_Q_RDYTIMECFG_DURATION) |
7665                           AR_Q_RDYTIMECFG_EN);
7666         }
7667
7668         REG_WRITE(ah, AR_DCHNTIME(q),
7669                   SM(qi->tqi_burstTime, AR_D_CHNTIME_DUR) |
7670                   (qi->tqi_burstTime ? AR_D_CHNTIME_EN : 0));
7671
7672         if (qi->tqi_burstTime
7673             && (qi->tqi_qflags & TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE)) {
7674                 REG_WRITE(ah, AR_QMISC(q),
7675                           REG_READ(ah,
7676                                    AR_QMISC(q)) |
7677                           AR_Q_MISC_RDYTIME_EXP_POLICY);
7678
7679         }
7680
7681         if (qi->tqi_qflags & TXQ_FLAG_BACKOFF_DISABLE) {
7682                 REG_WRITE(ah, AR_DMISC(q),
7683                           REG_READ(ah, AR_DMISC(q)) |
7684                           AR_D_MISC_POST_FR_BKOFF_DIS);
7685         }
7686         if (qi->tqi_qflags & TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE) {
7687                 REG_WRITE(ah, AR_DMISC(q),
7688                           REG_READ(ah, AR_DMISC(q)) |
7689                           AR_D_MISC_FRAG_BKOFF_EN);
7690         }
7691         switch (qi->tqi_type) {
7692         case ATH9K_TX_QUEUE_BEACON:
7693                 REG_WRITE(ah, AR_QMISC(q), REG_READ(ah, AR_QMISC(q))
7694                           | AR_Q_MISC_FSP_DBA_GATED
7695                           | AR_Q_MISC_BEACON_USE
7696                           | AR_Q_MISC_CBR_INCR_DIS1);
7697
7698                 REG_WRITE(ah, AR_DMISC(q), REG_READ(ah, AR_DMISC(q))
7699                           | (AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL <<
7700                              AR_D_MISC_ARB_LOCKOUT_CNTRL_S)
7701                           | AR_D_MISC_BEACON_USE
7702                           | AR_D_MISC_POST_FR_BKOFF_DIS);
7703                 break;
7704         case ATH9K_TX_QUEUE_CAB:
7705                 REG_WRITE(ah, AR_QMISC(q), REG_READ(ah, AR_QMISC(q))
7706                           | AR_Q_MISC_FSP_DBA_GATED
7707                           | AR_Q_MISC_CBR_INCR_DIS1
7708                           | AR_Q_MISC_CBR_INCR_DIS0);
7709                 value = (qi->tqi_readyTime
7710                          - (ah->ah_config.sw_beacon_response_time -
7711                             ah->ah_config.dma_beacon_response_time)
7712                          -
7713                          ah->ah_config.additional_swba_backoff) *
7714                         1024;
7715                 REG_WRITE(ah, AR_QRDYTIMECFG(q),
7716                           value | AR_Q_RDYTIMECFG_EN);
7717                 REG_WRITE(ah, AR_DMISC(q), REG_READ(ah, AR_DMISC(q))
7718                           | (AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL <<
7719                              AR_D_MISC_ARB_LOCKOUT_CNTRL_S));
7720                 break;
7721         case ATH9K_TX_QUEUE_PSPOLL:
7722                 REG_WRITE(ah, AR_QMISC(q),
7723                           REG_READ(ah,
7724                                    AR_QMISC(q)) | AR_Q_MISC_CBR_INCR_DIS1);
7725                 break;
7726         case ATH9K_TX_QUEUE_UAPSD:
7727                 REG_WRITE(ah, AR_DMISC(q), REG_READ(ah, AR_DMISC(q))
7728                           | AR_D_MISC_POST_FR_BKOFF_DIS);
7729                 break;
7730         default:
7731                 break;
7732         }
7733
7734         if (qi->tqi_intFlags & ATH9K_TXQ_USE_LOCKOUT_BKOFF_DIS) {
7735                 REG_WRITE(ah, AR_DMISC(q),
7736                           REG_READ(ah, AR_DMISC(q)) |
7737                           SM(AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL,
7738                              AR_D_MISC_ARB_LOCKOUT_CNTRL) |
7739                           AR_D_MISC_POST_FR_BKOFF_DIS);
7740         }
7741
7742         if (qi->tqi_qflags & TXQ_FLAG_TXOKINT_ENABLE)
7743                 ahp->ah_txOkInterruptMask |= 1 << q;
7744         else
7745                 ahp->ah_txOkInterruptMask &= ~(1 << q);
7746         if (qi->tqi_qflags & TXQ_FLAG_TXERRINT_ENABLE)
7747                 ahp->ah_txErrInterruptMask |= 1 << q;
7748         else
7749                 ahp->ah_txErrInterruptMask &= ~(1 << q);
7750         if (qi->tqi_qflags & TXQ_FLAG_TXDESCINT_ENABLE)
7751                 ahp->ah_txDescInterruptMask |= 1 << q;
7752         else
7753                 ahp->ah_txDescInterruptMask &= ~(1 << q);
7754         if (qi->tqi_qflags & TXQ_FLAG_TXEOLINT_ENABLE)
7755                 ahp->ah_txEolInterruptMask |= 1 << q;
7756         else
7757                 ahp->ah_txEolInterruptMask &= ~(1 << q);
7758         if (qi->tqi_qflags & TXQ_FLAG_TXURNINT_ENABLE)
7759                 ahp->ah_txUrnInterruptMask |= 1 << q;
7760         else
7761                 ahp->ah_txUrnInterruptMask &= ~(1 << q);
7762         ath9k_hw_set_txq_interrupts(ah, qi);
7763
7764         return true;
7765 }
7766
7767 void ath9k_hw_gettxintrtxqs(struct ath_hal *ah, u32 *txqs)
7768 {
7769         struct ath_hal_5416 *ahp = AH5416(ah);
7770         *txqs &= ahp->ah_intrTxqs;
7771         ahp->ah_intrTxqs &= ~(*txqs);
7772 }
7773
7774 bool
7775 ath9k_hw_filltxdesc(struct ath_hal *ah, struct ath_desc *ds,
7776                     u32 segLen, bool firstSeg,
7777                     bool lastSeg, const struct ath_desc *ds0)
7778 {
7779         struct ar5416_desc *ads = AR5416DESC(ds);
7780
7781         if (firstSeg) {
7782                 ads->ds_ctl1 |= segLen | (lastSeg ? 0 : AR_TxMore);
7783         } else if (lastSeg) {
7784                 ads->ds_ctl0 = 0;
7785                 ads->ds_ctl1 = segLen;
7786                 ads->ds_ctl2 = AR5416DESC_CONST(ds0)->ds_ctl2;
7787                 ads->ds_ctl3 = AR5416DESC_CONST(ds0)->ds_ctl3;
7788         } else {
7789                 ads->ds_ctl0 = 0;
7790                 ads->ds_ctl1 = segLen | AR_TxMore;
7791                 ads->ds_ctl2 = 0;
7792                 ads->ds_ctl3 = 0;
7793         }
7794         ads->ds_txstatus0 = ads->ds_txstatus1 = 0;
7795         ads->ds_txstatus2 = ads->ds_txstatus3 = 0;
7796         ads->ds_txstatus4 = ads->ds_txstatus5 = 0;
7797         ads->ds_txstatus6 = ads->ds_txstatus7 = 0;
7798         ads->ds_txstatus8 = ads->ds_txstatus9 = 0;
7799         return true;
7800 }
7801
7802 void ath9k_hw_cleartxdesc(struct ath_hal *ah, struct ath_desc *ds)
7803 {
7804         struct ar5416_desc *ads = AR5416DESC(ds);
7805
7806         ads->ds_txstatus0 = ads->ds_txstatus1 = 0;
7807         ads->ds_txstatus2 = ads->ds_txstatus3 = 0;
7808         ads->ds_txstatus4 = ads->ds_txstatus5 = 0;
7809         ads->ds_txstatus6 = ads->ds_txstatus7 = 0;
7810         ads->ds_txstatus8 = ads->ds_txstatus9 = 0;
7811 }
7812
7813 int
7814 ath9k_hw_txprocdesc(struct ath_hal *ah, struct ath_desc *ds)
7815 {
7816         struct ar5416_desc *ads = AR5416DESC(ds);
7817
7818         if ((ads->ds_txstatus9 & AR_TxDone) == 0)
7819                 return -EINPROGRESS;
7820
7821         ds->ds_txstat.ts_seqnum = MS(ads->ds_txstatus9, AR_SeqNum);
7822         ds->ds_txstat.ts_tstamp = ads->AR_SendTimestamp;
7823         ds->ds_txstat.ts_status = 0;
7824         ds->ds_txstat.ts_flags = 0;
7825
7826         if (ads->ds_txstatus1 & AR_ExcessiveRetries)
7827                 ds->ds_txstat.ts_status |= ATH9K_TXERR_XRETRY;
7828         if (ads->ds_txstatus1 & AR_Filtered)
7829                 ds->ds_txstat.ts_status |= ATH9K_TXERR_FILT;
7830         if (ads->ds_txstatus1 & AR_FIFOUnderrun)
7831                 ds->ds_txstat.ts_status |= ATH9K_TXERR_FIFO;
7832         if (ads->ds_txstatus9 & AR_TxOpExceeded)
7833                 ds->ds_txstat.ts_status |= ATH9K_TXERR_XTXOP;
7834         if (ads->ds_txstatus1 & AR_TxTimerExpired)
7835                 ds->ds_txstat.ts_status |= ATH9K_TXERR_TIMER_EXPIRED;
7836
7837         if (ads->ds_txstatus1 & AR_DescCfgErr)
7838                 ds->ds_txstat.ts_flags |= ATH9K_TX_DESC_CFG_ERR;
7839         if (ads->ds_txstatus1 & AR_TxDataUnderrun) {
7840                 ds->ds_txstat.ts_flags |= ATH9K_TX_DATA_UNDERRUN;
7841                 ath9k_hw_updatetxtriglevel(ah, true);
7842         }
7843         if (ads->ds_txstatus1 & AR_TxDelimUnderrun) {
7844                 ds->ds_txstat.ts_flags |= ATH9K_TX_DELIM_UNDERRUN;
7845                 ath9k_hw_updatetxtriglevel(ah, true);
7846         }
7847         if (ads->ds_txstatus0 & AR_TxBaStatus) {
7848                 ds->ds_txstat.ts_flags |= ATH9K_TX_BA;
7849                 ds->ds_txstat.ba_low = ads->AR_BaBitmapLow;
7850                 ds->ds_txstat.ba_high = ads->AR_BaBitmapHigh;
7851         }
7852
7853         ds->ds_txstat.ts_rateindex = MS(ads->ds_txstatus9, AR_FinalTxIdx);
7854         switch (ds->ds_txstat.ts_rateindex) {
7855         case 0:
7856                 ds->ds_txstat.ts_ratecode = MS(ads->ds_ctl3, AR_XmitRate0);
7857                 break;
7858         case 1:
7859                 ds->ds_txstat.ts_ratecode = MS(ads->ds_ctl3, AR_XmitRate1);
7860                 break;
7861         case 2:
7862                 ds->ds_txstat.ts_ratecode = MS(ads->ds_ctl3, AR_XmitRate2);
7863                 break;
7864         case 3:
7865                 ds->ds_txstat.ts_ratecode = MS(ads->ds_ctl3, AR_XmitRate3);
7866                 break;
7867         }
7868
7869         ds->ds_txstat.ts_rssi = MS(ads->ds_txstatus5, AR_TxRSSICombined);
7870         ds->ds_txstat.ts_rssi_ctl0 = MS(ads->ds_txstatus0, AR_TxRSSIAnt00);
7871         ds->ds_txstat.ts_rssi_ctl1 = MS(ads->ds_txstatus0, AR_TxRSSIAnt01);
7872         ds->ds_txstat.ts_rssi_ctl2 = MS(ads->ds_txstatus0, AR_TxRSSIAnt02);
7873         ds->ds_txstat.ts_rssi_ext0 = MS(ads->ds_txstatus5, AR_TxRSSIAnt10);
7874         ds->ds_txstat.ts_rssi_ext1 = MS(ads->ds_txstatus5, AR_TxRSSIAnt11);
7875         ds->ds_txstat.ts_rssi_ext2 = MS(ads->ds_txstatus5, AR_TxRSSIAnt12);
7876         ds->ds_txstat.evm0 = ads->AR_TxEVM0;
7877         ds->ds_txstat.evm1 = ads->AR_TxEVM1;
7878         ds->ds_txstat.evm2 = ads->AR_TxEVM2;
7879         ds->ds_txstat.ts_shortretry = MS(ads->ds_txstatus1, AR_RTSFailCnt);
7880         ds->ds_txstat.ts_longretry = MS(ads->ds_txstatus1, AR_DataFailCnt);
7881         ds->ds_txstat.ts_virtcol = MS(ads->ds_txstatus1, AR_VirtRetryCnt);
7882         ds->ds_txstat.ts_antenna = 1;
7883
7884         return 0;
7885 }
7886
7887 void
7888 ath9k_hw_set11n_txdesc(struct ath_hal *ah, struct ath_desc *ds,
7889                        u32 pktLen, enum ath9k_pkt_type type, u32 txPower,
7890                        u32 keyIx, enum ath9k_key_type keyType, u32 flags)
7891 {
7892         struct ar5416_desc *ads = AR5416DESC(ds);
7893         struct ath_hal_5416 *ahp = AH5416(ah);
7894
7895         txPower += ahp->ah_txPowerIndexOffset;
7896         if (txPower > 63)
7897                 txPower = 63;
7898
7899         ads->ds_ctl0 = (pktLen & AR_FrameLen)
7900                 | (flags & ATH9K_TXDESC_VMF ? AR_VirtMoreFrag : 0)
7901                 | SM(txPower, AR_XmitPower)
7902                 | (flags & ATH9K_TXDESC_VEOL ? AR_VEOL : 0)
7903                 | (flags & ATH9K_TXDESC_CLRDMASK ? AR_ClrDestMask : 0)
7904                 | (flags & ATH9K_TXDESC_INTREQ ? AR_TxIntrReq : 0)
7905                 | (keyIx != ATH9K_TXKEYIX_INVALID ? AR_DestIdxValid : 0);
7906
7907         ads->ds_ctl1 =
7908                 (keyIx != ATH9K_TXKEYIX_INVALID ? SM(keyIx, AR_DestIdx) : 0)
7909                 | SM(type, AR_FrameType)
7910                 | (flags & ATH9K_TXDESC_NOACK ? AR_NoAck : 0)
7911                 | (flags & ATH9K_TXDESC_EXT_ONLY ? AR_ExtOnly : 0)
7912                 | (flags & ATH9K_TXDESC_EXT_AND_CTL ? AR_ExtAndCtl : 0);
7913
7914         ads->ds_ctl6 = SM(keyType, AR_EncrType);
7915
7916         if (AR_SREV_9285(ah)) {
7917
7918                 ads->ds_ctl8 = 0;
7919                 ads->ds_ctl9 = 0;
7920                 ads->ds_ctl10 = 0;
7921                 ads->ds_ctl11 = 0;
7922         }
7923 }
7924
7925 void
7926 ath9k_hw_set11n_ratescenario(struct ath_hal *ah, struct ath_desc *ds,
7927                              struct ath_desc *lastds,
7928                              u32 durUpdateEn, u32 rtsctsRate,
7929                              u32 rtsctsDuration,
7930                              struct ath9k_11n_rate_series series[],
7931                              u32 nseries, u32 flags)
7932 {
7933         struct ar5416_desc *ads = AR5416DESC(ds);
7934         struct ar5416_desc *last_ads = AR5416DESC(lastds);
7935         u32 ds_ctl0;
7936
7937         (void) nseries;
7938         (void) rtsctsDuration;
7939
7940         if (flags & (ATH9K_TXDESC_RTSENA | ATH9K_TXDESC_CTSENA)) {
7941                 ds_ctl0 = ads->ds_ctl0;
7942
7943                 if (flags & ATH9K_TXDESC_RTSENA) {
7944                         ds_ctl0 &= ~AR_CTSEnable;
7945                         ds_ctl0 |= AR_RTSEnable;
7946                 } else {
7947                         ds_ctl0 &= ~AR_RTSEnable;
7948                         ds_ctl0 |= AR_CTSEnable;
7949                 }
7950
7951                 ads->ds_ctl0 = ds_ctl0;
7952         } else {
7953                 ads->ds_ctl0 =
7954                         (ads->ds_ctl0 & ~(AR_RTSEnable | AR_CTSEnable));
7955         }
7956
7957         ads->ds_ctl2 = set11nTries(series, 0)
7958                 | set11nTries(series, 1)
7959                 | set11nTries(series, 2)
7960                 | set11nTries(series, 3)
7961                 | (durUpdateEn ? AR_DurUpdateEna : 0)
7962                 | SM(0, AR_BurstDur);
7963
7964         ads->ds_ctl3 = set11nRate(series, 0)
7965                 | set11nRate(series, 1)
7966                 | set11nRate(series, 2)
7967                 | set11nRate(series, 3);
7968
7969         ads->ds_ctl4 = set11nPktDurRTSCTS(series, 0)
7970                 | set11nPktDurRTSCTS(series, 1);
7971
7972         ads->ds_ctl5 = set11nPktDurRTSCTS(series, 2)
7973                 | set11nPktDurRTSCTS(series, 3);
7974
7975         ads->ds_ctl7 = set11nRateFlags(series, 0)
7976                 | set11nRateFlags(series, 1)
7977                 | set11nRateFlags(series, 2)
7978                 | set11nRateFlags(series, 3)
7979                 | SM(rtsctsRate, AR_RTSCTSRate);
7980         last_ads->ds_ctl2 = ads->ds_ctl2;
7981         last_ads->ds_ctl3 = ads->ds_ctl3;
7982 }
7983
7984 void
7985 ath9k_hw_set11n_aggr_first(struct ath_hal *ah, struct ath_desc *ds,
7986                            u32 aggrLen)
7987 {
7988         struct ar5416_desc *ads = AR5416DESC(ds);
7989
7990         ads->ds_ctl1 |= (AR_IsAggr | AR_MoreAggr);
7991
7992         ads->ds_ctl6 &= ~AR_AggrLen;
7993         ads->ds_ctl6 |= SM(aggrLen, AR_AggrLen);
7994 }
7995
7996 void
7997 ath9k_hw_set11n_aggr_middle(struct ath_hal *ah, struct ath_desc *ds,
7998                             u32 numDelims)
7999 {
8000         struct ar5416_desc *ads = AR5416DESC(ds);
8001         unsigned int ctl6;
8002
8003         ads->ds_ctl1 |= (AR_IsAggr | AR_MoreAggr);
8004
8005         ctl6 = ads->ds_ctl6;
8006         ctl6 &= ~AR_PadDelim;
8007         ctl6 |= SM(numDelims, AR_PadDelim);
8008         ads->ds_ctl6 = ctl6;
8009 }
8010
8011 void ath9k_hw_set11n_aggr_last(struct ath_hal *ah, struct ath_desc *ds)
8012 {
8013         struct ar5416_desc *ads = AR5416DESC(ds);
8014
8015         ads->ds_ctl1 |= AR_IsAggr;
8016         ads->ds_ctl1 &= ~AR_MoreAggr;
8017         ads->ds_ctl6 &= ~AR_PadDelim;
8018 }
8019
8020 void ath9k_hw_clr11n_aggr(struct ath_hal *ah, struct ath_desc *ds)
8021 {
8022         struct ar5416_desc *ads = AR5416DESC(ds);
8023
8024         ads->ds_ctl1 &= (~AR_IsAggr & ~AR_MoreAggr);
8025 }
8026
8027 void
8028 ath9k_hw_set11n_burstduration(struct ath_hal *ah, struct ath_desc *ds,
8029                               u32 burstDuration)
8030 {
8031         struct ar5416_desc *ads = AR5416DESC(ds);
8032
8033         ads->ds_ctl2 &= ~AR_BurstDur;
8034         ads->ds_ctl2 |= SM(burstDuration, AR_BurstDur);
8035 }
8036
8037 void
8038 ath9k_hw_set11n_virtualmorefrag(struct ath_hal *ah, struct ath_desc *ds,
8039                                 u32 vmf)
8040 {
8041         struct ar5416_desc *ads = AR5416DESC(ds);
8042
8043         if (vmf)
8044                 ads->ds_ctl0 |= AR_VirtMoreFrag;
8045         else
8046                 ads->ds_ctl0 &= ~AR_VirtMoreFrag;
8047 }
8048
8049 void ath9k_hw_putrxbuf(struct ath_hal *ah, u32 rxdp)
8050 {
8051         REG_WRITE(ah, AR_RXDP, rxdp);
8052 }
8053
8054 void ath9k_hw_rxena(struct ath_hal *ah)
8055 {
8056         REG_WRITE(ah, AR_CR, AR_CR_RXE);
8057 }
8058
8059 bool ath9k_hw_setrxabort(struct ath_hal *ah, bool set)
8060 {
8061         if (set) {
8062
8063                 REG_SET_BIT(ah, AR_DIAG_SW,
8064                             (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
8065
8066                 if (!ath9k_hw_wait
8067                     (ah, AR_OBS_BUS_1, AR_OBS_BUS_1_RX_STATE, 0)) {
8068                         u32 reg;
8069
8070                         REG_CLR_BIT(ah, AR_DIAG_SW,
8071                                     (AR_DIAG_RX_DIS |
8072                                      AR_DIAG_RX_ABORT));
8073
8074                         reg = REG_READ(ah, AR_OBS_BUS_1);
8075                         DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
8076                                 "%s: rx failed to go idle in 10 ms RXSM=0x%x\n",
8077                                 __func__, reg);
8078
8079                         return false;
8080                 }
8081         } else {
8082                 REG_CLR_BIT(ah, AR_DIAG_SW,
8083                             (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
8084         }
8085
8086         return true;
8087 }
8088
8089 void
8090 ath9k_hw_setmcastfilter(struct ath_hal *ah, u32 filter0,
8091                         u32 filter1)
8092 {
8093         REG_WRITE(ah, AR_MCAST_FIL0, filter0);
8094         REG_WRITE(ah, AR_MCAST_FIL1, filter1);
8095 }
8096
8097 bool
8098 ath9k_hw_setuprxdesc(struct ath_hal *ah, struct ath_desc *ds,
8099                      u32 size, u32 flags)
8100 {
8101         struct ar5416_desc *ads = AR5416DESC(ds);
8102         struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
8103
8104         ads->ds_ctl1 = size & AR_BufLen;
8105         if (flags & ATH9K_RXDESC_INTREQ)
8106                 ads->ds_ctl1 |= AR_RxIntrReq;
8107
8108         ads->ds_rxstatus8 &= ~AR_RxDone;
8109         if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
8110                 memset(&(ads->u), 0, sizeof(ads->u));
8111         return true;
8112 }
8113
8114 int
8115 ath9k_hw_rxprocdesc(struct ath_hal *ah, struct ath_desc *ds,
8116                     u32 pa, struct ath_desc *nds, u64 tsf)
8117 {
8118         struct ar5416_desc ads;
8119         struct ar5416_desc *adsp = AR5416DESC(ds);
8120
8121         if ((adsp->ds_rxstatus8 & AR_RxDone) == 0)
8122                 return -EINPROGRESS;
8123
8124         ads.u.rx = adsp->u.rx;
8125
8126         ds->ds_rxstat.rs_status = 0;
8127         ds->ds_rxstat.rs_flags = 0;
8128
8129         ds->ds_rxstat.rs_datalen = ads.ds_rxstatus1 & AR_DataLen;
8130         ds->ds_rxstat.rs_tstamp = ads.AR_RcvTimestamp;
8131
8132         ds->ds_rxstat.rs_rssi = MS(ads.ds_rxstatus4, AR_RxRSSICombined);
8133         ds->ds_rxstat.rs_rssi_ctl0 = MS(ads.ds_rxstatus0, AR_RxRSSIAnt00);
8134         ds->ds_rxstat.rs_rssi_ctl1 = MS(ads.ds_rxstatus0, AR_RxRSSIAnt01);
8135         ds->ds_rxstat.rs_rssi_ctl2 = MS(ads.ds_rxstatus0, AR_RxRSSIAnt02);
8136         ds->ds_rxstat.rs_rssi_ext0 = MS(ads.ds_rxstatus4, AR_RxRSSIAnt10);
8137         ds->ds_rxstat.rs_rssi_ext1 = MS(ads.ds_rxstatus4, AR_RxRSSIAnt11);
8138         ds->ds_rxstat.rs_rssi_ext2 = MS(ads.ds_rxstatus4, AR_RxRSSIAnt12);
8139         if (ads.ds_rxstatus8 & AR_RxKeyIdxValid)
8140                 ds->ds_rxstat.rs_keyix = MS(ads.ds_rxstatus8, AR_KeyIdx);
8141         else
8142                 ds->ds_rxstat.rs_keyix = ATH9K_RXKEYIX_INVALID;
8143
8144         ds->ds_rxstat.rs_rate = RXSTATUS_RATE(ah, (&ads));
8145         ds->ds_rxstat.rs_more = (ads.ds_rxstatus1 & AR_RxMore) ? 1 : 0;
8146
8147         ds->ds_rxstat.rs_isaggr = (ads.ds_rxstatus8 & AR_RxAggr) ? 1 : 0;
8148         ds->ds_rxstat.rs_moreaggr =
8149                 (ads.ds_rxstatus8 & AR_RxMoreAggr) ? 1 : 0;
8150         ds->ds_rxstat.rs_antenna = MS(ads.ds_rxstatus3, AR_RxAntenna);
8151         ds->ds_rxstat.rs_flags =
8152                 (ads.ds_rxstatus3 & AR_GI) ? ATH9K_RX_GI : 0;
8153         ds->ds_rxstat.rs_flags |=
8154                 (ads.ds_rxstatus3 & AR_2040) ? ATH9K_RX_2040 : 0;
8155
8156         if (ads.ds_rxstatus8 & AR_PreDelimCRCErr)
8157                 ds->ds_rxstat.rs_flags |= ATH9K_RX_DELIM_CRC_PRE;
8158         if (ads.ds_rxstatus8 & AR_PostDelimCRCErr)
8159                 ds->ds_rxstat.rs_flags |= ATH9K_RX_DELIM_CRC_POST;
8160         if (ads.ds_rxstatus8 & AR_DecryptBusyErr)
8161                 ds->ds_rxstat.rs_flags |= ATH9K_RX_DECRYPT_BUSY;
8162
8163         if ((ads.ds_rxstatus8 & AR_RxFrameOK) == 0) {
8164
8165                 if (ads.ds_rxstatus8 & AR_CRCErr)
8166                         ds->ds_rxstat.rs_status |= ATH9K_RXERR_CRC;
8167                 else if (ads.ds_rxstatus8 & AR_PHYErr) {
8168                         u32 phyerr;
8169
8170                         ds->ds_rxstat.rs_status |= ATH9K_RXERR_PHY;
8171                         phyerr = MS(ads.ds_rxstatus8, AR_PHYErrCode);
8172                         ds->ds_rxstat.rs_phyerr = phyerr;
8173                 } else if (ads.ds_rxstatus8 & AR_DecryptCRCErr)
8174                         ds->ds_rxstat.rs_status |= ATH9K_RXERR_DECRYPT;
8175                 else if (ads.ds_rxstatus8 & AR_MichaelErr)
8176                         ds->ds_rxstat.rs_status |= ATH9K_RXERR_MIC;
8177         }
8178
8179         return 0;
8180 }
8181
8182 static void ath9k_hw_setup_rate_table(struct ath_hal *ah,
8183                                       struct ath9k_rate_table *rt)
8184 {
8185         int i;
8186
8187         if (rt->rateCodeToIndex[0] != 0)
8188                 return;
8189         for (i = 0; i < 256; i++)
8190                 rt->rateCodeToIndex[i] = (u8) -1;
8191         for (i = 0; i < rt->rateCount; i++) {
8192                 u8 code = rt->info[i].rateCode;
8193                 u8 cix = rt->info[i].controlRate;
8194
8195                 rt->rateCodeToIndex[code] = i;
8196                 rt->rateCodeToIndex[code | rt->info[i].shortPreamble] = i;
8197
8198                 rt->info[i].lpAckDuration =
8199                         ath9k_hw_computetxtime(ah, rt,
8200                                                WLAN_CTRL_FRAME_SIZE,
8201                                                cix,
8202                                                false);
8203                 rt->info[i].spAckDuration =
8204                         ath9k_hw_computetxtime(ah, rt,
8205                                                WLAN_CTRL_FRAME_SIZE,
8206                                                cix,
8207                                                true);
8208         }
8209 }
8210
8211 const struct ath9k_rate_table *ath9k_hw_getratetable(struct ath_hal *ah,
8212                                                    u32 mode)
8213 {
8214         struct ath9k_rate_table *rt;
8215         switch (mode) {
8216         case ATH9K_MODE_11A:
8217                 rt = &ar5416_11a_table;
8218                 break;
8219         case ATH9K_MODE_11B:
8220                 rt = &ar5416_11b_table;
8221                 break;
8222         case ATH9K_MODE_11G:
8223                 rt = &ar5416_11g_table;
8224                 break;
8225         case ATH9K_MODE_11NG_HT20:
8226         case ATH9K_MODE_11NG_HT40PLUS:
8227         case ATH9K_MODE_11NG_HT40MINUS:
8228                 rt = &ar5416_11ng_table;
8229                 break;
8230         case ATH9K_MODE_11NA_HT20:
8231         case ATH9K_MODE_11NA_HT40PLUS:
8232         case ATH9K_MODE_11NA_HT40MINUS:
8233                 rt = &ar5416_11na_table;
8234                 break;
8235         default:
8236                 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL, "%s: invalid mode 0x%x\n",
8237                          __func__, mode);
8238                 return NULL;
8239         }
8240         ath9k_hw_setup_rate_table(ah, rt);
8241         return rt;
8242 }
8243
8244 static const char *ath9k_hw_devname(u16 devid)
8245 {
8246         switch (devid) {
8247         case AR5416_DEVID_PCI:
8248         case AR5416_DEVID_PCIE:
8249                 return "Atheros 5416";
8250         case AR9160_DEVID_PCI:
8251                 return "Atheros 9160";
8252         case AR9280_DEVID_PCI:
8253         case AR9280_DEVID_PCIE:
8254                 return "Atheros 9280";
8255         }
8256         return NULL;
8257 }
8258
8259 const char *ath9k_hw_probe(u16 vendorid, u16 devid)
8260 {
8261         return vendorid == ATHEROS_VENDOR_ID ?
8262                 ath9k_hw_devname(devid) : NULL;
8263 }
8264
8265 struct ath_hal *ath9k_hw_attach(u16 devid,
8266                                 struct ath_softc *sc,
8267                                 void __iomem *mem,
8268                                 int *error)
8269 {
8270         struct ath_hal *ah = NULL;
8271
8272         switch (devid) {
8273         case AR5416_DEVID_PCI:
8274         case AR5416_DEVID_PCIE:
8275         case AR9160_DEVID_PCI:
8276         case AR9280_DEVID_PCI:
8277         case AR9280_DEVID_PCIE:
8278                 ah = ath9k_hw_do_attach(devid, sc, mem, error);
8279                 break;
8280         default:
8281                 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
8282                          "devid=0x%x not supported.\n", devid);
8283                 ah = NULL;
8284                 *error = -ENXIO;
8285                 break;
8286         }
8287
8288         return ah;
8289 }
8290
8291 u16
8292 ath9k_hw_computetxtime(struct ath_hal *ah,
8293                        const struct ath9k_rate_table *rates,
8294                        u32 frameLen, u16 rateix,
8295                        bool shortPreamble)
8296 {
8297         u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
8298         u32 kbps;
8299
8300         kbps = rates->info[rateix].rateKbps;
8301
8302         if (kbps == 0)
8303                 return 0;
8304         switch (rates->info[rateix].phy) {
8305
8306         case PHY_CCK:
8307                 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
8308                 if (shortPreamble && rates->info[rateix].shortPreamble)
8309                         phyTime >>= 1;
8310                 numBits = frameLen << 3;
8311                 txTime = CCK_SIFS_TIME + phyTime
8312                         + ((numBits * 1000) / kbps);
8313                 break;
8314         case PHY_OFDM:
8315                 if (ah->ah_curchan && IS_CHAN_QUARTER_RATE(ah->ah_curchan)) {
8316                         bitsPerSymbol =
8317                                 (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
8318
8319                         numBits = OFDM_PLCP_BITS + (frameLen << 3);
8320                         numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
8321                         txTime = OFDM_SIFS_TIME_QUARTER
8322                                 + OFDM_PREAMBLE_TIME_QUARTER
8323                                 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
8324                 } else if (ah->ah_curchan &&
8325                            IS_CHAN_HALF_RATE(ah->ah_curchan)) {
8326                         bitsPerSymbol =
8327                                 (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
8328
8329                         numBits = OFDM_PLCP_BITS + (frameLen << 3);
8330                         numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
8331                         txTime = OFDM_SIFS_TIME_HALF +
8332                                 OFDM_PREAMBLE_TIME_HALF
8333                                 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
8334                 } else {
8335                         bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
8336
8337                         numBits = OFDM_PLCP_BITS + (frameLen << 3);
8338                         numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
8339                         txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
8340                                 + (numSymbols * OFDM_SYMBOL_TIME);
8341                 }
8342                 break;
8343
8344         default:
8345                 DPRINTF(ah->ah_sc, ATH_DBG_PHY_IO,
8346                          "%s: unknown phy %u (rate ix %u)\n", __func__,
8347                          rates->info[rateix].phy, rateix);
8348                 txTime = 0;
8349                 break;
8350         }
8351         return txTime;
8352 }
8353
8354 u32 ath9k_hw_mhz2ieee(struct ath_hal *ah, u32 freq, u32 flags)
8355 {
8356         if (flags & CHANNEL_2GHZ) {
8357                 if (freq == 2484)
8358                         return 14;
8359                 if (freq < 2484)
8360                         return (freq - 2407) / 5;
8361                 else
8362                         return 15 + ((freq - 2512) / 20);
8363         } else if (flags & CHANNEL_5GHZ) {
8364                 if (ath9k_regd_is_public_safety_sku(ah) &&
8365                     IS_CHAN_IN_PUBLIC_SAFETY_BAND(freq)) {
8366                         return ((freq * 10) +
8367                                 (((freq % 5) == 2) ? 5 : 0) - 49400) / 5;
8368                 } else if ((flags & CHANNEL_A) && (freq <= 5000)) {
8369                         return (freq - 4000) / 5;
8370                 } else {
8371                         return (freq - 5000) / 5;
8372                 }
8373         } else {
8374                 if (freq == 2484)
8375                         return 14;
8376                 if (freq < 2484)
8377                         return (freq - 2407) / 5;
8378                 if (freq < 5000) {
8379                         if (ath9k_regd_is_public_safety_sku(ah)
8380                             && IS_CHAN_IN_PUBLIC_SAFETY_BAND(freq)) {
8381                                 return ((freq * 10) +
8382                                         (((freq % 5) ==
8383                                           2) ? 5 : 0) - 49400) / 5;
8384                         } else if (freq > 4900) {
8385                                 return (freq - 4000) / 5;
8386                         } else {
8387                                 return 15 + ((freq - 2512) / 20);
8388                         }
8389                 }
8390                 return (freq - 5000) / 5;
8391         }
8392 }
8393
8394 int16_t
8395 ath9k_hw_getchan_noise(struct ath_hal *ah, struct ath9k_channel *chan)
8396 {
8397         struct ath9k_channel *ichan;
8398
8399         ichan = ath9k_regd_check_channel(ah, chan);
8400         if (ichan == NULL) {
8401                 DPRINTF(ah->ah_sc, ATH_DBG_NF_CAL,
8402                          "%s: invalid channel %u/0x%x; no mapping\n",
8403                          __func__, chan->channel, chan->channelFlags);
8404                 return 0;
8405         }
8406         if (ichan->rawNoiseFloor == 0) {
8407                 enum wireless_mode mode = ath9k_hw_chan2wmode(ah, chan);
8408                 return NOISE_FLOOR[mode];
8409         } else
8410                 return ichan->rawNoiseFloor;
8411 }
8412
8413 bool ath9k_hw_set_tsfadjust(struct ath_hal *ah, u32 setting)
8414 {
8415         struct ath_hal_5416 *ahp = AH5416(ah);
8416
8417         if (setting)
8418                 ahp->ah_miscMode |= AR_PCU_TX_ADD_TSF;
8419         else
8420                 ahp->ah_miscMode &= ~AR_PCU_TX_ADD_TSF;
8421         return true;
8422 }
8423
8424 bool ath9k_hw_phycounters(struct ath_hal *ah)
8425 {
8426         struct ath_hal_5416 *ahp = AH5416(ah);
8427
8428         return ahp->ah_hasHwPhyCounters ? true : false;
8429 }
8430
8431 u32 ath9k_hw_gettxbuf(struct ath_hal *ah, u32 q)
8432 {
8433         return REG_READ(ah, AR_QTXDP(q));
8434 }
8435
8436 bool ath9k_hw_puttxbuf(struct ath_hal *ah, u32 q,
8437                        u32 txdp)
8438 {
8439         REG_WRITE(ah, AR_QTXDP(q), txdp);
8440
8441         return true;
8442 }
8443
8444 bool ath9k_hw_txstart(struct ath_hal *ah, u32 q)
8445 {
8446         DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: queue %u\n", __func__, q);
8447
8448         REG_WRITE(ah, AR_Q_TXE, 1 << q);
8449
8450         return true;
8451 }
8452
8453 u32 ath9k_hw_numtxpending(struct ath_hal *ah, u32 q)
8454 {
8455         u32 npend;
8456
8457         npend = REG_READ(ah, AR_QSTS(q)) & AR_Q_STS_PEND_FR_CNT;
8458         if (npend == 0) {
8459
8460                 if (REG_READ(ah, AR_Q_TXE) & (1 << q))
8461                         npend = 1;
8462         }
8463         return npend;
8464 }
8465
8466 bool ath9k_hw_stoptxdma(struct ath_hal *ah, u32 q)
8467 {
8468         u32 wait;
8469
8470         REG_WRITE(ah, AR_Q_TXD, 1 << q);
8471
8472         for (wait = 1000; wait != 0; wait--) {
8473                 if (ath9k_hw_numtxpending(ah, q) == 0)
8474                         break;
8475                 udelay(100);
8476         }
8477
8478         if (ath9k_hw_numtxpending(ah, q)) {
8479                 u32 tsfLow, j;
8480
8481                 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE,
8482                          "%s: Num of pending TX Frames %d on Q %d\n",
8483                          __func__, ath9k_hw_numtxpending(ah, q), q);
8484
8485                 for (j = 0; j < 2; j++) {
8486                         tsfLow = REG_READ(ah, AR_TSF_L32);
8487                         REG_WRITE(ah, AR_QUIET2,
8488                                   SM(10, AR_QUIET2_QUIET_DUR));
8489                         REG_WRITE(ah, AR_QUIET_PERIOD, 100);
8490                         REG_WRITE(ah, AR_NEXT_QUIET_TIMER, tsfLow >> 10);
8491                         REG_SET_BIT(ah, AR_TIMER_MODE,
8492                                        AR_QUIET_TIMER_EN);
8493
8494                         if ((REG_READ(ah, AR_TSF_L32) >> 10) ==
8495                             (tsfLow >> 10)) {
8496                                 break;
8497                         }
8498                         DPRINTF(ah->ah_sc, ATH_DBG_QUEUE,
8499                                 "%s: TSF have moved while trying to set "
8500                                 "quiet time TSF: 0x%08x\n",
8501                                 __func__, tsfLow);
8502                 }
8503
8504                 REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH);
8505
8506                 udelay(200);
8507                 REG_CLR_BIT(ah, AR_TIMER_MODE, AR_QUIET_TIMER_EN);
8508
8509                 wait = 1000;
8510
8511                 while (ath9k_hw_numtxpending(ah, q)) {
8512                         if ((--wait) == 0) {
8513                                 DPRINTF(ah->ah_sc, ATH_DBG_XMIT,
8514                                         "%s: Failed to stop Tx DMA in 100 "
8515                                         "msec after killing last frame\n",
8516                                         __func__);
8517                                 break;
8518                         }
8519                         udelay(100);
8520                 }
8521
8522                 REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH);
8523         }
8524
8525         REG_WRITE(ah, AR_Q_TXD, 0);
8526         return wait != 0;
8527 }