drivers/net/wireless/b43/main.c

   1 /*
   2
   3   Broadcom B43 wireless driver
   4
   5   Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>
   6   Copyright (c) 2005 Stefano Brivio <stefano.brivio@polimi.it>
   7   Copyright (c) 2005, 2006 Michael Buesch <mb@bu3sch.de>
   8   Copyright (c) 2005 Danny van Dyk <kugelfang@gentoo.org>
   9   Copyright (c) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch>
  10
  11   Some parts of the code in this file are derived from the ipw2200
  12   driver  Copyright(c) 2003 - 2004 Intel Corporation.
  13
  14   This program is free software; you can redistribute it and/or modify
  15   it under the terms of the GNU General Public License as published by
  16   the Free Software Foundation; either version 2 of the License, or
  17   (at your option) any later version.
  18
  19   This program is distributed in the hope that it will be useful,
  20   but WITHOUT ANY WARRANTY; without even the implied warranty of
  21   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  22   GNU General Public License for more details.
  23
  24   You should have received a copy of the GNU General Public License
  25   along with this program; see the file COPYING.  If not, write to
  26   the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
  27   Boston, MA 02110-1301, USA.
  28
  29 */
  30
  31 #include <linux/delay.h>
  32 #include <linux/init.h>
  33 #include <linux/moduleparam.h>
  34 #include <linux/if_arp.h>
  35 #include <linux/etherdevice.h>
  36 #include <linux/version.h>
  37 #include <linux/firmware.h>
  38 #include <linux/wireless.h>
  39 #include <linux/workqueue.h>
  40 #include <linux/skbuff.h>
  41 #include <linux/io.h>
  42 #include <linux/dma-mapping.h>
  43 #include <asm/unaligned.h>
  44
  45 #include "b43.h"
  46 #include "main.h"
  47 #include "debugfs.h"
  48 #include "phy.h"
  49 #include "dma.h"
  50 #include "sysfs.h"
  51 #include "xmit.h"
  52 #include "lo.h"
  53 #include "pcmcia.h"
  54
  55 MODULE_DESCRIPTION("Broadcom B43 wireless driver");
  56 MODULE_AUTHOR("Martin Langer");
  57 MODULE_AUTHOR("Stefano Brivio");
  58 MODULE_AUTHOR("Michael Buesch");
  59 MODULE_LICENSE("GPL");
  60
  61 MODULE_FIRMWARE(B43_SUPPORTED_FIRMWARE_ID);
  62
  63
  64 static int modparam_bad_frames_preempt;
  65 module_param_named(bad_frames_preempt, modparam_bad_frames_preempt, int, 0444);
  66 MODULE_PARM_DESC(bad_frames_preempt,
  67                  "enable(1) / disable(0) Bad Frames Preemption");
  68
  69 static char modparam_fwpostfix[16];
  70 module_param_string(fwpostfix, modparam_fwpostfix, 16, 0444);
  71 MODULE_PARM_DESC(fwpostfix, "Postfix for the .fw files to load.");
  72
  73 static int modparam_hwpctl;
  74 module_param_named(hwpctl, modparam_hwpctl, int, 0444);
  75 MODULE_PARM_DESC(hwpctl, "Enable hardware-side power control (default off)");
  76
  77 static int modparam_nohwcrypt;
  78 module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
  79 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
  80
  81 static const struct ssb_device_id b43_ssb_tbl[] = {
  82         SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 5),
  83         SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 6),
  84         SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 7),
  85         SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 9),
  86         SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 10),
  87         SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 11),
  88         SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 13),
  89         SSB_DEVTABLE_END
  90 };
  91
  92 MODULE_DEVICE_TABLE(ssb, b43_ssb_tbl);
  93
  94 /* Channel and ratetables are shared for all devices.
  95  * They can't be const, because ieee80211 puts some precalculated
  96  * data in there. This data is the same for all devices, so we don't
  97  * get concurrency issues */
  98 #define RATETAB_ENT(_rateid, _flags) \
  99         {                                                               \
 100                 .bitrate        = B43_RATE_TO_BASE100KBPS(_rateid),     \
 101                 .hw_value       = (_rateid),                            \
 102                 .flags          = (_flags),                             \
 103         }
 104
 105 /*
 106  * NOTE: When changing this, sync with xmit.c's
 107  *       b43_plcp_get_bitrate_idx_* functions!
 108  */
 109 static struct ieee80211_rate __b43_ratetable[] = {
 110         RATETAB_ENT(B43_CCK_RATE_1MB, 0),
 111         RATETAB_ENT(B43_CCK_RATE_2MB, IEEE80211_RATE_SHORT_PREAMBLE),
 112         RATETAB_ENT(B43_CCK_RATE_5MB, IEEE80211_RATE_SHORT_PREAMBLE),
 113         RATETAB_ENT(B43_CCK_RATE_11MB, IEEE80211_RATE_SHORT_PREAMBLE),
 114         RATETAB_ENT(B43_OFDM_RATE_6MB, 0),
 115         RATETAB_ENT(B43_OFDM_RATE_9MB, 0),
 116         RATETAB_ENT(B43_OFDM_RATE_12MB, 0),
 117         RATETAB_ENT(B43_OFDM_RATE_18MB, 0),
 118         RATETAB_ENT(B43_OFDM_RATE_24MB, 0),
 119         RATETAB_ENT(B43_OFDM_RATE_36MB, 0),
 120         RATETAB_ENT(B43_OFDM_RATE_48MB, 0),
 121         RATETAB_ENT(B43_OFDM_RATE_54MB, 0),
 122 };
 123
 124 #define b43_a_ratetable         (__b43_ratetable + 4)
 125 #define b43_a_ratetable_size    8
 126 #define b43_b_ratetable         (__b43_ratetable + 0)
 127 #define b43_b_ratetable_size    4
 128 #define b43_g_ratetable         (__b43_ratetable + 0)
 129 #define b43_g_ratetable_size    12
 130
 131 #define CHANTAB_ENT(_chanid, _freq) \
 132         {                                                       \
 133                 .center_freq    = (_freq),                      \
 134                 .hw_value       = (_chanid),                    \
 135         }
 136 static struct ieee80211_channel b43_2ghz_chantable[] = {
 137         CHANTAB_ENT(1, 2412),
 138         CHANTAB_ENT(2, 2417),
 139         CHANTAB_ENT(3, 2422),
 140         CHANTAB_ENT(4, 2427),
 141         CHANTAB_ENT(5, 2432),
 142         CHANTAB_ENT(6, 2437),
 143         CHANTAB_ENT(7, 2442),
 144         CHANTAB_ENT(8, 2447),
 145         CHANTAB_ENT(9, 2452),
 146         CHANTAB_ENT(10, 2457),
 147         CHANTAB_ENT(11, 2462),
 148         CHANTAB_ENT(12, 2467),
 149         CHANTAB_ENT(13, 2472),
 150         CHANTAB_ENT(14, 2484),
 151 };
 152
 153 #ifdef NOTYET
 154 static struct ieee80211_channel b43_5ghz_chantable[] = {
 155         CHANTAB_ENT(36, 5180),
 156         CHANTAB_ENT(40, 5200),
 157         CHANTAB_ENT(44, 5220),
 158         CHANTAB_ENT(48, 5240),
 159         CHANTAB_ENT(52, 5260),
 160         CHANTAB_ENT(56, 5280),
 161         CHANTAB_ENT(60, 5300),
 162         CHANTAB_ENT(64, 5320),
 163         CHANTAB_ENT(149, 5745),
 164         CHANTAB_ENT(153, 5765),
 165         CHANTAB_ENT(157, 5785),
 166         CHANTAB_ENT(161, 5805),
 167         CHANTAB_ENT(165, 5825),
 168 };
 169
 170 static struct ieee80211_supported_band b43_band_5GHz = {
 171         .channels = b43_5ghz_chantable,
 172         .n_channels = ARRAY_SIZE(b43_5ghz_chantable),
 173         .bitrates = b43_a_ratetable,
 174         .n_bitrates = b43_a_ratetable_size,
 175 };
 176 #endif
 177
 178 static struct ieee80211_supported_band b43_band_2GHz = {
 179         .channels = b43_2ghz_chantable,
 180         .n_channels = ARRAY_SIZE(b43_2ghz_chantable),
 181         .bitrates = b43_g_ratetable,
 182         .n_bitrates = b43_g_ratetable_size,
 183 };
 184
 185 static void b43_wireless_core_exit(struct b43_wldev *dev);
 186 static int b43_wireless_core_init(struct b43_wldev *dev);
 187 static void b43_wireless_core_stop(struct b43_wldev *dev);
 188 static int b43_wireless_core_start(struct b43_wldev *dev);
 189
 190 static int b43_ratelimit(struct b43_wl *wl)
 191 {
 192         if (!wl || !wl->current_dev)
 193                 return 1;
 194         if (b43_status(wl->current_dev) < B43_STAT_STARTED)
 195                 return 1;
 196         /* We are up and running.
 197          * Ratelimit the messages to avoid DoS over the net. */
 198         return net_ratelimit();
 199 }
 200
 201 void b43info(struct b43_wl *wl, const char *fmt, ...)
 202 {
 203         va_list args;
 204
 205         if (!b43_ratelimit(wl))
 206                 return;
 207         va_start(args, fmt);
 208         printk(KERN_INFO "b43-%s: ",
 209                (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
 210         vprintk(fmt, args);
 211         va_end(args);
 212 }
 213
 214 void b43err(struct b43_wl *wl, const char *fmt, ...)
 215 {
 216         va_list args;
 217
 218         if (!b43_ratelimit(wl))
 219                 return;
 220         va_start(args, fmt);
 221         printk(KERN_ERR "b43-%s ERROR: ",
 222                (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
 223         vprintk(fmt, args);
 224         va_end(args);
 225 }
 226
 227 void b43warn(struct b43_wl *wl, const char *fmt, ...)
 228 {
 229         va_list args;
 230
 231         if (!b43_ratelimit(wl))
 232                 return;
 233         va_start(args, fmt);
 234         printk(KERN_WARNING "b43-%s warning: ",
 235                (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
 236         vprintk(fmt, args);
 237         va_end(args);
 238 }
 239
 240 #if B43_DEBUG
 241 void b43dbg(struct b43_wl *wl, const char *fmt, ...)
 242 {
 243         va_list args;
 244
 245         va_start(args, fmt);
 246         printk(KERN_DEBUG "b43-%s debug: ",
 247                (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
 248         vprintk(fmt, args);
 249         va_end(args);
 250 }
 251 #endif /* DEBUG */
 252
 253 static void b43_ram_write(struct b43_wldev *dev, u16 offset, u32 val)
 254 {
 255         u32 macctl;
 256
 257         B43_WARN_ON(offset % 4 != 0);
 258
 259         macctl = b43_read32(dev, B43_MMIO_MACCTL);
 260         if (macctl & B43_MACCTL_BE)
 261                 val = swab32(val);
 262
 263         b43_write32(dev, B43_MMIO_RAM_CONTROL, offset);
 264         mmiowb();
 265         b43_write32(dev, B43_MMIO_RAM_DATA, val);
 266 }
 267
 268 static inline void b43_shm_control_word(struct b43_wldev *dev,
 269                                         u16 routing, u16 offset)
 270 {
 271         u32 control;
 272
 273         /* "offset" is the WORD offset. */
 274         control = routing;
 275         control <<= 16;
 276         control |= offset;
 277         b43_write32(dev, B43_MMIO_SHM_CONTROL, control);
 278 }
 279
 280 u32 b43_shm_read32(struct b43_wldev *dev, u16 routing, u16 offset)
 281 {
 282         struct b43_wl *wl = dev->wl;
 283         unsigned long flags;
 284         u32 ret;
 285
 286         spin_lock_irqsave(&wl->shm_lock, flags);
 287         if (routing == B43_SHM_SHARED) {
 288                 B43_WARN_ON(offset & 0x0001);
 289                 if (offset & 0x0003) {
 290                         /* Unaligned access */
 291                         b43_shm_control_word(dev, routing, offset >> 2);
 292                         ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
 293                         ret <<= 16;
 294                         b43_shm_control_word(dev, routing, (offset >> 2) + 1);
 295                         ret |= b43_read16(dev, B43_MMIO_SHM_DATA);
 296
 297                         goto out;
 298                 }
 299                 offset >>= 2;
 300         }
 301         b43_shm_control_word(dev, routing, offset);
 302         ret = b43_read32(dev, B43_MMIO_SHM_DATA);
 303 out:
 304         spin_unlock_irqrestore(&wl->shm_lock, flags);
 305
 306         return ret;
 307 }
 308
 309 u16 b43_shm_read16(struct b43_wldev * dev, u16 routing, u16 offset)
 310 {
 311         struct b43_wl *wl = dev->wl;
 312         unsigned long flags;
 313         u16 ret;
 314
 315         spin_lock_irqsave(&wl->shm_lock, flags);
 316         if (routing == B43_SHM_SHARED) {
 317                 B43_WARN_ON(offset & 0x0001);
 318                 if (offset & 0x0003) {
 319                         /* Unaligned access */
 320                         b43_shm_control_word(dev, routing, offset >> 2);
 321                         ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
 322
 323                         goto out;
 324                 }
 325                 offset >>= 2;
 326         }
 327         b43_shm_control_word(dev, routing, offset);
 328         ret = b43_read16(dev, B43_MMIO_SHM_DATA);
 329 out:
 330         spin_unlock_irqrestore(&wl->shm_lock, flags);
 331
 332         return ret;
 333 }
 334
 335 void b43_shm_write32(struct b43_wldev *dev, u16 routing, u16 offset, u32 value)
 336 {
 337         struct b43_wl *wl = dev->wl;
 338         unsigned long flags;
 339
 340         spin_lock_irqsave(&wl->shm_lock, flags);
 341         if (routing == B43_SHM_SHARED) {
 342                 B43_WARN_ON(offset & 0x0001);
 343                 if (offset & 0x0003) {
 344                         /* Unaligned access */
 345                         b43_shm_control_word(dev, routing, offset >> 2);
 346                         b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED,
 347                                     (value >> 16) & 0xffff);
 348                         b43_shm_control_word(dev, routing, (offset >> 2) + 1);
 349                         b43_write16(dev, B43_MMIO_SHM_DATA, value & 0xffff);
 350                         goto out;
 351                 }
 352                 offset >>= 2;
 353         }
 354         b43_shm_control_word(dev, routing, offset);
 355         b43_write32(dev, B43_MMIO_SHM_DATA, value);
 356 out:
 357         spin_unlock_irqrestore(&wl->shm_lock, flags);
 358 }
 359
 360 void b43_shm_write16(struct b43_wldev *dev, u16 routing, u16 offset, u16 value)
 361 {
 362         struct b43_wl *wl = dev->wl;
 363         unsigned long flags;
 364
 365         spin_lock_irqsave(&wl->shm_lock, flags);
 366         if (routing == B43_SHM_SHARED) {
 367                 B43_WARN_ON(offset & 0x0001);
 368                 if (offset & 0x0003) {
 369                         /* Unaligned access */
 370                         b43_shm_control_word(dev, routing, offset >> 2);
 371                         b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED, value);
 372                         goto out;
 373                 }
 374                 offset >>= 2;
 375         }
 376         b43_shm_control_word(dev, routing, offset);
 377         b43_write16(dev, B43_MMIO_SHM_DATA, value);
 378 out:
 379         spin_unlock_irqrestore(&wl->shm_lock, flags);
 380 }
 381
 382 /* Read HostFlags */
 383 u32 b43_hf_read(struct b43_wldev * dev)
 384 {
 385         u32 ret;
 386
 387         ret = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFHI);
 388         ret <<= 16;
 389         ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFLO);
 390
 391         return ret;
 392 }
 393
 394 /* Write HostFlags */
 395 void b43_hf_write(struct b43_wldev *dev, u32 value)
 396 {
 397         b43_shm_write16(dev, B43_SHM_SHARED,
 398                         B43_SHM_SH_HOSTFLO, (value & 0x0000FFFF));
 399         b43_shm_write16(dev, B43_SHM_SHARED,
 400                         B43_SHM_SH_HOSTFHI, ((value & 0xFFFF0000) >> 16));
 401 }
 402
 403 void b43_tsf_read(struct b43_wldev *dev, u64 * tsf)
 404 {
 405         /* We need to be careful. As we read the TSF from multiple
 406          * registers, we should take care of register overflows.
 407          * In theory, the whole tsf read process should be atomic.
 408          * We try to be atomic here, by restaring the read process,
 409          * if any of the high registers changed (overflew).
 410          */
 411         if (dev->dev->id.revision >= 3) {
 412                 u32 low, high, high2;
 413
 414                 do {
 415                         high = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_HIGH);
 416                         low = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_LOW);
 417                         high2 = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_HIGH);
 418                 } while (unlikely(high != high2));
 419
 420                 *tsf = high;
 421                 *tsf <<= 32;
 422                 *tsf |= low;
 423         } else {
 424                 u64 tmp;
 425                 u16 v0, v1, v2, v3;
 426                 u16 test1, test2, test3;
 427
 428                 do {
 429                         v3 = b43_read16(dev, B43_MMIO_TSF_3);
 430                         v2 = b43_read16(dev, B43_MMIO_TSF_2);
 431                         v1 = b43_read16(dev, B43_MMIO_TSF_1);
 432                         v0 = b43_read16(dev, B43_MMIO_TSF_0);
 433
 434                         test3 = b43_read16(dev, B43_MMIO_TSF_3);
 435                         test2 = b43_read16(dev, B43_MMIO_TSF_2);
 436                         test1 = b43_read16(dev, B43_MMIO_TSF_1);
 437                 } while (v3 != test3 || v2 != test2 || v1 != test1);
 438
 439                 *tsf = v3;
 440                 *tsf <<= 48;
 441                 tmp = v2;
 442                 tmp <<= 32;
 443                 *tsf |= tmp;
 444                 tmp = v1;
 445                 tmp <<= 16;
 446                 *tsf |= tmp;
 447                 *tsf |= v0;
 448         }
 449 }
 450
 451 static void b43_time_lock(struct b43_wldev *dev)
 452 {
 453         u32 macctl;
 454
 455         macctl = b43_read32(dev, B43_MMIO_MACCTL);
 456         macctl |= B43_MACCTL_TBTTHOLD;
 457         b43_write32(dev, B43_MMIO_MACCTL, macctl);
 458         /* Commit the write */
 459         b43_read32(dev, B43_MMIO_MACCTL);
 460 }
 461
 462 static void b43_time_unlock(struct b43_wldev *dev)
 463 {
 464         u32 macctl;
 465
 466         macctl = b43_read32(dev, B43_MMIO_MACCTL);
 467         macctl &= ~B43_MACCTL_TBTTHOLD;
 468         b43_write32(dev, B43_MMIO_MACCTL, macctl);
 469         /* Commit the write */
 470         b43_read32(dev, B43_MMIO_MACCTL);
 471 }
 472
 473 static void b43_tsf_write_locked(struct b43_wldev *dev, u64 tsf)
 474 {
 475         /* Be careful with the in-progress timer.
 476          * First zero out the low register, so we have a full
 477          * register-overflow duration to complete the operation.
 478          */
 479         if (dev->dev->id.revision >= 3) {
 480                 u32 lo = (tsf & 0x00000000FFFFFFFFULL);
 481                 u32 hi = (tsf & 0xFFFFFFFF00000000ULL) >> 32;
 482
 483                 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_LOW, 0);
 484                 mmiowb();
 485                 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_HIGH, hi);
 486                 mmiowb();
 487                 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_LOW, lo);
 488         } else {
 489                 u16 v0 = (tsf & 0x000000000000FFFFULL);
 490                 u16 v1 = (tsf & 0x00000000FFFF0000ULL) >> 16;
 491                 u16 v2 = (tsf & 0x0000FFFF00000000ULL) >> 32;
 492                 u16 v3 = (tsf & 0xFFFF000000000000ULL) >> 48;
 493
 494                 b43_write16(dev, B43_MMIO_TSF_0, 0);
 495                 mmiowb();
 496                 b43_write16(dev, B43_MMIO_TSF_3, v3);
 497                 mmiowb();
 498                 b43_write16(dev, B43_MMIO_TSF_2, v2);
 499                 mmiowb();
 500                 b43_write16(dev, B43_MMIO_TSF_1, v1);
 501                 mmiowb();
 502                 b43_write16(dev, B43_MMIO_TSF_0, v0);
 503         }
 504 }
 505
 506 void b43_tsf_write(struct b43_wldev *dev, u64 tsf)
 507 {
 508         b43_time_lock(dev);
 509         b43_tsf_write_locked(dev, tsf);
 510         b43_time_unlock(dev);
 511 }
 512
 513 static
 514 void b43_macfilter_set(struct b43_wldev *dev, u16 offset, const u8 * mac)
 515 {
 516         static const u8 zero_addr[ETH_ALEN] = { 0 };
 517         u16 data;
 518
 519         if (!mac)
 520                 mac = zero_addr;
 521
 522         offset |= 0x0020;
 523         b43_write16(dev, B43_MMIO_MACFILTER_CONTROL, offset);
 524
 525         data = mac[0];
 526         data |= mac[1] << 8;
 527         b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
 528         data = mac[2];
 529         data |= mac[3] << 8;
 530         b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
 531         data = mac[4];
 532         data |= mac[5] << 8;
 533         b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
 534 }
 535
 536 static void b43_write_mac_bssid_templates(struct b43_wldev *dev)
 537 {
 538         const u8 *mac;
 539         const u8 *bssid;
 540         u8 mac_bssid[ETH_ALEN * 2];
 541         int i;
 542         u32 tmp;
 543
 544         bssid = dev->wl->bssid;
 545         mac = dev->wl->mac_addr;
 546
 547         b43_macfilter_set(dev, B43_MACFILTER_BSSID, bssid);
 548
 549         memcpy(mac_bssid, mac, ETH_ALEN);
 550         memcpy(mac_bssid + ETH_ALEN, bssid, ETH_ALEN);
 551
 552         /* Write our MAC address and BSSID to template ram */
 553         for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32)) {
 554                 tmp = (u32) (mac_bssid[i + 0]);
 555                 tmp |= (u32) (mac_bssid[i + 1]) << 8;
 556                 tmp |= (u32) (mac_bssid[i + 2]) << 16;
 557                 tmp |= (u32) (mac_bssid[i + 3]) << 24;
 558                 b43_ram_write(dev, 0x20 + i, tmp);
 559         }
 560 }
 561
 562 static void b43_upload_card_macaddress(struct b43_wldev *dev)
 563 {
 564         b43_write_mac_bssid_templates(dev);
 565         b43_macfilter_set(dev, B43_MACFILTER_SELF, dev->wl->mac_addr);
 566 }
 567
 568 static void b43_set_slot_time(struct b43_wldev *dev, u16 slot_time)
 569 {
 570         /* slot_time is in usec. */
 571         if (dev->phy.type != B43_PHYTYPE_G)
 572                 return;
 573         b43_write16(dev, 0x684, 510 + slot_time);
 574         b43_shm_write16(dev, B43_SHM_SHARED, 0x0010, slot_time);
 575 }
 576
 577 static void b43_short_slot_timing_enable(struct b43_wldev *dev)
 578 {
 579         b43_set_slot_time(dev, 9);
 580         dev->short_slot = 1;
 581 }
 582
 583 static void b43_short_slot_timing_disable(struct b43_wldev *dev)
 584 {
 585         b43_set_slot_time(dev, 20);
 586         dev->short_slot = 0;
 587 }
 588
 589 /* Enable a Generic IRQ. "mask" is the mask of which IRQs to enable.
 590  * Returns the _previously_ enabled IRQ mask.
 591  */
 592 static inline u32 b43_interrupt_enable(struct b43_wldev *dev, u32 mask)
 593 {
 594         u32 old_mask;
 595
 596         old_mask = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
 597         b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, old_mask | mask);
 598
 599         return old_mask;
 600 }
 601
 602 /* Disable a Generic IRQ. "mask" is the mask of which IRQs to disable.
 603  * Returns the _previously_ enabled IRQ mask.
 604  */
 605 static inline u32 b43_interrupt_disable(struct b43_wldev *dev, u32 mask)
 606 {
 607         u32 old_mask;
 608
 609         old_mask = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
 610         b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, old_mask & ~mask);
 611
 612         return old_mask;
 613 }
 614
 615 /* Synchronize IRQ top- and bottom-half.
 616  * IRQs must be masked before calling this.
 617  * This must not be called with the irq_lock held.
 618  */
 619 static void b43_synchronize_irq(struct b43_wldev *dev)
 620 {
 621         synchronize_irq(dev->dev->irq);
 622         tasklet_kill(&dev->isr_tasklet);
 623 }
 624
 625 /* DummyTransmission function, as documented on
 626  * http://bcm-specs.sipsolutions.net/DummyTransmission
 627  */
 628 void b43_dummy_transmission(struct b43_wldev *dev)
 629 {
 630         struct b43_phy *phy = &dev->phy;
 631         unsigned int i, max_loop;
 632         u16 value;
 633         u32 buffer[5] = {
 634                 0x00000000,
 635                 0x00D40000,
 636                 0x00000000,
 637                 0x01000000,
 638                 0x00000000,
 639         };
 640
 641         switch (phy->type) {
 642         case B43_PHYTYPE_A:
 643                 max_loop = 0x1E;
 644                 buffer[0] = 0x000201CC;
 645                 break;
 646         case B43_PHYTYPE_B:
 647         case B43_PHYTYPE_G:
 648                 max_loop = 0xFA;
 649                 buffer[0] = 0x000B846E;
 650                 break;
 651         default:
 652                 B43_WARN_ON(1);
 653                 return;
 654         }
 655
 656         for (i = 0; i < 5; i++)
 657                 b43_ram_write(dev, i * 4, buffer[i]);
 658
 659         /* Commit writes */
 660         b43_read32(dev, B43_MMIO_MACCTL);
 661
 662         b43_write16(dev, 0x0568, 0x0000);
 663         b43_write16(dev, 0x07C0, 0x0000);
 664         value = ((phy->type == B43_PHYTYPE_A) ? 1 : 0);
 665         b43_write16(dev, 0x050C, value);
 666         b43_write16(dev, 0x0508, 0x0000);
 667         b43_write16(dev, 0x050A, 0x0000);
 668         b43_write16(dev, 0x054C, 0x0000);
 669         b43_write16(dev, 0x056A, 0x0014);
 670         b43_write16(dev, 0x0568, 0x0826);
 671         b43_write16(dev, 0x0500, 0x0000);
 672         b43_write16(dev, 0x0502, 0x0030);
 673
 674         if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
 675                 b43_radio_write16(dev, 0x0051, 0x0017);
 676         for (i = 0x00; i < max_loop; i++) {
 677                 value = b43_read16(dev, 0x050E);
 678                 if (value & 0x0080)
 679                         break;
 680                 udelay(10);
 681         }
 682         for (i = 0x00; i < 0x0A; i++) {
 683                 value = b43_read16(dev, 0x050E);
 684                 if (value & 0x0400)
 685                         break;
 686                 udelay(10);
 687         }
 688         for (i = 0x00; i < 0x0A; i++) {
 689                 value = b43_read16(dev, 0x0690);
 690                 if (!(value & 0x0100))
 691                         break;
 692                 udelay(10);
 693         }
 694         if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
 695                 b43_radio_write16(dev, 0x0051, 0x0037);
 696 }
 697
 698 static void key_write(struct b43_wldev *dev,
 699                       u8 index, u8 algorithm, const u8 * key)
 700 {
 701         unsigned int i;
 702         u32 offset;
 703         u16 value;
 704         u16 kidx;
 705
 706         /* Key index/algo block */
 707         kidx = b43_kidx_to_fw(dev, index);
 708         value = ((kidx << 4) | algorithm);
 709         b43_shm_write16(dev, B43_SHM_SHARED,
 710                         B43_SHM_SH_KEYIDXBLOCK + (kidx * 2), value);
 711
 712         /* Write the key to the Key Table Pointer offset */
 713         offset = dev->ktp + (index * B43_SEC_KEYSIZE);
 714         for (i = 0; i < B43_SEC_KEYSIZE; i += 2) {
 715                 value = key[i];
 716                 value |= (u16) (key[i + 1]) << 8;
 717                 b43_shm_write16(dev, B43_SHM_SHARED, offset + i, value);
 718         }
 719 }
 720
 721 static void keymac_write(struct b43_wldev *dev, u8 index, const u8 * addr)
 722 {
 723         u32 addrtmp[2] = { 0, 0, };
 724         u8 per_sta_keys_start = 8;
 725
 726         if (b43_new_kidx_api(dev))
 727                 per_sta_keys_start = 4;
 728
 729         B43_WARN_ON(index < per_sta_keys_start);
 730         /* We have two default TX keys and possibly two default RX keys.
 731          * Physical mac 0 is mapped to physical key 4 or 8, depending
 732          * on the firmware version.
 733          * So we must adjust the index here.
 734          */
 735         index -= per_sta_keys_start;
 736
 737         if (addr) {
 738                 addrtmp[0] = addr[0];
 739                 addrtmp[0] |= ((u32) (addr[1]) << 8);
 740                 addrtmp[0] |= ((u32) (addr[2]) << 16);
 741                 addrtmp[0] |= ((u32) (addr[3]) << 24);
 742                 addrtmp[1] = addr[4];
 743                 addrtmp[1] |= ((u32) (addr[5]) << 8);
 744         }
 745
 746         if (dev->dev->id.revision >= 5) {
 747                 /* Receive match transmitter address mechanism */
 748                 b43_shm_write32(dev, B43_SHM_RCMTA,
 749                                 (index * 2) + 0, addrtmp[0]);
 750                 b43_shm_write16(dev, B43_SHM_RCMTA,
 751                                 (index * 2) + 1, addrtmp[1]);
 752         } else {
 753                 /* RXE (Receive Engine) and
 754                  * PSM (Programmable State Machine) mechanism
 755                  */
 756                 if (index < 8) {
 757                         /* TODO write to RCM 16, 19, 22 and 25 */
 758                 } else {
 759                         b43_shm_write32(dev, B43_SHM_SHARED,
 760                                         B43_SHM_SH_PSM + (index * 6) + 0,
 761                                         addrtmp[0]);
 762                         b43_shm_write16(dev, B43_SHM_SHARED,
 763                                         B43_SHM_SH_PSM + (index * 6) + 4,
 764                                         addrtmp[1]);
 765                 }
 766         }
 767 }
 768
 769 static void do_key_write(struct b43_wldev *dev,
 770                          u8 index, u8 algorithm,
 771                          const u8 * key, size_t key_len, const u8 * mac_addr)
 772 {
 773         u8 buf[B43_SEC_KEYSIZE] = { 0, };
 774         u8 per_sta_keys_start = 8;
 775
 776         if (b43_new_kidx_api(dev))
 777                 per_sta_keys_start = 4;
 778
 779         B43_WARN_ON(index >= dev->max_nr_keys);
 780         B43_WARN_ON(key_len > B43_SEC_KEYSIZE);
 781
 782         if (index >= per_sta_keys_start)
 783                 keymac_write(dev, index, NULL); /* First zero out mac. */
 784         if (key)
 785                 memcpy(buf, key, key_len);
 786         key_write(dev, index, algorithm, buf);
 787         if (index >= per_sta_keys_start)
 788                 keymac_write(dev, index, mac_addr);
 789
 790         dev->key[index].algorithm = algorithm;
 791 }
 792
 793 static int b43_key_write(struct b43_wldev *dev,
 794                          int index, u8 algorithm,
 795                          const u8 * key, size_t key_len,
 796                          const u8 * mac_addr,
 797                          struct ieee80211_key_conf *keyconf)
 798 {
 799         int i;
 800         int sta_keys_start;
 801
 802         if (key_len > B43_SEC_KEYSIZE)
 803                 return -EINVAL;
 804         for (i = 0; i < dev->max_nr_keys; i++) {
 805                 /* Check that we don't already have this key. */
 806                 B43_WARN_ON(dev->key[i].keyconf == keyconf);
 807         }
 808         if (index < 0) {
 809                 /* Either pairwise key or address is 00:00:00:00:00:00
 810                  * for transmit-only keys. Search the index. */
 811                 if (b43_new_kidx_api(dev))
 812                         sta_keys_start = 4;
 813                 else
 814                         sta_keys_start = 8;
 815                 for (i = sta_keys_start; i < dev->max_nr_keys; i++) {
 816                         if (!dev->key[i].keyconf) {
 817                                 /* found empty */
 818                                 index = i;
 819                                 break;
 820                         }
 821                 }
 822                 if (index < 0) {
 823                         b43err(dev->wl, "Out of hardware key memory\n");
 824                         return -ENOSPC;
 825                 }
 826         } else
 827                 B43_WARN_ON(index > 3);
 828
 829         do_key_write(dev, index, algorithm, key, key_len, mac_addr);
 830         if ((index <= 3) && !b43_new_kidx_api(dev)) {
 831                 /* Default RX key */
 832                 B43_WARN_ON(mac_addr);
 833                 do_key_write(dev, index + 4, algorithm, key, key_len, NULL);
 834         }
 835         keyconf->hw_key_idx = index;
 836         dev->key[index].keyconf = keyconf;
 837
 838         return 0;
 839 }
 840
 841 static int b43_key_clear(struct b43_wldev *dev, int index)
 842 {
 843         if (B43_WARN_ON((index < 0) || (index >= dev->max_nr_keys)))
 844                 return -EINVAL;
 845         do_key_write(dev, index, B43_SEC_ALGO_NONE,
 846                      NULL, B43_SEC_KEYSIZE, NULL);
 847         if ((index <= 3) && !b43_new_kidx_api(dev)) {
 848                 do_key_write(dev, index + 4, B43_SEC_ALGO_NONE,
 849                              NULL, B43_SEC_KEYSIZE, NULL);
 850         }
 851         dev->key[index].keyconf = NULL;
 852
 853         return 0;
 854 }
 855
 856 static void b43_clear_keys(struct b43_wldev *dev)
 857 {
 858         int i;
 859
 860         for (i = 0; i < dev->max_nr_keys; i++)
 861                 b43_key_clear(dev, i);
 862 }
 863
 864 void b43_power_saving_ctl_bits(struct b43_wldev *dev, unsigned int ps_flags)
 865 {
 866         u32 macctl;
 867         u16 ucstat;
 868         bool hwps;
 869         bool awake;
 870         int i;
 871
 872         B43_WARN_ON((ps_flags & B43_PS_ENABLED) &&
 873                     (ps_flags & B43_PS_DISABLED));
 874         B43_WARN_ON((ps_flags & B43_PS_AWAKE) && (ps_flags & B43_PS_ASLEEP));
 875
 876         if (ps_flags & B43_PS_ENABLED) {
 877                 hwps = 1;
 878         } else if (ps_flags & B43_PS_DISABLED) {
 879                 hwps = 0;
 880         } else {
 881                 //TODO: If powersave is not off and FIXME is not set and we are not in adhoc
 882                 //      and thus is not an AP and we are associated, set bit 25
 883         }
 884         if (ps_flags & B43_PS_AWAKE) {
 885                 awake = 1;
 886         } else if (ps_flags & B43_PS_ASLEEP) {
 887                 awake = 0;
 888         } else {
 889                 //TODO: If the device is awake or this is an AP, or we are scanning, or FIXME,
 890                 //      or we are associated, or FIXME, or the latest PS-Poll packet sent was
 891                 //      successful, set bit26
 892         }
 893
 894 /* FIXME: For now we force awake-on and hwps-off */
 895         hwps = 0;
 896         awake = 1;
 897
 898         macctl = b43_read32(dev, B43_MMIO_MACCTL);
 899         if (hwps)
 900                 macctl |= B43_MACCTL_HWPS;
 901         else
 902                 macctl &= ~B43_MACCTL_HWPS;
 903         if (awake)
 904                 macctl |= B43_MACCTL_AWAKE;
 905         else
 906                 macctl &= ~B43_MACCTL_AWAKE;
 907         b43_write32(dev, B43_MMIO_MACCTL, macctl);
 908         /* Commit write */
 909         b43_read32(dev, B43_MMIO_MACCTL);
 910         if (awake && dev->dev->id.revision >= 5) {
 911                 /* Wait for the microcode to wake up. */
 912                 for (i = 0; i < 100; i++) {
 913                         ucstat = b43_shm_read16(dev, B43_SHM_SHARED,
 914                                                 B43_SHM_SH_UCODESTAT);
 915                         if (ucstat != B43_SHM_SH_UCODESTAT_SLEEP)
 916                                 break;
 917                         udelay(10);
 918                 }
 919         }
 920 }
 921
 922 /* Turn the Analog ON/OFF */
 923 static void b43_switch_analog(struct b43_wldev *dev, int on)
 924 {
 925         b43_write16(dev, B43_MMIO_PHY0, on ? 0 : 0xF4);
 926 }
 927
 928 void b43_wireless_core_reset(struct b43_wldev *dev, u32 flags)
 929 {
 930         u32 tmslow;
 931         u32 macctl;
 932
 933         flags |= B43_TMSLOW_PHYCLKEN;
 934         flags |= B43_TMSLOW_PHYRESET;
 935         ssb_device_enable(dev->dev, flags);
 936         msleep(2);              /* Wait for the PLL to turn on. */
 937
 938         /* Now take the PHY out of Reset again */
 939         tmslow = ssb_read32(dev->dev, SSB_TMSLOW);
 940         tmslow |= SSB_TMSLOW_FGC;
 941         tmslow &= ~B43_TMSLOW_PHYRESET;
 942         ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
 943         ssb_read32(dev->dev, SSB_TMSLOW);       /* flush */
 944         msleep(1);
 945         tmslow &= ~SSB_TMSLOW_FGC;
 946         ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
 947         ssb_read32(dev->dev, SSB_TMSLOW);       /* flush */
 948         msleep(1);
 949
 950         /* Turn Analog ON */
 951         b43_switch_analog(dev, 1);
 952
 953         macctl = b43_read32(dev, B43_MMIO_MACCTL);
 954         macctl &= ~B43_MACCTL_GMODE;
 955         if (flags & B43_TMSLOW_GMODE)
 956                 macctl |= B43_MACCTL_GMODE;
 957         macctl |= B43_MACCTL_IHR_ENABLED;
 958         b43_write32(dev, B43_MMIO_MACCTL, macctl);
 959 }
 960
 961 static void handle_irq_transmit_status(struct b43_wldev *dev)
 962 {
 963         u32 v0, v1;
 964         u16 tmp;
 965         struct b43_txstatus stat;
 966
 967         while (1) {
 968                 v0 = b43_read32(dev, B43_MMIO_XMITSTAT_0);
 969                 if (!(v0 & 0x00000001))
 970                         break;
 971                 v1 = b43_read32(dev, B43_MMIO_XMITSTAT_1);
 972
 973                 stat.cookie = (v0 >> 16);
 974                 stat.seq = (v1 & 0x0000FFFF);
 975                 stat.phy_stat = ((v1 & 0x00FF0000) >> 16);
 976                 tmp = (v0 & 0x0000FFFF);
 977                 stat.frame_count = ((tmp & 0xF000) >> 12);
 978                 stat.rts_count = ((tmp & 0x0F00) >> 8);
 979                 stat.supp_reason = ((tmp & 0x001C) >> 2);
 980                 stat.pm_indicated = !!(tmp & 0x0080);
 981                 stat.intermediate = !!(tmp & 0x0040);
 982                 stat.for_ampdu = !!(tmp & 0x0020);
 983                 stat.acked = !!(tmp & 0x0002);
 984
 985                 b43_handle_txstatus(dev, &stat);
 986         }
 987 }
 988
 989 static void drain_txstatus_queue(struct b43_wldev *dev)
 990 {
 991         u32 dummy;
 992
 993         if (dev->dev->id.revision < 5)
 994                 return;
 995         /* Read all entries from the microcode TXstatus FIFO
 996          * and throw them away.
 997          */
 998         while (1) {
 999                 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_0);
1000                 if (!(dummy & 0x00000001))
1001                         break;
1002                 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_1);
1003         }
1004 }
1005
1006 static u32 b43_jssi_read(struct b43_wldev *dev)
1007 {
1008         u32 val = 0;
1009
1010         val = b43_shm_read16(dev, B43_SHM_SHARED, 0x08A);
1011         val <<= 16;
1012         val |= b43_shm_read16(dev, B43_SHM_SHARED, 0x088);
1013
1014         return val;
1015 }
1016
1017 static void b43_jssi_write(struct b43_wldev *dev, u32 jssi)
1018 {
1019         b43_shm_write16(dev, B43_SHM_SHARED, 0x088, (jssi & 0x0000FFFF));
1020         b43_shm_write16(dev, B43_SHM_SHARED, 0x08A, (jssi & 0xFFFF0000) >> 16);
1021 }
1022
1023 static void b43_generate_noise_sample(struct b43_wldev *dev)
1024 {
1025         b43_jssi_write(dev, 0x7F7F7F7F);
1026         b43_write32(dev, B43_MMIO_MACCMD,
1027                     b43_read32(dev, B43_MMIO_MACCMD) | B43_MACCMD_BGNOISE);
1028         B43_WARN_ON(dev->noisecalc.channel_at_start != dev->phy.channel);
1029 }
1030
1031 static void b43_calculate_link_quality(struct b43_wldev *dev)
1032 {
1033         /* Top half of Link Quality calculation. */
1034
1035         if (dev->noisecalc.calculation_running)
1036                 return;
1037         dev->noisecalc.channel_at_start = dev->phy.channel;
1038         dev->noisecalc.calculation_running = 1;
1039         dev->noisecalc.nr_samples = 0;
1040
1041         b43_generate_noise_sample(dev);
1042 }
1043
1044 static void handle_irq_noise(struct b43_wldev *dev)
1045 {
1046         struct b43_phy *phy = &dev->phy;
1047         u16 tmp;
1048         u8 noise[4];
1049         u8 i, j;
1050         s32 average;
1051
1052         /* Bottom half of Link Quality calculation. */
1053
1054         B43_WARN_ON(!dev->noisecalc.calculation_running);
1055         if (dev->noisecalc.channel_at_start != phy->channel)
1056                 goto drop_calculation;
1057         *((__le32 *)noise) = cpu_to_le32(b43_jssi_read(dev));
1058         if (noise[0] == 0x7F || noise[1] == 0x7F ||
1059             noise[2] == 0x7F || noise[3] == 0x7F)
1060                 goto generate_new;
1061
1062         /* Get the noise samples. */
1063         B43_WARN_ON(dev->noisecalc.nr_samples >= 8);
1064         i = dev->noisecalc.nr_samples;
1065         noise[0] = limit_value(noise[0], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1066         noise[1] = limit_value(noise[1], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1067         noise[2] = limit_value(noise[2], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1068         noise[3] = limit_value(noise[3], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1069         dev->noisecalc.samples[i][0] = phy->nrssi_lt[noise[0]];
1070         dev->noisecalc.samples[i][1] = phy->nrssi_lt[noise[1]];
1071         dev->noisecalc.samples[i][2] = phy->nrssi_lt[noise[2]];
1072         dev->noisecalc.samples[i][3] = phy->nrssi_lt[noise[3]];
1073         dev->noisecalc.nr_samples++;
1074         if (dev->noisecalc.nr_samples == 8) {
1075                 /* Calculate the Link Quality by the noise samples. */
1076                 average = 0;
1077                 for (i = 0; i < 8; i++) {
1078                         for (j = 0; j < 4; j++)
1079                                 average += dev->noisecalc.samples[i][j];
1080                 }
1081                 average /= (8 * 4);
1082                 average *= 125;
1083                 average += 64;
1084                 average /= 128;
1085                 tmp = b43_shm_read16(dev, B43_SHM_SHARED, 0x40C);
1086                 tmp = (tmp / 128) & 0x1F;
1087                 if (tmp >= 8)
1088                         average += 2;
1089                 else
1090                         average -= 25;
1091                 if (tmp == 8)
1092                         average -= 72;
1093                 else
1094                         average -= 48;
1095
1096                 dev->stats.link_noise = average;
1097               drop_calculation:
1098                 dev->noisecalc.calculation_running = 0;
1099                 return;
1100         }
1101       generate_new:
1102         b43_generate_noise_sample(dev);
1103 }
1104
1105 static void handle_irq_tbtt_indication(struct b43_wldev *dev)
1106 {
1107         if (b43_is_mode(dev->wl, IEEE80211_IF_TYPE_AP)) {
1108                 ///TODO: PS TBTT
1109         } else {
1110                 if (1 /*FIXME: the last PSpoll frame was sent successfully */ )
1111                         b43_power_saving_ctl_bits(dev, 0);
1112         }
1113         if (b43_is_mode(dev->wl, IEEE80211_IF_TYPE_IBSS))
1114                 dev->dfq_valid = 1;
1115 }
1116
1117 static void handle_irq_atim_end(struct b43_wldev *dev)
1118 {
1119         if (dev->dfq_valid) {
1120                 b43_write32(dev, B43_MMIO_MACCMD,
1121                             b43_read32(dev, B43_MMIO_MACCMD)
1122                             | B43_MACCMD_DFQ_VALID);
1123                 dev->dfq_valid = 0;
1124         }
1125 }
1126
1127 static void handle_irq_pmq(struct b43_wldev *dev)
1128 {
1129         u32 tmp;
1130
1131         //TODO: AP mode.
1132
1133         while (1) {
1134                 tmp = b43_read32(dev, B43_MMIO_PS_STATUS);
1135                 if (!(tmp & 0x00000008))
1136                         break;
1137         }
1138         /* 16bit write is odd, but correct. */
1139         b43_write16(dev, B43_MMIO_PS_STATUS, 0x0002);
1140 }
1141
1142 static void b43_write_template_common(struct b43_wldev *dev,
1143                                       const u8 * data, u16 size,
1144                                       u16 ram_offset,
1145                                       u16 shm_size_offset, u8 rate)
1146 {
1147         u32 i, tmp;
1148         struct b43_plcp_hdr4 plcp;
1149
1150         plcp.data = 0;
1151         b43_generate_plcp_hdr(&plcp, size + FCS_LEN, rate);
1152         b43_ram_write(dev, ram_offset, le32_to_cpu(plcp.data));
1153         ram_offset += sizeof(u32);
1154         /* The PLCP is 6 bytes long, but we only wrote 4 bytes, yet.
1155          * So leave the first two bytes of the next write blank.
1156          */
1157         tmp = (u32) (data[0]) << 16;
1158         tmp |= (u32) (data[1]) << 24;
1159         b43_ram_write(dev, ram_offset, tmp);
1160         ram_offset += sizeof(u32);
1161         for (i = 2; i < size; i += sizeof(u32)) {
1162                 tmp = (u32) (data[i + 0]);
1163                 if (i + 1 < size)
1164                         tmp |= (u32) (data[i + 1]) << 8;
1165                 if (i + 2 < size)
1166                         tmp |= (u32) (data[i + 2]) << 16;
1167                 if (i + 3 < size)
1168                         tmp |= (u32) (data[i + 3]) << 24;
1169                 b43_ram_write(dev, ram_offset + i - 2, tmp);
1170         }
1171         b43_shm_write16(dev, B43_SHM_SHARED, shm_size_offset,
1172                         size + sizeof(struct b43_plcp_hdr6));
1173 }
1174
1175 static void b43_write_beacon_template(struct b43_wldev *dev,
1176                                       u16 ram_offset,
1177                                       u16 shm_size_offset, u8 rate)
1178 {
1179         unsigned int i, len, variable_len;
1180         const struct ieee80211_mgmt *bcn;
1181         const u8 *ie;
1182         bool tim_found = 0;
1183
1184         bcn = (const struct ieee80211_mgmt *)(dev->wl->current_beacon->data);
1185         len = min((size_t) dev->wl->current_beacon->len,
1186                   0x200 - sizeof(struct b43_plcp_hdr6));
1187
1188         b43_write_template_common(dev, (const u8 *)bcn,
1189                                   len, ram_offset, shm_size_offset, rate);
1190
1191         /* Find the position of the TIM and the DTIM_period value
1192          * and write them to SHM. */
1193         ie = bcn->u.beacon.variable;
1194         variable_len = len - offsetof(struct ieee80211_mgmt, u.beacon.variable);
1195         for (i = 0; i < variable_len - 2; ) {
1196                 uint8_t ie_id, ie_len;
1197
1198                 ie_id = ie[i];
1199                 ie_len = ie[i + 1];
1200                 if (ie_id == 5) {
1201                         u16 tim_position;
1202                         u16 dtim_period;
1203                         /* This is the TIM Information Element */
1204
1205                         /* Check whether the ie_len is in the beacon data range. */
1206                         if (variable_len < ie_len + 2 + i)
1207                                 break;
1208                         /* A valid TIM is at least 4 bytes long. */
1209                         if (ie_len < 4)
1210                                 break;
1211                         tim_found = 1;
1212
1213                         tim_position = sizeof(struct b43_plcp_hdr6);
1214                         tim_position += offsetof(struct ieee80211_mgmt, u.beacon.variable);
1215                         tim_position += i;
1216
1217                         dtim_period = ie[i + 3];
1218
1219                         b43_shm_write16(dev, B43_SHM_SHARED,
1220                                         B43_SHM_SH_TIMBPOS, tim_position);
1221                         b43_shm_write16(dev, B43_SHM_SHARED,
1222                                         B43_SHM_SH_DTIMPER, dtim_period);
1223                         break;
1224                 }
1225                 i += ie_len + 2;
1226         }
1227         if (!tim_found) {
1228                 b43warn(dev->wl, "Did not find a valid TIM IE in "
1229                         "the beacon template packet. AP or IBSS operation "
1230                         "may be broken.\n");
1231         }
1232 }
1233
1234 static void b43_write_probe_resp_plcp(struct b43_wldev *dev,
1235                                       u16 shm_offset, u16 size,
1236                                       struct ieee80211_rate *rate)
1237 {
1238         struct b43_plcp_hdr4 plcp;
1239         u32 tmp;
1240         __le16 dur;
1241
1242         plcp.data = 0;
1243         b43_generate_plcp_hdr(&plcp, size + FCS_LEN, rate->hw_value);
1244         dur = ieee80211_generic_frame_duration(dev->wl->hw,
1245                                                dev->wl->vif, size,
1246                                                rate);
1247         /* Write PLCP in two parts and timing for packet transfer */
1248         tmp = le32_to_cpu(plcp.data);
1249         b43_shm_write16(dev, B43_SHM_SHARED, shm_offset, tmp & 0xFFFF);
1250         b43_shm_write16(dev, B43_SHM_SHARED, shm_offset + 2, tmp >> 16);
1251         b43_shm_write16(dev, B43_SHM_SHARED, shm_offset + 6, le16_to_cpu(dur));
1252 }
1253
1254 /* Instead of using custom probe response template, this function
1255  * just patches custom beacon template by:
1256  * 1) Changing packet type
1257  * 2) Patching duration field
1258  * 3) Stripping TIM
1259  */
1260 static const u8 * b43_generate_probe_resp(struct b43_wldev *dev,
1261                                           u16 *dest_size,
1262                                           struct ieee80211_rate *rate)
1263 {
1264         const u8 *src_data;
1265         u8 *dest_data;
1266         u16 src_size, elem_size, src_pos, dest_pos;
1267         __le16 dur;
1268         struct ieee80211_hdr *hdr;
1269         size_t ie_start;
1270
1271         src_size = dev->wl->current_beacon->len;
1272         src_data = (const u8 *)dev->wl->current_beacon->data;
1273
1274         /* Get the start offset of the variable IEs in the packet. */
1275         ie_start = offsetof(struct ieee80211_mgmt, u.probe_resp.variable);
1276         B43_WARN_ON(ie_start != offsetof(struct ieee80211_mgmt, u.beacon.variable));
1277
1278         if (B43_WARN_ON(src_size < ie_start))
1279                 return NULL;
1280
1281         dest_data = kmalloc(src_size, GFP_ATOMIC);
1282         if (unlikely(!dest_data))
1283                 return NULL;
1284
1285         /* Copy the static data and all Information Elements, except the TIM. */
1286         memcpy(dest_data, src_data, ie_start);
1287         src_pos = ie_start;
1288         dest_pos = ie_start;
1289         for ( ; src_pos < src_size - 2; src_pos += elem_size) {
1290                 elem_size = src_data[src_pos + 1] + 2;
1291                 if (src_data[src_pos] == 5) {
1292                         /* This is the TIM. */
1293                         continue;
1294                 }
1295                 memcpy(dest_data + dest_pos, src_data + src_pos,
1296                        elem_size);
1297                 dest_pos += elem_size;
1298         }
1299         *dest_size = dest_pos;
1300         hdr = (struct ieee80211_hdr *)dest_data;
1301
1302         /* Set the frame control. */
1303         hdr->frame_control = cpu_to_le16(IEEE80211_FTYPE_MGMT |
1304                                          IEEE80211_STYPE_PROBE_RESP);
1305         dur = ieee80211_generic_frame_duration(dev->wl->hw,
1306                                                dev->wl->vif, *dest_size,
1307                                                rate);
1308         hdr->duration_id = dur;
1309
1310         return dest_data;
1311 }
1312
1313 static void b43_write_probe_resp_template(struct b43_wldev *dev,
1314                                           u16 ram_offset,
1315                                           u16 shm_size_offset,
1316                                           struct ieee80211_rate *rate)
1317 {
1318         const u8 *probe_resp_data;
1319         u16 size;
1320
1321         size = dev->wl->current_beacon->len;
1322         probe_resp_data = b43_generate_probe_resp(dev, &size, rate);
1323         if (unlikely(!probe_resp_data))
1324                 return;
1325
1326         /* Looks like PLCP headers plus packet timings are stored for
1327          * all possible basic rates
1328          */
1329         b43_write_probe_resp_plcp(dev, 0x31A, size, &b43_b_ratetable[0]);
1330         b43_write_probe_resp_plcp(dev, 0x32C, size, &b43_b_ratetable[1]);
1331         b43_write_probe_resp_plcp(dev, 0x33E, size, &b43_b_ratetable[2]);
1332         b43_write_probe_resp_plcp(dev, 0x350, size, &b43_b_ratetable[3]);
1333
1334         size = min((size_t) size, 0x200 - sizeof(struct b43_plcp_hdr6));
1335         b43_write_template_common(dev, probe_resp_data,
1336                                   size, ram_offset, shm_size_offset,
1337                                   rate->hw_value);
1338         kfree(probe_resp_data);
1339 }
1340
1341 /* Asynchronously update the packet templates in template RAM.
1342  * Locking: Requires wl->irq_lock to be locked. */
1343 static void b43_update_templates(struct b43_wl *wl, struct sk_buff *beacon)
1344 {
1345         /* This is the top half of the ansynchronous beacon update.
1346          * The bottom half is the beacon IRQ.
1347          * Beacon update must be asynchronous to avoid sending an
1348          * invalid beacon. This can happen for example, if the firmware
1349          * transmits a beacon while we are updating it. */
1350
1351         if (wl->current_beacon)
1352                 dev_kfree_skb_any(wl->current_beacon);
1353         wl->current_beacon = beacon;
1354         wl->beacon0_uploaded = 0;
1355         wl->beacon1_uploaded = 0;
1356 }
1357
1358 static void b43_set_ssid(struct b43_wldev *dev, const u8 * ssid, u8 ssid_len)
1359 {
1360         u32 tmp;
1361         u16 i, len;
1362
1363         len = min((u16) ssid_len, (u16) 0x100);
1364         for (i = 0; i < len; i += sizeof(u32)) {
1365                 tmp = (u32) (ssid[i + 0]);
1366                 if (i + 1 < len)
1367                         tmp |= (u32) (ssid[i + 1]) << 8;
1368                 if (i + 2 < len)
1369                         tmp |= (u32) (ssid[i + 2]) << 16;
1370                 if (i + 3 < len)
1371                         tmp |= (u32) (ssid[i + 3]) << 24;
1372                 b43_shm_write32(dev, B43_SHM_SHARED, 0x380 + i, tmp);
1373         }
1374         b43_shm_write16(dev, B43_SHM_SHARED, 0x48, len);
1375 }
1376
1377 static void b43_set_beacon_int(struct b43_wldev *dev, u16 beacon_int)
1378 {
1379         b43_time_lock(dev);
1380         if (dev->dev->id.revision >= 3) {
1381                 b43_write32(dev, 0x188, (beacon_int << 16));
1382         } else {
1383                 b43_write16(dev, 0x606, (beacon_int >> 6));
1384                 b43_write16(dev, 0x610, beacon_int);
1385         }
1386         b43_time_unlock(dev);
1387 }
1388
1389 static void handle_irq_beacon(struct b43_wldev *dev)
1390 {
1391         struct b43_wl *wl = dev->wl;
1392         u32 cmd;
1393
1394         if (!b43_is_mode(wl, IEEE80211_IF_TYPE_AP))
1395                 return;
1396
1397         /* This is the bottom half of the asynchronous beacon update. */
1398
1399         cmd = b43_read32(dev, B43_MMIO_MACCMD);
1400         if (!(cmd & B43_MACCMD_BEACON0_VALID)) {
1401                 if (!wl->beacon0_uploaded) {
1402                         b43_write_beacon_template(dev, 0x68, 0x18,
1403                                                   B43_CCK_RATE_1MB);
1404                         b43_write_probe_resp_template(dev, 0x268, 0x4A,
1405                                                       &__b43_ratetable[3]);
1406                         wl->beacon0_uploaded = 1;
1407                 }
1408                 cmd |= B43_MACCMD_BEACON0_VALID;
1409         }
1410         if (!(cmd & B43_MACCMD_BEACON1_VALID)) {
1411                 if (!wl->beacon1_uploaded) {
1412                         b43_write_beacon_template(dev, 0x468, 0x1A,
1413                                                   B43_CCK_RATE_1MB);
1414                         wl->beacon1_uploaded = 1;
1415                 }
1416                 cmd |= B43_MACCMD_BEACON1_VALID;
1417         }
1418         b43_write32(dev, B43_MMIO_MACCMD, cmd);
1419 }
1420
1421 static void handle_irq_ucode_debug(struct b43_wldev *dev)
1422 {
1423         //TODO
1424 }
1425
1426 /* Interrupt handler bottom-half */
1427 static void b43_interrupt_tasklet(struct b43_wldev *dev)
1428 {
1429         u32 reason;
1430         u32 dma_reason[ARRAY_SIZE(dev->dma_reason)];
1431         u32 merged_dma_reason = 0;
1432         int i;
1433         unsigned long flags;
1434
1435         spin_lock_irqsave(&dev->wl->irq_lock, flags);
1436
1437         B43_WARN_ON(b43_status(dev) != B43_STAT_STARTED);
1438
1439         reason = dev->irq_reason;
1440         for (i = 0; i < ARRAY_SIZE(dma_reason); i++) {
1441                 dma_reason[i] = dev->dma_reason[i];
1442                 merged_dma_reason |= dma_reason[i];
1443         }
1444
1445         if (unlikely(reason & B43_IRQ_MAC_TXERR))
1446                 b43err(dev->wl, "MAC transmission error\n");
1447
1448         if (unlikely(reason & B43_IRQ_PHY_TXERR)) {
1449                 b43err(dev->wl, "PHY transmission error\n");
1450                 rmb();
1451                 if (unlikely(atomic_dec_and_test(&dev->phy.txerr_cnt))) {
1452                         atomic_set(&dev->phy.txerr_cnt,
1453                                    B43_PHY_TX_BADNESS_LIMIT);
1454                         b43err(dev->wl, "Too many PHY TX errors, "
1455                                         "restarting the controller\n");
1456                         b43_controller_restart(dev, "PHY TX errors");
1457                 }
1458         }
1459
1460         if (unlikely(merged_dma_reason & (B43_DMAIRQ_FATALMASK |
1461                                           B43_DMAIRQ_NONFATALMASK))) {
1462                 if (merged_dma_reason & B43_DMAIRQ_FATALMASK) {
1463                         b43err(dev->wl, "Fatal DMA error: "
1464                                "0x%08X, 0x%08X, 0x%08X, "
1465                                "0x%08X, 0x%08X, 0x%08X\n",
1466                                dma_reason[0], dma_reason[1],
1467                                dma_reason[2], dma_reason[3],
1468                                dma_reason[4], dma_reason[5]);
1469                         b43_controller_restart(dev, "DMA error");
1470                         mmiowb();
1471                         spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
1472                         return;
1473                 }
1474                 if (merged_dma_reason & B43_DMAIRQ_NONFATALMASK) {
1475                         b43err(dev->wl, "DMA error: "
1476                                "0x%08X, 0x%08X, 0x%08X, "
1477                                "0x%08X, 0x%08X, 0x%08X\n",
1478                                dma_reason[0], dma_reason[1],
1479                                dma_reason[2], dma_reason[3],
1480                                dma_reason[4], dma_reason[5]);
1481                 }
1482         }
1483
1484         if (unlikely(reason & B43_IRQ_UCODE_DEBUG))
1485                 handle_irq_ucode_debug(dev);
1486         if (reason & B43_IRQ_TBTT_INDI)
1487                 handle_irq_tbtt_indication(dev);
1488         if (reason & B43_IRQ_ATIM_END)
1489                 handle_irq_atim_end(dev);
1490         if (reason & B43_IRQ_BEACON)
1491                 handle_irq_beacon(dev);
1492         if (reason & B43_IRQ_PMQ)
1493                 handle_irq_pmq(dev);
1494         if (reason & B43_IRQ_TXFIFO_FLUSH_OK)
1495                 ;/* TODO */
1496         if (reason & B43_IRQ_NOISESAMPLE_OK)
1497                 handle_irq_noise(dev);
1498
1499         /* Check the DMA reason registers for received data. */
1500         if (dma_reason[0] & B43_DMAIRQ_RX_DONE)
1501                 b43_dma_rx(dev->dma.rx_ring0);
1502         if (dma_reason[3] & B43_DMAIRQ_RX_DONE)
1503                 b43_dma_rx(dev->dma.rx_ring3);
1504         B43_WARN_ON(dma_reason[1] & B43_DMAIRQ_RX_DONE);
1505         B43_WARN_ON(dma_reason[2] & B43_DMAIRQ_RX_DONE);
1506         B43_WARN_ON(dma_reason[4] & B43_DMAIRQ_RX_DONE);
1507         B43_WARN_ON(dma_reason[5] & B43_DMAIRQ_RX_DONE);
1508
1509         if (reason & B43_IRQ_TX_OK)
1510                 handle_irq_transmit_status(dev);
1511
1512         b43_interrupt_enable(dev, dev->irq_savedstate);
1513         mmiowb();
1514         spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
1515 }
1516
1517 static void b43_interrupt_ack(struct b43_wldev *dev, u32 reason)
1518 {
1519         b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, reason);
1520
1521         b43_write32(dev, B43_MMIO_DMA0_REASON, dev->dma_reason[0]);
1522         b43_write32(dev, B43_MMIO_DMA1_REASON, dev->dma_reason[1]);
1523         b43_write32(dev, B43_MMIO_DMA2_REASON, dev->dma_reason[2]);
1524         b43_write32(dev, B43_MMIO_DMA3_REASON, dev->dma_reason[3]);
1525         b43_write32(dev, B43_MMIO_DMA4_REASON, dev->dma_reason[4]);
1526         b43_write32(dev, B43_MMIO_DMA5_REASON, dev->dma_reason[5]);
1527 }
1528
1529 /* Interrupt handler top-half */
1530 static irqreturn_t b43_interrupt_handler(int irq, void *dev_id)
1531 {
1532         irqreturn_t ret = IRQ_NONE;
1533         struct b43_wldev *dev = dev_id;
1534         u32 reason;
1535
1536         if (!dev)
1537                 return IRQ_NONE;
1538
1539         spin_lock(&dev->wl->irq_lock);
1540
1541         if (b43_status(dev) < B43_STAT_STARTED)
1542                 goto out;
1543         reason = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
1544         if (reason == 0xffffffff)       /* shared IRQ */
1545                 goto out;
1546         ret = IRQ_HANDLED;
1547         reason &= b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
1548         if (!reason)
1549                 goto out;
1550
1551         dev->dma_reason[0] = b43_read32(dev, B43_MMIO_DMA0_REASON)
1552             & 0x0001DC00;
1553         dev->dma_reason[1] = b43_read32(dev, B43_MMIO_DMA1_REASON)
1554             & 0x0000DC00;
1555         dev->dma_reason[2] = b43_read32(dev, B43_MMIO_DMA2_REASON)
1556             & 0x0000DC00;
1557         dev->dma_reason[3] = b43_read32(dev, B43_MMIO_DMA3_REASON)
1558             & 0x0001DC00;
1559         dev->dma_reason[4] = b43_read32(dev, B43_MMIO_DMA4_REASON)
1560             & 0x0000DC00;
1561         dev->dma_reason[5] = b43_read32(dev, B43_MMIO_DMA5_REASON)
1562             & 0x0000DC00;
1563
1564         b43_interrupt_ack(dev, reason);
1565         /* disable all IRQs. They are enabled again in the bottom half. */
1566         dev->irq_savedstate = b43_interrupt_disable(dev, B43_IRQ_ALL);
1567         /* save the reason code and call our bottom half. */
1568         dev->irq_reason = reason;
1569         tasklet_schedule(&dev->isr_tasklet);
1570       out:
1571         mmiowb();
1572         spin_unlock(&dev->wl->irq_lock);
1573
1574         return ret;
1575 }
1576
1577 static void do_release_fw(struct b43_firmware_file *fw)
1578 {
1579         release_firmware(fw->data);
1580         fw->data = NULL;
1581         fw->filename = NULL;
1582 }
1583
1584 static void b43_release_firmware(struct b43_wldev *dev)
1585 {
1586         do_release_fw(&dev->fw.ucode);
1587         do_release_fw(&dev->fw.pcm);
1588         do_release_fw(&dev->fw.initvals);
1589         do_release_fw(&dev->fw.initvals_band);
1590 }
1591
1592 static void b43_print_fw_helptext(struct b43_wl *wl, bool error)
1593 {
1594         const char *text;
1595
1596         text = "You must go to "
1597                "http://linuxwireless.org/en/users/Drivers/b43#devicefirmware "
1598                "and download the latest firmware (version 4).\n";
1599         if (error)
1600                 b43err(wl, text);
1601         else
1602                 b43warn(wl, text);
1603 }
1604
1605 static int do_request_fw(struct b43_wldev *dev,
1606                          const char *name,
1607                          struct b43_firmware_file *fw)
1608 {
1609         char path[sizeof(modparam_fwpostfix) + 32];
1610         const struct firmware *blob;
1611         struct b43_fw_header *hdr;
1612         u32 size;
1613         int err;
1614
1615         if (!name) {
1616                 /* Don't fetch anything. Free possibly cached firmware. */
1617                 do_release_fw(fw);
1618                 return 0;
1619         }
1620         if (fw->filename) {
1621                 if (strcmp(fw->filename, name) == 0)
1622                         return 0; /* Already have this fw. */
1623                 /* Free the cached firmware first. */
1624                 do_release_fw(fw);
1625         }
1626
1627         snprintf(path, ARRAY_SIZE(path),
1628                  "b43%s/%s.fw",
1629                  modparam_fwpostfix, name);
1630         err = request_firmware(&blob, path, dev->dev->dev);
1631         if (err) {
1632                 b43err(dev->wl, "Firmware file \"%s\" not found "
1633                        "or load failed.\n", path);
1634                 return err;
1635         }
1636         if (blob->size < sizeof(struct b43_fw_header))
1637                 goto err_format;
1638         hdr = (struct b43_fw_header *)(blob->data);
1639         switch (hdr->type) {
1640         case B43_FW_TYPE_UCODE:
1641         case B43_FW_TYPE_PCM:
1642                 size = be32_to_cpu(hdr->size);
1643                 if (size != blob->size - sizeof(struct b43_fw_header))
1644                         goto err_format;
1645                 /* fallthrough */
1646         case B43_FW_TYPE_IV:
1647                 if (hdr->ver != 1)
1648                         goto err_format;
1649                 break;
1650         default:
1651                 goto err_format;
1652         }
1653
1654         fw->data = blob;
1655         fw->filename = name;
1656
1657         return 0;
1658
1659 err_format:
1660         b43err(dev->wl, "Firmware file \"%s\" format error.\n", path);
1661         release_firmware(blob);
1662
1663         return -EPROTO;
1664 }
1665
1666 static int b43_request_firmware(struct b43_wldev *dev)
1667 {
1668         struct b43_firmware *fw = &dev->fw;
1669         const u8 rev = dev->dev->id.revision;
1670         const char *filename;
1671         u32 tmshigh;
1672         int err;
1673
1674         /* Get microcode */
1675         tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH);
1676         if ((rev >= 5) && (rev <= 10))
1677                 filename = "ucode5";
1678         else if ((rev >= 11) && (rev <= 12))
1679                 filename = "ucode11";
1680         else if (rev >= 13)
1681                 filename = "ucode13";
1682         else
1683                 goto err_no_ucode;
1684         err = do_request_fw(dev, filename, &fw->ucode);
1685         if (err)
1686                 goto err_load;
1687
1688         /* Get PCM code */
1689         if ((rev >= 5) && (rev <= 10))
1690                 filename = "pcm5";
1691         else if (rev >= 11)
1692                 filename = NULL;
1693         else
1694                 goto err_no_pcm;
1695         err = do_request_fw(dev, filename, &fw->pcm);
1696         if (err)
1697                 goto err_load;
1698
1699         /* Get initvals */
1700         switch (dev->phy.type) {
1701         case B43_PHYTYPE_A:
1702                 if ((rev >= 5) && (rev <= 10)) {
1703                         if (tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY)
1704                                 filename = "a0g1initvals5";
1705                         else
1706                                 filename = "a0g0initvals5";
1707                 } else
1708                         goto err_no_initvals;
1709                 break;
1710         case B43_PHYTYPE_G:
1711                 if ((rev >= 5) && (rev <= 10))
1712                         filename = "b0g0initvals5";
1713                 else if (rev >= 13)
1714                         filename = "lp0initvals13";
1715                 else
1716                         goto err_no_initvals;
1717                 break;
1718         case B43_PHYTYPE_N:
1719                 if ((rev >= 11) && (rev <= 12))
1720                         filename = "n0initvals11";
1721                 else
1722                         goto err_no_initvals;
1723                 break;
1724         default:
1725                 goto err_no_initvals;
1726         }
1727         err = do_request_fw(dev, filename, &fw->initvals);
1728         if (err)
1729                 goto err_load;
1730
1731         /* Get bandswitch initvals */
1732         switch (dev->phy.type) {
1733         case B43_PHYTYPE_A:
1734                 if ((rev >= 5) && (rev <= 10)) {
1735                         if (tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY)
1736                                 filename = "a0g1bsinitvals5";
1737                         else
1738                                 filename = "a0g0bsinitvals5";
1739                 } else if (rev >= 11)
1740                         filename = NULL;
1741                 else
1742                         goto err_no_initvals;
1743                 break;
1744         case B43_PHYTYPE_G:
1745                 if ((rev >= 5) && (rev <= 10))
1746                         filename = "b0g0bsinitvals5";
1747                 else if (rev >= 11)
1748                         filename = NULL;
1749                 else
1750                         goto err_no_initvals;
1751                 break;
1752         case B43_PHYTYPE_N:
1753                 if ((rev >= 11) && (rev <= 12))
1754                         filename = "n0bsinitvals11";
1755                 else
1756                         goto err_no_initvals;
1757                 break;
1758         default:
1759                 goto err_no_initvals;
1760         }
1761         err = do_request_fw(dev, filename, &fw->initvals_band);
1762         if (err)
1763                 goto err_load;
1764
1765         return 0;
1766
1767 err_load:
1768         b43_print_fw_helptext(dev->wl, 1);
1769         goto error;
1770
1771 err_no_ucode:
1772         err = -ENODEV;
1773         b43err(dev->wl, "No microcode available for core rev %u\n", rev);
1774         goto error;
1775
1776 err_no_pcm:
1777         err = -ENODEV;
1778         b43err(dev->wl, "No PCM available for core rev %u\n", rev);
1779         goto error;
1780
1781 err_no_initvals:
1782         err = -ENODEV;
1783         b43err(dev->wl, "No Initial Values firmware file for PHY %u, "
1784                "core rev %u\n", dev->phy.type, rev);
1785         goto error;
1786
1787 error:
1788         b43_release_firmware(dev);
1789         return err;
1790 }
1791
1792 static int b43_upload_microcode(struct b43_wldev *dev)
1793 {
1794         const size_t hdr_len = sizeof(struct b43_fw_header);
1795         const __be32 *data;
1796         unsigned int i, len;
1797         u16 fwrev, fwpatch, fwdate, fwtime;
1798         u32 tmp, macctl;
1799         int err = 0;
1800
1801         /* Jump the microcode PSM to offset 0 */
1802         macctl = b43_read32(dev, B43_MMIO_MACCTL);
1803         B43_WARN_ON(macctl & B43_MACCTL_PSM_RUN);
1804         macctl |= B43_MACCTL_PSM_JMP0;
1805         b43_write32(dev, B43_MMIO_MACCTL, macctl);
1806         /* Zero out all microcode PSM registers and shared memory. */
1807         for (i = 0; i < 64; i++)
1808                 b43_shm_write16(dev, B43_SHM_SCRATCH, i, 0);
1809         for (i = 0; i < 4096; i += 2)
1810                 b43_shm_write16(dev, B43_SHM_SHARED, i, 0);
1811
1812         /* Upload Microcode. */
1813         data = (__be32 *) (dev->fw.ucode.data->data + hdr_len);
1814         len = (dev->fw.ucode.data->size - hdr_len) / sizeof(__be32);
1815         b43_shm_control_word(dev, B43_SHM_UCODE | B43_SHM_AUTOINC_W, 0x0000);
1816         for (i = 0; i < len; i++) {
1817                 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
1818                 udelay(10);
1819         }
1820
1821         if (dev->fw.pcm.data) {
1822                 /* Upload PCM data. */
1823                 data = (__be32 *) (dev->fw.pcm.data->data + hdr_len);
1824                 len = (dev->fw.pcm.data->size - hdr_len) / sizeof(__be32);
1825                 b43_shm_control_word(dev, B43_SHM_HW, 0x01EA);
1826                 b43_write32(dev, B43_MMIO_SHM_DATA, 0x00004000);
1827                 /* No need for autoinc bit in SHM_HW */
1828                 b43_shm_control_word(dev, B43_SHM_HW, 0x01EB);
1829                 for (i = 0; i < len; i++) {
1830                         b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
1831                         udelay(10);
1832                 }
1833         }
1834
1835         b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_ALL);
1836
1837         /* Start the microcode PSM */
1838         macctl = b43_read32(dev, B43_MMIO_MACCTL);
1839         macctl &= ~B43_MACCTL_PSM_JMP0;
1840         macctl |= B43_MACCTL_PSM_RUN;
1841         b43_write32(dev, B43_MMIO_MACCTL, macctl);
1842
1843         /* Wait for the microcode to load and respond */
1844         i = 0;
1845         while (1) {
1846                 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
1847                 if (tmp == B43_IRQ_MAC_SUSPENDED)
1848                         break;
1849                 i++;
1850                 if (i >= 20) {
1851                         b43err(dev->wl, "Microcode not responding\n");
1852                         b43_print_fw_helptext(dev->wl, 1);
1853                         err = -ENODEV;
1854                         goto error;
1855                 }
1856                 msleep_interruptible(50);
1857                 if (signal_pending(current)) {
1858                         err = -EINTR;
1859                         goto error;
1860                 }
1861         }
1862         b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);       /* dummy read */
1863
1864         /* Get and check the revisions. */
1865         fwrev = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEREV);
1866         fwpatch = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEPATCH);
1867         fwdate = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEDATE);
1868         fwtime = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODETIME);
1869
1870         if (fwrev <= 0x128) {
1871                 b43err(dev->wl, "YOUR FIRMWARE IS TOO OLD. Firmware from "
1872                        "binary drivers older than version 4.x is unsupported. "
1873                        "You must upgrade your firmware files.\n");
1874                 b43_print_fw_helptext(dev->wl, 1);
1875                 err = -EOPNOTSUPP;
1876                 goto error;
1877         }
1878         b43info(dev->wl, "Loading firmware version %u.%u "
1879                 "(20%.2i-%.2i-%.2i %.2i:%.2i:%.2i)\n",
1880                 fwrev, fwpatch,
1881                 (fwdate >> 12) & 0xF, (fwdate >> 8) & 0xF, fwdate & 0xFF,
1882                 (fwtime >> 11) & 0x1F, (fwtime >> 5) & 0x3F, fwtime & 0x1F);
1883
1884         dev->fw.rev = fwrev;
1885         dev->fw.patch = fwpatch;
1886
1887         if (b43_is_old_txhdr_format(dev)) {
1888                 b43warn(dev->wl, "You are using an old firmware image. "
1889                         "Support for old firmware will be removed in July 2008.\n");
1890                 b43_print_fw_helptext(dev->wl, 0);
1891         }
1892
1893         return 0;
1894
1895 error:
1896         macctl = b43_read32(dev, B43_MMIO_MACCTL);
1897         macctl &= ~B43_MACCTL_PSM_RUN;
1898         macctl |= B43_MACCTL_PSM_JMP0;
1899         b43_write32(dev, B43_MMIO_MACCTL, macctl);
1900
1901         return err;
1902 }
1903
1904 static int b43_write_initvals(struct b43_wldev *dev,
1905                               const struct b43_iv *ivals,
1906                               size_t count,
1907                               size_t array_size)
1908 {
1909         const struct b43_iv *iv;
1910         u16 offset;
1911         size_t i;
1912         bool bit32;
1913
1914         BUILD_BUG_ON(sizeof(struct b43_iv) != 6);
1915         iv = ivals;
1916         for (i = 0; i < count; i++) {
1917                 if (array_size < sizeof(iv->offset_size))
1918                         goto err_format;
1919                 array_size -= sizeof(iv->offset_size);
1920                 offset = be16_to_cpu(iv->offset_size);
1921                 bit32 = !!(offset & B43_IV_32BIT);
1922                 offset &= B43_IV_OFFSET_MASK;
1923                 if (offset >= 0x1000)
1924                         goto err_format;
1925                 if (bit32) {
1926                         u32 value;
1927
1928                         if (array_size < sizeof(iv->data.d32))
1929                                 goto err_format;
1930                         array_size -= sizeof(iv->data.d32);
1931
1932                         value = be32_to_cpu(get_unaligned(&iv->data.d32));
1933                         b43_write32(dev, offset, value);
1934
1935                         iv = (const struct b43_iv *)((const uint8_t *)iv +
1936                                                         sizeof(__be16) +
1937                                                         sizeof(__be32));
1938                 } else {
1939                         u16 value;
1940
1941                         if (array_size < sizeof(iv->data.d16))
1942                                 goto err_format;
1943                         array_size -= sizeof(iv->data.d16);
1944
1945                         value = be16_to_cpu(iv->data.d16);
1946                         b43_write16(dev, offset, value);
1947
1948                         iv = (const struct b43_iv *)((const uint8_t *)iv +
1949                                                         sizeof(__be16) +
1950                                                         sizeof(__be16));
1951                 }
1952         }
1953         if (array_size)
1954                 goto err_format;
1955
1956         return 0;
1957
1958 err_format:
1959         b43err(dev->wl, "Initial Values Firmware file-format error.\n");
1960         b43_print_fw_helptext(dev->wl, 1);
1961
1962         return -EPROTO;
1963 }
1964
1965 static int b43_upload_initvals(struct b43_wldev *dev)
1966 {
1967         const size_t hdr_len = sizeof(struct b43_fw_header);
1968         const struct b43_fw_header *hdr;
1969         struct b43_firmware *fw = &dev->fw;
1970         const struct b43_iv *ivals;
1971         size_t count;
1972         int err;
1973
1974         hdr = (const struct b43_fw_header *)(fw->initvals.data->data);
1975         ivals = (const struct b43_iv *)(fw->initvals.data->data + hdr_len);
1976         count = be32_to_cpu(hdr->size);
1977         err = b43_write_initvals(dev, ivals, count,
1978                                  fw->initvals.data->size - hdr_len);
1979         if (err)
1980                 goto out;
1981         if (fw->initvals_band.data) {
1982                 hdr = (const struct b43_fw_header *)(fw->initvals_band.data->data);
1983                 ivals = (const struct b43_iv *)(fw->initvals_band.data->data + hdr_len);
1984                 count = be32_to_cpu(hdr->size);
1985                 err = b43_write_initvals(dev, ivals, count,
1986                                          fw->initvals_band.data->size - hdr_len);
1987                 if (err)
1988                         goto out;
1989         }
1990 out:
1991
1992         return err;
1993 }
1994
1995 /* Initialize the GPIOs
1996  * http://bcm-specs.sipsolutions.net/GPIO
1997  */
1998 static int b43_gpio_init(struct b43_wldev *dev)
1999 {
2000         struct ssb_bus *bus = dev->dev->bus;
2001         struct ssb_device *gpiodev, *pcidev = NULL;
2002         u32 mask, set;
2003
2004         b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
2005                     & ~B43_MACCTL_GPOUTSMSK);
2006
2007         b43_write16(dev, B43_MMIO_GPIO_MASK, b43_read16(dev, B43_MMIO_GPIO_MASK)
2008                     | 0x000F);
2009
2010         mask = 0x0000001F;
2011         set = 0x0000000F;
2012         if (dev->dev->bus->chip_id == 0x4301) {
2013                 mask |= 0x0060;
2014                 set |= 0x0060;
2015         }
2016         if (0 /* FIXME: conditional unknown */ ) {
2017                 b43_write16(dev, B43_MMIO_GPIO_MASK,
2018                             b43_read16(dev, B43_MMIO_GPIO_MASK)
2019                             | 0x0100);
2020                 mask |= 0x0180;
2021                 set |= 0x0180;
2022         }
2023         if (dev->dev->bus->sprom.boardflags_lo & B43_BFL_PACTRL) {
2024                 b43_write16(dev, B43_MMIO_GPIO_MASK,
2025                             b43_read16(dev, B43_MMIO_GPIO_MASK)
2026                             | 0x0200);
2027                 mask |= 0x0200;
2028                 set |= 0x0200;
2029         }
2030         if (dev->dev->id.revision >= 2)
2031                 mask |= 0x0010; /* FIXME: This is redundant. */
2032
2033 #ifdef CONFIG_SSB_DRIVER_PCICORE
2034         pcidev = bus->pcicore.dev;
2035 #endif
2036         gpiodev = bus->chipco.dev ? : pcidev;
2037         if (!gpiodev)
2038                 return 0;
2039         ssb_write32(gpiodev, B43_GPIO_CONTROL,
2040                     (ssb_read32(gpiodev, B43_GPIO_CONTROL)
2041                      & mask) | set);
2042
2043         return 0;
2044 }
2045
2046 /* Turn off all GPIO stuff. Call this on module unload, for example. */
2047 static void b43_gpio_cleanup(struct b43_wldev *dev)
2048 {
2049         struct ssb_bus *bus = dev->dev->bus;
2050         struct ssb_device *gpiodev, *pcidev = NULL;
2051
2052 #ifdef CONFIG_SSB_DRIVER_PCICORE
2053         pcidev = bus->pcicore.dev;
2054 #endif
2055         gpiodev = bus->chipco.dev ? : pcidev;
2056         if (!gpiodev)
2057                 return;
2058         ssb_write32(gpiodev, B43_GPIO_CONTROL, 0);
2059 }
2060
2061 /* http://bcm-specs.sipsolutions.net/EnableMac */
2062 void b43_mac_enable(struct b43_wldev *dev)
2063 {
2064         dev->mac_suspended--;
2065         B43_WARN_ON(dev->mac_suspended < 0);
2066         B43_WARN_ON(irqs_disabled());
2067         if (dev->mac_suspended == 0) {
2068                 b43_write32(dev, B43_MMIO_MACCTL,
2069                             b43_read32(dev, B43_MMIO_MACCTL)
2070                             | B43_MACCTL_ENABLED);
2071                 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON,
2072                             B43_IRQ_MAC_SUSPENDED);
2073                 /* Commit writes */
2074                 b43_read32(dev, B43_MMIO_MACCTL);
2075                 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2076                 b43_power_saving_ctl_bits(dev, 0);
2077
2078                 /* Re-enable IRQs. */
2079                 spin_lock_irq(&dev->wl->irq_lock);
2080                 b43_interrupt_enable(dev, dev->irq_savedstate);
2081                 spin_unlock_irq(&dev->wl->irq_lock);
2082         }
2083 }
2084
2085 /* http://bcm-specs.sipsolutions.net/SuspendMAC */
2086 void b43_mac_suspend(struct b43_wldev *dev)
2087 {
2088         int i;
2089         u32 tmp;
2090
2091         might_sleep();
2092         B43_WARN_ON(irqs_disabled());
2093         B43_WARN_ON(dev->mac_suspended < 0);
2094
2095         if (dev->mac_suspended == 0) {
2096                 /* Mask IRQs before suspending MAC. Otherwise
2097                  * the MAC stays busy and won't suspend. */
2098                 spin_lock_irq(&dev->wl->irq_lock);
2099                 tmp = b43_interrupt_disable(dev, B43_IRQ_ALL);
2100                 spin_unlock_irq(&dev->wl->irq_lock);
2101                 b43_synchronize_irq(dev);
2102                 dev->irq_savedstate = tmp;
2103
2104                 b43_power_saving_ctl_bits(dev, B43_PS_AWAKE);
2105                 b43_write32(dev, B43_MMIO_MACCTL,
2106                             b43_read32(dev, B43_MMIO_MACCTL)
2107                             & ~B43_MACCTL_ENABLED);
2108                 /* force pci to flush the write */
2109                 b43_read32(dev, B43_MMIO_MACCTL);
2110                 for (i = 40; i; i--) {
2111                         tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2112                         if (tmp & B43_IRQ_MAC_SUSPENDED)
2113                                 goto out;
2114                         msleep(1);
2115                 }
2116                 b43err(dev->wl, "MAC suspend failed\n");
2117         }
2118 out:
2119         dev->mac_suspended++;
2120 }
2121
2122 static void b43_adjust_opmode(struct b43_wldev *dev)
2123 {
2124         struct b43_wl *wl = dev->wl;
2125         u32 ctl;
2126         u16 cfp_pretbtt;
2127
2128         ctl = b43_read32(dev, B43_MMIO_MACCTL);
2129         /* Reset status to STA infrastructure mode. */
2130         ctl &= ~B43_MACCTL_AP;
2131         ctl &= ~B43_MACCTL_KEEP_CTL;
2132         ctl &= ~B43_MACCTL_KEEP_BADPLCP;
2133         ctl &= ~B43_MACCTL_KEEP_BAD;
2134         ctl &= ~B43_MACCTL_PROMISC;
2135         ctl &= ~B43_MACCTL_BEACPROMISC;
2136         ctl |= B43_MACCTL_INFRA;
2137
2138         if (b43_is_mode(wl, IEEE80211_IF_TYPE_AP))
2139                 ctl |= B43_MACCTL_AP;
2140         else if (b43_is_mode(wl, IEEE80211_IF_TYPE_IBSS))
2141                 ctl &= ~B43_MACCTL_INFRA;
2142
2143         if (wl->filter_flags & FIF_CONTROL)
2144                 ctl |= B43_MACCTL_KEEP_CTL;
2145         if (wl->filter_flags & FIF_FCSFAIL)
2146                 ctl |= B43_MACCTL_KEEP_BAD;
2147         if (wl->filter_flags & FIF_PLCPFAIL)
2148                 ctl |= B43_MACCTL_KEEP_BADPLCP;
2149         if (wl->filter_flags & FIF_PROMISC_IN_BSS)
2150                 ctl |= B43_MACCTL_PROMISC;
2151         if (wl->filter_flags & FIF_BCN_PRBRESP_PROMISC)
2152                 ctl |= B43_MACCTL_BEACPROMISC;
2153
2154         /* Workaround: On old hardware the HW-MAC-address-filter
2155          * doesn't work properly, so always run promisc in filter
2156          * it in software. */
2157         if (dev->dev->id.revision <= 4)
2158                 ctl |= B43_MACCTL_PROMISC;
2159
2160         b43_write32(dev, B43_MMIO_MACCTL, ctl);
2161
2162         cfp_pretbtt = 2;
2163         if ((ctl & B43_MACCTL_INFRA) && !(ctl & B43_MACCTL_AP)) {
2164                 if (dev->dev->bus->chip_id == 0x4306 &&
2165                     dev->dev->bus->chip_rev == 3)
2166                         cfp_pretbtt = 100;
2167                 else
2168                         cfp_pretbtt = 50;
2169         }
2170         b43_write16(dev, 0x612, cfp_pretbtt);
2171 }
2172
2173 static void b43_rate_memory_write(struct b43_wldev *dev, u16 rate, int is_ofdm)
2174 {
2175         u16 offset;
2176
2177         if (is_ofdm) {
2178                 offset = 0x480;
2179                 offset += (b43_plcp_get_ratecode_ofdm(rate) & 0x000F) * 2;
2180         } else {
2181                 offset = 0x4C0;
2182                 offset += (b43_plcp_get_ratecode_cck(rate) & 0x000F) * 2;
2183         }
2184         b43_shm_write16(dev, B43_SHM_SHARED, offset + 0x20,
2185                         b43_shm_read16(dev, B43_SHM_SHARED, offset));
2186 }
2187
2188 static void b43_rate_memory_init(struct b43_wldev *dev)
2189 {
2190         switch (dev->phy.type) {
2191         case B43_PHYTYPE_A:
2192         case B43_PHYTYPE_G:
2193         case B43_PHYTYPE_N:
2194                 b43_rate_memory_write(dev, B43_OFDM_RATE_6MB, 1);
2195                 b43_rate_memory_write(dev, B43_OFDM_RATE_12MB, 1);
2196                 b43_rate_memory_write(dev, B43_OFDM_RATE_18MB, 1);
2197                 b43_rate_memory_write(dev, B43_OFDM_RATE_24MB, 1);
2198                 b43_rate_memory_write(dev, B43_OFDM_RATE_36MB, 1);
2199                 b43_rate_memory_write(dev, B43_OFDM_RATE_48MB, 1);
2200                 b43_rate_memory_write(dev, B43_OFDM_RATE_54MB, 1);
2201                 if (dev->phy.type == B43_PHYTYPE_A)
2202                         break;
2203                 /* fallthrough */
2204         case B43_PHYTYPE_B:
2205                 b43_rate_memory_write(dev, B43_CCK_RATE_1MB, 0);
2206                 b43_rate_memory_write(dev, B43_CCK_RATE_2MB, 0);
2207                 b43_rate_memory_write(dev, B43_CCK_RATE_5MB, 0);
2208                 b43_rate_memory_write(dev, B43_CCK_RATE_11MB, 0);
2209                 break;
2210         default:
2211                 B43_WARN_ON(1);
2212         }
2213 }
2214
2215 /* Set the TX-Antenna for management frames sent by firmware. */
2216 static void b43_mgmtframe_txantenna(struct b43_wldev *dev, int antenna)
2217 {
2218         u16 ant = 0;
2219         u16 tmp;
2220
2221         switch (antenna) {
2222         case B43_ANTENNA0:
2223                 ant |= B43_TXH_PHY_ANT0;
2224                 break;
2225         case B43_ANTENNA1:
2226                 ant |= B43_TXH_PHY_ANT1;
2227                 break;
2228         case B43_ANTENNA2:
2229                 ant |= B43_TXH_PHY_ANT2;
2230                 break;
2231         case B43_ANTENNA3:
2232                 ant |= B43_TXH_PHY_ANT3;
2233                 break;
2234         case B43_ANTENNA_AUTO:
2235                 ant |= B43_TXH_PHY_ANT01AUTO;
2236                 break;
2237         default:
2238                 B43_WARN_ON(1);
2239         }
2240
2241         /* FIXME We also need to set the other flags of the PHY control field somewhere. */
2242
2243         /* For Beacons */
2244         tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL);
2245         tmp = (tmp & ~B43_TXH_PHY_ANT) | ant;
2246         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, tmp);
2247         /* For ACK/CTS */
2248         tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL);
2249         tmp = (tmp & ~B43_TXH_PHY_ANT) | ant;
2250         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, tmp);
2251         /* For Probe Resposes */
2252         tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL);
2253         tmp = (tmp & ~B43_TXH_PHY_ANT) | ant;
2254         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, tmp);
2255 }
2256
2257 /* This is the opposite of b43_chip_init() */
2258 static void b43_chip_exit(struct b43_wldev *dev)
2259 {
2260         b43_radio_turn_off(dev, 1);
2261         b43_gpio_cleanup(dev);
2262         /* firmware is released later */
2263 }
2264
2265 /* Initialize the chip
2266  * http://bcm-specs.sipsolutions.net/ChipInit
2267  */
2268 static int b43_chip_init(struct b43_wldev *dev)
2269 {
2270         struct b43_phy *phy = &dev->phy;
2271         int err, tmp;
2272         u32 value32, macctl;
2273         u16 value16;
2274
2275         /* Initialize the MAC control */
2276         macctl = B43_MACCTL_IHR_ENABLED | B43_MACCTL_SHM_ENABLED;
2277         if (dev->phy.gmode)
2278                 macctl |= B43_MACCTL_GMODE;
2279         macctl |= B43_MACCTL_INFRA;
2280         b43_write32(dev, B43_MMIO_MACCTL, macctl);
2281
2282         err = b43_request_firmware(dev);
2283         if (err)
2284                 goto out;
2285         err = b43_upload_microcode(dev);
2286         if (err)
2287                 goto out;       /* firmware is released later */
2288
2289         err = b43_gpio_init(dev);
2290         if (err)
2291                 goto out;       /* firmware is released later */
2292
2293         err = b43_upload_initvals(dev);
2294         if (err)
2295                 goto err_gpio_clean;
2296         b43_radio_turn_on(dev);
2297
2298         b43_write16(dev, 0x03E6, 0x0000);
2299         err = b43_phy_init(dev);
2300         if (err)
2301                 goto err_radio_off;
2302
2303         /* Select initial Interference Mitigation. */
2304         tmp = phy->interfmode;
2305         phy->interfmode = B43_INTERFMODE_NONE;
2306         b43_radio_set_interference_mitigation(dev, tmp);
2307
2308         b43_set_rx_antenna(dev, B43_ANTENNA_DEFAULT);
2309         b43_mgmtframe_txantenna(dev, B43_ANTENNA_DEFAULT);
2310
2311         if (phy->type == B43_PHYTYPE_B) {
2312                 value16 = b43_read16(dev, 0x005E);
2313                 value16 |= 0x0004;
2314                 b43_write16(dev, 0x005E, value16);
2315         }
2316         b43_write32(dev, 0x0100, 0x01000000);
2317         if (dev->dev->id.revision < 5)
2318                 b43_write32(dev, 0x010C, 0x01000000);
2319
2320         b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
2321                     & ~B43_MACCTL_INFRA);
2322         b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
2323                     | B43_MACCTL_INFRA);
2324
2325         /* Probe Response Timeout value */
2326         /* FIXME: Default to 0, has to be set by ioctl probably... :-/ */
2327         b43_shm_write16(dev, B43_SHM_SHARED, 0x0074, 0x0000);
2328
2329         /* Initially set the wireless operation mode. */
2330         b43_adjust_opmode(dev);
2331
2332         if (dev->dev->id.revision < 3) {
2333                 b43_write16(dev, 0x060E, 0x0000);
2334                 b43_write16(dev, 0x0610, 0x8000);
2335                 b43_write16(dev, 0x0604, 0x0000);
2336                 b43_write16(dev, 0x0606, 0x0200);
2337         } else {
2338                 b43_write32(dev, 0x0188, 0x80000000);
2339                 b43_write32(dev, 0x018C, 0x02000000);
2340         }
2341         b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, 0x00004000);
2342         b43_write32(dev, B43_MMIO_DMA0_IRQ_MASK, 0x0001DC00);
2343         b43_write32(dev, B43_MMIO_DMA1_IRQ_MASK, 0x0000DC00);
2344         b43_write32(dev, B43_MMIO_DMA2_IRQ_MASK, 0x0000DC00);
2345         b43_write32(dev, B43_MMIO_DMA3_IRQ_MASK, 0x0001DC00);
2346         b43_write32(dev, B43_MMIO_DMA4_IRQ_MASK, 0x0000DC00);
2347         b43_write32(dev, B43_MMIO_DMA5_IRQ_MASK, 0x0000DC00);
2348
2349         value32 = ssb_read32(dev->dev, SSB_TMSLOW);
2350         value32 |= 0x00100000;
2351         ssb_write32(dev->dev, SSB_TMSLOW, value32);
2352
2353         b43_write16(dev, B43_MMIO_POWERUP_DELAY,
2354                     dev->dev->bus->chipco.fast_pwrup_delay);
2355
2356         err = 0;
2357         b43dbg(dev->wl, "Chip initialized\n");
2358 out:
2359         return err;
2360
2361 err_radio_off:
2362         b43_radio_turn_off(dev, 1);
2363 err_gpio_clean:
2364         b43_gpio_cleanup(dev);
2365         return err;
2366 }
2367
2368 static void b43_periodic_every120sec(struct b43_wldev *dev)
2369 {
2370         struct b43_phy *phy = &dev->phy;
2371
2372         if (phy->type != B43_PHYTYPE_G || phy->rev < 2)
2373                 return;
2374
2375         b43_mac_suspend(dev);
2376         b43_lo_g_measure(dev);
2377         b43_mac_enable(dev);
2378         if (b43_has_hardware_pctl(phy))
2379                 b43_lo_g_ctl_mark_all_unused(dev);
2380 }
2381
2382 static void b43_periodic_every60sec(struct b43_wldev *dev)
2383 {
2384         struct b43_phy *phy = &dev->phy;
2385
2386         if (phy->type != B43_PHYTYPE_G)
2387                 return;
2388         if (!b43_has_hardware_pctl(phy))
2389                 b43_lo_g_ctl_mark_all_unused(dev);
2390         if (dev->dev->bus->sprom.boardflags_lo & B43_BFL_RSSI) {
2391                 b43_mac_suspend(dev);
2392                 b43_calc_nrssi_slope(dev);
2393                 if ((phy->radio_ver == 0x2050) && (phy->radio_rev == 8)) {
2394                         u8 old_chan = phy->channel;
2395
2396                         /* VCO Calibration */
2397                         if (old_chan >= 8)
2398                                 b43_radio_selectchannel(dev, 1, 0);
2399                         else
2400                                 b43_radio_selectchannel(dev, 13, 0);
2401                         b43_radio_selectchannel(dev, old_chan, 0);
2402                 }
2403                 b43_mac_enable(dev);
2404         }
2405 }
2406
2407 static void b43_periodic_every30sec(struct b43_wldev *dev)
2408 {
2409         /* Update device statistics. */
2410         b43_calculate_link_quality(dev);
2411 }
2412
2413 static void b43_periodic_every15sec(struct b43_wldev *dev)
2414 {
2415         struct b43_phy *phy = &dev->phy;
2416
2417         if (phy->type == B43_PHYTYPE_G) {
2418                 //TODO: update_aci_moving_average
2419                 if (phy->aci_enable && phy->aci_wlan_automatic) {
2420                         b43_mac_suspend(dev);
2421                         if (!phy->aci_enable && 1 /*TODO: not scanning? */ ) {
2422                                 if (0 /*TODO: bunch of conditions */ ) {
2423                                         b43_radio_set_interference_mitigation
2424                                             (dev, B43_INTERFMODE_MANUALWLAN);
2425                                 }
2426                         } else if (1 /*TODO*/) {
2427                                 /*
2428                                    if ((aci_average > 1000) && !(b43_radio_aci_scan(dev))) {
2429                                    b43_radio_set_interference_mitigation(dev,
2430                                    B43_INTERFMODE_NONE);
2431                                    }
2432                                  */
2433                         }
2434                         b43_mac_enable(dev);
2435                 } else if (phy->interfmode == B43_INTERFMODE_NONWLAN &&
2436                            phy->rev == 1) {
2437                         //TODO: implement rev1 workaround
2438                 }
2439         }
2440         b43_phy_xmitpower(dev); //FIXME: unless scanning?
2441         //TODO for APHY (temperature?)
2442
2443         atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT);
2444         wmb();
2445 }
2446
2447 static void do_periodic_work(struct b43_wldev *dev)
2448 {
2449         unsigned int state;
2450
2451         state = dev->periodic_state;
2452         if (state % 8 == 0)
2453                 b43_periodic_every120sec(dev);
2454         if (state % 4 == 0)
2455                 b43_periodic_every60sec(dev);
2456         if (state % 2 == 0)
2457                 b43_periodic_every30sec(dev);
2458         b43_periodic_every15sec(dev);
2459 }
2460
2461 /* Periodic work locking policy:
2462  *      The whole periodic work handler is protected by
2463  *      wl->mutex. If another lock is needed somewhere in the
2464  *      pwork callchain, it's aquired in-place, where it's needed.
2465  */
2466 static void b43_periodic_work_handler(struct work_struct *work)
2467 {
2468         struct b43_wldev *dev = container_of(work, struct b43_wldev,
2469                                              periodic_work.work);
2470         struct b43_wl *wl = dev->wl;
2471         unsigned long delay;
2472
2473         mutex_lock(&wl->mutex);
2474
2475         if (unlikely(b43_status(dev) != B43_STAT_STARTED))
2476                 goto out;
2477         if (b43_debug(dev, B43_DBG_PWORK_STOP))
2478                 goto out_requeue;
2479
2480         do_periodic_work(dev);
2481
2482         dev->periodic_state++;
2483 out_requeue:
2484         if (b43_debug(dev, B43_DBG_PWORK_FAST))
2485                 delay = msecs_to_jiffies(50);
2486         else
2487                 delay = round_jiffies_relative(HZ * 15);
2488         queue_delayed_work(wl->hw->workqueue, &dev->periodic_work, delay);
2489 out:
2490         mutex_unlock(&wl->mutex);
2491 }
2492
2493 static void b43_periodic_tasks_setup(struct b43_wldev *dev)
2494 {
2495         struct delayed_work *work = &dev->periodic_work;
2496
2497         dev->periodic_state = 0;
2498         INIT_DELAYED_WORK(work, b43_periodic_work_handler);
2499         queue_delayed_work(dev->wl->hw->workqueue, work, 0);
2500 }
2501
2502 /* Check if communication with the device works correctly. */
2503 static int b43_validate_chipaccess(struct b43_wldev *dev)
2504 {
2505         u32 v, backup;
2506
2507         backup = b43_shm_read32(dev, B43_SHM_SHARED, 0);
2508
2509         /* Check for read/write and endianness problems. */
2510         b43_shm_write32(dev, B43_SHM_SHARED, 0, 0x55AAAA55);
2511         if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0x55AAAA55)
2512                 goto error;
2513         b43_shm_write32(dev, B43_SHM_SHARED, 0, 0xAA5555AA);
2514         if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0xAA5555AA)
2515                 goto error;
2516
2517         b43_shm_write32(dev, B43_SHM_SHARED, 0, backup);
2518
2519         if ((dev->dev->id.revision >= 3) && (dev->dev->id.revision <= 10)) {
2520                 /* The 32bit register shadows the two 16bit registers
2521                  * with update sideeffects. Validate this. */
2522                 b43_write16(dev, B43_MMIO_TSF_CFP_START, 0xAAAA);
2523                 b43_write32(dev, B43_MMIO_TSF_CFP_START, 0xCCCCBBBB);
2524                 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_LOW) != 0xBBBB)
2525                         goto error;
2526                 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_HIGH) != 0xCCCC)
2527                         goto error;
2528         }
2529         b43_write32(dev, B43_MMIO_TSF_CFP_START, 0);
2530
2531         v = b43_read32(dev, B43_MMIO_MACCTL);
2532         v |= B43_MACCTL_GMODE;
2533         if (v != (B43_MACCTL_GMODE | B43_MACCTL_IHR_ENABLED))
2534                 goto error;
2535
2536         return 0;
2537 error:
2538         b43err(dev->wl, "Failed to validate the chipaccess\n");
2539         return -ENODEV;
2540 }
2541
2542 static void b43_security_init(struct b43_wldev *dev)
2543 {
2544         dev->max_nr_keys = (dev->dev->id.revision >= 5) ? 58 : 20;
2545         B43_WARN_ON(dev->max_nr_keys > ARRAY_SIZE(dev->key));
2546         dev->ktp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_KTP);
2547         /* KTP is a word address, but we address SHM bytewise.
2548          * So multiply by two.
2549          */
2550         dev->ktp *= 2;
2551         if (dev->dev->id.revision >= 5) {
2552                 /* Number of RCMTA address slots */
2553                 b43_write16(dev, B43_MMIO_RCMTA_COUNT, dev->max_nr_keys - 8);
2554         }
2555         b43_clear_keys(dev);
2556 }
2557
2558 static int b43_rng_read(struct hwrng *rng, u32 * data)
2559 {
2560         struct b43_wl *wl = (struct b43_wl *)rng->priv;
2561         unsigned long flags;
2562
2563         /* Don't take wl->mutex here, as it could deadlock with
2564          * hwrng internal locking. It's not needed to take
2565          * wl->mutex here, anyway. */
2566
2567         spin_lock_irqsave(&wl->irq_lock, flags);
2568         *data = b43_read16(wl->current_dev, B43_MMIO_RNG);
2569         spin_unlock_irqrestore(&wl->irq_lock, flags);
2570
2571         return (sizeof(u16));
2572 }
2573
2574 static void b43_rng_exit(struct b43_wl *wl, bool suspended)
2575 {
2576         if (wl->rng_initialized)
2577                 __hwrng_unregister(&wl->rng, suspended);
2578 }
2579
2580 static int b43_rng_init(struct b43_wl *wl)
2581 {
2582         int err;
2583
2584         snprintf(wl->rng_name, ARRAY_SIZE(wl->rng_name),
2585                  "%s_%s", KBUILD_MODNAME, wiphy_name(wl->hw->wiphy));
2586         wl->rng.name = wl->rng_name;
2587         wl->rng.data_read = b43_rng_read;
2588         wl->rng.priv = (unsigned long)wl;
2589         wl->rng_initialized = 1;
2590         err = hwrng_register(&wl->rng);
2591         if (err) {
2592                 wl->rng_initialized = 0;
2593                 b43err(wl, "Failed to register the random "
2594                        "number generator (%d)\n", err);
2595         }
2596
2597         return err;
2598 }
2599
2600 static int b43_op_tx(struct ieee80211_hw *hw,
2601                      struct sk_buff *skb,
2602                      struct ieee80211_tx_control *ctl)
2603 {
2604         struct b43_wl *wl = hw_to_b43_wl(hw);
2605         struct b43_wldev *dev = wl->current_dev;
2606         int err = -ENODEV;
2607
2608         if (unlikely(!dev))
2609                 goto out;
2610         if (unlikely(b43_status(dev) < B43_STAT_STARTED))
2611                 goto out;
2612         /* DMA-TX is done without a global lock. */
2613         err = b43_dma_tx(dev, skb, ctl);
2614 out:
2615         if (unlikely(err))
2616                 return NETDEV_TX_BUSY;
2617         return NETDEV_TX_OK;
2618 }
2619
2620 static int b43_op_conf_tx(struct ieee80211_hw *hw,
2621                           int queue,
2622                           const struct ieee80211_tx_queue_params *params)
2623 {
2624         return 0;
2625 }
2626
2627 static int b43_op_get_tx_stats(struct ieee80211_hw *hw,
2628                                struct ieee80211_tx_queue_stats *stats)
2629 {
2630         struct b43_wl *wl = hw_to_b43_wl(hw);
2631         struct b43_wldev *dev = wl->current_dev;
2632         unsigned long flags;
2633         int err = -ENODEV;
2634
2635         if (!dev)
2636                 goto out;
2637         spin_lock_irqsave(&wl->irq_lock, flags);
2638         if (likely(b43_status(dev) >= B43_STAT_STARTED)) {
2639                 b43_dma_get_tx_stats(dev, stats);
2640                 err = 0;
2641         }
2642         spin_unlock_irqrestore(&wl->irq_lock, flags);
2643 out:
2644         return err;
2645 }
2646
2647 static int b43_op_get_stats(struct ieee80211_hw *hw,
2648                             struct ieee80211_low_level_stats *stats)
2649 {
2650         struct b43_wl *wl = hw_to_b43_wl(hw);
2651         unsigned long flags;
2652
2653         spin_lock_irqsave(&wl->irq_lock, flags);
2654         memcpy(stats, &wl->ieee_stats, sizeof(*stats));
2655         spin_unlock_irqrestore(&wl->irq_lock, flags);
2656
2657         return 0;
2658 }
2659
2660 static const char *phymode_to_string(unsigned int phymode)
2661 {
2662         switch (phymode) {
2663         case B43_PHYMODE_A:
2664                 return "A";
2665         case B43_PHYMODE_B:
2666                 return "B";
2667         case B43_PHYMODE_G:
2668                 return "G";
2669         default:
2670                 B43_WARN_ON(1);
2671         }
2672         return "";
2673 }
2674
2675 static int find_wldev_for_phymode(struct b43_wl *wl,
2676                                   unsigned int phymode,
2677                                   struct b43_wldev **dev, bool * gmode)
2678 {
2679         struct b43_wldev *d;
2680
2681         list_for_each_entry(d, &wl->devlist, list) {
2682                 if (d->phy.possible_phymodes & phymode) {
2683                         /* Ok, this device supports the PHY-mode.
2684                          * Now figure out how the gmode bit has to be
2685                          * set to support it. */
2686                         if (phymode == B43_PHYMODE_A)
2687                                 *gmode = 0;
2688                         else
2689                                 *gmode = 1;
2690                         *dev = d;
2691
2692                         return 0;
2693                 }
2694         }
2695
2696         return -ESRCH;
2697 }
2698
2699 static void b43_put_phy_into_reset(struct b43_wldev *dev)
2700 {
2701         struct ssb_device *sdev = dev->dev;
2702         u32 tmslow;
2703
2704         tmslow = ssb_read32(sdev, SSB_TMSLOW);
2705         tmslow &= ~B43_TMSLOW_GMODE;
2706         tmslow |= B43_TMSLOW_PHYRESET;
2707         tmslow |= SSB_TMSLOW_FGC;
2708         ssb_write32(sdev, SSB_TMSLOW, tmslow);
2709         msleep(1);
2710
2711         tmslow = ssb_read32(sdev, SSB_TMSLOW);
2712         tmslow &= ~SSB_TMSLOW_FGC;
2713         tmslow |= B43_TMSLOW_PHYRESET;
2714         ssb_write32(sdev, SSB_TMSLOW, tmslow);
2715         msleep(1);
2716 }
2717
2718 /* Expects wl->mutex locked */
2719 static int b43_switch_phymode(struct b43_wl *wl, unsigned int new_mode)
2720 {
2721         struct b43_wldev *up_dev;
2722         struct b43_wldev *down_dev;
2723         int err;
2724         bool gmode = 0;
2725         int prev_status;
2726
2727         err = find_wldev_for_phymode(wl, new_mode, &up_dev, &gmode);
2728         if (err) {
2729                 b43err(wl, "Could not find a device for %s-PHY mode\n",
2730                        phymode_to_string(new_mode));
2731                 return err;
2732         }
2733         if ((up_dev == wl->current_dev) &&
2734             (!!wl->current_dev->phy.gmode == !!gmode)) {
2735                 /* This device is already running. */
2736                 return 0;
2737         }
2738         b43dbg(wl, "Reconfiguring PHYmode to %s-PHY\n",
2739                phymode_to_string(new_mode));
2740         down_dev = wl->current_dev;
2741
2742         prev_status = b43_status(down_dev);
2743         /* Shutdown the currently running core. */
2744         if (prev_status >= B43_STAT_STARTED)
2745                 b43_wireless_core_stop(down_dev);
2746         if (prev_status >= B43_STAT_INITIALIZED)
2747                 b43_wireless_core_exit(down_dev);
2748
2749         if (down_dev != up_dev) {
2750                 /* We switch to a different core, so we put PHY into
2751                  * RESET on the old core. */
2752                 b43_put_phy_into_reset(down_dev);
2753         }
2754
2755         /* Now start the new core. */
2756         up_dev->phy.gmode = gmode;
2757         if (prev_status >= B43_STAT_INITIALIZED) {
2758                 err = b43_wireless_core_init(up_dev);
2759                 if (err) {
2760                         b43err(wl, "Fatal: Could not initialize device for "
2761                                "newly selected %s-PHY mode\n",
2762                                phymode_to_string(new_mode));
2763                         goto init_failure;
2764                 }
2765         }
2766         if (prev_status >= B43_STAT_STARTED) {
2767                 err = b43_wireless_core_start(up_dev);
2768                 if (err) {
2769                         b43err(wl, "Fatal: Coult not start device for "
2770                                "newly selected %s-PHY mode\n",
2771                                phymode_to_string(new_mode));
2772                         b43_wireless_core_exit(up_dev);
2773                         goto init_failure;
2774                 }
2775         }
2776         B43_WARN_ON(b43_status(up_dev) != prev_status);
2777
2778         wl->current_dev = up_dev;
2779
2780         return 0;
2781       init_failure:
2782         /* Whoops, failed to init the new core. No core is operating now. */
2783         wl->current_dev = NULL;
2784         return err;
2785 }
2786
2787 /* Check if the use of the antenna that ieee80211 told us to
2788  * use is possible. This will fall back to DEFAULT.
2789  * "antenna_nr" is the antenna identifier we got from ieee80211. */
2790 u8 b43_ieee80211_antenna_sanitize(struct b43_wldev *dev,
2791                                   u8 antenna_nr)
2792 {
2793         u8 antenna_mask;
2794
2795         if (antenna_nr == 0) {
2796                 /* Zero means "use default antenna". That's always OK. */
2797                 return 0;
2798         }
2799
2800         /* Get the mask of available antennas. */
2801         if (dev->phy.gmode)
2802                 antenna_mask = dev->dev->bus->sprom.ant_available_bg;
2803         else
2804                 antenna_mask = dev->dev->bus->sprom.ant_available_a;
2805
2806         if (!(antenna_mask & (1 << (antenna_nr - 1)))) {
2807                 /* This antenna is not available. Fall back to default. */
2808                 return 0;
2809         }
2810
2811         return antenna_nr;
2812 }
2813
2814 static int b43_antenna_from_ieee80211(struct b43_wldev *dev, u8 antenna)
2815 {
2816         antenna = b43_ieee80211_antenna_sanitize(dev, antenna);
2817         switch (antenna) {
2818         case 0:         /* default/diversity */
2819                 return B43_ANTENNA_DEFAULT;
2820         case 1:         /* Antenna 0 */
2821                 return B43_ANTENNA0;
2822         case 2:         /* Antenna 1 */
2823                 return B43_ANTENNA1;
2824         case 3:         /* Antenna 2 */
2825                 return B43_ANTENNA2;
2826         case 4:         /* Antenna 3 */
2827                 return B43_ANTENNA3;
2828         default:
2829                 return B43_ANTENNA_DEFAULT;
2830         }
2831 }
2832
2833 static int b43_op_config(struct ieee80211_hw *hw, struct ieee80211_conf *conf)
2834 {
2835         struct b43_wl *wl = hw_to_b43_wl(hw);
2836         struct b43_wldev *dev;
2837         struct b43_phy *phy;
2838         unsigned long flags;
2839         unsigned int new_phymode = 0xFFFF;
2840         int antenna;
2841         int err = 0;
2842         u32 savedirqs;
2843
2844         mutex_lock(&wl->mutex);
2845
2846         /* Switch the PHY mode (if necessary). */
2847         switch (conf->channel->band) {
2848         case IEEE80211_BAND_5GHZ:
2849                 new_phymode = B43_PHYMODE_A;
2850                 break;
2851         case IEEE80211_BAND_2GHZ:
2852                 new_phymode = B43_PHYMODE_G;
2853                 break;
2854         default:
2855                 B43_WARN_ON(1);
2856         }
2857         err = b43_switch_phymode(wl, new_phymode);
2858         if (err)
2859                 goto out_unlock_mutex;
2860         dev = wl->current_dev;
2861         phy = &dev->phy;
2862
2863         /* Disable IRQs while reconfiguring the device.
2864          * This makes it possible to drop the spinlock throughout
2865          * the reconfiguration process. */
2866         spin_lock_irqsave(&wl->irq_lock, flags);
2867         if (b43_status(dev) < B43_STAT_STARTED) {
2868                 spin_unlock_irqrestore(&wl->irq_lock, flags);
2869                 goto out_unlock_mutex;
2870         }
2871         savedirqs = b43_interrupt_disable(dev, B43_IRQ_ALL);
2872         spin_unlock_irqrestore(&wl->irq_lock, flags);
2873         b43_synchronize_irq(dev);
2874
2875         /* Switch to the requested channel.
2876          * The firmware takes care of races with the TX handler. */
2877         if (conf->channel->hw_value != phy->channel)
2878                 b43_radio_selectchannel(dev, conf->channel->hw_value, 0);
2879
2880         /* Enable/Disable ShortSlot timing. */
2881         if ((!!(conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME)) !=
2882             dev->short_slot) {
2883                 B43_WARN_ON(phy->type != B43_PHYTYPE_G);
2884                 if (conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME)
2885                         b43_short_slot_timing_enable(dev);
2886                 else
2887                         b43_short_slot_timing_disable(dev);
2888         }
2889
2890         dev->wl->radiotap_enabled = !!(conf->flags & IEEE80211_CONF_RADIOTAP);
2891
2892         /* Adjust the desired TX power level. */
2893         if (conf->power_level != 0) {
2894                 if (conf->power_level != phy->power_level) {
2895                         phy->power_level = conf->power_level;
2896                         b43_phy_xmitpower(dev);
2897                 }
2898         }
2899
2900         /* Antennas for RX and management frame TX. */
2901         antenna = b43_antenna_from_ieee80211(dev, conf->antenna_sel_tx);
2902         b43_mgmtframe_txantenna(dev, antenna);
2903         antenna = b43_antenna_from_ieee80211(dev, conf->antenna_sel_rx);
2904         b43_set_rx_antenna(dev, antenna);
2905
2906         /* Update templates for AP mode. */
2907         if (b43_is_mode(wl, IEEE80211_IF_TYPE_AP))
2908                 b43_set_beacon_int(dev, conf->beacon_int);
2909
2910         if (!!conf->radio_enabled != phy->radio_on) {
2911                 if (conf->radio_enabled) {
2912                         b43_radio_turn_on(dev);
2913                         b43info(dev->wl, "Radio turned on by software\n");
2914                         if (!dev->radio_hw_enable) {
2915                                 b43info(dev->wl, "The hardware RF-kill button "
2916                                         "still turns the radio physically off. "
2917                                         "Press the button to turn it on.\n");
2918                         }
2919                 } else {
2920                         b43_radio_turn_off(dev, 0);
2921                         b43info(dev->wl, "Radio turned off by software\n");
2922                 }
2923         }
2924
2925         spin_lock_irqsave(&wl->irq_lock, flags);
2926         b43_interrupt_enable(dev, savedirqs);
2927         mmiowb();
2928         spin_unlock_irqrestore(&wl->irq_lock, flags);
2929       out_unlock_mutex:
2930         mutex_unlock(&wl->mutex);
2931
2932         return err;
2933 }
2934
2935 static int b43_op_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
2936                            const u8 *local_addr, const u8 *addr,
2937                            struct ieee80211_key_conf *key)
2938 {
2939         struct b43_wl *wl = hw_to_b43_wl(hw);
2940         struct b43_wldev *dev;
2941         unsigned long flags;
2942         u8 algorithm;
2943         u8 index;
2944         int err;
2945         DECLARE_MAC_BUF(mac);
2946
2947         if (modparam_nohwcrypt)
2948                 return -ENOSPC; /* User disabled HW-crypto */
2949
2950         mutex_lock(&wl->mutex);
2951         spin_lock_irqsave(&wl->irq_lock, flags);
2952
2953         dev = wl->current_dev;
2954         err = -ENODEV;
2955         if (!dev || b43_status(dev) < B43_STAT_INITIALIZED)
2956                 goto out_unlock;
2957
2958         err = -EINVAL;
2959         switch (key->alg) {
2960         case ALG_WEP:
2961                 if (key->keylen == 5)
2962                         algorithm = B43_SEC_ALGO_WEP40;
2963                 else
2964                         algorithm = B43_SEC_ALGO_WEP104;
2965                 break;
2966         case ALG_TKIP:
2967                 algorithm = B43_SEC_ALGO_TKIP;
2968                 break;
2969         case ALG_CCMP:
2970                 algorithm = B43_SEC_ALGO_AES;
2971                 break;
2972         default:
2973                 B43_WARN_ON(1);
2974                 goto out_unlock;
2975         }
2976         index = (u8) (key->keyidx);
2977         if (index > 3)
2978                 goto out_unlock;
2979
2980         switch (cmd) {
2981         case SET_KEY:
2982                 if (algorithm == B43_SEC_ALGO_TKIP) {
2983                         /* FIXME: No TKIP hardware encryption for now. */
2984                         err = -EOPNOTSUPP;
2985                         goto out_unlock;
2986                 }
2987
2988                 if (is_broadcast_ether_addr(addr)) {
2989                         /* addr is FF:FF:FF:FF:FF:FF for default keys */
2990                         err = b43_key_write(dev, index, algorithm,
2991                                             key->key, key->keylen, NULL, key);
2992                 } else {
2993                         /*
2994                          * either pairwise key or address is 00:00:00:00:00:00
2995                          * for transmit-only keys
2996                          */
2997                         err = b43_key_write(dev, -1, algorithm,
2998                                             key->key, key->keylen, addr, key);
2999                 }
3000                 if (err)
3001                         goto out_unlock;
3002
3003                 if (algorithm == B43_SEC_ALGO_WEP40 ||
3004                     algorithm == B43_SEC_ALGO_WEP104) {
3005                         b43_hf_write(dev, b43_hf_read(dev) | B43_HF_USEDEFKEYS);
3006                 } else {
3007                         b43_hf_write(dev,
3008                                      b43_hf_read(dev) & ~B43_HF_USEDEFKEYS);
3009                 }
3010                 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
3011                 break;
3012         case DISABLE_KEY: {
3013                 err = b43_key_clear(dev, key->hw_key_idx);
3014                 if (err)
3015                         goto out_unlock;
3016                 break;
3017         }
3018         default:
3019                 B43_WARN_ON(1);
3020         }
3021 out_unlock:
3022         spin_unlock_irqrestore(&wl->irq_lock, flags);
3023         mutex_unlock(&wl->mutex);
3024         if (!err) {
3025                 b43dbg(wl, "%s hardware based encryption for keyidx: %d, "
3026                        "mac: %s\n",
3027                        cmd == SET_KEY ? "Using" : "Disabling", key->keyidx,
3028                        print_mac(mac, addr));
3029         }
3030         return err;
3031 }
3032
3033 static void b43_op_configure_filter(struct ieee80211_hw *hw,
3034                                     unsigned int changed, unsigned int *fflags,
3035                                     int mc_count, struct dev_addr_list *mc_list)
3036 {
3037         struct b43_wl *wl = hw_to_b43_wl(hw);
3038         struct b43_wldev *dev = wl->current_dev;
3039         unsigned long flags;
3040
3041         if (!dev) {
3042                 *fflags = 0;
3043                 return;
3044         }
3045
3046         spin_lock_irqsave(&wl->irq_lock, flags);
3047         *fflags &= FIF_PROMISC_IN_BSS |
3048                   FIF_ALLMULTI |
3049                   FIF_FCSFAIL |
3050                   FIF_PLCPFAIL |
3051                   FIF_CONTROL |
3052                   FIF_OTHER_BSS |
3053                   FIF_BCN_PRBRESP_PROMISC;
3054
3055         changed &= FIF_PROMISC_IN_BSS |
3056                    FIF_ALLMULTI |
3057                    FIF_FCSFAIL |
3058                    FIF_PLCPFAIL |
3059                    FIF_CONTROL |
3060                    FIF_OTHER_BSS |
3061                    FIF_BCN_PRBRESP_PROMISC;
3062
3063         wl->filter_flags = *fflags;
3064
3065         if (changed && b43_status(dev) >= B43_STAT_INITIALIZED)
3066                 b43_adjust_opmode(dev);
3067         spin_unlock_irqrestore(&wl->irq_lock, flags);
3068 }
3069
3070 static int b43_op_config_interface(struct ieee80211_hw *hw,
3071                                    struct ieee80211_vif *vif,
3072                                    struct ieee80211_if_conf *conf)
3073 {
3074         struct b43_wl *wl = hw_to_b43_wl(hw);
3075         struct b43_wldev *dev = wl->current_dev;
3076         unsigned long flags;
3077
3078         if (!dev)
3079                 return -ENODEV;
3080         mutex_lock(&wl->mutex);
3081         spin_lock_irqsave(&wl->irq_lock, flags);
3082         B43_WARN_ON(wl->vif != vif);
3083         if (conf->bssid)
3084                 memcpy(wl->bssid, conf->bssid, ETH_ALEN);
3085         else
3086                 memset(wl->bssid, 0, ETH_ALEN);
3087         if (b43_status(dev) >= B43_STAT_INITIALIZED) {
3088                 if (b43_is_mode(wl, IEEE80211_IF_TYPE_AP)) {
3089                         B43_WARN_ON(conf->type != IEEE80211_IF_TYPE_AP);
3090                         b43_set_ssid(dev, conf->ssid, conf->ssid_len);
3091                         if (conf->beacon)
3092                                 b43_update_templates(wl, conf->beacon);
3093                 }
3094                 b43_write_mac_bssid_templates(dev);
3095         }
3096         spin_unlock_irqrestore(&wl->irq_lock, flags);
3097         mutex_unlock(&wl->mutex);
3098
3099         return 0;
3100 }
3101
3102 /* Locking: wl->mutex */
3103 static void b43_wireless_core_stop(struct b43_wldev *dev)
3104 {
3105         struct b43_wl *wl = dev->wl;
3106         unsigned long flags;
3107
3108         if (b43_status(dev) < B43_STAT_STARTED)
3109                 return;
3110
3111         /* Disable and sync interrupts. We must do this before than
3112          * setting the status to INITIALIZED, as the interrupt handler
3113          * won't care about IRQs then. */
3114         spin_lock_irqsave(&wl->irq_lock, flags);
3115         dev->irq_savedstate = b43_interrupt_disable(dev, B43_IRQ_ALL);
3116         b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); /* flush */
3117         spin_unlock_irqrestore(&wl->irq_lock, flags);
3118         b43_synchronize_irq(dev);
3119
3120         b43_set_status(dev, B43_STAT_INITIALIZED);
3121
3122         mutex_unlock(&wl->mutex);
3123         /* Must unlock as it would otherwise deadlock. No races here.
3124          * Cancel the possibly running self-rearming periodic work. */
3125         cancel_delayed_work_sync(&dev->periodic_work);
3126         mutex_lock(&wl->mutex);
3127
3128         ieee80211_stop_queues(wl->hw);  //FIXME this could cause a deadlock, as mac80211 seems buggy.
3129
3130         b43_mac_suspend(dev);
3131         free_irq(dev->dev->irq, dev);
3132         b43dbg(wl, "Wireless interface stopped\n");
3133 }
3134
3135 /* Locking: wl->mutex */
3136 static int b43_wireless_core_start(struct b43_wldev *dev)
3137 {
3138         int err;
3139
3140         B43_WARN_ON(b43_status(dev) != B43_STAT_INITIALIZED);
3141
3142         drain_txstatus_queue(dev);
3143         err = request_irq(dev->dev->irq, b43_interrupt_handler,
3144                           IRQF_SHARED, KBUILD_MODNAME, dev);
3145         if (err) {
3146                 b43err(dev->wl, "Cannot request IRQ-%d\n", dev->dev->irq);
3147                 goto out;
3148         }
3149
3150         /* We are ready to run. */
3151         b43_set_status(dev, B43_STAT_STARTED);
3152
3153         /* Start data flow (TX/RX). */
3154         b43_mac_enable(dev);
3155         b43_interrupt_enable(dev, dev->irq_savedstate);
3156         ieee80211_start_queues(dev->wl->hw);
3157
3158         /* Start maintainance work */
3159         b43_periodic_tasks_setup(dev);
3160
3161         b43dbg(dev->wl, "Wireless interface started\n");
3162       out:
3163         return err;
3164 }
3165
3166 /* Get PHY and RADIO versioning numbers */
3167 static int b43_phy_versioning(struct b43_wldev *dev)
3168 {
3169         struct b43_phy *phy = &dev->phy;
3170         u32 tmp;
3171         u8 analog_type;
3172         u8 phy_type;
3173         u8 phy_rev;
3174         u16 radio_manuf;
3175         u16 radio_ver;
3176         u16 radio_rev;
3177         int unsupported = 0;
3178
3179         /* Get PHY versioning */
3180         tmp = b43_read16(dev, B43_MMIO_PHY_VER);
3181         analog_type = (tmp & B43_PHYVER_ANALOG) >> B43_PHYVER_ANALOG_SHIFT;
3182         phy_type = (tmp & B43_PHYVER_TYPE) >> B43_PHYVER_TYPE_SHIFT;
3183         phy_rev = (tmp & B43_PHYVER_VERSION);
3184         switch (phy_type) {
3185         case B43_PHYTYPE_A:
3186                 if (phy_rev >= 4)
3187                         unsupported = 1;
3188                 break;
3189         case B43_PHYTYPE_B:
3190                 if (phy_rev != 2 && phy_rev != 4 && phy_rev != 6
3191                     && phy_rev != 7)
3192                         unsupported = 1;
3193                 break;
3194         case B43_PHYTYPE_G:
3195                 if (phy_rev > 9)
3196                         unsupported = 1;
3197                 break;
3198 #ifdef CONFIG_B43_NPHY
3199         case B43_PHYTYPE_N:
3200                 if (phy_rev > 1)
3201                         unsupported = 1;
3202                 break;
3203 #endif
3204         default:
3205                 unsupported = 1;
3206         };
3207         if (unsupported) {
3208                 b43err(dev->wl, "FOUND UNSUPPORTED PHY "
3209                        "(Analog %u, Type %u, Revision %u)\n",
3210                        analog_type, phy_type, phy_rev);
3211                 return -EOPNOTSUPP;
3212         }
3213         b43dbg(dev->wl, "Found PHY: Analog %u, Type %u, Revision %u\n",
3214                analog_type, phy_type, phy_rev);
3215
3216         /* Get RADIO versioning */
3217         if (dev->dev->bus->chip_id == 0x4317) {
3218                 if (dev->dev->bus->chip_rev == 0)
3219                         tmp = 0x3205017F;
3220                 else if (dev->dev->bus->chip_rev == 1)
3221                         tmp = 0x4205017F;
3222                 else
3223                         tmp = 0x5205017F;
3224         } else {
3225                 b43_write16(dev, B43_MMIO_RADIO_CONTROL, B43_RADIOCTL_ID);
3226                 tmp = b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
3227                 b43_write16(dev, B43_MMIO_RADIO_CONTROL, B43_RADIOCTL_ID);
3228                 tmp |= (u32)b43_read16(dev, B43_MMIO_RADIO_DATA_HIGH) << 16;
3229         }
3230         radio_manuf = (tmp & 0x00000FFF);
3231         radio_ver = (tmp & 0x0FFFF000) >> 12;
3232         radio_rev = (tmp & 0xF0000000) >> 28;
3233         if (radio_manuf != 0x17F /* Broadcom */)
3234                 unsupported = 1;
3235         switch (phy_type) {
3236         case B43_PHYTYPE_A:
3237                 if (radio_ver != 0x2060)
3238                         unsupported = 1;
3239                 if (radio_rev != 1)
3240                         unsupported = 1;
3241                 if (radio_manuf != 0x17F)
3242                         unsupported = 1;
3243                 break;
3244         case B43_PHYTYPE_B:
3245                 if ((radio_ver & 0xFFF0) != 0x2050)
3246                         unsupported = 1;
3247                 break;
3248         case B43_PHYTYPE_G:
3249                 if (radio_ver != 0x2050)
3250                         unsupported = 1;
3251                 break;
3252         case B43_PHYTYPE_N:
3253                 if (radio_ver != 0x2055)
3254                         unsupported = 1;
3255                 break;
3256         default:
3257                 B43_WARN_ON(1);
3258         }
3259         if (unsupported) {
3260                 b43err(dev->wl, "FOUND UNSUPPORTED RADIO "
3261                        "(Manuf 0x%X, Version 0x%X, Revision %u)\n",
3262                        radio_manuf, radio_ver, radio_rev);
3263                 return -EOPNOTSUPP;
3264         }
3265         b43dbg(dev->wl, "Found Radio: Manuf 0x%X, Version 0x%X, Revision %u\n",
3266                radio_manuf, radio_ver, radio_rev);
3267
3268         phy->radio_manuf = radio_manuf;
3269         phy->radio_ver = radio_ver;
3270         phy->radio_rev = radio_rev;
3271
3272         phy->analog = analog_type;
3273         phy->type = phy_type;
3274         phy->rev = phy_rev;
3275
3276         return 0;
3277 }
3278
3279 static void setup_struct_phy_for_init(struct b43_wldev *dev,
3280                                       struct b43_phy *phy)
3281 {
3282         struct b43_txpower_lo_control *lo;
3283         int i;
3284
3285         memset(phy->minlowsig, 0xFF, sizeof(phy->minlowsig));
3286         memset(phy->minlowsigpos, 0, sizeof(phy->minlowsigpos));
3287
3288         phy->aci_enable = 0;
3289         phy->aci_wlan_automatic = 0;
3290         phy->aci_hw_rssi = 0;
3291
3292         phy->radio_off_context.valid = 0;
3293
3294         lo = phy->lo_control;
3295         if (lo) {
3296                 memset(lo, 0, sizeof(*(phy->lo_control)));
3297                 lo->rebuild = 1;
3298                 lo->tx_bias = 0xFF;
3299         }
3300         phy->max_lb_gain = 0;
3301         phy->trsw_rx_gain = 0;
3302         phy->txpwr_offset = 0;
3303
3304         /* NRSSI */
3305         phy->nrssislope = 0;
3306         for (i = 0; i < ARRAY_SIZE(phy->nrssi); i++)
3307                 phy->nrssi[i] = -1000;
3308         for (i = 0; i < ARRAY_SIZE(phy->nrssi_lt); i++)
3309                 phy->nrssi_lt[i] = i;
3310
3311         phy->lofcal = 0xFFFF;
3312         phy->initval = 0xFFFF;
3313
3314         phy->interfmode = B43_INTERFMODE_NONE;
3315         phy->channel = 0xFF;
3316
3317         phy->hardware_power_control = !!modparam_hwpctl;
3318
3319         /* PHY TX errors counter. */
3320         atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT);
3321
3322         /* OFDM-table address caching. */
3323         phy->ofdmtab_addr_direction = B43_OFDMTAB_DIRECTION_UNKNOWN;
3324 }
3325
3326 static void setup_struct_wldev_for_init(struct b43_wldev *dev)
3327 {
3328         dev->dfq_valid = 0;
3329
3330         /* Assume the radio is enabled. If it's not enabled, the state will
3331          * immediately get fixed on the first periodic work run. */
3332         dev->radio_hw_enable = 1;
3333
3334         /* Stats */
3335         memset(&dev->stats, 0, sizeof(dev->stats));
3336
3337         setup_struct_phy_for_init(dev, &dev->phy);
3338
3339         /* IRQ related flags */
3340         dev->irq_reason = 0;
3341         memset(dev->dma_reason, 0, sizeof(dev->dma_reason));
3342         dev->irq_savedstate = B43_IRQ_MASKTEMPLATE;
3343
3344         dev->mac_suspended = 1;
3345
3346         /* Noise calculation context */
3347         memset(&dev->noisecalc, 0, sizeof(dev->noisecalc));
3348 }
3349
3350 static void b43_bluetooth_coext_enable(struct b43_wldev *dev)
3351 {
3352         struct ssb_sprom *sprom = &dev->dev->bus->sprom;
3353         u32 hf;
3354
3355         if (!(sprom->boardflags_lo & B43_BFL_BTCOEXIST))
3356                 return;
3357         if (dev->phy.type != B43_PHYTYPE_B && !dev->phy.gmode)
3358                 return;
3359
3360         hf = b43_hf_read(dev);
3361         if (sprom->boardflags_lo & B43_BFL_BTCMOD)
3362                 hf |= B43_HF_BTCOEXALT;
3363         else
3364                 hf |= B43_HF_BTCOEX;
3365         b43_hf_write(dev, hf);
3366         //TODO
3367 }
3368
3369 static void b43_bluetooth_coext_disable(struct b43_wldev *dev)
3370 {                               //TODO
3371 }
3372
3373 static void b43_imcfglo_timeouts_workaround(struct b43_wldev *dev)
3374 {
3375 #ifdef CONFIG_SSB_DRIVER_PCICORE
3376         struct ssb_bus *bus = dev->dev->bus;
3377         u32 tmp;
3378
3379         if (bus->pcicore.dev &&
3380             bus->pcicore.dev->id.coreid == SSB_DEV_PCI &&
3381             bus->pcicore.dev->id.revision <= 5) {
3382                 /* IMCFGLO timeouts workaround. */
3383                 tmp = ssb_read32(dev->dev, SSB_IMCFGLO);
3384                 tmp &= ~SSB_IMCFGLO_REQTO;
3385                 tmp &= ~SSB_IMCFGLO_SERTO;
3386                 switch (bus->bustype) {
3387                 case SSB_BUSTYPE_PCI:
3388                 case SSB_BUSTYPE_PCMCIA:
3389                         tmp |= 0x32;
3390                         break;
3391                 case SSB_BUSTYPE_SSB:
3392                         tmp |= 0x53;
3393                         break;
3394                 }
3395                 ssb_write32(dev->dev, SSB_IMCFGLO, tmp);
3396         }
3397 #endif /* CONFIG_SSB_DRIVER_PCICORE */
3398 }
3399
3400 /* Write the short and long frame retry limit values. */
3401 static void b43_set_retry_limits(struct b43_wldev *dev,
3402                                  unsigned int short_retry,
3403                                  unsigned int long_retry)
3404 {
3405         /* The retry limit is a 4-bit counter. Enforce this to avoid overflowing
3406          * the chip-internal counter. */
3407         short_retry = min(short_retry, (unsigned int)0xF);
3408         long_retry = min(long_retry, (unsigned int)0xF);
3409
3410         b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_SRLIMIT,
3411                         short_retry);
3412         b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_LRLIMIT,
3413                         long_retry);
3414 }
3415
3416 /* Shutdown a wireless core */
3417 /* Locking: wl->mutex */
3418 static void b43_wireless_core_exit(struct b43_wldev *dev)
3419 {
3420         struct b43_phy *phy = &dev->phy;
3421         u32 macctl;
3422
3423         B43_WARN_ON(b43_status(dev) > B43_STAT_INITIALIZED);
3424         if (b43_status(dev) != B43_STAT_INITIALIZED)
3425                 return;
3426         b43_set_status(dev, B43_STAT_UNINIT);
3427
3428         /* Stop the microcode PSM. */
3429         macctl = b43_read32(dev, B43_MMIO_MACCTL);
3430         macctl &= ~B43_MACCTL_PSM_RUN;
3431         macctl |= B43_MACCTL_PSM_JMP0;
3432         b43_write32(dev, B43_MMIO_MACCTL, macctl);
3433
3434         if (!dev->suspend_in_progress) {
3435                 b43_leds_exit(dev);
3436                 b43_rng_exit(dev->wl, false);
3437         }
3438         b43_dma_free(dev);
3439         b43_chip_exit(dev);
3440         b43_radio_turn_off(dev, 1);
3441         b43_switch_analog(dev, 0);
3442         if (phy->dyn_tssi_tbl)
3443                 kfree(phy->tssi2dbm);
3444         kfree(phy->lo_control);
3445         phy->lo_control = NULL;
3446         if (dev->wl->current_beacon) {
3447                 dev_kfree_skb_any(dev->wl->current_beacon);
3448                 dev->wl->current_beacon = NULL;
3449         }
3450
3451         ssb_device_disable(dev->dev, 0);
3452         ssb_bus_may_powerdown(dev->dev->bus);
3453 }
3454
3455 /* Initialize a wireless core */
3456 static int b43_wireless_core_init(struct b43_wldev *dev)
3457 {
3458         struct b43_wl *wl = dev->wl;
3459         struct ssb_bus *bus = dev->dev->bus;
3460         struct ssb_sprom *sprom = &bus->sprom;
3461         struct b43_phy *phy = &dev->phy;
3462         int err;
3463         u32 hf, tmp;
3464
3465         B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
3466
3467         err = ssb_bus_powerup(bus, 0);
3468         if (err)
3469                 goto out;
3470         if (!ssb_device_is_enabled(dev->dev)) {
3471                 tmp = phy->gmode ? B43_TMSLOW_GMODE : 0;
3472                 b43_wireless_core_reset(dev, tmp);
3473         }
3474
3475         if ((phy->type == B43_PHYTYPE_B) || (phy->type == B43_PHYTYPE_G)) {
3476                 phy->lo_control =
3477                     kzalloc(sizeof(*(phy->lo_control)), GFP_KERNEL);
3478                 if (!phy->lo_control) {
3479                         err = -ENOMEM;
3480                         goto err_busdown;
3481                 }
3482         }
3483         setup_struct_wldev_for_init(dev);
3484
3485         err = b43_phy_init_tssi2dbm_table(dev);
3486         if (err)
3487                 goto err_kfree_lo_control;
3488
3489         /* Enable IRQ routing to this device. */
3490         ssb_pcicore_dev_irqvecs_enable(&bus->pcicore, dev->dev);
3491
3492         b43_imcfglo_timeouts_workaround(dev);
3493         b43_bluetooth_coext_disable(dev);
3494         b43_phy_early_init(dev);
3495         err = b43_chip_init(dev);
3496         if (err)
3497                 goto err_kfree_tssitbl;
3498         b43_shm_write16(dev, B43_SHM_SHARED,
3499                         B43_SHM_SH_WLCOREREV, dev->dev->id.revision);
3500         hf = b43_hf_read(dev);
3501         if (phy->type == B43_PHYTYPE_G) {
3502                 hf |= B43_HF_SYMW;
3503                 if (phy->rev == 1)
3504                         hf |= B43_HF_GDCW;
3505                 if (sprom->boardflags_lo & B43_BFL_PACTRL)
3506                         hf |= B43_HF_OFDMPABOOST;
3507         } else if (phy->type == B43_PHYTYPE_B) {
3508                 hf |= B43_HF_SYMW;
3509                 if (phy->rev >= 2 && phy->radio_ver == 0x2050)
3510                         hf &= ~B43_HF_GDCW;
3511         }
3512         b43_hf_write(dev, hf);
3513
3514         b43_set_retry_limits(dev, B43_DEFAULT_SHORT_RETRY_LIMIT,
3515                              B43_DEFAULT_LONG_RETRY_LIMIT);
3516         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SFFBLIM, 3);
3517         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_LFFBLIM, 2);
3518
3519         /* Disable sending probe responses from firmware.
3520          * Setting the MaxTime to one usec will always trigger
3521          * a timeout, so we never send any probe resp.
3522          * A timeout of zero is infinite. */
3523         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRMAXTIME, 1);
3524
3525         b43_rate_memory_init(dev);
3526
3527         /* Minimum Contention Window */
3528         if (phy->type == B43_PHYTYPE_B) {
3529                 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0x1F);
3530         } else {
3531                 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0xF);
3532         }
3533         /* Maximum Contention Window */
3534         b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MAXCONT, 0x3FF);
3535
3536         err = b43_dma_init(dev);
3537         if (err)
3538                 goto err_chip_exit;
3539         b43_qos_init(dev);
3540
3541 //FIXME
3542 #if 1
3543         b43_write16(dev, 0x0612, 0x0050);
3544         b43_shm_write16(dev, B43_SHM_SHARED, 0x0416, 0x0050);
3545         b43_shm_write16(dev, B43_SHM_SHARED, 0x0414, 0x01F4);
3546 #endif
3547
3548         b43_bluetooth_coext_enable(dev);
3549
3550         ssb_bus_powerup(bus, 1);        /* Enable dynamic PCTL */
3551         b43_upload_card_macaddress(dev);
3552         b43_security_init(dev);
3553         if (!dev->suspend_in_progress)
3554                 b43_rng_init(wl);
3555
3556         b43_set_status(dev, B43_STAT_INITIALIZED);
3557
3558         if (!dev->suspend_in_progress)
3559                 b43_leds_init(dev);
3560 out:
3561         return err;
3562
3563       err_chip_exit:
3564         b43_chip_exit(dev);
3565       err_kfree_tssitbl:
3566         if (phy->dyn_tssi_tbl)
3567                 kfree(phy->tssi2dbm);
3568       err_kfree_lo_control:
3569         kfree(phy->lo_control);
3570         phy->lo_control = NULL;
3571       err_busdown:
3572         ssb_bus_may_powerdown(bus);
3573         B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
3574         return err;
3575 }
3576
3577 static int b43_op_add_interface(struct ieee80211_hw *hw,
3578                                 struct ieee80211_if_init_conf *conf)
3579 {
3580         struct b43_wl *wl = hw_to_b43_wl(hw);
3581         struct b43_wldev *dev;
3582         unsigned long flags;
3583         int err = -EOPNOTSUPP;
3584
3585         /* TODO: allow WDS/AP devices to coexist */
3586
3587         if (conf->type != IEEE80211_IF_TYPE_AP &&
3588             conf->type != IEEE80211_IF_TYPE_STA &&
3589             conf->type != IEEE80211_IF_TYPE_WDS &&
3590             conf->type != IEEE80211_IF_TYPE_IBSS)
3591                 return -EOPNOTSUPP;
3592
3593         mutex_lock(&wl->mutex);
3594         if (wl->operating)
3595                 goto out_mutex_unlock;
3596
3597         b43dbg(wl, "Adding Interface type %d\n", conf->type);
3598
3599         dev = wl->current_dev;
3600         wl->operating = 1;
3601         wl->vif = conf->vif;
3602         wl->if_type = conf->type;
3603         memcpy(wl->mac_addr, conf->mac_addr, ETH_ALEN);
3604
3605         spin_lock_irqsave(&wl->irq_lock, flags);
3606         b43_adjust_opmode(dev);
3607         b43_upload_card_macaddress(dev);
3608         spin_unlock_irqrestore(&wl->irq_lock, flags);
3609
3610         err = 0;
3611  out_mutex_unlock:
3612         mutex_unlock(&wl->mutex);
3613
3614         return err;
3615 }
3616
3617 static void b43_op_remove_interface(struct ieee80211_hw *hw,
3618                                     struct ieee80211_if_init_conf *conf)
3619 {
3620         struct b43_wl *wl = hw_to_b43_wl(hw);
3621         struct b43_wldev *dev = wl->current_dev;
3622         unsigned long flags;
3623
3624         b43dbg(wl, "Removing Interface type %d\n", conf->type);
3625
3626         mutex_lock(&wl->mutex);
3627
3628         B43_WARN_ON(!wl->operating);
3629         B43_WARN_ON(wl->vif != conf->vif);
3630         wl->vif = NULL;
3631
3632         wl->operating = 0;
3633
3634         spin_lock_irqsave(&wl->irq_lock, flags);
3635         b43_adjust_opmode(dev);
3636         memset(wl->mac_addr, 0, ETH_ALEN);
3637         b43_upload_card_macaddress(dev);
3638         spin_unlock_irqrestore(&wl->irq_lock, flags);
3639
3640         mutex_unlock(&wl->mutex);
3641 }
3642
3643 static int b43_op_start(struct ieee80211_hw *hw)
3644 {
3645         struct b43_wl *wl = hw_to_b43_wl(hw);
3646         struct b43_wldev *dev = wl->current_dev;
3647         int did_init = 0;
3648         int err = 0;
3649         bool do_rfkill_exit = 0;
3650
3651         /* Kill all old instance specific information to make sure
3652          * the card won't use it in the short timeframe between start
3653          * and mac80211 reconfiguring it. */
3654         memset(wl->bssid, 0, ETH_ALEN);
3655         memset(wl->mac_addr, 0, ETH_ALEN);
3656         wl->filter_flags = 0;
3657         wl->radiotap_enabled = 0;
3658
3659         /* First register RFkill.
3660          * LEDs that are registered later depend on it. */
3661         b43_rfkill_init(dev);
3662
3663         mutex_lock(&wl->mutex);
3664
3665         if (b43_status(dev) < B43_STAT_INITIALIZED) {
3666                 err = b43_wireless_core_init(dev);
3667                 if (err) {
3668                         do_rfkill_exit = 1;
3669                         goto out_mutex_unlock;
3670                 }
3671                 did_init = 1;
3672         }
3673
3674         if (b43_status(dev) < B43_STAT_STARTED) {
3675                 err = b43_wireless_core_start(dev);
3676                 if (err) {
3677                         if (did_init)
3678                                 b43_wireless_core_exit(dev);
3679                         do_rfkill_exit = 1;
3680                         goto out_mutex_unlock;
3681                 }
3682         }
3683
3684  out_mutex_unlock:
3685         mutex_unlock(&wl->mutex);
3686
3687         if (do_rfkill_exit)
3688                 b43_rfkill_exit(dev);
3689
3690         return err;
3691 }
3692
3693 static void b43_op_stop(struct ieee80211_hw *hw)
3694 {
3695         struct b43_wl *wl = hw_to_b43_wl(hw);
3696         struct b43_wldev *dev = wl->current_dev;
3697
3698         b43_rfkill_exit(dev);
3699
3700         mutex_lock(&wl->mutex);
3701         if (b43_status(dev) >= B43_STAT_STARTED)
3702                 b43_wireless_core_stop(dev);
3703         b43_wireless_core_exit(dev);
3704         mutex_unlock(&wl->mutex);
3705 }
3706
3707 static int b43_op_set_retry_limit(struct ieee80211_hw *hw,
3708                                   u32 short_retry_limit, u32 long_retry_limit)
3709 {
3710         struct b43_wl *wl = hw_to_b43_wl(hw);
3711         struct b43_wldev *dev;
3712         int err = 0;
3713
3714         mutex_lock(&wl->mutex);
3715         dev = wl->current_dev;
3716         if (unlikely(!dev || (b43_status(dev) < B43_STAT_INITIALIZED))) {
3717                 err = -ENODEV;
3718                 goto out_unlock;
3719         }
3720         b43_set_retry_limits(dev, short_retry_limit, long_retry_limit);
3721 out_unlock:
3722         mutex_unlock(&wl->mutex);
3723
3724         return err;
3725 }
3726
3727 static int b43_op_beacon_set_tim(struct ieee80211_hw *hw, int aid, int set)
3728 {
3729         struct b43_wl *wl = hw_to_b43_wl(hw);
3730         struct sk_buff *beacon;
3731         unsigned long flags;
3732
3733         /* We could modify the existing beacon and set the aid bit in
3734          * the TIM field, but that would probably require resizing and
3735          * moving of data within the beacon template.
3736          * Simply request a new beacon and let mac80211 do the hard work. */
3737         beacon = ieee80211_beacon_get(hw, wl->vif, NULL);
3738         if (unlikely(!beacon))
3739                 return -ENOMEM;
3740         spin_lock_irqsave(&wl->irq_lock, flags);
3741         b43_update_templates(wl, beacon);
3742         spin_unlock_irqrestore(&wl->irq_lock, flags);
3743
3744         return 0;
3745 }
3746
3747 static int b43_op_ibss_beacon_update(struct ieee80211_hw *hw,
3748                                      struct sk_buff *beacon,
3749                                      struct ieee80211_tx_control *ctl)
3750 {
3751         struct b43_wl *wl = hw_to_b43_wl(hw);
3752         unsigned long flags;
3753
3754         spin_lock_irqsave(&wl->irq_lock, flags);
3755         b43_update_templates(wl, beacon);
3756         spin_unlock_irqrestore(&wl->irq_lock, flags);
3757
3758         return 0;
3759 }
3760
3761 static const struct ieee80211_ops b43_hw_ops = {
3762         .tx                     = b43_op_tx,
3763         .conf_tx                = b43_op_conf_tx,
3764         .add_interface          = b43_op_add_interface,
3765         .remove_interface       = b43_op_remove_interface,
3766         .config                 = b43_op_config,
3767         .config_interface       = b43_op_config_interface,
3768         .configure_filter       = b43_op_configure_filter,
3769         .set_key                = b43_op_set_key,
3770         .get_stats              = b43_op_get_stats,
3771         .get_tx_stats           = b43_op_get_tx_stats,
3772         .start                  = b43_op_start,
3773         .stop                   = b43_op_stop,
3774         .set_retry_limit        = b43_op_set_retry_limit,
3775         .set_tim                = b43_op_beacon_set_tim,
3776         .beacon_update          = b43_op_ibss_beacon_update,
3777 };
3778
3779 /* Hard-reset the chip. Do not call this directly.
3780  * Use b43_controller_restart()
3781  */
3782 static void b43_chip_reset(struct work_struct *work)
3783 {
3784         struct b43_wldev *dev =
3785             container_of(work, struct b43_wldev, restart_work);
3786         struct b43_wl *wl = dev->wl;
3787         int err = 0;
3788         int prev_status;
3789
3790         mutex_lock(&wl->mutex);
3791
3792         prev_status = b43_status(dev);
3793         /* Bring the device down... */
3794         if (prev_status >= B43_STAT_STARTED)
3795                 b43_wireless_core_stop(dev);
3796         if (prev_status >= B43_STAT_INITIALIZED)
3797                 b43_wireless_core_exit(dev);
3798
3799         /* ...and up again. */
3800         if (prev_status >= B43_STAT_INITIALIZED) {
3801                 err = b43_wireless_core_init(dev);
3802                 if (err)
3803                         goto out;
3804         }
3805         if (prev_status >= B43_STAT_STARTED) {
3806                 err = b43_wireless_core_start(dev);
3807                 if (err) {
3808                         b43_wireless_core_exit(dev);
3809                         goto out;
3810                 }
3811         }
3812       out:
3813         mutex_unlock(&wl->mutex);
3814         if (err)
3815                 b43err(wl, "Controller restart FAILED\n");
3816         else
3817                 b43info(wl, "Controller restarted\n");
3818 }
3819
3820 static int b43_setup_modes(struct b43_wldev *dev,
3821                            bool have_2ghz_phy, bool have_5ghz_phy)
3822 {
3823         struct ieee80211_hw *hw = dev->wl->hw;
3824         struct b43_phy *phy = &dev->phy;
3825
3826         /* XXX: This function will go away soon, when mac80211
3827          *      band stuff is rewritten. So this is just a hack.
3828          *      For now we always claim GPHY mode, as there is no
3829          *      support for NPHY and APHY in the device, yet.
3830          *      This assumption is OK, as any B, N or A PHY will already
3831          *      have died a horrible sanity check death earlier. */
3832
3833         hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &b43_band_2GHz;
3834         phy->possible_phymodes |= B43_PHYMODE_G;
3835
3836         return 0;
3837 }
3838
3839 static void b43_wireless_core_detach(struct b43_wldev *dev)
3840 {
3841         /* We release firmware that late to not be required to re-request
3842          * is all the time when we reinit the core. */
3843         b43_release_firmware(dev);
3844 }
3845
3846 static int b43_wireless_core_attach(struct b43_wldev *dev)
3847 {
3848         struct b43_wl *wl = dev->wl;
3849         struct ssb_bus *bus = dev->dev->bus;
3850         struct pci_dev *pdev = bus->host_pci;
3851         int err;
3852         bool have_2ghz_phy = 0, have_5ghz_phy = 0;
3853         u32 tmp;
3854
3855         /* Do NOT do any device initialization here.
3856          * Do it in wireless_core_init() instead.
3857          * This function is for gathering basic information about the HW, only.
3858          * Also some structs may be set up here. But most likely you want to have
3859          * that in core_init(), too.
3860          */
3861
3862         err = ssb_bus_powerup(bus, 0);
3863         if (err) {
3864                 b43err(wl, "Bus powerup failed\n");
3865                 goto out;
3866         }
3867         /* Get the PHY type. */
3868         if (dev->dev->id.revision >= 5) {
3869                 u32 tmshigh;
3870
3871                 tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH);
3872                 have_2ghz_phy = !!(tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY);
3873                 have_5ghz_phy = !!(tmshigh & B43_TMSHIGH_HAVE_5GHZ_PHY);
3874         } else
3875                 B43_WARN_ON(1);
3876
3877         dev->phy.gmode = have_2ghz_phy;
3878         tmp = dev->phy.gmode ? B43_TMSLOW_GMODE : 0;
3879         b43_wireless_core_reset(dev, tmp);
3880
3881         err = b43_phy_versioning(dev);
3882         if (err)
3883                 goto err_powerdown;
3884         /* Check if this device supports multiband. */
3885         if (!pdev ||
3886             (pdev->device != 0x4312 &&
3887              pdev->device != 0x4319 && pdev->device != 0x4324)) {
3888                 /* No multiband support. */
3889                 have_2ghz_phy = 0;
3890                 have_5ghz_phy = 0;
3891                 switch (dev->phy.type) {
3892                 case B43_PHYTYPE_A:
3893                         have_5ghz_phy = 1;
3894                         break;
3895                 case B43_PHYTYPE_G:
3896                 case B43_PHYTYPE_N:
3897                         have_2ghz_phy = 1;
3898                         break;
3899                 default:
3900                         B43_WARN_ON(1);
3901                 }
3902         }
3903         if (dev->phy.type == B43_PHYTYPE_A) {
3904                 /* FIXME */
3905                 b43err(wl, "IEEE 802.11a devices are unsupported\n");
3906                 err = -EOPNOTSUPP;
3907                 goto err_powerdown;
3908         }
3909         dev->phy.gmode = have_2ghz_phy;
3910         tmp = dev->phy.gmode ? B43_TMSLOW_GMODE : 0;
3911         b43_wireless_core_reset(dev, tmp);
3912
3913         err = b43_validate_chipaccess(dev);
3914         if (err)
3915                 goto err_powerdown;
3916         err = b43_setup_modes(dev, have_2ghz_phy, have_5ghz_phy);
3917         if (err)
3918                 goto err_powerdown;
3919
3920         /* Now set some default "current_dev" */
3921         if (!wl->current_dev)
3922                 wl->current_dev = dev;
3923         INIT_WORK(&dev->restart_work, b43_chip_reset);
3924
3925         b43_radio_turn_off(dev, 1);
3926         b43_switch_analog(dev, 0);
3927         ssb_device_disable(dev->dev, 0);
3928         ssb_bus_may_powerdown(bus);
3929
3930 out:
3931         return err;
3932
3933 err_powerdown:
3934         ssb_bus_may_powerdown(bus);
3935         return err;
3936 }
3937
3938 static void b43_one_core_detach(struct ssb_device *dev)
3939 {
3940         struct b43_wldev *wldev;
3941         struct b43_wl *wl;
3942
3943         wldev = ssb_get_drvdata(dev);
3944         wl = wldev->wl;
3945         cancel_work_sync(&wldev->restart_work);
3946         b43_debugfs_remove_device(wldev);
3947         b43_wireless_core_detach(wldev);
3948         list_del(&wldev->list);
3949         wl->nr_devs--;
3950         ssb_set_drvdata(dev, NULL);
3951         kfree(wldev);
3952 }
3953
3954 static int b43_one_core_attach(struct ssb_device *dev, struct b43_wl *wl)
3955 {
3956         struct b43_wldev *wldev;
3957         struct pci_dev *pdev;
3958         int err = -ENOMEM;
3959
3960         if (!list_empty(&wl->devlist)) {
3961                 /* We are not the first core on this chip. */
3962                 pdev = dev->bus->host_pci;
3963                 /* Only special chips support more than one wireless
3964                  * core, although some of the other chips have more than
3965                  * one wireless core as well. Check for this and
3966                  * bail out early.
3967                  */
3968                 if (!pdev ||
3969                     ((pdev->device != 0x4321) &&
3970                      (pdev->device != 0x4313) && (pdev->device != 0x431A))) {
3971                         b43dbg(wl, "Ignoring unconnected 802.11 core\n");
3972                         return -ENODEV;
3973                 }
3974         }
3975
3976         wldev = kzalloc(sizeof(*wldev), GFP_KERNEL);
3977         if (!wldev)
3978                 goto out;
3979
3980         wldev->dev = dev;
3981         wldev->wl = wl;
3982         b43_set_status(wldev, B43_STAT_UNINIT);
3983         wldev->bad_frames_preempt = modparam_bad_frames_preempt;
3984         tasklet_init(&wldev->isr_tasklet,
3985                      (void (*)(unsigned long))b43_interrupt_tasklet,
3986                      (unsigned long)wldev);
3987         INIT_LIST_HEAD(&wldev->list);
3988
3989         err = b43_wireless_core_attach(wldev);
3990         if (err)
3991                 goto err_kfree_wldev;
3992
3993         list_add(&wldev->list, &wl->devlist);
3994         wl->nr_devs++;
3995         ssb_set_drvdata(dev, wldev);
3996         b43_debugfs_add_device(wldev);
3997
3998       out:
3999         return err;
4000
4001       err_kfree_wldev:
4002         kfree(wldev);
4003         return err;
4004 }
4005
4006 static void b43_sprom_fixup(struct ssb_bus *bus)
4007 {
4008         /* boardflags workarounds */
4009         if (bus->boardinfo.vendor == SSB_BOARDVENDOR_DELL &&
4010             bus->chip_id == 0x4301 && bus->boardinfo.rev == 0x74)
4011                 bus->sprom.boardflags_lo |= B43_BFL_BTCOEXIST;
4012         if (bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE &&
4013             bus->boardinfo.type == 0x4E && bus->boardinfo.rev > 0x40)
4014                 bus->sprom.boardflags_lo |= B43_BFL_PACTRL;
4015 }
4016
4017 static void b43_wireless_exit(struct ssb_device *dev, struct b43_wl *wl)
4018 {
4019         struct ieee80211_hw *hw = wl->hw;
4020
4021         ssb_set_devtypedata(dev, NULL);
4022         ieee80211_free_hw(hw);
4023 }
4024
4025 static int b43_wireless_init(struct ssb_device *dev)
4026 {
4027         struct ssb_sprom *sprom = &dev->bus->sprom;
4028         struct ieee80211_hw *hw;
4029         struct b43_wl *wl;
4030         int err = -ENOMEM;
4031
4032         b43_sprom_fixup(dev->bus);
4033
4034         hw = ieee80211_alloc_hw(sizeof(*wl), &b43_hw_ops);
4035         if (!hw) {
4036                 b43err(NULL, "Could not allocate ieee80211 device\n");
4037                 goto out;
4038         }
4039
4040         /* fill hw info */
4041         hw->flags = IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE |
4042                     IEEE80211_HW_RX_INCLUDES_FCS;
4043         hw->max_signal = 100;
4044         hw->max_rssi = -110;
4045         hw->max_noise = -110;
4046         hw->queues = 1;         /* FIXME: hardware has more queues */
4047         SET_IEEE80211_DEV(hw, dev->dev);
4048         if (is_valid_ether_addr(sprom->et1mac))
4049                 SET_IEEE80211_PERM_ADDR(hw, sprom->et1mac);
4050         else
4051                 SET_IEEE80211_PERM_ADDR(hw, sprom->il0mac);
4052
4053         /* Get and initialize struct b43_wl */
4054         wl = hw_to_b43_wl(hw);
4055         memset(wl, 0, sizeof(*wl));
4056         wl->hw = hw;
4057         spin_lock_init(&wl->irq_lock);
4058         spin_lock_init(&wl->leds_lock);
4059         spin_lock_init(&wl->shm_lock);
4060         mutex_init(&wl->mutex);
4061         INIT_LIST_HEAD(&wl->devlist);
4062
4063         ssb_set_devtypedata(dev, wl);
4064         b43info(wl, "Broadcom %04X WLAN found\n", dev->bus->chip_id);
4065         err = 0;
4066       out:
4067         return err;
4068 }
4069
4070 static int b43_probe(struct ssb_device *dev, const struct ssb_device_id *id)
4071 {
4072         struct b43_wl *wl;
4073         int err;
4074         int first = 0;
4075
4076         wl = ssb_get_devtypedata(dev);
4077         if (!wl) {
4078                 /* Probing the first core. Must setup common struct b43_wl */
4079                 first = 1;
4080                 err = b43_wireless_init(dev);
4081                 if (err)
4082                         goto out;
4083                 wl = ssb_get_devtypedata(dev);
4084                 B43_WARN_ON(!wl);
4085         }
4086         err = b43_one_core_attach(dev, wl);
4087         if (err)
4088                 goto err_wireless_exit;
4089
4090         if (first) {
4091                 err = ieee80211_register_hw(wl->hw);
4092                 if (err)
4093                         goto err_one_core_detach;
4094         }
4095
4096       out:
4097         return err;
4098
4099       err_one_core_detach:
4100         b43_one_core_detach(dev);
4101       err_wireless_exit:
4102         if (first)
4103                 b43_wireless_exit(dev, wl);
4104         return err;
4105 }
4106
4107 static void b43_remove(struct ssb_device *dev)
4108 {
4109         struct b43_wl *wl = ssb_get_devtypedata(dev);
4110         struct b43_wldev *wldev = ssb_get_drvdata(dev);
4111
4112         B43_WARN_ON(!wl);
4113         if (wl->current_dev == wldev)
4114                 ieee80211_unregister_hw(wl->hw);
4115
4116         b43_one_core_detach(dev);
4117
4118         if (list_empty(&wl->devlist)) {
4119                 /* Last core on the chip unregistered.
4120                  * We can destroy common struct b43_wl.
4121                  */
4122                 b43_wireless_exit(dev, wl);
4123         }
4124 }
4125
4126 /* Perform a hardware reset. This can be called from any context. */
4127 void b43_controller_restart(struct b43_wldev *dev, const char *reason)
4128 {
4129         /* Must avoid requeueing, if we are in shutdown. */
4130         if (b43_status(dev) < B43_STAT_INITIALIZED)
4131                 return;
4132         b43info(dev->wl, "Controller RESET (%s) ...\n", reason);
4133         queue_work(dev->wl->hw->workqueue, &dev->restart_work);
4134 }
4135
4136 #ifdef CONFIG_PM
4137
4138 static int b43_suspend(struct ssb_device *dev, pm_message_t state)
4139 {
4140         struct b43_wldev *wldev = ssb_get_drvdata(dev);
4141         struct b43_wl *wl = wldev->wl;
4142
4143         b43dbg(wl, "Suspending...\n");
4144
4145         mutex_lock(&wl->mutex);
4146         wldev->suspend_in_progress = true;
4147         wldev->suspend_init_status = b43_status(wldev);
4148         if (wldev->suspend_init_status >= B43_STAT_STARTED)
4149                 b43_wireless_core_stop(wldev);
4150         if (wldev->suspend_init_status >= B43_STAT_INITIALIZED)
4151                 b43_wireless_core_exit(wldev);
4152         mutex_unlock(&wl->mutex);
4153
4154         b43dbg(wl, "Device suspended.\n");
4155
4156         return 0;
4157 }
4158
4159 static int b43_resume(struct ssb_device *dev)
4160 {
4161         struct b43_wldev *wldev = ssb_get_drvdata(dev);
4162         struct b43_wl *wl = wldev->wl;
4163         int err = 0;
4164
4165         b43dbg(wl, "Resuming...\n");
4166
4167         mutex_lock(&wl->mutex);
4168         if (wldev->suspend_init_status >= B43_STAT_INITIALIZED) {
4169                 err = b43_wireless_core_init(wldev);
4170                 if (err) {
4171                         b43err(wl, "Resume failed at core init\n");
4172                         goto out;
4173                 }
4174         }
4175         if (wldev->suspend_init_status >= B43_STAT_STARTED) {
4176                 err = b43_wireless_core_start(wldev);
4177                 if (err) {
4178                         b43_leds_exit(wldev);
4179                         b43_rng_exit(wldev->wl, true);
4180                         b43_wireless_core_exit(wldev);
4181                         b43err(wl, "Resume failed at core start\n");
4182                         goto out;
4183                 }
4184         }
4185         b43dbg(wl, "Device resumed.\n");
4186  out:
4187         wldev->suspend_in_progress = false;
4188         mutex_unlock(&wl->mutex);
4189         return err;
4190 }
4191
4192 #else /* CONFIG_PM */
4193 # define b43_suspend    NULL
4194 # define b43_resume     NULL
4195 #endif /* CONFIG_PM */
4196
4197 static struct ssb_driver b43_ssb_driver = {
4198         .name           = KBUILD_MODNAME,
4199         .id_table       = b43_ssb_tbl,
4200         .probe          = b43_probe,
4201         .remove         = b43_remove,
4202         .suspend        = b43_suspend,
4203         .resume         = b43_resume,
4204 };
4205
4206 static void b43_print_driverinfo(void)
4207 {
4208         const char *feat_pci = "", *feat_pcmcia = "", *feat_nphy = "",
4209                    *feat_leds = "", *feat_rfkill = "";
4210
4211 #ifdef CONFIG_B43_PCI_AUTOSELECT
4212         feat_pci = "P";
4213 #endif
4214 #ifdef CONFIG_B43_PCMCIA
4215         feat_pcmcia = "M";
4216 #endif
4217 #ifdef CONFIG_B43_NPHY
4218         feat_nphy = "N";
4219 #endif
4220 #ifdef CONFIG_B43_LEDS
4221         feat_leds = "L";
4222 #endif
4223 #ifdef CONFIG_B43_RFKILL
4224         feat_rfkill = "R";
4225 #endif
4226         printk(KERN_INFO "Broadcom 43xx driver loaded "
4227                "[ Features: %s%s%s%s%s, Firmware-ID: "
4228                B43_SUPPORTED_FIRMWARE_ID " ]\n",
4229                feat_pci, feat_pcmcia, feat_nphy,
4230                feat_leds, feat_rfkill);
4231 }
4232
4233 static int __init b43_init(void)
4234 {
4235         int err;
4236
4237         b43_debugfs_init();
4238         err = b43_pcmcia_init();
4239         if (err)
4240                 goto err_dfs_exit;
4241         err = ssb_driver_register(&b43_ssb_driver);
4242         if (err)
4243                 goto err_pcmcia_exit;
4244         b43_print_driverinfo();
4245
4246         return err;
4247
4248 err_pcmcia_exit:
4249         b43_pcmcia_exit();
4250 err_dfs_exit:
4251         b43_debugfs_exit();
4252         return err;
4253 }
4254
4255 static void __exit b43_exit(void)
4256 {
4257         ssb_driver_unregister(&b43_ssb_driver);
4258         b43_pcmcia_exit();
4259         b43_debugfs_exit();
4260 }
4261
4262 module_init(b43_init)
4263 module_exit(b43_exit)