drivers/net/wireless/b43/phy_lp.c

   1 /*
   2
   3   Broadcom B43 wireless driver
   4   IEEE 802.11g LP-PHY driver
   5
   6   Copyright (c) 2008-2009 Michael Buesch <mb@bu3sch.de>
   7
   8   This program is free software; you can redistribute it and/or modify
   9   it under the terms of the GNU General Public License as published by
  10   the Free Software Foundation; either version 2 of the License, or
  11   (at your option) any later version.
  12
  13   This program is distributed in the hope that it will be useful,
  14   but WITHOUT ANY WARRANTY; without even the implied warranty of
  15   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16   GNU General Public License for more details.
  17
  18   You should have received a copy of the GNU General Public License
  19   along with this program; see the file COPYING.  If not, write to
  20   the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
  21   Boston, MA 02110-1301, USA.
  22
  23 */
  24
  25 #include "b43.h"
  26 #include "phy_lp.h"
  27 #include "phy_common.h"
  28 #include "tables_lpphy.h"
  29
  30
  31 static int b43_lpphy_op_allocate(struct b43_wldev *dev)
  32 {
  33         struct b43_phy_lp *lpphy;
  34
  35         lpphy = kzalloc(sizeof(*lpphy), GFP_KERNEL);
  36         if (!lpphy)
  37                 return -ENOMEM;
  38         dev->phy.lp = lpphy;
  39
  40         return 0;
  41 }
  42
  43 static void b43_lpphy_op_prepare_structs(struct b43_wldev *dev)
  44 {
  45         struct b43_phy *phy = &dev->phy;
  46         struct b43_phy_lp *lpphy = phy->lp;
  47
  48         memset(lpphy, 0, sizeof(*lpphy));
  49
  50         //TODO
  51 }
  52
  53 static void b43_lpphy_op_free(struct b43_wldev *dev)
  54 {
  55         struct b43_phy_lp *lpphy = dev->phy.lp;
  56
  57         kfree(lpphy);
  58         dev->phy.lp = NULL;
  59 }
  60
  61 static void lpphy_table_init(struct b43_wldev *dev)
  62 {
  63         //TODO
  64 }
  65
  66 static void lpphy_baseband_rev0_1_init(struct b43_wldev *dev)
  67 {
  68         B43_WARN_ON(1);//TODO rev < 2 not supported, yet.
  69 }
  70
  71 static void lpphy_baseband_rev2plus_init(struct b43_wldev *dev)
  72 {
  73         struct ssb_bus *bus = dev->dev->bus;
  74         struct b43_phy_lp *lpphy = dev->phy.lp;
  75
  76         b43_phy_write(dev, B43_LPPHY_AFE_DAC_CTL, 0x50);
  77         b43_phy_write(dev, B43_LPPHY_AFE_CTL, 0x8800);
  78         b43_phy_write(dev, B43_LPPHY_AFE_CTL_OVR, 0);
  79         b43_phy_write(dev, B43_LPPHY_AFE_CTL_OVRVAL, 0);
  80         b43_phy_write(dev, B43_LPPHY_RF_OVERRIDE_0, 0);
  81         b43_phy_write(dev, B43_LPPHY_RF_OVERRIDE_2, 0);
  82         b43_phy_write(dev, B43_PHY_OFDM(0xF9), 0);
  83         b43_phy_write(dev, B43_LPPHY_TR_LOOKUP_1, 0);
  84         b43_phy_set(dev, B43_LPPHY_ADC_COMPENSATION_CTL, 0x10);
  85         b43_phy_maskset(dev, B43_LPPHY_OFDMSYNCTHRESH0, 0xFF00, 0x78);
  86         b43_phy_maskset(dev, B43_LPPHY_DCOFFSETTRANSIENT, 0xF8FF, 0x200);
  87         b43_phy_maskset(dev, B43_LPPHY_DCOFFSETTRANSIENT, 0xFF00, 0x7F);
  88         b43_phy_maskset(dev, B43_LPPHY_GAINDIRECTMISMATCH, 0xFF0F, 0x40);
  89         b43_phy_maskset(dev, B43_LPPHY_PREAMBLECONFIRMTO, 0xFF00, 0x2);
  90         b43_phy_mask(dev, B43_LPPHY_CRSGAIN_CTL, ~0x4000);
  91         b43_phy_mask(dev, B43_LPPHY_CRSGAIN_CTL, ~0x2000);
  92         b43_phy_set(dev, B43_PHY_OFDM(0x10A), 0x1);
  93         b43_phy_maskset(dev, B43_PHY_OFDM(0x10A), 0xFF01, 0x10);
  94         b43_phy_maskset(dev, B43_PHY_OFDM(0xDF), 0xFF00, 0xF4);
  95         b43_phy_maskset(dev, B43_PHY_OFDM(0xDF), 0x00FF, 0xF100);
  96         b43_phy_write(dev, B43_LPPHY_CLIPTHRESH, 0x48);
  97         b43_phy_maskset(dev, B43_LPPHY_HIGAINDB, 0xFF00, 0x46);
  98         b43_phy_maskset(dev, B43_PHY_OFDM(0xE4), 0xFF00, 0x10);
  99         b43_phy_maskset(dev, B43_LPPHY_PWR_THRESH1, 0xFFF0, 0x9);
 100         b43_phy_mask(dev, B43_LPPHY_GAINDIRECTMISMATCH, ~0xF);
 101         b43_phy_maskset(dev, B43_LPPHY_VERYLOWGAINDB, 0x00FF, 0x5500);
 102         b43_phy_maskset(dev, B43_LPPHY_CLIPCTRTHRESH, 0xF81F, 0xA0);
 103         b43_phy_maskset(dev, B43_LPPHY_GAINDIRECTMISMATCH, 0xE0FF, 0x300);
 104         b43_phy_maskset(dev, B43_LPPHY_HIGAINDB, 0x00FF, 0x2A00);
 105         if ((bus->chip_id == 0x4325) && (bus->chip_rev == 0)) {
 106                 b43_phy_maskset(dev, B43_LPPHY_LOWGAINDB, 0x00FF, 0x2100);
 107                 b43_phy_maskset(dev, B43_LPPHY_VERYLOWGAINDB, 0xFF00, 0xA);
 108         } else {
 109                 b43_phy_maskset(dev, B43_LPPHY_LOWGAINDB, 0x00FF, 0x1E00);
 110                 b43_phy_maskset(dev, B43_LPPHY_VERYLOWGAINDB, 0xFF00, 0xD);
 111         }
 112         b43_phy_maskset(dev, B43_PHY_OFDM(0xFE), 0xFFE0, 0x1F);
 113         b43_phy_maskset(dev, B43_PHY_OFDM(0xFF), 0xFFE0, 0xC);
 114         b43_phy_maskset(dev, B43_PHY_OFDM(0x100), 0xFF00, 0x19);
 115         b43_phy_maskset(dev, B43_PHY_OFDM(0xFF), 0x03FF, 0x3C00);
 116         b43_phy_maskset(dev, B43_PHY_OFDM(0xFE), 0xFC1F, 0x3E0);
 117         b43_phy_maskset(dev, B43_PHY_OFDM(0xFF), 0xFFE0, 0xC);
 118         b43_phy_maskset(dev, B43_PHY_OFDM(0x100), 0x00FF, 0x1900);
 119         b43_phy_maskset(dev, B43_LPPHY_CLIPCTRTHRESH, 0x83FF, 0x5800);
 120         b43_phy_maskset(dev, B43_LPPHY_CLIPCTRTHRESH, 0xFFE0, 0x12);
 121         b43_phy_maskset(dev, B43_LPPHY_GAINMISMATCH, 0x0FFF, 0x9000);
 122
 123         b43_lptab_write(dev, B43_LPTAB16(0x08, 0x14), 0);
 124         b43_lptab_write(dev, B43_LPTAB16(0x08, 0x12), 0x40);
 125
 126         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
 127                 b43_phy_set(dev, B43_LPPHY_CRSGAIN_CTL, 0x40);
 128                 b43_phy_maskset(dev, B43_LPPHY_CRSGAIN_CTL, 0xF0FF, 0xB00);
 129                 b43_phy_maskset(dev, B43_LPPHY_SYNCPEAKCNT, 0xFFF8, 0x6);
 130                 b43_phy_maskset(dev, B43_LPPHY_MINPWR_LEVEL, 0x00FF, 0x9D00);
 131                 b43_phy_maskset(dev, B43_LPPHY_MINPWR_LEVEL, 0xFF00, 0xA1);
 132         } else /* 5GHz */
 133                 b43_phy_mask(dev, B43_LPPHY_CRSGAIN_CTL, ~0x40);
 134
 135         b43_phy_maskset(dev, B43_LPPHY_CRS_ED_THRESH, 0xFF00, 0xB3);
 136         b43_phy_maskset(dev, B43_LPPHY_CRS_ED_THRESH, 0x00FF, 0xAD00);
 137         b43_phy_maskset(dev, B43_LPPHY_INPUT_PWRDB, 0xFF00, lpphy->rx_pwr_offset);
 138         b43_phy_set(dev, B43_LPPHY_RESET_CTL, 0x44);
 139         b43_phy_write(dev, B43_LPPHY_RESET_CTL, 0x80);
 140         b43_phy_write(dev, B43_LPPHY_AFE_RSSI_CTL_0, 0xA954);
 141         b43_phy_write(dev, B43_LPPHY_AFE_RSSI_CTL_1,
 142                       0x2000 | ((u16)lpphy->rssi_gs << 10) |
 143                       ((u16)lpphy->rssi_vc << 4) | lpphy->rssi_vf);
 144 }
 145
 146 static void lpphy_baseband_init(struct b43_wldev *dev)
 147 {
 148         lpphy_table_init(dev);
 149         if (dev->phy.rev >= 2)
 150                 lpphy_baseband_rev2plus_init(dev);
 151         else
 152                 lpphy_baseband_rev0_1_init(dev);
 153 }
 154
 155 struct b2062_freqdata {
 156         u16 freq;
 157         u8 data[6];
 158 };
 159
 160 /* Initialize the 2062 radio. */
 161 static void lpphy_2062_init(struct b43_wldev *dev)
 162 {
 163         u32 crystalfreq, pdiv, tmp, ref;
 164         unsigned int i;
 165         const struct b2062_freqdata *fd = NULL;
 166
 167         static const struct b2062_freqdata freqdata_tab[] = {
 168                 { .freq = 12000, .data[0] =  6, .data[1] =  6, .data[2] =  6,
 169                                  .data[3] =  6, .data[4] = 10, .data[5] =  6, },
 170                 { .freq = 13000, .data[0] =  4, .data[1] =  4, .data[2] =  4,
 171                                  .data[3] =  4, .data[4] = 11, .data[5] =  7, },
 172                 { .freq = 14400, .data[0] =  3, .data[1] =  3, .data[2] =  3,
 173                                  .data[3] =  3, .data[4] = 12, .data[5] =  7, },
 174                 { .freq = 16200, .data[0] =  3, .data[1] =  3, .data[2] =  3,
 175                                  .data[3] =  3, .data[4] = 13, .data[5] =  8, },
 176                 { .freq = 18000, .data[0] =  2, .data[1] =  2, .data[2] =  2,
 177                                  .data[3] =  2, .data[4] = 14, .data[5] =  8, },
 178                 { .freq = 19200, .data[0] =  1, .data[1] =  1, .data[2] =  1,
 179                                  .data[3] =  1, .data[4] = 14, .data[5] =  9, },
 180         };
 181
 182         b2062_upload_init_table(dev);
 183
 184         b43_radio_write(dev, B2062_N_TX_CTL3, 0);
 185         b43_radio_write(dev, B2062_N_TX_CTL4, 0);
 186         b43_radio_write(dev, B2062_N_TX_CTL5, 0);
 187         b43_radio_write(dev, B2062_N_PDN_CTL0, 0x40);
 188         b43_radio_write(dev, B2062_N_PDN_CTL0, 0);
 189         b43_radio_write(dev, B2062_N_CALIB_TS, 0x10);
 190         b43_radio_write(dev, B2062_N_CALIB_TS, 0);
 191         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
 192                 b43_radio_set(dev, B2062_N_TSSI_CTL0, 0x1);
 193         else
 194                 b43_radio_mask(dev, B2062_N_TSSI_CTL0, ~0x1);
 195
 196         crystalfreq = 0;//FIXME
 197
 198         if (crystalfreq >= 30000000) {
 199                 pdiv = 1;
 200                 b43_radio_mask(dev, B2062_S_RFPLL_CTL1, 0xFFFB);
 201         } else {
 202                 pdiv = 2;
 203                 b43_radio_set(dev, B2062_S_RFPLL_CTL1, 0x4);
 204         }
 205
 206         tmp = (800000000 * pdiv + crystalfreq) / (32000000 * pdiv);
 207         tmp = (tmp - 1) & 0xFF;
 208         b43_radio_write(dev, B2062_S_RFPLL_CTL18, tmp);
 209
 210         tmp = (2 * crystalfreq + 1000000 * pdiv) / (2000000 * pdiv);
 211         tmp = ((tmp & 0xFF) - 1) & 0xFFFF;
 212         b43_radio_write(dev, B2062_S_RFPLL_CTL19, tmp);
 213
 214         ref = (1000 * pdiv + 2 * crystalfreq) / (2000 * pdiv);
 215         ref &= 0xFFFF;
 216         for (i = 0; i < ARRAY_SIZE(freqdata_tab); i++) {
 217                 if (ref < freqdata_tab[i].freq) {
 218                         fd = &freqdata_tab[i];
 219                         break;
 220                 }
 221         }
 222         if (B43_WARN_ON(!fd))
 223                 return;
 224
 225         b43_radio_write(dev, B2062_S_RFPLL_CTL8,
 226                         ((u16)(fd->data[1]) << 4) | fd->data[0]);
 227         b43_radio_write(dev, B2062_S_RFPLL_CTL9,
 228                         ((u16)(fd->data[3]) << 4) | fd->data[2]);//FIXME specs are different
 229         b43_radio_write(dev, B2062_S_RFPLL_CTL10, fd->data[4]);
 230         b43_radio_write(dev, B2062_S_RFPLL_CTL11, fd->data[5]);
 231 }
 232
 233 /* Initialize the 2063 radio. */
 234 static void lpphy_2063_init(struct b43_wldev *dev)
 235 {
 236         //TODO
 237 }
 238
 239 static void lpphy_sync_stx(struct b43_wldev *dev)
 240 {
 241         //TODO
 242 }
 243
 244 static void lpphy_radio_init(struct b43_wldev *dev)
 245 {
 246         /* The radio is attached through the 4wire bus. */
 247         b43_phy_set(dev, B43_LPPHY_FOURWIRE_CTL, 0x2);
 248         udelay(1);
 249         b43_phy_mask(dev, B43_LPPHY_FOURWIRE_CTL, 0xFFFD);
 250         udelay(1);
 251
 252         if (dev->phy.rev < 2) {
 253                 lpphy_2062_init(dev);
 254         } else {
 255                 lpphy_2063_init(dev);
 256                 lpphy_sync_stx(dev);
 257                 b43_phy_write(dev, B43_PHY_OFDM(0xF0), 0x5F80);
 258                 b43_phy_write(dev, B43_PHY_OFDM(0xF1), 0);
 259                 //TODO Do something on the backplane
 260         }
 261 }
 262
 263 static int b43_lpphy_op_init(struct b43_wldev *dev)
 264 {
 265         /* TODO: band SPROM */
 266         lpphy_baseband_init(dev);
 267         lpphy_radio_init(dev);
 268
 269         //TODO
 270
 271         return 0;
 272 }
 273
 274 static u16 b43_lpphy_op_read(struct b43_wldev *dev, u16 reg)
 275 {
 276         b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
 277         return b43_read16(dev, B43_MMIO_PHY_DATA);
 278 }
 279
 280 static void b43_lpphy_op_write(struct b43_wldev *dev, u16 reg, u16 value)
 281 {
 282         b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
 283         b43_write16(dev, B43_MMIO_PHY_DATA, value);
 284 }
 285
 286 static u16 b43_lpphy_op_radio_read(struct b43_wldev *dev, u16 reg)
 287 {
 288         /* Register 1 is a 32-bit register. */
 289         B43_WARN_ON(reg == 1);
 290         /* LP-PHY needs a special bit set for read access */
 291         if (dev->phy.rev < 2) {
 292                 if (reg != 0x4001)
 293                         reg |= 0x100;
 294         } else
 295                 reg |= 0x200;
 296
 297         b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
 298         return b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
 299 }
 300
 301 static void b43_lpphy_op_radio_write(struct b43_wldev *dev, u16 reg, u16 value)
 302 {
 303         /* Register 1 is a 32-bit register. */
 304         B43_WARN_ON(reg == 1);
 305
 306         b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
 307         b43_write16(dev, B43_MMIO_RADIO_DATA_LOW, value);
 308 }
 309
 310 static void b43_lpphy_op_software_rfkill(struct b43_wldev *dev,
 311                                          enum rfkill_state state)
 312 {
 313         //TODO
 314 }
 315
 316 static int b43_lpphy_op_switch_channel(struct b43_wldev *dev,
 317                                        unsigned int new_channel)
 318 {
 319         //TODO
 320         return 0;
 321 }
 322
 323 static unsigned int b43_lpphy_op_get_default_chan(struct b43_wldev *dev)
 324 {
 325         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
 326                 return 1;
 327         return 36;
 328 }
 329
 330 static void b43_lpphy_op_set_rx_antenna(struct b43_wldev *dev, int antenna)
 331 {
 332         //TODO
 333 }
 334
 335 static void b43_lpphy_op_adjust_txpower(struct b43_wldev *dev)
 336 {
 337         //TODO
 338 }
 339
 340 static enum b43_txpwr_result b43_lpphy_op_recalc_txpower(struct b43_wldev *dev,
 341                                                          bool ignore_tssi)
 342 {
 343         //TODO
 344         return B43_TXPWR_RES_DONE;
 345 }
 346
 347
 348 const struct b43_phy_operations b43_phyops_lp = {
 349         .allocate               = b43_lpphy_op_allocate,
 350         .free                   = b43_lpphy_op_free,
 351         .prepare_structs        = b43_lpphy_op_prepare_structs,
 352         .init                   = b43_lpphy_op_init,
 353         .phy_read               = b43_lpphy_op_read,
 354         .phy_write              = b43_lpphy_op_write,
 355         .radio_read             = b43_lpphy_op_radio_read,
 356         .radio_write            = b43_lpphy_op_radio_write,
 357         .software_rfkill        = b43_lpphy_op_software_rfkill,
 358         .switch_analog          = b43_phyop_switch_analog_generic,
 359         .switch_channel         = b43_lpphy_op_switch_channel,
 360         .get_default_chan       = b43_lpphy_op_get_default_chan,
 361         .set_rx_antenna         = b43_lpphy_op_set_rx_antenna,
 362         .recalc_txpower         = b43_lpphy_op_recalc_txpower,
 363         .adjust_txpower         = b43_lpphy_op_adjust_txpower,
 364 };