3 Broadcom BCM43xx wireless driver
5 Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>,
6 Stefano Brivio <st3@riseup.net>
7 Michael Buesch <mbuesch@freenet.de>
8 Danny van Dyk <kugelfang@gentoo.org>
9 Andreas Jaggi <andreas.jaggi@waterwave.ch>
11 Some parts of the code in this file are derived from the ipw2200
12 driver Copyright(c) 2003 - 2004 Intel Corporation.
14 This program is free software; you can redistribute it and/or modify
15 it under the terms of the GNU General Public License as published by
16 the Free Software Foundation; either version 2 of the License, or
17 (at your option) any later version.
19 This program is distributed in the hope that it will be useful,
20 but WITHOUT ANY WARRANTY; without even the implied warranty of
21 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 GNU General Public License for more details.
24 You should have received a copy of the GNU General Public License
25 along with this program; see the file COPYING. If not, write to
26 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
27 Boston, MA 02110-1301, USA.
31 #include <linux/delay.h>
32 #include <linux/init.h>
33 #include <linux/moduleparam.h>
34 #include <linux/if_arp.h>
35 #include <linux/etherdevice.h>
36 #include <linux/version.h>
37 #include <linux/firmware.h>
38 #include <linux/wireless.h>
39 #include <linux/workqueue.h>
40 #include <linux/skbuff.h>
41 #include <net/iw_handler.h>
44 #include "bcm43xx_main.h"
45 #include "bcm43xx_debugfs.h"
46 #include "bcm43xx_radio.h"
47 #include "bcm43xx_phy.h"
48 #include "bcm43xx_dma.h"
49 #include "bcm43xx_pio.h"
50 #include "bcm43xx_power.h"
51 #include "bcm43xx_wx.h"
52 #include "bcm43xx_ethtool.h"
53 #include "bcm43xx_xmit.h"
56 MODULE_DESCRIPTION("Broadcom BCM43xx wireless driver");
57 MODULE_AUTHOR("Martin Langer");
58 MODULE_AUTHOR("Stefano Brivio");
59 MODULE_AUTHOR("Michael Buesch");
60 MODULE_LICENSE("GPL");
62 #ifdef CONFIG_BCM947XX
63 extern char *nvram_get(char *name);
66 #if defined(CONFIG_BCM43XX_DMA) && defined(CONFIG_BCM43XX_PIO)
67 static int modparam_pio;
68 module_param_named(pio, modparam_pio, int, 0444);
69 MODULE_PARM_DESC(pio, "enable(1) / disable(0) PIO mode");
70 #elif defined(CONFIG_BCM43XX_DMA)
71 # define modparam_pio 0
72 #elif defined(CONFIG_BCM43XX_PIO)
73 # define modparam_pio 1
76 static int modparam_bad_frames_preempt;
77 module_param_named(bad_frames_preempt, modparam_bad_frames_preempt, int, 0444);
78 MODULE_PARM_DESC(bad_frames_preempt, "enable(1) / disable(0) Bad Frames Preemption");
80 static int modparam_short_retry = BCM43xx_DEFAULT_SHORT_RETRY_LIMIT;
81 module_param_named(short_retry, modparam_short_retry, int, 0444);
82 MODULE_PARM_DESC(short_retry, "Short-Retry-Limit (0 - 15)");
84 static int modparam_long_retry = BCM43xx_DEFAULT_LONG_RETRY_LIMIT;
85 module_param_named(long_retry, modparam_long_retry, int, 0444);
86 MODULE_PARM_DESC(long_retry, "Long-Retry-Limit (0 - 15)");
88 static int modparam_locale = -1;
89 module_param_named(locale, modparam_locale, int, 0444);
90 MODULE_PARM_DESC(country, "Select LocaleCode 0-11 (For travelers)");
92 static int modparam_noleds;
93 module_param_named(noleds, modparam_noleds, int, 0444);
94 MODULE_PARM_DESC(noleds, "Turn off all LED activity");
96 #ifdef CONFIG_BCM43XX_DEBUG
97 static char modparam_fwpostfix[64];
98 module_param_string(fwpostfix, modparam_fwpostfix, 64, 0444);
99 MODULE_PARM_DESC(fwpostfix, "Postfix for .fw files. Useful for debugging.");
101 # define modparam_fwpostfix ""
102 #endif /* CONFIG_BCM43XX_DEBUG*/
105 /* If you want to debug with just a single device, enable this,
106 * where the string is the pci device ID (as given by the kernel's
107 * pci_name function) of the device to be used.
109 //#define DEBUG_SINGLE_DEVICE_ONLY "0001:11:00.0"
111 /* If you want to enable printing of each MMIO access, enable this. */
112 //#define DEBUG_ENABLE_MMIO_PRINT
114 /* If you want to enable printing of MMIO access within
115 * ucode/pcm upload, initvals write, enable this.
117 //#define DEBUG_ENABLE_UCODE_MMIO_PRINT
119 /* If you want to enable printing of PCI Config Space access, enable this */
120 //#define DEBUG_ENABLE_PCILOG
123 /* Detailed list maintained at:
124 * http://openfacts.berlios.de/index-en.phtml?title=Bcm43xxDevices
126 static struct pci_device_id bcm43xx_pci_tbl[] = {
127 /* Broadcom 4303 802.11b */
128 { PCI_VENDOR_ID_BROADCOM, 0x4301, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
129 /* Broadcom 4307 802.11b */
130 { PCI_VENDOR_ID_BROADCOM, 0x4307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
131 /* Broadcom 4318 802.11b/g */
132 { PCI_VENDOR_ID_BROADCOM, 0x4318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
133 /* Broadcom 4306 802.11b/g */
134 { PCI_VENDOR_ID_BROADCOM, 0x4320, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
135 /* Broadcom 4306 802.11a */
136 // { PCI_VENDOR_ID_BROADCOM, 0x4321, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
137 /* Broadcom 4309 802.11a/b/g */
138 { PCI_VENDOR_ID_BROADCOM, 0x4324, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
139 /* Broadcom 43XG 802.11b/g */
140 { PCI_VENDOR_ID_BROADCOM, 0x4325, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
141 #ifdef CONFIG_BCM947XX
142 /* SB bus on BCM947xx */
143 { PCI_VENDOR_ID_BROADCOM, 0x0800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
147 MODULE_DEVICE_TABLE(pci, bcm43xx_pci_tbl);
149 static void bcm43xx_ram_write(struct bcm43xx_private *bcm, u16 offset, u32 val)
153 status = bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD);
154 if (!(status & BCM43xx_SBF_XFER_REG_BYTESWAP))
157 bcm43xx_write32(bcm, BCM43xx_MMIO_RAM_CONTROL, offset);
159 bcm43xx_write32(bcm, BCM43xx_MMIO_RAM_DATA, val);
163 void bcm43xx_shm_control_word(struct bcm43xx_private *bcm,
164 u16 routing, u16 offset)
168 /* "offset" is the WORD offset. */
173 bcm43xx_write32(bcm, BCM43xx_MMIO_SHM_CONTROL, control);
176 u32 bcm43xx_shm_read32(struct bcm43xx_private *bcm,
177 u16 routing, u16 offset)
181 if (routing == BCM43xx_SHM_SHARED) {
182 if (offset & 0x0003) {
183 /* Unaligned access */
184 bcm43xx_shm_control_word(bcm, routing, offset >> 2);
185 ret = bcm43xx_read16(bcm, BCM43xx_MMIO_SHM_DATA_UNALIGNED);
187 bcm43xx_shm_control_word(bcm, routing, (offset >> 2) + 1);
188 ret |= bcm43xx_read16(bcm, BCM43xx_MMIO_SHM_DATA);
194 bcm43xx_shm_control_word(bcm, routing, offset);
195 ret = bcm43xx_read32(bcm, BCM43xx_MMIO_SHM_DATA);
200 u16 bcm43xx_shm_read16(struct bcm43xx_private *bcm,
201 u16 routing, u16 offset)
205 if (routing == BCM43xx_SHM_SHARED) {
206 if (offset & 0x0003) {
207 /* Unaligned access */
208 bcm43xx_shm_control_word(bcm, routing, offset >> 2);
209 ret = bcm43xx_read16(bcm, BCM43xx_MMIO_SHM_DATA_UNALIGNED);
215 bcm43xx_shm_control_word(bcm, routing, offset);
216 ret = bcm43xx_read16(bcm, BCM43xx_MMIO_SHM_DATA);
221 void bcm43xx_shm_write32(struct bcm43xx_private *bcm,
222 u16 routing, u16 offset,
225 if (routing == BCM43xx_SHM_SHARED) {
226 if (offset & 0x0003) {
227 /* Unaligned access */
228 bcm43xx_shm_control_word(bcm, routing, offset >> 2);
230 bcm43xx_write16(bcm, BCM43xx_MMIO_SHM_DATA_UNALIGNED,
231 (value >> 16) & 0xffff);
233 bcm43xx_shm_control_word(bcm, routing, (offset >> 2) + 1);
235 bcm43xx_write16(bcm, BCM43xx_MMIO_SHM_DATA,
241 bcm43xx_shm_control_word(bcm, routing, offset);
243 bcm43xx_write32(bcm, BCM43xx_MMIO_SHM_DATA, value);
246 void bcm43xx_shm_write16(struct bcm43xx_private *bcm,
247 u16 routing, u16 offset,
250 if (routing == BCM43xx_SHM_SHARED) {
251 if (offset & 0x0003) {
252 /* Unaligned access */
253 bcm43xx_shm_control_word(bcm, routing, offset >> 2);
255 bcm43xx_write16(bcm, BCM43xx_MMIO_SHM_DATA_UNALIGNED,
261 bcm43xx_shm_control_word(bcm, routing, offset);
263 bcm43xx_write16(bcm, BCM43xx_MMIO_SHM_DATA, value);
266 void bcm43xx_tsf_read(struct bcm43xx_private *bcm, u64 *tsf)
268 /* We need to be careful. As we read the TSF from multiple
269 * registers, we should take care of register overflows.
270 * In theory, the whole tsf read process should be atomic.
271 * We try to be atomic here, by restaring the read process,
272 * if any of the high registers changed (overflew).
274 if (bcm->current_core->rev >= 3) {
275 u32 low, high, high2;
278 high = bcm43xx_read32(bcm, BCM43xx_MMIO_REV3PLUS_TSF_HIGH);
279 low = bcm43xx_read32(bcm, BCM43xx_MMIO_REV3PLUS_TSF_LOW);
280 high2 = bcm43xx_read32(bcm, BCM43xx_MMIO_REV3PLUS_TSF_HIGH);
281 } while (unlikely(high != high2));
289 u16 test1, test2, test3;
292 v3 = bcm43xx_read16(bcm, BCM43xx_MMIO_TSF_3);
293 v2 = bcm43xx_read16(bcm, BCM43xx_MMIO_TSF_2);
294 v1 = bcm43xx_read16(bcm, BCM43xx_MMIO_TSF_1);
295 v0 = bcm43xx_read16(bcm, BCM43xx_MMIO_TSF_0);
297 test3 = bcm43xx_read16(bcm, BCM43xx_MMIO_TSF_3);
298 test2 = bcm43xx_read16(bcm, BCM43xx_MMIO_TSF_2);
299 test1 = bcm43xx_read16(bcm, BCM43xx_MMIO_TSF_1);
300 } while (v3 != test3 || v2 != test2 || v1 != test1);
314 void bcm43xx_tsf_write(struct bcm43xx_private *bcm, u64 tsf)
318 status = bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD);
319 status |= BCM43xx_SBF_TIME_UPDATE;
320 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD, status);
323 /* Be careful with the in-progress timer.
324 * First zero out the low register, so we have a full
325 * register-overflow duration to complete the operation.
327 if (bcm->current_core->rev >= 3) {
328 u32 lo = (tsf & 0x00000000FFFFFFFFULL);
329 u32 hi = (tsf & 0xFFFFFFFF00000000ULL) >> 32;
331 bcm43xx_write32(bcm, BCM43xx_MMIO_REV3PLUS_TSF_LOW, 0);
333 bcm43xx_write32(bcm, BCM43xx_MMIO_REV3PLUS_TSF_HIGH, hi);
335 bcm43xx_write32(bcm, BCM43xx_MMIO_REV3PLUS_TSF_LOW, lo);
337 u16 v0 = (tsf & 0x000000000000FFFFULL);
338 u16 v1 = (tsf & 0x00000000FFFF0000ULL) >> 16;
339 u16 v2 = (tsf & 0x0000FFFF00000000ULL) >> 32;
340 u16 v3 = (tsf & 0xFFFF000000000000ULL) >> 48;
342 bcm43xx_write16(bcm, BCM43xx_MMIO_TSF_0, 0);
344 bcm43xx_write16(bcm, BCM43xx_MMIO_TSF_3, v3);
346 bcm43xx_write16(bcm, BCM43xx_MMIO_TSF_2, v2);
348 bcm43xx_write16(bcm, BCM43xx_MMIO_TSF_1, v1);
350 bcm43xx_write16(bcm, BCM43xx_MMIO_TSF_0, v0);
353 status = bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD);
354 status &= ~BCM43xx_SBF_TIME_UPDATE;
355 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD, status);
359 void bcm43xx_macfilter_set(struct bcm43xx_private *bcm,
366 bcm43xx_write16(bcm, BCM43xx_MMIO_MACFILTER_CONTROL, offset);
370 bcm43xx_write16(bcm, BCM43xx_MMIO_MACFILTER_DATA, data);
373 bcm43xx_write16(bcm, BCM43xx_MMIO_MACFILTER_DATA, data);
376 bcm43xx_write16(bcm, BCM43xx_MMIO_MACFILTER_DATA, data);
379 static void bcm43xx_macfilter_clear(struct bcm43xx_private *bcm,
382 const u8 zero_addr[ETH_ALEN] = { 0 };
384 bcm43xx_macfilter_set(bcm, offset, zero_addr);
387 static void bcm43xx_write_mac_bssid_templates(struct bcm43xx_private *bcm)
389 const u8 *mac = (const u8 *)(bcm->net_dev->dev_addr);
390 const u8 *bssid = (const u8 *)(bcm->ieee->bssid);
391 u8 mac_bssid[ETH_ALEN * 2];
394 memcpy(mac_bssid, mac, ETH_ALEN);
395 memcpy(mac_bssid + ETH_ALEN, bssid, ETH_ALEN);
397 /* Write our MAC address and BSSID to template ram */
398 for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32))
399 bcm43xx_ram_write(bcm, 0x20 + i, *((u32 *)(mac_bssid + i)));
400 for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32))
401 bcm43xx_ram_write(bcm, 0x78 + i, *((u32 *)(mac_bssid + i)));
402 for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32))
403 bcm43xx_ram_write(bcm, 0x478 + i, *((u32 *)(mac_bssid + i)));
406 static void bcm43xx_set_slot_time(struct bcm43xx_private *bcm, u16 slot_time)
408 /* slot_time is in usec. */
409 if (bcm43xx_current_phy(bcm)->type != BCM43xx_PHYTYPE_G)
411 bcm43xx_write16(bcm, 0x684, 510 + slot_time);
412 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, 0x0010, slot_time);
415 static void bcm43xx_short_slot_timing_enable(struct bcm43xx_private *bcm)
417 bcm43xx_set_slot_time(bcm, 9);
420 static void bcm43xx_short_slot_timing_disable(struct bcm43xx_private *bcm)
422 bcm43xx_set_slot_time(bcm, 20);
425 //FIXME: rename this func?
426 static void bcm43xx_disassociate(struct bcm43xx_private *bcm)
428 bcm43xx_mac_suspend(bcm);
429 bcm43xx_macfilter_clear(bcm, BCM43xx_MACFILTER_ASSOC);
431 bcm43xx_ram_write(bcm, 0x0026, 0x0000);
432 bcm43xx_ram_write(bcm, 0x0028, 0x0000);
433 bcm43xx_ram_write(bcm, 0x007E, 0x0000);
434 bcm43xx_ram_write(bcm, 0x0080, 0x0000);
435 bcm43xx_ram_write(bcm, 0x047E, 0x0000);
436 bcm43xx_ram_write(bcm, 0x0480, 0x0000);
438 if (bcm->current_core->rev < 3) {
439 bcm43xx_write16(bcm, 0x0610, 0x8000);
440 bcm43xx_write16(bcm, 0x060E, 0x0000);
442 bcm43xx_write32(bcm, 0x0188, 0x80000000);
444 bcm43xx_shm_write32(bcm, BCM43xx_SHM_WIRELESS, 0x0004, 0x000003ff);
446 if (bcm43xx_current_phy(bcm)->type == BCM43xx_PHYTYPE_G &&
447 ieee80211_is_ofdm_rate(bcm->softmac->txrates.default_rate))
448 bcm43xx_short_slot_timing_enable(bcm);
450 bcm43xx_mac_enable(bcm);
453 //FIXME: rename this func?
454 static void bcm43xx_associate(struct bcm43xx_private *bcm,
457 memcpy(bcm->ieee->bssid, mac, ETH_ALEN);
459 bcm43xx_mac_suspend(bcm);
460 bcm43xx_macfilter_set(bcm, BCM43xx_MACFILTER_ASSOC, mac);
461 bcm43xx_write_mac_bssid_templates(bcm);
462 bcm43xx_mac_enable(bcm);
465 /* Enable a Generic IRQ. "mask" is the mask of which IRQs to enable.
466 * Returns the _previously_ enabled IRQ mask.
468 static inline u32 bcm43xx_interrupt_enable(struct bcm43xx_private *bcm, u32 mask)
472 old_mask = bcm43xx_read32(bcm, BCM43xx_MMIO_GEN_IRQ_MASK);
473 bcm43xx_write32(bcm, BCM43xx_MMIO_GEN_IRQ_MASK, old_mask | mask);
478 /* Disable a Generic IRQ. "mask" is the mask of which IRQs to disable.
479 * Returns the _previously_ enabled IRQ mask.
481 static inline u32 bcm43xx_interrupt_disable(struct bcm43xx_private *bcm, u32 mask)
485 old_mask = bcm43xx_read32(bcm, BCM43xx_MMIO_GEN_IRQ_MASK);
486 bcm43xx_write32(bcm, BCM43xx_MMIO_GEN_IRQ_MASK, old_mask & ~mask);
491 /* Make sure we don't receive more data from the device. */
492 static int bcm43xx_disable_interrupts_sync(struct bcm43xx_private *bcm, u32 *oldstate)
497 bcm43xx_lock_mmio(bcm, flags);
498 if (bcm43xx_is_initializing(bcm) || bcm->shutting_down) {
499 bcm43xx_unlock_mmio(bcm, flags);
502 old = bcm43xx_interrupt_disable(bcm, BCM43xx_IRQ_ALL);
503 tasklet_disable(&bcm->isr_tasklet);
504 bcm43xx_unlock_mmio(bcm, flags);
511 static int bcm43xx_read_radioinfo(struct bcm43xx_private *bcm)
513 struct bcm43xx_radioinfo *radio = bcm43xx_current_radio(bcm);
514 struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
521 if (bcm->chip_id == 0x4317) {
522 if (bcm->chip_rev == 0x00)
523 radio_id = 0x3205017F;
524 else if (bcm->chip_rev == 0x01)
525 radio_id = 0x4205017F;
527 radio_id = 0x5205017F;
529 bcm43xx_write16(bcm, BCM43xx_MMIO_RADIO_CONTROL, BCM43xx_RADIOCTL_ID);
530 radio_id = bcm43xx_read16(bcm, BCM43xx_MMIO_RADIO_DATA_HIGH);
532 bcm43xx_write16(bcm, BCM43xx_MMIO_RADIO_CONTROL, BCM43xx_RADIOCTL_ID);
533 radio_id |= bcm43xx_read16(bcm, BCM43xx_MMIO_RADIO_DATA_LOW);
536 manufact = (radio_id & 0x00000FFF);
537 version = (radio_id & 0x0FFFF000) >> 12;
538 revision = (radio_id & 0xF0000000) >> 28;
540 dprintk(KERN_INFO PFX "Detected Radio: ID: %x (Manuf: %x Ver: %x Rev: %x)\n",
541 radio_id, manufact, version, revision);
544 case BCM43xx_PHYTYPE_A:
545 if ((version != 0x2060) || (revision != 1) || (manufact != 0x17f))
546 goto err_unsupported_radio;
548 case BCM43xx_PHYTYPE_B:
549 if ((version & 0xFFF0) != 0x2050)
550 goto err_unsupported_radio;
552 case BCM43xx_PHYTYPE_G:
553 if (version != 0x2050)
554 goto err_unsupported_radio;
558 radio->manufact = manufact;
559 radio->version = version;
560 radio->revision = revision;
562 /* Set default attenuation values. */
563 radio->txpower[0] = 2;
564 radio->txpower[1] = 2;
566 radio->txpower[2] = 3;
568 radio->txpower[2] = 0;
569 if (phy->type == BCM43xx_PHYTYPE_A)
570 radio->txpower_desired = bcm->sprom.maxpower_aphy;
572 radio->txpower_desired = bcm->sprom.maxpower_bgphy;
574 /* Initialize the in-memory nrssi Lookup Table. */
575 for (i = 0; i < 64; i++)
576 radio->nrssi_lt[i] = i;
580 err_unsupported_radio:
581 printk(KERN_ERR PFX "Unsupported Radio connected to the PHY!\n");
585 static const char * bcm43xx_locale_iso(u8 locale)
587 /* ISO 3166-1 country codes.
588 * Note that there aren't ISO 3166-1 codes for
589 * all or locales. (Not all locales are countries)
592 case BCM43xx_LOCALE_WORLD:
593 case BCM43xx_LOCALE_ALL:
595 case BCM43xx_LOCALE_THAILAND:
597 case BCM43xx_LOCALE_ISRAEL:
599 case BCM43xx_LOCALE_JORDAN:
601 case BCM43xx_LOCALE_CHINA:
603 case BCM43xx_LOCALE_JAPAN:
604 case BCM43xx_LOCALE_JAPAN_HIGH:
606 case BCM43xx_LOCALE_USA_CANADA_ANZ:
607 case BCM43xx_LOCALE_USA_LOW:
609 case BCM43xx_LOCALE_EUROPE:
611 case BCM43xx_LOCALE_NONE:
618 static const char * bcm43xx_locale_string(u8 locale)
621 case BCM43xx_LOCALE_WORLD:
623 case BCM43xx_LOCALE_THAILAND:
625 case BCM43xx_LOCALE_ISRAEL:
627 case BCM43xx_LOCALE_JORDAN:
629 case BCM43xx_LOCALE_CHINA:
631 case BCM43xx_LOCALE_JAPAN:
633 case BCM43xx_LOCALE_USA_CANADA_ANZ:
634 return "USA/Canada/ANZ";
635 case BCM43xx_LOCALE_EUROPE:
637 case BCM43xx_LOCALE_USA_LOW:
639 case BCM43xx_LOCALE_JAPAN_HIGH:
641 case BCM43xx_LOCALE_ALL:
643 case BCM43xx_LOCALE_NONE:
650 static inline u8 bcm43xx_crc8(u8 crc, u8 data)
652 static const u8 t[] = {
653 0x00, 0xF7, 0xB9, 0x4E, 0x25, 0xD2, 0x9C, 0x6B,
654 0x4A, 0xBD, 0xF3, 0x04, 0x6F, 0x98, 0xD6, 0x21,
655 0x94, 0x63, 0x2D, 0xDA, 0xB1, 0x46, 0x08, 0xFF,
656 0xDE, 0x29, 0x67, 0x90, 0xFB, 0x0C, 0x42, 0xB5,
657 0x7F, 0x88, 0xC6, 0x31, 0x5A, 0xAD, 0xE3, 0x14,
658 0x35, 0xC2, 0x8C, 0x7B, 0x10, 0xE7, 0xA9, 0x5E,
659 0xEB, 0x1C, 0x52, 0xA5, 0xCE, 0x39, 0x77, 0x80,
660 0xA1, 0x56, 0x18, 0xEF, 0x84, 0x73, 0x3D, 0xCA,
661 0xFE, 0x09, 0x47, 0xB0, 0xDB, 0x2C, 0x62, 0x95,
662 0xB4, 0x43, 0x0D, 0xFA, 0x91, 0x66, 0x28, 0xDF,
663 0x6A, 0x9D, 0xD3, 0x24, 0x4F, 0xB8, 0xF6, 0x01,
664 0x20, 0xD7, 0x99, 0x6E, 0x05, 0xF2, 0xBC, 0x4B,
665 0x81, 0x76, 0x38, 0xCF, 0xA4, 0x53, 0x1D, 0xEA,
666 0xCB, 0x3C, 0x72, 0x85, 0xEE, 0x19, 0x57, 0xA0,
667 0x15, 0xE2, 0xAC, 0x5B, 0x30, 0xC7, 0x89, 0x7E,
668 0x5F, 0xA8, 0xE6, 0x11, 0x7A, 0x8D, 0xC3, 0x34,
669 0xAB, 0x5C, 0x12, 0xE5, 0x8E, 0x79, 0x37, 0xC0,
670 0xE1, 0x16, 0x58, 0xAF, 0xC4, 0x33, 0x7D, 0x8A,
671 0x3F, 0xC8, 0x86, 0x71, 0x1A, 0xED, 0xA3, 0x54,
672 0x75, 0x82, 0xCC, 0x3B, 0x50, 0xA7, 0xE9, 0x1E,
673 0xD4, 0x23, 0x6D, 0x9A, 0xF1, 0x06, 0x48, 0xBF,
674 0x9E, 0x69, 0x27, 0xD0, 0xBB, 0x4C, 0x02, 0xF5,
675 0x40, 0xB7, 0xF9, 0x0E, 0x65, 0x92, 0xDC, 0x2B,
676 0x0A, 0xFD, 0xB3, 0x44, 0x2F, 0xD8, 0x96, 0x61,
677 0x55, 0xA2, 0xEC, 0x1B, 0x70, 0x87, 0xC9, 0x3E,
678 0x1F, 0xE8, 0xA6, 0x51, 0x3A, 0xCD, 0x83, 0x74,
679 0xC1, 0x36, 0x78, 0x8F, 0xE4, 0x13, 0x5D, 0xAA,
680 0x8B, 0x7C, 0x32, 0xC5, 0xAE, 0x59, 0x17, 0xE0,
681 0x2A, 0xDD, 0x93, 0x64, 0x0F, 0xF8, 0xB6, 0x41,
682 0x60, 0x97, 0xD9, 0x2E, 0x45, 0xB2, 0xFC, 0x0B,
683 0xBE, 0x49, 0x07, 0xF0, 0x9B, 0x6C, 0x22, 0xD5,
684 0xF4, 0x03, 0x4D, 0xBA, 0xD1, 0x26, 0x68, 0x9F,
686 return t[crc ^ data];
689 static u8 bcm43xx_sprom_crc(const u16 *sprom)
694 for (word = 0; word < BCM43xx_SPROM_SIZE - 1; word++) {
695 crc = bcm43xx_crc8(crc, sprom[word] & 0x00FF);
696 crc = bcm43xx_crc8(crc, (sprom[word] & 0xFF00) >> 8);
698 crc = bcm43xx_crc8(crc, sprom[BCM43xx_SPROM_VERSION] & 0x00FF);
704 int bcm43xx_sprom_read(struct bcm43xx_private *bcm, u16 *sprom)
707 u8 crc, expected_crc;
709 for (i = 0; i < BCM43xx_SPROM_SIZE; i++)
710 sprom[i] = bcm43xx_read16(bcm, BCM43xx_SPROM_BASE + (i * 2));
712 crc = bcm43xx_sprom_crc(sprom);
713 expected_crc = (sprom[BCM43xx_SPROM_VERSION] & 0xFF00) >> 8;
714 if (crc != expected_crc) {
715 printk(KERN_WARNING PFX "WARNING: Invalid SPROM checksum "
716 "(0x%02X, expected: 0x%02X)\n",
724 int bcm43xx_sprom_write(struct bcm43xx_private *bcm, const u16 *sprom)
727 u8 crc, expected_crc;
730 /* CRC-8 validation of the input data. */
731 crc = bcm43xx_sprom_crc(sprom);
732 expected_crc = (sprom[BCM43xx_SPROM_VERSION] & 0xFF00) >> 8;
733 if (crc != expected_crc) {
734 printk(KERN_ERR PFX "SPROM input data: Invalid CRC\n");
738 printk(KERN_INFO PFX "Writing SPROM. Do NOT turn off the power! Please stand by...\n");
739 err = bcm43xx_pci_read_config32(bcm, BCM43xx_PCICFG_SPROMCTL, &spromctl);
742 spromctl |= 0x10; /* SPROM WRITE enable. */
743 bcm43xx_pci_write_config32(bcm, BCM43xx_PCICFG_SPROMCTL, spromctl);
746 /* We must burn lots of CPU cycles here, but that does not
747 * really matter as one does not write the SPROM every other minute...
749 printk(KERN_INFO PFX "[ 0%%");
751 for (i = 0; i < BCM43xx_SPROM_SIZE; i++) {
760 bcm43xx_write16(bcm, BCM43xx_SPROM_BASE + (i * 2), sprom[i]);
764 spromctl &= ~0x10; /* SPROM WRITE enable. */
765 bcm43xx_pci_write_config32(bcm, BCM43xx_PCICFG_SPROMCTL, spromctl);
770 printk(KERN_INFO PFX "SPROM written.\n");
771 bcm43xx_controller_restart(bcm, "SPROM update");
775 printk(KERN_ERR PFX "Could not access SPROM control register.\n");
779 static int bcm43xx_sprom_extract(struct bcm43xx_private *bcm)
783 #ifdef CONFIG_BCM947XX
787 sprom = kzalloc(BCM43xx_SPROM_SIZE * sizeof(u16),
790 printk(KERN_ERR PFX "sprom_extract OOM\n");
793 #ifdef CONFIG_BCM947XX
794 sprom[BCM43xx_SPROM_BOARDFLAGS2] = atoi(nvram_get("boardflags2"));
795 sprom[BCM43xx_SPROM_BOARDFLAGS] = atoi(nvram_get("boardflags"));
797 if ((c = nvram_get("il0macaddr")) != NULL)
798 e_aton(c, (char *) &(sprom[BCM43xx_SPROM_IL0MACADDR]));
800 if ((c = nvram_get("et1macaddr")) != NULL)
801 e_aton(c, (char *) &(sprom[BCM43xx_SPROM_ET1MACADDR]));
803 sprom[BCM43xx_SPROM_PA0B0] = atoi(nvram_get("pa0b0"));
804 sprom[BCM43xx_SPROM_PA0B1] = atoi(nvram_get("pa0b1"));
805 sprom[BCM43xx_SPROM_PA0B2] = atoi(nvram_get("pa0b2"));
807 sprom[BCM43xx_SPROM_PA1B0] = atoi(nvram_get("pa1b0"));
808 sprom[BCM43xx_SPROM_PA1B1] = atoi(nvram_get("pa1b1"));
809 sprom[BCM43xx_SPROM_PA1B2] = atoi(nvram_get("pa1b2"));
811 sprom[BCM43xx_SPROM_BOARDREV] = atoi(nvram_get("boardrev"));
813 bcm43xx_sprom_read(bcm, sprom);
817 value = sprom[BCM43xx_SPROM_BOARDFLAGS2];
818 bcm->sprom.boardflags2 = value;
821 value = sprom[BCM43xx_SPROM_IL0MACADDR + 0];
822 *(((u16 *)bcm->sprom.il0macaddr) + 0) = cpu_to_be16(value);
823 value = sprom[BCM43xx_SPROM_IL0MACADDR + 1];
824 *(((u16 *)bcm->sprom.il0macaddr) + 1) = cpu_to_be16(value);
825 value = sprom[BCM43xx_SPROM_IL0MACADDR + 2];
826 *(((u16 *)bcm->sprom.il0macaddr) + 2) = cpu_to_be16(value);
829 value = sprom[BCM43xx_SPROM_ET0MACADDR + 0];
830 *(((u16 *)bcm->sprom.et0macaddr) + 0) = cpu_to_be16(value);
831 value = sprom[BCM43xx_SPROM_ET0MACADDR + 1];
832 *(((u16 *)bcm->sprom.et0macaddr) + 1) = cpu_to_be16(value);
833 value = sprom[BCM43xx_SPROM_ET0MACADDR + 2];
834 *(((u16 *)bcm->sprom.et0macaddr) + 2) = cpu_to_be16(value);
837 value = sprom[BCM43xx_SPROM_ET1MACADDR + 0];
838 *(((u16 *)bcm->sprom.et1macaddr) + 0) = cpu_to_be16(value);
839 value = sprom[BCM43xx_SPROM_ET1MACADDR + 1];
840 *(((u16 *)bcm->sprom.et1macaddr) + 1) = cpu_to_be16(value);
841 value = sprom[BCM43xx_SPROM_ET1MACADDR + 2];
842 *(((u16 *)bcm->sprom.et1macaddr) + 2) = cpu_to_be16(value);
844 /* ethernet phy settings */
845 value = sprom[BCM43xx_SPROM_ETHPHY];
846 bcm->sprom.et0phyaddr = (value & 0x001F);
847 bcm->sprom.et1phyaddr = (value & 0x03E0) >> 5;
848 bcm->sprom.et0mdcport = (value & (1 << 14)) >> 14;
849 bcm->sprom.et1mdcport = (value & (1 << 15)) >> 15;
851 /* boardrev, antennas, locale */
852 value = sprom[BCM43xx_SPROM_BOARDREV];
853 bcm->sprom.boardrev = (value & 0x00FF);
854 bcm->sprom.locale = (value & 0x0F00) >> 8;
855 bcm->sprom.antennas_aphy = (value & 0x3000) >> 12;
856 bcm->sprom.antennas_bgphy = (value & 0xC000) >> 14;
857 if (modparam_locale != -1) {
858 if (modparam_locale >= 0 && modparam_locale <= 11) {
859 bcm->sprom.locale = modparam_locale;
860 printk(KERN_WARNING PFX "Operating with modified "
861 "LocaleCode %u (%s)\n",
863 bcm43xx_locale_string(bcm->sprom.locale));
865 printk(KERN_WARNING PFX "Module parameter \"locale\" "
866 "invalid value. (0 - 11)\n");
871 value = sprom[BCM43xx_SPROM_PA0B0];
872 bcm->sprom.pa0b0 = value;
873 value = sprom[BCM43xx_SPROM_PA0B1];
874 bcm->sprom.pa0b1 = value;
875 value = sprom[BCM43xx_SPROM_PA0B2];
876 bcm->sprom.pa0b2 = value;
879 value = sprom[BCM43xx_SPROM_WL0GPIO0];
882 bcm->sprom.wl0gpio0 = value & 0x00FF;
883 bcm->sprom.wl0gpio1 = (value & 0xFF00) >> 8;
884 value = sprom[BCM43xx_SPROM_WL0GPIO2];
887 bcm->sprom.wl0gpio2 = value & 0x00FF;
888 bcm->sprom.wl0gpio3 = (value & 0xFF00) >> 8;
891 value = sprom[BCM43xx_SPROM_MAXPWR];
892 bcm->sprom.maxpower_aphy = (value & 0xFF00) >> 8;
893 bcm->sprom.maxpower_bgphy = value & 0x00FF;
896 value = sprom[BCM43xx_SPROM_PA1B0];
897 bcm->sprom.pa1b0 = value;
898 value = sprom[BCM43xx_SPROM_PA1B1];
899 bcm->sprom.pa1b1 = value;
900 value = sprom[BCM43xx_SPROM_PA1B2];
901 bcm->sprom.pa1b2 = value;
903 /* idle tssi target */
904 value = sprom[BCM43xx_SPROM_IDL_TSSI_TGT];
905 bcm->sprom.idle_tssi_tgt_aphy = value & 0x00FF;
906 bcm->sprom.idle_tssi_tgt_bgphy = (value & 0xFF00) >> 8;
909 value = sprom[BCM43xx_SPROM_BOARDFLAGS];
912 bcm->sprom.boardflags = value;
913 /* boardflags workarounds */
914 if (bcm->board_vendor == PCI_VENDOR_ID_DELL &&
915 bcm->chip_id == 0x4301 &&
916 bcm->board_revision == 0x74)
917 bcm->sprom.boardflags |= BCM43xx_BFL_BTCOEXIST;
918 if (bcm->board_vendor == PCI_VENDOR_ID_APPLE &&
919 bcm->board_type == 0x4E &&
920 bcm->board_revision > 0x40)
921 bcm->sprom.boardflags |= BCM43xx_BFL_PACTRL;
924 value = sprom[BCM43xx_SPROM_ANTENNA_GAIN];
925 if (value == 0x0000 || value == 0xFFFF)
927 /* convert values to Q5.2 */
928 bcm->sprom.antennagain_aphy = ((value & 0xFF00) >> 8) * 4;
929 bcm->sprom.antennagain_bgphy = (value & 0x00FF) * 4;
936 static void bcm43xx_geo_init(struct bcm43xx_private *bcm)
938 struct ieee80211_geo geo;
939 struct ieee80211_channel *chan;
940 int have_a = 0, have_bg = 0;
943 struct bcm43xx_phyinfo *phy;
944 const char *iso_country;
946 memset(&geo, 0, sizeof(geo));
947 for (i = 0; i < bcm->nr_80211_available; i++) {
948 phy = &(bcm->core_80211_ext[i].phy);
950 case BCM43xx_PHYTYPE_B:
951 case BCM43xx_PHYTYPE_G:
954 case BCM43xx_PHYTYPE_A:
961 iso_country = bcm43xx_locale_iso(bcm->sprom.locale);
964 for (i = 0, channel = 0; channel < 201; channel++) {
966 chan->freq = bcm43xx_channel_to_freq_a(channel);
967 chan->channel = channel;
972 for (i = 0, channel = 1; channel < 15; channel++) {
974 chan->freq = bcm43xx_channel_to_freq_bg(channel);
975 chan->channel = channel;
979 memcpy(geo.name, iso_country, 2);
980 if (0 /*TODO: Outdoor use only */)
982 else if (0 /*TODO: Indoor use only */)
988 ieee80211_set_geo(bcm->ieee, &geo);
991 /* DummyTransmission function, as documented on
992 * http://bcm-specs.sipsolutions.net/DummyTransmission
994 void bcm43xx_dummy_transmission(struct bcm43xx_private *bcm)
996 struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
997 struct bcm43xx_radioinfo *radio = bcm43xx_current_radio(bcm);
998 unsigned int i, max_loop;
1008 switch (phy->type) {
1009 case BCM43xx_PHYTYPE_A:
1011 buffer[0] = 0xCC010200;
1013 case BCM43xx_PHYTYPE_B:
1014 case BCM43xx_PHYTYPE_G:
1016 buffer[0] = 0x6E840B00;
1023 for (i = 0; i < 5; i++)
1024 bcm43xx_ram_write(bcm, i * 4, buffer[i]);
1026 bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD); /* dummy read */
1028 bcm43xx_write16(bcm, 0x0568, 0x0000);
1029 bcm43xx_write16(bcm, 0x07C0, 0x0000);
1030 bcm43xx_write16(bcm, 0x050C, ((phy->type == BCM43xx_PHYTYPE_A) ? 1 : 0));
1031 bcm43xx_write16(bcm, 0x0508, 0x0000);
1032 bcm43xx_write16(bcm, 0x050A, 0x0000);
1033 bcm43xx_write16(bcm, 0x054C, 0x0000);
1034 bcm43xx_write16(bcm, 0x056A, 0x0014);
1035 bcm43xx_write16(bcm, 0x0568, 0x0826);
1036 bcm43xx_write16(bcm, 0x0500, 0x0000);
1037 bcm43xx_write16(bcm, 0x0502, 0x0030);
1039 if (radio->version == 0x2050 && radio->revision <= 0x5)
1040 bcm43xx_radio_write16(bcm, 0x0051, 0x0017);
1041 for (i = 0x00; i < max_loop; i++) {
1042 value = bcm43xx_read16(bcm, 0x050E);
1047 for (i = 0x00; i < 0x0A; i++) {
1048 value = bcm43xx_read16(bcm, 0x050E);
1053 for (i = 0x00; i < 0x0A; i++) {
1054 value = bcm43xx_read16(bcm, 0x0690);
1055 if (!(value & 0x0100))
1059 if (radio->version == 0x2050 && radio->revision <= 0x5)
1060 bcm43xx_radio_write16(bcm, 0x0051, 0x0037);
1063 static void key_write(struct bcm43xx_private *bcm,
1064 u8 index, u8 algorithm, const u16 *key)
1066 unsigned int i, basic_wep = 0;
1070 /* Write associated key information */
1071 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, 0x100 + (index * 2),
1072 ((index << 4) | (algorithm & 0x0F)));
1074 /* The first 4 WEP keys need extra love */
1075 if (((algorithm == BCM43xx_SEC_ALGO_WEP) ||
1076 (algorithm == BCM43xx_SEC_ALGO_WEP104)) && (index < 4))
1079 /* Write key payload, 8 little endian words */
1080 offset = bcm->security_offset + (index * BCM43xx_SEC_KEYSIZE);
1081 for (i = 0; i < (BCM43xx_SEC_KEYSIZE / sizeof(u16)); i++) {
1082 value = cpu_to_le16(key[i]);
1083 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED,
1084 offset + (i * 2), value);
1089 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED,
1090 offset + (i * 2) + 4 * BCM43xx_SEC_KEYSIZE,
1095 static void keymac_write(struct bcm43xx_private *bcm,
1096 u8 index, const u32 *addr)
1098 /* for keys 0-3 there is no associated mac address */
1103 if (bcm->current_core->rev >= 5) {
1104 bcm43xx_shm_write32(bcm,
1107 cpu_to_be32(*addr));
1108 bcm43xx_shm_write16(bcm,
1111 cpu_to_be16(*((u16 *)(addr + 1))));
1114 TODO(); /* Put them in the macaddress filter */
1117 /* Put them BCM43xx_SHM_SHARED, stating index 0x0120.
1118 Keep in mind to update the count of keymacs in 0x003E as well! */
1123 static int bcm43xx_key_write(struct bcm43xx_private *bcm,
1124 u8 index, u8 algorithm,
1125 const u8 *_key, int key_len,
1128 u8 key[BCM43xx_SEC_KEYSIZE] = { 0 };
1130 if (index >= ARRAY_SIZE(bcm->key))
1132 if (key_len > ARRAY_SIZE(key))
1134 if (algorithm < 1 || algorithm > 5)
1137 memcpy(key, _key, key_len);
1138 key_write(bcm, index, algorithm, (const u16 *)key);
1139 keymac_write(bcm, index, (const u32 *)mac_addr);
1141 bcm->key[index].algorithm = algorithm;
1146 static void bcm43xx_clear_keys(struct bcm43xx_private *bcm)
1148 static const u32 zero_mac[2] = { 0 };
1149 unsigned int i,j, nr_keys = 54;
1152 if (bcm->current_core->rev < 5)
1154 assert(nr_keys <= ARRAY_SIZE(bcm->key));
1156 for (i = 0; i < nr_keys; i++) {
1157 bcm->key[i].enabled = 0;
1158 /* returns for i < 4 immediately */
1159 keymac_write(bcm, i, zero_mac);
1160 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED,
1161 0x100 + (i * 2), 0x0000);
1162 for (j = 0; j < 8; j++) {
1163 offset = bcm->security_offset + (j * 4) + (i * BCM43xx_SEC_KEYSIZE);
1164 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED,
1168 dprintk(KERN_INFO PFX "Keys cleared\n");
1171 /* Lowlevel core-switch function. This is only to be used in
1172 * bcm43xx_switch_core() and bcm43xx_probe_cores()
1174 static int _switch_core(struct bcm43xx_private *bcm, int core)
1182 err = bcm43xx_pci_write_config32(bcm, BCM43xx_PCICFG_ACTIVE_CORE,
1183 (core * 0x1000) + 0x18000000);
1186 err = bcm43xx_pci_read_config32(bcm, BCM43xx_PCICFG_ACTIVE_CORE,
1190 current_core = (current_core - 0x18000000) / 0x1000;
1191 if (current_core == core)
1194 if (unlikely(attempts++ > BCM43xx_SWITCH_CORE_MAX_RETRIES))
1198 #ifdef CONFIG_BCM947XX
1199 if (bcm->pci_dev->bus->number == 0)
1200 bcm->current_core_offset = 0x1000 * core;
1202 bcm->current_core_offset = 0;
1207 printk(KERN_ERR PFX "Failed to switch to core %d\n", core);
1211 int bcm43xx_switch_core(struct bcm43xx_private *bcm, struct bcm43xx_coreinfo *new_core)
1215 if (unlikely(!new_core))
1217 if (!new_core->available)
1219 if (bcm->current_core == new_core)
1221 err = _switch_core(bcm, new_core->index);
1225 bcm->current_core = new_core;
1226 bcm->current_80211_core_idx = -1;
1227 if (new_core->id == BCM43xx_COREID_80211)
1228 bcm->current_80211_core_idx = (int)(new_core - &(bcm->core_80211[0]));
1234 static int bcm43xx_core_enabled(struct bcm43xx_private *bcm)
1238 value = bcm43xx_read32(bcm, BCM43xx_CIR_SBTMSTATELOW);
1239 value &= BCM43xx_SBTMSTATELOW_CLOCK | BCM43xx_SBTMSTATELOW_RESET
1240 | BCM43xx_SBTMSTATELOW_REJECT;
1242 return (value == BCM43xx_SBTMSTATELOW_CLOCK);
1245 /* disable current core */
1246 static int bcm43xx_core_disable(struct bcm43xx_private *bcm, u32 core_flags)
1252 /* fetch sbtmstatelow from core information registers */
1253 sbtmstatelow = bcm43xx_read32(bcm, BCM43xx_CIR_SBTMSTATELOW);
1255 /* core is already in reset */
1256 if (sbtmstatelow & BCM43xx_SBTMSTATELOW_RESET)
1259 if (sbtmstatelow & BCM43xx_SBTMSTATELOW_CLOCK) {
1260 sbtmstatelow = BCM43xx_SBTMSTATELOW_CLOCK |
1261 BCM43xx_SBTMSTATELOW_REJECT;
1262 bcm43xx_write32(bcm, BCM43xx_CIR_SBTMSTATELOW, sbtmstatelow);
1264 for (i = 0; i < 1000; i++) {
1265 sbtmstatelow = bcm43xx_read32(bcm, BCM43xx_CIR_SBTMSTATELOW);
1266 if (sbtmstatelow & BCM43xx_SBTMSTATELOW_REJECT) {
1273 printk(KERN_ERR PFX "Error: core_disable() REJECT timeout!\n");
1277 for (i = 0; i < 1000; i++) {
1278 sbtmstatehigh = bcm43xx_read32(bcm, BCM43xx_CIR_SBTMSTATEHIGH);
1279 if (!(sbtmstatehigh & BCM43xx_SBTMSTATEHIGH_BUSY)) {
1286 printk(KERN_ERR PFX "Error: core_disable() BUSY timeout!\n");
1290 sbtmstatelow = BCM43xx_SBTMSTATELOW_FORCE_GATE_CLOCK |
1291 BCM43xx_SBTMSTATELOW_REJECT |
1292 BCM43xx_SBTMSTATELOW_RESET |
1293 BCM43xx_SBTMSTATELOW_CLOCK |
1295 bcm43xx_write32(bcm, BCM43xx_CIR_SBTMSTATELOW, sbtmstatelow);
1299 sbtmstatelow = BCM43xx_SBTMSTATELOW_RESET |
1300 BCM43xx_SBTMSTATELOW_REJECT |
1302 bcm43xx_write32(bcm, BCM43xx_CIR_SBTMSTATELOW, sbtmstatelow);
1305 bcm->current_core->enabled = 0;
1310 /* enable (reset) current core */
1311 static int bcm43xx_core_enable(struct bcm43xx_private *bcm, u32 core_flags)
1318 err = bcm43xx_core_disable(bcm, core_flags);
1322 sbtmstatelow = BCM43xx_SBTMSTATELOW_CLOCK |
1323 BCM43xx_SBTMSTATELOW_RESET |
1324 BCM43xx_SBTMSTATELOW_FORCE_GATE_CLOCK |
1326 bcm43xx_write32(bcm, BCM43xx_CIR_SBTMSTATELOW, sbtmstatelow);
1329 sbtmstatehigh = bcm43xx_read32(bcm, BCM43xx_CIR_SBTMSTATEHIGH);
1330 if (sbtmstatehigh & BCM43xx_SBTMSTATEHIGH_SERROR) {
1331 sbtmstatehigh = 0x00000000;
1332 bcm43xx_write32(bcm, BCM43xx_CIR_SBTMSTATEHIGH, sbtmstatehigh);
1335 sbimstate = bcm43xx_read32(bcm, BCM43xx_CIR_SBIMSTATE);
1336 if (sbimstate & (BCM43xx_SBIMSTATE_IB_ERROR | BCM43xx_SBIMSTATE_TIMEOUT)) {
1337 sbimstate &= ~(BCM43xx_SBIMSTATE_IB_ERROR | BCM43xx_SBIMSTATE_TIMEOUT);
1338 bcm43xx_write32(bcm, BCM43xx_CIR_SBIMSTATE, sbimstate);
1341 sbtmstatelow = BCM43xx_SBTMSTATELOW_CLOCK |
1342 BCM43xx_SBTMSTATELOW_FORCE_GATE_CLOCK |
1344 bcm43xx_write32(bcm, BCM43xx_CIR_SBTMSTATELOW, sbtmstatelow);
1347 sbtmstatelow = BCM43xx_SBTMSTATELOW_CLOCK | core_flags;
1348 bcm43xx_write32(bcm, BCM43xx_CIR_SBTMSTATELOW, sbtmstatelow);
1351 bcm->current_core->enabled = 1;
1357 /* http://bcm-specs.sipsolutions.net/80211CoreReset */
1358 void bcm43xx_wireless_core_reset(struct bcm43xx_private *bcm, int connect_phy)
1360 u32 flags = 0x00040000;
1362 if ((bcm43xx_core_enabled(bcm)) &&
1363 !bcm43xx_using_pio(bcm)) {
1364 //FIXME: Do we _really_ want #ifndef CONFIG_BCM947XX here?
1365 #ifndef CONFIG_BCM947XX
1366 /* reset all used DMA controllers. */
1367 bcm43xx_dmacontroller_tx_reset(bcm, BCM43xx_MMIO_DMA1_BASE);
1368 bcm43xx_dmacontroller_tx_reset(bcm, BCM43xx_MMIO_DMA2_BASE);
1369 bcm43xx_dmacontroller_tx_reset(bcm, BCM43xx_MMIO_DMA3_BASE);
1370 bcm43xx_dmacontroller_tx_reset(bcm, BCM43xx_MMIO_DMA4_BASE);
1371 bcm43xx_dmacontroller_rx_reset(bcm, BCM43xx_MMIO_DMA1_BASE);
1372 if (bcm->current_core->rev < 5)
1373 bcm43xx_dmacontroller_rx_reset(bcm, BCM43xx_MMIO_DMA4_BASE);
1376 if (bcm->shutting_down) {
1377 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD,
1378 bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD)
1379 & ~(BCM43xx_SBF_MAC_ENABLED | 0x00000002));
1382 flags |= 0x20000000;
1383 bcm43xx_phy_connect(bcm, connect_phy);
1384 bcm43xx_core_enable(bcm, flags);
1385 bcm43xx_write16(bcm, 0x03E6, 0x0000);
1386 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD,
1387 bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD)
1392 static void bcm43xx_wireless_core_disable(struct bcm43xx_private *bcm)
1394 bcm43xx_radio_turn_off(bcm);
1395 bcm43xx_write16(bcm, 0x03E6, 0x00F4);
1396 bcm43xx_core_disable(bcm, 0);
1399 /* Mark the current 80211 core inactive.
1400 * "active_80211_core" is the other 80211 core, which is used.
1402 static int bcm43xx_wireless_core_mark_inactive(struct bcm43xx_private *bcm,
1403 struct bcm43xx_coreinfo *active_80211_core)
1406 struct bcm43xx_coreinfo *old_core;
1409 bcm43xx_interrupt_disable(bcm, BCM43xx_IRQ_ALL);
1410 bcm43xx_radio_turn_off(bcm);
1411 sbtmstatelow = bcm43xx_read32(bcm, BCM43xx_CIR_SBTMSTATELOW);
1412 sbtmstatelow &= ~0x200a0000;
1413 sbtmstatelow |= 0xa0000;
1414 bcm43xx_write32(bcm, BCM43xx_CIR_SBTMSTATELOW, sbtmstatelow);
1416 sbtmstatelow = bcm43xx_read32(bcm, BCM43xx_CIR_SBTMSTATELOW);
1417 sbtmstatelow &= ~0xa0000;
1418 sbtmstatelow |= 0x80000;
1419 bcm43xx_write32(bcm, BCM43xx_CIR_SBTMSTATELOW, sbtmstatelow);
1422 if (bcm43xx_current_phy(bcm)->type == BCM43xx_PHYTYPE_G) {
1423 old_core = bcm->current_core;
1424 err = bcm43xx_switch_core(bcm, active_80211_core);
1427 sbtmstatelow = bcm43xx_read32(bcm, BCM43xx_CIR_SBTMSTATELOW);
1428 sbtmstatelow &= ~0x20000000;
1429 sbtmstatelow |= 0x20000000;
1430 bcm43xx_write32(bcm, BCM43xx_CIR_SBTMSTATELOW, sbtmstatelow);
1431 err = bcm43xx_switch_core(bcm, old_core);
1438 static void handle_irq_transmit_status(struct bcm43xx_private *bcm)
1442 struct bcm43xx_xmitstatus stat;
1445 v0 = bcm43xx_read32(bcm, BCM43xx_MMIO_XMITSTAT_0);
1448 v1 = bcm43xx_read32(bcm, BCM43xx_MMIO_XMITSTAT_1);
1450 stat.cookie = (v0 >> 16) & 0x0000FFFF;
1451 tmp = (u16)((v0 & 0xFFF0) | ((v0 & 0xF) >> 1));
1452 stat.flags = tmp & 0xFF;
1453 stat.cnt1 = (tmp & 0x0F00) >> 8;
1454 stat.cnt2 = (tmp & 0xF000) >> 12;
1455 stat.seq = (u16)(v1 & 0xFFFF);
1456 stat.unknown = (u16)((v1 >> 16) & 0xFF);
1458 bcm43xx_debugfs_log_txstat(bcm, &stat);
1460 if (stat.flags & BCM43xx_TXSTAT_FLAG_IGNORE)
1462 if (!(stat.flags & BCM43xx_TXSTAT_FLAG_ACK)) {
1463 //TODO: packet was not acked (was lost)
1465 //TODO: There are more (unknown) flags to test. see bcm43xx_main.h
1467 if (bcm43xx_using_pio(bcm))
1468 bcm43xx_pio_handle_xmitstatus(bcm, &stat);
1470 bcm43xx_dma_handle_xmitstatus(bcm, &stat);
1474 static void bcm43xx_generate_noise_sample(struct bcm43xx_private *bcm)
1476 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, 0x408, 0x7F7F);
1477 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, 0x40A, 0x7F7F);
1478 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS2_BITFIELD,
1479 bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS2_BITFIELD) | (1 << 4));
1480 assert(bcm->noisecalc.core_at_start == bcm->current_core);
1481 assert(bcm->noisecalc.channel_at_start == bcm43xx_current_radio(bcm)->channel);
1484 static void bcm43xx_calculate_link_quality(struct bcm43xx_private *bcm)
1486 /* Top half of Link Quality calculation. */
1488 if (bcm->noisecalc.calculation_running)
1490 bcm->noisecalc.core_at_start = bcm->current_core;
1491 bcm->noisecalc.channel_at_start = bcm43xx_current_radio(bcm)->channel;
1492 bcm->noisecalc.calculation_running = 1;
1493 bcm->noisecalc.nr_samples = 0;
1495 bcm43xx_generate_noise_sample(bcm);
1498 static void handle_irq_noise(struct bcm43xx_private *bcm)
1500 struct bcm43xx_radioinfo *radio = bcm43xx_current_radio(bcm);
1506 /* Bottom half of Link Quality calculation. */
1508 assert(bcm->noisecalc.calculation_running);
1509 if (bcm->noisecalc.core_at_start != bcm->current_core ||
1510 bcm->noisecalc.channel_at_start != radio->channel)
1511 goto drop_calculation;
1512 tmp = bcm43xx_shm_read16(bcm, BCM43xx_SHM_SHARED, 0x408);
1513 noise[0] = (tmp & 0x00FF);
1514 noise[1] = (tmp & 0xFF00) >> 8;
1515 tmp = bcm43xx_shm_read16(bcm, BCM43xx_SHM_SHARED, 0x40A);
1516 noise[2] = (tmp & 0x00FF);
1517 noise[3] = (tmp & 0xFF00) >> 8;
1518 if (noise[0] == 0x7F || noise[1] == 0x7F ||
1519 noise[2] == 0x7F || noise[3] == 0x7F)
1522 /* Get the noise samples. */
1523 assert(bcm->noisecalc.nr_samples <= 8);
1524 i = bcm->noisecalc.nr_samples;
1525 noise[0] = limit_value(noise[0], 0, ARRAY_SIZE(radio->nrssi_lt) - 1);
1526 noise[1] = limit_value(noise[1], 0, ARRAY_SIZE(radio->nrssi_lt) - 1);
1527 noise[2] = limit_value(noise[2], 0, ARRAY_SIZE(radio->nrssi_lt) - 1);
1528 noise[3] = limit_value(noise[3], 0, ARRAY_SIZE(radio->nrssi_lt) - 1);
1529 bcm->noisecalc.samples[i][0] = radio->nrssi_lt[noise[0]];
1530 bcm->noisecalc.samples[i][1] = radio->nrssi_lt[noise[1]];
1531 bcm->noisecalc.samples[i][2] = radio->nrssi_lt[noise[2]];
1532 bcm->noisecalc.samples[i][3] = radio->nrssi_lt[noise[3]];
1533 bcm->noisecalc.nr_samples++;
1534 if (bcm->noisecalc.nr_samples == 8) {
1535 /* Calculate the Link Quality by the noise samples. */
1537 for (i = 0; i < 8; i++) {
1538 for (j = 0; j < 4; j++)
1539 average += bcm->noisecalc.samples[i][j];
1545 tmp = bcm43xx_shm_read16(bcm, BCM43xx_SHM_SHARED, 0x40C);
1546 tmp = (tmp / 128) & 0x1F;
1557 bcm->stats.link_quality = 0;
1558 else if (average > -75)
1559 bcm->stats.link_quality = 1;
1560 else if (average > -85)
1561 bcm->stats.link_quality = 2;
1563 bcm->stats.link_quality = 3;
1564 // dprintk(KERN_INFO PFX "Link Quality: %u (avg was %d)\n", bcm->stats.link_quality, average);
1566 bcm->noisecalc.calculation_running = 0;
1570 bcm43xx_generate_noise_sample(bcm);
1573 static void handle_irq_ps(struct bcm43xx_private *bcm)
1575 if (bcm->ieee->iw_mode == IW_MODE_MASTER) {
1578 if (1/*FIXME: the last PSpoll frame was sent successfully */)
1579 bcm43xx_power_saving_ctl_bits(bcm, -1, -1);
1581 if (bcm->ieee->iw_mode == IW_MODE_ADHOC)
1582 bcm->reg124_set_0x4 = 1;
1583 //FIXME else set to false?
1586 static void handle_irq_reg124(struct bcm43xx_private *bcm)
1588 if (!bcm->reg124_set_0x4)
1590 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS2_BITFIELD,
1591 bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS2_BITFIELD)
1593 //FIXME: reset reg124_set_0x4 to false?
1596 static void handle_irq_pmq(struct bcm43xx_private *bcm)
1603 tmp = bcm43xx_read32(bcm, BCM43xx_MMIO_PS_STATUS);
1604 if (!(tmp & 0x00000008))
1607 /* 16bit write is odd, but correct. */
1608 bcm43xx_write16(bcm, BCM43xx_MMIO_PS_STATUS, 0x0002);
1611 static void bcm43xx_generate_beacon_template(struct bcm43xx_private *bcm,
1612 u16 ram_offset, u16 shm_size_offset)
1618 //FIXME: assumption: The chip sets the timestamp
1620 bcm43xx_ram_write(bcm, ram_offset++, value);
1621 bcm43xx_ram_write(bcm, ram_offset++, value);
1624 /* Beacon Interval / Capability Information */
1625 value = 0x0000;//FIXME: Which interval?
1626 value |= (1 << 0) << 16; /* ESS */
1627 value |= (1 << 2) << 16; /* CF Pollable */ //FIXME?
1628 value |= (1 << 3) << 16; /* CF Poll Request */ //FIXME?
1629 if (!bcm->ieee->open_wep)
1630 value |= (1 << 4) << 16; /* Privacy */
1631 bcm43xx_ram_write(bcm, ram_offset++, value);
1637 /* FH Parameter Set */
1640 /* DS Parameter Set */
1643 /* CF Parameter Set */
1649 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, shm_size_offset, size);
1652 static void handle_irq_beacon(struct bcm43xx_private *bcm)
1656 bcm->irq_savedstate &= ~BCM43xx_IRQ_BEACON;
1657 status = bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS2_BITFIELD);
1659 if ((status & 0x1) && (status & 0x2)) {
1660 /* ACK beacon IRQ. */
1661 bcm43xx_write32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON,
1662 BCM43xx_IRQ_BEACON);
1663 bcm->irq_savedstate |= BCM43xx_IRQ_BEACON;
1666 if (!(status & 0x1)) {
1667 bcm43xx_generate_beacon_template(bcm, 0x68, 0x18);
1669 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS2_BITFIELD, status);
1671 if (!(status & 0x2)) {
1672 bcm43xx_generate_beacon_template(bcm, 0x468, 0x1A);
1674 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS2_BITFIELD, status);
1678 /* Interrupt handler bottom-half */
1679 static void bcm43xx_interrupt_tasklet(struct bcm43xx_private *bcm)
1684 unsigned long flags;
1686 #ifdef CONFIG_BCM43XX_DEBUG
1687 u32 _handled = 0x00000000;
1688 # define bcmirq_handled(irq) do { _handled |= (irq); } while (0)
1690 # define bcmirq_handled(irq) do { /* nothing */ } while (0)
1691 #endif /* CONFIG_BCM43XX_DEBUG*/
1693 bcm43xx_lock_mmio(bcm, flags);
1694 reason = bcm->irq_reason;
1695 dma_reason[0] = bcm->dma_reason[0];
1696 dma_reason[1] = bcm->dma_reason[1];
1697 dma_reason[2] = bcm->dma_reason[2];
1698 dma_reason[3] = bcm->dma_reason[3];
1700 if (unlikely(reason & BCM43xx_IRQ_XMIT_ERROR)) {
1701 /* TX error. We get this when Template Ram is written in wrong endianess
1702 * in dummy_tx(). We also get this if something is wrong with the TX header
1703 * on DMA or PIO queues.
1704 * Maybe we get this in other error conditions, too.
1706 printkl(KERN_ERR PFX "FATAL ERROR: BCM43xx_IRQ_XMIT_ERROR\n");
1707 bcmirq_handled(BCM43xx_IRQ_XMIT_ERROR);
1709 if (unlikely((dma_reason[0] & BCM43xx_DMAIRQ_FATALMASK) |
1710 (dma_reason[1] & BCM43xx_DMAIRQ_FATALMASK) |
1711 (dma_reason[2] & BCM43xx_DMAIRQ_FATALMASK) |
1712 (dma_reason[3] & BCM43xx_DMAIRQ_FATALMASK))) {
1713 printkl(KERN_ERR PFX "FATAL ERROR: Fatal DMA error: "
1714 "0x%08X, 0x%08X, 0x%08X, 0x%08X\n",
1715 dma_reason[0], dma_reason[1],
1716 dma_reason[2], dma_reason[3]);
1717 bcm43xx_controller_restart(bcm, "DMA error");
1718 bcm43xx_unlock_mmio(bcm, flags);
1721 if (unlikely((dma_reason[0] & BCM43xx_DMAIRQ_NONFATALMASK) |
1722 (dma_reason[1] & BCM43xx_DMAIRQ_NONFATALMASK) |
1723 (dma_reason[2] & BCM43xx_DMAIRQ_NONFATALMASK) |
1724 (dma_reason[3] & BCM43xx_DMAIRQ_NONFATALMASK))) {
1725 printkl(KERN_ERR PFX "DMA error: "
1726 "0x%08X, 0x%08X, 0x%08X, 0x%08X\n",
1727 dma_reason[0], dma_reason[1],
1728 dma_reason[2], dma_reason[3]);
1731 if (reason & BCM43xx_IRQ_PS) {
1733 bcmirq_handled(BCM43xx_IRQ_PS);
1736 if (reason & BCM43xx_IRQ_REG124) {
1737 handle_irq_reg124(bcm);
1738 bcmirq_handled(BCM43xx_IRQ_REG124);
1741 if (reason & BCM43xx_IRQ_BEACON) {
1742 if (bcm->ieee->iw_mode == IW_MODE_MASTER)
1743 handle_irq_beacon(bcm);
1744 bcmirq_handled(BCM43xx_IRQ_BEACON);
1747 if (reason & BCM43xx_IRQ_PMQ) {
1748 handle_irq_pmq(bcm);
1749 bcmirq_handled(BCM43xx_IRQ_PMQ);
1752 if (reason & BCM43xx_IRQ_SCAN) {
1754 //bcmirq_handled(BCM43xx_IRQ_SCAN);
1757 if (reason & BCM43xx_IRQ_NOISE) {
1758 handle_irq_noise(bcm);
1759 bcmirq_handled(BCM43xx_IRQ_NOISE);
1762 /* Check the DMA reason registers for received data. */
1763 assert(!(dma_reason[1] & BCM43xx_DMAIRQ_RX_DONE));
1764 assert(!(dma_reason[2] & BCM43xx_DMAIRQ_RX_DONE));
1765 if (dma_reason[0] & BCM43xx_DMAIRQ_RX_DONE) {
1766 if (bcm43xx_using_pio(bcm))
1767 bcm43xx_pio_rx(bcm43xx_current_pio(bcm)->queue0);
1769 bcm43xx_dma_rx(bcm43xx_current_dma(bcm)->rx_ring0);
1770 /* We intentionally don't set "activity" to 1, here. */
1772 if (dma_reason[3] & BCM43xx_DMAIRQ_RX_DONE) {
1773 if (bcm43xx_using_pio(bcm))
1774 bcm43xx_pio_rx(bcm43xx_current_pio(bcm)->queue3);
1776 bcm43xx_dma_rx(bcm43xx_current_dma(bcm)->rx_ring1);
1779 bcmirq_handled(BCM43xx_IRQ_RX);
1781 if (reason & BCM43xx_IRQ_XMIT_STATUS) {
1782 handle_irq_transmit_status(bcm);
1784 //TODO: In AP mode, this also causes sending of powersave responses.
1785 bcmirq_handled(BCM43xx_IRQ_XMIT_STATUS);
1788 /* We get spurious IRQs, althought they are masked.
1789 * Assume they are void and ignore them.
1791 bcmirq_handled(~(bcm->irq_savedstate));
1792 /* IRQ_PIO_WORKAROUND is handled in the top-half. */
1793 bcmirq_handled(BCM43xx_IRQ_PIO_WORKAROUND);
1794 #ifdef CONFIG_BCM43XX_DEBUG
1795 if (unlikely(reason & ~_handled)) {
1796 printkl(KERN_WARNING PFX
1797 "Unhandled IRQ! Reason: 0x%08x, Unhandled: 0x%08x, "
1798 "DMA: 0x%08x, 0x%08x, 0x%08x, 0x%08x\n",
1799 reason, (reason & ~_handled),
1800 dma_reason[0], dma_reason[1],
1801 dma_reason[2], dma_reason[3]);
1804 #undef bcmirq_handled
1806 if (!modparam_noleds)
1807 bcm43xx_leds_update(bcm, activity);
1808 bcm43xx_interrupt_enable(bcm, bcm->irq_savedstate);
1809 bcm43xx_unlock_mmio(bcm, flags);
1812 static void bcm43xx_interrupt_ack(struct bcm43xx_private *bcm,
1813 u32 reason, u32 mask)
1815 bcm->dma_reason[0] = bcm43xx_read32(bcm, BCM43xx_MMIO_DMA1_REASON)
1817 bcm->dma_reason[1] = bcm43xx_read32(bcm, BCM43xx_MMIO_DMA2_REASON)
1819 bcm->dma_reason[2] = bcm43xx_read32(bcm, BCM43xx_MMIO_DMA3_REASON)
1821 bcm->dma_reason[3] = bcm43xx_read32(bcm, BCM43xx_MMIO_DMA4_REASON)
1824 if (bcm43xx_using_pio(bcm) &&
1825 (bcm->current_core->rev < 3) &&
1826 (!(reason & BCM43xx_IRQ_PIO_WORKAROUND))) {
1827 /* Apply a PIO specific workaround to the dma_reasons */
1829 #define apply_pio_workaround(BASE, QNUM) \
1831 if (bcm43xx_read16(bcm, BASE + BCM43xx_PIO_RXCTL) & BCM43xx_PIO_RXCTL_DATAAVAILABLE) \
1832 bcm->dma_reason[QNUM] |= 0x00010000; \
1834 bcm->dma_reason[QNUM] &= ~0x00010000; \
1837 apply_pio_workaround(BCM43xx_MMIO_PIO1_BASE, 0);
1838 apply_pio_workaround(BCM43xx_MMIO_PIO2_BASE, 1);
1839 apply_pio_workaround(BCM43xx_MMIO_PIO3_BASE, 2);
1840 apply_pio_workaround(BCM43xx_MMIO_PIO4_BASE, 3);
1842 #undef apply_pio_workaround
1845 bcm43xx_write32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON,
1848 bcm43xx_write32(bcm, BCM43xx_MMIO_DMA1_REASON,
1849 bcm->dma_reason[0]);
1850 bcm43xx_write32(bcm, BCM43xx_MMIO_DMA2_REASON,
1851 bcm->dma_reason[1]);
1852 bcm43xx_write32(bcm, BCM43xx_MMIO_DMA3_REASON,
1853 bcm->dma_reason[2]);
1854 bcm43xx_write32(bcm, BCM43xx_MMIO_DMA4_REASON,
1855 bcm->dma_reason[3]);
1858 /* Interrupt handler top-half */
1859 static irqreturn_t bcm43xx_interrupt_handler(int irq, void *dev_id, struct pt_regs *regs)
1861 irqreturn_t ret = IRQ_HANDLED;
1862 struct bcm43xx_private *bcm = dev_id;
1868 spin_lock(&bcm->_lock);
1870 reason = bcm43xx_read32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON);
1871 if (reason == 0xffffffff) {
1872 /* irq not for us (shared irq) */
1876 mask = bcm43xx_read32(bcm, BCM43xx_MMIO_GEN_IRQ_MASK);
1877 if (!(reason & mask))
1880 bcm43xx_interrupt_ack(bcm, reason, mask);
1882 /* Only accept IRQs, if we are initialized properly.
1883 * This avoids an RX race while initializing.
1884 * We should probably not enable IRQs before we are initialized
1885 * completely, but some careful work is needed to fix this. I think it
1886 * is best to stay with this cheap workaround for now... .
1888 if (likely(bcm->initialized)) {
1889 /* disable all IRQs. They are enabled again in the bottom half. */
1890 bcm->irq_savedstate = bcm43xx_interrupt_disable(bcm, BCM43xx_IRQ_ALL);
1891 /* save the reason code and call our bottom half. */
1892 bcm->irq_reason = reason;
1893 tasklet_schedule(&bcm->isr_tasklet);
1898 spin_unlock(&bcm->_lock);
1903 static void bcm43xx_release_firmware(struct bcm43xx_private *bcm, int force)
1905 if (bcm->firmware_norelease && !force)
1906 return; /* Suspending or controller reset. */
1907 release_firmware(bcm->ucode);
1909 release_firmware(bcm->pcm);
1911 release_firmware(bcm->initvals0);
1912 bcm->initvals0 = NULL;
1913 release_firmware(bcm->initvals1);
1914 bcm->initvals1 = NULL;
1917 static int bcm43xx_request_firmware(struct bcm43xx_private *bcm)
1919 struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
1920 u8 rev = bcm->current_core->rev;
1923 char buf[22 + sizeof(modparam_fwpostfix) - 1] = { 0 };
1926 snprintf(buf, ARRAY_SIZE(buf), "bcm43xx_microcode%d%s.fw",
1927 (rev >= 5 ? 5 : rev),
1928 modparam_fwpostfix);
1929 err = request_firmware(&bcm->ucode, buf, &bcm->pci_dev->dev);
1932 "Error: Microcode \"%s\" not available or load failed.\n",
1939 snprintf(buf, ARRAY_SIZE(buf),
1940 "bcm43xx_pcm%d%s.fw",
1942 modparam_fwpostfix);
1943 err = request_firmware(&bcm->pcm, buf, &bcm->pci_dev->dev);
1946 "Error: PCM \"%s\" not available or load failed.\n",
1952 if (!bcm->initvals0) {
1953 if (rev == 2 || rev == 4) {
1954 switch (phy->type) {
1955 case BCM43xx_PHYTYPE_A:
1958 case BCM43xx_PHYTYPE_B:
1959 case BCM43xx_PHYTYPE_G:
1966 } else if (rev >= 5) {
1967 switch (phy->type) {
1968 case BCM43xx_PHYTYPE_A:
1971 case BCM43xx_PHYTYPE_B:
1972 case BCM43xx_PHYTYPE_G:
1980 snprintf(buf, ARRAY_SIZE(buf), "bcm43xx_initval%02d%s.fw",
1981 nr, modparam_fwpostfix);
1983 err = request_firmware(&bcm->initvals0, buf, &bcm->pci_dev->dev);
1986 "Error: InitVals \"%s\" not available or load failed.\n",
1990 if (bcm->initvals0->size % sizeof(struct bcm43xx_initval)) {
1991 printk(KERN_ERR PFX "InitVals fileformat error.\n");
1996 if (!bcm->initvals1) {
2000 switch (phy->type) {
2001 case BCM43xx_PHYTYPE_A:
2002 sbtmstatehigh = bcm43xx_read32(bcm, BCM43xx_CIR_SBTMSTATEHIGH);
2003 if (sbtmstatehigh & 0x00010000)
2008 case BCM43xx_PHYTYPE_B:
2009 case BCM43xx_PHYTYPE_G:
2015 snprintf(buf, ARRAY_SIZE(buf), "bcm43xx_initval%02d%s.fw",
2016 nr, modparam_fwpostfix);
2018 err = request_firmware(&bcm->initvals1, buf, &bcm->pci_dev->dev);
2021 "Error: InitVals \"%s\" not available or load failed.\n",
2025 if (bcm->initvals1->size % sizeof(struct bcm43xx_initval)) {
2026 printk(KERN_ERR PFX "InitVals fileformat error.\n");
2035 bcm43xx_release_firmware(bcm, 1);
2038 printk(KERN_ERR PFX "Error: No InitVals available!\n");
2043 static void bcm43xx_upload_microcode(struct bcm43xx_private *bcm)
2046 unsigned int i, len;
2048 /* Upload Microcode. */
2049 data = (u32 *)(bcm->ucode->data);
2050 len = bcm->ucode->size / sizeof(u32);
2051 bcm43xx_shm_control_word(bcm, BCM43xx_SHM_UCODE, 0x0000);
2052 for (i = 0; i < len; i++) {
2053 bcm43xx_write32(bcm, BCM43xx_MMIO_SHM_DATA,
2054 be32_to_cpu(data[i]));
2058 /* Upload PCM data. */
2059 data = (u32 *)(bcm->pcm->data);
2060 len = bcm->pcm->size / sizeof(u32);
2061 bcm43xx_shm_control_word(bcm, BCM43xx_SHM_PCM, 0x01ea);
2062 bcm43xx_write32(bcm, BCM43xx_MMIO_SHM_DATA, 0x00004000);
2063 bcm43xx_shm_control_word(bcm, BCM43xx_SHM_PCM, 0x01eb);
2064 for (i = 0; i < len; i++) {
2065 bcm43xx_write32(bcm, BCM43xx_MMIO_SHM_DATA,
2066 be32_to_cpu(data[i]));
2071 static int bcm43xx_write_initvals(struct bcm43xx_private *bcm,
2072 const struct bcm43xx_initval *data,
2073 const unsigned int len)
2079 for (i = 0; i < len; i++) {
2080 offset = be16_to_cpu(data[i].offset);
2081 size = be16_to_cpu(data[i].size);
2082 value = be32_to_cpu(data[i].value);
2084 if (unlikely(offset >= 0x1000))
2087 if (unlikely(value & 0xFFFF0000))
2089 bcm43xx_write16(bcm, offset, (u16)value);
2090 } else if (size == 4) {
2091 bcm43xx_write32(bcm, offset, value);
2099 printk(KERN_ERR PFX "InitVals (bcm43xx_initvalXX.fw) file-format error. "
2100 "Please fix your bcm43xx firmware files.\n");
2104 static int bcm43xx_upload_initvals(struct bcm43xx_private *bcm)
2108 err = bcm43xx_write_initvals(bcm, (struct bcm43xx_initval *)bcm->initvals0->data,
2109 bcm->initvals0->size / sizeof(struct bcm43xx_initval));
2112 if (bcm->initvals1) {
2113 err = bcm43xx_write_initvals(bcm, (struct bcm43xx_initval *)bcm->initvals1->data,
2114 bcm->initvals1->size / sizeof(struct bcm43xx_initval));
2122 static int bcm43xx_initialize_irq(struct bcm43xx_private *bcm)
2128 bcm->irq = bcm->pci_dev->irq;
2129 #ifdef CONFIG_BCM947XX
2130 if (bcm->pci_dev->bus->number == 0) {
2131 struct pci_dev *d = NULL;
2132 /* FIXME: we will probably need more device IDs here... */
2133 d = pci_find_device(PCI_VENDOR_ID_BROADCOM, 0x4324, NULL);
2139 res = request_irq(bcm->irq, bcm43xx_interrupt_handler,
2140 SA_SHIRQ, KBUILD_MODNAME, bcm);
2142 printk(KERN_ERR PFX "Cannot register IRQ%d\n", bcm->irq);
2145 bcm43xx_write32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON, 0xffffffff);
2146 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD, 0x00020402);
2149 data = bcm43xx_read32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON);
2150 if (data == BCM43xx_IRQ_READY)
2153 if (i >= BCM43xx_IRQWAIT_MAX_RETRIES) {
2154 printk(KERN_ERR PFX "Card IRQ register not responding. "
2156 free_irq(bcm->irq, bcm);
2162 bcm43xx_read32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON);
2167 /* Switch to the core used to write the GPIO register.
2168 * This is either the ChipCommon, or the PCI core.
2170 static int switch_to_gpio_core(struct bcm43xx_private *bcm)
2174 /* Where to find the GPIO register depends on the chipset.
2175 * If it has a ChipCommon, its register at offset 0x6c is the GPIO
2176 * control register. Otherwise the register at offset 0x6c in the
2177 * PCI core is the GPIO control register.
2179 err = bcm43xx_switch_core(bcm, &bcm->core_chipcommon);
2180 if (err == -ENODEV) {
2181 err = bcm43xx_switch_core(bcm, &bcm->core_pci);
2182 if (unlikely(err == -ENODEV)) {
2183 printk(KERN_ERR PFX "gpio error: "
2184 "Neither ChipCommon nor PCI core available!\n");
2186 } else if (unlikely(err != 0))
2188 } else if (unlikely(err != 0))
2194 /* Initialize the GPIOs
2195 * http://bcm-specs.sipsolutions.net/GPIO
2197 static int bcm43xx_gpio_init(struct bcm43xx_private *bcm)
2199 struct bcm43xx_coreinfo *old_core;
2203 value = bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD);
2205 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD, value);
2209 bcm43xx_write16(bcm, BCM43xx_MMIO_GPIO_CONTROL,
2210 bcm43xx_read16(bcm, BCM43xx_MMIO_GPIO_CONTROL) & 0xFFF0);
2211 bcm43xx_write16(bcm, BCM43xx_MMIO_GPIO_MASK,
2212 bcm43xx_read16(bcm, BCM43xx_MMIO_GPIO_MASK) | 0x000F);
2214 old_core = bcm->current_core;
2216 err = switch_to_gpio_core(bcm);
2220 if (bcm->current_core->rev >= 2){
2224 if (bcm->chip_id == 0x4301) {
2228 if (bcm->sprom.boardflags & BCM43xx_BFL_PACTRL) {
2233 bcm43xx_write32(bcm, BCM43xx_GPIO_CONTROL,
2234 (bcm43xx_read32(bcm, BCM43xx_GPIO_CONTROL) & mask) | value);
2236 err = bcm43xx_switch_core(bcm, old_core);
2242 /* Turn off all GPIO stuff. Call this on module unload, for example. */
2243 static int bcm43xx_gpio_cleanup(struct bcm43xx_private *bcm)
2245 struct bcm43xx_coreinfo *old_core;
2248 old_core = bcm->current_core;
2249 err = switch_to_gpio_core(bcm);
2252 bcm43xx_write32(bcm, BCM43xx_GPIO_CONTROL, 0x00000000);
2253 err = bcm43xx_switch_core(bcm, old_core);
2259 /* http://bcm-specs.sipsolutions.net/EnableMac */
2260 void bcm43xx_mac_enable(struct bcm43xx_private *bcm)
2262 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD,
2263 bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD)
2264 | BCM43xx_SBF_MAC_ENABLED);
2265 bcm43xx_write32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON, BCM43xx_IRQ_READY);
2266 bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD); /* dummy read */
2267 bcm43xx_read32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON); /* dummy read */
2268 bcm43xx_power_saving_ctl_bits(bcm, -1, -1);
2271 /* http://bcm-specs.sipsolutions.net/SuspendMAC */
2272 void bcm43xx_mac_suspend(struct bcm43xx_private *bcm)
2277 bcm43xx_power_saving_ctl_bits(bcm, -1, 1);
2278 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD,
2279 bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD)
2280 & ~BCM43xx_SBF_MAC_ENABLED);
2281 bcm43xx_read32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON); /* dummy read */
2282 for (i = 100000; i; i--) {
2283 tmp = bcm43xx_read32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON);
2284 if (tmp & BCM43xx_IRQ_READY)
2288 printkl(KERN_ERR PFX "MAC suspend failed\n");
2291 void bcm43xx_set_iwmode(struct bcm43xx_private *bcm,
2294 unsigned long flags;
2297 spin_lock_irqsave(&bcm->ieee->lock, flags);
2298 bcm->ieee->iw_mode = iw_mode;
2299 spin_unlock_irqrestore(&bcm->ieee->lock, flags);
2300 if (iw_mode == IW_MODE_MONITOR)
2301 bcm->net_dev->type = ARPHRD_IEEE80211;
2303 bcm->net_dev->type = ARPHRD_ETHER;
2305 if (!bcm->initialized)
2308 bcm43xx_mac_suspend(bcm);
2309 status = bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD);
2310 /* Reset status to infrastructured mode */
2311 status &= ~(BCM43xx_SBF_MODE_AP | BCM43xx_SBF_MODE_MONITOR);
2312 /*FIXME: We actually set promiscuous mode as well, until we don't
2313 * get the HW mac filter working */
2314 status |= BCM43xx_SBF_MODE_NOTADHOC | BCM43xx_SBF_MODE_PROMISC;
2317 case IW_MODE_MONITOR:
2318 status |= (BCM43xx_SBF_MODE_PROMISC |
2319 BCM43xx_SBF_MODE_MONITOR);
2322 status &= ~BCM43xx_SBF_MODE_NOTADHOC;
2324 case IW_MODE_MASTER:
2325 case IW_MODE_SECOND:
2326 case IW_MODE_REPEAT:
2327 /* TODO: No AP/Repeater mode for now :-/ */
2331 /* nothing to be done here... */
2334 printk(KERN_ERR PFX "Unknown iwmode %d\n", iw_mode);
2337 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD, status);
2338 bcm43xx_mac_enable(bcm);
2341 /* This is the opposite of bcm43xx_chip_init() */
2342 static void bcm43xx_chip_cleanup(struct bcm43xx_private *bcm)
2344 bcm43xx_radio_turn_off(bcm);
2345 if (!modparam_noleds)
2346 bcm43xx_leds_exit(bcm);
2347 bcm43xx_gpio_cleanup(bcm);
2348 free_irq(bcm->irq, bcm);
2349 bcm43xx_release_firmware(bcm, 0);
2352 /* Initialize the chip
2353 * http://bcm-specs.sipsolutions.net/ChipInit
2355 static int bcm43xx_chip_init(struct bcm43xx_private *bcm)
2357 struct bcm43xx_radioinfo *radio = bcm43xx_current_radio(bcm);
2358 struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
2360 int iw_mode = bcm->ieee->iw_mode;
2365 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD,
2366 BCM43xx_SBF_CORE_READY
2369 err = bcm43xx_request_firmware(bcm);
2372 bcm43xx_upload_microcode(bcm);
2374 err = bcm43xx_initialize_irq(bcm);
2376 goto err_release_fw;
2378 err = bcm43xx_gpio_init(bcm);
2382 err = bcm43xx_upload_initvals(bcm);
2384 goto err_gpio_cleanup;
2385 bcm43xx_radio_turn_on(bcm);
2387 if (modparam_noleds)
2388 bcm43xx_leds_turn_off(bcm);
2390 bcm43xx_leds_update(bcm, 0);
2392 bcm43xx_write16(bcm, 0x03E6, 0x0000);
2393 err = bcm43xx_phy_init(bcm);
2397 /* Select initial Interference Mitigation. */
2398 tmp = radio->interfmode;
2399 radio->interfmode = BCM43xx_RADIO_INTERFMODE_NONE;
2400 bcm43xx_radio_set_interference_mitigation(bcm, tmp);
2402 bcm43xx_phy_set_antenna_diversity(bcm);
2403 bcm43xx_radio_set_txantenna(bcm, BCM43xx_RADIO_TXANTENNA_DEFAULT);
2404 if (phy->type == BCM43xx_PHYTYPE_B) {
2405 value16 = bcm43xx_read16(bcm, 0x005E);
2407 bcm43xx_write16(bcm, 0x005E, value16);
2409 bcm43xx_write32(bcm, 0x0100, 0x01000000);
2410 if (bcm->current_core->rev < 5)
2411 bcm43xx_write32(bcm, 0x010C, 0x01000000);
2413 value32 = bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD);
2414 value32 &= ~ BCM43xx_SBF_MODE_NOTADHOC;
2415 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD, value32);
2416 value32 = bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD);
2417 value32 |= BCM43xx_SBF_MODE_NOTADHOC;
2418 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD, value32);
2419 /*FIXME: For now, use promiscuous mode at all times; otherwise we don't
2420 get broadcast or multicast packets */
2421 value32 = bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD);
2422 value32 |= BCM43xx_SBF_MODE_PROMISC;
2423 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD, value32);
2425 if (iw_mode == IW_MODE_MONITOR) {
2426 value32 = bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD);
2427 value32 |= BCM43xx_SBF_MODE_PROMISC;
2428 value32 |= BCM43xx_SBF_MODE_MONITOR;
2429 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD, value32);
2431 value32 = bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD);
2432 value32 |= 0x100000; //FIXME: What's this? Is this correct?
2433 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD, value32);
2435 if (bcm43xx_using_pio(bcm)) {
2436 bcm43xx_write32(bcm, 0x0210, 0x00000100);
2437 bcm43xx_write32(bcm, 0x0230, 0x00000100);
2438 bcm43xx_write32(bcm, 0x0250, 0x00000100);
2439 bcm43xx_write32(bcm, 0x0270, 0x00000100);
2440 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, 0x0034, 0x0000);
2443 /* Probe Response Timeout value */
2444 /* FIXME: Default to 0, has to be set by ioctl probably... :-/ */
2445 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, 0x0074, 0x0000);
2447 if (iw_mode != IW_MODE_ADHOC && iw_mode != IW_MODE_MASTER) {
2448 if ((bcm->chip_id == 0x4306) && (bcm->chip_rev == 3))
2449 bcm43xx_write16(bcm, 0x0612, 0x0064);
2451 bcm43xx_write16(bcm, 0x0612, 0x0032);
2453 bcm43xx_write16(bcm, 0x0612, 0x0002);
2455 if (bcm->current_core->rev < 3) {
2456 bcm43xx_write16(bcm, 0x060E, 0x0000);
2457 bcm43xx_write16(bcm, 0x0610, 0x8000);
2458 bcm43xx_write16(bcm, 0x0604, 0x0000);
2459 bcm43xx_write16(bcm, 0x0606, 0x0200);
2461 bcm43xx_write32(bcm, 0x0188, 0x80000000);
2462 bcm43xx_write32(bcm, 0x018C, 0x02000000);
2464 bcm43xx_write32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON, 0x00004000);
2465 bcm43xx_write32(bcm, BCM43xx_MMIO_DMA1_IRQ_MASK, 0x0001DC00);
2466 bcm43xx_write32(bcm, BCM43xx_MMIO_DMA2_IRQ_MASK, 0x0000DC00);
2467 bcm43xx_write32(bcm, BCM43xx_MMIO_DMA3_IRQ_MASK, 0x0000DC00);
2468 bcm43xx_write32(bcm, BCM43xx_MMIO_DMA4_IRQ_MASK, 0x0001DC00);
2470 value32 = bcm43xx_read32(bcm, BCM43xx_CIR_SBTMSTATELOW);
2471 value32 |= 0x00100000;
2472 bcm43xx_write32(bcm, BCM43xx_CIR_SBTMSTATELOW, value32);
2474 bcm43xx_write16(bcm, BCM43xx_MMIO_POWERUP_DELAY, bcm43xx_pctl_powerup_delay(bcm));
2477 dprintk(KERN_INFO PFX "Chip initialized\n");
2482 bcm43xx_radio_turn_off(bcm);
2484 bcm43xx_gpio_cleanup(bcm);
2486 free_irq(bcm->irq, bcm);
2488 bcm43xx_release_firmware(bcm, 1);
2492 /* Validate chip access
2493 * http://bcm-specs.sipsolutions.net/ValidateChipAccess */
2494 static int bcm43xx_validate_chip(struct bcm43xx_private *bcm)
2499 shm_backup = bcm43xx_shm_read32(bcm, BCM43xx_SHM_SHARED, 0x0000);
2500 bcm43xx_shm_write32(bcm, BCM43xx_SHM_SHARED, 0x0000, 0xAA5555AA);
2501 if (bcm43xx_shm_read32(bcm, BCM43xx_SHM_SHARED, 0x0000) != 0xAA5555AA)
2503 bcm43xx_shm_write32(bcm, BCM43xx_SHM_SHARED, 0x0000, 0x55AAAA55);
2504 if (bcm43xx_shm_read32(bcm, BCM43xx_SHM_SHARED, 0x0000) != 0x55AAAA55)
2506 bcm43xx_shm_write32(bcm, BCM43xx_SHM_SHARED, 0x0000, shm_backup);
2508 value = bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD);
2509 if ((value | 0x80000000) != 0x80000400)
2512 value = bcm43xx_read32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON);
2513 if (value != 0x00000000)
2518 printk(KERN_ERR PFX "Failed to validate the chipaccess\n");
2522 void bcm43xx_init_struct_phyinfo(struct bcm43xx_phyinfo *phy)
2524 /* Initialize a "phyinfo" structure. The structure is already
2527 phy->antenna_diversity = 0xFFFF;
2528 phy->savedpctlreg = 0xFFFF;
2529 phy->minlowsig[0] = 0xFFFF;
2530 phy->minlowsig[1] = 0xFFFF;
2531 spin_lock_init(&phy->lock);
2534 void bcm43xx_init_struct_radioinfo(struct bcm43xx_radioinfo *radio)
2536 /* Initialize a "radioinfo" structure. The structure is already
2539 radio->interfmode = BCM43xx_RADIO_INTERFMODE_NONE;
2540 radio->channel = 0xFF;
2541 radio->initial_channel = 0xFF;
2542 radio->lofcal = 0xFFFF;
2543 radio->initval = 0xFFFF;
2544 radio->nrssi[0] = -1000;
2545 radio->nrssi[1] = -1000;
2548 static int bcm43xx_probe_cores(struct bcm43xx_private *bcm)
2552 u32 core_vendor, core_id, core_rev;
2553 u32 sb_id_hi, chip_id_32 = 0;
2554 u16 pci_device, chip_id_16;
2557 memset(&bcm->core_chipcommon, 0, sizeof(struct bcm43xx_coreinfo));
2558 memset(&bcm->core_pci, 0, sizeof(struct bcm43xx_coreinfo));
2559 memset(&bcm->core_80211, 0, sizeof(struct bcm43xx_coreinfo)
2560 * BCM43xx_MAX_80211_CORES);
2561 memset(&bcm->core_80211_ext, 0, sizeof(struct bcm43xx_coreinfo_80211)
2562 * BCM43xx_MAX_80211_CORES);
2563 bcm->current_80211_core_idx = -1;
2564 bcm->nr_80211_available = 0;
2565 bcm->current_core = NULL;
2566 bcm->active_80211_core = NULL;
2569 err = _switch_core(bcm, 0);
2573 /* fetch sb_id_hi from core information registers */
2574 sb_id_hi = bcm43xx_read32(bcm, BCM43xx_CIR_SB_ID_HI);
2576 core_id = (sb_id_hi & 0xFFF0) >> 4;
2577 core_rev = (sb_id_hi & 0xF);
2578 core_vendor = (sb_id_hi & 0xFFFF0000) >> 16;
2580 /* if present, chipcommon is always core 0; read the chipid from it */
2581 if (core_id == BCM43xx_COREID_CHIPCOMMON) {
2582 chip_id_32 = bcm43xx_read32(bcm, 0);
2583 chip_id_16 = chip_id_32 & 0xFFFF;
2584 bcm->core_chipcommon.available = 1;
2585 bcm->core_chipcommon.id = core_id;
2586 bcm->core_chipcommon.rev = core_rev;
2587 bcm->core_chipcommon.index = 0;
2588 /* While we are at it, also read the capabilities. */
2589 bcm->chipcommon_capabilities = bcm43xx_read32(bcm, BCM43xx_CHIPCOMMON_CAPABILITIES);
2591 /* without a chipCommon, use a hard coded table. */
2592 pci_device = bcm->pci_dev->device;
2593 if (pci_device == 0x4301)
2594 chip_id_16 = 0x4301;
2595 else if ((pci_device >= 0x4305) && (pci_device <= 0x4307))
2596 chip_id_16 = 0x4307;
2597 else if ((pci_device >= 0x4402) && (pci_device <= 0x4403))
2598 chip_id_16 = 0x4402;
2599 else if ((pci_device >= 0x4610) && (pci_device <= 0x4615))
2600 chip_id_16 = 0x4610;
2601 else if ((pci_device >= 0x4710) && (pci_device <= 0x4715))
2602 chip_id_16 = 0x4710;
2603 #ifdef CONFIG_BCM947XX
2604 else if ((pci_device >= 0x4320) && (pci_device <= 0x4325))
2605 chip_id_16 = 0x4309;
2608 printk(KERN_ERR PFX "Could not determine Chip ID\n");
2613 /* ChipCommon with Core Rev >=4 encodes number of cores,
2614 * otherwise consult hardcoded table */
2615 if ((core_id == BCM43xx_COREID_CHIPCOMMON) && (core_rev >= 4)) {
2616 core_count = (chip_id_32 & 0x0F000000) >> 24;
2618 switch (chip_id_16) {
2641 /* SOL if we get here */
2647 bcm->chip_id = chip_id_16;
2648 bcm->chip_rev = (chip_id_32 & 0x000f0000) >> 16;
2650 dprintk(KERN_INFO PFX "Chip ID 0x%x, rev 0x%x\n",
2651 bcm->chip_id, bcm->chip_rev);
2652 dprintk(KERN_INFO PFX "Number of cores: %d\n", core_count);
2653 if (bcm->core_chipcommon.available) {
2654 dprintk(KERN_INFO PFX "Core 0: ID 0x%x, rev 0x%x, vendor 0x%x, %s\n",
2655 core_id, core_rev, core_vendor,
2656 bcm43xx_core_enabled(bcm) ? "enabled" : "disabled");
2659 if (bcm->core_chipcommon.available)
2663 for ( ; current_core < core_count; current_core++) {
2664 struct bcm43xx_coreinfo *core;
2665 struct bcm43xx_coreinfo_80211 *ext_80211;
2667 err = _switch_core(bcm, current_core);
2670 /* Gather information */
2671 /* fetch sb_id_hi from core information registers */
2672 sb_id_hi = bcm43xx_read32(bcm, BCM43xx_CIR_SB_ID_HI);
2674 /* extract core_id, core_rev, core_vendor */
2675 core_id = (sb_id_hi & 0xFFF0) >> 4;
2676 core_rev = (sb_id_hi & 0xF);
2677 core_vendor = (sb_id_hi & 0xFFFF0000) >> 16;
2679 dprintk(KERN_INFO PFX "Core %d: ID 0x%x, rev 0x%x, vendor 0x%x, %s\n",
2680 current_core, core_id, core_rev, core_vendor,
2681 bcm43xx_core_enabled(bcm) ? "enabled" : "disabled" );
2685 case BCM43xx_COREID_PCI:
2686 core = &bcm->core_pci;
2687 if (core->available) {
2688 printk(KERN_WARNING PFX "Multiple PCI cores found.\n");
2692 case BCM43xx_COREID_80211:
2693 for (i = 0; i < BCM43xx_MAX_80211_CORES; i++) {
2694 core = &(bcm->core_80211[i]);
2695 ext_80211 = &(bcm->core_80211_ext[i]);
2696 if (!core->available)
2701 printk(KERN_WARNING PFX "More than %d cores of type 802.11 found.\n",
2702 BCM43xx_MAX_80211_CORES);
2706 /* More than one 80211 core is only supported
2708 * There are chips with two 80211 cores, but with
2709 * dangling pins on the second core. Be careful
2710 * and ignore these cores here.
2712 if (bcm->pci_dev->device != 0x4324) {
2713 dprintk(KERN_INFO PFX "Ignoring additional 802.11 core.\n");
2726 printk(KERN_ERR PFX "Error: Unsupported 80211 core revision %u\n",
2731 bcm->nr_80211_available++;
2732 bcm43xx_init_struct_phyinfo(&ext_80211->phy);
2733 bcm43xx_init_struct_radioinfo(&ext_80211->radio);
2735 case BCM43xx_COREID_CHIPCOMMON:
2736 printk(KERN_WARNING PFX "Multiple CHIPCOMMON cores found.\n");
2740 core->available = 1;
2742 core->rev = core_rev;
2743 core->index = current_core;
2747 if (!bcm->core_80211[0].available) {
2748 printk(KERN_ERR PFX "Error: No 80211 core found!\n");
2753 err = bcm43xx_switch_core(bcm, &bcm->core_80211[0]);
2760 static void bcm43xx_gen_bssid(struct bcm43xx_private *bcm)
2762 const u8 *mac = (const u8*)(bcm->net_dev->dev_addr);
2763 u8 *bssid = bcm->ieee->bssid;
2765 switch (bcm->ieee->iw_mode) {
2767 random_ether_addr(bssid);
2769 case IW_MODE_MASTER:
2771 case IW_MODE_REPEAT:
2772 case IW_MODE_SECOND:
2773 case IW_MODE_MONITOR:
2774 memcpy(bssid, mac, ETH_ALEN);
2781 static void bcm43xx_rate_memory_write(struct bcm43xx_private *bcm,
2789 offset += (bcm43xx_plcp_get_ratecode_ofdm(rate) & 0x000F) * 2;
2793 offset += (bcm43xx_plcp_get_ratecode_cck(rate) & 0x000F) * 2;
2795 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, offset + 0x20,
2796 bcm43xx_shm_read16(bcm, BCM43xx_SHM_SHARED, offset));
2799 static void bcm43xx_rate_memory_init(struct bcm43xx_private *bcm)
2801 switch (bcm43xx_current_phy(bcm)->type) {
2802 case BCM43xx_PHYTYPE_A:
2803 case BCM43xx_PHYTYPE_G:
2804 bcm43xx_rate_memory_write(bcm, IEEE80211_OFDM_RATE_6MB, 1);
2805 bcm43xx_rate_memory_write(bcm, IEEE80211_OFDM_RATE_12MB, 1);
2806 bcm43xx_rate_memory_write(bcm, IEEE80211_OFDM_RATE_18MB, 1);
2807 bcm43xx_rate_memory_write(bcm, IEEE80211_OFDM_RATE_24MB, 1);
2808 bcm43xx_rate_memory_write(bcm, IEEE80211_OFDM_RATE_36MB, 1);
2809 bcm43xx_rate_memory_write(bcm, IEEE80211_OFDM_RATE_48MB, 1);
2810 bcm43xx_rate_memory_write(bcm, IEEE80211_OFDM_RATE_54MB, 1);
2811 case BCM43xx_PHYTYPE_B:
2812 bcm43xx_rate_memory_write(bcm, IEEE80211_CCK_RATE_1MB, 0);
2813 bcm43xx_rate_memory_write(bcm, IEEE80211_CCK_RATE_2MB, 0);
2814 bcm43xx_rate_memory_write(bcm, IEEE80211_CCK_RATE_5MB, 0);
2815 bcm43xx_rate_memory_write(bcm, IEEE80211_CCK_RATE_11MB, 0);
2822 static void bcm43xx_wireless_core_cleanup(struct bcm43xx_private *bcm)
2824 bcm43xx_chip_cleanup(bcm);
2825 bcm43xx_pio_free(bcm);
2826 bcm43xx_dma_free(bcm);
2828 bcm->current_core->initialized = 0;
2831 /* http://bcm-specs.sipsolutions.net/80211Init */
2832 static int bcm43xx_wireless_core_init(struct bcm43xx_private *bcm)
2834 struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
2835 struct bcm43xx_radioinfo *radio = bcm43xx_current_radio(bcm);
2841 if (bcm->chip_rev < 5) {
2842 sbimconfiglow = bcm43xx_read32(bcm, BCM43xx_CIR_SBIMCONFIGLOW);
2843 sbimconfiglow &= ~ BCM43xx_SBIMCONFIGLOW_REQUEST_TOUT_MASK;
2844 sbimconfiglow &= ~ BCM43xx_SBIMCONFIGLOW_SERVICE_TOUT_MASK;
2845 if (bcm->bustype == BCM43xx_BUSTYPE_PCI)
2846 sbimconfiglow |= 0x32;
2847 else if (bcm->bustype == BCM43xx_BUSTYPE_SB)
2848 sbimconfiglow |= 0x53;
2851 bcm43xx_write32(bcm, BCM43xx_CIR_SBIMCONFIGLOW, sbimconfiglow);
2854 bcm43xx_phy_calibrate(bcm);
2855 err = bcm43xx_chip_init(bcm);
2859 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, 0x0016, bcm->current_core->rev);
2860 ucodeflags = bcm43xx_shm_read32(bcm, BCM43xx_SHM_SHARED, BCM43xx_UCODEFLAGS_OFFSET);
2862 if (0 /*FIXME: which condition has to be used here? */)
2863 ucodeflags |= 0x00000010;
2865 /* HW decryption needs to be set now */
2866 ucodeflags |= 0x40000000;
2868 if (phy->type == BCM43xx_PHYTYPE_G) {
2869 ucodeflags |= BCM43xx_UCODEFLAG_UNKBGPHY;
2871 ucodeflags |= BCM43xx_UCODEFLAG_UNKGPHY;
2872 if (bcm->sprom.boardflags & BCM43xx_BFL_PACTRL)
2873 ucodeflags |= BCM43xx_UCODEFLAG_UNKPACTRL;
2874 } else if (phy->type == BCM43xx_PHYTYPE_B) {
2875 ucodeflags |= BCM43xx_UCODEFLAG_UNKBGPHY;
2876 if (phy->rev >= 2 && radio->version == 0x2050)
2877 ucodeflags &= ~BCM43xx_UCODEFLAG_UNKGPHY;
2880 if (ucodeflags != bcm43xx_shm_read32(bcm, BCM43xx_SHM_SHARED,
2881 BCM43xx_UCODEFLAGS_OFFSET)) {
2882 bcm43xx_shm_write32(bcm, BCM43xx_SHM_SHARED,
2883 BCM43xx_UCODEFLAGS_OFFSET, ucodeflags);
2886 /* Short/Long Retry Limit.
2887 * The retry-limit is a 4-bit counter. Enforce this to avoid overflowing
2888 * the chip-internal counter.
2890 limit = limit_value(modparam_short_retry, 0, 0xF);
2891 bcm43xx_shm_write32(bcm, BCM43xx_SHM_WIRELESS, 0x0006, limit);
2892 limit = limit_value(modparam_long_retry, 0, 0xF);
2893 bcm43xx_shm_write32(bcm, BCM43xx_SHM_WIRELESS, 0x0007, limit);
2895 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, 0x0044, 3);
2896 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, 0x0046, 2);
2898 bcm43xx_rate_memory_init(bcm);
2900 /* Minimum Contention Window */
2901 if (phy->type == BCM43xx_PHYTYPE_B)
2902 bcm43xx_shm_write32(bcm, BCM43xx_SHM_WIRELESS, 0x0003, 0x0000001f);
2904 bcm43xx_shm_write32(bcm, BCM43xx_SHM_WIRELESS, 0x0003, 0x0000000f);
2905 /* Maximum Contention Window */
2906 bcm43xx_shm_write32(bcm, BCM43xx_SHM_WIRELESS, 0x0004, 0x000003ff);
2908 bcm43xx_gen_bssid(bcm);
2909 bcm43xx_write_mac_bssid_templates(bcm);
2911 if (bcm->current_core->rev >= 5)
2912 bcm43xx_write16(bcm, 0x043C, 0x000C);
2914 if (bcm43xx_using_pio(bcm))
2915 err = bcm43xx_pio_init(bcm);
2917 err = bcm43xx_dma_init(bcm);
2919 goto err_chip_cleanup;
2920 bcm43xx_write16(bcm, 0x0612, 0x0050);
2921 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, 0x0416, 0x0050);
2922 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, 0x0414, 0x01F4);
2924 bcm43xx_mac_enable(bcm);
2925 bcm43xx_interrupt_enable(bcm, bcm->irq_savedstate);
2927 bcm->current_core->initialized = 1;
2932 bcm43xx_chip_cleanup(bcm);
2936 static int bcm43xx_chipset_attach(struct bcm43xx_private *bcm)
2941 err = bcm43xx_pctl_set_crystal(bcm, 1);
2944 bcm43xx_pci_read_config16(bcm, PCI_STATUS, &pci_status);
2945 bcm43xx_pci_write_config16(bcm, PCI_STATUS, pci_status & ~PCI_STATUS_SIG_TARGET_ABORT);
2951 static void bcm43xx_chipset_detach(struct bcm43xx_private *bcm)
2953 bcm43xx_pctl_set_clock(bcm, BCM43xx_PCTL_CLK_SLOW);
2954 bcm43xx_pctl_set_crystal(bcm, 0);
2957 static void bcm43xx_pcicore_broadcast_value(struct bcm43xx_private *bcm,
2961 bcm43xx_write32(bcm, BCM43xx_PCICORE_BCAST_ADDR, address);
2962 bcm43xx_write32(bcm, BCM43xx_PCICORE_BCAST_DATA, data);
2965 static int bcm43xx_pcicore_commit_settings(struct bcm43xx_private *bcm)
2968 struct bcm43xx_coreinfo *old_core;
2970 old_core = bcm->current_core;
2971 err = bcm43xx_switch_core(bcm, &bcm->core_pci);
2975 bcm43xx_pcicore_broadcast_value(bcm, 0xfd8, 0x00000000);
2977 bcm43xx_switch_core(bcm, old_core);
2983 /* Make an I/O Core usable. "core_mask" is the bitmask of the cores to enable.
2984 * To enable core 0, pass a core_mask of 1<<0
2986 static int bcm43xx_setup_backplane_pci_connection(struct bcm43xx_private *bcm,
2989 u32 backplane_flag_nr;
2991 struct bcm43xx_coreinfo *old_core;
2994 value = bcm43xx_read32(bcm, BCM43xx_CIR_SBTPSFLAG);
2995 backplane_flag_nr = value & BCM43xx_BACKPLANE_FLAG_NR_MASK;
2997 old_core = bcm->current_core;
2998 err = bcm43xx_switch_core(bcm, &bcm->core_pci);
3002 if (bcm->core_pci.rev < 6) {
3003 value = bcm43xx_read32(bcm, BCM43xx_CIR_SBINTVEC);
3004 value |= (1 << backplane_flag_nr);
3005 bcm43xx_write32(bcm, BCM43xx_CIR_SBINTVEC, value);
3007 err = bcm43xx_pci_read_config32(bcm, BCM43xx_PCICFG_ICR, &value);
3009 printk(KERN_ERR PFX "Error: ICR setup failure!\n");
3010 goto out_switch_back;
3012 value |= core_mask << 8;
3013 err = bcm43xx_pci_write_config32(bcm, BCM43xx_PCICFG_ICR, value);
3015 printk(KERN_ERR PFX "Error: ICR setup failure!\n");
3016 goto out_switch_back;
3020 value = bcm43xx_read32(bcm, BCM43xx_PCICORE_SBTOPCI2);
3021 value |= BCM43xx_SBTOPCI2_PREFETCH | BCM43xx_SBTOPCI2_BURST;
3022 bcm43xx_write32(bcm, BCM43xx_PCICORE_SBTOPCI2, value);
3024 if (bcm->core_pci.rev < 5) {
3025 value = bcm43xx_read32(bcm, BCM43xx_CIR_SBIMCONFIGLOW);
3026 value |= (2 << BCM43xx_SBIMCONFIGLOW_SERVICE_TOUT_SHIFT)
3027 & BCM43xx_SBIMCONFIGLOW_SERVICE_TOUT_MASK;
3028 value |= (3 << BCM43xx_SBIMCONFIGLOW_REQUEST_TOUT_SHIFT)
3029 & BCM43xx_SBIMCONFIGLOW_REQUEST_TOUT_MASK;
3030 bcm43xx_write32(bcm, BCM43xx_CIR_SBIMCONFIGLOW, value);
3031 err = bcm43xx_pcicore_commit_settings(bcm);
3036 err = bcm43xx_switch_core(bcm, old_core);
3041 static void bcm43xx_softmac_init(struct bcm43xx_private *bcm)
3043 ieee80211softmac_start(bcm->net_dev);
3046 static void bcm43xx_periodic_every120sec(struct bcm43xx_private *bcm)
3048 struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
3050 if (phy->type != BCM43xx_PHYTYPE_G || phy->rev < 2)
3053 bcm43xx_mac_suspend(bcm);
3054 bcm43xx_phy_lo_g_measure(bcm);
3055 bcm43xx_mac_enable(bcm);
3058 static void bcm43xx_periodic_every60sec(struct bcm43xx_private *bcm)
3060 bcm43xx_phy_lo_mark_all_unused(bcm);
3061 if (bcm->sprom.boardflags & BCM43xx_BFL_RSSI) {
3062 bcm43xx_mac_suspend(bcm);
3063 bcm43xx_calc_nrssi_slope(bcm);
3064 bcm43xx_mac_enable(bcm);
3068 static void bcm43xx_periodic_every30sec(struct bcm43xx_private *bcm)
3070 /* Update device statistics. */
3071 bcm43xx_calculate_link_quality(bcm);
3074 static void bcm43xx_periodic_every15sec(struct bcm43xx_private *bcm)
3076 struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
3077 struct bcm43xx_radioinfo *radio = bcm43xx_current_radio(bcm);
3079 if (phy->type == BCM43xx_PHYTYPE_G) {
3080 //TODO: update_aci_moving_average
3081 if (radio->aci_enable && radio->aci_wlan_automatic) {
3082 bcm43xx_mac_suspend(bcm);
3083 if (!radio->aci_enable && 1 /*TODO: not scanning? */) {
3084 if (0 /*TODO: bunch of conditions*/) {
3085 bcm43xx_radio_set_interference_mitigation(bcm,
3086 BCM43xx_RADIO_INTERFMODE_MANUALWLAN);
3088 } else if (1/*TODO*/) {
3090 if ((aci_average > 1000) && !(bcm43xx_radio_aci_scan(bcm))) {
3091 bcm43xx_radio_set_interference_mitigation(bcm,
3092 BCM43xx_RADIO_INTERFMODE_NONE);
3096 bcm43xx_mac_enable(bcm);
3097 } else if (radio->interfmode == BCM43xx_RADIO_INTERFMODE_NONWLAN &&
3099 //TODO: implement rev1 workaround
3102 bcm43xx_phy_xmitpower(bcm); //FIXME: unless scanning?
3103 //TODO for APHY (temperature?)
3106 static void bcm43xx_periodic_task_handler(unsigned long d)
3108 struct bcm43xx_private *bcm = (struct bcm43xx_private *)d;
3109 unsigned long flags;
3112 bcm43xx_lock_mmio(bcm, flags);
3114 assert(bcm->initialized);
3115 state = bcm->periodic_state;
3117 bcm43xx_periodic_every120sec(bcm);
3119 bcm43xx_periodic_every60sec(bcm);
3121 bcm43xx_periodic_every30sec(bcm);
3122 bcm43xx_periodic_every15sec(bcm);
3123 bcm->periodic_state = state + 1;
3125 mod_timer(&bcm->periodic_tasks, jiffies + (HZ * 15));
3127 bcm43xx_unlock_mmio(bcm, flags);
3130 static void bcm43xx_periodic_tasks_delete(struct bcm43xx_private *bcm)
3132 del_timer_sync(&bcm->periodic_tasks);
3135 static void bcm43xx_periodic_tasks_setup(struct bcm43xx_private *bcm)
3137 struct timer_list *timer = &(bcm->periodic_tasks);
3139 assert(bcm->initialized);
3141 bcm43xx_periodic_task_handler,
3142 (unsigned long)bcm);
3143 timer->expires = jiffies;
3147 static void bcm43xx_security_init(struct bcm43xx_private *bcm)
3149 bcm->security_offset = bcm43xx_shm_read16(bcm, BCM43xx_SHM_SHARED,
3151 bcm43xx_clear_keys(bcm);
3154 /* This is the opposite of bcm43xx_init_board() */
3155 static void bcm43xx_free_board(struct bcm43xx_private *bcm)
3158 unsigned long flags;
3160 bcm43xx_sysfs_unregister(bcm);
3162 bcm43xx_periodic_tasks_delete(bcm);
3164 bcm43xx_lock(bcm, flags);
3165 bcm->initialized = 0;
3166 bcm->shutting_down = 1;
3167 bcm43xx_unlock(bcm, flags);
3169 for (i = 0; i < BCM43xx_MAX_80211_CORES; i++) {
3170 if (!bcm->core_80211[i].available)
3172 if (!bcm->core_80211[i].initialized)
3175 err = bcm43xx_switch_core(bcm, &bcm->core_80211[i]);
3177 bcm43xx_wireless_core_cleanup(bcm);
3180 bcm43xx_pctl_set_crystal(bcm, 0);
3182 bcm43xx_lock(bcm, flags);
3183 bcm->shutting_down = 0;
3184 bcm43xx_unlock(bcm, flags);
3187 static int bcm43xx_init_board(struct bcm43xx_private *bcm)
3191 unsigned long flags;
3195 bcm43xx_lock(bcm, flags);
3196 bcm->initialized = 0;
3197 bcm->shutting_down = 0;
3198 bcm43xx_unlock(bcm, flags);
3200 err = bcm43xx_pctl_set_crystal(bcm, 1);
3203 err = bcm43xx_pctl_init(bcm);
3205 goto err_crystal_off;
3206 err = bcm43xx_pctl_set_clock(bcm, BCM43xx_PCTL_CLK_FAST);
3208 goto err_crystal_off;
3210 tasklet_enable(&bcm->isr_tasklet);
3211 for (i = 0; i < bcm->nr_80211_available; i++) {
3212 err = bcm43xx_switch_core(bcm, &bcm->core_80211[i]);
3213 assert(err != -ENODEV);
3215 goto err_80211_unwind;
3217 /* Enable the selected wireless core.
3218 * Connect PHY only on the first core.
3220 if (!bcm43xx_core_enabled(bcm)) {
3221 if (bcm->nr_80211_available == 1) {
3222 connect_phy = bcm43xx_current_phy(bcm)->connected;
3229 bcm43xx_wireless_core_reset(bcm, connect_phy);
3233 bcm43xx_wireless_core_mark_inactive(bcm, &bcm->core_80211[0]);
3235 err = bcm43xx_wireless_core_init(bcm);
3237 goto err_80211_unwind;
3240 bcm43xx_mac_suspend(bcm);
3241 bcm43xx_interrupt_disable(bcm, BCM43xx_IRQ_ALL);
3242 bcm43xx_radio_turn_off(bcm);
3245 bcm->active_80211_core = &bcm->core_80211[0];
3246 if (bcm->nr_80211_available >= 2) {
3247 bcm43xx_switch_core(bcm, &bcm->core_80211[0]);
3248 bcm43xx_mac_enable(bcm);
3250 bcm43xx_macfilter_clear(bcm, BCM43xx_MACFILTER_ASSOC);
3251 bcm43xx_macfilter_set(bcm, BCM43xx_MACFILTER_SELF, (u8 *)(bcm->net_dev->dev_addr));
3252 dprintk(KERN_INFO PFX "80211 cores initialized\n");
3253 bcm43xx_security_init(bcm);
3254 bcm43xx_softmac_init(bcm);
3256 bcm43xx_pctl_set_clock(bcm, BCM43xx_PCTL_CLK_DYNAMIC);
3258 if (bcm43xx_current_radio(bcm)->initial_channel != 0xFF) {
3259 bcm43xx_mac_suspend(bcm);
3260 bcm43xx_radio_selectchannel(bcm, bcm43xx_current_radio(bcm)->initial_channel, 0);
3261 bcm43xx_mac_enable(bcm);
3264 /* Initialization of the board is done. Flag it as such. */
3265 bcm43xx_lock(bcm, flags);
3266 bcm->initialized = 1;
3267 bcm43xx_unlock(bcm, flags);
3269 bcm43xx_periodic_tasks_setup(bcm);
3270 bcm43xx_sysfs_register(bcm);
3271 //FIXME: check for bcm43xx_sysfs_register failure. This function is a bit messy regarding unwinding, though...
3278 tasklet_disable(&bcm->isr_tasklet);
3279 /* unwind all 80211 initialization */
3280 for (i = 0; i < bcm->nr_80211_available; i++) {
3281 if (!bcm->core_80211[i].initialized)
3283 bcm43xx_interrupt_disable(bcm, BCM43xx_IRQ_ALL);
3284 bcm43xx_wireless_core_cleanup(bcm);
3287 bcm43xx_pctl_set_crystal(bcm, 0);
3291 static void bcm43xx_detach_board(struct bcm43xx_private *bcm)
3293 struct pci_dev *pci_dev = bcm->pci_dev;
3296 bcm43xx_chipset_detach(bcm);
3297 /* Do _not_ access the chip, after it is detached. */
3298 iounmap(bcm->mmio_addr);
3300 pci_release_regions(pci_dev);
3301 pci_disable_device(pci_dev);
3303 /* Free allocated structures/fields */
3304 for (i = 0; i < BCM43xx_MAX_80211_CORES; i++) {
3305 kfree(bcm->core_80211_ext[i].phy._lo_pairs);
3306 if (bcm->core_80211_ext[i].phy.dyn_tssi_tbl)
3307 kfree(bcm->core_80211_ext[i].phy.tssi2dbm);
3311 static int bcm43xx_read_phyinfo(struct bcm43xx_private *bcm)
3313 struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
3321 value = bcm43xx_read16(bcm, BCM43xx_MMIO_PHY_VER);
3323 phy_version = (value & 0xF000) >> 12;
3324 phy_type = (value & 0x0F00) >> 8;
3325 phy_rev = (value & 0x000F);
3327 dprintk(KERN_INFO PFX "Detected PHY: Version: %x, Type %x, Revision %x\n",
3328 phy_version, phy_type, phy_rev);
3331 case BCM43xx_PHYTYPE_A:
3334 /*FIXME: We need to switch the ieee->modulation, etc.. flags,
3335 * if we switch 80211 cores after init is done.
3336 * As we do not implement on the fly switching between
3337 * wireless cores, I will leave this as a future task.
3339 bcm->ieee->modulation = IEEE80211_OFDM_MODULATION;
3340 bcm->ieee->mode = IEEE_A;
3341 bcm->ieee->freq_band = IEEE80211_52GHZ_BAND |
3342 IEEE80211_24GHZ_BAND;
3344 case BCM43xx_PHYTYPE_B:
3345 if (phy_rev != 2 && phy_rev != 4 && phy_rev != 6 && phy_rev != 7)
3347 bcm->ieee->modulation = IEEE80211_CCK_MODULATION;
3348 bcm->ieee->mode = IEEE_B;
3349 bcm->ieee->freq_band = IEEE80211_24GHZ_BAND;
3351 case BCM43xx_PHYTYPE_G:
3354 bcm->ieee->modulation = IEEE80211_OFDM_MODULATION |
3355 IEEE80211_CCK_MODULATION;
3356 bcm->ieee->mode = IEEE_G;
3357 bcm->ieee->freq_band = IEEE80211_24GHZ_BAND;
3360 printk(KERN_ERR PFX "Error: Unknown PHY Type %x\n",
3365 printk(KERN_WARNING PFX "Invalid PHY Revision %x\n",
3369 phy->version = phy_version;
3370 phy->type = phy_type;
3372 if ((phy_type == BCM43xx_PHYTYPE_B) || (phy_type == BCM43xx_PHYTYPE_G)) {
3373 p = kzalloc(sizeof(struct bcm43xx_lopair) * BCM43xx_LO_COUNT,
3383 static int bcm43xx_attach_board(struct bcm43xx_private *bcm)
3385 struct pci_dev *pci_dev = bcm->pci_dev;
3386 struct net_device *net_dev = bcm->net_dev;
3389 unsigned long mmio_start, mmio_flags, mmio_len;
3392 err = pci_enable_device(pci_dev);
3394 printk(KERN_ERR PFX "unable to wake up pci device (%i)\n", err);
3397 mmio_start = pci_resource_start(pci_dev, 0);
3398 mmio_flags = pci_resource_flags(pci_dev, 0);
3399 mmio_len = pci_resource_len(pci_dev, 0);
3400 if (!(mmio_flags & IORESOURCE_MEM)) {
3402 "%s, region #0 not an MMIO resource, aborting\n",
3405 goto err_pci_disable;
3407 err = pci_request_regions(pci_dev, KBUILD_MODNAME);
3410 "could not access PCI resources (%i)\n", err);
3411 goto err_pci_disable;
3413 /* enable PCI bus-mastering */
3414 pci_set_master(pci_dev);
3415 bcm->mmio_addr = ioremap(mmio_start, mmio_len);
3416 if (!bcm->mmio_addr) {
3417 printk(KERN_ERR PFX "%s: cannot remap MMIO, aborting\n",
3420 goto err_pci_release;
3422 bcm->mmio_len = mmio_len;
3423 net_dev->base_addr = (unsigned long)bcm->mmio_addr;
3425 bcm43xx_pci_read_config16(bcm, PCI_SUBSYSTEM_VENDOR_ID,
3426 &bcm->board_vendor);
3427 bcm43xx_pci_read_config16(bcm, PCI_SUBSYSTEM_ID,
3429 bcm43xx_pci_read_config16(bcm, PCI_REVISION_ID,
3430 &bcm->board_revision);
3432 err = bcm43xx_chipset_attach(bcm);
3435 err = bcm43xx_pctl_init(bcm);
3437 goto err_chipset_detach;
3438 err = bcm43xx_probe_cores(bcm);
3440 goto err_chipset_detach;
3442 /* Attach all IO cores to the backplane. */
3444 for (i = 0; i < bcm->nr_80211_available; i++)
3445 coremask |= (1 << bcm->core_80211[i].index);
3446 //FIXME: Also attach some non80211 cores?
3447 err = bcm43xx_setup_backplane_pci_connection(bcm, coremask);
3449 printk(KERN_ERR PFX "Backplane->PCI connection failed!\n");
3450 goto err_chipset_detach;
3453 err = bcm43xx_sprom_extract(bcm);
3455 goto err_chipset_detach;
3456 err = bcm43xx_leds_init(bcm);
3458 goto err_chipset_detach;
3460 for (i = 0; i < bcm->nr_80211_available; i++) {
3461 err = bcm43xx_switch_core(bcm, &bcm->core_80211[i]);
3462 assert(err != -ENODEV);
3464 goto err_80211_unwind;
3466 /* Enable the selected wireless core.
3467 * Connect PHY only on the first core.
3469 bcm43xx_wireless_core_reset(bcm, (i == 0));
3471 err = bcm43xx_read_phyinfo(bcm);
3472 if (err && (i == 0))
3473 goto err_80211_unwind;
3475 err = bcm43xx_read_radioinfo(bcm);
3476 if (err && (i == 0))
3477 goto err_80211_unwind;
3479 err = bcm43xx_validate_chip(bcm);
3480 if (err && (i == 0))
3481 goto err_80211_unwind;
3483 bcm43xx_radio_turn_off(bcm);
3484 err = bcm43xx_phy_init_tssi2dbm_table(bcm);
3486 goto err_80211_unwind;
3487 bcm43xx_wireless_core_disable(bcm);
3489 bcm43xx_pctl_set_crystal(bcm, 0);
3491 /* Set the MAC address in the networking subsystem */
3492 if (bcm43xx_current_phy(bcm)->type == BCM43xx_PHYTYPE_A)
3493 memcpy(bcm->net_dev->dev_addr, bcm->sprom.et1macaddr, 6);
3495 memcpy(bcm->net_dev->dev_addr, bcm->sprom.il0macaddr, 6);
3497 bcm43xx_geo_init(bcm);
3499 snprintf(bcm->nick, IW_ESSID_MAX_SIZE,
3500 "Broadcom %04X", bcm->chip_id);
3507 for (i = 0; i < BCM43xx_MAX_80211_CORES; i++) {
3508 kfree(bcm->core_80211_ext[i].phy._lo_pairs);
3509 if (bcm->core_80211_ext[i].phy.dyn_tssi_tbl)
3510 kfree(bcm->core_80211_ext[i].phy.tssi2dbm);
3513 bcm43xx_chipset_detach(bcm);
3515 iounmap(bcm->mmio_addr);
3517 pci_release_regions(pci_dev);
3519 pci_disable_device(pci_dev);
3523 /* Do the Hardware IO operations to send the txb */
3524 static inline int bcm43xx_tx(struct bcm43xx_private *bcm,
3525 struct ieee80211_txb *txb)
3529 if (bcm43xx_using_pio(bcm))
3530 err = bcm43xx_pio_tx(bcm, txb);
3532 err = bcm43xx_dma_tx(bcm, txb);
3537 static void bcm43xx_ieee80211_set_chan(struct net_device *net_dev,
3540 struct bcm43xx_private *bcm = bcm43xx_priv(net_dev);
3541 unsigned long flags;
3543 bcm43xx_lock_mmio(bcm, flags);
3544 bcm43xx_mac_suspend(bcm);
3545 bcm43xx_radio_selectchannel(bcm, channel, 0);
3546 bcm43xx_mac_enable(bcm);
3547 bcm43xx_unlock_mmio(bcm, flags);
3550 /* set_security() callback in struct ieee80211_device */
3551 static void bcm43xx_ieee80211_set_security(struct net_device *net_dev,
3552 struct ieee80211_security *sec)
3554 struct bcm43xx_private *bcm = bcm43xx_priv(net_dev);
3555 struct ieee80211_security *secinfo = &bcm->ieee->sec;
3556 unsigned long flags;
3559 dprintk(KERN_INFO PFX "set security called\n");
3561 bcm43xx_lock_mmio(bcm, flags);
3563 for (keyidx = 0; keyidx<WEP_KEYS; keyidx++)
3564 if (sec->flags & (1<<keyidx)) {
3565 secinfo->encode_alg[keyidx] = sec->encode_alg[keyidx];
3566 secinfo->key_sizes[keyidx] = sec->key_sizes[keyidx];
3567 memcpy(secinfo->keys[keyidx], sec->keys[keyidx], SCM_KEY_LEN);
3570 if (sec->flags & SEC_ACTIVE_KEY) {
3571 secinfo->active_key = sec->active_key;
3572 dprintk(KERN_INFO PFX " .active_key = %d\n", sec->active_key);
3574 if (sec->flags & SEC_UNICAST_GROUP) {
3575 secinfo->unicast_uses_group = sec->unicast_uses_group;
3576 dprintk(KERN_INFO PFX " .unicast_uses_group = %d\n", sec->unicast_uses_group);
3578 if (sec->flags & SEC_LEVEL) {
3579 secinfo->level = sec->level;
3580 dprintk(KERN_INFO PFX " .level = %d\n", sec->level);
3582 if (sec->flags & SEC_ENABLED) {
3583 secinfo->enabled = sec->enabled;
3584 dprintk(KERN_INFO PFX " .enabled = %d\n", sec->enabled);
3586 if (sec->flags & SEC_ENCRYPT) {
3587 secinfo->encrypt = sec->encrypt;
3588 dprintk(KERN_INFO PFX " .encrypt = %d\n", sec->encrypt);
3590 if (bcm->initialized && !bcm->ieee->host_encrypt) {
3591 if (secinfo->enabled) {
3592 /* upload WEP keys to hardware */
3593 char null_address[6] = { 0 };
3595 for (keyidx = 0; keyidx<WEP_KEYS; keyidx++) {
3596 if (!(sec->flags & (1<<keyidx)))
3598 switch (sec->encode_alg[keyidx]) {
3599 case SEC_ALG_NONE: algorithm = BCM43xx_SEC_ALGO_NONE; break;
3601 algorithm = BCM43xx_SEC_ALGO_WEP;
3602 if (secinfo->key_sizes[keyidx] == 13)
3603 algorithm = BCM43xx_SEC_ALGO_WEP104;
3607 algorithm = BCM43xx_SEC_ALGO_TKIP;
3611 algorithm = BCM43xx_SEC_ALGO_AES;
3617 bcm43xx_key_write(bcm, keyidx, algorithm, sec->keys[keyidx], secinfo->key_sizes[keyidx], &null_address[0]);
3618 bcm->key[keyidx].enabled = 1;
3619 bcm->key[keyidx].algorithm = algorithm;
3622 bcm43xx_clear_keys(bcm);
3624 bcm43xx_unlock_mmio(bcm, flags);
3627 /* hard_start_xmit() callback in struct ieee80211_device */
3628 static int bcm43xx_ieee80211_hard_start_xmit(struct ieee80211_txb *txb,
3629 struct net_device *net_dev,
3632 struct bcm43xx_private *bcm = bcm43xx_priv(net_dev);
3634 unsigned long flags;
3636 bcm43xx_lock_mmio(bcm, flags);
3637 if (likely(bcm->initialized))
3638 err = bcm43xx_tx(bcm, txb);
3639 bcm43xx_unlock_mmio(bcm, flags);
3644 static struct net_device_stats * bcm43xx_net_get_stats(struct net_device *net_dev)
3646 return &(bcm43xx_priv(net_dev)->ieee->stats);
3649 static void bcm43xx_net_tx_timeout(struct net_device *net_dev)
3651 struct bcm43xx_private *bcm = bcm43xx_priv(net_dev);
3652 unsigned long flags;
3654 bcm43xx_lock_mmio(bcm, flags);
3655 bcm43xx_controller_restart(bcm, "TX timeout");
3656 bcm43xx_unlock_mmio(bcm, flags);
3659 #ifdef CONFIG_NET_POLL_CONTROLLER
3660 static void bcm43xx_net_poll_controller(struct net_device *net_dev)
3662 struct bcm43xx_private *bcm = bcm43xx_priv(net_dev);
3663 unsigned long flags;
3665 local_irq_save(flags);
3666 bcm43xx_interrupt_handler(bcm->irq, bcm, NULL);
3667 local_irq_restore(flags);
3669 #endif /* CONFIG_NET_POLL_CONTROLLER */
3671 static int bcm43xx_net_open(struct net_device *net_dev)
3673 struct bcm43xx_private *bcm = bcm43xx_priv(net_dev);
3675 return bcm43xx_init_board(bcm);
3678 static int bcm43xx_net_stop(struct net_device *net_dev)
3680 struct bcm43xx_private *bcm = bcm43xx_priv(net_dev);
3682 ieee80211softmac_stop(net_dev);
3683 bcm43xx_disable_interrupts_sync(bcm, NULL);
3684 bcm43xx_free_board(bcm);
3689 static int bcm43xx_init_private(struct bcm43xx_private *bcm,
3690 struct net_device *net_dev,
3691 struct pci_dev *pci_dev)
3695 bcm->ieee = netdev_priv(net_dev);
3696 bcm->softmac = ieee80211_priv(net_dev);
3697 bcm->softmac->set_channel = bcm43xx_ieee80211_set_chan;
3699 bcm->irq_savedstate = BCM43xx_IRQ_INITIAL;
3700 bcm->pci_dev = pci_dev;
3701 bcm->net_dev = net_dev;
3702 bcm->bad_frames_preempt = modparam_bad_frames_preempt;
3703 spin_lock_init(&bcm->_lock);
3704 tasklet_init(&bcm->isr_tasklet,
3705 (void (*)(unsigned long))bcm43xx_interrupt_tasklet,
3706 (unsigned long)bcm);
3707 tasklet_disable_nosync(&bcm->isr_tasklet);
3709 bcm->__using_pio = 1;
3711 err = pci_set_dma_mask(pci_dev, DMA_30BIT_MASK);
3712 err |= pci_set_consistent_dma_mask(pci_dev, DMA_30BIT_MASK);
3714 #ifdef CONFIG_BCM43XX_PIO
3715 printk(KERN_WARNING PFX "DMA not supported. Falling back to PIO.\n");
3716 bcm->__using_pio = 1;
3718 printk(KERN_ERR PFX "FATAL: DMA not supported and PIO not configured. "
3719 "Recompile the driver with PIO support, please.\n");
3721 #endif /* CONFIG_BCM43XX_PIO */
3724 bcm->rts_threshold = BCM43xx_DEFAULT_RTS_THRESHOLD;
3726 /* default to sw encryption for now */
3727 bcm->ieee->host_build_iv = 0;
3728 bcm->ieee->host_encrypt = 1;
3729 bcm->ieee->host_decrypt = 1;
3731 bcm->ieee->iw_mode = BCM43xx_INITIAL_IWMODE;
3732 bcm->ieee->tx_headroom = sizeof(struct bcm43xx_txhdr);
3733 bcm->ieee->set_security = bcm43xx_ieee80211_set_security;
3734 bcm->ieee->hard_start_xmit = bcm43xx_ieee80211_hard_start_xmit;
3739 static int __devinit bcm43xx_init_one(struct pci_dev *pdev,
3740 const struct pci_device_id *ent)
3742 struct net_device *net_dev;
3743 struct bcm43xx_private *bcm;
3746 #ifdef CONFIG_BCM947XX
3747 if ((pdev->bus->number == 0) && (pdev->device != 0x0800))
3751 #ifdef DEBUG_SINGLE_DEVICE_ONLY
3752 if (strcmp(pci_name(pdev), DEBUG_SINGLE_DEVICE_ONLY))
3756 net_dev = alloc_ieee80211softmac(sizeof(*bcm));
3759 "could not allocate ieee80211 device %s\n",
3764 /* initialize the net_device struct */
3765 SET_MODULE_OWNER(net_dev);
3766 SET_NETDEV_DEV(net_dev, &pdev->dev);
3768 net_dev->open = bcm43xx_net_open;
3769 net_dev->stop = bcm43xx_net_stop;
3770 net_dev->get_stats = bcm43xx_net_get_stats;
3771 net_dev->tx_timeout = bcm43xx_net_tx_timeout;
3772 #ifdef CONFIG_NET_POLL_CONTROLLER
3773 net_dev->poll_controller = bcm43xx_net_poll_controller;
3775 net_dev->wireless_handlers = &bcm43xx_wx_handlers_def;
3776 net_dev->irq = pdev->irq;
3777 SET_ETHTOOL_OPS(net_dev, &bcm43xx_ethtool_ops);
3779 /* initialize the bcm43xx_private struct */
3780 bcm = bcm43xx_priv(net_dev);
3781 memset(bcm, 0, sizeof(*bcm));
3782 err = bcm43xx_init_private(bcm, net_dev, pdev);
3784 goto err_free_netdev;
3786 pci_set_drvdata(pdev, net_dev);
3788 err = bcm43xx_attach_board(bcm);
3790 goto err_free_netdev;
3792 err = register_netdev(net_dev);
3794 printk(KERN_ERR PFX "Cannot register net device, "
3797 goto err_detach_board;
3800 bcm43xx_debugfs_add_device(bcm);
3807 bcm43xx_detach_board(bcm);
3809 free_ieee80211softmac(net_dev);
3813 static void __devexit bcm43xx_remove_one(struct pci_dev *pdev)
3815 struct net_device *net_dev = pci_get_drvdata(pdev);
3816 struct bcm43xx_private *bcm = bcm43xx_priv(net_dev);
3818 bcm43xx_debugfs_remove_device(bcm);
3819 unregister_netdev(net_dev);
3820 bcm43xx_detach_board(bcm);
3821 assert(bcm->ucode == NULL);
3822 free_ieee80211softmac(net_dev);
3825 /* Hard-reset the chip. Do not call this directly.
3826 * Use bcm43xx_controller_restart()
3828 static void bcm43xx_chip_reset(void *_bcm)
3830 struct bcm43xx_private *bcm = _bcm;
3831 struct net_device *net_dev = bcm->net_dev;
3832 struct pci_dev *pci_dev = bcm->pci_dev;
3834 int was_initialized = bcm->initialized;
3836 netif_stop_queue(bcm->net_dev);
3837 tasklet_disable(&bcm->isr_tasklet);
3839 bcm->firmware_norelease = 1;
3840 if (was_initialized)
3841 bcm43xx_free_board(bcm);
3842 bcm->firmware_norelease = 0;
3843 bcm43xx_detach_board(bcm);
3844 err = bcm43xx_init_private(bcm, net_dev, pci_dev);
3847 err = bcm43xx_attach_board(bcm);
3850 if (was_initialized) {
3851 err = bcm43xx_init_board(bcm);
3855 netif_wake_queue(bcm->net_dev);
3856 printk(KERN_INFO PFX "Controller restarted\n");
3860 printk(KERN_ERR PFX "Controller restart failed\n");
3863 /* Hard-reset the chip.
3864 * This can be called from interrupt or process context.
3865 * Make sure to _not_ re-enable device interrupts after this has been called.
3867 void bcm43xx_controller_restart(struct bcm43xx_private *bcm, const char *reason)
3869 bcm43xx_interrupt_disable(bcm, BCM43xx_IRQ_ALL);
3870 bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD); /* dummy read */
3871 printk(KERN_ERR PFX "Controller RESET (%s) ...\n", reason);
3872 INIT_WORK(&bcm->restart_work, bcm43xx_chip_reset, bcm);
3873 schedule_work(&bcm->restart_work);
3878 static int bcm43xx_suspend(struct pci_dev *pdev, pm_message_t state)
3880 struct net_device *net_dev = pci_get_drvdata(pdev);
3881 struct bcm43xx_private *bcm = bcm43xx_priv(net_dev);
3882 unsigned long flags;
3883 int try_to_shutdown = 0, err;
3885 dprintk(KERN_INFO PFX "Suspending...\n");
3887 bcm43xx_lock(bcm, flags);
3888 bcm->was_initialized = bcm->initialized;
3889 if (bcm->initialized)
3890 try_to_shutdown = 1;
3891 bcm43xx_unlock(bcm, flags);
3893 netif_device_detach(net_dev);
3894 if (try_to_shutdown) {
3895 ieee80211softmac_stop(net_dev);
3896 err = bcm43xx_disable_interrupts_sync(bcm, &bcm->irq_savedstate);
3897 if (unlikely(err)) {
3898 dprintk(KERN_ERR PFX "Suspend failed.\n");
3901 bcm->firmware_norelease = 1;
3902 bcm43xx_free_board(bcm);
3903 bcm->firmware_norelease = 0;
3905 bcm43xx_chipset_detach(bcm);
3907 pci_save_state(pdev);
3908 pci_disable_device(pdev);
3909 pci_set_power_state(pdev, pci_choose_state(pdev, state));
3911 dprintk(KERN_INFO PFX "Device suspended.\n");
3916 static int bcm43xx_resume(struct pci_dev *pdev)
3918 struct net_device *net_dev = pci_get_drvdata(pdev);
3919 struct bcm43xx_private *bcm = bcm43xx_priv(net_dev);
3922 dprintk(KERN_INFO PFX "Resuming...\n");
3924 pci_set_power_state(pdev, 0);
3925 pci_enable_device(pdev);
3926 pci_restore_state(pdev);
3928 bcm43xx_chipset_attach(bcm);
3929 if (bcm->was_initialized) {
3930 bcm->irq_savedstate = BCM43xx_IRQ_INITIAL;
3931 err = bcm43xx_init_board(bcm);
3934 printk(KERN_ERR PFX "Resume failed!\n");
3938 netif_device_attach(net_dev);
3940 /*FIXME: This should be handled by softmac instead. */
3941 schedule_work(&bcm->softmac->associnfo.work);
3943 dprintk(KERN_INFO PFX "Device resumed.\n");
3948 #endif /* CONFIG_PM */
3950 static struct pci_driver bcm43xx_pci_driver = {
3951 .name = KBUILD_MODNAME,
3952 .id_table = bcm43xx_pci_tbl,
3953 .probe = bcm43xx_init_one,
3954 .remove = __devexit_p(bcm43xx_remove_one),
3956 .suspend = bcm43xx_suspend,
3957 .resume = bcm43xx_resume,
3958 #endif /* CONFIG_PM */
3961 static int __init bcm43xx_init(void)
3963 printk(KERN_INFO KBUILD_MODNAME " driver\n");
3964 bcm43xx_debugfs_init();
3965 return pci_register_driver(&bcm43xx_pci_driver);
3968 static void __exit bcm43xx_exit(void)
3970 pci_unregister_driver(&bcm43xx_pci_driver);
3971 bcm43xx_debugfs_exit();
3974 module_init(bcm43xx_init)
3975 module_exit(bcm43xx_exit)
3977 /* vim: set ts=8 sw=8 sts=8: */