drivers/net/wireless/iwlwifi/iwl-5000.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2007-2008 Intel Corporation. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17  *
  18  * The full GNU General Public License is included in this distribution in the
  19  * file called LICENSE.
  20  *
  21  * Contact Information:
  22  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  23  *
  24  *****************************************************************************/
  25
  26 #include <linux/kernel.h>
  27 #include <linux/module.h>
  28 #include <linux/init.h>
  29 #include <linux/pci.h>
  30 #include <linux/dma-mapping.h>
  31 #include <linux/delay.h>
  32 #include <linux/skbuff.h>
  33 #include <linux/netdevice.h>
  34 #include <linux/wireless.h>
  35 #include <net/mac80211.h>
  36 #include <linux/etherdevice.h>
  37 #include <asm/unaligned.h>
  38
  39 #include "iwl-eeprom.h"
  40 #include "iwl-dev.h"
  41 #include "iwl-core.h"
  42 #include "iwl-io.h"
  43 #include "iwl-sta.h"
  44 #include "iwl-helpers.h"
  45 #include "iwl-5000-hw.h"
  46
  47 #define IWL5000_UCODE_API  "-1"
  48
  49 static const u16 iwl5000_default_queue_to_tx_fifo[] = {
  50         IWL_TX_FIFO_AC3,
  51         IWL_TX_FIFO_AC2,
  52         IWL_TX_FIFO_AC1,
  53         IWL_TX_FIFO_AC0,
  54         IWL50_CMD_FIFO_NUM,
  55         IWL_TX_FIFO_HCCA_1,
  56         IWL_TX_FIFO_HCCA_2
  57 };
  58
  59 /* FIXME: same implementation as 4965 */
  60 static int iwl5000_apm_stop_master(struct iwl_priv *priv)
  61 {
  62         int ret = 0;
  63         unsigned long flags;
  64
  65         spin_lock_irqsave(&priv->lock, flags);
  66
  67         /* set stop master bit */
  68         iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
  69
  70         ret = iwl_poll_bit(priv, CSR_RESET,
  71                                   CSR_RESET_REG_FLAG_MASTER_DISABLED,
  72                                   CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
  73         if (ret < 0)
  74                 goto out;
  75
  76 out:
  77         spin_unlock_irqrestore(&priv->lock, flags);
  78         IWL_DEBUG_INFO("stop master\n");
  79
  80         return ret;
  81 }
  82
  83
  84 static int iwl5000_apm_init(struct iwl_priv *priv)
  85 {
  86         int ret = 0;
  87
  88         iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
  89                     CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
  90
  91         /* disable L0s without affecting L1 :don't wait for ICH L0s bug W/A) */
  92         iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
  93                     CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
  94
  95         /* Set FH wait treshold to maximum (HW error during stress W/A) */
  96         iwl_set_bit(priv, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
  97
  98         /* enable HAP INTA to move device L1a -> L0s */
  99         iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
 100                     CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
 101
 102         iwl_set_bit(priv, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL);
 103
 104         /* set "initialization complete" bit to move adapter
 105          * D0U* --> D0A* state */
 106         iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 107
 108         /* wait for clock stabilization */
 109         ret = iwl_poll_bit(priv, CSR_GP_CNTRL,
 110                           CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
 111                           CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
 112         if (ret < 0) {
 113                 IWL_DEBUG_INFO("Failed to init the card\n");
 114                 return ret;
 115         }
 116
 117         ret = iwl_grab_nic_access(priv);
 118         if (ret)
 119                 return ret;
 120
 121         /* enable DMA */
 122         iwl_write_prph(priv, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT);
 123
 124         udelay(20);
 125
 126         /* disable L1-Active */
 127         iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
 128                           APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
 129
 130         iwl_release_nic_access(priv);
 131
 132         return ret;
 133 }
 134
 135 /* FIXME: this is indentical to 4965 */
 136 static void iwl5000_apm_stop(struct iwl_priv *priv)
 137 {
 138         unsigned long flags;
 139
 140         iwl5000_apm_stop_master(priv);
 141
 142         spin_lock_irqsave(&priv->lock, flags);
 143
 144         iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
 145
 146         udelay(10);
 147
 148         /* clear "init complete"  move adapter D0A* --> D0U state */
 149         iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 150
 151         spin_unlock_irqrestore(&priv->lock, flags);
 152 }
 153
 154
 155 static int iwl5000_apm_reset(struct iwl_priv *priv)
 156 {
 157         int ret = 0;
 158         unsigned long flags;
 159
 160         iwl5000_apm_stop_master(priv);
 161
 162         spin_lock_irqsave(&priv->lock, flags);
 163
 164         iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
 165
 166         udelay(10);
 167
 168
 169         /* FIXME: put here L1A -L0S w/a */
 170
 171         iwl_set_bit(priv, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL);
 172
 173         /* set "initialization complete" bit to move adapter
 174          * D0U* --> D0A* state */
 175         iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 176
 177         /* wait for clock stabilization */
 178         ret = iwl_poll_bit(priv, CSR_GP_CNTRL,
 179                           CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
 180                           CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
 181         if (ret < 0) {
 182                 IWL_DEBUG_INFO("Failed to init the card\n");
 183                 goto out;
 184         }
 185
 186         ret = iwl_grab_nic_access(priv);
 187         if (ret)
 188                 goto out;
 189
 190         /* enable DMA */
 191         iwl_write_prph(priv, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT);
 192
 193         udelay(20);
 194
 195         /* disable L1-Active */
 196         iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
 197                           APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
 198
 199         iwl_release_nic_access(priv);
 200
 201 out:
 202         spin_unlock_irqrestore(&priv->lock, flags);
 203
 204         return ret;
 205 }
 206
 207
 208 static void iwl5000_nic_config(struct iwl_priv *priv)
 209 {
 210         unsigned long flags;
 211         u16 radio_cfg;
 212         u8 val_link;
 213
 214         spin_lock_irqsave(&priv->lock, flags);
 215
 216         pci_read_config_byte(priv->pci_dev, PCI_LINK_CTRL, &val_link);
 217
 218         /* L1 is enabled by BIOS */
 219         if ((val_link & PCI_LINK_VAL_L1_EN) == PCI_LINK_VAL_L1_EN)
 220                 /* diable L0S disabled L1A enabled */
 221                 iwl_set_bit(priv, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
 222         else
 223                 /* L0S enabled L1A disabled */
 224                 iwl_clear_bit(priv, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
 225
 226         radio_cfg = iwl_eeprom_query16(priv, EEPROM_RADIO_CONFIG);
 227
 228         /* write radio config values to register */
 229         if (EEPROM_RF_CFG_TYPE_MSK(radio_cfg) < EEPROM_5000_RF_CFG_TYPE_MAX)
 230                 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
 231                             EEPROM_RF_CFG_TYPE_MSK(radio_cfg) |
 232                             EEPROM_RF_CFG_STEP_MSK(radio_cfg) |
 233                             EEPROM_RF_CFG_DASH_MSK(radio_cfg));
 234
 235         /* set CSR_HW_CONFIG_REG for uCode use */
 236         iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
 237                     CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI |
 238                     CSR_HW_IF_CONFIG_REG_BIT_MAC_SI);
 239
 240         /* W/A : NIC is stuck in a reset state after Early PCIe power off
 241          * (PCIe power is lost before PERST# is asserted),
 242          * causing ME FW to lose ownership and not being able to obtain it back.
 243          */
 244         iwl_grab_nic_access(priv);
 245         iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
 246                                 APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS,
 247                                 ~APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS);
 248         iwl_release_nic_access(priv);
 249
 250         spin_unlock_irqrestore(&priv->lock, flags);
 251 }
 252
 253
 254
 255 /*
 256  * EEPROM
 257  */
 258 static u32 eeprom_indirect_address(const struct iwl_priv *priv, u32 address)
 259 {
 260         u16 offset = 0;
 261
 262         if ((address & INDIRECT_ADDRESS) == 0)
 263                 return address;
 264
 265         switch (address & INDIRECT_TYPE_MSK) {
 266         case INDIRECT_HOST:
 267                 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_HOST);
 268                 break;
 269         case INDIRECT_GENERAL:
 270                 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_GENERAL);
 271                 break;
 272         case INDIRECT_REGULATORY:
 273                 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_REGULATORY);
 274                 break;
 275         case INDIRECT_CALIBRATION:
 276                 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_CALIBRATION);
 277                 break;
 278         case INDIRECT_PROCESS_ADJST:
 279                 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_PROCESS_ADJST);
 280                 break;
 281         case INDIRECT_OTHERS:
 282                 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_OTHERS);
 283                 break;
 284         default:
 285                 IWL_ERROR("illegal indirect type: 0x%X\n",
 286                 address & INDIRECT_TYPE_MSK);
 287                 break;
 288         }
 289
 290         /* translate the offset from words to byte */
 291         return (address & ADDRESS_MSK) + (offset << 1);
 292 }
 293
 294 static int iwl5000_eeprom_check_version(struct iwl_priv *priv)
 295 {
 296         u16 eeprom_ver;
 297         struct iwl_eeprom_calib_hdr {
 298                 u8 version;
 299                 u8 pa_type;
 300                 u16 voltage;
 301         } *hdr;
 302
 303         eeprom_ver = iwl_eeprom_query16(priv, EEPROM_VERSION);
 304
 305         hdr = (struct iwl_eeprom_calib_hdr *)iwl_eeprom_query_addr(priv,
 306                                                         EEPROM_5000_CALIB_ALL);
 307
 308         if (eeprom_ver < EEPROM_5000_EEPROM_VERSION ||
 309             hdr->version < EEPROM_5000_TX_POWER_VERSION)
 310                 goto err;
 311
 312         return 0;
 313 err:
 314         IWL_ERROR("Unsuported EEPROM VER=0x%x < 0x%x CALIB=0x%x < 0x%x\n",
 315                   eeprom_ver, EEPROM_5000_EEPROM_VERSION,
 316                   hdr->version, EEPROM_5000_TX_POWER_VERSION);
 317         return -EINVAL;
 318
 319 }
 320
 321 static void iwl5000_gain_computation(struct iwl_priv *priv,
 322                 u32 average_noise[NUM_RX_CHAINS],
 323                 u16 min_average_noise_antenna_i,
 324                 u32 min_average_noise)
 325 {
 326         int i;
 327         s32 delta_g;
 328         struct iwl_chain_noise_data *data = &priv->chain_noise_data;
 329
 330         /* Find Gain Code for the antennas B and C */
 331         for (i = 1; i < NUM_RX_CHAINS; i++) {
 332                 if ((data->disconn_array[i])) {
 333                         data->delta_gain_code[i] = 0;
 334                         continue;
 335                 }
 336                 delta_g = (1000 * ((s32)average_noise[0] -
 337                         (s32)average_noise[i])) / 1500;
 338                 /* bound gain by 2 bits value max, 3rd bit is sign */
 339                 data->delta_gain_code[i] =
 340                         min(abs(delta_g), CHAIN_NOISE_MAX_DELTA_GAIN_CODE);
 341
 342                 if (delta_g < 0)
 343                         /* set negative sign */
 344                         data->delta_gain_code[i] |= (1 << 2);
 345         }
 346
 347         IWL_DEBUG_CALIB("Delta gains: ANT_B = %d  ANT_C = %d\n",
 348                         data->delta_gain_code[1], data->delta_gain_code[2]);
 349
 350         if (!data->radio_write) {
 351                 struct iwl5000_calibration_chain_noise_gain_cmd cmd;
 352                 memset(&cmd, 0, sizeof(cmd));
 353
 354                 cmd.op_code = IWL5000_PHY_CALIBRATE_CHAIN_NOISE_GAIN_CMD;
 355                 cmd.delta_gain_1 = data->delta_gain_code[1];
 356                 cmd.delta_gain_2 = data->delta_gain_code[2];
 357                 iwl_send_cmd_pdu_async(priv, REPLY_PHY_CALIBRATION_CMD,
 358                         sizeof(cmd), &cmd, NULL);
 359
 360                 data->radio_write = 1;
 361                 data->state = IWL_CHAIN_NOISE_CALIBRATED;
 362         }
 363
 364         data->chain_noise_a = 0;
 365         data->chain_noise_b = 0;
 366         data->chain_noise_c = 0;
 367         data->chain_signal_a = 0;
 368         data->chain_signal_b = 0;
 369         data->chain_signal_c = 0;
 370         data->beacon_count = 0;
 371 }
 372
 373 static void iwl5000_chain_noise_reset(struct iwl_priv *priv)
 374 {
 375         struct iwl_chain_noise_data *data = &priv->chain_noise_data;
 376
 377         if ((data->state == IWL_CHAIN_NOISE_ALIVE) && iwl_is_associated(priv)) {
 378                 struct iwl5000_calibration_chain_noise_reset_cmd cmd;
 379
 380                 memset(&cmd, 0, sizeof(cmd));
 381                 cmd.op_code = IWL5000_PHY_CALIBRATE_CHAIN_NOISE_RESET_CMD;
 382                 if (iwl_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD,
 383                         sizeof(cmd), &cmd))
 384                         IWL_ERROR("Could not send REPLY_PHY_CALIBRATION_CMD\n");
 385                 data->state = IWL_CHAIN_NOISE_ACCUMULATE;
 386                 IWL_DEBUG_CALIB("Run chain_noise_calibrate\n");
 387         }
 388 }
 389
 390 static void iwl5000_rts_tx_cmd_flag(struct ieee80211_tx_info *info,
 391                         __le32 *tx_flags)
 392 {
 393         if ((info->flags & IEEE80211_TX_CTL_USE_RTS_CTS) ||
 394             (info->flags & IEEE80211_TX_CTL_USE_CTS_PROTECT))
 395                 *tx_flags |= TX_CMD_FLG_RTS_CTS_MSK;
 396         else
 397                 *tx_flags &= ~TX_CMD_FLG_RTS_CTS_MSK;
 398 }
 399
 400 static struct iwl_sensitivity_ranges iwl5000_sensitivity = {
 401         .min_nrg_cck = 95,
 402         .max_nrg_cck = 0,
 403         .auto_corr_min_ofdm = 90,
 404         .auto_corr_min_ofdm_mrc = 170,
 405         .auto_corr_min_ofdm_x1 = 120,
 406         .auto_corr_min_ofdm_mrc_x1 = 240,
 407
 408         .auto_corr_max_ofdm = 120,
 409         .auto_corr_max_ofdm_mrc = 210,
 410         .auto_corr_max_ofdm_x1 = 155,
 411         .auto_corr_max_ofdm_mrc_x1 = 290,
 412
 413         .auto_corr_min_cck = 125,
 414         .auto_corr_max_cck = 200,
 415         .auto_corr_min_cck_mrc = 170,
 416         .auto_corr_max_cck_mrc = 400,
 417         .nrg_th_cck = 95,
 418         .nrg_th_ofdm = 95,
 419 };
 420
 421 static const u8 *iwl5000_eeprom_query_addr(const struct iwl_priv *priv,
 422                                            size_t offset)
 423 {
 424         u32 address = eeprom_indirect_address(priv, offset);
 425         BUG_ON(address >= priv->cfg->eeprom_size);
 426         return &priv->eeprom[address];
 427 }
 428
 429 /*
 430  *  Calibration
 431  */
 432 static int iwl5000_send_Xtal_calib(struct iwl_priv *priv)
 433 {
 434         u16 *xtal_calib = (u16 *)iwl_eeprom_query_addr(priv, EEPROM_5000_XTAL);
 435
 436         struct iwl5000_calibration cal_cmd = {
 437                 .op_code = IWL5000_PHY_CALIBRATE_CRYSTAL_FRQ_CMD,
 438                 .data = {
 439                         (u8)xtal_calib[0],
 440                         (u8)xtal_calib[1],
 441                 }
 442         };
 443
 444         return iwl_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD,
 445                                 sizeof(cal_cmd), &cal_cmd);
 446 }
 447
 448 static int iwl5000_send_calib_results(struct iwl_priv *priv)
 449 {
 450         int ret = 0;
 451
 452         struct iwl_host_cmd hcmd = {
 453                 .id = REPLY_PHY_CALIBRATION_CMD,
 454                 .meta.flags = CMD_SIZE_HUGE,
 455         };
 456
 457         if (priv->calib_results.lo_res) {
 458                 hcmd.len = priv->calib_results.lo_res_len;
 459                 hcmd.data = priv->calib_results.lo_res;
 460                 ret = iwl_send_cmd_sync(priv, &hcmd);
 461
 462                 if (ret)
 463                         goto err;
 464         }
 465
 466         if (priv->calib_results.tx_iq_res) {
 467                 hcmd.len = priv->calib_results.tx_iq_res_len;
 468                 hcmd.data = priv->calib_results.tx_iq_res;
 469                 ret = iwl_send_cmd_sync(priv, &hcmd);
 470
 471                 if (ret)
 472                         goto err;
 473         }
 474
 475         if (priv->calib_results.tx_iq_perd_res) {
 476                 hcmd.len = priv->calib_results.tx_iq_perd_res_len;
 477                 hcmd.data = priv->calib_results.tx_iq_perd_res;
 478                 ret = iwl_send_cmd_sync(priv, &hcmd);
 479
 480                 if (ret)
 481                         goto err;
 482         }
 483
 484         return 0;
 485 err:
 486         IWL_ERROR("Error %d\n", ret);
 487         return ret;
 488 }
 489
 490 static int iwl5000_send_calib_cfg(struct iwl_priv *priv)
 491 {
 492         struct iwl5000_calib_cfg_cmd calib_cfg_cmd;
 493         struct iwl_host_cmd cmd = {
 494                 .id = CALIBRATION_CFG_CMD,
 495                 .len = sizeof(struct iwl5000_calib_cfg_cmd),
 496                 .data = &calib_cfg_cmd,
 497         };
 498
 499         memset(&calib_cfg_cmd, 0, sizeof(calib_cfg_cmd));
 500         calib_cfg_cmd.ucd_calib_cfg.once.is_enable = IWL_CALIB_INIT_CFG_ALL;
 501         calib_cfg_cmd.ucd_calib_cfg.once.start = IWL_CALIB_INIT_CFG_ALL;
 502         calib_cfg_cmd.ucd_calib_cfg.once.send_res = IWL_CALIB_INIT_CFG_ALL;
 503         calib_cfg_cmd.ucd_calib_cfg.flags = IWL_CALIB_INIT_CFG_ALL;
 504
 505         return iwl_send_cmd(priv, &cmd);
 506 }
 507
 508 static void iwl5000_rx_calib_result(struct iwl_priv *priv,
 509                              struct iwl_rx_mem_buffer *rxb)
 510 {
 511         struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
 512         struct iwl5000_calib_hdr *hdr = (struct iwl5000_calib_hdr *)pkt->u.raw;
 513         int len = le32_to_cpu(pkt->len) & FH_RSCSR_FRAME_SIZE_MSK;
 514
 515         iwl_free_calib_results(priv);
 516
 517         /* reduce the size of the length field itself */
 518         len -= 4;
 519
 520         switch (hdr->op_code) {
 521         case IWL5000_PHY_CALIBRATE_LO_CMD:
 522                 priv->calib_results.lo_res = kzalloc(len, GFP_ATOMIC);
 523                 priv->calib_results.lo_res_len = len;
 524                 memcpy(priv->calib_results.lo_res, pkt->u.raw, len);
 525                 break;
 526         case IWL5000_PHY_CALIBRATE_TX_IQ_CMD:
 527                 priv->calib_results.tx_iq_res = kzalloc(len, GFP_ATOMIC);
 528                 priv->calib_results.tx_iq_res_len = len;
 529                 memcpy(priv->calib_results.tx_iq_res, pkt->u.raw, len);
 530                 break;
 531         case IWL5000_PHY_CALIBRATE_TX_IQ_PERD_CMD:
 532                 priv->calib_results.tx_iq_perd_res = kzalloc(len, GFP_ATOMIC);
 533                 priv->calib_results.tx_iq_perd_res_len = len;
 534                 memcpy(priv->calib_results.tx_iq_perd_res, pkt->u.raw, len);
 535                 break;
 536         default:
 537                 IWL_ERROR("Unknown calibration notification %d\n",
 538                           hdr->op_code);
 539                 return;
 540         }
 541 }
 542
 543 static void iwl5000_rx_calib_complete(struct iwl_priv *priv,
 544                                struct iwl_rx_mem_buffer *rxb)
 545 {
 546         IWL_DEBUG_INFO("Init. calibration is completed, restarting fw.\n");
 547         queue_work(priv->workqueue, &priv->restart);
 548 }
 549
 550 /*
 551  * ucode
 552  */
 553 static int iwl5000_load_section(struct iwl_priv *priv,
 554                                 struct fw_desc *image,
 555                                 u32 dst_addr)
 556 {
 557         int ret = 0;
 558         unsigned long flags;
 559
 560         dma_addr_t phy_addr = image->p_addr;
 561         u32 byte_cnt = image->len;
 562
 563         spin_lock_irqsave(&priv->lock, flags);
 564         ret = iwl_grab_nic_access(priv);
 565         if (ret) {
 566                 spin_unlock_irqrestore(&priv->lock, flags);
 567                 return ret;
 568         }
 569
 570         iwl_write_direct32(priv,
 571                 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
 572                 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
 573
 574         iwl_write_direct32(priv,
 575                 FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL), dst_addr);
 576
 577         iwl_write_direct32(priv,
 578                 FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
 579                 phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
 580
 581         iwl_write_direct32(priv,
 582                 FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
 583                 (iwl_get_dma_hi_address(phy_addr)
 584                         << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
 585
 586         iwl_write_direct32(priv,
 587                 FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
 588                 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM |
 589                 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX |
 590                 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
 591
 592         iwl_write_direct32(priv,
 593                 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
 594                 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE       |
 595                 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE_VAL |
 596                 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
 597
 598         iwl_release_nic_access(priv);
 599         spin_unlock_irqrestore(&priv->lock, flags);
 600         return 0;
 601 }
 602
 603 static int iwl5000_load_given_ucode(struct iwl_priv *priv,
 604                 struct fw_desc *inst_image,
 605                 struct fw_desc *data_image)
 606 {
 607         int ret = 0;
 608
 609         ret = iwl5000_load_section(
 610                 priv, inst_image, RTC_INST_LOWER_BOUND);
 611         if (ret)
 612                 return ret;
 613
 614         IWL_DEBUG_INFO("INST uCode section being loaded...\n");
 615         ret = wait_event_interruptible_timeout(priv->wait_command_queue,
 616                                 priv->ucode_write_complete, 5 * HZ);
 617         if (ret == -ERESTARTSYS) {
 618                 IWL_ERROR("Could not load the INST uCode section due "
 619                         "to interrupt\n");
 620                 return ret;
 621         }
 622         if (!ret) {
 623                 IWL_ERROR("Could not load the INST uCode section\n");
 624                 return -ETIMEDOUT;
 625         }
 626
 627         priv->ucode_write_complete = 0;
 628
 629         ret = iwl5000_load_section(
 630                 priv, data_image, RTC_DATA_LOWER_BOUND);
 631         if (ret)
 632                 return ret;
 633
 634         IWL_DEBUG_INFO("DATA uCode section being loaded...\n");
 635
 636         ret = wait_event_interruptible_timeout(priv->wait_command_queue,
 637                                 priv->ucode_write_complete, 5 * HZ);
 638         if (ret == -ERESTARTSYS) {
 639                 IWL_ERROR("Could not load the INST uCode section due "
 640                         "to interrupt\n");
 641                 return ret;
 642         } else if (!ret) {
 643                 IWL_ERROR("Could not load the DATA uCode section\n");
 644                 return -ETIMEDOUT;
 645         } else
 646                 ret = 0;
 647
 648         priv->ucode_write_complete = 0;
 649
 650         return ret;
 651 }
 652
 653 static int iwl5000_load_ucode(struct iwl_priv *priv)
 654 {
 655         int ret = 0;
 656
 657         /* check whether init ucode should be loaded, or rather runtime ucode */
 658         if (priv->ucode_init.len && (priv->ucode_type == UCODE_NONE)) {
 659                 IWL_DEBUG_INFO("Init ucode found. Loading init ucode...\n");
 660                 ret = iwl5000_load_given_ucode(priv,
 661                         &priv->ucode_init, &priv->ucode_init_data);
 662                 if (!ret) {
 663                         IWL_DEBUG_INFO("Init ucode load complete.\n");
 664                         priv->ucode_type = UCODE_INIT;
 665                 }
 666         } else {
 667                 IWL_DEBUG_INFO("Init ucode not found, or already loaded. "
 668                         "Loading runtime ucode...\n");
 669                 ret = iwl5000_load_given_ucode(priv,
 670                         &priv->ucode_code, &priv->ucode_data);
 671                 if (!ret) {
 672                         IWL_DEBUG_INFO("Runtime ucode load complete.\n");
 673                         priv->ucode_type = UCODE_RT;
 674                 }
 675         }
 676
 677         return ret;
 678 }
 679
 680 static void iwl5000_init_alive_start(struct iwl_priv *priv)
 681 {
 682         int ret = 0;
 683
 684         /* Check alive response for "valid" sign from uCode */
 685         if (priv->card_alive_init.is_valid != UCODE_VALID_OK) {
 686                 /* We had an error bringing up the hardware, so take it
 687                  * all the way back down so we can try again */
 688                 IWL_DEBUG_INFO("Initialize Alive failed.\n");
 689                 goto restart;
 690         }
 691
 692         /* initialize uCode was loaded... verify inst image.
 693          * This is a paranoid check, because we would not have gotten the
 694          * "initialize" alive if code weren't properly loaded.  */
 695         if (iwl_verify_ucode(priv)) {
 696                 /* Runtime instruction load was bad;
 697                  * take it all the way back down so we can try again */
 698                 IWL_DEBUG_INFO("Bad \"initialize\" uCode load.\n");
 699                 goto restart;
 700         }
 701
 702         iwl_clear_stations_table(priv);
 703         ret = priv->cfg->ops->lib->alive_notify(priv);
 704         if (ret) {
 705                 IWL_WARNING("Could not complete ALIVE transition: %d\n", ret);
 706                 goto restart;
 707         }
 708
 709         iwl5000_send_calib_cfg(priv);
 710         return;
 711
 712 restart:
 713         /* real restart (first load init_ucode) */
 714         queue_work(priv->workqueue, &priv->restart);
 715 }
 716
 717 static void iwl5000_set_wr_ptrs(struct iwl_priv *priv,
 718                                 int txq_id, u32 index)
 719 {
 720         iwl_write_direct32(priv, HBUS_TARG_WRPTR,
 721                         (index & 0xff) | (txq_id << 8));
 722         iwl_write_prph(priv, IWL50_SCD_QUEUE_RDPTR(txq_id), index);
 723 }
 724
 725 static void iwl5000_tx_queue_set_status(struct iwl_priv *priv,
 726                                         struct iwl_tx_queue *txq,
 727                                         int tx_fifo_id, int scd_retry)
 728 {
 729         int txq_id = txq->q.id;
 730         int active = test_bit(txq_id, &priv->txq_ctx_active_msk)?1:0;
 731
 732         iwl_write_prph(priv, IWL50_SCD_QUEUE_STATUS_BITS(txq_id),
 733                         (active << IWL50_SCD_QUEUE_STTS_REG_POS_ACTIVE) |
 734                         (tx_fifo_id << IWL50_SCD_QUEUE_STTS_REG_POS_TXF) |
 735                         (1 << IWL50_SCD_QUEUE_STTS_REG_POS_WSL) |
 736                         IWL50_SCD_QUEUE_STTS_REG_MSK);
 737
 738         txq->sched_retry = scd_retry;
 739
 740         IWL_DEBUG_INFO("%s %s Queue %d on AC %d\n",
 741                        active ? "Activate" : "Deactivate",
 742                        scd_retry ? "BA" : "AC", txq_id, tx_fifo_id);
 743 }
 744
 745 static int iwl5000_send_wimax_coex(struct iwl_priv *priv)
 746 {
 747         struct iwl_wimax_coex_cmd coex_cmd;
 748
 749         memset(&coex_cmd, 0, sizeof(coex_cmd));
 750
 751         return iwl_send_cmd_pdu(priv, COEX_PRIORITY_TABLE_CMD,
 752                                 sizeof(coex_cmd), &coex_cmd);
 753 }
 754
 755 static int iwl5000_alive_notify(struct iwl_priv *priv)
 756 {
 757         u32 a;
 758         int i = 0;
 759         unsigned long flags;
 760         int ret;
 761
 762         spin_lock_irqsave(&priv->lock, flags);
 763
 764         ret = iwl_grab_nic_access(priv);
 765         if (ret) {
 766                 spin_unlock_irqrestore(&priv->lock, flags);
 767                 return ret;
 768         }
 769
 770         priv->scd_base_addr = iwl_read_prph(priv, IWL50_SCD_SRAM_BASE_ADDR);
 771         a = priv->scd_base_addr + IWL50_SCD_CONTEXT_DATA_OFFSET;
 772         for (; a < priv->scd_base_addr + IWL50_SCD_TX_STTS_BITMAP_OFFSET;
 773                 a += 4)
 774                 iwl_write_targ_mem(priv, a, 0);
 775         for (; a < priv->scd_base_addr + IWL50_SCD_TRANSLATE_TBL_OFFSET;
 776                 a += 4)
 777                 iwl_write_targ_mem(priv, a, 0);
 778         for (; a < sizeof(u16) * priv->hw_params.max_txq_num; a += 4)
 779                 iwl_write_targ_mem(priv, a, 0);
 780
 781         iwl_write_prph(priv, IWL50_SCD_DRAM_BASE_ADDR,
 782                 (priv->shared_phys +
 783                  offsetof(struct iwl5000_shared, queues_byte_cnt_tbls)) >> 10);
 784         iwl_write_prph(priv, IWL50_SCD_QUEUECHAIN_SEL,
 785                 IWL50_SCD_QUEUECHAIN_SEL_ALL(
 786                         priv->hw_params.max_txq_num));
 787         iwl_write_prph(priv, IWL50_SCD_AGGR_SEL, 0);
 788
 789         /* initiate the queues */
 790         for (i = 0; i < priv->hw_params.max_txq_num; i++) {
 791                 iwl_write_prph(priv, IWL50_SCD_QUEUE_RDPTR(i), 0);
 792                 iwl_write_direct32(priv, HBUS_TARG_WRPTR, 0 | (i << 8));
 793                 iwl_write_targ_mem(priv, priv->scd_base_addr +
 794                                 IWL50_SCD_CONTEXT_QUEUE_OFFSET(i), 0);
 795                 iwl_write_targ_mem(priv, priv->scd_base_addr +
 796                                 IWL50_SCD_CONTEXT_QUEUE_OFFSET(i) +
 797                                 sizeof(u32),
 798                                 ((SCD_WIN_SIZE <<
 799                                 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
 800                                 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
 801                                 ((SCD_FRAME_LIMIT <<
 802                                 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
 803                                 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
 804         }
 805
 806         iwl_write_prph(priv, IWL50_SCD_INTERRUPT_MASK,
 807                         IWL_MASK(0, priv->hw_params.max_txq_num));
 808
 809         /* Activate all Tx DMA/FIFO channels */
 810         priv->cfg->ops->lib->txq_set_sched(priv, IWL_MASK(0, 7));
 811
 812         iwl5000_set_wr_ptrs(priv, IWL_CMD_QUEUE_NUM, 0);
 813         /* map qos queues to fifos one-to-one */
 814         for (i = 0; i < ARRAY_SIZE(iwl5000_default_queue_to_tx_fifo); i++) {
 815                 int ac = iwl5000_default_queue_to_tx_fifo[i];
 816                 iwl_txq_ctx_activate(priv, i);
 817                 iwl5000_tx_queue_set_status(priv, &priv->txq[i], ac, 0);
 818         }
 819         /* TODO - need to initialize those FIFOs inside the loop above,
 820          * not only mark them as active */
 821         iwl_txq_ctx_activate(priv, 4);
 822         iwl_txq_ctx_activate(priv, 7);
 823         iwl_txq_ctx_activate(priv, 8);
 824         iwl_txq_ctx_activate(priv, 9);
 825
 826         iwl_release_nic_access(priv);
 827         spin_unlock_irqrestore(&priv->lock, flags);
 828
 829
 830         iwl5000_send_wimax_coex(priv);
 831
 832         iwl5000_send_Xtal_calib(priv);
 833
 834         if (priv->ucode_type == UCODE_RT)
 835                 iwl5000_send_calib_results(priv);
 836
 837         return 0;
 838 }
 839
 840 static int iwl5000_hw_set_hw_params(struct iwl_priv *priv)
 841 {
 842         if ((priv->cfg->mod_params->num_of_queues > IWL50_NUM_QUEUES) ||
 843             (priv->cfg->mod_params->num_of_queues < IWL_MIN_NUM_QUEUES)) {
 844                 IWL_ERROR("invalid queues_num, should be between %d and %d\n",
 845                           IWL_MIN_NUM_QUEUES, IWL50_NUM_QUEUES);
 846                 return -EINVAL;
 847         }
 848
 849         priv->hw_params.max_txq_num = priv->cfg->mod_params->num_of_queues;
 850         priv->hw_params.first_ampdu_q = IWL50_FIRST_AMPDU_QUEUE;
 851         priv->hw_params.max_stations = IWL5000_STATION_COUNT;
 852         priv->hw_params.bcast_sta_id = IWL5000_BROADCAST_ID;
 853         priv->hw_params.max_data_size = IWL50_RTC_DATA_SIZE;
 854         priv->hw_params.max_inst_size = IWL50_RTC_INST_SIZE;
 855         priv->hw_params.max_bsm_size = 0;
 856         priv->hw_params.fat_channel =  BIT(IEEE80211_BAND_2GHZ) |
 857                                         BIT(IEEE80211_BAND_5GHZ);
 858         priv->hw_params.sens = &iwl5000_sensitivity;
 859
 860         switch (priv->hw_rev & CSR_HW_REV_TYPE_MSK) {
 861         case CSR_HW_REV_TYPE_5100:
 862         case CSR_HW_REV_TYPE_5150:
 863                 priv->hw_params.tx_chains_num = 1;
 864                 priv->hw_params.rx_chains_num = 2;
 865                 /* FIXME: move to ANT_A, ANT_B, ANT_C enum */
 866                 priv->hw_params.valid_tx_ant = ANT_A;
 867                 priv->hw_params.valid_rx_ant = ANT_AB;
 868                 break;
 869         case CSR_HW_REV_TYPE_5300:
 870         case CSR_HW_REV_TYPE_5350:
 871                 priv->hw_params.tx_chains_num = 3;
 872                 priv->hw_params.rx_chains_num = 3;
 873                 priv->hw_params.valid_tx_ant = ANT_ABC;
 874                 priv->hw_params.valid_rx_ant = ANT_ABC;
 875                 break;
 876         }
 877
 878         switch (priv->hw_rev & CSR_HW_REV_TYPE_MSK) {
 879         case CSR_HW_REV_TYPE_5100:
 880         case CSR_HW_REV_TYPE_5300:
 881                 /* 5X00 wants in Celsius */
 882                 priv->hw_params.ct_kill_threshold = CT_KILL_THRESHOLD;
 883                 break;
 884         case CSR_HW_REV_TYPE_5150:
 885         case CSR_HW_REV_TYPE_5350:
 886                 /* 5X50 wants in Kelvin */
 887                 priv->hw_params.ct_kill_threshold =
 888                                 CELSIUS_TO_KELVIN(CT_KILL_THRESHOLD);
 889                 break;
 890         }
 891
 892         return 0;
 893 }
 894
 895 static int iwl5000_alloc_shared_mem(struct iwl_priv *priv)
 896 {
 897         priv->shared_virt = pci_alloc_consistent(priv->pci_dev,
 898                                         sizeof(struct iwl5000_shared),
 899                                         &priv->shared_phys);
 900         if (!priv->shared_virt)
 901                 return -ENOMEM;
 902
 903         memset(priv->shared_virt, 0, sizeof(struct iwl5000_shared));
 904
 905         priv->rb_closed_offset = offsetof(struct iwl5000_shared, rb_closed);
 906
 907         return 0;
 908 }
 909
 910 static void iwl5000_free_shared_mem(struct iwl_priv *priv)
 911 {
 912         if (priv->shared_virt)
 913                 pci_free_consistent(priv->pci_dev,
 914                                     sizeof(struct iwl5000_shared),
 915                                     priv->shared_virt,
 916                                     priv->shared_phys);
 917 }
 918
 919 static int iwl5000_shared_mem_rx_idx(struct iwl_priv *priv)
 920 {
 921         struct iwl5000_shared *s = priv->shared_virt;
 922         return le32_to_cpu(s->rb_closed) & 0xFFF;
 923 }
 924
 925 /**
 926  * iwl5000_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array
 927  */
 928 static void iwl5000_txq_update_byte_cnt_tbl(struct iwl_priv *priv,
 929                                             struct iwl_tx_queue *txq,
 930                                             u16 byte_cnt)
 931 {
 932         struct iwl5000_shared *shared_data = priv->shared_virt;
 933         int txq_id = txq->q.id;
 934         u8 sec_ctl = 0;
 935         u8 sta = 0;
 936         int len;
 937
 938         len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE;
 939
 940         if (txq_id != IWL_CMD_QUEUE_NUM) {
 941                 sta = txq->cmd[txq->q.write_ptr]->cmd.tx.sta_id;
 942                 sec_ctl = txq->cmd[txq->q.write_ptr]->cmd.tx.sec_ctl;
 943
 944                 switch (sec_ctl & TX_CMD_SEC_MSK) {
 945                 case TX_CMD_SEC_CCM:
 946                         len += CCMP_MIC_LEN;
 947                         break;
 948                 case TX_CMD_SEC_TKIP:
 949                         len += TKIP_ICV_LEN;
 950                         break;
 951                 case TX_CMD_SEC_WEP:
 952                         len += WEP_IV_LEN + WEP_ICV_LEN;
 953                         break;
 954                 }
 955         }
 956
 957         IWL_SET_BITS16(shared_data->queues_byte_cnt_tbls[txq_id].
 958                        tfd_offset[txq->q.write_ptr], byte_cnt, len);
 959
 960         IWL_SET_BITS16(shared_data->queues_byte_cnt_tbls[txq_id].
 961                        tfd_offset[txq->q.write_ptr], sta_id, sta);
 962
 963         if (txq->q.write_ptr < IWL50_MAX_WIN_SIZE) {
 964                 IWL_SET_BITS16(shared_data->queues_byte_cnt_tbls[txq_id].
 965                         tfd_offset[IWL50_QUEUE_SIZE + txq->q.write_ptr],
 966                         byte_cnt, len);
 967                 IWL_SET_BITS16(shared_data->queues_byte_cnt_tbls[txq_id].
 968                         tfd_offset[IWL50_QUEUE_SIZE + txq->q.write_ptr],
 969                         sta_id, sta);
 970         }
 971 }
 972
 973 static void iwl5000_txq_inval_byte_cnt_tbl(struct iwl_priv *priv,
 974                                            struct iwl_tx_queue *txq)
 975 {
 976         int txq_id = txq->q.id;
 977         struct iwl5000_shared *shared_data = priv->shared_virt;
 978         u8 sta = 0;
 979
 980         if (txq_id != IWL_CMD_QUEUE_NUM)
 981                 sta = txq->cmd[txq->q.read_ptr]->cmd.tx.sta_id;
 982
 983         shared_data->queues_byte_cnt_tbls[txq_id].tfd_offset[txq->q.read_ptr].
 984                                         val = cpu_to_le16(1 | (sta << 12));
 985
 986         if (txq->q.write_ptr < IWL50_MAX_WIN_SIZE) {
 987                 shared_data->queues_byte_cnt_tbls[txq_id].
 988                         tfd_offset[IWL50_QUEUE_SIZE + txq->q.read_ptr].
 989                                 val = cpu_to_le16(1 | (sta << 12));
 990         }
 991 }
 992
 993 static int iwl5000_tx_queue_set_q2ratid(struct iwl_priv *priv, u16 ra_tid,
 994                                         u16 txq_id)
 995 {
 996         u32 tbl_dw_addr;
 997         u32 tbl_dw;
 998         u16 scd_q2ratid;
 999
1000         scd_q2ratid = ra_tid & IWL_SCD_QUEUE_RA_TID_MAP_RATID_MSK;
1001
1002         tbl_dw_addr = priv->scd_base_addr +
1003                         IWL50_SCD_TRANSLATE_TBL_OFFSET_QUEUE(txq_id);
1004
1005         tbl_dw = iwl_read_targ_mem(priv, tbl_dw_addr);
1006
1007         if (txq_id & 0x1)
1008                 tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
1009         else
1010                 tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);
1011
1012         iwl_write_targ_mem(priv, tbl_dw_addr, tbl_dw);
1013
1014         return 0;
1015 }
1016 static void iwl5000_tx_queue_stop_scheduler(struct iwl_priv *priv, u16 txq_id)
1017 {
1018         /* Simply stop the queue, but don't change any configuration;
1019          * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */
1020         iwl_write_prph(priv,
1021                 IWL50_SCD_QUEUE_STATUS_BITS(txq_id),
1022                 (0 << IWL50_SCD_QUEUE_STTS_REG_POS_ACTIVE)|
1023                 (1 << IWL50_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN));
1024 }
1025
1026 static int iwl5000_txq_agg_enable(struct iwl_priv *priv, int txq_id,
1027                                   int tx_fifo, int sta_id, int tid, u16 ssn_idx)
1028 {
1029         unsigned long flags;
1030         int ret;
1031         u16 ra_tid;
1032
1033         if ((IWL50_FIRST_AMPDU_QUEUE > txq_id) ||
1034             (IWL50_FIRST_AMPDU_QUEUE + IWL50_NUM_AMPDU_QUEUES <= txq_id)) {
1035                 IWL_WARNING("queue number out of range: %d, must be %d to %d\n",
1036                         txq_id, IWL50_FIRST_AMPDU_QUEUE,
1037                         IWL50_FIRST_AMPDU_QUEUE + IWL50_NUM_AMPDU_QUEUES - 1);
1038                 return -EINVAL;
1039         }
1040
1041         ra_tid = BUILD_RAxTID(sta_id, tid);
1042
1043         /* Modify device's station table to Tx this TID */
1044         iwl_sta_modify_enable_tid_tx(priv, sta_id, tid);
1045
1046         spin_lock_irqsave(&priv->lock, flags);
1047         ret = iwl_grab_nic_access(priv);
1048         if (ret) {
1049                 spin_unlock_irqrestore(&priv->lock, flags);
1050                 return ret;
1051         }
1052
1053         /* Stop this Tx queue before configuring it */
1054         iwl5000_tx_queue_stop_scheduler(priv, txq_id);
1055
1056         /* Map receiver-address / traffic-ID to this queue */
1057         iwl5000_tx_queue_set_q2ratid(priv, ra_tid, txq_id);
1058
1059         /* Set this queue as a chain-building queue */
1060         iwl_set_bits_prph(priv, IWL50_SCD_QUEUECHAIN_SEL, (1<<txq_id));
1061
1062         /* enable aggregations for the queue */
1063         iwl_set_bits_prph(priv, IWL50_SCD_AGGR_SEL, (1<<txq_id));
1064
1065         /* Place first TFD at index corresponding to start sequence number.
1066          * Assumes that ssn_idx is valid (!= 0xFFF) */
1067         priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
1068         priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
1069         iwl5000_set_wr_ptrs(priv, txq_id, ssn_idx);
1070
1071         /* Set up Tx window size and frame limit for this queue */
1072         iwl_write_targ_mem(priv, priv->scd_base_addr +
1073                         IWL50_SCD_CONTEXT_QUEUE_OFFSET(txq_id) +
1074                         sizeof(u32),
1075                         ((SCD_WIN_SIZE <<
1076                         IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
1077                         IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
1078                         ((SCD_FRAME_LIMIT <<
1079                         IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
1080                         IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
1081
1082         iwl_set_bits_prph(priv, IWL50_SCD_INTERRUPT_MASK, (1 << txq_id));
1083
1084         /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */
1085         iwl5000_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 1);
1086
1087         iwl_release_nic_access(priv);
1088         spin_unlock_irqrestore(&priv->lock, flags);
1089
1090         return 0;
1091 }
1092
1093 static int iwl5000_txq_agg_disable(struct iwl_priv *priv, u16 txq_id,
1094                                    u16 ssn_idx, u8 tx_fifo)
1095 {
1096         int ret;
1097
1098         if ((IWL50_FIRST_AMPDU_QUEUE > txq_id) ||
1099             (IWL50_FIRST_AMPDU_QUEUE + IWL50_NUM_AMPDU_QUEUES <= txq_id)) {
1100                 IWL_WARNING("queue number out of range: %d, must be %d to %d\n",
1101                         txq_id, IWL50_FIRST_AMPDU_QUEUE,
1102                         IWL50_FIRST_AMPDU_QUEUE + IWL50_NUM_AMPDU_QUEUES - 1);
1103                 return -EINVAL;
1104         }
1105
1106         ret = iwl_grab_nic_access(priv);
1107         if (ret)
1108                 return ret;
1109
1110         iwl5000_tx_queue_stop_scheduler(priv, txq_id);
1111
1112         iwl_clear_bits_prph(priv, IWL50_SCD_AGGR_SEL, (1 << txq_id));
1113
1114         priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
1115         priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
1116         /* supposes that ssn_idx is valid (!= 0xFFF) */
1117         iwl5000_set_wr_ptrs(priv, txq_id, ssn_idx);
1118
1119         iwl_clear_bits_prph(priv, IWL50_SCD_INTERRUPT_MASK, (1 << txq_id));
1120         iwl_txq_ctx_deactivate(priv, txq_id);
1121         iwl5000_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 0);
1122
1123         iwl_release_nic_access(priv);
1124
1125         return 0;
1126 }
1127
1128 static u16 iwl5000_build_addsta_hcmd(const struct iwl_addsta_cmd *cmd, u8 *data)
1129 {
1130         u16 size = (u16)sizeof(struct iwl_addsta_cmd);
1131         memcpy(data, cmd, size);
1132         return size;
1133 }
1134
1135
1136 /*
1137  * Activate/Deactivat Tx DMA/FIFO channels according tx fifos mask
1138  * must be called under priv->lock and mac access
1139  */
1140 static void iwl5000_txq_set_sched(struct iwl_priv *priv, u32 mask)
1141 {
1142         iwl_write_prph(priv, IWL50_SCD_TXFACT, mask);
1143 }
1144
1145
1146 static inline u32 iwl5000_get_scd_ssn(struct iwl5000_tx_resp *tx_resp)
1147 {
1148         return le32_to_cpup((__le32 *)&tx_resp->status +
1149                             tx_resp->frame_count) & MAX_SN;
1150 }
1151
1152 static int iwl5000_tx_status_reply_tx(struct iwl_priv *priv,
1153                                       struct iwl_ht_agg *agg,
1154                                       struct iwl5000_tx_resp *tx_resp,
1155                                       int txq_id, u16 start_idx)
1156 {
1157         u16 status;
1158         struct agg_tx_status *frame_status = &tx_resp->status;
1159         struct ieee80211_tx_info *info = NULL;
1160         struct ieee80211_hdr *hdr = NULL;
1161         u32 rate_n_flags = le32_to_cpu(tx_resp->rate_n_flags);
1162         int i, sh, idx;
1163         u16 seq;
1164
1165         if (agg->wait_for_ba)
1166                 IWL_DEBUG_TX_REPLY("got tx response w/o block-ack\n");
1167
1168         agg->frame_count = tx_resp->frame_count;
1169         agg->start_idx = start_idx;
1170         agg->rate_n_flags = rate_n_flags;
1171         agg->bitmap = 0;
1172
1173         /* # frames attempted by Tx command */
1174         if (agg->frame_count == 1) {
1175                 /* Only one frame was attempted; no block-ack will arrive */
1176                 status = le16_to_cpu(frame_status[0].status);
1177                 idx = start_idx;
1178
1179                 /* FIXME: code repetition */
1180                 IWL_DEBUG_TX_REPLY("FrameCnt = %d, StartIdx=%d idx=%d\n",
1181                                    agg->frame_count, agg->start_idx, idx);
1182
1183                 info = IEEE80211_SKB_CB(priv->txq[txq_id].txb[idx].skb[0]);
1184                 info->status.retry_count = tx_resp->failure_frame;
1185                 info->flags &= ~IEEE80211_TX_CTL_AMPDU;
1186                 info->flags |= iwl_is_tx_success(status)?
1187                         IEEE80211_TX_STAT_ACK : 0;
1188                 iwl_hwrate_to_tx_control(priv, rate_n_flags, info);
1189
1190                 /* FIXME: code repetition end */
1191
1192                 IWL_DEBUG_TX_REPLY("1 Frame 0x%x failure :%d\n",
1193                                     status & 0xff, tx_resp->failure_frame);
1194                 IWL_DEBUG_TX_REPLY("Rate Info rate_n_flags=%x\n", rate_n_flags);
1195
1196                 agg->wait_for_ba = 0;
1197         } else {
1198                 /* Two or more frames were attempted; expect block-ack */
1199                 u64 bitmap = 0;
1200                 int start = agg->start_idx;
1201
1202                 /* Construct bit-map of pending frames within Tx window */
1203                 for (i = 0; i < agg->frame_count; i++) {
1204                         u16 sc;
1205                         status = le16_to_cpu(frame_status[i].status);
1206                         seq  = le16_to_cpu(frame_status[i].sequence);
1207                         idx = SEQ_TO_INDEX(seq);
1208                         txq_id = SEQ_TO_QUEUE(seq);
1209
1210                         if (status & (AGG_TX_STATE_FEW_BYTES_MSK |
1211                                       AGG_TX_STATE_ABORT_MSK))
1212                                 continue;
1213
1214                         IWL_DEBUG_TX_REPLY("FrameCnt = %d, txq_id=%d idx=%d\n",
1215                                            agg->frame_count, txq_id, idx);
1216
1217                         hdr = iwl_tx_queue_get_hdr(priv, txq_id, idx);
1218
1219                         sc = le16_to_cpu(hdr->seq_ctrl);
1220                         if (idx != (SEQ_TO_SN(sc) & 0xff)) {
1221                                 IWL_ERROR("BUG_ON idx doesn't match seq control"
1222                                           " idx=%d, seq_idx=%d, seq=%d\n",
1223                                           idx, SEQ_TO_SN(sc),
1224                                           hdr->seq_ctrl);
1225                                 return -1;
1226                         }
1227
1228                         IWL_DEBUG_TX_REPLY("AGG Frame i=%d idx %d seq=%d\n",
1229                                            i, idx, SEQ_TO_SN(sc));
1230
1231                         sh = idx - start;
1232                         if (sh > 64) {
1233                                 sh = (start - idx) + 0xff;
1234                                 bitmap = bitmap << sh;
1235                                 sh = 0;
1236                                 start = idx;
1237                         } else if (sh < -64)
1238                                 sh  = 0xff - (start - idx);
1239                         else if (sh < 0) {
1240                                 sh = start - idx;
1241                                 start = idx;
1242                                 bitmap = bitmap << sh;
1243                                 sh = 0;
1244                         }
1245                         bitmap |= 1ULL << sh;
1246                         IWL_DEBUG_TX_REPLY("start=%d bitmap=0x%llx\n",
1247                                            start, (unsigned long long)bitmap);
1248                 }
1249
1250                 agg->bitmap = bitmap;
1251                 agg->start_idx = start;
1252                 IWL_DEBUG_TX_REPLY("Frames %d start_idx=%d bitmap=0x%llx\n",
1253                                    agg->frame_count, agg->start_idx,
1254                                    (unsigned long long)agg->bitmap);
1255
1256                 if (bitmap)
1257                         agg->wait_for_ba = 1;
1258         }
1259         return 0;
1260 }
1261
1262 static void iwl5000_rx_reply_tx(struct iwl_priv *priv,
1263                                 struct iwl_rx_mem_buffer *rxb)
1264 {
1265         struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
1266         u16 sequence = le16_to_cpu(pkt->hdr.sequence);
1267         int txq_id = SEQ_TO_QUEUE(sequence);
1268         int index = SEQ_TO_INDEX(sequence);
1269         struct iwl_tx_queue *txq = &priv->txq[txq_id];
1270         struct ieee80211_tx_info *info;
1271         struct iwl5000_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
1272         u32  status = le16_to_cpu(tx_resp->status.status);
1273         int tid = MAX_TID_COUNT, sta_id = IWL_INVALID_STATION;
1274         struct ieee80211_hdr *hdr;
1275         u8 *qc = NULL;
1276
1277         if ((index >= txq->q.n_bd) || (iwl_queue_used(&txq->q, index) == 0)) {
1278                 IWL_ERROR("Read index for DMA queue txq_id (%d) index %d "
1279                           "is out of range [0-%d] %d %d\n", txq_id,
1280                           index, txq->q.n_bd, txq->q.write_ptr,
1281                           txq->q.read_ptr);
1282                 return;
1283         }
1284
1285         info = IEEE80211_SKB_CB(txq->txb[txq->q.read_ptr].skb[0]);
1286         memset(&info->status, 0, sizeof(info->status));
1287
1288         hdr = iwl_tx_queue_get_hdr(priv, txq_id, index);
1289         if (ieee80211_is_data_qos(hdr->frame_control)) {
1290                 qc = ieee80211_get_qos_ctl(hdr);
1291                 tid = qc[0] & 0xf;
1292         }
1293
1294         sta_id = iwl_get_ra_sta_id(priv, hdr);
1295         if (txq->sched_retry && unlikely(sta_id == IWL_INVALID_STATION)) {
1296                 IWL_ERROR("Station not known\n");
1297                 return;
1298         }
1299
1300         if (txq->sched_retry) {
1301                 const u32 scd_ssn = iwl5000_get_scd_ssn(tx_resp);
1302                 struct iwl_ht_agg *agg = NULL;
1303
1304                 if (!qc)
1305                         return;
1306
1307                 agg = &priv->stations[sta_id].tid[tid].agg;
1308
1309                 iwl5000_tx_status_reply_tx(priv, agg, tx_resp, txq_id, index);
1310
1311                 /* check if BAR is needed */
1312                 if ((tx_resp->frame_count == 1) && !iwl_is_tx_success(status))
1313                         info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK;
1314
1315                 if (txq->q.read_ptr != (scd_ssn & 0xff)) {
1316                         int freed, ampdu_q;
1317                         index = iwl_queue_dec_wrap(scd_ssn & 0xff, txq->q.n_bd);
1318                         IWL_DEBUG_TX_REPLY("Retry scheduler reclaim scd_ssn "
1319                                            "%d index %d\n", scd_ssn , index);
1320                         freed = iwl_tx_queue_reclaim(priv, txq_id, index);
1321                         priv->stations[sta_id].tid[tid].tfds_in_queue -= freed;
1322
1323                         if (iwl_queue_space(&txq->q) > txq->q.low_mark &&
1324                             txq_id >= 0 && priv->mac80211_registered &&
1325                             agg->state != IWL_EMPTYING_HW_QUEUE_DELBA) {
1326                                 /* calculate mac80211 ampdu sw queue to wake */
1327                                 ampdu_q = txq_id - IWL50_FIRST_AMPDU_QUEUE +
1328                                           priv->hw->queues;
1329                                 if (agg->state == IWL_AGG_OFF)
1330                                         ieee80211_wake_queue(priv->hw, txq_id);
1331                                 else
1332                                         ieee80211_wake_queue(priv->hw, ampdu_q);
1333                         }
1334                         iwl_txq_check_empty(priv, sta_id, tid, txq_id);
1335                 }
1336         } else {
1337                 info->status.retry_count = tx_resp->failure_frame;
1338                 info->flags =
1339                         iwl_is_tx_success(status) ? IEEE80211_TX_STAT_ACK : 0;
1340                 iwl_hwrate_to_tx_control(priv,
1341                                         le32_to_cpu(tx_resp->rate_n_flags),
1342                                         info);
1343
1344                 IWL_DEBUG_TX("Tx queue %d Status %s (0x%08x) rate_n_flags "
1345                              "0x%x retries %d\n", txq_id,
1346                                 iwl_get_tx_fail_reason(status),
1347                                 status, le32_to_cpu(tx_resp->rate_n_flags),
1348                                 tx_resp->failure_frame);
1349
1350                 IWL_DEBUG_TX_REPLY("Tx queue reclaim %d\n", index);
1351                 if (index != -1) {
1352                     int freed = iwl_tx_queue_reclaim(priv, txq_id, index);
1353                     if (tid != MAX_TID_COUNT)
1354                         priv->stations[sta_id].tid[tid].tfds_in_queue -= freed;
1355                     if (iwl_queue_space(&txq->q) > txq->q.low_mark &&
1356                         (txq_id >= 0) && priv->mac80211_registered)
1357                         ieee80211_wake_queue(priv->hw, txq_id);
1358                     if (tid != MAX_TID_COUNT)
1359                         iwl_txq_check_empty(priv, sta_id, tid, txq_id);
1360                 }
1361         }
1362
1363         if (iwl_check_bits(status, TX_ABORT_REQUIRED_MSK))
1364                 IWL_ERROR("TODO:  Implement Tx ABORT REQUIRED!!!\n");
1365 }
1366
1367 /* Currently 5000 is the supperset of everything */
1368 static u16 iwl5000_get_hcmd_size(u8 cmd_id, u16 len)
1369 {
1370         return len;
1371 }
1372
1373 static void iwl5000_setup_deferred_work(struct iwl_priv *priv)
1374 {
1375         /* in 5000 the tx power calibration is done in uCode */
1376         priv->disable_tx_power_cal = 1;
1377 }
1378
1379 static void iwl5000_rx_handler_setup(struct iwl_priv *priv)
1380 {
1381         /* init calibration handlers */
1382         priv->rx_handlers[CALIBRATION_RES_NOTIFICATION] =
1383                                         iwl5000_rx_calib_result;
1384         priv->rx_handlers[CALIBRATION_COMPLETE_NOTIFICATION] =
1385                                         iwl5000_rx_calib_complete;
1386         priv->rx_handlers[REPLY_TX] = iwl5000_rx_reply_tx;
1387 }
1388
1389
1390 static int iwl5000_hw_valid_rtc_data_addr(u32 addr)
1391 {
1392         return (addr >= RTC_DATA_LOWER_BOUND) &&
1393                 (addr < IWL50_RTC_DATA_UPPER_BOUND);
1394 }
1395
1396 static int iwl5000_send_rxon_assoc(struct iwl_priv *priv)
1397 {
1398         int ret = 0;
1399         struct iwl5000_rxon_assoc_cmd rxon_assoc;
1400         const struct iwl_rxon_cmd *rxon1 = &priv->staging_rxon;
1401         const struct iwl_rxon_cmd *rxon2 = &priv->active_rxon;
1402
1403         if ((rxon1->flags == rxon2->flags) &&
1404             (rxon1->filter_flags == rxon2->filter_flags) &&
1405             (rxon1->cck_basic_rates == rxon2->cck_basic_rates) &&
1406             (rxon1->ofdm_ht_single_stream_basic_rates ==
1407              rxon2->ofdm_ht_single_stream_basic_rates) &&
1408             (rxon1->ofdm_ht_dual_stream_basic_rates ==
1409              rxon2->ofdm_ht_dual_stream_basic_rates) &&
1410             (rxon1->ofdm_ht_triple_stream_basic_rates ==
1411              rxon2->ofdm_ht_triple_stream_basic_rates) &&
1412             (rxon1->acquisition_data == rxon2->acquisition_data) &&
1413             (rxon1->rx_chain == rxon2->rx_chain) &&
1414             (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) {
1415                 IWL_DEBUG_INFO("Using current RXON_ASSOC.  Not resending.\n");
1416                 return 0;
1417         }
1418
1419         rxon_assoc.flags = priv->staging_rxon.flags;
1420         rxon_assoc.filter_flags = priv->staging_rxon.filter_flags;
1421         rxon_assoc.ofdm_basic_rates = priv->staging_rxon.ofdm_basic_rates;
1422         rxon_assoc.cck_basic_rates = priv->staging_rxon.cck_basic_rates;
1423         rxon_assoc.reserved1 = 0;
1424         rxon_assoc.reserved2 = 0;
1425         rxon_assoc.reserved3 = 0;
1426         rxon_assoc.ofdm_ht_single_stream_basic_rates =
1427             priv->staging_rxon.ofdm_ht_single_stream_basic_rates;
1428         rxon_assoc.ofdm_ht_dual_stream_basic_rates =
1429             priv->staging_rxon.ofdm_ht_dual_stream_basic_rates;
1430         rxon_assoc.rx_chain_select_flags = priv->staging_rxon.rx_chain;
1431         rxon_assoc.ofdm_ht_triple_stream_basic_rates =
1432                  priv->staging_rxon.ofdm_ht_triple_stream_basic_rates;
1433         rxon_assoc.acquisition_data = priv->staging_rxon.acquisition_data;
1434
1435         ret = iwl_send_cmd_pdu_async(priv, REPLY_RXON_ASSOC,
1436                                      sizeof(rxon_assoc), &rxon_assoc, NULL);
1437         if (ret)
1438                 return ret;
1439
1440         return ret;
1441 }
1442 static int  iwl5000_send_tx_power(struct iwl_priv *priv)
1443 {
1444         struct iwl5000_tx_power_dbm_cmd tx_power_cmd;
1445
1446         /* half dBm need to multiply */
1447         tx_power_cmd.global_lmt = (s8)(2 * priv->tx_power_user_lmt);
1448         tx_power_cmd.flags = IWL50_TX_POWER_NO_CLOSED;
1449         tx_power_cmd.srv_chan_lmt = IWL50_TX_POWER_AUTO;
1450         return  iwl_send_cmd_pdu_async(priv, REPLY_TX_POWER_DBM_CMD,
1451                                        sizeof(tx_power_cmd), &tx_power_cmd,
1452                                        NULL);
1453 }
1454
1455 static void iwl5000_temperature(struct iwl_priv *priv)
1456 {
1457         /* store temperature from statistics (in Celsius) */
1458         priv->temperature = le32_to_cpu(priv->statistics.general.temperature);
1459 }
1460
1461 /* Calc max signal level (dBm) among 3 possible receivers */
1462 static int iwl5000_calc_rssi(struct iwl_priv *priv,
1463                              struct iwl_rx_phy_res *rx_resp)
1464 {
1465         /* data from PHY/DSP regarding signal strength, etc.,
1466          *   contents are always there, not configurable by host
1467          */
1468         struct iwl5000_non_cfg_phy *ncphy =
1469                 (struct iwl5000_non_cfg_phy *)rx_resp->non_cfg_phy_buf;
1470         u32 val, rssi_a, rssi_b, rssi_c, max_rssi;
1471         u8 agc;
1472
1473         val  = le32_to_cpu(ncphy->non_cfg_phy[IWL50_RX_RES_AGC_IDX]);
1474         agc = (val & IWL50_OFDM_AGC_MSK) >> IWL50_OFDM_AGC_BIT_POS;
1475
1476         /* Find max rssi among 3 possible receivers.
1477          * These values are measured by the digital signal processor (DSP).
1478          * They should stay fairly constant even as the signal strength varies,
1479          *   if the radio's automatic gain control (AGC) is working right.
1480          * AGC value (see below) will provide the "interesting" info.
1481          */
1482         val = le32_to_cpu(ncphy->non_cfg_phy[IWL50_RX_RES_RSSI_AB_IDX]);
1483         rssi_a = (val & IWL50_OFDM_RSSI_A_MSK) >> IWL50_OFDM_RSSI_A_BIT_POS;
1484         rssi_b = (val & IWL50_OFDM_RSSI_B_MSK) >> IWL50_OFDM_RSSI_B_BIT_POS;
1485         val = le32_to_cpu(ncphy->non_cfg_phy[IWL50_RX_RES_RSSI_C_IDX]);
1486         rssi_c = (val & IWL50_OFDM_RSSI_C_MSK) >> IWL50_OFDM_RSSI_C_BIT_POS;
1487
1488         max_rssi = max_t(u32, rssi_a, rssi_b);
1489         max_rssi = max_t(u32, max_rssi, rssi_c);
1490
1491         IWL_DEBUG_STATS("Rssi In A %d B %d C %d Max %d AGC dB %d\n",
1492                 rssi_a, rssi_b, rssi_c, max_rssi, agc);
1493
1494         /* dBm = max_rssi dB - agc dB - constant.
1495          * Higher AGC (higher radio gain) means lower signal. */
1496         return max_rssi - agc - IWL_RSSI_OFFSET;
1497 }
1498
1499 static struct iwl_hcmd_ops iwl5000_hcmd = {
1500         .rxon_assoc = iwl5000_send_rxon_assoc,
1501 };
1502
1503 static struct iwl_hcmd_utils_ops iwl5000_hcmd_utils = {
1504         .get_hcmd_size = iwl5000_get_hcmd_size,
1505         .build_addsta_hcmd = iwl5000_build_addsta_hcmd,
1506         .gain_computation = iwl5000_gain_computation,
1507         .chain_noise_reset = iwl5000_chain_noise_reset,
1508         .rts_tx_cmd_flag = iwl5000_rts_tx_cmd_flag,
1509         .calc_rssi = iwl5000_calc_rssi,
1510 };
1511
1512 static struct iwl_lib_ops iwl5000_lib = {
1513         .set_hw_params = iwl5000_hw_set_hw_params,
1514         .alloc_shared_mem = iwl5000_alloc_shared_mem,
1515         .free_shared_mem = iwl5000_free_shared_mem,
1516         .shared_mem_rx_idx = iwl5000_shared_mem_rx_idx,
1517         .txq_update_byte_cnt_tbl = iwl5000_txq_update_byte_cnt_tbl,
1518         .txq_inval_byte_cnt_tbl = iwl5000_txq_inval_byte_cnt_tbl,
1519         .txq_set_sched = iwl5000_txq_set_sched,
1520         .txq_agg_enable = iwl5000_txq_agg_enable,
1521         .txq_agg_disable = iwl5000_txq_agg_disable,
1522         .rx_handler_setup = iwl5000_rx_handler_setup,
1523         .setup_deferred_work = iwl5000_setup_deferred_work,
1524         .is_valid_rtc_data_addr = iwl5000_hw_valid_rtc_data_addr,
1525         .load_ucode = iwl5000_load_ucode,
1526         .init_alive_start = iwl5000_init_alive_start,
1527         .alive_notify = iwl5000_alive_notify,
1528         .send_tx_power = iwl5000_send_tx_power,
1529         .temperature = iwl5000_temperature,
1530         .update_chain_flags = iwl4965_update_chain_flags,
1531         .apm_ops = {
1532                 .init = iwl5000_apm_init,
1533                 .reset = iwl5000_apm_reset,
1534                 .stop = iwl5000_apm_stop,
1535                 .config = iwl5000_nic_config,
1536                 .set_pwr_src = iwl4965_set_pwr_src,
1537         },
1538         .eeprom_ops = {
1539                 .regulatory_bands = {
1540                         EEPROM_5000_REG_BAND_1_CHANNELS,
1541                         EEPROM_5000_REG_BAND_2_CHANNELS,
1542                         EEPROM_5000_REG_BAND_3_CHANNELS,
1543                         EEPROM_5000_REG_BAND_4_CHANNELS,
1544                         EEPROM_5000_REG_BAND_5_CHANNELS,
1545                         EEPROM_5000_REG_BAND_24_FAT_CHANNELS,
1546                         EEPROM_5000_REG_BAND_52_FAT_CHANNELS
1547                 },
1548                 .verify_signature  = iwlcore_eeprom_verify_signature,
1549                 .acquire_semaphore = iwlcore_eeprom_acquire_semaphore,
1550                 .release_semaphore = iwlcore_eeprom_release_semaphore,
1551                 .check_version  = iwl5000_eeprom_check_version,
1552                 .query_addr = iwl5000_eeprom_query_addr,
1553         },
1554 };
1555
1556 static struct iwl_ops iwl5000_ops = {
1557         .lib = &iwl5000_lib,
1558         .hcmd = &iwl5000_hcmd,
1559         .utils = &iwl5000_hcmd_utils,
1560 };
1561
1562 static struct iwl_mod_params iwl50_mod_params = {
1563         .num_of_queues = IWL50_NUM_QUEUES,
1564         .num_of_ampdu_queues = IWL50_NUM_AMPDU_QUEUES,
1565         .enable_qos = 1,
1566         .amsdu_size_8K = 1,
1567         .restart_fw = 1,
1568         /* the rest are 0 by default */
1569 };
1570
1571
1572 struct iwl_cfg iwl5300_agn_cfg = {
1573         .name = "5300AGN",
1574         .fw_name = "iwlwifi-5000" IWL5000_UCODE_API ".ucode",
1575         .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
1576         .ops = &iwl5000_ops,
1577         .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1578         .mod_params = &iwl50_mod_params,
1579 };
1580
1581 struct iwl_cfg iwl5100_bg_cfg = {
1582         .name = "5100BG",
1583         .fw_name = "iwlwifi-5000" IWL5000_UCODE_API ".ucode",
1584         .sku = IWL_SKU_G,
1585         .ops = &iwl5000_ops,
1586         .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1587         .mod_params = &iwl50_mod_params,
1588 };
1589
1590 struct iwl_cfg iwl5100_abg_cfg = {
1591         .name = "5100ABG",
1592         .fw_name = "iwlwifi-5000" IWL5000_UCODE_API ".ucode",
1593         .sku = IWL_SKU_A|IWL_SKU_G,
1594         .ops = &iwl5000_ops,
1595         .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1596         .mod_params = &iwl50_mod_params,
1597 };
1598
1599 struct iwl_cfg iwl5100_agn_cfg = {
1600         .name = "5100AGN",
1601         .fw_name = "iwlwifi-5000" IWL5000_UCODE_API ".ucode",
1602         .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
1603         .ops = &iwl5000_ops,
1604         .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1605         .mod_params = &iwl50_mod_params,
1606 };
1607
1608 struct iwl_cfg iwl5350_agn_cfg = {
1609         .name = "5350AGN",
1610         .fw_name = "iwlwifi-5000" IWL5000_UCODE_API ".ucode",
1611         .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
1612         .ops = &iwl5000_ops,
1613         .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1614         .mod_params = &iwl50_mod_params,
1615 };
1616
1617 module_param_named(disable50, iwl50_mod_params.disable, int, 0444);
1618 MODULE_PARM_DESC(disable50,
1619                   "manually disable the 50XX radio (default 0 [radio on])");
1620 module_param_named(swcrypto50, iwl50_mod_params.sw_crypto, bool, 0444);
1621 MODULE_PARM_DESC(swcrypto50,
1622                   "using software crypto engine (default 0 [hardware])\n");
1623 module_param_named(debug50, iwl50_mod_params.debug, int, 0444);
1624 MODULE_PARM_DESC(debug50, "50XX debug output mask");
1625 module_param_named(queues_num50, iwl50_mod_params.num_of_queues, int, 0444);
1626 MODULE_PARM_DESC(queues_num50, "number of hw queues in 50xx series");
1627 module_param_named(qos_enable50, iwl50_mod_params.enable_qos, int, 0444);
1628 MODULE_PARM_DESC(qos_enable50, "enable all 50XX QoS functionality");
1629 module_param_named(11n_disable50, iwl50_mod_params.disable_11n, int, 0444);
1630 MODULE_PARM_DESC(11n_disable50, "disable 50XX 11n functionality");
1631 module_param_named(amsdu_size_8K50, iwl50_mod_params.amsdu_size_8K, int, 0444);
1632 MODULE_PARM_DESC(amsdu_size_8K50, "enable 8K amsdu size in 50XX series");
1633 module_param_named(fw_restart50, iwl50_mod_params.restart_fw, int, 0444);
1634 MODULE_PARM_DESC(fw_restart50, "restart firmware in case of error");