1 /******************************************************************************
3 * Copyright(c) 2003 - 2008 Intel Corporation. All rights reserved.
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
24 * Contact Information:
25 * James P. Ketrenos <ipw2100-admin@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
28 *****************************************************************************/
30 #include <net/mac80211.h>
31 #include "iwl-eeprom.h"
36 #include "iwl-helpers.h"
39 * iwl_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
41 * Does NOT advance any TFD circular buffer read/write indexes
42 * Does NOT free the TFD itself (which is within circular buffer)
44 int iwl_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq)
46 struct iwl_tfd_frame *bd_tmp = (struct iwl_tfd_frame *)&txq->bd[0];
47 struct iwl_tfd_frame *bd = &bd_tmp[txq->q.read_ptr];
48 struct pci_dev *dev = priv->pci_dev;
53 /* Host command buffers stay mapped in memory, nothing to clean */
54 if (txq->q.id == IWL_CMD_QUEUE_NUM)
57 /* Sanity check on number of chunks */
58 counter = IWL_GET_BITS(*bd, num_tbs);
59 if (counter > MAX_NUM_OF_TBS) {
60 IWL_ERROR("Too many chunks: %i\n", counter);
61 /* @todo issue fatal error, it is quite serious situation */
65 /* Unmap chunks, if any.
66 * TFD info for odd chunks is different format than for even chunks. */
67 for (i = 0; i < counter; i++) {
74 IWL_GET_BITS(bd->pa[index], tb2_addr_lo16) |
75 (IWL_GET_BITS(bd->pa[index],
76 tb2_addr_hi20) << 16),
77 IWL_GET_BITS(bd->pa[index], tb2_len),
82 le32_to_cpu(bd->pa[index].tb1_addr),
83 IWL_GET_BITS(bd->pa[index], tb1_len),
86 /* Free SKB, if any, for this chunk */
87 if (txq->txb[txq->q.read_ptr].skb[i]) {
88 struct sk_buff *skb = txq->txb[txq->q.read_ptr].skb[i];
91 txq->txb[txq->q.read_ptr].skb[i] = NULL;
96 EXPORT_SYMBOL(iwl_hw_txq_free_tfd);
99 * iwl_tx_queue_free - Deallocate DMA queue.
100 * @txq: Transmit queue to deallocate.
102 * Empty queue by removing and destroying all BD's.
104 * 0-fill, but do not free "txq" descriptor structure.
106 static void iwl_tx_queue_free(struct iwl_priv *priv, struct iwl_tx_queue *txq)
108 struct iwl_queue *q = &txq->q;
109 struct pci_dev *dev = priv->pci_dev;
115 /* first, empty all BD's */
116 for (; q->write_ptr != q->read_ptr;
117 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd))
118 iwl_hw_txq_free_tfd(priv, txq);
120 len = sizeof(struct iwl_cmd) * q->n_window;
121 if (q->id == IWL_CMD_QUEUE_NUM)
122 len += IWL_MAX_SCAN_SIZE;
124 /* De-alloc array of command/tx buffers */
125 pci_free_consistent(dev, len, txq->cmd, txq->dma_addr_cmd);
127 /* De-alloc circular buffer of TFDs */
129 pci_free_consistent(dev, sizeof(struct iwl_tfd_frame) *
130 txq->q.n_bd, txq->bd, txq->q.dma_addr);
132 /* De-alloc array of per-TFD driver data */
136 /* 0-fill queue descriptor structure */
137 memset(txq, 0, sizeof(*txq));
141 * iwl_hw_txq_ctx_free - Free TXQ Context
143 * Destroy all TX DMA queues and structures
145 void iwl_hw_txq_ctx_free(struct iwl_priv *priv)
150 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++)
151 iwl_tx_queue_free(priv, &priv->txq[txq_id]);
153 /* Keep-warm buffer */
156 EXPORT_SYMBOL(iwl_hw_txq_ctx_free);
159 * iwl_queue_init - Initialize queue's high/low-water and read/write indexes
161 static int iwl_queue_init(struct iwl_priv *priv, struct iwl_queue *q,
162 int count, int slots_num, u32 id)
165 q->n_window = slots_num;
168 /* count must be power-of-two size, otherwise iwl_queue_inc_wrap
169 * and iwl_queue_dec_wrap are broken. */
170 BUG_ON(!is_power_of_2(count));
172 /* slots_num must be power-of-two size, otherwise
173 * get_cmd_index is broken. */
174 BUG_ON(!is_power_of_2(slots_num));
176 q->low_mark = q->n_window / 4;
180 q->high_mark = q->n_window / 8;
181 if (q->high_mark < 2)
184 q->write_ptr = q->read_ptr = 0;
190 * iwl_tx_queue_alloc - Alloc driver data and TFD CB for one Tx/cmd queue
192 static int iwl_tx_queue_alloc(struct iwl_priv *priv,
193 struct iwl_tx_queue *txq, u32 id)
195 struct pci_dev *dev = priv->pci_dev;
197 /* Driver private data, only for Tx (not command) queues,
198 * not shared with device. */
199 if (id != IWL_CMD_QUEUE_NUM) {
200 txq->txb = kmalloc(sizeof(txq->txb[0]) *
201 TFD_QUEUE_SIZE_MAX, GFP_KERNEL);
203 IWL_ERROR("kmalloc for auxiliary BD "
204 "structures failed\n");
210 /* Circular buffer of transmit frame descriptors (TFDs),
211 * shared with device */
212 txq->bd = pci_alloc_consistent(dev,
213 sizeof(txq->bd[0]) * TFD_QUEUE_SIZE_MAX,
217 IWL_ERROR("pci_alloc_consistent(%zd) failed\n",
218 sizeof(txq->bd[0]) * TFD_QUEUE_SIZE_MAX);
233 * Tell nic where to find circular buffer of Tx Frame Descriptors for
234 * given Tx queue, and enable the DMA channel used for that queue.
236 * 4965 supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA
237 * channels supported in hardware.
239 static int iwl_hw_tx_queue_init(struct iwl_priv *priv,
240 struct iwl_tx_queue *txq)
244 int txq_id = txq->q.id;
246 spin_lock_irqsave(&priv->lock, flags);
247 rc = iwl_grab_nic_access(priv);
249 spin_unlock_irqrestore(&priv->lock, flags);
253 /* Circular buffer (TFD queue in DRAM) physical base address */
254 iwl_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id),
255 txq->q.dma_addr >> 8);
257 /* Enable DMA channel, using same id as for TFD queue */
259 priv, FH_TCSR_CHNL_TX_CONFIG_REG(txq_id),
260 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
261 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL);
262 iwl_release_nic_access(priv);
263 spin_unlock_irqrestore(&priv->lock, flags);
269 * iwl_tx_queue_init - Allocate and initialize one tx/cmd queue
271 static int iwl_tx_queue_init(struct iwl_priv *priv,
272 struct iwl_tx_queue *txq,
273 int slots_num, u32 txq_id)
275 struct pci_dev *dev = priv->pci_dev;
280 * Alloc buffer array for commands (Tx or other types of commands).
281 * For the command queue (#4), allocate command space + one big
282 * command for scan, since scan command is very huge; the system will
283 * not have two scans at the same time, so only one is needed.
284 * For normal Tx queues (all other queues), no super-size command
287 len = sizeof(struct iwl_cmd) * slots_num;
288 if (txq_id == IWL_CMD_QUEUE_NUM)
289 len += IWL_MAX_SCAN_SIZE;
290 txq->cmd = pci_alloc_consistent(dev, len, &txq->dma_addr_cmd);
294 /* Alloc driver data array and TFD circular buffer */
295 rc = iwl_tx_queue_alloc(priv, txq, txq_id);
297 pci_free_consistent(dev, len, txq->cmd, txq->dma_addr_cmd);
301 txq->need_update = 0;
303 /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
304 * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */
305 BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1));
307 /* Initialize queue's high/low-water marks, and head/tail indexes */
308 iwl_queue_init(priv, &txq->q, TFD_QUEUE_SIZE_MAX, slots_num, txq_id);
310 /* Tell device where to find queue */
311 iwl_hw_tx_queue_init(priv, txq);
317 * iwl_txq_ctx_reset - Reset TX queue context
318 * Destroys all DMA structures and initialise them again
323 int iwl_txq_ctx_reset(struct iwl_priv *priv)
326 int txq_id, slots_num;
330 /* Free all tx/cmd queues and keep-warm buffer */
331 iwl_hw_txq_ctx_free(priv);
333 /* Alloc keep-warm buffer */
334 ret = iwl_kw_alloc(priv);
336 IWL_ERROR("Keep Warm allocation failed");
340 /* Turn off all Tx DMA fifos */
341 ret = priv->cfg->ops->lib->disable_tx_fifo(priv);
345 /* Tell nic where to find the keep-warm buffer */
346 ret = iwl_kw_init(priv);
348 IWL_ERROR("kw_init failed\n");
352 /* Alloc and init all (default 16) Tx queues,
353 * including the command queue (#4) */
354 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) {
355 slots_num = (txq_id == IWL_CMD_QUEUE_NUM) ?
356 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
357 ret = iwl_tx_queue_init(priv, &priv->txq[txq_id], slots_num,
360 IWL_ERROR("Tx %d queue init failed\n", txq_id);
368 iwl_hw_txq_ctx_free(priv);