drivers/net/wireless/rt2x00/rt73usb.c

   1 /*
   2         Copyright (C) 2004 - 2008 rt2x00 SourceForge Project
   3         <http://rt2x00.serialmonkey.com>
   4
   5         This program is free software; you can redistribute it and/or modify
   6         it under the terms of the GNU General Public License as published by
   7         the Free Software Foundation; either version 2 of the License, or
   8         (at your option) any later version.
   9
  10         This program is distributed in the hope that it will be useful,
  11         but WITHOUT ANY WARRANTY; without even the implied warranty of
  12         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13         GNU General Public License for more details.
  14
  15         You should have received a copy of the GNU General Public License
  16         along with this program; if not, write to the
  17         Free Software Foundation, Inc.,
  18         59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  19  */
  20
  21 /*
  22         Module: rt73usb
  23         Abstract: rt73usb device specific routines.
  24         Supported chipsets: rt2571W & rt2671.
  25  */
  26
  27 #include <linux/crc-itu-t.h>
  28 #include <linux/delay.h>
  29 #include <linux/etherdevice.h>
  30 #include <linux/init.h>
  31 #include <linux/kernel.h>
  32 #include <linux/module.h>
  33 #include <linux/usb.h>
  34
  35 #include "rt2x00.h"
  36 #include "rt2x00usb.h"
  37 #include "rt73usb.h"
  38
  39 /*
  40  * Allow hardware encryption to be disabled.
  41  */
  42 static int modparam_nohwcrypt = 0;
  43 module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
  44 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
  45
  46 /*
  47  * Register access.
  48  * All access to the CSR registers will go through the methods
  49  * rt73usb_register_read and rt73usb_register_write.
  50  * BBP and RF register require indirect register access,
  51  * and use the CSR registers BBPCSR and RFCSR to achieve this.
  52  * These indirect registers work with busy bits,
  53  * and we will try maximal REGISTER_BUSY_COUNT times to access
  54  * the register while taking a REGISTER_BUSY_DELAY us delay
  55  * between each attampt. When the busy bit is still set at that time,
  56  * the access attempt is considered to have failed,
  57  * and we will print an error.
  58  * The _lock versions must be used if you already hold the usb_cache_mutex
  59  */
  60 static inline void rt73usb_register_read(struct rt2x00_dev *rt2x00dev,
  61                                          const unsigned int offset, u32 *value)
  62 {
  63         __le32 reg;
  64         rt2x00usb_vendor_request_buff(rt2x00dev, USB_MULTI_READ,
  65                                       USB_VENDOR_REQUEST_IN, offset,
  66                                       &reg, sizeof(u32), REGISTER_TIMEOUT);
  67         *value = le32_to_cpu(reg);
  68 }
  69
  70 static inline void rt73usb_register_read_lock(struct rt2x00_dev *rt2x00dev,
  71                                               const unsigned int offset, u32 *value)
  72 {
  73         __le32 reg;
  74         rt2x00usb_vendor_req_buff_lock(rt2x00dev, USB_MULTI_READ,
  75                                        USB_VENDOR_REQUEST_IN, offset,
  76                                        &reg, sizeof(u32), REGISTER_TIMEOUT);
  77         *value = le32_to_cpu(reg);
  78 }
  79
  80 static inline void rt73usb_register_multiread(struct rt2x00_dev *rt2x00dev,
  81                                               const unsigned int offset,
  82                                               void *value, const u32 length)
  83 {
  84         rt2x00usb_vendor_request_buff(rt2x00dev, USB_MULTI_READ,
  85                                       USB_VENDOR_REQUEST_IN, offset,
  86                                       value, length,
  87                                       REGISTER_TIMEOUT32(length));
  88 }
  89
  90 static inline void rt73usb_register_write(struct rt2x00_dev *rt2x00dev,
  91                                           const unsigned int offset, u32 value)
  92 {
  93         __le32 reg = cpu_to_le32(value);
  94         rt2x00usb_vendor_request_buff(rt2x00dev, USB_MULTI_WRITE,
  95                                       USB_VENDOR_REQUEST_OUT, offset,
  96                                       &reg, sizeof(u32), REGISTER_TIMEOUT);
  97 }
  98
  99 static inline void rt73usb_register_write_lock(struct rt2x00_dev *rt2x00dev,
 100                                                const unsigned int offset, u32 value)
 101 {
 102         __le32 reg = cpu_to_le32(value);
 103         rt2x00usb_vendor_req_buff_lock(rt2x00dev, USB_MULTI_WRITE,
 104                                        USB_VENDOR_REQUEST_OUT, offset,
 105                                       &reg, sizeof(u32), REGISTER_TIMEOUT);
 106 }
 107
 108 static inline void rt73usb_register_multiwrite(struct rt2x00_dev *rt2x00dev,
 109                                                const unsigned int offset,
 110                                                void *value, const u32 length)
 111 {
 112         rt2x00usb_vendor_request_buff(rt2x00dev, USB_MULTI_WRITE,
 113                                       USB_VENDOR_REQUEST_OUT, offset,
 114                                       value, length,
 115                                       REGISTER_TIMEOUT32(length));
 116 }
 117
 118 static u32 rt73usb_bbp_check(struct rt2x00_dev *rt2x00dev)
 119 {
 120         u32 reg;
 121         unsigned int i;
 122
 123         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 124                 rt73usb_register_read_lock(rt2x00dev, PHY_CSR3, &reg);
 125                 if (!rt2x00_get_field32(reg, PHY_CSR3_BUSY))
 126                         break;
 127                 udelay(REGISTER_BUSY_DELAY);
 128         }
 129
 130         return reg;
 131 }
 132
 133 static void rt73usb_bbp_write(struct rt2x00_dev *rt2x00dev,
 134                               const unsigned int word, const u8 value)
 135 {
 136         u32 reg;
 137
 138         mutex_lock(&rt2x00dev->usb_cache_mutex);
 139
 140         /*
 141          * Wait until the BBP becomes ready.
 142          */
 143         reg = rt73usb_bbp_check(rt2x00dev);
 144         if (rt2x00_get_field32(reg, PHY_CSR3_BUSY))
 145                 goto exit_fail;
 146
 147         /*
 148          * Write the data into the BBP.
 149          */
 150         reg = 0;
 151         rt2x00_set_field32(&reg, PHY_CSR3_VALUE, value);
 152         rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
 153         rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
 154         rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 0);
 155
 156         rt73usb_register_write_lock(rt2x00dev, PHY_CSR3, reg);
 157         mutex_unlock(&rt2x00dev->usb_cache_mutex);
 158
 159         return;
 160
 161 exit_fail:
 162         mutex_unlock(&rt2x00dev->usb_cache_mutex);
 163
 164         ERROR(rt2x00dev, "PHY_CSR3 register busy. Write failed.\n");
 165 }
 166
 167 static void rt73usb_bbp_read(struct rt2x00_dev *rt2x00dev,
 168                              const unsigned int word, u8 *value)
 169 {
 170         u32 reg;
 171
 172         mutex_lock(&rt2x00dev->usb_cache_mutex);
 173
 174         /*
 175          * Wait until the BBP becomes ready.
 176          */
 177         reg = rt73usb_bbp_check(rt2x00dev);
 178         if (rt2x00_get_field32(reg, PHY_CSR3_BUSY))
 179                 goto exit_fail;
 180
 181         /*
 182          * Write the request into the BBP.
 183          */
 184         reg = 0;
 185         rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
 186         rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
 187         rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 1);
 188
 189         rt73usb_register_write_lock(rt2x00dev, PHY_CSR3, reg);
 190
 191         /*
 192          * Wait until the BBP becomes ready.
 193          */
 194         reg = rt73usb_bbp_check(rt2x00dev);
 195         if (rt2x00_get_field32(reg, PHY_CSR3_BUSY))
 196                 goto exit_fail;
 197
 198         *value = rt2x00_get_field32(reg, PHY_CSR3_VALUE);
 199         mutex_unlock(&rt2x00dev->usb_cache_mutex);
 200
 201         return;
 202
 203 exit_fail:
 204         mutex_unlock(&rt2x00dev->usb_cache_mutex);
 205
 206         ERROR(rt2x00dev, "PHY_CSR3 register busy. Read failed.\n");
 207         *value = 0xff;
 208 }
 209
 210 static void rt73usb_rf_write(struct rt2x00_dev *rt2x00dev,
 211                              const unsigned int word, const u32 value)
 212 {
 213         u32 reg;
 214         unsigned int i;
 215
 216         if (!word)
 217                 return;
 218
 219         mutex_lock(&rt2x00dev->usb_cache_mutex);
 220
 221         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 222                 rt73usb_register_read_lock(rt2x00dev, PHY_CSR4, &reg);
 223                 if (!rt2x00_get_field32(reg, PHY_CSR4_BUSY))
 224                         goto rf_write;
 225                 udelay(REGISTER_BUSY_DELAY);
 226         }
 227
 228         mutex_unlock(&rt2x00dev->usb_cache_mutex);
 229         ERROR(rt2x00dev, "PHY_CSR4 register busy. Write failed.\n");
 230         return;
 231
 232 rf_write:
 233         reg = 0;
 234         rt2x00_set_field32(&reg, PHY_CSR4_VALUE, value);
 235
 236         /*
 237          * RF5225 and RF2527 contain 21 bits per RF register value,
 238          * all others contain 20 bits.
 239          */
 240         rt2x00_set_field32(&reg, PHY_CSR4_NUMBER_OF_BITS,
 241                            20 + (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
 242                                  rt2x00_rf(&rt2x00dev->chip, RF2527)));
 243         rt2x00_set_field32(&reg, PHY_CSR4_IF_SELECT, 0);
 244         rt2x00_set_field32(&reg, PHY_CSR4_BUSY, 1);
 245
 246         rt73usb_register_write_lock(rt2x00dev, PHY_CSR4, reg);
 247         rt2x00_rf_write(rt2x00dev, word, value);
 248         mutex_unlock(&rt2x00dev->usb_cache_mutex);
 249 }
 250
 251 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
 252 #define CSR_OFFSET(__word)      ( CSR_REG_BASE + ((__word) * sizeof(u32)) )
 253
 254 static void rt73usb_read_csr(struct rt2x00_dev *rt2x00dev,
 255                              const unsigned int word, u32 *data)
 256 {
 257         rt73usb_register_read(rt2x00dev, CSR_OFFSET(word), data);
 258 }
 259
 260 static void rt73usb_write_csr(struct rt2x00_dev *rt2x00dev,
 261                               const unsigned int word, u32 data)
 262 {
 263         rt73usb_register_write(rt2x00dev, CSR_OFFSET(word), data);
 264 }
 265
 266 static const struct rt2x00debug rt73usb_rt2x00debug = {
 267         .owner  = THIS_MODULE,
 268         .csr    = {
 269                 .read           = rt73usb_read_csr,
 270                 .write          = rt73usb_write_csr,
 271                 .word_size      = sizeof(u32),
 272                 .word_count     = CSR_REG_SIZE / sizeof(u32),
 273         },
 274         .eeprom = {
 275                 .read           = rt2x00_eeprom_read,
 276                 .write          = rt2x00_eeprom_write,
 277                 .word_size      = sizeof(u16),
 278                 .word_count     = EEPROM_SIZE / sizeof(u16),
 279         },
 280         .bbp    = {
 281                 .read           = rt73usb_bbp_read,
 282                 .write          = rt73usb_bbp_write,
 283                 .word_size      = sizeof(u8),
 284                 .word_count     = BBP_SIZE / sizeof(u8),
 285         },
 286         .rf     = {
 287                 .read           = rt2x00_rf_read,
 288                 .write          = rt73usb_rf_write,
 289                 .word_size      = sizeof(u32),
 290                 .word_count     = RF_SIZE / sizeof(u32),
 291         },
 292 };
 293 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
 294
 295 #ifdef CONFIG_RT2X00_LIB_LEDS
 296 static void rt73usb_brightness_set(struct led_classdev *led_cdev,
 297                                    enum led_brightness brightness)
 298 {
 299         struct rt2x00_led *led =
 300            container_of(led_cdev, struct rt2x00_led, led_dev);
 301         unsigned int enabled = brightness != LED_OFF;
 302         unsigned int a_mode =
 303             (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
 304         unsigned int bg_mode =
 305             (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
 306
 307         if (led->type == LED_TYPE_RADIO) {
 308                 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
 309                                    MCU_LEDCS_RADIO_STATUS, enabled);
 310
 311                 rt2x00usb_vendor_request_sw(led->rt2x00dev, USB_LED_CONTROL,
 312                                             0, led->rt2x00dev->led_mcu_reg,
 313                                             REGISTER_TIMEOUT);
 314         } else if (led->type == LED_TYPE_ASSOC) {
 315                 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
 316                                    MCU_LEDCS_LINK_BG_STATUS, bg_mode);
 317                 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
 318                                    MCU_LEDCS_LINK_A_STATUS, a_mode);
 319
 320                 rt2x00usb_vendor_request_sw(led->rt2x00dev, USB_LED_CONTROL,
 321                                             0, led->rt2x00dev->led_mcu_reg,
 322                                             REGISTER_TIMEOUT);
 323         } else if (led->type == LED_TYPE_QUALITY) {
 324                 /*
 325                  * The brightness is divided into 6 levels (0 - 5),
 326                  * this means we need to convert the brightness
 327                  * argument into the matching level within that range.
 328                  */
 329                 rt2x00usb_vendor_request_sw(led->rt2x00dev, USB_LED_CONTROL,
 330                                             brightness / (LED_FULL / 6),
 331                                             led->rt2x00dev->led_mcu_reg,
 332                                             REGISTER_TIMEOUT);
 333         }
 334 }
 335
 336 static int rt73usb_blink_set(struct led_classdev *led_cdev,
 337                              unsigned long *delay_on,
 338                              unsigned long *delay_off)
 339 {
 340         struct rt2x00_led *led =
 341             container_of(led_cdev, struct rt2x00_led, led_dev);
 342         u32 reg;
 343
 344         rt73usb_register_read(led->rt2x00dev, MAC_CSR14, &reg);
 345         rt2x00_set_field32(&reg, MAC_CSR14_ON_PERIOD, *delay_on);
 346         rt2x00_set_field32(&reg, MAC_CSR14_OFF_PERIOD, *delay_off);
 347         rt73usb_register_write(led->rt2x00dev, MAC_CSR14, reg);
 348
 349         return 0;
 350 }
 351
 352 static void rt73usb_init_led(struct rt2x00_dev *rt2x00dev,
 353                              struct rt2x00_led *led,
 354                              enum led_type type)
 355 {
 356         led->rt2x00dev = rt2x00dev;
 357         led->type = type;
 358         led->led_dev.brightness_set = rt73usb_brightness_set;
 359         led->led_dev.blink_set = rt73usb_blink_set;
 360         led->flags = LED_INITIALIZED;
 361 }
 362 #endif /* CONFIG_RT2X00_LIB_LEDS */
 363
 364 /*
 365  * Configuration handlers.
 366  */
 367 static int rt73usb_config_shared_key(struct rt2x00_dev *rt2x00dev,
 368                                      struct rt2x00lib_crypto *crypto,
 369                                      struct ieee80211_key_conf *key)
 370 {
 371         struct hw_key_entry key_entry;
 372         struct rt2x00_field32 field;
 373         int timeout;
 374         u32 mask;
 375         u32 reg;
 376
 377         if (crypto->cmd == SET_KEY) {
 378                 /*
 379                  * rt2x00lib can't determine the correct free
 380                  * key_idx for shared keys. We have 1 register
 381                  * with key valid bits. The goal is simple, read
 382                  * the register, if that is full we have no slots
 383                  * left.
 384                  * Note that each BSS is allowed to have up to 4
 385                  * shared keys, so put a mask over the allowed
 386                  * entries.
 387                  */
 388                 mask = (0xf << crypto->bssidx);
 389
 390                 rt73usb_register_read(rt2x00dev, SEC_CSR0, &reg);
 391                 reg &= mask;
 392
 393                 if (reg && reg == mask)
 394                         return -ENOSPC;
 395
 396                 key->hw_key_idx += reg ? ffz(reg) : 0;
 397
 398                 /*
 399                  * Upload key to hardware
 400                  */
 401                 memcpy(key_entry.key, crypto->key,
 402                        sizeof(key_entry.key));
 403                 memcpy(key_entry.tx_mic, crypto->tx_mic,
 404                        sizeof(key_entry.tx_mic));
 405                 memcpy(key_entry.rx_mic, crypto->rx_mic,
 406                        sizeof(key_entry.rx_mic));
 407
 408                 reg = SHARED_KEY_ENTRY(key->hw_key_idx);
 409                 timeout = REGISTER_TIMEOUT32(sizeof(key_entry));
 410                 rt2x00usb_vendor_request_large_buff(rt2x00dev, USB_MULTI_WRITE,
 411                                                     USB_VENDOR_REQUEST_OUT, reg,
 412                                                     &key_entry,
 413                                                     sizeof(key_entry),
 414                                                     timeout);
 415
 416                 /*
 417                  * The cipher types are stored over 2 registers.
 418                  * bssidx 0 and 1 keys are stored in SEC_CSR1 and
 419                  * bssidx 1 and 2 keys are stored in SEC_CSR5.
 420                  * Using the correct defines correctly will cause overhead,
 421                  * so just calculate the correct offset.
 422                  */
 423                 if (key->hw_key_idx < 8) {
 424                         field.bit_offset = (3 * key->hw_key_idx);
 425                         field.bit_mask = 0x7 << field.bit_offset;
 426
 427                         rt73usb_register_read(rt2x00dev, SEC_CSR1, &reg);
 428                         rt2x00_set_field32(&reg, field, crypto->cipher);
 429                         rt73usb_register_write(rt2x00dev, SEC_CSR1, reg);
 430                 } else {
 431                         field.bit_offset = (3 * (key->hw_key_idx - 8));
 432                         field.bit_mask = 0x7 << field.bit_offset;
 433
 434                         rt73usb_register_read(rt2x00dev, SEC_CSR5, &reg);
 435                         rt2x00_set_field32(&reg, field, crypto->cipher);
 436                         rt73usb_register_write(rt2x00dev, SEC_CSR5, reg);
 437                 }
 438
 439                 /*
 440                  * The driver does not support the IV/EIV generation
 441                  * in hardware. However it doesn't support the IV/EIV
 442                  * inside the ieee80211 frame either, but requires it
 443                  * to be provided seperately for the descriptor.
 444                  * rt2x00lib will cut the IV/EIV data out of all frames
 445                  * given to us by mac80211, but we must tell mac80211
 446                  * to generate the IV/EIV data.
 447                  */
 448                 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
 449         }
 450
 451         /*
 452          * SEC_CSR0 contains only single-bit fields to indicate
 453          * a particular key is valid. Because using the FIELD32()
 454          * defines directly will cause a lot of overhead we use
 455          * a calculation to determine the correct bit directly.
 456          */
 457         mask = 1 << key->hw_key_idx;
 458
 459         rt73usb_register_read(rt2x00dev, SEC_CSR0, &reg);
 460         if (crypto->cmd == SET_KEY)
 461                 reg |= mask;
 462         else if (crypto->cmd == DISABLE_KEY)
 463                 reg &= ~mask;
 464         rt73usb_register_write(rt2x00dev, SEC_CSR0, reg);
 465
 466         return 0;
 467 }
 468
 469 static int rt73usb_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
 470                                        struct rt2x00lib_crypto *crypto,
 471                                        struct ieee80211_key_conf *key)
 472 {
 473         struct hw_pairwise_ta_entry addr_entry;
 474         struct hw_key_entry key_entry;
 475         int timeout;
 476         u32 mask;
 477         u32 reg;
 478
 479         if (crypto->cmd == SET_KEY) {
 480                 /*
 481                  * rt2x00lib can't determine the correct free
 482                  * key_idx for pairwise keys. We have 2 registers
 483                  * with key valid bits. The goal is simple, read
 484                  * the first register, if that is full move to
 485                  * the next register.
 486                  * When both registers are full, we drop the key,
 487                  * otherwise we use the first invalid entry.
 488                  */
 489                 rt73usb_register_read(rt2x00dev, SEC_CSR2, &reg);
 490                 if (reg && reg == ~0) {
 491                         key->hw_key_idx = 32;
 492                         rt73usb_register_read(rt2x00dev, SEC_CSR3, &reg);
 493                         if (reg && reg == ~0)
 494                                 return -ENOSPC;
 495                 }
 496
 497                 key->hw_key_idx += reg ? ffz(reg) : 0;
 498
 499                 /*
 500                  * Upload key to hardware
 501                  */
 502                 memcpy(key_entry.key, crypto->key,
 503                        sizeof(key_entry.key));
 504                 memcpy(key_entry.tx_mic, crypto->tx_mic,
 505                        sizeof(key_entry.tx_mic));
 506                 memcpy(key_entry.rx_mic, crypto->rx_mic,
 507                        sizeof(key_entry.rx_mic));
 508
 509                 reg = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
 510                 timeout = REGISTER_TIMEOUT32(sizeof(key_entry));
 511                 rt2x00usb_vendor_request_large_buff(rt2x00dev, USB_MULTI_WRITE,
 512                                                     USB_VENDOR_REQUEST_OUT, reg,
 513                                                     &key_entry,
 514                                                     sizeof(key_entry),
 515                                                     timeout);
 516
 517                 /*
 518                  * Send the address and cipher type to the hardware register.
 519                  * This data fits within the CSR cache size, so we can use
 520                  * rt73usb_register_multiwrite() directly.
 521                  */
 522                 memset(&addr_entry, 0, sizeof(addr_entry));
 523                 memcpy(&addr_entry, crypto->address, ETH_ALEN);
 524                 addr_entry.cipher = crypto->cipher;
 525
 526                 reg = PAIRWISE_TA_ENTRY(key->hw_key_idx);
 527                 rt73usb_register_multiwrite(rt2x00dev, reg,
 528                                             &addr_entry, sizeof(addr_entry));
 529
 530                 /*
 531                  * Enable pairwise lookup table for given BSS idx,
 532                  * without this received frames will not be decrypted
 533                  * by the hardware.
 534                  */
 535                 rt73usb_register_read(rt2x00dev, SEC_CSR4, &reg);
 536                 reg |= (1 << crypto->bssidx);
 537                 rt73usb_register_write(rt2x00dev, SEC_CSR4, reg);
 538
 539                 /*
 540                  * The driver does not support the IV/EIV generation
 541                  * in hardware. However it doesn't support the IV/EIV
 542                  * inside the ieee80211 frame either, but requires it
 543                  * to be provided seperately for the descriptor.
 544                  * rt2x00lib will cut the IV/EIV data out of all frames
 545                  * given to us by mac80211, but we must tell mac80211
 546                  * to generate the IV/EIV data.
 547                  */
 548                 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
 549         }
 550
 551         /*
 552          * SEC_CSR2 and SEC_CSR3 contain only single-bit fields to indicate
 553          * a particular key is valid. Because using the FIELD32()
 554          * defines directly will cause a lot of overhead we use
 555          * a calculation to determine the correct bit directly.
 556          */
 557         if (key->hw_key_idx < 32) {
 558                 mask = 1 << key->hw_key_idx;
 559
 560                 rt73usb_register_read(rt2x00dev, SEC_CSR2, &reg);
 561                 if (crypto->cmd == SET_KEY)
 562                         reg |= mask;
 563                 else if (crypto->cmd == DISABLE_KEY)
 564                         reg &= ~mask;
 565                 rt73usb_register_write(rt2x00dev, SEC_CSR2, reg);
 566         } else {
 567                 mask = 1 << (key->hw_key_idx - 32);
 568
 569                 rt73usb_register_read(rt2x00dev, SEC_CSR3, &reg);
 570                 if (crypto->cmd == SET_KEY)
 571                         reg |= mask;
 572                 else if (crypto->cmd == DISABLE_KEY)
 573                         reg &= ~mask;
 574                 rt73usb_register_write(rt2x00dev, SEC_CSR3, reg);
 575         }
 576
 577         return 0;
 578 }
 579
 580 static void rt73usb_config_filter(struct rt2x00_dev *rt2x00dev,
 581                                   const unsigned int filter_flags)
 582 {
 583         u32 reg;
 584
 585         /*
 586          * Start configuration steps.
 587          * Note that the version error will always be dropped
 588          * and broadcast frames will always be accepted since
 589          * there is no filter for it at this time.
 590          */
 591         rt73usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
 592         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CRC,
 593                            !(filter_flags & FIF_FCSFAIL));
 594         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_PHYSICAL,
 595                            !(filter_flags & FIF_PLCPFAIL));
 596         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CONTROL,
 597                            !(filter_flags & FIF_CONTROL));
 598         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_NOT_TO_ME,
 599                            !(filter_flags & FIF_PROMISC_IN_BSS));
 600         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_TO_DS,
 601                            !(filter_flags & FIF_PROMISC_IN_BSS) &&
 602                            !rt2x00dev->intf_ap_count);
 603         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_VERSION_ERROR, 1);
 604         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_MULTICAST,
 605                            !(filter_flags & FIF_ALLMULTI));
 606         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_BROADCAST, 0);
 607         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_ACK_CTS,
 608                            !(filter_flags & FIF_CONTROL));
 609         rt73usb_register_write(rt2x00dev, TXRX_CSR0, reg);
 610 }
 611
 612 static void rt73usb_config_intf(struct rt2x00_dev *rt2x00dev,
 613                                 struct rt2x00_intf *intf,
 614                                 struct rt2x00intf_conf *conf,
 615                                 const unsigned int flags)
 616 {
 617         unsigned int beacon_base;
 618         u32 reg;
 619
 620         if (flags & CONFIG_UPDATE_TYPE) {
 621                 /*
 622                  * Clear current synchronisation setup.
 623                  * For the Beacon base registers we only need to clear
 624                  * the first byte since that byte contains the VALID and OWNER
 625                  * bits which (when set to 0) will invalidate the entire beacon.
 626                  */
 627                 beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
 628                 rt73usb_register_write(rt2x00dev, beacon_base, 0);
 629
 630                 /*
 631                  * Enable synchronisation.
 632                  */
 633                 rt73usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
 634                 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
 635                 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, conf->sync);
 636                 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1);
 637                 rt73usb_register_write(rt2x00dev, TXRX_CSR9, reg);
 638         }
 639
 640         if (flags & CONFIG_UPDATE_MAC) {
 641                 reg = le32_to_cpu(conf->mac[1]);
 642                 rt2x00_set_field32(&reg, MAC_CSR3_UNICAST_TO_ME_MASK, 0xff);
 643                 conf->mac[1] = cpu_to_le32(reg);
 644
 645                 rt73usb_register_multiwrite(rt2x00dev, MAC_CSR2,
 646                                             conf->mac, sizeof(conf->mac));
 647         }
 648
 649         if (flags & CONFIG_UPDATE_BSSID) {
 650                 reg = le32_to_cpu(conf->bssid[1]);
 651                 rt2x00_set_field32(&reg, MAC_CSR5_BSS_ID_MASK, 3);
 652                 conf->bssid[1] = cpu_to_le32(reg);
 653
 654                 rt73usb_register_multiwrite(rt2x00dev, MAC_CSR4,
 655                                             conf->bssid, sizeof(conf->bssid));
 656         }
 657 }
 658
 659 static void rt73usb_config_erp(struct rt2x00_dev *rt2x00dev,
 660                                struct rt2x00lib_erp *erp)
 661 {
 662         u32 reg;
 663
 664         rt73usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
 665         rt2x00_set_field32(&reg, TXRX_CSR0_RX_ACK_TIMEOUT, erp->ack_timeout);
 666         rt73usb_register_write(rt2x00dev, TXRX_CSR0, reg);
 667
 668         rt73usb_register_read(rt2x00dev, TXRX_CSR4, &reg);
 669         rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_PREAMBLE,
 670                            !!erp->short_preamble);
 671         rt73usb_register_write(rt2x00dev, TXRX_CSR4, reg);
 672
 673         rt73usb_register_write(rt2x00dev, TXRX_CSR5, erp->basic_rates);
 674
 675         rt73usb_register_read(rt2x00dev, MAC_CSR9, &reg);
 676         rt2x00_set_field32(&reg, MAC_CSR9_SLOT_TIME, erp->slot_time);
 677         rt73usb_register_write(rt2x00dev, MAC_CSR9, reg);
 678
 679         rt73usb_register_read(rt2x00dev, MAC_CSR8, &reg);
 680         rt2x00_set_field32(&reg, MAC_CSR8_SIFS, erp->sifs);
 681         rt2x00_set_field32(&reg, MAC_CSR8_SIFS_AFTER_RX_OFDM, 3);
 682         rt2x00_set_field32(&reg, MAC_CSR8_EIFS, erp->eifs);
 683         rt73usb_register_write(rt2x00dev, MAC_CSR8, reg);
 684 }
 685
 686 static void rt73usb_config_antenna_5x(struct rt2x00_dev *rt2x00dev,
 687                                       struct antenna_setup *ant)
 688 {
 689         u8 r3;
 690         u8 r4;
 691         u8 r77;
 692         u8 temp;
 693
 694         rt73usb_bbp_read(rt2x00dev, 3, &r3);
 695         rt73usb_bbp_read(rt2x00dev, 4, &r4);
 696         rt73usb_bbp_read(rt2x00dev, 77, &r77);
 697
 698         rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, 0);
 699
 700         /*
 701          * Configure the RX antenna.
 702          */
 703         switch (ant->rx) {
 704         case ANTENNA_HW_DIVERSITY:
 705                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
 706                 temp = !test_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags)
 707                        && (rt2x00dev->curr_band != IEEE80211_BAND_5GHZ);
 708                 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, temp);
 709                 break;
 710         case ANTENNA_A:
 711                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
 712                 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
 713                 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ)
 714                         rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
 715                 else
 716                         rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
 717                 break;
 718         case ANTENNA_B:
 719         default:
 720                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
 721                 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
 722                 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ)
 723                         rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
 724                 else
 725                         rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
 726                 break;
 727         }
 728
 729         rt73usb_bbp_write(rt2x00dev, 77, r77);
 730         rt73usb_bbp_write(rt2x00dev, 3, r3);
 731         rt73usb_bbp_write(rt2x00dev, 4, r4);
 732 }
 733
 734 static void rt73usb_config_antenna_2x(struct rt2x00_dev *rt2x00dev,
 735                                       struct antenna_setup *ant)
 736 {
 737         u8 r3;
 738         u8 r4;
 739         u8 r77;
 740
 741         rt73usb_bbp_read(rt2x00dev, 3, &r3);
 742         rt73usb_bbp_read(rt2x00dev, 4, &r4);
 743         rt73usb_bbp_read(rt2x00dev, 77, &r77);
 744
 745         rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, 0);
 746         rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
 747                           !test_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags));
 748
 749         /*
 750          * Configure the RX antenna.
 751          */
 752         switch (ant->rx) {
 753         case ANTENNA_HW_DIVERSITY:
 754                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
 755                 break;
 756         case ANTENNA_A:
 757                 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
 758                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
 759                 break;
 760         case ANTENNA_B:
 761         default:
 762                 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
 763                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
 764                 break;
 765         }
 766
 767         rt73usb_bbp_write(rt2x00dev, 77, r77);
 768         rt73usb_bbp_write(rt2x00dev, 3, r3);
 769         rt73usb_bbp_write(rt2x00dev, 4, r4);
 770 }
 771
 772 struct antenna_sel {
 773         u8 word;
 774         /*
 775          * value[0] -> non-LNA
 776          * value[1] -> LNA
 777          */
 778         u8 value[2];
 779 };
 780
 781 static const struct antenna_sel antenna_sel_a[] = {
 782         { 96,  { 0x58, 0x78 } },
 783         { 104, { 0x38, 0x48 } },
 784         { 75,  { 0xfe, 0x80 } },
 785         { 86,  { 0xfe, 0x80 } },
 786         { 88,  { 0xfe, 0x80 } },
 787         { 35,  { 0x60, 0x60 } },
 788         { 97,  { 0x58, 0x58 } },
 789         { 98,  { 0x58, 0x58 } },
 790 };
 791
 792 static const struct antenna_sel antenna_sel_bg[] = {
 793         { 96,  { 0x48, 0x68 } },
 794         { 104, { 0x2c, 0x3c } },
 795         { 75,  { 0xfe, 0x80 } },
 796         { 86,  { 0xfe, 0x80 } },
 797         { 88,  { 0xfe, 0x80 } },
 798         { 35,  { 0x50, 0x50 } },
 799         { 97,  { 0x48, 0x48 } },
 800         { 98,  { 0x48, 0x48 } },
 801 };
 802
 803 static void rt73usb_config_ant(struct rt2x00_dev *rt2x00dev,
 804                                struct antenna_setup *ant)
 805 {
 806         const struct antenna_sel *sel;
 807         unsigned int lna;
 808         unsigned int i;
 809         u32 reg;
 810
 811         /*
 812          * We should never come here because rt2x00lib is supposed
 813          * to catch this and send us the correct antenna explicitely.
 814          */
 815         BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY ||
 816                ant->tx == ANTENNA_SW_DIVERSITY);
 817
 818         if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
 819                 sel = antenna_sel_a;
 820                 lna = test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
 821         } else {
 822                 sel = antenna_sel_bg;
 823                 lna = test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
 824         }
 825
 826         for (i = 0; i < ARRAY_SIZE(antenna_sel_a); i++)
 827                 rt73usb_bbp_write(rt2x00dev, sel[i].word, sel[i].value[lna]);
 828
 829         rt73usb_register_read(rt2x00dev, PHY_CSR0, &reg);
 830
 831         rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_BG,
 832                            (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ));
 833         rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_A,
 834                            (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ));
 835
 836         rt73usb_register_write(rt2x00dev, PHY_CSR0, reg);
 837
 838         if (rt2x00_rf(&rt2x00dev->chip, RF5226) ||
 839             rt2x00_rf(&rt2x00dev->chip, RF5225))
 840                 rt73usb_config_antenna_5x(rt2x00dev, ant);
 841         else if (rt2x00_rf(&rt2x00dev->chip, RF2528) ||
 842                  rt2x00_rf(&rt2x00dev->chip, RF2527))
 843                 rt73usb_config_antenna_2x(rt2x00dev, ant);
 844 }
 845
 846 static void rt73usb_config_lna_gain(struct rt2x00_dev *rt2x00dev,
 847                                     struct rt2x00lib_conf *libconf)
 848 {
 849         u16 eeprom;
 850         short lna_gain = 0;
 851
 852         if (libconf->conf->channel->band == IEEE80211_BAND_2GHZ) {
 853                 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags))
 854                         lna_gain += 14;
 855
 856                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &eeprom);
 857                 lna_gain -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_BG_1);
 858         } else {
 859                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &eeprom);
 860                 lna_gain -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_A_1);
 861         }
 862
 863         rt2x00dev->lna_gain = lna_gain;
 864 }
 865
 866 static void rt73usb_config_channel(struct rt2x00_dev *rt2x00dev,
 867                                    struct rf_channel *rf, const int txpower)
 868 {
 869         u8 r3;
 870         u8 r94;
 871         u8 smart;
 872
 873         rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
 874         rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
 875
 876         smart = !(rt2x00_rf(&rt2x00dev->chip, RF5225) ||
 877                   rt2x00_rf(&rt2x00dev->chip, RF2527));
 878
 879         rt73usb_bbp_read(rt2x00dev, 3, &r3);
 880         rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, smart);
 881         rt73usb_bbp_write(rt2x00dev, 3, r3);
 882
 883         r94 = 6;
 884         if (txpower > MAX_TXPOWER && txpower <= (MAX_TXPOWER + r94))
 885                 r94 += txpower - MAX_TXPOWER;
 886         else if (txpower < MIN_TXPOWER && txpower >= (MIN_TXPOWER - r94))
 887                 r94 += txpower;
 888         rt73usb_bbp_write(rt2x00dev, 94, r94);
 889
 890         rt73usb_rf_write(rt2x00dev, 1, rf->rf1);
 891         rt73usb_rf_write(rt2x00dev, 2, rf->rf2);
 892         rt73usb_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
 893         rt73usb_rf_write(rt2x00dev, 4, rf->rf4);
 894
 895         rt73usb_rf_write(rt2x00dev, 1, rf->rf1);
 896         rt73usb_rf_write(rt2x00dev, 2, rf->rf2);
 897         rt73usb_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
 898         rt73usb_rf_write(rt2x00dev, 4, rf->rf4);
 899
 900         rt73usb_rf_write(rt2x00dev, 1, rf->rf1);
 901         rt73usb_rf_write(rt2x00dev, 2, rf->rf2);
 902         rt73usb_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
 903         rt73usb_rf_write(rt2x00dev, 4, rf->rf4);
 904
 905         udelay(10);
 906 }
 907
 908 static void rt73usb_config_txpower(struct rt2x00_dev *rt2x00dev,
 909                                    const int txpower)
 910 {
 911         struct rf_channel rf;
 912
 913         rt2x00_rf_read(rt2x00dev, 1, &rf.rf1);
 914         rt2x00_rf_read(rt2x00dev, 2, &rf.rf2);
 915         rt2x00_rf_read(rt2x00dev, 3, &rf.rf3);
 916         rt2x00_rf_read(rt2x00dev, 4, &rf.rf4);
 917
 918         rt73usb_config_channel(rt2x00dev, &rf, txpower);
 919 }
 920
 921 static void rt73usb_config_retry_limit(struct rt2x00_dev *rt2x00dev,
 922                                        struct rt2x00lib_conf *libconf)
 923 {
 924         u32 reg;
 925
 926         rt73usb_register_read(rt2x00dev, TXRX_CSR4, &reg);
 927         rt2x00_set_field32(&reg, TXRX_CSR4_LONG_RETRY_LIMIT,
 928                            libconf->conf->long_frame_max_tx_count);
 929         rt2x00_set_field32(&reg, TXRX_CSR4_SHORT_RETRY_LIMIT,
 930                            libconf->conf->short_frame_max_tx_count);
 931         rt73usb_register_write(rt2x00dev, TXRX_CSR4, reg);
 932 }
 933
 934 static void rt73usb_config_duration(struct rt2x00_dev *rt2x00dev,
 935                                     struct rt2x00lib_conf *libconf)
 936 {
 937         u32 reg;
 938
 939         rt73usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
 940         rt2x00_set_field32(&reg, TXRX_CSR0_TSF_OFFSET, IEEE80211_HEADER);
 941         rt73usb_register_write(rt2x00dev, TXRX_CSR0, reg);
 942
 943         rt73usb_register_read(rt2x00dev, TXRX_CSR4, &reg);
 944         rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_ENABLE, 1);
 945         rt73usb_register_write(rt2x00dev, TXRX_CSR4, reg);
 946
 947         rt73usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
 948         rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL,
 949                            libconf->conf->beacon_int * 16);
 950         rt73usb_register_write(rt2x00dev, TXRX_CSR9, reg);
 951 }
 952
 953 static void rt73usb_config(struct rt2x00_dev *rt2x00dev,
 954                            struct rt2x00lib_conf *libconf,
 955                            const unsigned int flags)
 956 {
 957         /* Always recalculate LNA gain before changing configuration */
 958         rt73usb_config_lna_gain(rt2x00dev, libconf);
 959
 960         if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
 961                 rt73usb_config_channel(rt2x00dev, &libconf->rf,
 962                                        libconf->conf->power_level);
 963         if ((flags & IEEE80211_CONF_CHANGE_POWER) &&
 964             !(flags & IEEE80211_CONF_CHANGE_CHANNEL))
 965                 rt73usb_config_txpower(rt2x00dev, libconf->conf->power_level);
 966         if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
 967                 rt73usb_config_retry_limit(rt2x00dev, libconf);
 968         if (flags & IEEE80211_CONF_CHANGE_BEACON_INTERVAL)
 969                 rt73usb_config_duration(rt2x00dev, libconf);
 970 }
 971
 972 /*
 973  * Link tuning
 974  */
 975 static void rt73usb_link_stats(struct rt2x00_dev *rt2x00dev,
 976                                struct link_qual *qual)
 977 {
 978         u32 reg;
 979
 980         /*
 981          * Update FCS error count from register.
 982          */
 983         rt73usb_register_read(rt2x00dev, STA_CSR0, &reg);
 984         qual->rx_failed = rt2x00_get_field32(reg, STA_CSR0_FCS_ERROR);
 985
 986         /*
 987          * Update False CCA count from register.
 988          */
 989         rt73usb_register_read(rt2x00dev, STA_CSR1, &reg);
 990         qual->false_cca = rt2x00_get_field32(reg, STA_CSR1_FALSE_CCA_ERROR);
 991 }
 992
 993 static void rt73usb_reset_tuner(struct rt2x00_dev *rt2x00dev)
 994 {
 995         rt73usb_bbp_write(rt2x00dev, 17, 0x20);
 996         rt2x00dev->link.vgc_level = 0x20;
 997 }
 998
 999 static void rt73usb_link_tuner(struct rt2x00_dev *rt2x00dev)
1000 {
1001         int rssi = rt2x00_get_link_rssi(&rt2x00dev->link);
1002         u8 r17;
1003         u8 up_bound;
1004         u8 low_bound;
1005
1006         rt73usb_bbp_read(rt2x00dev, 17, &r17);
1007
1008         /*
1009          * Determine r17 bounds.
1010          */
1011         if (rt2x00dev->rx_status.band == IEEE80211_BAND_5GHZ) {
1012                 low_bound = 0x28;
1013                 up_bound = 0x48;
1014
1015                 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) {
1016                         low_bound += 0x10;
1017                         up_bound += 0x10;
1018                 }
1019         } else {
1020                 if (rssi > -82) {
1021                         low_bound = 0x1c;
1022                         up_bound = 0x40;
1023                 } else if (rssi > -84) {
1024                         low_bound = 0x1c;
1025                         up_bound = 0x20;
1026                 } else {
1027                         low_bound = 0x1c;
1028                         up_bound = 0x1c;
1029                 }
1030
1031                 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
1032                         low_bound += 0x14;
1033                         up_bound += 0x10;
1034                 }
1035         }
1036
1037         /*
1038          * If we are not associated, we should go straight to the
1039          * dynamic CCA tuning.
1040          */
1041         if (!rt2x00dev->intf_associated)
1042                 goto dynamic_cca_tune;
1043
1044         /*
1045          * Special big-R17 for very short distance
1046          */
1047         if (rssi > -35) {
1048                 if (r17 != 0x60)
1049                         rt73usb_bbp_write(rt2x00dev, 17, 0x60);
1050                 return;
1051         }
1052
1053         /*
1054          * Special big-R17 for short distance
1055          */
1056         if (rssi >= -58) {
1057                 if (r17 != up_bound)
1058                         rt73usb_bbp_write(rt2x00dev, 17, up_bound);
1059                 return;
1060         }
1061
1062         /*
1063          * Special big-R17 for middle-short distance
1064          */
1065         if (rssi >= -66) {
1066                 low_bound += 0x10;
1067                 if (r17 != low_bound)
1068                         rt73usb_bbp_write(rt2x00dev, 17, low_bound);
1069                 return;
1070         }
1071
1072         /*
1073          * Special mid-R17 for middle distance
1074          */
1075         if (rssi >= -74) {
1076                 if (r17 != (low_bound + 0x10))
1077                         rt73usb_bbp_write(rt2x00dev, 17, low_bound + 0x08);
1078                 return;
1079         }
1080
1081         /*
1082          * Special case: Change up_bound based on the rssi.
1083          * Lower up_bound when rssi is weaker then -74 dBm.
1084          */
1085         up_bound -= 2 * (-74 - rssi);
1086         if (low_bound > up_bound)
1087                 up_bound = low_bound;
1088
1089         if (r17 > up_bound) {
1090                 rt73usb_bbp_write(rt2x00dev, 17, up_bound);
1091                 return;
1092         }
1093
1094 dynamic_cca_tune:
1095
1096         /*
1097          * r17 does not yet exceed upper limit, continue and base
1098          * the r17 tuning on the false CCA count.
1099          */
1100         if (rt2x00dev->link.qual.false_cca > 512 && r17 < up_bound) {
1101                 r17 += 4;
1102                 if (r17 > up_bound)
1103                         r17 = up_bound;
1104                 rt73usb_bbp_write(rt2x00dev, 17, r17);
1105         } else if (rt2x00dev->link.qual.false_cca < 100 && r17 > low_bound) {
1106                 r17 -= 4;
1107                 if (r17 < low_bound)
1108                         r17 = low_bound;
1109                 rt73usb_bbp_write(rt2x00dev, 17, r17);
1110         }
1111 }
1112
1113 /*
1114  * Firmware functions
1115  */
1116 static char *rt73usb_get_firmware_name(struct rt2x00_dev *rt2x00dev)
1117 {
1118         return FIRMWARE_RT2571;
1119 }
1120
1121 static u16 rt73usb_get_firmware_crc(const void *data, const size_t len)
1122 {
1123         u16 crc;
1124
1125         /*
1126          * Use the crc itu-t algorithm.
1127          * The last 2 bytes in the firmware array are the crc checksum itself,
1128          * this means that we should never pass those 2 bytes to the crc
1129          * algorithm.
1130          */
1131         crc = crc_itu_t(0, data, len - 2);
1132         crc = crc_itu_t_byte(crc, 0);
1133         crc = crc_itu_t_byte(crc, 0);
1134
1135         return crc;
1136 }
1137
1138 static int rt73usb_load_firmware(struct rt2x00_dev *rt2x00dev, const void *data,
1139                                  const size_t len)
1140 {
1141         unsigned int i;
1142         int status;
1143         u32 reg;
1144
1145         /*
1146          * Wait for stable hardware.
1147          */
1148         for (i = 0; i < 100; i++) {
1149                 rt73usb_register_read(rt2x00dev, MAC_CSR0, &reg);
1150                 if (reg)
1151                         break;
1152                 msleep(1);
1153         }
1154
1155         if (!reg) {
1156                 ERROR(rt2x00dev, "Unstable hardware.\n");
1157                 return -EBUSY;
1158         }
1159
1160         /*
1161          * Write firmware to device.
1162          */
1163         rt2x00usb_vendor_request_large_buff(rt2x00dev, USB_MULTI_WRITE,
1164                                             USB_VENDOR_REQUEST_OUT,
1165                                             FIRMWARE_IMAGE_BASE,
1166                                             data, len,
1167                                             REGISTER_TIMEOUT32(len));
1168
1169         /*
1170          * Send firmware request to device to load firmware,
1171          * we need to specify a long timeout time.
1172          */
1173         status = rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE,
1174                                              0, USB_MODE_FIRMWARE,
1175                                              REGISTER_TIMEOUT_FIRMWARE);
1176         if (status < 0) {
1177                 ERROR(rt2x00dev, "Failed to write Firmware to device.\n");
1178                 return status;
1179         }
1180
1181         return 0;
1182 }
1183
1184 /*
1185  * Initialization functions.
1186  */
1187 static int rt73usb_init_registers(struct rt2x00_dev *rt2x00dev)
1188 {
1189         u32 reg;
1190
1191         rt73usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
1192         rt2x00_set_field32(&reg, TXRX_CSR0_AUTO_TX_SEQ, 1);
1193         rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX, 0);
1194         rt2x00_set_field32(&reg, TXRX_CSR0_TX_WITHOUT_WAITING, 0);
1195         rt73usb_register_write(rt2x00dev, TXRX_CSR0, reg);
1196
1197         rt73usb_register_read(rt2x00dev, TXRX_CSR1, &reg);
1198         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0, 47); /* CCK Signal */
1199         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0_VALID, 1);
1200         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1, 30); /* Rssi */
1201         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1_VALID, 1);
1202         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2, 42); /* OFDM Rate */
1203         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2_VALID, 1);
1204         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3, 30); /* Rssi */
1205         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3_VALID, 1);
1206         rt73usb_register_write(rt2x00dev, TXRX_CSR1, reg);
1207
1208         /*
1209          * CCK TXD BBP registers
1210          */
1211         rt73usb_register_read(rt2x00dev, TXRX_CSR2, &reg);
1212         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0, 13);
1213         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0_VALID, 1);
1214         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1, 12);
1215         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1_VALID, 1);
1216         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2, 11);
1217         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2_VALID, 1);
1218         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3, 10);
1219         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3_VALID, 1);
1220         rt73usb_register_write(rt2x00dev, TXRX_CSR2, reg);
1221
1222         /*
1223          * OFDM TXD BBP registers
1224          */
1225         rt73usb_register_read(rt2x00dev, TXRX_CSR3, &reg);
1226         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0, 7);
1227         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0_VALID, 1);
1228         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1, 6);
1229         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1_VALID, 1);
1230         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2, 5);
1231         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2_VALID, 1);
1232         rt73usb_register_write(rt2x00dev, TXRX_CSR3, reg);
1233
1234         rt73usb_register_read(rt2x00dev, TXRX_CSR7, &reg);
1235         rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_6MBS, 59);
1236         rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_9MBS, 53);
1237         rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_12MBS, 49);
1238         rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_18MBS, 46);
1239         rt73usb_register_write(rt2x00dev, TXRX_CSR7, reg);
1240
1241         rt73usb_register_read(rt2x00dev, TXRX_CSR8, &reg);
1242         rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_24MBS, 44);
1243         rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_36MBS, 42);
1244         rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_48MBS, 42);
1245         rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_54MBS, 42);
1246         rt73usb_register_write(rt2x00dev, TXRX_CSR8, reg);
1247
1248         rt73usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
1249         rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL, 0);
1250         rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 0);
1251         rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, 0);
1252         rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 0);
1253         rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
1254         rt2x00_set_field32(&reg, TXRX_CSR9_TIMESTAMP_COMPENSATE, 0);
1255         rt73usb_register_write(rt2x00dev, TXRX_CSR9, reg);
1256
1257         rt73usb_register_write(rt2x00dev, TXRX_CSR15, 0x0000000f);
1258
1259         rt73usb_register_read(rt2x00dev, MAC_CSR6, &reg);
1260         rt2x00_set_field32(&reg, MAC_CSR6_MAX_FRAME_UNIT, 0xfff);
1261         rt73usb_register_write(rt2x00dev, MAC_CSR6, reg);
1262
1263         rt73usb_register_write(rt2x00dev, MAC_CSR10, 0x00000718);
1264
1265         if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
1266                 return -EBUSY;
1267
1268         rt73usb_register_write(rt2x00dev, MAC_CSR13, 0x00007f00);
1269
1270         /*
1271          * Invalidate all Shared Keys (SEC_CSR0),
1272          * and clear the Shared key Cipher algorithms (SEC_CSR1 & SEC_CSR5)
1273          */
1274         rt73usb_register_write(rt2x00dev, SEC_CSR0, 0x00000000);
1275         rt73usb_register_write(rt2x00dev, SEC_CSR1, 0x00000000);
1276         rt73usb_register_write(rt2x00dev, SEC_CSR5, 0x00000000);
1277
1278         reg = 0x000023b0;
1279         if (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
1280             rt2x00_rf(&rt2x00dev->chip, RF2527))
1281                 rt2x00_set_field32(&reg, PHY_CSR1_RF_RPI, 1);
1282         rt73usb_register_write(rt2x00dev, PHY_CSR1, reg);
1283
1284         rt73usb_register_write(rt2x00dev, PHY_CSR5, 0x00040a06);
1285         rt73usb_register_write(rt2x00dev, PHY_CSR6, 0x00080606);
1286         rt73usb_register_write(rt2x00dev, PHY_CSR7, 0x00000408);
1287
1288         rt73usb_register_read(rt2x00dev, MAC_CSR9, &reg);
1289         rt2x00_set_field32(&reg, MAC_CSR9_CW_SELECT, 0);
1290         rt73usb_register_write(rt2x00dev, MAC_CSR9, reg);
1291
1292         /*
1293          * Clear all beacons
1294          * For the Beacon base registers we only need to clear
1295          * the first byte since that byte contains the VALID and OWNER
1296          * bits which (when set to 0) will invalidate the entire beacon.
1297          */
1298         rt73usb_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
1299         rt73usb_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
1300         rt73usb_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
1301         rt73usb_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
1302
1303         /*
1304          * We must clear the error counters.
1305          * These registers are cleared on read,
1306          * so we may pass a useless variable to store the value.
1307          */
1308         rt73usb_register_read(rt2x00dev, STA_CSR0, &reg);
1309         rt73usb_register_read(rt2x00dev, STA_CSR1, &reg);
1310         rt73usb_register_read(rt2x00dev, STA_CSR2, &reg);
1311
1312         /*
1313          * Reset MAC and BBP registers.
1314          */
1315         rt73usb_register_read(rt2x00dev, MAC_CSR1, &reg);
1316         rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 1);
1317         rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 1);
1318         rt73usb_register_write(rt2x00dev, MAC_CSR1, reg);
1319
1320         rt73usb_register_read(rt2x00dev, MAC_CSR1, &reg);
1321         rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 0);
1322         rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 0);
1323         rt73usb_register_write(rt2x00dev, MAC_CSR1, reg);
1324
1325         rt73usb_register_read(rt2x00dev, MAC_CSR1, &reg);
1326         rt2x00_set_field32(&reg, MAC_CSR1_HOST_READY, 1);
1327         rt73usb_register_write(rt2x00dev, MAC_CSR1, reg);
1328
1329         return 0;
1330 }
1331
1332 static int rt73usb_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
1333 {
1334         unsigned int i;
1335         u8 value;
1336
1337         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1338                 rt73usb_bbp_read(rt2x00dev, 0, &value);
1339                 if ((value != 0xff) && (value != 0x00))
1340                         return 0;
1341                 udelay(REGISTER_BUSY_DELAY);
1342         }
1343
1344         ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1345         return -EACCES;
1346 }
1347
1348 static int rt73usb_init_bbp(struct rt2x00_dev *rt2x00dev)
1349 {
1350         unsigned int i;
1351         u16 eeprom;
1352         u8 reg_id;
1353         u8 value;
1354
1355         if (unlikely(rt73usb_wait_bbp_ready(rt2x00dev)))
1356                 return -EACCES;
1357
1358         rt73usb_bbp_write(rt2x00dev, 3, 0x80);
1359         rt73usb_bbp_write(rt2x00dev, 15, 0x30);
1360         rt73usb_bbp_write(rt2x00dev, 21, 0xc8);
1361         rt73usb_bbp_write(rt2x00dev, 22, 0x38);
1362         rt73usb_bbp_write(rt2x00dev, 23, 0x06);
1363         rt73usb_bbp_write(rt2x00dev, 24, 0xfe);
1364         rt73usb_bbp_write(rt2x00dev, 25, 0x0a);
1365         rt73usb_bbp_write(rt2x00dev, 26, 0x0d);
1366         rt73usb_bbp_write(rt2x00dev, 32, 0x0b);
1367         rt73usb_bbp_write(rt2x00dev, 34, 0x12);
1368         rt73usb_bbp_write(rt2x00dev, 37, 0x07);
1369         rt73usb_bbp_write(rt2x00dev, 39, 0xf8);
1370         rt73usb_bbp_write(rt2x00dev, 41, 0x60);
1371         rt73usb_bbp_write(rt2x00dev, 53, 0x10);
1372         rt73usb_bbp_write(rt2x00dev, 54, 0x18);
1373         rt73usb_bbp_write(rt2x00dev, 60, 0x10);
1374         rt73usb_bbp_write(rt2x00dev, 61, 0x04);
1375         rt73usb_bbp_write(rt2x00dev, 62, 0x04);
1376         rt73usb_bbp_write(rt2x00dev, 75, 0xfe);
1377         rt73usb_bbp_write(rt2x00dev, 86, 0xfe);
1378         rt73usb_bbp_write(rt2x00dev, 88, 0xfe);
1379         rt73usb_bbp_write(rt2x00dev, 90, 0x0f);
1380         rt73usb_bbp_write(rt2x00dev, 99, 0x00);
1381         rt73usb_bbp_write(rt2x00dev, 102, 0x16);
1382         rt73usb_bbp_write(rt2x00dev, 107, 0x04);
1383
1384         for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1385                 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1386
1387                 if (eeprom != 0xffff && eeprom != 0x0000) {
1388                         reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1389                         value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
1390                         rt73usb_bbp_write(rt2x00dev, reg_id, value);
1391                 }
1392         }
1393
1394         return 0;
1395 }
1396
1397 /*
1398  * Device state switch handlers.
1399  */
1400 static void rt73usb_toggle_rx(struct rt2x00_dev *rt2x00dev,
1401                               enum dev_state state)
1402 {
1403         u32 reg;
1404
1405         rt73usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
1406         rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX,
1407                            (state == STATE_RADIO_RX_OFF) ||
1408                            (state == STATE_RADIO_RX_OFF_LINK));
1409         rt73usb_register_write(rt2x00dev, TXRX_CSR0, reg);
1410 }
1411
1412 static int rt73usb_enable_radio(struct rt2x00_dev *rt2x00dev)
1413 {
1414         /*
1415          * Initialize all registers.
1416          */
1417         if (unlikely(rt73usb_init_registers(rt2x00dev) ||
1418                      rt73usb_init_bbp(rt2x00dev)))
1419                 return -EIO;
1420
1421         return 0;
1422 }
1423
1424 static void rt73usb_disable_radio(struct rt2x00_dev *rt2x00dev)
1425 {
1426         rt73usb_register_write(rt2x00dev, MAC_CSR10, 0x00001818);
1427
1428         /*
1429          * Disable synchronisation.
1430          */
1431         rt73usb_register_write(rt2x00dev, TXRX_CSR9, 0);
1432
1433         rt2x00usb_disable_radio(rt2x00dev);
1434 }
1435
1436 static int rt73usb_set_state(struct rt2x00_dev *rt2x00dev, enum dev_state state)
1437 {
1438         u32 reg;
1439         unsigned int i;
1440         char put_to_sleep;
1441
1442         put_to_sleep = (state != STATE_AWAKE);
1443
1444         rt73usb_register_read(rt2x00dev, MAC_CSR12, &reg);
1445         rt2x00_set_field32(&reg, MAC_CSR12_FORCE_WAKEUP, !put_to_sleep);
1446         rt2x00_set_field32(&reg, MAC_CSR12_PUT_TO_SLEEP, put_to_sleep);
1447         rt73usb_register_write(rt2x00dev, MAC_CSR12, reg);
1448
1449         /*
1450          * Device is not guaranteed to be in the requested state yet.
1451          * We must wait until the register indicates that the
1452          * device has entered the correct state.
1453          */
1454         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1455                 rt73usb_register_read(rt2x00dev, MAC_CSR12, &reg);
1456                 state = rt2x00_get_field32(reg, MAC_CSR12_BBP_CURRENT_STATE);
1457                 if (state == !put_to_sleep)
1458                         return 0;
1459                 msleep(10);
1460         }
1461
1462         return -EBUSY;
1463 }
1464
1465 static int rt73usb_set_device_state(struct rt2x00_dev *rt2x00dev,
1466                                     enum dev_state state)
1467 {
1468         int retval = 0;
1469
1470         switch (state) {
1471         case STATE_RADIO_ON:
1472                 retval = rt73usb_enable_radio(rt2x00dev);
1473                 break;
1474         case STATE_RADIO_OFF:
1475                 rt73usb_disable_radio(rt2x00dev);
1476                 break;
1477         case STATE_RADIO_RX_ON:
1478         case STATE_RADIO_RX_ON_LINK:
1479         case STATE_RADIO_RX_OFF:
1480         case STATE_RADIO_RX_OFF_LINK:
1481                 rt73usb_toggle_rx(rt2x00dev, state);
1482                 break;
1483         case STATE_RADIO_IRQ_ON:
1484         case STATE_RADIO_IRQ_OFF:
1485                 /* No support, but no error either */
1486                 break;
1487         case STATE_DEEP_SLEEP:
1488         case STATE_SLEEP:
1489         case STATE_STANDBY:
1490         case STATE_AWAKE:
1491                 retval = rt73usb_set_state(rt2x00dev, state);
1492                 break;
1493         default:
1494                 retval = -ENOTSUPP;
1495                 break;
1496         }
1497
1498         if (unlikely(retval))
1499                 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
1500                       state, retval);
1501
1502         return retval;
1503 }
1504
1505 /*
1506  * TX descriptor initialization
1507  */
1508 static void rt73usb_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1509                                   struct sk_buff *skb,
1510                                   struct txentry_desc *txdesc)
1511 {
1512         struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
1513         __le32 *txd = skbdesc->desc;
1514         u32 word;
1515
1516         /*
1517          * Start writing the descriptor words.
1518          */
1519         rt2x00_desc_read(txd, 1, &word);
1520         rt2x00_set_field32(&word, TXD_W1_HOST_Q_ID, txdesc->queue);
1521         rt2x00_set_field32(&word, TXD_W1_AIFSN, txdesc->aifs);
1522         rt2x00_set_field32(&word, TXD_W1_CWMIN, txdesc->cw_min);
1523         rt2x00_set_field32(&word, TXD_W1_CWMAX, txdesc->cw_max);
1524         rt2x00_set_field32(&word, TXD_W1_IV_OFFSET, txdesc->iv_offset);
1525         rt2x00_set_field32(&word, TXD_W1_HW_SEQUENCE,
1526                            test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
1527         rt2x00_desc_write(txd, 1, word);
1528
1529         rt2x00_desc_read(txd, 2, &word);
1530         rt2x00_set_field32(&word, TXD_W2_PLCP_SIGNAL, txdesc->signal);
1531         rt2x00_set_field32(&word, TXD_W2_PLCP_SERVICE, txdesc->service);
1532         rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_LOW, txdesc->length_low);
1533         rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_HIGH, txdesc->length_high);
1534         rt2x00_desc_write(txd, 2, word);
1535
1536         if (test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags)) {
1537                 _rt2x00_desc_write(txd, 3, skbdesc->iv);
1538                 _rt2x00_desc_write(txd, 4, skbdesc->eiv);
1539         }
1540
1541         rt2x00_desc_read(txd, 5, &word);
1542         rt2x00_set_field32(&word, TXD_W5_TX_POWER,
1543                            TXPOWER_TO_DEV(rt2x00dev->tx_power));
1544         rt2x00_set_field32(&word, TXD_W5_WAITING_DMA_DONE_INT, 1);
1545         rt2x00_desc_write(txd, 5, word);
1546
1547         rt2x00_desc_read(txd, 0, &word);
1548         rt2x00_set_field32(&word, TXD_W0_BURST,
1549                            test_bit(ENTRY_TXD_BURST, &txdesc->flags));
1550         rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1551         rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
1552                            test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
1553         rt2x00_set_field32(&word, TXD_W0_ACK,
1554                            test_bit(ENTRY_TXD_ACK, &txdesc->flags));
1555         rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
1556                            test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
1557         rt2x00_set_field32(&word, TXD_W0_OFDM,
1558                            test_bit(ENTRY_TXD_OFDM_RATE, &txdesc->flags));
1559         rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
1560         rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1561                            test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags));
1562         rt2x00_set_field32(&word, TXD_W0_TKIP_MIC,
1563                            test_bit(ENTRY_TXD_ENCRYPT_MMIC, &txdesc->flags));
1564         rt2x00_set_field32(&word, TXD_W0_KEY_TABLE,
1565                            test_bit(ENTRY_TXD_ENCRYPT_PAIRWISE, &txdesc->flags));
1566         rt2x00_set_field32(&word, TXD_W0_KEY_INDEX, txdesc->key_idx);
1567         rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, skb->len);
1568         rt2x00_set_field32(&word, TXD_W0_BURST2,
1569                            test_bit(ENTRY_TXD_BURST, &txdesc->flags));
1570         rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, txdesc->cipher);
1571         rt2x00_desc_write(txd, 0, word);
1572 }
1573
1574 /*
1575  * TX data initialization
1576  */
1577 static void rt73usb_write_beacon(struct queue_entry *entry)
1578 {
1579         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1580         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1581         unsigned int beacon_base;
1582         u32 reg;
1583
1584         /*
1585          * Add the descriptor in front of the skb.
1586          */
1587         skb_push(entry->skb, entry->queue->desc_size);
1588         memcpy(entry->skb->data, skbdesc->desc, skbdesc->desc_len);
1589         skbdesc->desc = entry->skb->data;
1590
1591         /*
1592          * Disable beaconing while we are reloading the beacon data,
1593          * otherwise we might be sending out invalid data.
1594          */
1595         rt73usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
1596         rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 0);
1597         rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 0);
1598         rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
1599         rt73usb_register_write(rt2x00dev, TXRX_CSR9, reg);
1600
1601         /*
1602          * Write entire beacon with descriptor to register.
1603          */
1604         beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
1605         rt2x00usb_vendor_request_large_buff(rt2x00dev, USB_MULTI_WRITE,
1606                                             USB_VENDOR_REQUEST_OUT, beacon_base,
1607                                             entry->skb->data, entry->skb->len,
1608                                             REGISTER_TIMEOUT32(entry->skb->len));
1609
1610         /*
1611          * Clean up the beacon skb.
1612          */
1613         dev_kfree_skb(entry->skb);
1614         entry->skb = NULL;
1615 }
1616
1617 static int rt73usb_get_tx_data_len(struct rt2x00_dev *rt2x00dev,
1618                                    struct sk_buff *skb)
1619 {
1620         int length;
1621
1622         /*
1623          * The length _must_ be a multiple of 4,
1624          * but it must _not_ be a multiple of the USB packet size.
1625          */
1626         length = roundup(skb->len, 4);
1627         length += (4 * !(length % rt2x00dev->usb_maxpacket));
1628
1629         return length;
1630 }
1631
1632 static void rt73usb_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
1633                                   const enum data_queue_qid queue)
1634 {
1635         u32 reg;
1636
1637         if (queue != QID_BEACON) {
1638                 rt2x00usb_kick_tx_queue(rt2x00dev, queue);
1639                 return;
1640         }
1641
1642         /*
1643          * For Wi-Fi faily generated beacons between participating stations.
1644          * Set TBTT phase adaptive adjustment step to 8us (default 16us)
1645          */
1646         rt73usb_register_write(rt2x00dev, TXRX_CSR10, 0x00001008);
1647
1648         rt73usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
1649         if (!rt2x00_get_field32(reg, TXRX_CSR9_BEACON_GEN)) {
1650                 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
1651                 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1);
1652                 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 1);
1653                 rt73usb_register_write(rt2x00dev, TXRX_CSR9, reg);
1654         }
1655 }
1656
1657 /*
1658  * RX control handlers
1659  */
1660 static int rt73usb_agc_to_rssi(struct rt2x00_dev *rt2x00dev, int rxd_w1)
1661 {
1662         u8 offset = rt2x00dev->lna_gain;
1663         u8 lna;
1664
1665         lna = rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_LNA);
1666         switch (lna) {
1667         case 3:
1668                 offset += 90;
1669                 break;
1670         case 2:
1671                 offset += 74;
1672                 break;
1673         case 1:
1674                 offset += 64;
1675                 break;
1676         default:
1677                 return 0;
1678         }
1679
1680         if (rt2x00dev->rx_status.band == IEEE80211_BAND_5GHZ) {
1681                 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) {
1682                         if (lna == 3 || lna == 2)
1683                                 offset += 10;
1684                 } else {
1685                         if (lna == 3)
1686                                 offset += 6;
1687                         else if (lna == 2)
1688                                 offset += 8;
1689                 }
1690         }
1691
1692         return rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_AGC) * 2 - offset;
1693 }
1694
1695 static void rt73usb_fill_rxdone(struct queue_entry *entry,
1696                                 struct rxdone_entry_desc *rxdesc)
1697 {
1698         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1699         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1700         __le32 *rxd = (__le32 *)entry->skb->data;
1701         u32 word0;
1702         u32 word1;
1703
1704         /*
1705          * Copy descriptor to the skbdesc->desc buffer, making it safe from moving of
1706          * frame data in rt2x00usb.
1707          */
1708         memcpy(skbdesc->desc, rxd, skbdesc->desc_len);
1709         rxd = (__le32 *)skbdesc->desc;
1710
1711         /*
1712          * It is now safe to read the descriptor on all architectures.
1713          */
1714         rt2x00_desc_read(rxd, 0, &word0);
1715         rt2x00_desc_read(rxd, 1, &word1);
1716
1717         if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
1718                 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
1719
1720         if (test_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags)) {
1721                 rxdesc->cipher =
1722                     rt2x00_get_field32(word0, RXD_W0_CIPHER_ALG);
1723                 rxdesc->cipher_status =
1724                     rt2x00_get_field32(word0, RXD_W0_CIPHER_ERROR);
1725         }
1726
1727         if (rxdesc->cipher != CIPHER_NONE) {
1728                 _rt2x00_desc_read(rxd, 2, &rxdesc->iv);
1729                 _rt2x00_desc_read(rxd, 3, &rxdesc->eiv);
1730                 _rt2x00_desc_read(rxd, 4, &rxdesc->icv);
1731
1732                 /*
1733                  * Hardware has stripped IV/EIV data from 802.11 frame during
1734                  * decryption. It has provided the data seperately but rt2x00lib
1735                  * should decide if it should be reinserted.
1736                  */
1737                 rxdesc->flags |= RX_FLAG_IV_STRIPPED;
1738
1739                 /*
1740                  * FIXME: Legacy driver indicates that the frame does
1741                  * contain the Michael Mic. Unfortunately, in rt2x00
1742                  * the MIC seems to be missing completely...
1743                  */
1744                 rxdesc->flags |= RX_FLAG_MMIC_STRIPPED;
1745
1746                 if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS)
1747                         rxdesc->flags |= RX_FLAG_DECRYPTED;
1748                 else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC)
1749                         rxdesc->flags |= RX_FLAG_MMIC_ERROR;
1750         }
1751
1752         /*
1753          * Obtain the status about this packet.
1754          * When frame was received with an OFDM bitrate,
1755          * the signal is the PLCP value. If it was received with
1756          * a CCK bitrate the signal is the rate in 100kbit/s.
1757          */
1758         rxdesc->signal = rt2x00_get_field32(word1, RXD_W1_SIGNAL);
1759         rxdesc->rssi = rt73usb_agc_to_rssi(rt2x00dev, word1);
1760         rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
1761
1762         if (rt2x00_get_field32(word0, RXD_W0_OFDM))
1763                 rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP;
1764         else
1765                 rxdesc->dev_flags |= RXDONE_SIGNAL_BITRATE;
1766         if (rt2x00_get_field32(word0, RXD_W0_MY_BSS))
1767                 rxdesc->dev_flags |= RXDONE_MY_BSS;
1768
1769         /*
1770          * Set skb pointers, and update frame information.
1771          */
1772         skb_pull(entry->skb, entry->queue->desc_size);
1773         skb_trim(entry->skb, rxdesc->size);
1774 }
1775
1776 /*
1777  * Device probe functions.
1778  */
1779 static int rt73usb_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1780 {
1781         u16 word;
1782         u8 *mac;
1783         s8 value;
1784
1785         rt2x00usb_eeprom_read(rt2x00dev, rt2x00dev->eeprom, EEPROM_SIZE);
1786
1787         /*
1788          * Start validation of the data that has been read.
1789          */
1790         mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1791         if (!is_valid_ether_addr(mac)) {
1792                 random_ether_addr(mac);
1793                 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
1794         }
1795
1796         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1797         if (word == 0xffff) {
1798                 rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
1799                 rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT,
1800                                    ANTENNA_B);
1801                 rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT,
1802                                    ANTENNA_B);
1803                 rt2x00_set_field16(&word, EEPROM_ANTENNA_FRAME_TYPE, 0);
1804                 rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0);
1805                 rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0);
1806                 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF5226);
1807                 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
1808                 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
1809         }
1810
1811         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
1812         if (word == 0xffff) {
1813                 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA, 0);
1814                 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
1815                 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
1816         }
1817
1818         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &word);
1819         if (word == 0xffff) {
1820                 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_RDY_G, 0);
1821                 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_RDY_A, 0);
1822                 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_ACT, 0);
1823                 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_0, 0);
1824                 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_1, 0);
1825                 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_2, 0);
1826                 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_3, 0);
1827                 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_4, 0);
1828                 rt2x00_set_field16(&word, EEPROM_LED_LED_MODE,
1829                                    LED_MODE_DEFAULT);
1830                 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED, word);
1831                 EEPROM(rt2x00dev, "Led: 0x%04x\n", word);
1832         }
1833
1834         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
1835         if (word == 0xffff) {
1836                 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
1837                 rt2x00_set_field16(&word, EEPROM_FREQ_SEQ, 0);
1838                 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
1839                 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
1840         }
1841
1842         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &word);
1843         if (word == 0xffff) {
1844                 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
1845                 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
1846                 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
1847                 EEPROM(rt2x00dev, "RSSI OFFSET BG: 0x%04x\n", word);
1848         } else {
1849                 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_1);
1850                 if (value < -10 || value > 10)
1851                         rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
1852                 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_2);
1853                 if (value < -10 || value > 10)
1854                         rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
1855                 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
1856         }
1857
1858         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &word);
1859         if (word == 0xffff) {
1860                 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
1861                 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
1862                 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
1863                 EEPROM(rt2x00dev, "RSSI OFFSET A: 0x%04x\n", word);
1864         } else {
1865                 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_1);
1866                 if (value < -10 || value > 10)
1867                         rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
1868                 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_2);
1869                 if (value < -10 || value > 10)
1870                         rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
1871                 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
1872         }
1873
1874         return 0;
1875 }
1876
1877 static int rt73usb_init_eeprom(struct rt2x00_dev *rt2x00dev)
1878 {
1879         u32 reg;
1880         u16 value;
1881         u16 eeprom;
1882
1883         /*
1884          * Read EEPROM word for configuration.
1885          */
1886         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1887
1888         /*
1889          * Identify RF chipset.
1890          */
1891         value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1892         rt73usb_register_read(rt2x00dev, MAC_CSR0, &reg);
1893         rt2x00_set_chip(rt2x00dev, RT2571, value, reg);
1894
1895         if (!rt2x00_check_rev(&rt2x00dev->chip, 0x25730)) {
1896                 ERROR(rt2x00dev, "Invalid RT chipset detected.\n");
1897                 return -ENODEV;
1898         }
1899
1900         if (!rt2x00_rf(&rt2x00dev->chip, RF5226) &&
1901             !rt2x00_rf(&rt2x00dev->chip, RF2528) &&
1902             !rt2x00_rf(&rt2x00dev->chip, RF5225) &&
1903             !rt2x00_rf(&rt2x00dev->chip, RF2527)) {
1904                 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1905                 return -ENODEV;
1906         }
1907
1908         /*
1909          * Identify default antenna configuration.
1910          */
1911         rt2x00dev->default_ant.tx =
1912             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
1913         rt2x00dev->default_ant.rx =
1914             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1915
1916         /*
1917          * Read the Frame type.
1918          */
1919         if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_FRAME_TYPE))
1920                 __set_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags);
1921
1922         /*
1923          * Read frequency offset.
1924          */
1925         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
1926         rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
1927
1928         /*
1929          * Read external LNA informations.
1930          */
1931         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
1932
1933         if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA)) {
1934                 __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
1935                 __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
1936         }
1937
1938         /*
1939          * Store led settings, for correct led behaviour.
1940          */
1941 #ifdef CONFIG_RT2X00_LIB_LEDS
1942         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &eeprom);
1943
1944         rt73usb_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
1945         rt73usb_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
1946         if (value == LED_MODE_SIGNAL_STRENGTH)
1947                 rt73usb_init_led(rt2x00dev, &rt2x00dev->led_qual,
1948                                  LED_TYPE_QUALITY);
1949
1950         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_LED_MODE, value);
1951         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_0,
1952                            rt2x00_get_field16(eeprom,
1953                                               EEPROM_LED_POLARITY_GPIO_0));
1954         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_1,
1955                            rt2x00_get_field16(eeprom,
1956                                               EEPROM_LED_POLARITY_GPIO_1));
1957         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_2,
1958                            rt2x00_get_field16(eeprom,
1959                                               EEPROM_LED_POLARITY_GPIO_2));
1960         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_3,
1961                            rt2x00_get_field16(eeprom,
1962                                               EEPROM_LED_POLARITY_GPIO_3));
1963         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_4,
1964                            rt2x00_get_field16(eeprom,
1965                                               EEPROM_LED_POLARITY_GPIO_4));
1966         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_ACT,
1967                            rt2x00_get_field16(eeprom, EEPROM_LED_POLARITY_ACT));
1968         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_BG,
1969                            rt2x00_get_field16(eeprom,
1970                                               EEPROM_LED_POLARITY_RDY_G));
1971         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_A,
1972                            rt2x00_get_field16(eeprom,
1973                                               EEPROM_LED_POLARITY_RDY_A));
1974 #endif /* CONFIG_RT2X00_LIB_LEDS */
1975
1976         return 0;
1977 }
1978
1979 /*
1980  * RF value list for RF2528
1981  * Supports: 2.4 GHz
1982  */
1983 static const struct rf_channel rf_vals_bg_2528[] = {
1984         { 1,  0x00002c0c, 0x00000786, 0x00068255, 0x000fea0b },
1985         { 2,  0x00002c0c, 0x00000786, 0x00068255, 0x000fea1f },
1986         { 3,  0x00002c0c, 0x0000078a, 0x00068255, 0x000fea0b },
1987         { 4,  0x00002c0c, 0x0000078a, 0x00068255, 0x000fea1f },
1988         { 5,  0x00002c0c, 0x0000078e, 0x00068255, 0x000fea0b },
1989         { 6,  0x00002c0c, 0x0000078e, 0x00068255, 0x000fea1f },
1990         { 7,  0x00002c0c, 0x00000792, 0x00068255, 0x000fea0b },
1991         { 8,  0x00002c0c, 0x00000792, 0x00068255, 0x000fea1f },
1992         { 9,  0x00002c0c, 0x00000796, 0x00068255, 0x000fea0b },
1993         { 10, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea1f },
1994         { 11, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea0b },
1995         { 12, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea1f },
1996         { 13, 0x00002c0c, 0x0000079e, 0x00068255, 0x000fea0b },
1997         { 14, 0x00002c0c, 0x000007a2, 0x00068255, 0x000fea13 },
1998 };
1999
2000 /*
2001  * RF value list for RF5226
2002  * Supports: 2.4 GHz & 5.2 GHz
2003  */
2004 static const struct rf_channel rf_vals_5226[] = {
2005         { 1,  0x00002c0c, 0x00000786, 0x00068255, 0x000fea0b },
2006         { 2,  0x00002c0c, 0x00000786, 0x00068255, 0x000fea1f },
2007         { 3,  0x00002c0c, 0x0000078a, 0x00068255, 0x000fea0b },
2008         { 4,  0x00002c0c, 0x0000078a, 0x00068255, 0x000fea1f },
2009         { 5,  0x00002c0c, 0x0000078e, 0x00068255, 0x000fea0b },
2010         { 6,  0x00002c0c, 0x0000078e, 0x00068255, 0x000fea1f },
2011         { 7,  0x00002c0c, 0x00000792, 0x00068255, 0x000fea0b },
2012         { 8,  0x00002c0c, 0x00000792, 0x00068255, 0x000fea1f },
2013         { 9,  0x00002c0c, 0x00000796, 0x00068255, 0x000fea0b },
2014         { 10, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea1f },
2015         { 11, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea0b },
2016         { 12, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea1f },
2017         { 13, 0x00002c0c, 0x0000079e, 0x00068255, 0x000fea0b },
2018         { 14, 0x00002c0c, 0x000007a2, 0x00068255, 0x000fea13 },
2019
2020         /* 802.11 UNI / HyperLan 2 */
2021         { 36, 0x00002c0c, 0x0000099a, 0x00098255, 0x000fea23 },
2022         { 40, 0x00002c0c, 0x000009a2, 0x00098255, 0x000fea03 },
2023         { 44, 0x00002c0c, 0x000009a6, 0x00098255, 0x000fea0b },
2024         { 48, 0x00002c0c, 0x000009aa, 0x00098255, 0x000fea13 },
2025         { 52, 0x00002c0c, 0x000009ae, 0x00098255, 0x000fea1b },
2026         { 56, 0x00002c0c, 0x000009b2, 0x00098255, 0x000fea23 },
2027         { 60, 0x00002c0c, 0x000009ba, 0x00098255, 0x000fea03 },
2028         { 64, 0x00002c0c, 0x000009be, 0x00098255, 0x000fea0b },
2029
2030         /* 802.11 HyperLan 2 */
2031         { 100, 0x00002c0c, 0x00000a2a, 0x000b8255, 0x000fea03 },
2032         { 104, 0x00002c0c, 0x00000a2e, 0x000b8255, 0x000fea0b },
2033         { 108, 0x00002c0c, 0x00000a32, 0x000b8255, 0x000fea13 },
2034         { 112, 0x00002c0c, 0x00000a36, 0x000b8255, 0x000fea1b },
2035         { 116, 0x00002c0c, 0x00000a3a, 0x000b8255, 0x000fea23 },
2036         { 120, 0x00002c0c, 0x00000a82, 0x000b8255, 0x000fea03 },
2037         { 124, 0x00002c0c, 0x00000a86, 0x000b8255, 0x000fea0b },
2038         { 128, 0x00002c0c, 0x00000a8a, 0x000b8255, 0x000fea13 },
2039         { 132, 0x00002c0c, 0x00000a8e, 0x000b8255, 0x000fea1b },
2040         { 136, 0x00002c0c, 0x00000a92, 0x000b8255, 0x000fea23 },
2041
2042         /* 802.11 UNII */
2043         { 140, 0x00002c0c, 0x00000a9a, 0x000b8255, 0x000fea03 },
2044         { 149, 0x00002c0c, 0x00000aa2, 0x000b8255, 0x000fea1f },
2045         { 153, 0x00002c0c, 0x00000aa6, 0x000b8255, 0x000fea27 },
2046         { 157, 0x00002c0c, 0x00000aae, 0x000b8255, 0x000fea07 },
2047         { 161, 0x00002c0c, 0x00000ab2, 0x000b8255, 0x000fea0f },
2048         { 165, 0x00002c0c, 0x00000ab6, 0x000b8255, 0x000fea17 },
2049
2050         /* MMAC(Japan)J52 ch 34,38,42,46 */
2051         { 34, 0x00002c0c, 0x0008099a, 0x000da255, 0x000d3a0b },
2052         { 38, 0x00002c0c, 0x0008099e, 0x000da255, 0x000d3a13 },
2053         { 42, 0x00002c0c, 0x000809a2, 0x000da255, 0x000d3a1b },
2054         { 46, 0x00002c0c, 0x000809a6, 0x000da255, 0x000d3a23 },
2055 };
2056
2057 /*
2058  * RF value list for RF5225 & RF2527
2059  * Supports: 2.4 GHz & 5.2 GHz
2060  */
2061 static const struct rf_channel rf_vals_5225_2527[] = {
2062         { 1,  0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
2063         { 2,  0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
2064         { 3,  0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
2065         { 4,  0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
2066         { 5,  0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
2067         { 6,  0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
2068         { 7,  0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
2069         { 8,  0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
2070         { 9,  0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
2071         { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
2072         { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
2073         { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
2074         { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
2075         { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
2076
2077         /* 802.11 UNI / HyperLan 2 */
2078         { 36, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa23 },
2079         { 40, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa03 },
2080         { 44, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa0b },
2081         { 48, 0x00002ccc, 0x000049aa, 0x0009be55, 0x000ffa13 },
2082         { 52, 0x00002ccc, 0x000049ae, 0x0009ae55, 0x000ffa1b },
2083         { 56, 0x00002ccc, 0x000049b2, 0x0009ae55, 0x000ffa23 },
2084         { 60, 0x00002ccc, 0x000049ba, 0x0009ae55, 0x000ffa03 },
2085         { 64, 0x00002ccc, 0x000049be, 0x0009ae55, 0x000ffa0b },
2086
2087         /* 802.11 HyperLan 2 */
2088         { 100, 0x00002ccc, 0x00004a2a, 0x000bae55, 0x000ffa03 },
2089         { 104, 0x00002ccc, 0x00004a2e, 0x000bae55, 0x000ffa0b },
2090         { 108, 0x00002ccc, 0x00004a32, 0x000bae55, 0x000ffa13 },
2091         { 112, 0x00002ccc, 0x00004a36, 0x000bae55, 0x000ffa1b },
2092         { 116, 0x00002ccc, 0x00004a3a, 0x000bbe55, 0x000ffa23 },
2093         { 120, 0x00002ccc, 0x00004a82, 0x000bbe55, 0x000ffa03 },
2094         { 124, 0x00002ccc, 0x00004a86, 0x000bbe55, 0x000ffa0b },
2095         { 128, 0x00002ccc, 0x00004a8a, 0x000bbe55, 0x000ffa13 },
2096         { 132, 0x00002ccc, 0x00004a8e, 0x000bbe55, 0x000ffa1b },
2097         { 136, 0x00002ccc, 0x00004a92, 0x000bbe55, 0x000ffa23 },
2098
2099         /* 802.11 UNII */
2100         { 140, 0x00002ccc, 0x00004a9a, 0x000bbe55, 0x000ffa03 },
2101         { 149, 0x00002ccc, 0x00004aa2, 0x000bbe55, 0x000ffa1f },
2102         { 153, 0x00002ccc, 0x00004aa6, 0x000bbe55, 0x000ffa27 },
2103         { 157, 0x00002ccc, 0x00004aae, 0x000bbe55, 0x000ffa07 },
2104         { 161, 0x00002ccc, 0x00004ab2, 0x000bbe55, 0x000ffa0f },
2105         { 165, 0x00002ccc, 0x00004ab6, 0x000bbe55, 0x000ffa17 },
2106
2107         /* MMAC(Japan)J52 ch 34,38,42,46 */
2108         { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa0b },
2109         { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000ffa13 },
2110         { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa1b },
2111         { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa23 },
2112 };
2113
2114
2115 static int rt73usb_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
2116 {
2117         struct hw_mode_spec *spec = &rt2x00dev->spec;
2118         struct channel_info *info;
2119         char *tx_power;
2120         unsigned int i;
2121
2122         /*
2123          * Initialize all hw fields.
2124          */
2125         rt2x00dev->hw->flags =
2126             IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
2127             IEEE80211_HW_SIGNAL_DBM;
2128         rt2x00dev->hw->extra_tx_headroom = TXD_DESC_SIZE;
2129
2130         SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
2131         SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
2132                                 rt2x00_eeprom_addr(rt2x00dev,
2133                                                    EEPROM_MAC_ADDR_0));
2134
2135         /*
2136          * Initialize hw_mode information.
2137          */
2138         spec->supported_bands = SUPPORT_BAND_2GHZ;
2139         spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
2140
2141         if (rt2x00_rf(&rt2x00dev->chip, RF2528)) {
2142                 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2528);
2143                 spec->channels = rf_vals_bg_2528;
2144         } else if (rt2x00_rf(&rt2x00dev->chip, RF5226)) {
2145                 spec->supported_bands |= SUPPORT_BAND_5GHZ;
2146                 spec->num_channels = ARRAY_SIZE(rf_vals_5226);
2147                 spec->channels = rf_vals_5226;
2148         } else if (rt2x00_rf(&rt2x00dev->chip, RF2527)) {
2149                 spec->num_channels = 14;
2150                 spec->channels = rf_vals_5225_2527;
2151         } else if (rt2x00_rf(&rt2x00dev->chip, RF5225)) {
2152                 spec->supported_bands |= SUPPORT_BAND_5GHZ;
2153                 spec->num_channels = ARRAY_SIZE(rf_vals_5225_2527);
2154                 spec->channels = rf_vals_5225_2527;
2155         }
2156
2157         /*
2158          * Create channel information array
2159          */
2160         info = kzalloc(spec->num_channels * sizeof(*info), GFP_KERNEL);
2161         if (!info)
2162                 return -ENOMEM;
2163
2164         spec->channels_info = info;
2165
2166         tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_G_START);
2167         for (i = 0; i < 14; i++)
2168                 info[i].tx_power1 = TXPOWER_FROM_DEV(tx_power[i]);
2169
2170         if (spec->num_channels > 14) {
2171                 tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A_START);
2172                 for (i = 14; i < spec->num_channels; i++)
2173                         info[i].tx_power1 = TXPOWER_FROM_DEV(tx_power[i]);
2174         }
2175
2176         return 0;
2177 }
2178
2179 static int rt73usb_probe_hw(struct rt2x00_dev *rt2x00dev)
2180 {
2181         int retval;
2182
2183         /*
2184          * Allocate eeprom data.
2185          */
2186         retval = rt73usb_validate_eeprom(rt2x00dev);
2187         if (retval)
2188                 return retval;
2189
2190         retval = rt73usb_init_eeprom(rt2x00dev);
2191         if (retval)
2192                 return retval;
2193
2194         /*
2195          * Initialize hw specifications.
2196          */
2197         retval = rt73usb_probe_hw_mode(rt2x00dev);
2198         if (retval)
2199                 return retval;
2200
2201         /*
2202          * This device requires firmware.
2203          */
2204         __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
2205         __set_bit(DRIVER_REQUIRE_SCHEDULED, &rt2x00dev->flags);
2206         if (!modparam_nohwcrypt)
2207                 __set_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags);
2208
2209         /*
2210          * Set the rssi offset.
2211          */
2212         rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
2213
2214         return 0;
2215 }
2216
2217 /*
2218  * IEEE80211 stack callback functions.
2219  */
2220 static int rt73usb_conf_tx(struct ieee80211_hw *hw, u16 queue_idx,
2221                            const struct ieee80211_tx_queue_params *params)
2222 {
2223         struct rt2x00_dev *rt2x00dev = hw->priv;
2224         struct data_queue *queue;
2225         struct rt2x00_field32 field;
2226         int retval;
2227         u32 reg;
2228
2229         /*
2230          * First pass the configuration through rt2x00lib, that will
2231          * update the queue settings and validate the input. After that
2232          * we are free to update the registers based on the value
2233          * in the queue parameter.
2234          */
2235         retval = rt2x00mac_conf_tx(hw, queue_idx, params);
2236         if (retval)
2237                 return retval;
2238
2239         queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
2240
2241         /* Update WMM TXOP register */
2242         if (queue_idx < 2) {
2243                 field.bit_offset = queue_idx * 16;
2244                 field.bit_mask = 0xffff << field.bit_offset;
2245
2246                 rt73usb_register_read(rt2x00dev, AC_TXOP_CSR0, &reg);
2247                 rt2x00_set_field32(&reg, field, queue->txop);
2248                 rt73usb_register_write(rt2x00dev, AC_TXOP_CSR0, reg);
2249         } else if (queue_idx < 4) {
2250                 field.bit_offset = (queue_idx - 2) * 16;
2251                 field.bit_mask = 0xffff << field.bit_offset;
2252
2253                 rt73usb_register_read(rt2x00dev, AC_TXOP_CSR1, &reg);
2254                 rt2x00_set_field32(&reg, field, queue->txop);
2255                 rt73usb_register_write(rt2x00dev, AC_TXOP_CSR1, reg);
2256         }
2257
2258         /* Update WMM registers */
2259         field.bit_offset = queue_idx * 4;
2260         field.bit_mask = 0xf << field.bit_offset;
2261
2262         rt73usb_register_read(rt2x00dev, AIFSN_CSR, &reg);
2263         rt2x00_set_field32(&reg, field, queue->aifs);
2264         rt73usb_register_write(rt2x00dev, AIFSN_CSR, reg);
2265
2266         rt73usb_register_read(rt2x00dev, CWMIN_CSR, &reg);
2267         rt2x00_set_field32(&reg, field, queue->cw_min);
2268         rt73usb_register_write(rt2x00dev, CWMIN_CSR, reg);
2269
2270         rt73usb_register_read(rt2x00dev, CWMAX_CSR, &reg);
2271         rt2x00_set_field32(&reg, field, queue->cw_max);
2272         rt73usb_register_write(rt2x00dev, CWMAX_CSR, reg);
2273
2274         return 0;
2275 }
2276
2277 #if 0
2278 /*
2279  * Mac80211 demands get_tsf must be atomic.
2280  * This is not possible for rt73usb since all register access
2281  * functions require sleeping. Untill mac80211 no longer needs
2282  * get_tsf to be atomic, this function should be disabled.
2283  */
2284 static u64 rt73usb_get_tsf(struct ieee80211_hw *hw)
2285 {
2286         struct rt2x00_dev *rt2x00dev = hw->priv;
2287         u64 tsf;
2288         u32 reg;
2289
2290         rt73usb_register_read(rt2x00dev, TXRX_CSR13, &reg);
2291         tsf = (u64) rt2x00_get_field32(reg, TXRX_CSR13_HIGH_TSFTIMER) << 32;
2292         rt73usb_register_read(rt2x00dev, TXRX_CSR12, &reg);
2293         tsf |= rt2x00_get_field32(reg, TXRX_CSR12_LOW_TSFTIMER);
2294
2295         return tsf;
2296 }
2297 #else
2298 #define rt73usb_get_tsf NULL
2299 #endif
2300
2301 static const struct ieee80211_ops rt73usb_mac80211_ops = {
2302         .tx                     = rt2x00mac_tx,
2303         .start                  = rt2x00mac_start,
2304         .stop                   = rt2x00mac_stop,
2305         .add_interface          = rt2x00mac_add_interface,
2306         .remove_interface       = rt2x00mac_remove_interface,
2307         .config                 = rt2x00mac_config,
2308         .config_interface       = rt2x00mac_config_interface,
2309         .configure_filter       = rt2x00mac_configure_filter,
2310         .set_key                = rt2x00mac_set_key,
2311         .get_stats              = rt2x00mac_get_stats,
2312         .bss_info_changed       = rt2x00mac_bss_info_changed,
2313         .conf_tx                = rt73usb_conf_tx,
2314         .get_tx_stats           = rt2x00mac_get_tx_stats,
2315         .get_tsf                = rt73usb_get_tsf,
2316 };
2317
2318 static const struct rt2x00lib_ops rt73usb_rt2x00_ops = {
2319         .probe_hw               = rt73usb_probe_hw,
2320         .get_firmware_name      = rt73usb_get_firmware_name,
2321         .get_firmware_crc       = rt73usb_get_firmware_crc,
2322         .load_firmware          = rt73usb_load_firmware,
2323         .initialize             = rt2x00usb_initialize,
2324         .uninitialize           = rt2x00usb_uninitialize,
2325         .init_rxentry           = rt2x00usb_init_rxentry,
2326         .init_txentry           = rt2x00usb_init_txentry,
2327         .set_device_state       = rt73usb_set_device_state,
2328         .link_stats             = rt73usb_link_stats,
2329         .reset_tuner            = rt73usb_reset_tuner,
2330         .link_tuner             = rt73usb_link_tuner,
2331         .write_tx_desc          = rt73usb_write_tx_desc,
2332         .write_tx_data          = rt2x00usb_write_tx_data,
2333         .write_beacon           = rt73usb_write_beacon,
2334         .get_tx_data_len        = rt73usb_get_tx_data_len,
2335         .kick_tx_queue          = rt73usb_kick_tx_queue,
2336         .fill_rxdone            = rt73usb_fill_rxdone,
2337         .config_shared_key      = rt73usb_config_shared_key,
2338         .config_pairwise_key    = rt73usb_config_pairwise_key,
2339         .config_filter          = rt73usb_config_filter,
2340         .config_intf            = rt73usb_config_intf,
2341         .config_erp             = rt73usb_config_erp,
2342         .config_ant             = rt73usb_config_ant,
2343         .config                 = rt73usb_config,
2344 };
2345
2346 static const struct data_queue_desc rt73usb_queue_rx = {
2347         .entry_num              = RX_ENTRIES,
2348         .data_size              = DATA_FRAME_SIZE,
2349         .desc_size              = RXD_DESC_SIZE,
2350         .priv_size              = sizeof(struct queue_entry_priv_usb),
2351 };
2352
2353 static const struct data_queue_desc rt73usb_queue_tx = {
2354         .entry_num              = TX_ENTRIES,
2355         .data_size              = DATA_FRAME_SIZE,
2356         .desc_size              = TXD_DESC_SIZE,
2357         .priv_size              = sizeof(struct queue_entry_priv_usb),
2358 };
2359
2360 static const struct data_queue_desc rt73usb_queue_bcn = {
2361         .entry_num              = 4 * BEACON_ENTRIES,
2362         .data_size              = MGMT_FRAME_SIZE,
2363         .desc_size              = TXINFO_SIZE,
2364         .priv_size              = sizeof(struct queue_entry_priv_usb),
2365 };
2366
2367 static const struct rt2x00_ops rt73usb_ops = {
2368         .name           = KBUILD_MODNAME,
2369         .max_sta_intf   = 1,
2370         .max_ap_intf    = 4,
2371         .eeprom_size    = EEPROM_SIZE,
2372         .rf_size        = RF_SIZE,
2373         .tx_queues      = NUM_TX_QUEUES,
2374         .rx             = &rt73usb_queue_rx,
2375         .tx             = &rt73usb_queue_tx,
2376         .bcn            = &rt73usb_queue_bcn,
2377         .lib            = &rt73usb_rt2x00_ops,
2378         .hw             = &rt73usb_mac80211_ops,
2379 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
2380         .debugfs        = &rt73usb_rt2x00debug,
2381 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
2382 };
2383
2384 /*
2385  * rt73usb module information.
2386  */
2387 static struct usb_device_id rt73usb_device_table[] = {
2388         /* AboCom */
2389         { USB_DEVICE(0x07b8, 0xb21d), USB_DEVICE_DATA(&rt73usb_ops) },
2390         /* Askey */
2391         { USB_DEVICE(0x1690, 0x0722), USB_DEVICE_DATA(&rt73usb_ops) },
2392         /* ASUS */
2393         { USB_DEVICE(0x0b05, 0x1723), USB_DEVICE_DATA(&rt73usb_ops) },
2394         { USB_DEVICE(0x0b05, 0x1724), USB_DEVICE_DATA(&rt73usb_ops) },
2395         /* Belkin */
2396         { USB_DEVICE(0x050d, 0x7050), USB_DEVICE_DATA(&rt73usb_ops) },
2397         { USB_DEVICE(0x050d, 0x705a), USB_DEVICE_DATA(&rt73usb_ops) },
2398         { USB_DEVICE(0x050d, 0x905b), USB_DEVICE_DATA(&rt73usb_ops) },
2399         { USB_DEVICE(0x050d, 0x905c), USB_DEVICE_DATA(&rt73usb_ops) },
2400         /* Billionton */
2401         { USB_DEVICE(0x1631, 0xc019), USB_DEVICE_DATA(&rt73usb_ops) },
2402         /* Buffalo */
2403         { USB_DEVICE(0x0411, 0x00f4), USB_DEVICE_DATA(&rt73usb_ops) },
2404         /* CNet */
2405         { USB_DEVICE(0x1371, 0x9022), USB_DEVICE_DATA(&rt73usb_ops) },
2406         { USB_DEVICE(0x1371, 0x9032), USB_DEVICE_DATA(&rt73usb_ops) },
2407         /* Conceptronic */
2408         { USB_DEVICE(0x14b2, 0x3c22), USB_DEVICE_DATA(&rt73usb_ops) },
2409         /* Corega */
2410         { USB_DEVICE(0x07aa, 0x002e), USB_DEVICE_DATA(&rt73usb_ops) },
2411         /* D-Link */
2412         { USB_DEVICE(0x07d1, 0x3c03), USB_DEVICE_DATA(&rt73usb_ops) },
2413         { USB_DEVICE(0x07d1, 0x3c04), USB_DEVICE_DATA(&rt73usb_ops) },
2414         { USB_DEVICE(0x07d1, 0x3c06), USB_DEVICE_DATA(&rt73usb_ops) },
2415         { USB_DEVICE(0x07d1, 0x3c07), USB_DEVICE_DATA(&rt73usb_ops) },
2416         /* Gemtek */
2417         { USB_DEVICE(0x15a9, 0x0004), USB_DEVICE_DATA(&rt73usb_ops) },
2418         /* Gigabyte */
2419         { USB_DEVICE(0x1044, 0x8008), USB_DEVICE_DATA(&rt73usb_ops) },
2420         { USB_DEVICE(0x1044, 0x800a), USB_DEVICE_DATA(&rt73usb_ops) },
2421         /* Huawei-3Com */
2422         { USB_DEVICE(0x1472, 0x0009), USB_DEVICE_DATA(&rt73usb_ops) },
2423         /* Hercules */
2424         { USB_DEVICE(0x06f8, 0xe010), USB_DEVICE_DATA(&rt73usb_ops) },
2425         { USB_DEVICE(0x06f8, 0xe020), USB_DEVICE_DATA(&rt73usb_ops) },
2426         /* Linksys */
2427         { USB_DEVICE(0x13b1, 0x0020), USB_DEVICE_DATA(&rt73usb_ops) },
2428         { USB_DEVICE(0x13b1, 0x0023), USB_DEVICE_DATA(&rt73usb_ops) },
2429         /* MSI */
2430         { USB_DEVICE(0x0db0, 0x6877), USB_DEVICE_DATA(&rt73usb_ops) },
2431         { USB_DEVICE(0x0db0, 0x6874), USB_DEVICE_DATA(&rt73usb_ops) },
2432         { USB_DEVICE(0x0db0, 0xa861), USB_DEVICE_DATA(&rt73usb_ops) },
2433         { USB_DEVICE(0x0db0, 0xa874), USB_DEVICE_DATA(&rt73usb_ops) },
2434         /* Ralink */
2435         { USB_DEVICE(0x148f, 0x2573), USB_DEVICE_DATA(&rt73usb_ops) },
2436         { USB_DEVICE(0x148f, 0x2671), USB_DEVICE_DATA(&rt73usb_ops) },
2437         /* Qcom */
2438         { USB_DEVICE(0x18e8, 0x6196), USB_DEVICE_DATA(&rt73usb_ops) },
2439         { USB_DEVICE(0x18e8, 0x6229), USB_DEVICE_DATA(&rt73usb_ops) },
2440         { USB_DEVICE(0x18e8, 0x6238), USB_DEVICE_DATA(&rt73usb_ops) },
2441         /* Senao */
2442         { USB_DEVICE(0x1740, 0x7100), USB_DEVICE_DATA(&rt73usb_ops) },
2443         /* Sitecom */
2444         { USB_DEVICE(0x0df6, 0x9712), USB_DEVICE_DATA(&rt73usb_ops) },
2445         { USB_DEVICE(0x0df6, 0x90ac), USB_DEVICE_DATA(&rt73usb_ops) },
2446         /* Surecom */
2447         { USB_DEVICE(0x0769, 0x31f3), USB_DEVICE_DATA(&rt73usb_ops) },
2448         /* Planex */
2449         { USB_DEVICE(0x2019, 0xab01), USB_DEVICE_DATA(&rt73usb_ops) },
2450         { USB_DEVICE(0x2019, 0xab50), USB_DEVICE_DATA(&rt73usb_ops) },
2451         { 0, }
2452 };
2453
2454 MODULE_AUTHOR(DRV_PROJECT);
2455 MODULE_VERSION(DRV_VERSION);
2456 MODULE_DESCRIPTION("Ralink RT73 USB Wireless LAN driver.");
2457 MODULE_SUPPORTED_DEVICE("Ralink RT2571W & RT2671 USB chipset based cards");
2458 MODULE_DEVICE_TABLE(usb, rt73usb_device_table);
2459 MODULE_FIRMWARE(FIRMWARE_RT2571);
2460 MODULE_LICENSE("GPL");
2461
2462 static struct usb_driver rt73usb_driver = {
2463         .name           = KBUILD_MODNAME,
2464         .id_table       = rt73usb_device_table,
2465         .probe          = rt2x00usb_probe,
2466         .disconnect     = rt2x00usb_disconnect,
2467         .suspend        = rt2x00usb_suspend,
2468         .resume         = rt2x00usb_resume,
2469 };
2470
2471 static int __init rt73usb_init(void)
2472 {
2473         return usb_register(&rt73usb_driver);
2474 }
2475
2476 static void __exit rt73usb_exit(void)
2477 {
2478         usb_deregister(&rt73usb_driver);
2479 }
2480
2481 module_init(rt73usb_init);
2482 module_exit(rt73usb_exit);