2 Copyright (C) 2004 - 2008 rt2x00 SourceForge Project
3 <http://rt2x00.serialmonkey.com>
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
23 Abstract: Data structures and registers for the rt73usb module.
24 Supported chipsets: rt2571W & rt2671.
40 * Defaul offset is required for RSSI <-> dBm conversion.
42 #define MAX_SIGNAL 100
44 #define DEFAULT_RSSI_OFFSET 120
47 * Register layout information.
49 #define CSR_REG_BASE 0x3000
50 #define CSR_REG_SIZE 0x04b0
51 #define EEPROM_BASE 0x0000
52 #define EEPROM_SIZE 0x0100
53 #define BBP_SIZE 0x0080
54 #define RF_SIZE 0x0014
57 * Number of TX queues.
59 #define NUM_TX_QUEUES 4
66 * MCU_LEDCS: LED control for MCU Mailbox.
68 #define MCU_LEDCS_LED_MODE FIELD16(0x001f)
69 #define MCU_LEDCS_RADIO_STATUS FIELD16(0x0020)
70 #define MCU_LEDCS_LINK_BG_STATUS FIELD16(0x0040)
71 #define MCU_LEDCS_LINK_A_STATUS FIELD16(0x0080)
72 #define MCU_LEDCS_POLARITY_GPIO_0 FIELD16(0x0100)
73 #define MCU_LEDCS_POLARITY_GPIO_1 FIELD16(0x0200)
74 #define MCU_LEDCS_POLARITY_GPIO_2 FIELD16(0x0400)
75 #define MCU_LEDCS_POLARITY_GPIO_3 FIELD16(0x0800)
76 #define MCU_LEDCS_POLARITY_GPIO_4 FIELD16(0x1000)
77 #define MCU_LEDCS_POLARITY_ACT FIELD16(0x2000)
78 #define MCU_LEDCS_POLARITY_READY_BG FIELD16(0x4000)
79 #define MCU_LEDCS_POLARITY_READY_A FIELD16(0x8000)
82 * 8051 firmware image.
84 #define FIRMWARE_RT2571 "rt73.bin"
85 #define FIRMWARE_IMAGE_BASE 0x0800
88 * Security key table memory.
89 * 16 entries 32-byte for shared key table
90 * 64 entries 32-byte for pairwise key table
91 * 64 entries 8-byte for pairwise ta key table
93 #define SHARED_KEY_TABLE_BASE 0x1000
94 #define PAIRWISE_KEY_TABLE_BASE 0x1200
95 #define PAIRWISE_TA_TABLE_BASE 0x1a00
101 } __attribute__ ((packed));
103 struct hw_pairwise_ta_entry {
106 } __attribute__ ((packed));
109 * Since NULL frame won't be that long (256 byte),
110 * We steal 16 tail bytes to save debugging settings.
112 #define HW_DEBUG_SETTING_BASE 0x2bf0
115 * On-chip BEACON frame space.
117 #define HW_BEACON_BASE0 0x2400
118 #define HW_BEACON_BASE1 0x2500
119 #define HW_BEACON_BASE2 0x2600
120 #define HW_BEACON_BASE3 0x2700
122 #define HW_BEACON_OFFSET(__index) \
123 ( HW_BEACON_BASE0 + (__index * 0x0100) )
126 * MAC Control/Status Registers(CSR).
127 * Some values are set in TU, whereas 1 TU == 1024 us.
131 * MAC_CSR0: ASIC revision number.
133 #define MAC_CSR0 0x3000
136 * MAC_CSR1: System control register.
137 * SOFT_RESET: Software reset bit, 1: reset, 0: normal.
138 * BBP_RESET: Hardware reset BBP.
139 * HOST_READY: Host is ready after initialization, 1: ready.
141 #define MAC_CSR1 0x3004
142 #define MAC_CSR1_SOFT_RESET FIELD32(0x00000001)
143 #define MAC_CSR1_BBP_RESET FIELD32(0x00000002)
144 #define MAC_CSR1_HOST_READY FIELD32(0x00000004)
147 * MAC_CSR2: STA MAC register 0.
149 #define MAC_CSR2 0x3008
150 #define MAC_CSR2_BYTE0 FIELD32(0x000000ff)
151 #define MAC_CSR2_BYTE1 FIELD32(0x0000ff00)
152 #define MAC_CSR2_BYTE2 FIELD32(0x00ff0000)
153 #define MAC_CSR2_BYTE3 FIELD32(0xff000000)
156 * MAC_CSR3: STA MAC register 1.
157 * UNICAST_TO_ME_MASK:
158 * Used to mask off bits from byte 5 of the MAC address
159 * to determine the UNICAST_TO_ME bit for RX frames.
160 * The full mask is complemented by BSS_ID_MASK:
161 * MASK = BSS_ID_MASK & UNICAST_TO_ME_MASK
163 #define MAC_CSR3 0x300c
164 #define MAC_CSR3_BYTE4 FIELD32(0x000000ff)
165 #define MAC_CSR3_BYTE5 FIELD32(0x0000ff00)
166 #define MAC_CSR3_UNICAST_TO_ME_MASK FIELD32(0x00ff0000)
169 * MAC_CSR4: BSSID register 0.
171 #define MAC_CSR4 0x3010
172 #define MAC_CSR4_BYTE0 FIELD32(0x000000ff)
173 #define MAC_CSR4_BYTE1 FIELD32(0x0000ff00)
174 #define MAC_CSR4_BYTE2 FIELD32(0x00ff0000)
175 #define MAC_CSR4_BYTE3 FIELD32(0xff000000)
178 * MAC_CSR5: BSSID register 1.
180 * This mask is used to mask off bits 0 and 1 of byte 5 of the
181 * BSSID. This will make sure that those bits will be ignored
182 * when determining the MY_BSS of RX frames.
183 * 0: 1-BSSID mode (BSS index = 0)
184 * 1: 2-BSSID mode (BSS index: Byte5, bit 0)
185 * 2: 2-BSSID mode (BSS index: byte5, bit 1)
186 * 3: 4-BSSID mode (BSS index: byte5, bit 0 - 1)
188 #define MAC_CSR5 0x3014
189 #define MAC_CSR5_BYTE4 FIELD32(0x000000ff)
190 #define MAC_CSR5_BYTE5 FIELD32(0x0000ff00)
191 #define MAC_CSR5_BSS_ID_MASK FIELD32(0x00ff0000)
194 * MAC_CSR6: Maximum frame length register.
196 #define MAC_CSR6 0x3018
197 #define MAC_CSR6_MAX_FRAME_UNIT FIELD32(0x00000fff)
202 #define MAC_CSR7 0x301c
205 * MAC_CSR8: SIFS/EIFS register.
206 * All units are in US.
208 #define MAC_CSR8 0x3020
209 #define MAC_CSR8_SIFS FIELD32(0x000000ff)
210 #define MAC_CSR8_SIFS_AFTER_RX_OFDM FIELD32(0x0000ff00)
211 #define MAC_CSR8_EIFS FIELD32(0xffff0000)
214 * MAC_CSR9: Back-Off control register.
215 * SLOT_TIME: Slot time, default is 20us for 802.11BG.
216 * CWMIN: Bit for Cwmin. default Cwmin is 31 (2^5 - 1).
217 * CWMAX: Bit for Cwmax, default Cwmax is 1023 (2^10 - 1).
218 * CW_SELECT: 1: CWmin/Cwmax select from register, 0:select from TxD.
220 #define MAC_CSR9 0x3024
221 #define MAC_CSR9_SLOT_TIME FIELD32(0x000000ff)
222 #define MAC_CSR9_CWMIN FIELD32(0x00000f00)
223 #define MAC_CSR9_CWMAX FIELD32(0x0000f000)
224 #define MAC_CSR9_CW_SELECT FIELD32(0x00010000)
227 * MAC_CSR10: Power state configuration.
229 #define MAC_CSR10 0x3028
232 * MAC_CSR11: Power saving transition time register.
233 * DELAY_AFTER_TBCN: Delay after Tbcn expired in units of TU.
234 * TBCN_BEFORE_WAKEUP: Number of beacon before wakeup.
235 * WAKEUP_LATENCY: In unit of TU.
237 #define MAC_CSR11 0x302c
238 #define MAC_CSR11_DELAY_AFTER_TBCN FIELD32(0x000000ff)
239 #define MAC_CSR11_TBCN_BEFORE_WAKEUP FIELD32(0x00007f00)
240 #define MAC_CSR11_AUTOWAKE FIELD32(0x00008000)
241 #define MAC_CSR11_WAKEUP_LATENCY FIELD32(0x000f0000)
244 * MAC_CSR12: Manual power control / status register (merge CSR20 & PWRCSR1).
245 * CURRENT_STATE: 0:sleep, 1:awake.
246 * FORCE_WAKEUP: This has higher priority than PUT_TO_SLEEP.
247 * BBP_CURRENT_STATE: 0: BBP sleep, 1: BBP awake.
249 #define MAC_CSR12 0x3030
250 #define MAC_CSR12_CURRENT_STATE FIELD32(0x00000001)
251 #define MAC_CSR12_PUT_TO_SLEEP FIELD32(0x00000002)
252 #define MAC_CSR12_FORCE_WAKEUP FIELD32(0x00000004)
253 #define MAC_CSR12_BBP_CURRENT_STATE FIELD32(0x00000008)
258 #define MAC_CSR13 0x3034
261 * MAC_CSR14: LED control register.
262 * ON_PERIOD: On period, default 70ms.
263 * OFF_PERIOD: Off period, default 30ms.
264 * HW_LED: HW TX activity, 1: normal OFF, 0: normal ON.
265 * SW_LED: s/w LED, 1: ON, 0: OFF.
266 * HW_LED_POLARITY: 0: active low, 1: active high.
268 #define MAC_CSR14 0x3038
269 #define MAC_CSR14_ON_PERIOD FIELD32(0x000000ff)
270 #define MAC_CSR14_OFF_PERIOD FIELD32(0x0000ff00)
271 #define MAC_CSR14_HW_LED FIELD32(0x00010000)
272 #define MAC_CSR14_SW_LED FIELD32(0x00020000)
273 #define MAC_CSR14_HW_LED_POLARITY FIELD32(0x00040000)
274 #define MAC_CSR14_SW_LED2 FIELD32(0x00080000)
277 * MAC_CSR15: NAV control.
279 #define MAC_CSR15 0x303c
282 * TXRX control registers.
283 * Some values are set in TU, whereas 1 TU == 1024 us.
287 * TXRX_CSR0: TX/RX configuration register.
288 * TSF_OFFSET: Default is 24.
289 * AUTO_TX_SEQ: 1: ASIC auto replace sequence nr in outgoing frame.
290 * DISABLE_RX: Disable Rx engine.
291 * DROP_CRC: Drop CRC error.
292 * DROP_PHYSICAL: Drop physical error.
293 * DROP_CONTROL: Drop control frame.
294 * DROP_NOT_TO_ME: Drop not to me unicast frame.
295 * DROP_TO_DS: Drop fram ToDs bit is true.
296 * DROP_VERSION_ERROR: Drop version error frame.
297 * DROP_MULTICAST: Drop multicast frames.
298 * DROP_BORADCAST: Drop broadcast frames.
299 * ROP_ACK_CTS: Drop received ACK and CTS.
301 #define TXRX_CSR0 0x3040
302 #define TXRX_CSR0_RX_ACK_TIMEOUT FIELD32(0x000001ff)
303 #define TXRX_CSR0_TSF_OFFSET FIELD32(0x00007e00)
304 #define TXRX_CSR0_AUTO_TX_SEQ FIELD32(0x00008000)
305 #define TXRX_CSR0_DISABLE_RX FIELD32(0x00010000)
306 #define TXRX_CSR0_DROP_CRC FIELD32(0x00020000)
307 #define TXRX_CSR0_DROP_PHYSICAL FIELD32(0x00040000)
308 #define TXRX_CSR0_DROP_CONTROL FIELD32(0x00080000)
309 #define TXRX_CSR0_DROP_NOT_TO_ME FIELD32(0x00100000)
310 #define TXRX_CSR0_DROP_TO_DS FIELD32(0x00200000)
311 #define TXRX_CSR0_DROP_VERSION_ERROR FIELD32(0x00400000)
312 #define TXRX_CSR0_DROP_MULTICAST FIELD32(0x00800000)
313 #define TXRX_CSR0_DROP_BROADCAST FIELD32(0x01000000)
314 #define TXRX_CSR0_DROP_ACK_CTS FIELD32(0x02000000)
315 #define TXRX_CSR0_TX_WITHOUT_WAITING FIELD32(0x04000000)
320 #define TXRX_CSR1 0x3044
321 #define TXRX_CSR1_BBP_ID0 FIELD32(0x0000007f)
322 #define TXRX_CSR1_BBP_ID0_VALID FIELD32(0x00000080)
323 #define TXRX_CSR1_BBP_ID1 FIELD32(0x00007f00)
324 #define TXRX_CSR1_BBP_ID1_VALID FIELD32(0x00008000)
325 #define TXRX_CSR1_BBP_ID2 FIELD32(0x007f0000)
326 #define TXRX_CSR1_BBP_ID2_VALID FIELD32(0x00800000)
327 #define TXRX_CSR1_BBP_ID3 FIELD32(0x7f000000)
328 #define TXRX_CSR1_BBP_ID3_VALID FIELD32(0x80000000)
333 #define TXRX_CSR2 0x3048
334 #define TXRX_CSR2_BBP_ID0 FIELD32(0x0000007f)
335 #define TXRX_CSR2_BBP_ID0_VALID FIELD32(0x00000080)
336 #define TXRX_CSR2_BBP_ID1 FIELD32(0x00007f00)
337 #define TXRX_CSR2_BBP_ID1_VALID FIELD32(0x00008000)
338 #define TXRX_CSR2_BBP_ID2 FIELD32(0x007f0000)
339 #define TXRX_CSR2_BBP_ID2_VALID FIELD32(0x00800000)
340 #define TXRX_CSR2_BBP_ID3 FIELD32(0x7f000000)
341 #define TXRX_CSR2_BBP_ID3_VALID FIELD32(0x80000000)
346 #define TXRX_CSR3 0x304c
347 #define TXRX_CSR3_BBP_ID0 FIELD32(0x0000007f)
348 #define TXRX_CSR3_BBP_ID0_VALID FIELD32(0x00000080)
349 #define TXRX_CSR3_BBP_ID1 FIELD32(0x00007f00)
350 #define TXRX_CSR3_BBP_ID1_VALID FIELD32(0x00008000)
351 #define TXRX_CSR3_BBP_ID2 FIELD32(0x007f0000)
352 #define TXRX_CSR3_BBP_ID2_VALID FIELD32(0x00800000)
353 #define TXRX_CSR3_BBP_ID3 FIELD32(0x7f000000)
354 #define TXRX_CSR3_BBP_ID3_VALID FIELD32(0x80000000)
357 * TXRX_CSR4: Auto-Responder/Tx-retry register.
358 * AUTORESPOND_PREAMBLE: 0:long, 1:short preamble.
359 * OFDM_TX_RATE_DOWN: 1:enable.
360 * OFDM_TX_RATE_STEP: 0:1-step, 1: 2-step, 2:3-step, 3:4-step.
361 * OFDM_TX_FALLBACK_CCK: 0: Fallback to OFDM 6M only, 1: Fallback to CCK 1M,2M.
363 #define TXRX_CSR4 0x3050
364 #define TXRX_CSR4_TX_ACK_TIMEOUT FIELD32(0x000000ff)
365 #define TXRX_CSR4_CNTL_ACK_POLICY FIELD32(0x00000700)
366 #define TXRX_CSR4_ACK_CTS_PSM FIELD32(0x00010000)
367 #define TXRX_CSR4_AUTORESPOND_ENABLE FIELD32(0x00020000)
368 #define TXRX_CSR4_AUTORESPOND_PREAMBLE FIELD32(0x00040000)
369 #define TXRX_CSR4_OFDM_TX_RATE_DOWN FIELD32(0x00080000)
370 #define TXRX_CSR4_OFDM_TX_RATE_STEP FIELD32(0x00300000)
371 #define TXRX_CSR4_OFDM_TX_FALLBACK_CCK FIELD32(0x00400000)
372 #define TXRX_CSR4_LONG_RETRY_LIMIT FIELD32(0x0f000000)
373 #define TXRX_CSR4_SHORT_RETRY_LIMIT FIELD32(0xf0000000)
378 #define TXRX_CSR5 0x3054
381 * TXRX_CSR6: ACK/CTS payload consumed time
383 #define TXRX_CSR6 0x3058
386 * TXRX_CSR7: OFDM ACK/CTS payload consumed time for 6/9/12/18 mbps.
388 #define TXRX_CSR7 0x305c
389 #define TXRX_CSR7_ACK_CTS_6MBS FIELD32(0x000000ff)
390 #define TXRX_CSR7_ACK_CTS_9MBS FIELD32(0x0000ff00)
391 #define TXRX_CSR7_ACK_CTS_12MBS FIELD32(0x00ff0000)
392 #define TXRX_CSR7_ACK_CTS_18MBS FIELD32(0xff000000)
395 * TXRX_CSR8: OFDM ACK/CTS payload consumed time for 24/36/48/54 mbps.
397 #define TXRX_CSR8 0x3060
398 #define TXRX_CSR8_ACK_CTS_24MBS FIELD32(0x000000ff)
399 #define TXRX_CSR8_ACK_CTS_36MBS FIELD32(0x0000ff00)
400 #define TXRX_CSR8_ACK_CTS_48MBS FIELD32(0x00ff0000)
401 #define TXRX_CSR8_ACK_CTS_54MBS FIELD32(0xff000000)
404 * TXRX_CSR9: Synchronization control register.
405 * BEACON_INTERVAL: In unit of 1/16 TU.
406 * TSF_TICKING: Enable TSF auto counting.
407 * TSF_SYNC: Tsf sync, 0: disable, 1: infra, 2: ad-hoc/master mode.
408 * BEACON_GEN: Enable beacon generator.
410 #define TXRX_CSR9 0x3064
411 #define TXRX_CSR9_BEACON_INTERVAL FIELD32(0x0000ffff)
412 #define TXRX_CSR9_TSF_TICKING FIELD32(0x00010000)
413 #define TXRX_CSR9_TSF_SYNC FIELD32(0x00060000)
414 #define TXRX_CSR9_TBTT_ENABLE FIELD32(0x00080000)
415 #define TXRX_CSR9_BEACON_GEN FIELD32(0x00100000)
416 #define TXRX_CSR9_TIMESTAMP_COMPENSATE FIELD32(0xff000000)
419 * TXRX_CSR10: BEACON alignment.
421 #define TXRX_CSR10 0x3068
424 * TXRX_CSR11: AES mask.
426 #define TXRX_CSR11 0x306c
429 * TXRX_CSR12: TSF low 32.
431 #define TXRX_CSR12 0x3070
432 #define TXRX_CSR12_LOW_TSFTIMER FIELD32(0xffffffff)
435 * TXRX_CSR13: TSF high 32.
437 #define TXRX_CSR13 0x3074
438 #define TXRX_CSR13_HIGH_TSFTIMER FIELD32(0xffffffff)
441 * TXRX_CSR14: TBTT timer.
443 #define TXRX_CSR14 0x3078
446 * TXRX_CSR15: TKIP MIC priority byte "AND" mask.
448 #define TXRX_CSR15 0x307c
451 * PHY control registers.
452 * Some values are set in TU, whereas 1 TU == 1024 us.
456 * PHY_CSR0: RF/PS control.
458 #define PHY_CSR0 0x3080
459 #define PHY_CSR0_PA_PE_BG FIELD32(0x00010000)
460 #define PHY_CSR0_PA_PE_A FIELD32(0x00020000)
465 #define PHY_CSR1 0x3084
466 #define PHY_CSR1_RF_RPI FIELD32(0x00010000)
469 * PHY_CSR2: Pre-TX BBP control.
471 #define PHY_CSR2 0x3088
474 * PHY_CSR3: BBP serial control register.
475 * VALUE: Register value to program into BBP.
476 * REG_NUM: Selected BBP register.
477 * READ_CONTROL: 0: Write BBP, 1: Read BBP.
478 * BUSY: 1: ASIC is busy execute BBP programming.
480 #define PHY_CSR3 0x308c
481 #define PHY_CSR3_VALUE FIELD32(0x000000ff)
482 #define PHY_CSR3_REGNUM FIELD32(0x00007f00)
483 #define PHY_CSR3_READ_CONTROL FIELD32(0x00008000)
484 #define PHY_CSR3_BUSY FIELD32(0x00010000)
487 * PHY_CSR4: RF serial control register
488 * VALUE: Register value (include register id) serial out to RF/IF chip.
489 * NUMBER_OF_BITS: Number of bits used in RFRegValue (I:20, RFMD:22).
490 * IF_SELECT: 1: select IF to program, 0: select RF to program.
491 * PLL_LD: RF PLL_LD status.
492 * BUSY: 1: ASIC is busy execute RF programming.
494 #define PHY_CSR4 0x3090
495 #define PHY_CSR4_VALUE FIELD32(0x00ffffff)
496 #define PHY_CSR4_NUMBER_OF_BITS FIELD32(0x1f000000)
497 #define PHY_CSR4_IF_SELECT FIELD32(0x20000000)
498 #define PHY_CSR4_PLL_LD FIELD32(0x40000000)
499 #define PHY_CSR4_BUSY FIELD32(0x80000000)
502 * PHY_CSR5: RX to TX signal switch timing control.
504 #define PHY_CSR5 0x3094
505 #define PHY_CSR5_IQ_FLIP FIELD32(0x00000004)
508 * PHY_CSR6: TX to RX signal timing control.
510 #define PHY_CSR6 0x3098
511 #define PHY_CSR6_IQ_FLIP FIELD32(0x00000004)
514 * PHY_CSR7: TX DAC switching timing control.
516 #define PHY_CSR7 0x309c
519 * Security control register.
523 * SEC_CSR0: Shared key table control.
525 #define SEC_CSR0 0x30a0
526 #define SEC_CSR0_BSS0_KEY0_VALID FIELD32(0x00000001)
527 #define SEC_CSR0_BSS0_KEY1_VALID FIELD32(0x00000002)
528 #define SEC_CSR0_BSS0_KEY2_VALID FIELD32(0x00000004)
529 #define SEC_CSR0_BSS0_KEY3_VALID FIELD32(0x00000008)
530 #define SEC_CSR0_BSS1_KEY0_VALID FIELD32(0x00000010)
531 #define SEC_CSR0_BSS1_KEY1_VALID FIELD32(0x00000020)
532 #define SEC_CSR0_BSS1_KEY2_VALID FIELD32(0x00000040)
533 #define SEC_CSR0_BSS1_KEY3_VALID FIELD32(0x00000080)
534 #define SEC_CSR0_BSS2_KEY0_VALID FIELD32(0x00000100)
535 #define SEC_CSR0_BSS2_KEY1_VALID FIELD32(0x00000200)
536 #define SEC_CSR0_BSS2_KEY2_VALID FIELD32(0x00000400)
537 #define SEC_CSR0_BSS2_KEY3_VALID FIELD32(0x00000800)
538 #define SEC_CSR0_BSS3_KEY0_VALID FIELD32(0x00001000)
539 #define SEC_CSR0_BSS3_KEY1_VALID FIELD32(0x00002000)
540 #define SEC_CSR0_BSS3_KEY2_VALID FIELD32(0x00004000)
541 #define SEC_CSR0_BSS3_KEY3_VALID FIELD32(0x00008000)
544 * SEC_CSR1: Shared key table security mode register.
546 #define SEC_CSR1 0x30a4
547 #define SEC_CSR1_BSS0_KEY0_CIPHER_ALG FIELD32(0x00000007)
548 #define SEC_CSR1_BSS0_KEY1_CIPHER_ALG FIELD32(0x00000070)
549 #define SEC_CSR1_BSS0_KEY2_CIPHER_ALG FIELD32(0x00000700)
550 #define SEC_CSR1_BSS0_KEY3_CIPHER_ALG FIELD32(0x00007000)
551 #define SEC_CSR1_BSS1_KEY0_CIPHER_ALG FIELD32(0x00070000)
552 #define SEC_CSR1_BSS1_KEY1_CIPHER_ALG FIELD32(0x00700000)
553 #define SEC_CSR1_BSS1_KEY2_CIPHER_ALG FIELD32(0x07000000)
554 #define SEC_CSR1_BSS1_KEY3_CIPHER_ALG FIELD32(0x70000000)
557 * Pairwise key table valid bitmap registers.
558 * SEC_CSR2: pairwise key table valid bitmap 0.
559 * SEC_CSR3: pairwise key table valid bitmap 1.
561 #define SEC_CSR2 0x30a8
562 #define SEC_CSR3 0x30ac
565 * SEC_CSR4: Pairwise key table lookup control.
567 #define SEC_CSR4 0x30b0
570 * SEC_CSR5: shared key table security mode register.
572 #define SEC_CSR5 0x30b4
573 #define SEC_CSR5_BSS2_KEY0_CIPHER_ALG FIELD32(0x00000007)
574 #define SEC_CSR5_BSS2_KEY1_CIPHER_ALG FIELD32(0x00000070)
575 #define SEC_CSR5_BSS2_KEY2_CIPHER_ALG FIELD32(0x00000700)
576 #define SEC_CSR5_BSS2_KEY3_CIPHER_ALG FIELD32(0x00007000)
577 #define SEC_CSR5_BSS3_KEY0_CIPHER_ALG FIELD32(0x00070000)
578 #define SEC_CSR5_BSS3_KEY1_CIPHER_ALG FIELD32(0x00700000)
579 #define SEC_CSR5_BSS3_KEY2_CIPHER_ALG FIELD32(0x07000000)
580 #define SEC_CSR5_BSS3_KEY3_CIPHER_ALG FIELD32(0x70000000)
583 * STA control registers.
587 * STA_CSR0: RX PLCP error count & RX FCS error count.
589 #define STA_CSR0 0x30c0
590 #define STA_CSR0_FCS_ERROR FIELD32(0x0000ffff)
591 #define STA_CSR0_PLCP_ERROR FIELD32(0xffff0000)
594 * STA_CSR1: RX False CCA count & RX LONG frame count.
596 #define STA_CSR1 0x30c4
597 #define STA_CSR1_PHYSICAL_ERROR FIELD32(0x0000ffff)
598 #define STA_CSR1_FALSE_CCA_ERROR FIELD32(0xffff0000)
601 * STA_CSR2: TX Beacon count and RX FIFO overflow count.
603 #define STA_CSR2 0x30c8
604 #define STA_CSR2_RX_FIFO_OVERFLOW_COUNT FIELD32(0x0000ffff)
605 #define STA_CSR2_RX_OVERFLOW_COUNT FIELD32(0xffff0000)
608 * STA_CSR3: TX Beacon count.
610 #define STA_CSR3 0x30cc
611 #define STA_CSR3_TX_BEACON_COUNT FIELD32(0x0000ffff)
614 * STA_CSR4: TX Retry count.
616 #define STA_CSR4 0x30d0
617 #define STA_CSR4_TX_NO_RETRY_COUNT FIELD32(0x0000ffff)
618 #define STA_CSR4_TX_ONE_RETRY_COUNT FIELD32(0xffff0000)
621 * STA_CSR5: TX Retry count.
623 #define STA_CSR5 0x30d4
624 #define STA_CSR4_TX_MULTI_RETRY_COUNT FIELD32(0x0000ffff)
625 #define STA_CSR4_TX_RETRY_FAIL_COUNT FIELD32(0xffff0000)
628 * QOS control registers.
632 * QOS_CSR1: TXOP holder MAC address register.
634 #define QOS_CSR1 0x30e4
635 #define QOS_CSR1_BYTE4 FIELD32(0x000000ff)
636 #define QOS_CSR1_BYTE5 FIELD32(0x0000ff00)
639 * QOS_CSR2: TXOP holder timeout register.
641 #define QOS_CSR2 0x30e8
644 * RX QOS-CFPOLL MAC address register.
645 * QOS_CSR3: RX QOS-CFPOLL MAC address 0.
646 * QOS_CSR4: RX QOS-CFPOLL MAC address 1.
648 #define QOS_CSR3 0x30ec
649 #define QOS_CSR4 0x30f0
652 * QOS_CSR5: "QosControl" field of the RX QOS-CFPOLL.
654 #define QOS_CSR5 0x30f4
657 * WMM Scheduler Register
661 * AIFSN_CSR: AIFSN for each EDCA AC.
667 #define AIFSN_CSR 0x0400
668 #define AIFSN_CSR_AIFSN0 FIELD32(0x0000000f)
669 #define AIFSN_CSR_AIFSN1 FIELD32(0x000000f0)
670 #define AIFSN_CSR_AIFSN2 FIELD32(0x00000f00)
671 #define AIFSN_CSR_AIFSN3 FIELD32(0x0000f000)
674 * CWMIN_CSR: CWmin for each EDCA AC.
680 #define CWMIN_CSR 0x0404
681 #define CWMIN_CSR_CWMIN0 FIELD32(0x0000000f)
682 #define CWMIN_CSR_CWMIN1 FIELD32(0x000000f0)
683 #define CWMIN_CSR_CWMIN2 FIELD32(0x00000f00)
684 #define CWMIN_CSR_CWMIN3 FIELD32(0x0000f000)
687 * CWMAX_CSR: CWmax for each EDCA AC.
693 #define CWMAX_CSR 0x0408
694 #define CWMAX_CSR_CWMAX0 FIELD32(0x0000000f)
695 #define CWMAX_CSR_CWMAX1 FIELD32(0x000000f0)
696 #define CWMAX_CSR_CWMAX2 FIELD32(0x00000f00)
697 #define CWMAX_CSR_CWMAX3 FIELD32(0x0000f000)
700 * AC_TXOP_CSR0: AC_BK/AC_BE TXOP register.
701 * AC0_TX_OP: For AC_BK, in unit of 32us.
702 * AC1_TX_OP: For AC_BE, in unit of 32us.
704 #define AC_TXOP_CSR0 0x040c
705 #define AC_TXOP_CSR0_AC0_TX_OP FIELD32(0x0000ffff)
706 #define AC_TXOP_CSR0_AC1_TX_OP FIELD32(0xffff0000)
709 * AC_TXOP_CSR1: AC_VO/AC_VI TXOP register.
710 * AC2_TX_OP: For AC_VI, in unit of 32us.
711 * AC3_TX_OP: For AC_VO, in unit of 32us.
713 #define AC_TXOP_CSR1 0x0410
714 #define AC_TXOP_CSR1_AC2_TX_OP FIELD32(0x0000ffff)
715 #define AC_TXOP_CSR1_AC3_TX_OP FIELD32(0xffff0000)
719 * The wordsize of the BBP is 8 bits.
725 #define BBP_R2_BG_MODE FIELD8(0x20)
730 #define BBP_R3_SMART_MODE FIELD8(0x01)
733 * R4: RX antenna control
734 * FRAME_END: 1 - DPDT, 0 - SPDT (Only valid for 802.11G, RF2527 & RF2529)
738 * ANTENNA_CONTROL semantics (guessed):
739 * 0x1: Software controlled antenna switching (fixed or SW diversity)
740 * 0x2: Hardware diversity.
742 #define BBP_R4_RX_ANTENNA_CONTROL FIELD8(0x03)
743 #define BBP_R4_RX_FRAME_END FIELD8(0x20)
748 #define BBP_R77_RX_ANTENNA FIELD8(0x03)
757 #define RF3_TXPOWER FIELD32(0x00003e00)
762 #define RF4_FREQ_OFFSET FIELD32(0x0003f000)
766 * The wordsize of the EEPROM is 16 bits.
772 #define EEPROM_MAC_ADDR_0 0x0002
773 #define EEPROM_MAC_ADDR_BYTE0 FIELD16(0x00ff)
774 #define EEPROM_MAC_ADDR_BYTE1 FIELD16(0xff00)
775 #define EEPROM_MAC_ADDR1 0x0003
776 #define EEPROM_MAC_ADDR_BYTE2 FIELD16(0x00ff)
777 #define EEPROM_MAC_ADDR_BYTE3 FIELD16(0xff00)
778 #define EEPROM_MAC_ADDR_2 0x0004
779 #define EEPROM_MAC_ADDR_BYTE4 FIELD16(0x00ff)
780 #define EEPROM_MAC_ADDR_BYTE5 FIELD16(0xff00)
784 * ANTENNA_NUM: Number of antenna's.
785 * TX_DEFAULT: Default antenna 0: diversity, 1: A, 2: B.
786 * RX_DEFAULT: Default antenna 0: diversity, 1: A, 2: B.
787 * FRAME_TYPE: 0: DPDT , 1: SPDT , noted this bit is valid for g only.
788 * DYN_TXAGC: Dynamic TX AGC control.
789 * HARDWARE_RADIO: 1: Hardware controlled radio. Read GPIO0.
790 * RF_TYPE: Rf_type of this adapter.
792 #define EEPROM_ANTENNA 0x0010
793 #define EEPROM_ANTENNA_NUM FIELD16(0x0003)
794 #define EEPROM_ANTENNA_TX_DEFAULT FIELD16(0x000c)
795 #define EEPROM_ANTENNA_RX_DEFAULT FIELD16(0x0030)
796 #define EEPROM_ANTENNA_FRAME_TYPE FIELD16(0x0040)
797 #define EEPROM_ANTENNA_DYN_TXAGC FIELD16(0x0200)
798 #define EEPROM_ANTENNA_HARDWARE_RADIO FIELD16(0x0400)
799 #define EEPROM_ANTENNA_RF_TYPE FIELD16(0xf800)
803 * EXTERNAL_LNA: External LNA.
805 #define EEPROM_NIC 0x0011
806 #define EEPROM_NIC_EXTERNAL_LNA FIELD16(0x0010)
810 * GEO_A: Default geographical setting for 5GHz band
811 * GEO: Default geographical setting.
813 #define EEPROM_GEOGRAPHY 0x0012
814 #define EEPROM_GEOGRAPHY_GEO_A FIELD16(0x00ff)
815 #define EEPROM_GEOGRAPHY_GEO FIELD16(0xff00)
820 #define EEPROM_BBP_START 0x0013
821 #define EEPROM_BBP_SIZE 16
822 #define EEPROM_BBP_VALUE FIELD16(0x00ff)
823 #define EEPROM_BBP_REG_ID FIELD16(0xff00)
826 * EEPROM TXPOWER 802.11G
828 #define EEPROM_TXPOWER_G_START 0x0023
829 #define EEPROM_TXPOWER_G_SIZE 7
830 #define EEPROM_TXPOWER_G_1 FIELD16(0x00ff)
831 #define EEPROM_TXPOWER_G_2 FIELD16(0xff00)
836 #define EEPROM_FREQ 0x002f
837 #define EEPROM_FREQ_OFFSET FIELD16(0x00ff)
838 #define EEPROM_FREQ_SEQ_MASK FIELD16(0xff00)
839 #define EEPROM_FREQ_SEQ FIELD16(0x0300)
843 * POLARITY_RDY_G: Polarity RDY_G setting.
844 * POLARITY_RDY_A: Polarity RDY_A setting.
845 * POLARITY_ACT: Polarity ACT setting.
846 * POLARITY_GPIO_0: Polarity GPIO0 setting.
847 * POLARITY_GPIO_1: Polarity GPIO1 setting.
848 * POLARITY_GPIO_2: Polarity GPIO2 setting.
849 * POLARITY_GPIO_3: Polarity GPIO3 setting.
850 * POLARITY_GPIO_4: Polarity GPIO4 setting.
851 * LED_MODE: Led mode.
853 #define EEPROM_LED 0x0030
854 #define EEPROM_LED_POLARITY_RDY_G FIELD16(0x0001)
855 #define EEPROM_LED_POLARITY_RDY_A FIELD16(0x0002)
856 #define EEPROM_LED_POLARITY_ACT FIELD16(0x0004)
857 #define EEPROM_LED_POLARITY_GPIO_0 FIELD16(0x0008)
858 #define EEPROM_LED_POLARITY_GPIO_1 FIELD16(0x0010)
859 #define EEPROM_LED_POLARITY_GPIO_2 FIELD16(0x0020)
860 #define EEPROM_LED_POLARITY_GPIO_3 FIELD16(0x0040)
861 #define EEPROM_LED_POLARITY_GPIO_4 FIELD16(0x0080)
862 #define EEPROM_LED_LED_MODE FIELD16(0x1f00)
865 * EEPROM TXPOWER 802.11A
867 #define EEPROM_TXPOWER_A_START 0x0031
868 #define EEPROM_TXPOWER_A_SIZE 12
869 #define EEPROM_TXPOWER_A_1 FIELD16(0x00ff)
870 #define EEPROM_TXPOWER_A_2 FIELD16(0xff00)
873 * EEPROM RSSI offset 802.11BG
875 #define EEPROM_RSSI_OFFSET_BG 0x004d
876 #define EEPROM_RSSI_OFFSET_BG_1 FIELD16(0x00ff)
877 #define EEPROM_RSSI_OFFSET_BG_2 FIELD16(0xff00)
880 * EEPROM RSSI offset 802.11A
882 #define EEPROM_RSSI_OFFSET_A 0x004e
883 #define EEPROM_RSSI_OFFSET_A_1 FIELD16(0x00ff)
884 #define EEPROM_RSSI_OFFSET_A_2 FIELD16(0xff00)
887 * DMA descriptor defines.
889 #define TXD_DESC_SIZE ( 6 * sizeof(__le32) )
890 #define TXINFO_SIZE ( 6 * sizeof(__le32) )
891 #define RXD_DESC_SIZE ( 6 * sizeof(__le32) )
894 * TX descriptor format for TX, PRIO and Beacon Ring.
899 * BURST: Next frame belongs to same "burst" event.
900 * TKIP_MIC: ASIC appends TKIP MIC if TKIP is used.
901 * KEY_TABLE: Use per-client pairwise KEY table.
903 * Key index (0~31) to the pairwise KEY table.
904 * 0~3 to shared KEY table 0 (BSS0).
905 * 4~7 to shared KEY table 1 (BSS1).
906 * 8~11 to shared KEY table 2 (BSS2).
907 * 12~15 to shared KEY table 3 (BSS3).
908 * BURST2: For backward compatibility, set to same value as BURST.
910 #define TXD_W0_BURST FIELD32(0x00000001)
911 #define TXD_W0_VALID FIELD32(0x00000002)
912 #define TXD_W0_MORE_FRAG FIELD32(0x00000004)
913 #define TXD_W0_ACK FIELD32(0x00000008)
914 #define TXD_W0_TIMESTAMP FIELD32(0x00000010)
915 #define TXD_W0_OFDM FIELD32(0x00000020)
916 #define TXD_W0_IFS FIELD32(0x00000040)
917 #define TXD_W0_RETRY_MODE FIELD32(0x00000080)
918 #define TXD_W0_TKIP_MIC FIELD32(0x00000100)
919 #define TXD_W0_KEY_TABLE FIELD32(0x00000200)
920 #define TXD_W0_KEY_INDEX FIELD32(0x0000fc00)
921 #define TXD_W0_DATABYTE_COUNT FIELD32(0x0fff0000)
922 #define TXD_W0_BURST2 FIELD32(0x10000000)
923 #define TXD_W0_CIPHER_ALG FIELD32(0xe0000000)
927 * HOST_Q_ID: EDCA/HCCA queue ID.
928 * HW_SEQUENCE: MAC overwrites the frame sequence number.
929 * BUFFER_COUNT: Number of buffers in this TXD.
931 #define TXD_W1_HOST_Q_ID FIELD32(0x0000000f)
932 #define TXD_W1_AIFSN FIELD32(0x000000f0)
933 #define TXD_W1_CWMIN FIELD32(0x00000f00)
934 #define TXD_W1_CWMAX FIELD32(0x0000f000)
935 #define TXD_W1_IV_OFFSET FIELD32(0x003f0000)
936 #define TXD_W1_HW_SEQUENCE FIELD32(0x10000000)
937 #define TXD_W1_BUFFER_COUNT FIELD32(0xe0000000)
940 * Word2: PLCP information
942 #define TXD_W2_PLCP_SIGNAL FIELD32(0x000000ff)
943 #define TXD_W2_PLCP_SERVICE FIELD32(0x0000ff00)
944 #define TXD_W2_PLCP_LENGTH_LOW FIELD32(0x00ff0000)
945 #define TXD_W2_PLCP_LENGTH_HIGH FIELD32(0xff000000)
950 #define TXD_W3_IV FIELD32(0xffffffff)
955 #define TXD_W4_EIV FIELD32(0xffffffff)
959 * FRAME_OFFSET: Frame start offset inside ASIC TXFIFO (after TXINFO field).
960 * PACKET_ID: Driver assigned packet ID to categorize TXResult in interrupt.
961 * WAITING_DMA_DONE_INT: TXD been filled with data
962 * and waiting for TxDoneISR housekeeping.
964 #define TXD_W5_FRAME_OFFSET FIELD32(0x000000ff)
965 #define TXD_W5_PACKET_ID FIELD32(0x0000ff00)
966 #define TXD_W5_TX_POWER FIELD32(0x00ff0000)
967 #define TXD_W5_WAITING_DMA_DONE_INT FIELD32(0x01000000)
970 * RX descriptor format for RX Ring.
975 * CIPHER_ERROR: 1:ICV error, 2:MIC error, 3:invalid key.
976 * KEY_INDEX: Decryption key actually used.
978 #define RXD_W0_OWNER_NIC FIELD32(0x00000001)
979 #define RXD_W0_DROP FIELD32(0x00000002)
980 #define RXD_W0_UNICAST_TO_ME FIELD32(0x00000004)
981 #define RXD_W0_MULTICAST FIELD32(0x00000008)
982 #define RXD_W0_BROADCAST FIELD32(0x00000010)
983 #define RXD_W0_MY_BSS FIELD32(0x00000020)
984 #define RXD_W0_CRC_ERROR FIELD32(0x00000040)
985 #define RXD_W0_OFDM FIELD32(0x00000080)
986 #define RXD_W0_CIPHER_ERROR FIELD32(0x00000300)
987 #define RXD_W0_KEY_INDEX FIELD32(0x0000fc00)
988 #define RXD_W0_DATABYTE_COUNT FIELD32(0x0fff0000)
989 #define RXD_W0_CIPHER_ALG FIELD32(0xe0000000)
993 * SIGNAL: RX raw data rate reported by BBP.
994 * RSSI: RSSI reported by BBP.
996 #define RXD_W1_SIGNAL FIELD32(0x000000ff)
997 #define RXD_W1_RSSI_AGC FIELD32(0x00001f00)
998 #define RXD_W1_RSSI_LNA FIELD32(0x00006000)
999 #define RXD_W1_FRAME_OFFSET FIELD32(0x7f000000)
1003 * IV: Received IV of originally encrypted.
1005 #define RXD_W2_IV FIELD32(0xffffffff)
1009 * EIV: Received EIV of originally encrypted.
1011 #define RXD_W3_EIV FIELD32(0xffffffff)
1016 #define RXD_W4_RESERVED FIELD32(0xffffffff)
1019 * the above 20-byte is called RXINFO and will be DMAed to MAC RX block
1020 * and passed to the HOST driver.
1021 * The following fields are for DMA block and HOST usage only.
1022 * Can't be touched by ASIC MAC block.
1028 #define RXD_W5_RESERVED FIELD32(0xffffffff)
1031 * Macro's for converting txpower from EEPROM to mac80211 value
1032 * and from mac80211 value to register value.
1034 #define MIN_TXPOWER 0
1035 #define MAX_TXPOWER 31
1036 #define DEFAULT_TXPOWER 24
1038 #define TXPOWER_FROM_DEV(__txpower) \
1040 ((__txpower) > MAX_TXPOWER) ? \
1041 DEFAULT_TXPOWER : (__txpower); \
1044 #define TXPOWER_TO_DEV(__txpower) \
1046 ((__txpower) <= MIN_TXPOWER) ? MIN_TXPOWER : \
1047 (((__txpower) >= MAX_TXPOWER) ? MAX_TXPOWER : \
1051 #endif /* RT73USB_H */